PGA2500IDBR [TI]
增益范围：0dB 和 10dB 至 65dB（1dB 阶跃） | DB | 28 | -40 to 85;
| 型号： | PGA2500IDBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增益范围：0dB 和 10dB 至 65dB（1dB 阶跃） | DB | 28 | -40 to 85 放大器 光电二极管 商用集成电路 |
| 文件： | 总23页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PGA2500
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
Digitally Controlled
Microphone Preamplifier
FEATURES
APPLICATIONS
D
Fully Differential Input-to-Output Architecture
Digitally Controlled Gain Using Serial Port
Interface:
− Gain Range: 10dB through 65dB, 1dB per
step
− Unity (0dB) Gain Setting via Serial Port or
Dedicated Control Pin
D
Microphone Preamplifiers and Mixers
D
D
Digital Mixers and Recorders
DESCRIPTION
The PGA2500 is a digitally controlled, analog microphone
preamplifier designed for use as a front end for high-
performance audio analog-to-digital converters (ADCs). The
PGA2500 features include low noise, wide dynamic range,
and a differential signal path. An on-chip DC servo loop is
employed to minimize DC offset, while a common-mode
servo function may be used to enhance common-mode
rejection.
D
Dynamic Performance:
− Equivalent Input Noise with Z = 150Ω and
S
Gain = 30dB: −128dBu
− Total Harmonic Distortion plus Noise
(THD+N) with Gain = 30dB: 0.0004%
Zero Crossing Detection Minimizes Audible
Artifacts when Gain Switching
Integrated DC Servo Minimizes Output Offset
Voltage
D
D
The PGA2500 features a gain range of 10dB through 65dB
(1dB/step), along with a unity gain setting. The wide gain
range allows the PGA2500 to be used with a variety of
microphones. Gain settings and internal functions are
programmed using a 16-bit control word, which is loaded
using a simple serial port interface. A serial data output pin
provides support for daisy-chained connection of multiple
PGA2500 devices. Four programmable digital outputs are
provided for controlling the external switching of input pads,
phantom power, high pass filters, and polarity reversal
functions. The PGA2500 requires both +5V and −5V power
supplies and is available in a small SSOP-28 package.
D
Common-Mode Servo Improves CMRR
D
Four-Wire Serial Control Port Interface:
− Simple Interface to Microprocessor or
DSP Serial Ports
− Supports Daisy-Chaining of Multiple
PGA2500 Devices
Dedicated Input Pin for Selecting Unity Gain
Overload Output Pin Provides Clipping
Indication
D
D
D
D
D
Four General-Purpose Digital Output Pins
Requires 5V Power Supplies
Available in an SSOP-28 Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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Copyright 2003, Texas Instruments Incorporated
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted
(1)
proper handling and installation procedures can cause damage.
PGA2500
+5.5
UNIT
Supply Voltage, VA+
V
V
V
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Supply Voltage, VA−
−5.5
Supply Voltage, VD−
−5.5
Voltage Difference, VA− to VD−
Analog input voltage
Less than 300
(VA−) −0.3 to (VA+) +0.3
−0.3 to (VA+) + 0.3
−40 to +85
mV
V
Digital input voltage
V
Operating Temperature Range
Storage Temperature Range
°C
°C
−60 to +150
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
(1)
PGA2500IDB
Rails, 48
PGA2500
SSOP-28
DB
−40°C to +85°C
PGA2500I
PGA2500IDBR
Tape and Reel, 1000
(1)
For the most current specifications and package information, refer to our web site at www.ti.com.
2
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS
All parameters specified with TA = +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and VCOMIN = 0V, unless otherwise noted.
PGA2500
PARAMETER
DC Characteristics
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Step Size
Gain = 10dB through 65dB
All Gain Settings
1
dB
dB
Gain Error
0.5
AC Characteristics
Gain = 0dB, VOUT = 3.5VRMS, VCOMIN = 0V
Gain = 30dB, VOUT = 3.5VRMS, VCOMIN = 0V
−114
−108
−108
−102
dB
dB
THD+N with fIN = 1kHz
Analog Input
Maximum Input Voltage
Gain = 0dB
VA− +1.5
VA+ −2.0
V
Input Resistance
Per Input Pin
Differential
4600
9200
Ω
Ω
Analog Output
Output Voltage Range
Output Offset Voltage
Input Referred Offset
Output Resistive Loading
VCOMIN = 0V, RL = 600Ω
DC Servo On, Any Gain
DC Servo Off, Gain = 30dB
VA− +0.9
600
VA+ −0.9
1
V
0.04
1
mV
mV
Ω
Load Capacitance Stability
Short Circuit Current
100
100
pF
10-second duration
mA
Digital Characteristics
High-Level Input Voltage, VIH
Low-Level Input Voltage, VIL
High-Level Output Voltage, VOH
Low-Level Output Voltage, VOL
Input Leakage Current, IIN
+2.0
−0.3
VA+
0.8
V
V
IO = 200µA
IO = −3.2mA
(VA+) − 1.0
V
0.4
10
V
2
µA
Switching Characteristics
Serial Clock (SCLK) Frequency
Serial Clock (SCLK) Pulse Width Low
Serial Clock (SCLK) Pulse Width High
Input Timing
fSCLK
tPH
0
6.25
MHz
ns
80
80
tPL
ns
SDI Setup Time
tSDS
tSDH
tCSCR
tCFCS
20
20
90
35
ns
ns
ns
ns
SDI Hold Time
CS Falling to SCLK Rising
SCLK Falling to CS Rising
Output Timing
CS Low to SDO Active
tCSO
tCFDO
tCSZ
35
60
ns
ns
ns
SCLK Falling to SDO Data Valid
CS High to SDO High Impedance
Power Supply
100
Operating Voltage
VA+
VA−
VD−
+4.75
−4.75
−4.75
+5
−5
−5
+5.25
−5.25
−5.25
V
V
V
Quiescent Current
IA+
IA−
ID−
VA+ = +5V
VA− = −5V
VD− = −5V
30
30
1
40
40
2
mA
mA
mA
3
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
PIN CONFIGURATION
GPO1
GPO2
GPO3
GPO4
OVR
1
2
3
4
5
6
7
8
9
28 AGND
27 VIN
26 VIN
+
−
25 VCOMIN
24 CS11
23 CS12
22 CS21
21 CS22
DGND
DCEN
0dB
PGA2500
−
20 VA
ZCEN
SDI 10
CS 11
19 VA+
18 VA+
17 VOUT
16 VOUT
SCLK 12
SDO 13
+
−
−
−
15 VA
VD
14
PIN DESCRIPTIONS
PIN NUMBER
NAME
GPO1
GPO2
GPO3
GPO4
OVR
DESCRIPTION
1
General-Purpose CMOS Logic Output
General-Purpose CMOS Logic Output
General-Purpose CMOS Logic Output
General-Purpose CMOS Logic Output
Over Range Output (Active High)
Digital Ground
2
3
4
5
6
DGND
DCEN
0dB
7
DC Servo Enable (Active Low)
Unity Gain Enable (Active High)
Zero Crossing Detector Enable (Active High)
Serial Data Input
8
9
ZCEN
SDI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CS
Chip Select Input (Active Low)
Serial Data Clock Input
SCLK
SDO
Serial Data Output
VD−
−5V Digital Supply
VA−
−5V Analog Supply
VOUT
−
+
Analog Output, Inverting
VOUT
Analog Output, Non-Inverting
+5V Analog Supply
VA+
VA+
+5V Analog Supply
VA−
−5V Analog Supply
CS22
DC Servo Capacitor #2, Terminal 2
DC Servo Capacitor #2, Terminal 1
DC Servo Capacitor #1, Terminal 2
DC Servo Capacitor #1, Terminal 1
Common Mode Voltage Input, 0V to +2.5V
Analog Input, Inverting
CS21
CS12
CS11
VCOMIN
VIN−
VIN+
Analog Input, Noninverting
Analog Ground
AGND
4
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
All specifications at TA = +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and VCOMIN = 0V, unless otherwise noted.
EQUIVALENT INPUT NOISE (E.I.N.) AS A FUNCTION OF GAIN
EQUIVALENT INPUT NOISE (E.I.N.) AS A FUNCTION OF GAIN
Ω
Ω
(with Z = 0 )
(with Z = 150 )
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
THD+N vs GAIN
THD+N AND NOISE vs GAIN
Ω
(with 4.0 VRMS Output and Z = 40 )
(0dB = 4VRMS)
−
0.01
80
85
90
95
−
THD+N
with Z = 40
−
−
Ω
−
−
−
−
−
−
−
100
105
110
115
120
125
130
Noise
with Z = 0
0.001
Ω
0.0001
10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
10 15 20 25 30 35 40 45 50 55 60 65
Gain Set (dB)
THD+N vs FREQUENCY
THD+N vs FREQUENCY
Ω
Ω
Ω
Ω
(RS = 40 , RL = 600 , VCOMIN = 0V, BW = 22Hz to 22kHz)
(RS = 40 , RL = 600 , VCOMIN = +2.5V, BW = 22Hz to 22kHz)
0.1
0.01
0.1
VOUT = 2.0Vrms Differential
for Gains = 10, 20, 30, 40, 50, and 60dB
VOUT = 1.0Vrms Differential for Gain = 0dB
60dB
0.01
0.001
60dB
50dB
50dB
40dB
40dB
10dB
0.001
0.0001
30dB
10dB
0dB
30dB
20dB
0dB
20dB
0.0001
20
100
1k
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
Frequency (Hz)
5
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and VCOMIN = 0V, unless otherwise noted.
THD+N vs FREQUENCY
BANDWIDTH vs GAIN
Ω
Ω
(RS = 40 , RL = 600 , VCOMIN = +2.5V, BW = 22Hz to 22kHz)
7
6
5
4
3
2
1
0
0.1
0.01
VOUT = 1.0Vrms Differential for All Gain Settings
60dB
50dB
40dB
30dB
0.001
0.0001
10dB
0dB
20dB
10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
20
100
1k
10k 20k
Frequency (Hz)
THD+N vs OUTPUT AMPLITUDE
0.1
0.01
Gain = 30dB
f = 1kHz
VCOMIN = 0V
0.001
Ω
RS = 40
Ω
RL = 600
0.0003
0.3
0.30
3.00
6.00
Output Amplitude (Vrms)
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
The four-wire serial port interface is used to program the
PGA2500 gain and support functions. A 16-bit control
word is utilized to program these functions (see Figure 2,
page 9). A serial data output pin provides support for
daisy-chaining multiple PGA2500 devices on a single
serial interface bus (see Figure 4, page 10).
OVERVIEW
The PGA2500 is a digitally controlled microphone
preamplifier integrated circuit designed for amplifying the
output of dynamic and condenser microphones and
driving high performance audio analog-to-digital
converters (ADCs). A functional block diagram of the
PGA2500 is shown in Figure 1.
The differential analog output of the PGA2500 is
constantly monitored by a DC servo amplifier loop. The
purpose of the servo loop is to minimize the DC offset
voltage present at the analog outputs by feeding back an
error signal to the input stage of the programmable gain
amplifier. The error signal is then used to correct the offset.
The DC servo may be disabled by driving the DCEN input
(pin 7) high or setting the DC bit in the serial control word
to 1. Normally, the DCEN pin is connected to DGND to
enable the DC servo, while the DC bit is set to 0.
The analog input to the preamplifier is provided
differentially at the V + and V − inputs (pins 27 and 26,
IN
IN
respectively). The programmable gain amplifier can be
programmed to either pass through the signal at unity gain,
or apply 10dB to 65dB of gain to the input signal. The gain
of the amplifier is adjustable over the full 10dB to 65dB
range in 1dB steps. The differential output of the PGA2500
is made available at V
respectively). Gain is controlled using a serial port
interface.
+ and V
OUT
− (pins 17 and 16,
OUT
0dB
CS
SCLK
ZCEN
SERIAL
PORT and
LOGIC
GPO1
GPO2
GPO3
GPO4
SDI
SDO
OVR
CONTROL
VCOMIN
VOUT
+
VIN+
PGA
−
VOUT
−
VIN
Gain Range
0dB or
CS1
AGND
+10dB to +65dB
1dB per step
VA+
VA+
DC
Servo
−
−
VA
VA
−
VD
DGND
CS2
DCEN
CS1 and CS2 are external DC servo integrator capacitors,
and are connected across the CS11/CS12 and CS21/CS22 pins, respectively.
Figure 1. PGA2500 Functional Block Diagram
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Two external capacitors are required for the DC servo
switching gain, thereby minimizing audible artifacts at the
preamplifier output. Since zero crossing detection can add
some delay when performing gain changes (up to 16ms
maximum for a detector timeout event), there may be
cases where the user may wish to disable the function.
Forcing the ZCEN input low disables zero crossing
detection, with gain changes occurring immediately when
programmed.
function, with one capacitor connected between C
and
S11
C
(pins 24 and 23), and the second capacitor connected
S12
between C
and C
(pins 22 and 21). Capacitor values
S21
S22
up to 4.7µF may be utilized. However, larger valued
capacitors will result in longer settling times for the DC
servo loop. A value of 1µF is recommended for use in most
microphone preamplifier applications.
The PGA2500 includes a common-mode servo function.
This function is enabled and disabled using the CM bit in
the serial control word; see Figure 2. When enabled, the
servo provides common-mode negative feedback at the
input differential pair, resulting in very low common-mode
input impedance. The differential input impedance is not
affected by this feedback. This function is useful when the
source is floating, or has a high common-mode output
impedance. In this case, the only connection between the
source and the ground will be through the PGA2500
preamplifier input resistance.
An overflow indicator output, OVR, is provided at pin 5.
The OVR pin is an active high, CMOS-logic-level output.
The overflow output is forced high when the preamplifier
output voltage exceeds one of two preset thresholds. The
threshold is programmed through the serial port interface
using the OL bit. If OL = 0, then the threshold is set to
5.1V
differential, which is approximately −1dB below
RMS
the specified output voltage range. If OL = 1, then the
threshold is set to 4.0V differential, which is
RMS
approximately −3dB below the specified output voltage
range.
In this case, input common-mode parasitic current is
determined by high output impedance of the source, not by
input impedance of the amplifier. Therefore, input
common-mode interference can be reduced by lowering
the common-mode input impedance while at the same
time not increasing the input common-mode current.
Increasing common-mode current degrades common-
mode rejection. Using the common-mode servo, overall
common-mode rejection can be improved by suppressing
low and medium frequency common-mode interference.
The PGA2500 includes four programmable digital outputs,
named GPO1 through GPO4 (pins 1 through 4,
respectively), which are controlled via the serial port
interface. All four pins are CMOS-logic-level outputs.
These pins may be used to control relay drivers or
switches used for external preamplifier functions,
including input pads, filtering, polarity reversal, or phantom
power.
ANALOG INPUTS AND OUTPUTS
An analog signal is input differentially across the V + (pin
The common-mode servo function is designed to operate
with a total common-mode input capacitance (including
the microphone cable capacitance) of up to 10nF. Beyond
this limit, stable servo operation is not ensured.
IN
27) and V − (pin 26) inputs. The input voltage range and
IN
input impedance are provided in the Electrical
Characteristics table. The Applications Information
section of this datasheet provides additional details
regarding typical input circuit considerations when
interfacing the PGA2500 to a microphone input.
The common-mode voltage control input, named V
IN
COM
(pin 25), allows the PGA2500 output and input to be DC-
biased to a common-mode voltage between 0 and +2.5V.
This allows for a DC-coupled interface between the
PGA2500 preamplifier output and the inputs of common
single-supply audio ADCs.
Both VIN+ and VIN− are biased at approximately 0.65V
below the common-mode input voltage, supplied at
VCOMIN (pin 25). The use of AC-coupling capacitors (see
Figure 7, page 12) is highly recommended for the analog
inputs of the PGA2500. If DC-coupling is required for a
given application, the user must take this offset into
account.
A dedicated 0dB input (pin 8) is provided so that the gain
of the PGA2500 may be forced to unity without using the
serial port interface. The 0dB input overrides gain settings
made through the serial port. While the 0dB input is active
(forced high), the serial port register may be updated or
data may passed through the serial interface to other
PGA2500 devices in daisy-chain configuration. However,
any changes made in the gain will not take effect until the
0dB input is driven low.
It is recommended that a small capacitor be connected
from each analog input pin to analog ground. Values of at
least 50pF are recommended. See Figure 7 (page 12) for
larger capacitors being used for EMI filtering which will
satisfy this requirement.
The zero crossing control input, named ZCEN (pin 9), is
provided for enabling and disabling the internal zero
crossing detector function. Forcing the ZCEN input high
enables the function. Zero crossing detection is used to
force gain changes on zero crossings of the analog input
signal. This limits the glitch energy associated with
The analog output is presented differentially across V
+
OUT
(pin 17) and V
− (pin 16). The output voltage range is
OUT
provided in the Electrical Characteristics table. The analog
output is designed to drive a 600Ω differential load while
meeting the published THD+N specifications and typical
performance curves.
8
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The SCLK input is used to clock serial data into the SDI pin
and out of the SDO pin. The SDI pin functions as the serial
data input, and is used to write the serial port register. The
SDO pin is the shift register serial output, and is used for
either register read-back or for daisy-chaining multiple
PGA2500 devices. Data on SDI is sampled on the rising
edge of SCLK, while data is clocked out of SDO on the
falling edge of SCLK.
SERIAL PORT OPERATION
The serial port interface for the PGA2500 is comprised of
four wires: CS (pin 11), SCLK (pin 12), SDI (pin 10), and
SDO (pin 13). Figure 2 illustrates the serial port protocol,
while Figure 3 and the Electrical Characteristics table
provide detailed timing parameters for the port.
The CS input functions as the chip select and word latch
clock for the serial port. The CS input must be low in order
to clock data into and out of the serial port. The control
word is latched on a low-to-high transition of the CS input.
The serial port ignores the SCLK and SDI inputs when CS
is high, and the SDO output is set to a high impedance
state while CS is high.
When the 0dB input (pin 8) is forced high, the gain set by
the serial port register will be overridden. The serial port
register may be updated while the 0dB input is forced high,
but the programmed gain will not take effect until the 0dB
input is forced low.
CS
SCLK
SDI
Data Ignored
DC
DC
CM
CM
0
0
OL
OL
D4
D4
D3
D3
D2
D2
D1
D1
0
0
0
0
G5
G5
G4
G4
G3
G3
G2
G2
G1
G1
G0
G0
Data Ignored
High Impedance
High Impedance
SDO
DC Servo Enable
(Active Low)
Preamplifier Gain
where N = G[5:0]DEC
CM Servo Enable
(Active High)
For N = 0
Gain = 0dB
Overload Indicator Bit
(0 = 5.1VRMS, 1 = 4.0VRMS
)
For N = 1 to 56
Gain (dB) = 9 + N
Data for GPO4
Data for GPO3
Data for GPO2
Data for GPO1
For N = 57 to 63
Gain (dB) = 65
Figure 2. Serial Port Protocol
CS
tSDS
tCSCR
tCFCS
tSDH
SCLK
SDI
MSB
SDO
MSB
tCSZ
tCSO
tCFDO
Figure 3. Serial Port Timing Requirements
9
ꢀ ꢠꢉ ꢡ ꢢ ꢣ ꢣ
www.ti.com
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
number of cascaded PGA2500 devices. To program all of
the devices, simply force CS low for 16 x N serial clock
periods and clock in 16 x N bits of control data. The CS
input is then forced high to latch in the new settings.
DAISY-CHAINING MULTIPLE PGA2500
PREAMPLIFIERS
Since the serial port interface may be viewed as a serial in,
serial out shift register, multiple PGA2500 preamplifiers
may be connected in a cascaded or daisy-chained fashion,
as shown in Figure 4. The daisy-chained PGA2500
devices behave as a 16 x N-bit shift register, whereN is the
A timing diagram for the daisy-chain application is shown
in Figure 5.
VOUT
+
SDI
CS
DOUT
−
VOUT
CS
Micro
or DSP
PGA2500
#1
SCLK
SDO
DATACLK
DIN
VIN
+
−
VIN
VOUT
+
SDI
CS
−
VOUT
PGA2500
#2
SCLK
SDO
VIN
+
−
VIN
VOUT
+
SDI
CS
−
VOUT
PGA2500
#N
SCLK
SDO
VIN+
−
VIN
Figure 4. Daisy-Chain Configuration for Multiple PGA2500 Preamplifiers
CS
SCLK
SDI
G0
DC
G0
DC
DC
G0
Device #N
Device #2
Device #1
Figure 5. Serial Port Operation for Daisy-Chain Operation
10
ꢀ ꢠ ꢉꢡ ꢢꢣ ꢣ
www.ti.com
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
The PGA2500 can be placed on a split ground plane, with
the package located over the split. However, there must be
a low impedance connection between the analog and
digital grounds at a common return point.
APPLICATION INFORMATION
This section provides practical information for designing
the PGA2500 into end applications.
BASIC CIRCUIT CONFIGURATION
The DC common-mode input, V IN (pin 25), can be
COM
A typical applications circuit, without the input and output
circuitry, is shown in Figure 6. Power-supply bypass and
DC servo capacitors are shown with recommended
values. All capacitors should be placed as close as
possible to the PGA2500 package to limit inductive noise
coupling. Surface-mount capacitors are recommended
(X7R ceramic for the 0.1µF and 1µF capacitors, and low
ESR tantalum for the 4.7µF capacitors).
connected to analog ground or a DC voltage (such as the
reference or common voltage output of an audio ADC).
When biasing this input to a DC voltage, keep in mind that
both the analog output and input pins are level-shifted by
the value of the bias voltage.
1
28
GPO1
AGND
2
GPO2
To
27
26
3
Relay Drivers,
GPO3
Switches, or Indicators
From
VIN
+
Analog Input
Circuit
4
GPO4
−
VIN
To
5
25
Optional
Common−Mode
Voltage
OVR
VCOMIN
6
(1)
(1)
µ
1 F
DGND
Ω
µ
0
0.1 F
24
23
CS11
CS12
7
DCEN
µ
1 F
8
22
21
17
16
0dB
CS21
CS22
PGA2500
To/From
MPU, MCU,
DSP, or Logic
9
10
11
12
13
ZCEN
SDI
To
VOUT+
Analog Output
Circuit
−
CS
VOUT
SCLK
SDO
µ
0.1 F
19
18
−
−
VA
µ
0.1 F
µ
0.1 F
14
−
VD
VA
µ
4.7 F
+
µ
0.1 F
15
20
µ
4.7 F
+
−
−
VA
VA
µ
0.1 F
VA+
µ
4.7 F
+
= Analog Ground
= Digital Ground
Connect Digital and Analog Grounds at
one common return point in the circuit.
Ω
10
Ω
NOTE: (1) Install a 0 shunt or jumper only when connecting VCOMIN
−
VA
µ
to analog ground. Install a 0.1 F ceramic capacitor (X7R type) only
when connecting VCOMIN to a DC common−mode voltage source.
Figure 6. Basic Circuit Configuration for the PGA2500
11
ꢀ ꢠꢉ ꢡ ꢢ ꢣ ꢣ
www.ti.com
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
have a high working voltage rating, with 50V being the
minimum and 63V recommended for long term reliability.
INPUT CIRCUIT CONSIDERATIONS
The input circuit for the PGA2500 must include several
items that are common to most microphone preamplifiers.
Figure 7 shows a typical input circuit configuration. Other
functions, such as input attenuation (pads), filters, and
polarity reversal switches are commonly found in
preamplifier circuits, but are not shown here in order to
focus on the basic input circuit requirements.
The blocking capacitors, along with the PGA2500 input
resistance, form a high-pass filter circuit. With the typical
input resistance of the PGA2500 specified in the Electrical
Characteristics table, the value of the capacitor can be
chosen to meet the desired low frequency response for the
end application. At the same time, the value should be no
higher than required, since larger capacitors store more
charge and increase the surge current seen at the
preamplifier when a short circuit occurs on the microphone
input connector.
The microphone input is typically taken from a balanced
XLR or TRS input connection (XLR shown). The 1000pF
capacitors provide simple EMI filtering for the circuit.
Additional filtering for low- or high-frequency noise may be
added, depending upon the end application environment.
A bridging resistor is shown and may be selected to
provide the desired overall input impedance required for a
given microphone. This resistance will be in parallel with
the phantom power bias resistors and the PGA2500 input
resistance to set the actual impedance seen by the
microphone.
To protect the PGA2500 from large surge currents, power
Schottky diodes are placed on the input pins to both the
VA+ and VA− power supplies. Schottky diodes are used
due to their lower turn-on voltage compared to standard
rectifier diodes. Power devices are required since the
surge currents from a large valued blocking capacitor
(47µF) can exceed 4.5 amps for a very short duration of
time. It is recommended that the Schottky diode chosen for
this application be specified for at least a 10A surge
current.
Connections for +48V phantom power, required for
condenser microphones, are shown in Figure 7. The
phantom power requires an On/Off switch, as dynamic
microphones do not require phantom power and may be
damaged if power is applied. DC-blocking capacitors are
required between the phantom power connections and the
PGA2500 inputs. The blocking capacitors are selected to
The use of a series current-limiting resistor prior to the
protection diodes will aid in handling surge currents,
although the resistor will add noise to the circuit. Select a
current-liming resistor value that is as high as tolerable for
the desired noise performance of the preamplifier circuit.
µ
−
µ
10 F 47 F
(3)
63WV
+
VIN+
(2)
(4)
(4)
Ω
0.25W
6.81k
1000pF
1000pF
Mic Input
−
VA
VA+
2
1
(1)
3
Ω
0.25W
6.81k
1000pF
µ
−
µ
10 F 47 F
(4)
(4)
(3)
63WV
+
−
VIN
(2)
Phantom
Power
Switch
+48V
NOTES: (1) Bridging resistor, used to set the impedance seen by the microphone.
(2) The blocking capacitor value is selected based upon the desired low frequency response.
(3) Current−limiting resistor. Select the highest value tolerable based upon input noise requirements.
(4) Schottky diode, selected for fast turn−on and rated for a minimum of a 10A surge current.
Recommended device is the MBRA120LT3 from ON Semiconductor.
Figure 7. Typical Input Circuit for the PGA2500
12
ꢀ ꢠ ꢉꢡ ꢢꢣ ꢣ
www.ti.com
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
Plots of THD+N vs Frequency are shown in the Typical
Characteristics section of this datasheet for both
OPERATION WITH V
IN = +2.5V
COM
When interfacing the analog outputs of the PGA2500 with
audio ADC inputs, the converter will frequently have a
common-mode DC output pin. This pin may be connected
to the VCOMIN pin of the PGA2500 in order to facilitate a
DC-coupled interface between the two devices. The
common-mode DC voltage level is typically +2.5V,
although some converters may have a slightly lower value,
usually between +2.1V and +2.5V. There are several
issues that must be considered when operating the
PGA2500 in this fashion.
V
COMIN = 0V and +2.5V. The performance difference can
be seen when comparing the plots. The user needs to
consider whether the difference is acceptable for the end
application.
As a suggested alternative, the PGA2500 analog outputs
may be AC-coupled to the ADC inputs, allowing the
PGA2500 to operate with VCOMIN = 0V in order to achieve
best performance. The AC-coupling capacitors will affect
the overall low-frequency response of the preamplifier and
converter combination, and the user is advised to choose
a value that best suits the application requirements.
Both the analog input and output pins of the PGA2500 will
be level shifted by the VCOMIN voltage. The analog outputs
will be shifted to the VCOMIN level, while the analog inputs
will be shifted to approximately VCOMIN − 0.65V, due to the
offset that normally exists on the input pins. The level
shifting will limit the input and output swing of the
PGA2500, reducing the overall signal-to-noise ratio and
degrading the THD+N performance.
Figure 8 illustrates a typical PGA2500 to audio ADC
interface utilizing AC-coupling. In addition to the coupling
capacitors, a passive RC filter is required as an anti-alias
filter for the converter. The vast majority of audio ADCs are
of the oversampling delta-sigma variety, with a simple
single-pole filter meeting the anti-aliasing requirements for
this type of converter. Providing at least 6dB of attenuation
will also allow the PGA2500 to operate near full signal
swing without overdriving the ADC inputs.
Given VCOMIN = +2.5V and gains of 10dB through 65dB,
the output swing is limited to less than one-half that
specified in the Electrical Characteristics table. The output
will hard-clip at approximately a diode drop below the VA+
supply rail and a diode drop above analog ground.
Given VCOMIN = +2.5V and a gain of 0dB, the practical
maximum input or output voltage swing is approximately
1.0Vrms differential. Increasing the signal level much
beyond this point will result in a substantial increase in
distortion.
Figure 9 illustrates an application where the VCOMIN pin of
the PGA2500 is connected to the common-mode DC
output of the audio ADC, with a DC-coupled interface
between the PGA2500 analog outputs and the ADC
analog inputs.
Coupling
A/D Converter(1)
Capacitors
PGA2500
CC1
R
R
+
VOUT
+
+
Serial Data Output
PCM or DSD
2R
C
ADC
PGA
−
VOUT
CC2
VCOMIN
Attenuation and
Anti−Alias Filter
NOTE: (1) PCM1804, PCM4202, or PCM4204.
Figure 8. PGA2500 Analog Output to ADC Analog Input Interface, AC-Coupled
13
ꢀ ꢠꢉ ꢡ ꢢ ꢣ ꢣ
www.ti.com
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
PGA2500
A/D Converter(1)
R
R
+
−
VOUT
Serial Data Output
PCM or DSD
C
ADC
PGA
VOUT
VCOMIN
VCOM Output
Anti−Alias Filter
µ
0.1 F
NOTE: (1) PCM1804, PCM4202, or PCM4204.
Figure 9. PGA2500 Analog Output to ADC Analog Input Interface, DC-Coupled
14
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PGA2500IDB
PGA2500IDBG4
PGA2500IDBR
PGA2500IDBRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SSOP
DB
DB
DB
DB
28
28
28
28
50
50
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PGA2500I
NIPDAU
NIPDAU
NIPDAU
PGA2500I
PGA2500I
PGA2500I
1000 RoHS & Green
1000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PGA2500IDBR
SSOP
DB
28
1000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DB 28
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
PGA2500IDBR
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PGA2500IDB
DB
DB
SSOP
SSOP
28
28
50
50
530
530
10.5
10.5
4000
4000
4.1
4.1
PGA2500IDBG4
Pack Materials-Page 3
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
S
C
A
L
E
1
.
5
0
0
SMALL OUTLINE PACKAGE
C
8.2
7.4
TYP
A
0.1 C
SEATING
PIN 1 INDEX AREA
PLANE
26X 0.65
28
1
2X
10.5
9.9
8.45
NOTE 3
14
15
0.38
0.22
28X
0.15
C A B
5.6
5.0
B
NOTE 4
2 MAX
0.25
GAGE PLANE
(0.15) TYP
SEE DETAIL A
0.95
0.55
0.05 MIN
0 -8
A
15
DETAIL A
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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