首页 |元器件品牌

PGA870_10 [TI]

High-Speed, Fully Differential, Programmable-Gain Amplifier; 高速全差动，可编程增益放大器
PGA870_10
型号： PGA870_10
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

High-Speed, Fully Differential, Programmable-Gain Amplifier
高速全差动，可编程增益放大器

放大器
文件： 总26页 (文件大小：1182K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
PGA870  
www.ti.com  
SBOS436 –DECEMBER 2009  
High-Speed, Fully Differential, Programmable-Gain Amplifier  
Check for Samples: PGA870  
1
FEATURES  
DESCRIPTION  
23  
•
Wideband +5-V Operation: 650-MHz Bandwidth  
Low Impedance, Voltage Mode Output  
Wide Gain Range: –11.5 dB to +20 dB  
The PGA870 is a wideband programmable-gain  
amplifier (PGA) for high-speed signal chain and data  
acquisition systems. The PGA870 has been  
optimized to provide high bandwidth, low distortion,  
and low noise, making it ideally suited as a 14-bit  
analog-to-digital converter (ADC) driver for wireless  
base station signal chain applications. The wide gain  
range of –11.5 dB to +20 dB can be adjusted in  
0.5-dB gain steps through a 6-bit control word applied  
to the parallel interface. The gain control interface  
may be configured as a level-triggered latch or an  
edge-triggered latch, or it may be placed in an  
unlatched (transparent) mode. In addition to the 6-bit  
gain control, the PGA870 contains a power-down pin  
(PD) that can be used to put the device into a  
low-current, power-down mode. In this mode, the  
quiescent current drops to 2 mA, but the gain control  
circuitry remains active, allowing the gain of the  
PGA870 to be set before device power-up. The  
•
•
•
Precise 0.5-dB Gain Steps  
Step-to-Step Gain Error = ±0.03 dB  
•
•
•
•
HD2: –93 dBc at 100 MHz  
HD3: –88 dBc at 100 MHz  
IMD3: –98 dBc at 100 MHz, –95 dBc at 200 MHz  
OIP3: +47 dBm at 100 MHz;  
Exceeds +45 dBm for Frequencies to 300 MHz  
•
Flexible Gain Control Interface:  
–
–
–
Supports latched and unlatched options  
Gain may be set in power-down state  
Fast setup and hold times: 2.5 ns  
•
•
Low Disable Current: 2 mA  
Pb-Free (RoHS-Compliant) and Green Package  
PGA870 is offered in  
package.  
a QFN-28 PowerPAD™  
APPLICATIONS  
RELATED PRODUCTS  
•
Programmable Gain IF Amplifier:  
DEVICE  
DESCRIPTION  
–
–
Differential signal chains  
Single-ended to differential conversion  
Wideband, low-noise, low-distortion, fully  
differential amplifier  
THS4509  
•
Fast Gain Control Loops for:  
High-speed, fully differential 16-bit ADC  
driver  
THS7700  
THS9000  
ADS6149  
ADS6145  
–
–
Test/measurement  
Digital radio signal chains  
50-MHz to 400-MHz IF/RF Amplifier  
14-Bit, 250-MSPS ADC with DDR  
LVDS/CMOS Outputs  
•
•
ADC Driver for Wireless Base Station Signal  
Chains: GSM, WCDMA, MC-GSM  
Radar/Ranging Systems  
14-Bit, 125-MSPS ADC with DDR  
LVDS/CMOS Outputs  
Fast Gain Control Loop  
6b Gain Adjust  
+5 V  
6b  
FS = 250 MHz  
6b  
Signal Source  
Programmable  
Attenuator  
Bandpass  
Filter  
ADS6149  
FPGA  
Control Logic  
PGA870  
Latch Mode 1  
Powerdown 1  
Gain Strobe 1  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
PowerPAD is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
PGA870  
SBOS436 –DECEMBER 2009  
www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ORDERING INFORMATION(1)  
SPECIFIED  
PACKAGE  
DESIGNATOR  
TEMPERATURE  
RANGE  
PACKAGE  
MARKING  
ORDERING  
NUMBER  
TRANSPORT MEDIA,  
QUANTITY  
PRODUCT  
PACKAGE-LEAD  
PGA870  
PGA870  
PGA870IRHDT  
PGA870IRHDR  
Tape and Reel, 250  
Tape and Reel, 3000  
PGA870  
QFN-28  
RHD  
–40°C to +85°C  
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS(1)  
Over operating free-air temperature range, unless otherwise noted.  
PGA870  
UNIT  
Power supply  
6
V
Internal power dissipation  
See Thermal Characteristics  
Input voltage range  
VS  
–40 to +125  
+150  
V
°C  
°C  
°C  
V
Storage temperature range  
Maximum junction temperature (TJ)  
Maximum junction temperature (TJ), continuous operation, long-term reliability  
Human body model (HBM)  
+140  
2000  
ESD rating  
Charged device model (CDM)  
Machine model (MM)  
1000  
V
200  
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not supported.  
DISSIPATION RATINGS(1)  
POWER RATING(2)  
(TJ= +125°C)  
PACKAGE  
θJP(°C/W)  
θJA(°C/W)  
TA= +25°C  
TA= +85°C  
QFN-28  
4.1  
35  
2.9 W  
0.87 W  
(1) These data were taken with the JEDEC High-K test PCB. For the JEDEC low-K test PCB, θJA is 350°C/W.  
(2) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase and  
long-term reliability starts to be reduced. Thermal management of the final printed circuit board should strive to keep the junction  
temperature at or below +125° C for best performance and reliability.  
2
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): PGA870  
PGA870  
www.ti.com  
SBOS436 –DECEMBER 2009  
ELECTRICAL CHARACTERISTICS: VS+= +5 V  
Boldface limits are tested at +25°C.  
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL= 200 Ω differential, G = 20 dB, and input and  
output common-mode at internal midsupply reference, unless otherwise noted.  
PGA870IRHD  
TEST  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
LEVEL(1)  
AC PERFORMANCE  
Small-signal bandwidth  
Large-signal bandwidth  
Bandwidth for 0.1-dB flatness  
Slew rate (differential)  
Rise time  
G = 20 dB, VO = 100 mVPP  
650  
650  
100  
2900  
0.55  
0.55  
3
MHz  
MHz  
MHz  
V/µs  
ns  
C
C
C
C
C
C
C
C
G = 20 dB, VO = 2 VPP  
2-V step  
2-V step  
Fall time  
2-V step  
ns  
Settling time to 1%  
Settling time to 0.1%  
HARMONIC DISTORTION  
2-V step  
ns  
2-V step  
5
ns  
Gain = +20 dB, VO = 2 VPP, RL = 200 Ω  
f = 50 MHz  
–108  
–93  
–71  
–95  
–88  
–75  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Second-order harmonic distortion  
Third-order harmonic distortion  
f = 100 MHz  
f = 200 MHz  
f = 50 MHz  
f = 100 MHz  
f = 200 MHz  
f1(MHz)  
49  
f2(MHz)  
51  
-87  
-90  
-89  
-103  
–98  
–95  
50  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBm  
dBm  
dBm  
dB  
Second-order intermodulation  
distortion  
2-MHz tone  
spacing  
99  
101  
201  
51  
199  
49  
2-MHz tone  
spacing  
Third-order intermodulation distortion  
Output third-order intercept  
99  
101  
201  
51  
199  
49  
VOUT = 2 VPP  
RL = 200 Ω  
,
99  
101  
201  
47  
199  
45  
Noise figure  
150-Ω system, Gain = +20 dB, f = 100 MHz  
13  
DC  
TA= +25°C  
–30  
±5  
20  
30  
mV  
mV  
A
B
B
Output offset voltage  
TA= –40°C to +85°C  
TA= –40°C to +85°C  
–35  
35  
Average offset voltage drift  
INPUT  
μV/°C  
Input return loss  
ZSYS= 150 Ω, frequency < 300MHz  
-40  
150  
1.2  
141  
76  
dB  
Ω
B
B
C
B
A
Differential input resistance  
Differential input capacitance  
Single-ended input resistance  
Common-mode rejection ratio  
129  
173  
pF  
Ω
TA= +25°C, Gain = 20 dB  
54  
dB  
(1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization  
and simulation. (C) Typical value; only for information.  
Copyright © 2009, Texas Instruments Incorporated  
3
Product Folder Link(s): PGA870  
PGA870  
SBOS436 –DECEMBER 2009  
www.ti.com  
ELECTRICAL CHARACTERISTICS: VS+= +5 V (continued)  
Boldface limits are tested at +25°C.  
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL= 200 Ω differential, G = 20 dB, and input and  
output common-mode at internal midsupply reference, unless otherwise noted.  
PGA870IRHD  
TEST  
PARAMETER  
OUTPUT  
CONDITIONS  
MIN  
TYP  
3.7  
1.3  
4.8  
MAX  
UNITS  
LEVEL(1)  
TA= +25°C  
3.5  
V
V
A
B
A
B
B
B
A
Maximum output voltage high  
Minimum output voltage low  
Each output with  
100 Ω to  
TA= –40°C to +85°C  
3.4  
TA= +25°C  
1.5  
V
midsupply  
TA= –40°C to +85°C  
1.6  
V
TA= +25°C, RL = 200 Ω  
TA= –40°C to +85°C  
TA= +25°C, RL = 20 Ω  
4
3.6  
40  
VPP  
VPP  
mAP  
Differential output voltage swing  
Differential output current drive  
50  
Output common-mode offset from  
midsupply  
TA= +25°C, RL = 20 Ω  
–60  
±10  
60  
mV  
A
Differential output impedance  
Differential output impedance model  
POWER SUPPLY  
f = 100 MHz  
3.5 / 87  
0.3 / 3.8  
Ω / °  
B
B
Series ROUT,EQ, LOUT,EQ  
Ω / nH  
Specified operating voltage  
4.75  
138  
136  
54  
5
5.25  
148  
150  
V
C
A
B
A
TA= +25°C  
143  
mA  
mA  
dB  
Quiescent current  
TA= –40°C to +85°C  
TA= +25°C, Gain = 20 dB(2)  
Power-supply rejection ratio (PSRR)  
POWER DOWN  
76  
2
Device power-up voltage threshold  
Device power-down voltage threshold  
Ensured on above 2.1 V  
Ensured off below 0.9 V  
TA= +25°C  
2.1  
V
V
A
A
A
B
C
B
C
C
C
0.9  
4
mA  
mA  
dB  
Power-down quiescent current  
TA= –40°C to +85°C  
4.8  
Forward isolation in power-down state f = 100 MHz  
-110  
0.5  
PD pin input bias current  
PD pin input impedance  
Turn-on time delay  
Turn-off time delay  
GAIN SETTING  
PD= VS–  
μA  
20 || 0.5  
16  
kΩ || pF  
ns  
Measured to output on  
Measured to output off  
60  
ns  
Gain range  
–11.5  
+20  
dB  
Bits  
dB  
A
B
A
A
A
B
B
Gain control: G0 to G5  
Gain step size  
6
0.50  
–11.5 dB ≤ Gain ≤ +20 dB  
Absolute gain error  
–0.35  
–0.10  
0.0018  
5
±0.05  
±0.03  
0.0022  
0.35  
0.10  
dB  
Gain error over entire gain range  
Step to step gain error  
dB  
Gain temp coefficient  
0.0026  
dB/°C  
ns  
Gain settling time  
DIGITAL INPUTS  
B0 to B5 and Latch  
Digital threshold low  
0.9  
V
V
A
A
C
C
Digital threshold high  
2.1  
Current into/out of digital pins  
Data set up time to GAIN STROBE low  
±20  
2.5  
nA  
ns  
Data hold time after GAIN STROBE  
low  
0
ns  
ns  
C
C
Latency time  
6.4  
(2) PSRR is defined with respect to a differential output.  
4
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): PGA870  
PGA870  
www.ti.com  
SBOS436 –DECEMBER 2009  
PIN CONFIGURATION  
QFN-28  
RHD PACKAGE  
(TOP VIEW)  
21 GND  
20 VS+  
LATCH MODE  
VS+  
1
2
3
19 OUT+  
18 GND  
17 OUT-  
16 VS+  
IN+  
VMID2  
4
5
6
7
IN-  
VS+  
PowerPADä  
15  
GND  
GAIN STROBE  
PIN ASSIGNMENTS  
PIN NUMBER  
PIN NAME  
DESCRIPTION  
Controls latched and unlatched acquisition of the gain control word (B0 to B5). See the application section Gain  
Control Modes for a detailed description.  
1
LATCH MODE  
2, 6, 11, 16, 20, 25  
3
VS+  
IN+  
+5V power supply  
Noninverting input  
Buffer output for the internal midsupply reference. This point is the output of an active buffer which is not intended  
to drive an external load. It should be bypassed by a 0.1-μF capacitor.  
4
VMID2  
5
7
IN–  
GAIN STROBE  
B5 (MSB)  
B4  
Inverting input  
Gain latch clock pin  
Gain control MSB  
Gain control bit 4  
Gain control bit 3  
Gain control bit 2  
Gain control bit 1  
Gain control bit 0  
Inverting output  
8
9
10  
12  
13  
14  
17  
B3  
B2  
B1  
B0 (LSB)  
OUT–  
15, 18, 21, 22, 23,  
24, 26  
GND  
Ground  
19  
27  
OUT+  
PD  
Noninverting output  
Active low power-down for device analog circuitry. Gain control CMOS circuitry is still active when PD is low.  
Chip bypass pin for internal midsupply reference. This point is the midpoint of a resistive voltage divider and is not  
intended to function as an input. It should be bypassed with a 0.1-μF capacitor.  
28  
VMID1  
Thermal Pad  
PowerPAD  
Thermal contact for heat dissipation. The thermal pad must be connected to electrical ground.  
Copyright © 2009, Texas Instruments Incorporated  
5
Product Folder Link(s): PGA870  
PGA870  
SBOS436 –DECEMBER 2009  
www.ti.com  
TYPICAL CHARACTERISTICS  
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and  
output common-mode at internal midsupply reference, unless otherwise noted.  
SMALL-SIGNAL AC RESPONSE  
SMALL-SIGNAL AC RESPONSE  
Gain Adjusted from –11.5 dB to +5 dB  
Gain Adjusted from +5.5 dB to +20 dB  
10  
5
25  
20  
15  
10  
5
Gain Adjusted in 0.5-dB Steps  
VOUT = 200 mVPP  
Gain Adjusted in 0.5-dB Steps  
VOUT = 200 mVPP  
Gain = +5 dB  
Gain = +20 dB  
0
-5  
-10  
-15  
Gain = +5.5 dB  
Gain = -11.5 dB  
0
10  
100  
1000  
10  
100  
Frequency (MHz)  
1000  
Frequency (MHz)  
Figure 1.  
Figure 2.  
LARGE-SIGNAL AC RESPONSE AT FOUR GAINS  
DIFFERENTIAL INPUT  
LARGE-SIGNAL AC RESPONSE AT FOUR GAINS  
SINGLE-ENDED INPUT  
30  
30  
25  
20  
15  
10  
5
25  
20  
15  
10  
5
Gain = 20 dB  
Gain = 10 dB  
Gain = 20 dB  
Gain = 10 dB  
Gain = 0 dB  
Gain = 0 dB  
0
0
Gain = -6 dB  
Gain = -6 dB  
-5  
-5  
-10  
-15  
-20  
-10  
-15  
-20  
Differential Input  
VOUT = 2 VPP  
Single-Ended Input  
VOUT = 2 VPP  
10  
100  
1000  
10  
100  
1000  
Frequency (MHz)  
Frequency (MHz)  
Figure 3.  
Figure 4.  
DIFFERENTIAL FREQUENCY RESPONSE vs CAPACITIVE LOAD  
ROS vs CAPACITIVE LOAD  
25  
100  
10  
1
CL = 44 pF  
CL = 94 pF  
CL  
=
10 pF  
20  
15  
10  
5
CL = 820 pF  
CL = 470 pF  
CL  
=
ROS  
ROS  
16 pF  
CL  
CL  
CL  
=
VOUT  
VOUT  
PGA870  
PGA870  
ROS  
ROS  
20 pF  
CL  
CL  
0
10  
100  
1000  
1
10  
100  
1000  
Frequency (MHz)  
Capacitive Load (pF)  
Figure 5.  
Figure 6.  
6
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): PGA870  
PGA870  
www.ti.com  
SBOS436 –DECEMBER 2009  
TYPICAL CHARACTERISTICS (continued)  
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and  
output common-mode at internal midsupply reference, unless otherwise noted.  
STEP-TO-STEP GAIN ERROR vs GAIN SETTING  
LARGE-SIGNAL GAIN vs GAIN SETTING  
OVER TEMPERATURE  
25  
20  
15  
10  
5
0.15  
0.10  
0.05  
0
-40°C  
+25°C  
-0.05  
-0.10  
-0.15  
-0.20  
0
+85°C  
-5  
-10  
-15  
50 MHz  
100 MHz  
200 MHz  
-12-10 -8 -6 -4 -2  
0
2
4
6
8
10 12 14 16 18 20  
-12-10 -8 -6 -4 -2  
0
2
4
6
8
10 12 14 16 18 20  
Gain Setting  
Gain Setting  
Figure 7.  
Figure 8.  
STEP-TO-STEP GAIN ERROR vs GAIN SETTING  
OVER FREQUENCY  
GAIN STEP RESPONSE: NO LATCH  
4.0  
1.5  
1.0  
0.5  
0
0.04  
Gain Control  
Gain Code = 111111  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
0.02  
0
-0.02  
-0.04  
-0.06  
-0.08  
-0.5  
-1.0  
-1.5  
50 MHz  
100 MHz  
200 MHz  
Gain Code = 000000  
Amplifier  
Output  
-0.5  
-1.0  
0
100  
200  
300  
400  
500  
-12-10 -8 -6 -4 -2  
0
2
4
6
8 10 12 14 16 18 20  
Time (ns)  
Gain Setting  
Figure 9.  
Figure 10.  
GAIN STEP RESPONSE: LEVEL-TRIGGERED GAIN LATCH  
GAIN STEP RESPONSE: EDGE-TRIGGERED LATCH  
2.5  
2.5  
2.0  
1.5  
1.0  
0.5  
0
Gain Code =  
Gain Strobe  
111111  
Gain Code = 111111  
Gain  
Strobe  
2.0  
1.5  
1.0  
0.5  
0
Gain Code =  
000000  
1.0  
0.5  
0
1.0  
Gain Code =  
000000  
0.5  
0
-0.5  
-1.0  
-0.5  
-1.0  
Time (50 ns/div)  
Time (50 ns/div)  
Figure 11.  
Figure 12.  
Copyright © 2009, Texas Instruments Incorporated  
7
Product Folder Link(s): PGA870  
PGA870  
SBOS436 –DECEMBER 2009  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and  
output common-mode at internal midsupply reference, unless otherwise noted.  
SECOND-ORDER INTERMODULATION DISTORTION  
THIRD-ORDER INTERMODULATION DISTORTION  
FOR FOUR OUTPUT LOADS (VOUT = 2 VPP  
)
FOR TWO GAINS AND FOUR OUTPUT LOADS (VOUT = 2 VPP)  
-70  
-75  
-80  
-85  
-90  
-95  
-100  
-80  
-82  
-84  
-86  
-88  
-90  
-92  
-94  
VOUT = 2 VPP  
VOUT = 2 VPP  
DF = 2 MHz  
DF = 2 MHz  
-96  
-98  
-100  
-102  
-104  
-106  
-108  
-110  
RL = 100 W  
RL = 200 W  
RL = 500 W  
RL = 1 kW  
RL = 100 W  
RL = 200 W  
RL = 500 W  
RL = 1 kW  
Dashed lines: Gain = -6 dB  
Solid lines: Gain = +10 dB  
Gain = +10 dB  
50 100  
150  
200  
250  
300  
50  
100  
150  
200  
250  
300  
Frequency (MHz)  
Frequency (MHz)  
Figure 13.  
Figure 14.  
SECOND-ORDER INTERMODULATION DISTORTION  
FOR FOUR OUTPUT LOADS (VOUT = 2 VPP  
THIRD-ORDER INTERMODULATION DISTORTION  
FOR TWO GAINS AND FOUR OUTPUT LOADS (VOUT = 2 VPP)  
)
-70  
-75  
-80  
-85  
-90  
-95  
-100  
-80  
-82  
-84  
-86  
-88  
-90  
-92  
-94  
VOUT = 2 VPP  
VOUT = 2 VPP  
RL = 100 W  
RL = 200 W  
RL = 500 W  
RL = 1 kW  
DF = 2 MHz  
DF = 2 MHz  
-96  
-98  
-100  
-102  
-104  
-106  
-108  
-110  
RL = 100 W  
RL = 200 W  
RL = 500 W  
RL = 1 kW  
Dashed lines: Gain = 0 dB  
Solid lines: Gain = +20 dB  
Gain = +20 dB  
50  
100  
150  
200  
250  
300  
50  
100  
150  
200  
250  
300  
Frequency (MHz)  
Frequency (MHz)  
Figure 15.  
Figure 16.  
OUTPUT THIRD-ORDER INTERCEPT vs FREQUENCY  
(VOUT = 2 VPP  
)
50  
48  
46  
44  
42  
40  
38  
36  
VOUT = 2 VPP  
RL = 200 W  
Gain = +20 dB  
Gain = +10 dB  
Gain = 0 dB  
Gain = -6 dB  
50  
100  
150  
200  
250  
300  
Frequency (MHz)  
Figure 17.  
8
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): PGA870  
PGA870  
www.ti.com  
SBOS436 –DECEMBER 2009  
TYPICAL CHARACTERISTICS (continued)  
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and  
output common-mode at internal midsupply reference, unless otherwise noted.  
SECOND-ORDER INTERMODULATION DISTORTION  
THIRD-ORDER INTERMODULATION DISTORTION  
FOR FOUR OUTPUT LOADS (VOUT = 3 VPP  
)
FOR TWO GAINS AND FOUR OUTPUT LOADS (VOUT = 3 VPP)  
-70  
-75  
-80  
-85  
-90  
-95  
-100  
-74  
VOUT = 3 VPP  
Gain = +10 dB  
-76  
DF = 2 MHz  
-78  
-80  
-82  
-84  
-86  
-88  
-90  
RL = 100 W  
RL = 200 W  
RL = 500 W  
RL = 100 W  
RL = 200 W  
RL = 500 W  
RL = 1 kW  
-92  
-94  
-96  
VOUT = 3 VPP  
Dashed lines: Gain = -6 dB  
-98  
RL = 1 kW  
DF = 2 MHz  
Solid lines: Gain = +10 dB  
-100  
50  
100  
150  
200  
250  
300  
50  
100  
150  
200  
250  
300  
Frequency (MHz)  
Frequency (MHz)  
Figure 18.  
Figure 19.  
SECOND-ORDER INTERMODULATION DISTORTION  
THIRD-ORDER INTERMODULATION DISTORTION  
FOR FOUR OUTPUT LOADS (VOUT = 3 VPP  
)
FOR TWO GAINS AND FOUR OUTPUT LOADS (VOUT = 3 VPP)  
-70  
-75  
-80  
-85  
-90  
-95  
-100  
-74  
VOUT = 3 VPP  
VOUT = 3 VPP  
RL = 100 W  
RL = 200 W  
RL = 500 W  
RL = 1 kW  
RL = 100 W  
RL = 200 W  
RL = 500 W  
RL = 1 kW  
-76  
-78  
-80  
-82  
-84  
-86  
-88  
-90  
-92  
-94  
-96  
-98  
-100  
DF = 2 MHz  
DF = 2 MHz  
Dashed lines: Gain = 0 dB  
Solid lines: Gain = +20 dB  
Gain = +20 dB  
50  
100  
150  
200  
250  
300  
50  
100  
150  
200  
250  
300  
Frequency (MHz)  
Frequency (MHz)  
Figure 20.  
Figure 21.  
OUTPUT THIRD-ORDER INTERCEPT vs FREQUENCY  
(VOUT = 3 VPP  
)
52  
50  
48  
46  
44  
42  
40  
38  
VOUT = 3 VPP  
RL = 200 W  
Gain = +20 dB  
Gain = +10 dB  
Gain = 0 dB  
Gain = -6 dB  
50  
100  
150  
200  
250  
300  
Frequency (MHz)  
Figure 22.  
Copyright © 2009, Texas Instruments Incorporated  
9
Product Folder Link(s): PGA870  
PGA870  
SBOS436 –DECEMBER 2009  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and  
output common-mode at internal midsupply reference, unless otherwise noted.  
HARMONIC DISTORTION vs FREQUENCY  
(VOUT = 2 VPP  
HARMONIC DISTORTION vs FREQUENCY  
(VOUT = 2 VPP  
)
)
-55  
-60  
-45  
-50  
-55  
-60  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
-100  
-55  
-60  
-45  
-50  
-55  
-60  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
-100  
VOUT = 2 VPP  
VOUT = 2 VPP  
RL = 100 W  
RL = 200 W  
-65  
-65  
-70  
-70  
-75  
-75  
-80  
-80  
-85  
-85  
-90  
-90  
Dashed lines: 2nd Harmonic  
Solid lines: 3rd Harmonic  
Dashed lines: 2nd Harmonic  
Solid lines: 3rd Harmonic  
-95  
-95  
-100  
-105  
-110  
-100  
-105  
-110  
Gain = -6 dB  
Gain = +10 dB  
Gain = +20 dB  
Gain = -6 dB  
Gain = +10 dB  
Gain = +20 dB  
Gain = 0 dB  
Gain = 0 dB  
0
50  
100  
150  
200  
250  
300  
0
50  
100  
150  
200  
250  
300  
Frequency (MHz)  
Frequency (MHz)  
Figure 23.  
Figure 24.  
HARMONIC DISTORTION vs FREQUENCY  
(VOUT = 2 VPP  
HARMONIC DISTORTION vs FREQUENCY  
(VOUT = 2 VPP  
)
)
-55  
-60  
-45  
-50  
-55  
-60  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
-100  
-55  
-60  
-45  
-50  
-55  
-60  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
-100  
VOUT = 2 VPP  
VOUT = 2 VPP  
RL = 500 W  
RL = 1 kW  
-65  
-65  
-70  
-70  
-75  
-75  
-80  
-80  
-85  
-85  
-90  
-90  
-95  
-95  
Dashed lines: 2nd Harmonic  
Solid lines: 3rd Harmonic  
Dashed lines: 2nd Harmonic  
Solid lines: 3rd Harmonic  
-100  
-105  
-110  
-100  
-105  
-110  
Gain = -6 dB  
Gain = +10 dB  
Gain = +20 dB  
Gain = -6 dB  
Gain = +10 dB  
Gain = +20 dB  
Gain = 0 dB  
Gain = 0 dB  
0
50  
100  
150  
200  
250  
300  
0
50  
100  
150  
200  
250  
300  
Frequency (MHz)  
Frequency (MHz)  
Figure 25.  
Figure 26.  
10  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): PGA870  
PGA870  
www.ti.com  
SBOS436 –DECEMBER 2009  
TYPICAL CHARACTERISTICS (continued)  
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and  
output common-mode at internal midsupply reference, unless otherwise noted.  
HARMONIC DISTORTION vs FREQUENCY  
(VOUT = 3 VPP  
HARMONIC DISTORTION vs FREQUENCY  
(VOUT = 3 VPP  
)
)
-55  
-60  
-40  
-45  
-50  
-55  
-60  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
-55  
-60  
-40  
-45  
-50  
-55  
-60  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
VOUT = 3 VPP  
VOUT = 3 VPP  
RL = 100 W  
RL = 200 W  
-65  
-65  
-70  
-70  
-75  
-75  
-80  
-80  
-85  
-85  
-90  
-90  
Dashed lines: 2nd Harmonic  
Solid lines: 3rd Harmonic  
Dashed lines: 2nd Harmonic  
Solid lines: 3rd Harmonic  
-95  
-95  
-100  
-105  
-110  
-100  
-105  
-110  
Gain = -6 dB  
Gain = +10 dB  
Gain = +20 dB  
Gain = -6 dB  
Gain = +10 dB  
Gain = +20 dB  
Gain = 0 dB  
Gain = 0 dB  
0
50  
100  
150  
200  
250  
300  
0
50  
100  
150  
200  
250  
300  
Frequency (MHz)  
Frequency (MHz)  
Figure 27.  
Figure 28.  
HARMONIC DISTORTION vs FREQUENCY  
(VOUT = 3 VPP  
HARMONIC DISTORTION vs FREQUENCY  
(VOUT = 3 VPP  
)
)
-55  
-60  
-40  
-45  
-50  
-55  
-60  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
-55  
-60  
-40  
-45  
-50  
-55  
-60  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
VOUT = 3 VPP  
VOUT = 3 VPP  
RL = 500 W  
RL = 1 kW  
-65  
-65  
-70  
-70  
-75  
-75  
-80  
-80  
-85  
-85  
-90  
-90  
Dashed lines: 2nd Harmonic  
Solid lines: 3rd Harmonic  
Dashed lines: 2nd Harmonic  
Solid lines: 3rd Harmonic  
-95  
-95  
-100  
-105  
-110  
-100  
-105  
-110  
Gain = -6 dB  
Gain = +10 dB  
Gain = +20 dB  
Gain = -6 dB  
Gain = +10 dB  
Gain = +20 dB  
Gain = 0 dB  
Gain = 0 dB  
0
50  
100  
150  
200  
250  
300  
0
50  
100  
150  
200  
250  
300  
Frequency (MHz)  
Frequency (MHz)  
Figure 29.  
Figure 30.  
Copyright © 2009, Texas Instruments Incorporated  
11  
Product Folder Link(s): PGA870  
PGA870  
SBOS436 –DECEMBER 2009  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and  
output common-mode at internal midsupply reference, unless otherwise noted.  
NOISE FIGURE vs GAIN  
DISABLE STEP RESPONSE  
45  
40  
35  
30  
25  
20  
15  
10  
2.25  
2.00  
1.75  
1.50  
1.25  
1.00  
0.75  
0.50  
0.25  
0
1.5  
f = 100 MHz  
RSYS = 150 W  
Disable Signal  
1.2  
0.9  
0.6  
0.3  
0
-0.3  
-0.6  
-0.9  
-1.2  
-1.5  
Amplifier Output  
-0.25  
100  
200  
300  
400  
500  
-12-10 -8 -6 -4 -2  
0
2
4
6
8 10 12 14 16 18 20 22  
Time (ns)  
Gain (dB)  
Figure 31.  
Figure 32.  
LARGE- AND SMALL-SIGNAL  
DIFFERENTIAL PULSE RESPONSE  
FORWARD ISOLATION vs FREQUENCY  
IN DISABLED MODE  
1.5  
1.0  
0.15  
0.10  
0.05  
0
-60  
Gain = 20 dB, RL = 200 W  
-80  
-100  
-120  
-140  
0.5  
0
-0.5  
-1.0  
-1.5  
-0.05  
-0.10  
-0.15  
Left Scale  
Right Scale  
10  
0
5
15  
20  
25  
0
100  
200  
300  
400  
500  
Time (2.5 ns/div)  
Frequency (MHz)  
Figure 33.  
Figure 34.  
DIFFERENTIAL INPUT RETURN LOSS  
vs FREQUENCY  
DIFFERENTIAL INPUT IMPEDANCE  
0
-10  
-20  
-30  
-40  
-50  
-60  
160  
150  
140  
130  
120  
110  
100  
4
ZSYS = 150 W  
Magnitude  
0
-4  
-8  
-12  
-16  
-20  
Phase  
20 dB  
10 dB  
0 dB  
-6 dB  
100 k  
1 M  
10 M  
100 M  
1 G  
100 M  
1 G  
Frequency (Hz)  
Frequency (Hz)  
Figure 35.  
Figure 36.  
12  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): PGA870  
PGA870  
www.ti.com  
SBOS436 –DECEMBER 2009  
TYPICAL CHARACTERISTICS (continued)  
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and  
output common-mode at internal midsupply reference, unless otherwise noted.  
SINGLE-ENDED INPUT RETURN LOSS  
vs FREQUENCY  
DIFFERENTIAL OUTPUT IMPEDANCE  
100  
10  
1
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0
-5  
ZSYS = 150 W  
Phase  
-10  
-15  
-20  
-25  
-30  
-35  
20 dB  
10 dB  
0 dB  
Magnitude  
-6 dB  
0.1  
10 k  
100 k  
1 M  
10 M  
100 M 300 M  
10 M  
100 M  
1 G  
Frequency (Hz)  
Frequency (Hz)  
Figure 37.  
Figure 38.  
DIFFERENTIAL OUTPUT SWING  
vs RLOAD  
PSRR AND CMRR  
vs FREQUENCY  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
5.5  
5.0  
4.5  
4.0  
3.5  
PSRR  
CMRR  
1 k  
10 k  
100 k  
1 M  
10 M  
100 M  
1 G  
100  
1 k  
10 k  
Frequency (Hz)  
Differential Load Resistance, RLOAD (W)  
Figure 39.  
Figure 40.  
Copyright © 2009, Texas Instruments Incorporated  
13  
Product Folder Link(s): PGA870  
PGA870  
SBOS436 –DECEMBER 2009  
www.ti.com  
APPLICATION INFORMATION  
Device Operation  
The PGA870 is a wideband, fully differential, programmable-gain amplifier. Looking at the block diagram in  
Figure 41, the PGA870 can be separated into the following functional blocks:  
•
•
•
•
•
Input Attenuator  
Buffered MUX  
Output Amplifier  
8-bit digital interface  
Power function  
Attenuator  
1
2
IN-  
VS  
Gain = +20 dB  
OUT-  
Output  
Amp  
Buffered  
MUX  
VMID2  
OUT+  
7
8
IN+  
BIAS  
Control  
Gain Control  
PGA870  
Gain Latch  
B0 B1 B2 B3 B4 B5  
Strobe Mode (LSB)  
(MSB)  
Disable  
Figure 41. PGA870 Block Diagram  
Input Attenuator  
The input stage of the PGA870 consists of a logarithmic R2R ladder and presents a 150-Ω load to the previous  
stage. To minimize input return loss and noise figure, it is recommended to provide a 150-Ω matching for that  
input. This input can be driven either differentially or single-ended.  
This resistive input network is internally biased to midsupply by an internal buffer (VMID2 on pin 4). Proper  
bypassing is required on this node (0.1 μF). The buffer midsupply is generated by a passive resistor network  
(VMID1 on pin 28). A 0.1-μF capacitor is expected on VMID1 for adequate bypassing. Although VMID1 and VMID2 are  
externally accessible, neither of these pins is intended to be externally driven. Additionally, VMID2 is not intended  
to drive the midsupply reference to another chip, but can source approximately 200 μA if required.  
During power-down operation, the input maintains its nominal differential resistance. However, VMD1 and VMID2  
fall to 0 V.  
The input attenuator is controlled via the three most significant bits (MSBs) of the gain control. Refer to Table 1  
for the step size of each of these three MSBs.  
Input Amplifier and Buffered MUX  
Following the input attenuator is a programmable buffer stage; the gain of the programmable buffer is controlled  
by the three least significant bits (LSBs) of the gain-control word. Refer to Table 1 for the step size of each of  
these three LSBs.  
14  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): PGA870  
 
PGA870  
www.ti.com  
SBOS436 –DECEMBER 2009  
Table 1. Gain Bits and Corresponding Gain Step Sizes (in dB)  
(MSB)  
B5  
(LSB)  
B0  
B4  
B3  
B2  
B1  
16  
8
4
2
1
0.5  
Output Amplifier  
The PGA870 has a differential, voltage-mode output stage with a differential output resistance of approximately  
0.3 Ω and an inductive reactance equivalent to 3.8 nH. The common-mode output voltage has a nominal value of  
VMID2. This output amplifier has a nominal gain of +20 dB.  
The nominal load is 200 Ω, but the PGA870 can drive loads as low as 100 Ω with only minor changes to the  
device distortion.  
The output pins go to a high-impedance state when the device is the power-down state (that is, when PD is low).  
8-bit Digital Interface  
The 8-bit digital interface is composed of six bits: three MSBs that control the input attenuation and three LSBs  
that control the input amplifier and buffered MUX. For more information on this parallel interface, refer to the Gain  
Control and Latch Modes section.  
Power function  
The PGA870 features a low-power disabled state for the analog circuitry when the power-down (PD) pin is low.  
In the disabled state, the digital circuitry remains active, which allows the gain to be set before device power-up.  
There is no internal circuitry to provide a nominal bias to this pin. If this pin is to be left open, it must be biased  
with an external pull-up resistor.  
Note that when the PGA870 is in this low-power mode, the gain can be programmed using the 8-bit digital  
interface, the output pins go to a high-impedance state, and the voltage on the midsupply pins biasing the  
attenuator (pin 4 and pin 28) goes to 0 V.  
Gain Control and Latch Modes  
The PGA870 has six bits of gain control (B5 to B0) that give an extended gain range from a maximum gain of 20  
dB to a minimum gain of –11.5 dB. The LSB (B0) represents a minimum gain change (step size) of 0.5 dB, and  
the LSB (B5) represents a gain change of 16 dB. The equivalent gain step size of each gain control bit is shown  
in Table 1. The device voltage gain can be expressed by the following equation:  
GaindB= 20 dB − 0.5 dB × (NG− 63)  
NG is the equivalent base-10 integer number that corresponds to the binary gain control word. A summary of the  
63 possible device gains versus NG and the values of B0 to B5 are shown in Table 2.  
The high and low voltage thresholds allow all of the gain control pins to be controlled by CMOS circuitry. There  
are no internal pull-up resistors on the gain-control pins. If the pins are to be left open, they must be biased with  
external pull-up resistors.  
The PGA870 can be configured so the device gain is controlled by only the six gain bits (no latch) when the  
GAIN STROBE pin and the GAIN MODE pin are both held high. In this operating mode, the device voltage gain  
follows the signals on pins B0 to B5. Transients on the six gain bits can cause changes to the PGA870 gain  
while in this mode, as well. To combat this possibility, the PGA870 also supports two gain modes where the gain  
bit data are acquired and latched by signals on the GAIN STROBE pin.  
The device is configured for a level-triggered latch when the LATCH MODE pin is high; this configuration allows  
the six gain bits to be acquired and latched only on a high signal on the GAIN STROBE. When the GAIN  
STROBE signal goes low, the gain-control data are latched and the PGA870 gain is independent of the six gain  
bits until the GAIN STROBE goes high again.  
If the PGA870 LATCH MODE pin is low, the device is configured for an edge-triggered latch that acquires and  
latches the six gain-control bits only on the falling edge of the GAIN STROBE signal.  
Copyright © 2009, Texas Instruments Incorporated  
15  
Product Folder Link(s): PGA870  
 
 
PGA870  
SBOS436 –DECEMBER 2009  
www.ti.com  
Table 2. PGA870 Gain and Corresponding Gain Word Values  
Gain  
Gain  
State  
NG  
Gain  
(dB)  
(MSB)  
B5  
(LSB)  
B0  
State  
NG  
Gain  
(dB)  
(MSB)  
B5  
(LSB)  
B0  
B4  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
B2  
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
B1  
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
B4  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
B2  
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
B1  
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
20  
19.5  
19  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
4
3.5  
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
18.5  
18  
2.5  
2
17.5  
17  
1.5  
1
16.5  
16  
0.5  
0
15.5  
15  
-0.5  
-1  
14.5  
14  
-1.5  
-2  
13.5  
13  
-2.5  
-3  
12.5  
12  
-3.5  
-4  
11.5  
11  
-4.5  
-5  
10.5  
10  
-5.5  
-6  
9.5  
9
-6.5  
-7  
8.5  
8
8
-7.5  
-8  
7
7.5  
7
6
-8.5  
-9  
5
6.5  
6
4
-9.5  
-10  
-10.5  
-11  
-11.5  
3
5.5  
5
2
1
4.5  
0
Table 3. Gain Control Signals and Latch Modes  
Latch Mode  
GAIN STROBE  
LATCH MODE  
CONDITION  
Device gain follows and latches gain control word (B0  
to B5) only on GAIN STROBE falling edge.  
Edge-triggered latch  
Falling edge  
Low  
Device gain follows gain control word (B0 to B5) when  
GAIN STROBE and LATCH MODE are both high.  
Device gain latches when GAIN STROBE goes low.  
Level-triggered latch  
Low  
High  
High  
Device gain is level-triggered on the gain-control word  
(B0 to B5) when LATCH MODE is high and GAIN  
STROBE remains high.  
No latch  
High  
16  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): PGA870  
 
PGA870  
www.ti.com  
SBOS436 –DECEMBER 2009  
Table 3 and Figure 42 show a summary table and timing diagrams of the gain modes, respectively. Figure 43  
illustrates a timing diagram that defines the transitions and timing of the set-up and hold times for both  
level-triggered and edge-triggered latch modes.  
Latched on  
Gain Strobe  
Falling Edge  
Latched on  
Gain Strobe  
High Level  
No Latch  
Follows  
Gain Control Word  
1
Gain Strobe  
Latch Mode  
0
1
0
1
Gain Bits  
B5 to B0  
(MSB to LSB)  
0
1
0
Gain  
Figure 42. Gain Mode Timing  
1
Gain Bits  
B5 to B0  
(MSB to LSB)  
0
tSU  
tHOLD  
1
Gain Strobe  
0
1
tLATENCY  
Gain  
0
1
Latch Mode  
0
Figure 43. Set-Up and Hold Times: Level-Triggered and Edge-Triggered Latch Modes  
Copyright © 2009, Texas Instruments Incorporated  
17  
Product Folder Link(s): PGA870  
 
 
PGA870  
SBOS436 –DECEMBER 2009  
www.ti.com  
Single-Ended to Differential Operation  
Figure 44 represents a single-ended to differential conversion test configuration with a 50-Ω source and a 200-Ω  
load. The midsupply pins VMID1 and VMID2 are properly bypassed; because this circuit is ac-coupled, these pins  
provide the biasing voltage required by the PGA870 input stage. The LATCH MODE, GAIN STROBE, and PD  
pins are connected to the supply voltage through a pull-up resistor. The PD pin set high powers up the PGA870,  
while setting the LATCH MODE and GAIN STROBE pins high bypasses the latch mode, allowing instantaneous  
gain changes as B5 to B0 change. On the noninverting input, a 75-Ω resistance was added to adapt the 150 Ω to  
50 Ω and match the 50-Ω source.  
If a differential signal source is to be dc-coupled to the device, it should have a common-mode voltage that is  
within 0.2 V of the midsupply reference. If the input common-mode/dc voltage is greater than 0.2 V from  
midsupply, then increased distortion and reduced performance can result. The non-driven input pin of the  
PGA870 should be ac-coupled to ground through a capacitor. If a single-ended signal source is dc-coupled to an  
input pin, and the non-driven input pin is grounded, the PGA870 amplifies the desired signal as well as the  
difference between the offset from the PGA870 midsupply reference, VMID1  
.
+5 V  
1k W  
From 50-W  
Source  
0.1 mF  
IN+  
LM(1)  
GS(1)  
75 W  
PD  
VMID2  
OUT+  
0.1 mF  
200 W  
PGA870  
VMID1  
0.1 mF  
0.1 mF  
OUT-  
B0 to B5  
IN-  
B0 to B5  
(1) LM = LATCH MODE pin (pin 1), GS = GAIN STROBE pin (pin 7).  
Figure 44. Basic Connections for Single-Ended to Differential Conversion  
18  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): PGA870  
 
PGA870  
www.ti.com  
SBOS436 –DECEMBER 2009  
Differential-to-Differential Operation  
Differential operation of PGA870 is shown in Figure 45. In this example, both input pins are connected to a  
differential 150-Ω source. The PGA870 is driving a typical 200-Ω load. Both midsupply voltage pins VMID1 and  
VMID2 are bypassed with a 0.1-μF capacitor. The LATCH MODE, GAIN STROBE, and PD pins are connected to  
the power supply using a 1-kΩ pull-up resistor. The PD pin set high powers up the PGA870, while setting the  
Latch Mode and the Gain Strobe pins high bypasses the latch mode, allowing instantaneous gain changes as B5  
to B0 change.  
+5 V  
1k W  
From 150-W  
Differential Source  
0.1 mF  
IN+  
LM(1)  
GS(1)  
PD  
VMID2  
OUT+  
0.1 mF  
0.1 mF  
200 W  
PGA870  
VMID1  
OUT-  
B0 to B5  
IN-  
0.1 mF  
B0 to B5  
(1) LM = LATCH MODE pin (pin 1), GS = GAIN STROBE pin (pin 7).  
Figure 45. Basic Connections for Fully Differential Operation  
PCB Layout Recommendations  
Complete information about the PGA870EVM is found in the PGA870EVM User Guide, available for download  
through the PGA870 product folder on the TI web site. Printed circuit board (PCB) layout should follow these  
general guidelines:  
1. Signal routing should be direct and as short as possible into and out of the device input and output pins.  
Routing the signal path between layers using vias should be avoided if possible.  
2. The device PowerPAD should be connected to a solid ground plane with multiple vias. The PowerPAD must  
be connected to electrical ground. Consult the PGA870EVM User Guide for a layout example.  
3. Ground or power planes should be removed from directly under the amplifier output pins.  
4. A 0.1-μF capacitor should be placed between the VMIDpin and ground near to the pin.  
5. An output resistor is recommended in each output lead, placed as near to the output pins as possible.  
6. Two 0.1-μF power-supply decoupling capacitors should be placed as near to the power-supply pins as  
possible.  
7. Two 10-μF power-supply decoupling capacitors should be placed within 1 in (2,54 cm) of the device.  
8. The digital control pins use CMOS logic levels for high and low signals, but can tolerate being pulled high to  
a +5-V power supply. The digital control pins do not have internal pull-up resistors.  
Copyright © 2009, Texas Instruments Incorporated  
19  
Product Folder Link(s): PGA870  
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Dec-2009  
PACKAGING INFORMATION  
Orderable Device  
PGA870IRHDR  
PGA870IRHDT  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
VQFN  
RHD  
28  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
VQFN  
RHD  
28  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
20-Jul-2010  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
PGA870IRHDR  
PGA870IRHDT  
VQFN  
VQFN  
RHD  
RHD  
28  
28  
3000  
250  
330.0  
180.0  
12.4  
12.4  
5.3  
5.3  
5.3  
5.3  
1.5  
1.5  
8.0  
8.0  
12.0  
12.0  
Q2  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
20-Jul-2010  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
PGA870IRHDR  
PGA870IRHDT  
VQFN  
VQFN  
RHD  
RHD  
28  
28  
3000  
250  
346.0  
190.5  
346.0  
212.7  
29.0  
31.8  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are  
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where  
mandated by government requirements, testing of all parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,  
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information  
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a  
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual  
property of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied  
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive  
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional  
restrictions.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all  
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not  
responsible or liable for any such statements.  
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably  
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing  
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and  
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products  
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be  
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in  
such safety-critical applications.  
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are  
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military  
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at  
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.  
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are  
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated  
products in automotive applications, TI will not be responsible for any failure to meet such requirements.  
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
www.ti.com/audio  
Data Converters  
DLP® Products  
Automotive  
www.ti.com/automotive  
www.ti.com/communications  
Communications and  
Telecom  
DSP  
dsp.ti.com  
Computers and  
Peripherals  
www.ti.com/computers  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
Consumer Electronics  
Energy  
www.ti.com/consumer-apps  
www.ti.com/energy  
Logic  
Industrial  
www.ti.com/industrial  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Medical  
www.ti.com/medical  
microcontroller.ti.com  
www.ti-rfid.com  
Security  
www.ti.com/security  
Space, Avionics &  
Defense  
www.ti.com/space-avionics-defense  
RF/IF and ZigBee® Solutions www.ti.com/lprf  
Video and Imaging  
Wireless  
www.ti.com/video  
www.ti.com/wireless-apps  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2010, Texas Instruments Incorporated  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明