PLL1700 [TI]
MULTI-CLOCK GENERATOR;
| 型号： | PLL1700 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MULTI-CLOCK GENERATOR |
| 文件： | 总15页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL1700
P
L
®
L
1
7
0
0
49%
FPO
SBOS096A – JANUARY 1998 – REVISED MAY 2007
MULTI-CLOCK GENERATOR
FEATURES
● 27MHz MASTER CLOCK INPUT
DESCRIPTION
The PLL1700 is a low cost, multi-clock generator Phase
Lock Loop (PLL).
● GENERATED AUDIO SYSTEM CLOCK:
SCKO1: 33.8688MHz (Fixed)
SCKO2: 256fS
The PLL1700 can generate four systems clocks from a
27MHz reference input frequency.
SCKO3: 384fS
SCKO4: 768fS
The device gives customers both cost and space savings
by eliminating external components and enables custom-
ers to achieve the very low jitter performance needed for
high-performance audio digital-to-analog converters
(DACs) and/or analog-to-digital converters (ADCs).
● ZERO PPM ERROR OUTPUT CLOCKS
● LOW CLOCK JITTER: 150ps at SCKO3
● MULTIPLE SAMPLING FREQUENCIES:
fS = 32kHz, 44.1kHz, 48kHz, 64kHz,
88.2kHz, 96kHz
The PLL1700 is ideal for MPEG-2 applications that use a
27MHz master clock such as DVD players, DVD add-on
cards for multimedia PCs, digital HDTV systems, and set-
top boxes.
● +3.3V CMOS LOGIC INTERFACE
● DUAL POWER SUPPLIES: +5V and +3.3V
● SMALL PACKAGE: 20-Lead SSOP
MODE
ML
MC
MD
VDDP GNDP VDDB GNDB VDD GND
Power Supply
Mode
Control
I/F
Reset
OSC
RST
PLL2
XT1
XT2
PLL1
Counter P
SCKO3
Counter Q
SCKO2
MCKO MCKO
SCKO4
SCKO1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998-2007, Texas Instruments Incorporated
www.ti.com
PIN CONFIGURATION
ELECTROSTATIC
TOP VIEW
SSOP
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to ob-
serve proper handling and installation procedures can
cause damage.
ML/SR0
MODE
VDD
1
2
3
4
5
6
7
8
9
20 MC/FS1
19 MD/FS0
18 RST
GND
XT2
17 SCKO3
16 VDDB
ESD damage can range from subtle performance deg-
radation to complete device failure. Precision integrated
circuits may be more susceptible to damage because
very small parametric changes could cause the device
not to meet its published specifications.
PLL1700E
XT1
15 GNDB
14 SCKO2
13 SCKO4
12 SCKO1
11 MCKO
GNDP
VDDP
RSV
ABSOLUTE MAXIMUM RATINGS(1)
MCKO 10
Supply Voltage (+VDD, +VDDP, +VDDB) .............................................. +6.5V
Supply Voltage Differences (+VDD, +VDDP) ....................................... ±0.1V
GND Voltage Differences: GND, GNDP, GNDB ............................... ±0.1V
Digital Input Voltage ................................................. –0.3V to (VDD + 0.3V)
Digital Output Voltage ............................................ –0.3V to (VDDB + 0.3V)
Input Current (any pins except supply pins) ................................... ±10mA
Power Dissipation .......................................................................... 300mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s).................................................. +260°C
Package Temperature (IR reflow, 10s) .......................................... +235°C
PIN ASSIGNMENTS
PIN NAME
I/O
FUNCTION
1
ML/SR0
IN
Latch Enable for Software Mode/Sampling Rate
Selection for Hardware Mode. When MODE pin
is LOW, ML is selected.(1)
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
2
MODE
IN
Mode Control Select. When this pin is HIGH,
device is operated in hardware mode using SR0
(pin 1), FS0 (pin 19), and FS1 (pin 20). When
this pin is LOW, device is operated in software
mode by three-wire interface using ML (pin 1),
MD (pin 19) and MC (pin 20).(1)
PACKAGE INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
3
4
5
VDD
GND
XT2
—
—
—
Digital Power Supply, +5V.
Digital Ground.
PACKAGE
DESIGNATOR
PRODUCT
PACKAGE
27MHz Crystal. When an external 27MHz clock
is applied to XT1 (pin 6), this pin must be
connected to GND.
PLL1700E
20-Lead SSOP
–25°C to +85°C
DB
NOTE: (1) For the most current package and ordering information, see the
Package Option Addendum at the end of this data sheet, or see the TI web
site at www.ti.com.
6
7
XT1
GNDP
VDDP
IN
—
27MHz Oscillator Input/External 27MHz Input.
Ground for PLL.
8
—
Power Supply for PLL, +5V.
Reserved. Must be left open.
27MHz Output.
9
RSV
—
10
11
MCKO
MCKO
OUT
OUT
OUT
OUT
OUT
—
Inverted 27MHz Output.
Fixed 33.8688MHz Clock Output.
768fS Clock Output.
12 SCKO1
13 SCKO4
14 SCKO2
256fS Clock Output.
15
16
GNDB
VDDB
Digital Ground for VDDB.
—
Digital Power Supply for Clock Output Buffers,
+3.3V.
17 SCKO3
OUT
384fS Output. This output has been optimized
for the lowest jitter and should be connected to
the audio DAC(s).
18
RST
IN
IN
Reset. When this pin is LOW, device is held in
reset.(1)
19 MD/FS0
20 MC/FS1
Serial Data Input for Software Mode/Sampling
Frequency Selection for Hardware Mode. When
MODE pin is LOW, MD is selected.(1)
IN
Shift Clock Input for Software Mode/Sampling
Frequency Selection for Hardware Mode. When
MODE pin is LOW, MC is selected.(1)
NOTE: (1) Schmitt-trigger input with internal pull-down resistors.
PLL1700
2
SBOS096A
www.ti.com
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, VDD = VDDP = +5V, VDDB = +3.3V, fM = 27MHz crystal oscillation, and fS = 48kHz, unless otherwise noted.
PLL1700E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUT/OUTPUT
Input Logic Level:
TTL-Compatible
(1)
VIH
2.0
1.2
VDC
VDC
VDC
VDC
(1)
VIL
0.8
0.4
(2)
VIH
(2)
VIL
Input Logic Current:
(1)
IIH
VIN = VDD
VIN = 0V
VIN = VDD
VIN = 0V
200
–1
µA
µA
mA
µA
(1)
IIL
(2)
IIH
4
(2)
IIL
–800
Output Logic Level:
CMOS
(3)
VOH
IOH = 4mA
IOL = 4mA
Standard fS
Double fS
VDDB – 0.4V
VDC
VDC
kHz
(3)
VOL
0.4
48
96
Sampling Frequency (fS)
32
64
44.1
88.2
kHz
MASTER CLOCK (MCKO, MCKO)
Master Clock Frequency
Clock Jitter(4)
fM = 27MHz, CL = 20pF
26.73
27
300
50
27.27
MHz
ps
%
Clock Duty Cycle
MCKO
C1 = C2 = 15pF
40
40
60
60
For Crystal Oscillation MCKO
50
%
Clock Duty Cycle
For External Clock
MCKO
MCKO
40
%
60
%
PHASE LOCK LOOP (PLL)
Generated System Clock Frequency
SCKO1
fM = 27MHz, CL = 20pF
Fixed
256fS
33.8688
MHz
MHz
MHz
MHz
ns
SCKO2
8.192
12.288
24.576
24.576
36.864
36.864
SCKO3
384fS
SCKO4
768fS
Generated Clock Rise Time(3)
Generated Clock Fall Time(3)
Generated Clock Duty Cycle
20% to 80% VDDB
80% to 20% VDDB
SCKO1, SCKO3, SCKO4
SCKO2 (standard)
SCKO2 (double)(5)
SCKO1, SCKO2 (standard), SCKO4
SCKO3
5
5
ns
40
40
25
50
60
60
40
%
50
%
33
%
Generated Clock Jitter(4)
300
150
450
ps
ps
SCKO2 (double)
To Programmed Frequency
To Programmed Frequency
ps
Settling Time
20
30
ms
ms
Power-Up Time
15
POWER SUPPLY REQUIREMENTS
Voltage Range
VDD, VDDP
VDDB
+4.5
+2.7
+5
+5.5
+3.6
VDC
VDC
+3.3
Supply Current(6)
IDD + IDDP
IDDB
:
VDD = VDDP = 5V, fS = 48kHz
VDDB = +3.3V, fS = 48kHz
fS = 48kHz
11
6
16
9
mA
mA
mW
Power Dissipation
75
110
TEMPERATURE RANGE
Operation
–25
–55
+85
°C
°C
Storage
+125
NOTES: (1) ML, MC, MD, MODE, RST (Schmitt-trigger input with internal pull-down resistor).
(2) XT1, when an external 27MHz clock is used, the buffer ICs, such as 74HC04, are recommended to interface to XT1.
(3) MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.
(4) Jitter performance is specified as standard deviation of jitter under 27MHz crystal oscillation.
(5) When SCKO2 is set to double rate clock output, its duty cycle is 33%.
(6) fM = 27MHz crystal oscillation, no load on MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.
PLL1700
SBOS096A
3
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VDD = VDDP = +5V, VDDB = +3.3V, CL = 20pF, unless otherwise noted.
JITTER vs SAMPLING FREQUENCY
400
SCKO3 JITTER vs TEMPERATURE
300
200
100
0
SCKO1
300
32kHz
96kHz
200
MCKO
48kHz
100
SCKO3
0
32
44.1 48
Sampling Frequency, fS (kHz)
96
–25
+25
+85
Temperature (°C)
DUTY CYCLE RATIO vs SAMPLING FREQUENCY
SCKO3 JITTER vs VDDB
70
60
50
40
30
300
200
100
0
32kHz
SCKO3
MCKO (XTAL Operation)
MCKO (External Clock)
96kHz
48kHz
32
44.1 48
Sampling Frequency, fS (kHz)
96
2.7
3.3
3.6
VDDB (V)
PLL1700
4
SBOS096A
www.ti.com
oscillator placed between XT1 (pin 6) and XT2 (pin 5), or
an external input to XT1. If an external master clock is
used, XT2 must be connected to ground. In both cases,
the signal amplitude on XT1 must satisfy the specification
described in Figure 3. Therefore, careful C1 and C2
determination is required for keeping this specification
when using a crystal oscillator.
Figure 2 illustrates possible system clock connection
options. Figure 3 illustrates the 27MHz master clock
timing requirements.
THEORY OF OPERATION
MASTER CLOCK AND SYSTEM CLOCK OUTPUT
The PLL1700 consists of a dual PLL clock and master
clock generator which generates four system clocks and
two buffered 27MHz clocks from a 27MHz master clock.
Figure 1 shows the block diagram of the PLL1700. The
PLL is designed to accept a 27MHz master clock or
crystal oscillator. The master clock can be either a crystal
SCKO2
256fS
Frequency Control
PLL2
Counter N
Phase Detector
and
Loop Filter
Data
ROM
VCO
Counter Q
Counter M
PLL1
Counter P
Counter M
Counter N
Phase Detector
and
Loop Filter
OSC
VCO
SCKO1
33.8688MHz
SCKO4
768fS
SCKO3
384fS
XT2 XT1 MCKO MCKO
27MHz
FIGURE 1. Block Diagram of PLL1700.
MCKO
MCKO
Buffer
Buffer
Buffer
MCKO
MCKO
Buffer
C1
Xtal
XTI
XT1
XT2
27MHz Internal
Master Clock
27MHz Internal
Master Clock
External Clock
Crystal
OSC
Circuit
Crystal
OSC
Circuit
C2
XT2
C1, C2 = 10pF to 33pF
PLL1700
Crystal Resonator Connection
PLL1700
External Clock Input
FIGURE 2. Master Clock Generator Connection Diagram.
tXT1H
DESCRIPTION
SYMBOL MIN TYP MAX UNITS
1.2V
XT1
System Clock Pulse Width HIGH
System Clock Pulse Width LOW
tXT1H
tXT1L
10
15
ns
ns
0.4V
tXT1L
FIGURE 3. External Master Clock Timing Requirement.
PLL1700
SBOS096A
5
www.ti.com
The PLL1700 provides a very low jitter, high accuracy
clock. SCKO1 is a fixed frequency clock which is
33.8688MHz (768 x 44.1kHz) for a CD-DA DSP. The
output frequency of the remaining clocks is determined by
the sampling frequency (fS) by software or hardware
control. SCKO2 and SCKO3 output 256fS and 384fS
systems clocks, respectively. SCKO4 output is 768fS if the
sampling frequency is 32kHz, 44.1kHz, 48kHz, or the
output is 384fS if the sampling frequency is 64kHz, 88.2kHz,
or 96kHz. Table I shows each sampling frequency. The
system clock output frequencies are generated by a
27MHz master clock and programmed sampling frequen-
cies are shown in Table II.
FUNCTION CONTROL
The built-in function of the PLL1700 can be controlled in
the software mode (serial mode), which uses a three-wire
interface by ML (pin 1), MC (pin 20), and MD (pin 19), when
MODE (pin 2) = L. They can also be controlled in the
hardware mode (parallel mode) which uses SR0 (pin 1),
FS1 (pin 20) and FS0 (pin 19), when MODE (pin 2) = H.
The selectable functions are shown in Table III.
HARDWARE SOFTWARE
MODE
MODE
(MODE = L)
FUNCTION
(MODE = H)
Sampling Frequency Select
(32kHz, 44.1kHz, 48kHz)
Yes
Yes
No
Yes
Yes
Yes
Sampling Rate Select (Standard/Double)
Each Clock Output Enable/Disable
SAMPLING
SAMPLING RATE
FREQUENCY (kHz)
Standard Sampling Frequencies
32
64
44.1
88.2
48
TABLE III. Selectable Functions.
Double of Standard Sampling Frequencies
96
TABLE I. Sampling Frequencies.
HARDWARE MODE (MODE = H)
In the hardware mode, the following functions can be
selected:
SAMPLING
Sampling Group Select
FREQUENCY
(kHz)
SAMPLING
RATE
SKCO2
(MHz)
SCKO3
(MHz)
SCKO4
(MHz)
The sampling frequency group can be selected by FS1
(pin 20) and FS0 (pin 19). This selection must be made
with an interval time greater than 20µs.
32
44.1
48
Standard
Standard
Standard
8.192
11.2896
12.288
12.288
24.576
33.8688
36.8640
16.9344
18.4320
64
88.2
96
Double
Double
Double
16.384
22.5792
24.576
24.576
33.8688
36.8640
24.576
33.8688
36.8640
FS1 (Pin 20)
FS0 (Pin 19)
SAMPLING GROUP
L
L
L
H
L
48kHz
44.1kHz
32kHz
H
H
TABLE II. Sampling Frequencies and Master Clock
Output Frequencies.
H
Reserved
Response time from power-on (or applying the clock to
XT1) to SCKO settling time is typically 15ms. Delay time
from sampling frequency change to SCKO settling time is
20ms maximum. Figure 4 illustrates SCKO transient
timing.
External buffers are recommended on all output clocks in
order to avoid degrading the jitter performance of the
PLL1700.
Sampling Rate Select
The sampling rate can be selected by SR0 (pin 1).
SR0 (Pin 1)
SAMPLING RATE SELECT
L
Standard
Double
H
SOFTWARE MODE (MODE = L)
RESET
The PLL1700 special function in software mode is shown
in Table IV. These functions are controlled using ML, MC,
and MD serial control signal.
The PLL1700 has an internal power-on reset circuit, as
well as an external forced reset (RST, pin 18). Both resets
have the same effect on the PLL1700 functions. The
mode register default settings for software mode are
initialized by reset. Throughout the reset period, all clock
outputs are enabled with the default settings. Initialization
for the internal power-on reset is done automatically
during 1024 master clocks at VDD ≥ 2.2V (1.8V to 2.6V).
When using the internal power-on reset, RST should be
HIGH. Power-on reset timing is shown in Figure 5. RST
(pin 18) accepts an external forced reset by RST = L.
Initialization (reset) is done when RST = L and 1024
master clocks after RST = H. External reset timing is
shown in Figures 6 and 7.
FUNCTION
DEFAULT
Sampling Frequency Select (32kHz, 44.1kHz, 48kHz)
Sampling Rate Select (Standard/Double)
Each Clock Output Enable/Disable
48kHz Group
Standard
Enable
TABLE IV. Selectable Functions.
PLL1700
6
SBOS096A
www.ti.com
ML
20ms
3 clocks of MCKO
Stable
SCKO2
SCKO3
SCKO4
Clock Transistion Region
Stable
SCKO1
33.8688MHz
FIGURE 4. System Clock Transient Timing Chart.
2.6V
2.2V
1.8V
VDD
Reset
Reset Removal
Internal Reset
Master Clock
1024 System Clock Periods
FIGURE 5. Power-On Reset Timing.
RST
tRST
Reset
Reset Removal
Internal Reset
Master Clock
1024 System Clock Periods
FIGURE 6. External Reset Timing.
RST
1.4V
tRST
System Clock Pulse Width LOW
tRST
20ns
(min)
FIGURE 7. Reset Pulse Timing Requirement.
PLL1700
SBOS096A
7
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PROGRAM REGISTER BIT-MAPPING
Mode Register
The built-in functions of the PLL1700 are controlled through
a 16-bit program register. This register is loaded using
MD. After the 16 data bits are clocked in using the rising
edge of MC, ML is used to latch the data into the register.
Table V shows the bit-mapping of the registers. The
software mode control format and control data input
timing is shown in Figures 8 and 9, respectively.
FS [1:0]: Sampling Frequency Group Select. This se-
lection must be made with an interval time
greater than 20µs.
FS1
FS0
SAMPLING FREQUENCY
DEFAULT
0
0
1
1
0
1
0
1
48kHz
44.1kHz
32kHz
O
Reserved
Mode Register
D15 D14 D13 D12 D11 D0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
SR [1:0]: Sample Rate Select
0
1
1
1
0
0
CE6 CE5 CE4 CE3 CE2 CE1 SR1 SR0 FS1 FS0
SR1
SR0
SAMPLING RATE
DEFAULT
0
0
1
1
0
1
0
1
Standard
Double
Reserved
Reserved
O
REGISTER
BIT NAME
DESCRIPTION
MODE
CE6
CE5
CE4
CE3
CE2
CE1
SR [1:0]
FS [1:0]
MCKO Output Enable/Disable
MCKO Output Enable/Disable
SCKO4 Output Enable/Disable
SCKO3 Output Enable/Disable
SCKO2 Output Enable/Disable
SCKO1 Output Enable/Disable
Sampling Rate Select
CE [1:6]: Clock Output Control
CE1 - CE6
CLOCK OUTPUT CONTROL
DEFAULT
Sampling Frequency Select
0
1
Clock Output Disable
Clock Output Enable
O
TABLE V. Register Mapping.
ML (pin 1)
MC (pin 20)
MD (pin 19)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FIGURE 8. Software Mode Control Format.
tMLL
tMHH
ML (pin 1)
1.4V
1.4V
1.4V
tMLS
tMCH
tMCL
tMLH
tMLS
MC (pin 20)
MD (pin 19)
tMCY
MSB
LSB
tMDS
tMDH
DESCRIPTION
SYMBOL
MIN
TYP
MAX
UNITS
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Hold Time
tMCY
tMCL
tMCH
tMDH
tMDS
tMLL
tMHH
tMLH
tMLS
100
40
ns
ns
40
ns
40
ns
MD Set-Up Time
40
ns
ML Low Level Time
ML High Level Time
ML Hold Time(2)
16
MC Clocks(1)
200
40
ns
ns
ns
ML Set-Up Time(3)
40
NOTES: (1) MC clocks: MC clock period. (2) MC rising edge for LSB to ML rising edge. (3) ML rising edge
to the next MC rising edge. If the MC Clock is stopped after the LSB, any ML rising time is accepted.
FIGURE 9. Control Data Input Timing.
8
PLL1700
SBOS096A
www.ti.com
CONNECTION DIAGRAM
MPEG-2 APPLICATIONS
Figure 10 shows the typical connection circuit for the
PLL1700. There are three grounds for digital, analog and
PLL power supply. However, the use of one common
ground connection is recommended to avoid latch-up
problems. Power supplies should be bypassed as close
as possible to the device.
Typical applications for the PLL1700 are MPEG-2 based
systems such as DVD players, DVD add-on cards for
multimedia PCs, digital HDTV systems, and set-top boxes.
The PLL1700 provides audio system clocks for a CD-DA
DSP, DVD DSP, Karaoke DSP, and DAC(s) from a
27MHz video clock.
+5V
+
C1
+3.3 V
22µF to 47µF
+
C2
22µF to 47µF
PLL1700E
Mode
Control
ML/SR01
MC/FS1
MD/FS0
RST
1
2
20
19
18
17
16
15
14
13
12
11
MODE
VDD
0.1µF and 10µF(1)
3
C3
GND
XT2
SCKO3
VDDB
4
(2)
C5
0.1µF
and
5
10µF(1)
XT1
GNDB
SCKO2
SCKO4
SCKO1
MCKO
6
GNDP
VDDP
RSV
7
C4
0.1µF
8
Clock
Output(3)
and
9
10µF(1)
MCKO
10
NOTES: (1) 0.1µF ceramic and 10µF electrolytic capacitor typical, depending on quality of power supply and pattern layout.
(2) 27MHz quartz crystal and 10pF through two 33pF ceramic capacitors.
(3) To achieve best possible jitter performance, it is recommended to minimize the load capacitance on the clock output.
FIGURE 10. Typical Connection Diagram.
PLL1700
SCKO3
384fS
768fS
256fS
27MHz
SCKO4
SCKO2
MCKO
27MHz
Crystal
PCM1716
PCM1716
PCM1716
Front
SCKO1
Surround
Karaoke
DSP
Center
CD-DA/
DVD DSP
MPEG/AC-3
Audio Decoder
Subwoofer
FIGURE 11. PLL1700 System Application Block Diagram.
PLL1700
SBOS096A
9
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Revision History
DATE
REVISION PAGE
SECTION
DESCRIPTION
—
Entire Document
Updated format to current standard look.
Added note (1) to VIH and VIL.
3
Electrical Characteristics
Added two rows to Input Logic Level for VIH and VIL with note (2).
Added condition to Clock Duty Cycle row stating that C1 = C2 = 15pF.
Master Clock and
System Clock Output
Changed "X2 should be connected" to "X2 must be connected."
Added text regarding signal amplitude.
5
5/07
A
Changed voltage from 2.0V to 1.2V.
Changed voltage from 0.8V to 0.4V.
Changed tXT1H min value from 15 to 10.
5
Figure 5
6
8
Sampling Group Select
Mode Register
Added text regarding interval time.
Added text regarding interval time.
Deleted note (1) from C1 and C2.
9
Figure 10
Changed note text from "tantalum" to "electrolytic" capacitor.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PLL1700
10
SBOS096A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PLL1700E
NRND
SSOP
DB
20
65 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PLL1700E-1/2K
PLL1700E-1/2KG4
PLL1700E/2K
OBSOLETE
OBSOLETE
NRND
SSOP
SSOP
SSOP
DB
DB
DB
20
20
20
TBD
TBD
Call TI
Call TI
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PLL1700E/2KG4
PLL1700EG
NRND
NRND
NRND
NRND
NRND
NRND
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
DB
DB
DB
DB
DB
DB
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
65
Pb-Free
(RoHS)
CU SNBI
CU SNBI
CU SNBI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
PLL1700EG/2K
PLL1700EG/2KE6
PLL1700EG4
2000
2000
Pb-Free
(RoHS)
Pb-Free
(RoHS)
65 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PLL1700EGE6
65
Pb-Free
(RoHS)
CU SNBI
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
PLL1700E/2K
SSOP
SSOP
DB
DB
20
20
2000
2000
330.0
330.0
17.4
17.4
8.5
8.5
7.6
7.6
2.4
2.4
12.0
12.0
16.0
16.0
Q1
Q1
PLL1700EG/2K
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PLL1700E/2K
SSOP
SSOP
DB
DB
20
20
2000
2000
336.6
336.6
336.6
336.6
28.6
28.6
PLL1700EG/2K
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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