PLM63460AASQRYFTQ1 [TI]
采用增强型 QFN 封装的汽车类 3V 至 36V、6A、低 EMI 同步降压转换器 | RYF | 22 | -40 to 150;
| 型号： | PLM63460AASQRYFTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用增强型 QFN 封装的汽车类 3V 至 36V、6A、低 EMI 同步降压转换器 | RYF | 22 | -40 to 150 转换器 |
| 文件： | 总53页 (文件大小：2783K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM63460-Q1
ZHCSLU2A –DECEMBER 2021 –REVISED OCTOBER 2022
LM63460-Q1 具有可调开关频率、针对可靠性和低EMI 进行优化的3V 至36V、
6A 汽车类同步降压直流/直流转换器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
LM63460-Q1 属于汽车类同步降压直流/直流转换器系
列，具有卓越的效率和超低的 IQ。该器件具有集成式
高侧和低侧 MOSFET，能够在 3V 至 36V 的宽输入电
压范围内提供高达 6A 的输出电流，支持高达 42V 的
负载突降瞬变。该转换器可对压降进行软恢复，因此无
需对输出进行过冲。
– 器件温度等级1：–40°C 至+125°C 环境工作
温度范围
• 提供功能安全
– 可帮助进行功能安全系统设计的文档
• 多功能同步降压直流/直流转换器
– 3V 至36V 宽输入电压范围，可耐受高达42V 的
负载突降瞬变
– 1% 精度可调节输出电压（1V 至95% VIN）
– 150°C 最大结温
– 使用RT 引脚或SYNC 信号可在200kHz 至
2.2MHz 范围内调节频率
LM63460-Q1 集成了许多功能，可实现卓越的 EMI 性
能，包括展频频率调制、低 EMI 增强型 HotRod QFN
封装（可缓解开关节点振铃）和对称引脚排列（可实现
理想的输入电容器放置）。开关频率在 200kHz 和
2.2MHz 之间可设置，从而避免敏感频带，同时根据应
用要求优化效率或解决方案尺寸。
• 通过优化引脚排列设计和相邻引脚短路测试间隙提
高可靠性
• 进行了优化，可满足低EMI 要求
PFM 模式可在轻负载运行时进行频率折返，实现仅
7µA（典型值）的空载电流消耗和高轻负载效率。
PWM 模式和 PFM 模式之间无缝转换， 以及低
MOSFET 导通电阻和外部偏置输入，可在整个负载范
围内提供卓越的效率和热性能。该封装在关键电源引脚
之间有多个NC 引脚，从而改进了故障模式和影响分析
(FMEA) 结果。
– 具有双输入路径的增强型HotRod™ QFN 封装可
减少开关节点振铃
– 展频调频
– 轻负载时可选择FPWM 或PFM 模式
• 在整个负载范围内具有高效率
– 13.5V VIN、5V VOUT、6A、2.1MHz 时为92.5%
– 空载输入电流：3.3VOUT 时为7µA（典型值）
– 关断静态电流：0.6µA（典型值）
– 6A 负载下的典型压降为0.6V
封装信息
封装(1)
封装尺寸（标称值）
器件型号
RYF（VQFN，
22）
LM63460-Q1
3.50mm × 4.00mm
– 具有用于提升效率的外部偏置选项
• 使用LM63460-Q1 并借助WEBENCH® Power
Designer 创建定制稳压器设计方案
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 汽车信息娱乐系统与仪表组：音响主机、媒体集线
器、USB 充电器、显示屏
• 汽车ADAS 和车身电子装置
VIN = 3 V...36 V
100
95
CIN
VIN1
VIN2
CIN-HF1
10 nF
CIN-HF2
10 nF
10 F
PGND1
PGND2
BIAS
VOUT = 5 V
IOUT = 6 A
EN/SYNC
90
LO
LM63460-Q1
SW
PGOOD
0.76
CBOOT
H
COUT
85
0.1
F
2 ꢀ 47
F
RT
CBOOT
FB
VIN = 8 V
VIN = 12 V
VIN = 18 V
VCC
RRT
80
RFBT
100 k
6.04 k
GND
CVCC
RFBB
24.9 k
1
F
VIN = 24 V
* VOUT tracks VIN if VIN < 5.6 V
75
0
1
2
3
4
5
6
Output Current (A)
典型原理图
效率图，VOUT = 5V，fSW = 2.1MHz
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBW1
LM63460-Q1
ZHCSLU2A –DECEMBER 2021 –REVISED OCTOBER 2022
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................24
9 Application and Implementation..................................29
9.1 Application Information............................................. 29
9.2 Typical Applications.................................................. 29
9.3 Power Supply Recommendations.............................42
9.4 Layout....................................................................... 42
10 Device and Documentation Support..........................46
10.1 Device Support....................................................... 46
10.2 Documentation Support.......................................... 47
10.3 接收文档更新通知................................................... 47
10.4 支持资源..................................................................47
10.5 Trademarks.............................................................47
10.6 Electrostatic Discharge Caution..............................47
10.7 术语表..................................................................... 48
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
6.1 Wettable Flanks.......................................................... 5
6.2 Pinout Design for Clearance and FMEA.....................5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Timing Characteristics...............................................10
7.7 Systems Characteristics............................................11
7.8 Typical Characteristics..............................................12
8 Detailed Description......................................................14
8.1 Overview...................................................................14
Information.................................................................... 48
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2021) to Revision A (October 2022)
Page
• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Device Comparison Table
ORDERABLE PART
REFERENCE PART
NUMBER
OUTPUT
VOLTAGE
SPREAD
SPECTRUM
LIGHT-LOAD
MODE
SWITCHING
FREQUENCY
DEVICE
NUMBER
LM63460AASQRYFRQ1
LM63460-Q1
LM63460AAS-Q1
LM63460AFS-Q1
LM64460APP-Q1
LM64460BPP-Q1
LM64460CPP-Q1
Adjustable
Adjustable
Adjustable
3.3 V
On
AUTO
Adjustable
Adjustable
2.1 MHz
LM63460AFSQRYFRQ1
On
FPWM
LM64460APPQRYFRQ1
Pin selectable
Pin selectable
Pin selectable
Pin selectable
Pin selectable
Pin selectable
LM64460-Q1
LM64460BPPQRYFRQ1
LM64460CPPQRYFRQ1
2.1 MHz
5 V
2.1 MHz
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6 Pin Configuration and Functions
NC SW3 SW2 SW1 NC
16
14
13
17
15
18
12
PGND1
PGND2
NC
19
20
21
22
NC
11
10
9
VIN2
NC
VIN1
NC
GND
SW4
8
EN/SYNC
RT
CBOOT
1
7
2
3
4
5
6
NC BIAS VCC FB PGOOD
图6-1. 22-Pin Enhanced HotRod ™ QFN RYF Package (Top View)
表6-1. Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
CBOOT
NC
NO.
1
High-side driver supply rail. Connect a 100-nF capacitor between SW and CBOOT. An internal
bootstrap diode connects to VCC and allows the bootstrap capacitor to charge when SW is low.
P
2
No internal connection
—
Input to the internal LDO. Connect to the output voltage point to improve efficiency. Connect an
optional high-quality 0.1-µF to 1-µF capacitor from this pin to GND for improved noise immunity. If the
output voltage is above 12 V, connect BIAS to GND.
BIAS
VCC
FB
3
4
5
P
O
I
Internal LDO output. VCC supplies the internal control circuits. Do not connect to any external loads.
Connect a high-quality 1-µF capacitor from VCC to GND.
Output voltage feedback input to the internal control loop. Connect to the output voltage sense point
for fixed 3.3-V or 5-V output voltage settings. Connect to a feedback divider tap point to set an
adjustable output voltage. Do not float or connect to GND.
Open-drain power-good status indicator output. Pull up PGOOD to a suitable voltage supply through
a current-limiting resistor. High = power OK, low = fault. The PGOOD output goes low when EN = low,
VIN > 1 V.
PGOOD
RT
6
7
O
Connect a resistor from RT to GND with a value between 5.76 kΩand 66.5 kΩto set the switching
frequency between 200 kHz and 2.2 MHz. Do not float or connect directly to GND.
I/O
Precision enable input. High = on, Low = off. EN/SYNC can be connected to VIN. Precision enable
allows this pin to be used as an adjustable input voltage UVLO. See Precision Enable and Input
Voltage UVLO (EN). Do not float. EN/SYNC also functions as a synchronization input pin, triggering
on the rising edge of the external clock signal. Use a capacitor to AC couple the clock signal to EN/
SYNC. When synchronized to an external clock, the converter operates in FPWM mode and disables
the PFM light-load mode. See 节8.3.5.
EN/SYNC
8
I
NC
9
No internal connection
—
Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to
PGND2. A low-impedance connection must be provided to VIN1.
VIN2
NC
10
11
P
No internal connection
—
Power-ground connection to the internal low-side MOSFET. Connect to system ground. A low-
impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or
capacitors from this pin to VIN2.
PGND2
NC
12
13
G
No internal connection
—
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表6-1. Pin Functions (continued)
PIN
I/O (1)
DESCRIPTION
NAME
SW1
SW2
SW3
NC
NO.
14
15
P
Switch node of the converter. Connect to the output inductor.
No internal connection
16
17
—
Power ground to the internal low-side MOSFET. Connect to system ground. A low-impedance
connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from
this pin to VIN1.
PGND1
18
G
NC
19
20
No internal connection
—
Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to
PGND1. A low-impedance connection must be provided to VIN2.
VIN1
P
NC
21
22
No internal connection
—
SW4
P
Switch node of the converter. Connect to the bootstrap capacitor.
Exposed pad of the package internally connected to ground. The exposed pad must be connected to
the PCB inner-layer system ground plane or planes using numerous thermal vias to reduce thermal
impedance. See Layout Guidelines.
GND
G
–
(1) P = Power, G = Ground, I = Input, O = Output
6.1 Wettable Flanks
100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high
reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins
and terminals that are easily viewed. Therefore, it is difficult to visually determine whether or not the package is
successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve
the issue of side-lead wetting of leadless packaging. The LM63460-Q1 is assembled using a 22-pin Enhanced
HotRod VQFN package with wettable flanks to provide a visual indicator of solderability, which reduces the
inspection time and manufacturing costs.
6.2 Pinout Design for Clearance and FMEA
The LM63460-Q1 has a carefully designed pinout arrangement that provides additional clearance spacing
between high-voltage pins (VIN, SW, and CBOOT) and nearby low-voltage pins (such as PGND). Moreover, the
LM63460-Q1 pinout is designed for critical automotive applications requiring functional safety system design with
stricter reliability and higher durability. In terms of pin FMEA (failure mode effects analysis), the typical failure
scenarios considered include short circuit to ground, short circuit to input supply (VIN), short circuit to a
neighboring pin, and if a pin is left open circuit. These faults are considered as applied externally to the IC and
therefore are board-level failures rather than IC-level reliability failures. Example sources of such faults are stray
conductive filaments causing pin-to-pin shorts or a board manufacturing defect causing an open-circuit track.
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VIN1, VIN2 to PGND1, PGND2
CBOOT to SW
42
5.5
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0
V
BIAS to PGND1, PGND2
EN/SYNC to PGND1, PGND2
RT to PGND1, PGND2
FB to PGND1, PGND2
PGOOD to PGND1, PGND2
SW to PGND1, PGND2(2)
VCC to PGND1, PGND2
PGOOD sink current
16
V
Input Voltage
42
V
5.5
V
16
V
20
V
VIN + 0.3
5.5
V
–0.3
–0.3
Output Voltage
V
Current
TJ
10
mA
°C
°C
Junction temperature
150
150
–40
–40
Tstg
Storage temperature
(1) Operation outside the Absolute Maximum Ratings can cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device can not be fully functional,
and this can affect device reliability, functionality, performance, and shorten the device lifetime.
(2) A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤200 ns with a duty cycle of ≤0.01%.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
Device HBM Classification Level 2
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC Q100-011
Device CDM Classification Level C5
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
V
Input voltage
Input voltage
Output voltage
Frequency
Input voltage range after start-up
BIAS pin operating voltage
3
36
12
V
Output voltage range for adjustable version(2)
1
200
200
0
0.95*VIN
2200
2200
6
V
Frequency adjustment range
kHz
kHz
A
Sync frequency
Load current
Temperature
Synchronization frequency range
Output DC current range(3)
Operating junction temperature TJ range
150
°C
–40
(1) Recommended operating conditions indicate conditions for which the device is intended to be functional. For detailed specifications
and conditions, see Electrical Characteristics table.
(2) Under no conditions must the output voltage be allowed to fall below zero volts.
(3) Maximum continuous DC current can be derated when operating with high switching frequency and/or high ambient temperature. See
Application Information for details.
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7.4 Thermal Information
The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design
purposes. These values were calculated in accordance with JESD 51-7 and simulated on a 4-layer JEDEC board. They do
not represent the performance obtained in an actual application. For example, the EVM for this device achieves an RθJA of
23.5℃/W.
LM63460-Q1
THERMAL METRIC(1)
RYF (VQFN)
UNIT
22 PINS
23.5
38.5
30.3
8.8
RθJA
Junction-to-ambient thermal resistance (LM63460-Q1 EVM) (3)
Junction-to-ambient thermal resistance (JESD 51-7)(2)
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
RθJC(top)
RθJB
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1
ΨJT
8.7
ΨJB
RθJC(bot)
8.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These
values were calculated in accordance with JESD 51-7 and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application.
(3) Refer to the LM63460-Q1 EVM User's Guide for board layout and additional information. For thermal design information please see the
Application Information section.
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5 V. VIN1 shorted to VIN2 = VIN. VOUT is the converter output voltage.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE AND CURRENT
Needed to start up
3.95
3.0
VIN_OPERATE
Input operating voltage(1)
V
V
Once operating
VIN_OPERATE_H Hysteresis(1)
1
9
Operating quiescent current (not
IQ_VIN
IQ
VFB = +5%, VBIAS = 5 V, VOUT = 5 V
VFB = +5%, VBIAS = 5 V
18
6
µA
µA
µA
µA
switching)(2)
Operating quiescent current (not
switching); measured at VIN pin(3)
0.6
24
Current into BIAS pin (not switching,
maximum at TJ = 125°C)(3)
IBIAS
VFB = +5%, VBIAS = 5 V, AUTO mode
VEN = 0 V, TJ = 25°C
31.2
6
Shutdown quiescent current;
measured at VIN pin
ISD
0.6
ENABLE
VEN-TH
Enable input threshold voltage
(rising)
1.263
V
Enable input threshold voltage –
rising deviation from typical
VEN-ACC
5%
–5%
Enable threshold hysteresis as
percentage of VEN-TH (typical)
VEN-HYST
24%
0.4
28%
2.3
32%
VEN-WAKE
IEN
Enable wake-up threshold
Enable pin input current
V
VIN = VEN = 13.5 V
nA
Use this edge height to sync using
EN/SYNC pin
VEN_SYNC_E
Rise/fall time < 30 ns
2.4
V
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7.5 Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5 V. VIN1 shorted to VIN2 = VIN. VOUT is the converter output voltage.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LDO AND VCC
VBIAS > 3.4 V, CCM operation(1)
VBIAS = 3.1 V, non-switching
3.3
3.1
3.6
VCC
Internal VCC voltage
V
VCC-UVLO
Internal VCC undervoltage lockout
VCC rising undervoltage threshold
V
V
Internal VCC undervoltage lockout
hysteresis
VCC-UVLO-HYST
FEEDBACK
VFB_acc
Hysteresis below VCC-UVLO
1.1
VIN = 3.3 V to 36 V, TJ = 25°C,
FPWM mode
Initial reference voltage accuracy
Input current from FB to GND
1%
–1%
IFB
Adjustable versions only, VFB = 1 V
1
50
nA
OSCILLATOR
Minimum adjustable frequency by
RT pin
0.18
0.36
1.98
0.2
0.4
2.2
0.22 MHz
0.44 MHz
2.42 MHz
RRT = 66.5 kΩ
RRT = 33.2 kΩ
RRT = 5.76 kΩ
Adjustable frequency by RT pin with
400-kHz setting
fADJ
Maximum adjustable frequency by
RT pin
Frequency span of spread spectrum
operation –largest deviation from
center frequency
fS_SS
Spread spectrum active
2%
Spread spectrum pattern
frequency(1)
Spread spectrum active, fSW = 2.1
MHz
fPSS
1.5
Hz
MOSFETS
RDS(on)HS
RDS(on)LS
Power switch on-resistance
Power switch on-resistance
High-side MOSFET RDS(on)
Low-side MOSFET RDS(on)
41
21
82
45
mΩ
mΩ
Voltage on CBOOT relative to SW
that turns off the high-side switch
VBOOT-UVLO
2.1
V
CURRENT LIMITS
IL-HS
High-side switch current limit(4)
IL-LS
Duty cycle approaches 0%
8.9
6.1
10.3
7.1
11.5
8.1
A
A
Low-side switch current limit
Zero-cross current limit. Positive
current direction is out of the SW pin
IL-ZC
AUTO mode, static measurement
FPWM operation
0.25
–3
A
A
Negative current limit. Positive
current direction is out of the SW pin
IL-NEG
Minimum peak command in AUTO
mode / device current rating
IPK_MIN_0
IPK_MIN_100
VHICCUP
Pulse duration < 100 ns
Pulse duration > 1 µs
25%
Minimum peak command in AUTO
mode / device current rating
12.5%
40%
Ratio of FB voltage to in-regulation
FB voltage
Hiccup disabled during soft start
POWER GOOD
PGDOV
% of VOUT setting
% of VOUT setting
% of VOUT setting
105%
92%
107%
94%
110%
PGOOD upper threshold –rising
PGOOD lower threshold –falling
PGOOD hysteresis
PGDUV
96.5%
PGDHYST
1.3%
Input voltage for proper
PGOOD function
VIN(PGD-VALID)
1.0
V
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7.5 Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5 V. VIN1 shorted to VIN2 = VIN. VOUT is the converter output voltage.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
46-µA pullup to PGOOD, VIN = 1 V,
VEN = 0 V
0.4
Low-level PGOOD function output
voltage
VPGD(LOW)
V
1-mA pullup to PGOOD, VEN = 0 V
2-mA pullup to PGOOD, VEN = 3.3 V
1-mA pullup to PGOOD, VEN = 0 V
1-mA pullup to PGOOD, VEN = 3.3 V
0.4
0.4
17
40
40
90
Ω
Ω
RPGD
RDS(on) of PGOOD output
Pulldown current at the SW node in
an overvoltage condition
IOV
0.5
mA
THERMAL SHUTDOWN
TSHD
Thermal shutdown rising threshold(1)
Thermal shutdown hysteresis(1)
158
168
10
180
℃
℃
TSHD-HYS
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.
(2) IQ_VIN = IQ + IBIAS × (VOUT / VIN)
(3) This is the current used by the device while not switching, open loop, with FB pulled to +5% above nominal. It does not represent the
total input current to the converter while regulating.
(4) High-side current limit is a function of duty cycle. High-side current limit value is highest at small duty cycle and less at higher duty
cycle.
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7.6 Timing Characteristics
Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5 V.
Parameter
Test Condition
MIN
TYP
MAX UNIT
SWITCH NODE
tON(min)
Minimum HS switch on time
Maximum HS switch on time
Minimum LS switch on time
VIN = 20 V, IOUT = 2 A
55
9
70
ns
μs
ns
tON(max)
tOFF(min)
VIN = 4 V, IOUT = 1 A
65
85
7
Time from first SW pulse to VREF at
90%
tSS
3.5
9.5
5
ms
V
V
IN ≥4.2 V
IN ≥4.2 V
Time from first SW pulse to release
of FPWM lockout if output not in
regulation
tSS2
13
80
17
ms
ms
tW
Short circuit wait time ("hiccup" time)
ENABLE
CVCC = 1 µF, time from EN high to
first SW pulse if output starts at 0 V
tEN
Turn-on delay(1)
0.7
ms
µs
ns
Blanking of EN after rising or falling
edges(1)
tB
4
28
Enable sync signal hold time after
edge for edge recognition
tSYNC_EDGE
100
POWER GOOD
tPGDFLT(rise)
Delay time to PGOOD high signal
1.5
2
2.5
ms
µs
Glitch filter time constant for
PGOOD function
tPGDFLT(fall)
120
(1) Parameter specified using design, statistical analysis and production testing of correlated parameters; not tested in production.
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7.7 Systems Characteristics
The following values are specified by design provided that the component values in the typical application circuit are used.
Limits apply over the junction temperature range of –40°C to +150°C, unless otherwise noted. Minimum and Maximum limits
are derived using test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C,
and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. VIN1
shorted to VIN2 = VIN. VOUT is output setting. These parameters are not tested in production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
EFFICIENCY
VOUT = 5 V, IOUT = 6 A
92.5%
73%
Typical 2.1-MHz efficiency
Typical 2.1-MHz efficiency
Typical 400-kHz efficiency
ƞ5V_2p1MHz
VOUT = 5 V, IOUT = 100 µA, RFBT = 1
MΩ
VOUT = 3.3 V, IOUT = 6 A
90%
ƞ3p3V_2p1MHz
VOUT = 3.3 V, IOUT = 100 µA, RFBT
1 MΩ
=
71%
VOUT = 5 V, IOUT = 6 A
93.6%
76%
ƞ5V_400kHz
VOUT = 5 V, IOUT = 100 µA, RFBT = 1
MΩ
RANGE OF OPERATION
VIN for full functionality at reduced
VVIN_MIN1
VOUT set to 3.3 V
VOUT set to 3.3 V
3.0
V
V
load, after start-up
VIN for full functionality at 100% of
maximum rated load, after start-up
VVIN_MIN2
3.95
VOUT = 3.3 V, IOUT = 0 A, AUTO
mode, RFBT = 1 MΩ
7
10
IQ-VIN
Operating quiescent current(1)
µA
V
VOUT = 5 V, IOUT = 0 A, AUTO mode,
RFBT = 1 MΩ
VOUT = 3.3 V, IOUT = 4 A, –3%
output accuracy at 25°C
0.4
Input-to-output voltage differential to
maintain regulation accuracy without
inductor DCR drop
VDROP1
VOUT = 3.3 V, IOUT = 4 A, –3%
output accuracy at 125°C
0.55
0.8
VOUT = 3.3 V, IOUT = 4 A, –3%
regulation accuracy at 25°C
Input-to-output voltage differential to
maintain fSW ≥1.85 MHz, without
inductor DCR drop
VDROP2
V
VOUT = 3.3 V, IOUT = 4 A, –3%
regulation accuracy at 125°C
1.2
fSW = 1.85 MHz
87%
DMAX
Maximum switch duty cycle
While in frequency foldback
98%
(1) See detailed Input Supply Current for the meaning of this specification and how it can be calculated.
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7.8 Typical Characteristics
Unless otherwise specified, VIN = 13.5 V and fSW = 2.1 MHz.
16
4
3
2
1
0
TJ = -40C
TJ = 25C
TJ = 150C
12
8
4
0
-50
-25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
Junction Temperature (C)
Input Voltage (V)
VBIAS = 5 V
VEN/SYNC = 0 V
图7-1. Non-Switching Input Supply Current
图7-2. Shutdown Supply Current
1.01
1.005
1
12
10
8
0.995
6
Peak
Valley
0.99
4
-50
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (C)
图7-3. Feedback Voltage
图7-4. High-Side and Low-Side Current Limits
2400
2000
1600
1200
800
400
0
70
60
50
40
30
20
10
fSW = 200 kHz
fSW = 400 kHz
fSW = 2.2 MHz
High-side MOSFET
Low-side MOSFET
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
图7-5. Switching Frequency Set by RT Resistor
图7-6. High-Side and Low-Side MOSFET RDS(on)
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7.8 Typical Characteristics (continued)
Unless otherwise specified, VIN = 13.5 V and fSW = 2.1 MHz.
1.5
115
110
105
100
95
1.25
1
0.75
0.5
90
VEN Rising
OV Tripping
OV Recovery
UV Recovery
UV Tripping
VEN Falling
VEN_WAKE Rising
VEN_WAKE Falling
0.25
85
0
-50
80
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
Junction Temperature (°C)
Junction Temperature (°C)
图7-7. Enable Thresholds
图7-8. PGOOD Thresholds
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8 Detailed Description
8.1 Overview
The LM63460-Q1 is an easy-to-use synchronous buck DC/DC converter designed for a wide variety of
automotive applications where strict reliability and low EMI are of paramount importance. The devices operates
over an input voltage range of 3.95 V to 36 V, with operation down to 3 V after start-up and transients as high as
42 V. The LM63460-Q1 delivers up to 6-A DC load current with high conversion efficiency and ultra-low input
quiescent current in a very small solution size.
The LM63460-Q1 has a programmable switching frequency between 200 kHz to 2.2 MHz using its RT pin,
including sub-AM band at 400 kHz and above the AM band at 2.1 MHz. The converter includes specific features
for optimal EMI performance in noise-sensitive automotive applications, such as:
• An optimized package and pinout design enables a shielded switch-node layout that mitigates radiated EMI.
• Parallel input paths with a symmetrical capacitor layout minimize parasitic inductance, switch-voltage ringing,
and radiated field coupling.
• Pseudo-random spread spectrum (PRSS) modulation reduces peak emissions.
• Frequency synchronization and optional FPWM mode enable constant switching frequency across the full
load current range.
• Integrated high-side and low-side power MOSFETs with enhanced gate-drive control enable low-noise PWM
switching.
Together, these features significantly reduce EMI filtering requirements, thus eliminating shielding and other
expensive EMI mitigation measures, while helping to meet the CISPR 25 Class 5 automotive EMI standard for
conducted and radiated emissions.
The Enhanced HotRod QFN package of the LM63460-Q1 has a carefully designed wettable-flank pinout
arrangement that provides additional clearance spacing between adjacent VIN, SW, or PGND power pins to
improve reliability and pin FMEA. The converter also incorporates other features for comprehensive system
requirements, including:
• A precision enable input with hysteresis for programmable line undervoltage lockout (UVLO)
• Cycle-by-cycle peak and valley current limits for optimal inductor sizing
• An open-drain power-good monitor for power-rail sequencing and fault reporting
• Internally fixed output voltage soft start
• Monotonic start-up into prebiased loads
• Thermal shutdown with automatic recovery
The LM63460-Q1 is qualified to AEC-Q100 grade 1 and has electrical characteristics specified up to a maximum
junction temperature of 150°C. The following help provide an ideal point-of-load regulator solution for automotive
applications requiring enhanced reliability and durability:
• Wide input voltage range
• Low quiescent current consumption
• Optimized thermal design and high-temperature operation
• Improved pin FMEA
• Small solution size
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8.2 Functional Block Diagram
VCC
Clock
VCC
Oscillator
RT
BIAS
VCC UVLO
LDO
Slope
compensation
VIN
Over
temperature
detect
OTP
Sync
SYNC
detect
Frequency foldback
FPWM / AUTO
System enable
Enable
EN/SYNC
CBOOT
VIN1
HS current sense
Error
amplifier
VIN
+
+
–
VIN2
COMP
–
Clock
+
High and
low limiting
circuit
+
–
Output
low
HS
current
limit
SW
System enable
FB
OTP
Gate drivers
and logic
Soft start
circuit and
bandgap
Hiccup active
LS
current
limit
VCC UVLO
–
+
Voltage reference
FPWM / AUTO
–
+
PGND1
PGND2
LS
current
min
PGOOD
PGOOD logic
with filter and
release delay
Vout UV/OV
LS current sense
System enable
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8.3 Feature Description
8.3.1 Input Voltage Range (VIN1, VIN2)
With a steady-state input voltage range from 3 V to 36 V, the LM63460-Q1 is intended for step-down
conversions from typical 12-V and 24-V automotive supply rails. The schematic circuit in 图 8-1 shows all the
necessary components to implement an LM63460-Q1 step-down regulator using a single input supply.
VIN = 3 V to 36 V
CIN1
VIN1
VIN2
CIN2
CIN-HF2
CIN-HF1
PGND1
PGND2
Precision
enable for
VIN UVLO
VCC
Optional external bias
LO
BIAS
VOUT = 1 V to 95% VIN
IOUT(max) = 6 A
RPG
LM63460-Q1
Synchronization
(200 kHz to 2.2 MHz)
RENT
SW
PGOOD
CBOOT
PGOOD indicator
CSYNC
COUT
SYNC
EN/SYNC
RT
CBOOT
RFBT
RENB
optional
FB
VCC
GND
RRT
CVCC
RFBB
RFF
CFF
Optional feedforward
network
图8-1. LM63460-Q1 Schematic Diagram with Input Voltage Operating Range of 3 V to 36 V
The minimum input voltage required for start-up is 3.95 V. Take extra care to make sure that the voltage at the
VIN pins of the converter (VIN1 and VIN2) does not exceed the absolute maximum voltage rating of 42 V during
line or load transient events. Voltage ringing at the VIN pins that exceeds the Absolute Maximum Ratings can
damage the IC.
8.3.2 Output Voltage Setpoint (FB)
While dependent on switching frequency and load current levels, the LM63460-Q1 is generally capable of
providing an output voltage in the range of 1 V to a maximum of slightly less than the input voltage. Define the
output voltage setpoint with feedback resistors designated as RFBT and RFBB as shown in 图8-1.
The LM63460-Q1 uses a 1-V reference voltage, and the internal error amplifier regulates the FB voltage to be
equal to the reference voltage. Use 方程式 1 to determine RFBB for a desired output voltage setpoint and a given
value of RFBT
.
(1)
While RFBT is generally in the range of 10 kΩ to 1 MΩ, use a value of 100 kΩ for improved noise immunity
(relative to higher resistances such as 1 MΩ) and reduced current consumption (compared to lower resistance
values).
8.3.3 Precision Enable and Input Voltage UVLO (EN/SYNC)
The EN/SYNC input supports adjustable input undervoltage lockout (UVLO) programmed by resistor values for
application-specific power-up and power-down requirements. Also, an external logic signal can be used to drive
the EN/SYNC input to toggle the output ON or OFF and for system sequencing or protection.
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The LM63460-Q1 enters a low-IQ shutdown mode when EN/SYNC is pulled below 0.4 V. The internal LDO
regulator powers off, shutting down the bias currents of the LM63460-Q1. When the EN/SYNC voltage is
between the hard shutdown and the precision enable thresholds, the LM63460-Q1 operates in standby mode
with the VCC voltage in regulation. After the voltage at EN/SYNC is above VEN-TH, the converter begins to switch
normally, provided the input voltage drives the internal VCC above its rising UVLO threshold of 3.6 V (typical).
The EN/SYNC pin cannot be left floating. The simplest way to enable operation is to connect the EN/SYNC pin
to VIN, allowing self-start-up of the LM63460-Q1. However, many applications benefit from the use of a divider
network from VIN to EN/SYNC as shown in 图 8-1, which establishes a precision input voltage UVLO. This can
be used for sequencing, to prevent re-triggering of the device when used with long input cables, or to reduce the
occurrence of deep discharge of a battery power source. Note that the precision enable threshold, VEN-TH, has a
28% hysteresis to prevent ON/OFF re-triggering. An external logic output of another IC can also be used to drive
EN/SYNC, allowing system power sequencing.
Calculate the resistor divider values using 方程式2. See Input Voltage UVLO for additional information.
(2)
where
• VIN(on) is the required input voltage turn-on threshold.
Note that EN/SYNC can also be used as an external synchronization clock input. A blanking time, tB, is applied
to the enable logic after a clock edge is detected. Any logic change within the blanking time is ignored. The
blanking time is not applied when the converter is in shutdown mode. The blanking time ranges from 4 µs to 28
µs. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 µs.
8.3.4 Frequency Synchronization (EN/SYNC)
Use the EN/SYNC pin of the LM63460-Q1 to synchronize the internal oscillator to an external clock signal
ranging from 200 kHz to 2.2 MHz. The internal oscillator can be synchronized by AC coupling a positive clock
edge to EN/SYNC, as shown in 图8-1.
It is recommended to keep the parallel combination value of RENT and RENB in the 100-kΩ range. RENT is
required for synchronization, but RENB can be left unmounted. The external clock must be off before start-up to
allow proper start-up sequencing.
Referring to 图 8-2, the AC-coupled voltage edge at EN/SYNC must exceed the SYNC amplitude threshold,
VEN_SYNC, to trip the internal synchronization pulse detector. In addition, the minimum EN/SYNC rising pulse and
falling pulse durations must be longer than tSYNC_EDGE and shorter than the blanking time, tB. A 3.3-V or higher
amplitude pulse signal coupled through a 1-nF capacitor, CSYNC, is suggested.
VEN/SYNC
tSYNC_EDGE
VEN_SYNC
t
0
tSYNC_EDGE
图8-2. Typical Synchronization Waveform Applied to EN/SYNC
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After a valid synchronization signal is applied for 2048 cycles, the clock frequency quickly changes to that of the
applied signal. Synchronization overrides spread spectrum, turning it off.
8.3.5 Clock Locking
A clock locking procedure initiates after a valid synchronization signal is detected. The LM63460-Q1 receives
this signal at the EN/SYNC pin. After approximately 2048 pulses, the clock frequency completes a smooth
transition to the frequency of the synchronization signal without output voltage variation. Note that when the
frequency is adjusted suddenly, the phase is maintained so the clock cycle that lies between operation at the
default frequency and at the synchronization frequency is of intermediate length. This action eliminates very long
or very short pulses. After the frequency is adjusted, the phase is adjusted over a few tens of cycles so that
rising synchronization edges correspond to rising switch (SW) node pulses. See 图8-3.
Pulse
~2048
Pulse
~2049
Pulse
~2050
Pulse
~2051
Pulse 1
Pulse 2
Pulse 3
Pulse 4
VSYNCDH
VSYNCDL
Synchronization
signal
Spread Spectrum is on between pulse 1 and
approximately pulse 2048, there is no change to
operating frequency
Also clock frequency matches the
synchronization signal and phase
locking begins
Phase lock achieved, Rising edges
align to within approximately 45 ns,
no spread spectrum
On approximately pulse 2048, spread
spectrum turns off
SW Node
VIN
GND
The synchronization signal is detected after four pulses. The converter is ready to synchronize after approximately 2048 pulses, and the
frequency is adjusted using a glitch-free technique. Phase locking is subsequently achieved.
图8-3. Synchronization Process
Note also that the LM63460-Q1 turns on spread spectrum after the first edge in the synchronization pulse. See
the EN/SYNC pin description in Pin Configuration and Functions. Upon adjustment of the frequency at the
approximate 2048th pulse, spread spectrum is turned off. Finally, if the converter runs at reduced switching
frequency due to low or high input voltage or during current limit, frequency lock does not occur until the
condition causing low-frequency operation has been removed.
8.3.6 Adjustable Switching Frequency (RT)
Connect a resistor from RT to GND to set the switching frequency. Use 方程式 3 or refer to 图 8-4 for resistor
values. Note that a resistor value outside of the recommended range can cause the device to shut down. This
prevents unintended operation if RT is shorted to ground or left open. Do not apply a pulsed signal to this pin to
force synchronization. If synchronization to an external clock is required, refer to 节8.3.4.
(3)
70
60
50
40
30
20
10
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Frequency (kHz)
图8-4. Setting the Switching Frequency
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8.3.7 Power-Good Monitor (PGOOD)
The PGOOD function is implemented to replace a discrete reset device, reducing BOM count and cost. The
PGOOD voltage goes low when the feedback (FB) voltage is outside of the specified PGOOD thresholds (see 图
7-8). This can occur during current limit and thermal shutdown, as well as when disabled and during normal
start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line
and load transients. Output voltage excursions that are shorter than tPGDFLT(fall) do not trip the PGOOD flag.
Refer to 图8-5 to best understand PGOOD operation.
The PGOOD output consists of an open-drain N-channel transistor, requiring an external pullup resistor to a
suitable logic supply or VOUT. When EN is pulled low, the flag output is also forced low. With EN low, PGOOD
remains valid as long as the input voltage is above 1 V (typical).
Output
Voltage
Input
Voltage
Input Voltage
tPGDFLT(fall)
tPGDFLT(rise)
tPGDFLT(rise)
tPGDFLT(fall)
VPGD_HYST
tPGDFLT(fall)
tPGDFLT(fall)
VPGD_UV (falling)
VIN_OPERATE (rising)
VIN_OPERATE (falling)
VIN(PGD_VALID)
GND
< 18 V
PGOOD
Small glitches
do not cause
PGOOD to
PGOOD may
not be valid if
input is below
VIN(PGD_VALID)
Small glitches do not
reset tPGDFLT(rise) timer
PGOOD may not
be valid if input is
below VIN(PGD_VALID)
Startup
delay
signal a fault
图8-5. PGOOD Timing Diagram (Excludes OV Events)
表8-1. Conditions That Cause PGOOD to Signal a Fault (Pull Low)
FAULT CONDITION ENDS (AFTER WHICH tPGDFLT(rise) MUST PASS
BEFORE PGOOD OUTPUT IS RELEASED)(1)
FAULT CONDITION INITIATED
Output voltage in regulation:
VOUT < VOUT-target × PGDUV AND t > tPGDFLT(fall)
VOUT-target × (PGDUV + PGDHYST) < VOUT < VOUT-target × (PGDOV –
PGDHYST) (see 图7-8)
VOUT > VOUT-target × PGDOV AND t > tPGDFLT(fall)
TJ > TSHD
Output voltage in regulation
TJ < TSHD-F AND output voltage in regulation
VEN > VEN-TH rising AND output voltage in regulation
VCC > VCC-UVLO AND output voltage in regulation
VEN < VEN-TH falling
VCC < VCC-UVLO - VCC-UVLO-HYST
(1) As an additional operational check, PGOOD remains low during the soft-start time, which is defined as the time for the output voltage
to reach its setpoint or tSS2 has passed since initiation (whichever is lower).
8.3.8 Bias Supply Regulator (VCC, BIAS)
VCC is the output of the internal LDO subregulator used to supply the control circuits of the LM63460-Q1. The
nominal VCC voltage is 3.3 V. The BIAS pin is the input to the internal LDO. This input can be connected to VOUT
to provide the lowest possible input supply current. If the BIAS voltage is less than 3.1 V, VIN1 and VIN2 directly
power the internal LDO.
To prevent unsafe operation, VCC has UVLO protection that prevents switching if the internal voltage is too low.
See VCC-UVLO and VCC-UVLO-HYST in the Electrical Characteristics. Note that these UVLO levels and the dropout
voltage of the LDO are used to derive the minimum VIN_OPERATE and VIN_OPERATE_H values.
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8.3.9 Bootstrap Voltage and UVLO (CBOOT)
The gate driver of the high-side (HS) switch requires a bias voltage higher than VIN. The bootstrap capacitor,
CBOOT, connected between CBOOT and SW, works as a charge pump to boost the voltage on CBOOT to a level
of VCC above the SW voltage. The LM63460-Q1 has an integrated bootstrap diode to minimize external
component count. Use a 100-nF bootstrap capacitor rated for 10 V or higher. The VBOOT-UVLO threshold (2.1 V
typical) is designed to maintain proper HS switch operation. If the bootstrap capacitor voltage drops below
VBOOT-UVLO, then the converter initiates a charging sequence, turning on the low-side switch before attempting to
turn on the HS switch.
8.3.10 Spread Spectrum
The purpose of spread spectrum is to eliminate peak emissions at specific frequencies by spreading these
emissions across a wider range of frequencies. In most systems containing the LM63460-Q1, low-frequency
conducted emissions from the first few harmonics of the switching frequency can be easily filtered. A more
difficult design criterion is reduction of the emissions at higher harmonics that fall in the FM frequency band.
These harmonics often couple to the environment through electric fields around the switch node and inductor.
The LM63460-Q1 uses a ±2% spread of frequencies, which can spread energy smoothly across the FM and TV
bands but is small enough to limit subharmonic emissions below the converter switching frequency. Peak
emissions at the switching frequency of the converter are only reduced slightly, by less than 1 dB, while peaks in
the FM band are typically reduced by more than 6 dB.
The LM63460-Q1 uses a cycle-to-cycle frequency hopping method based on a linear feedback shift register
(LFSR). This intelligent pseudo-random generator limits cycle-to-cycle frequency changes to limit output ripple.
The pseudo-random pattern repeats at less than 1.5 Hz, which is below the audio band.
Spread spectrum is only available while the clock of the LM63460-Q1 is free running at its natural frequency. Any
of the following conditions overrides spread spectrum, turning it off:
• The clock is slowed when operating in dropout.
• The clock is slowed at light load in AUTO mode. In FPWM mode, spread spectrum is active even if there is
no load.
• At a high-input-voltage to low-output-voltage conversion ratio when the device operates at its minimum on
time, the internal clock is slowed, disabling spread spectrum. Refer to the Timing Characteristics for more
detail.
• The clock is synchronized to an external clock signal.
8.3.11 Soft Start and Recovery From Dropout
The converter uses a reference-based soft start that prevents output voltage overshoot and large inrush current
during start-up. Soft start is triggered by any of the following conditions:
• Power is applied to the VIN pins of the IC, releasing UVLO.
• EN/SYNC goes high to turn on the device.
• Recovery from a hiccup-waiting period
• Recovery from thermal shutdown protection
After soft start is triggered, the IC takes the following actions:
• The reference used by the IC to regulate the output voltage is slowly ramped. The net result is that the output
voltage takes tSS to reach 90% of its desired value.
• The operating mode is set to AUTO, activating diode emulation. This action allows a pre-biased start-up
without pulling the output voltage low if there is a voltage already present on the output.
Together, these actions provide start-up with limited inrush currents and also facilitate the use of high output
capacitance and higher loading conditions that cause the peak inductor current to border on current limit during
start-up without triggering hiccup. See 图8-6.
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Triggering event
Triggering event
If selected, FPWM is
enabled after regulation
but no later than tSS2
If selected, FPWM is
enabled after regulation
but no later than tSS2
tEN
tSS
tEN
tSS
V
V
VEN
VEN
VOUT setpoint
VOUT setpoint
VOUT
VOUT
90% of VOUT
setpoint
90% of VOUT
setpoint
t
t
0 V
0 V
tSS2
tSS2
(a)
(b)
Soft start functions with the output voltage starting from 0 V in (a), or if there is already a prebiased output as shown in (b). In either
case, the output voltage must reach within 10% of the setpoint within tSS after soft start initiates. FPWM and hiccup are disabled during
soft start, with both FPWM and hiccup enabled after the output voltage reaches regulation or after the tSS2 time interval expires,
whichever happens first.
图8-6. Soft-Start Operation
Any time the output voltage falls more than a few percent, the output voltage ramps up slowly. This condition is
called recovery from dropout and differs from soft start in three important ways:
• The reference voltage is set to approximately 1% above what is needed to achieve the preset output voltage
setpoint.
• Hiccup is allowed if the output voltage is less than 40% of the nominal setpoint. Note that during dropout
regulation itself, hiccup is inhibited.
• FPWM mode is allowed during recovery from dropout. If the output voltage were to suddenly be pulled up by
an external supply, the converter can pull down on the output.
Despite being called recovery from dropout, this feature is active whenever the output voltage drops to a few
percent lower than the setpoint. This action primarily occurs under the following conditions:
• Dropout: When there is insufficient input voltage to maintain the desired output voltage
• Overcurrent: When there is an overcurrent event that is not severe enough to trigger hiccup
V
VIN
Slope
VOUT
VOUT Set
Point
the same
as during
soft start
t
Time
Whether the output voltage falls due to high load current or low input voltage, after the condition that causes the output to fall below its
setpoint is removed, the output recovers at the same rate as during start-up. Even though hiccup does not trigger due to dropout, it can,
in principle, be triggered during recovery if output voltage is below 40% of the output voltage setpoint for more than 128 clock cycles.
图8-7. Recovery From Dropout
8.3.12 Overcurrent and Short-Circuit Protection
The converter protects from overcurrent conditions with cycle-by-cycle current limiting on both the high-side and
the low-side MOSFETs. High-side MOSFET overcurrent protection is implemented by nature of peak-current
mode control. The HS switch current is sensed when the HS switch is turned on after a short blanking time.
Every switching cycle, this switch current is compared to the minimum of a fixed current setpoint or the output of
the voltage regulation loop minus slope compensation. Because the voltage loop output has a maximum value
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and slope compensation increases with duty cycle, the HS current limit decreases with increased duty cycle
when the duty cycle is above 35%. See 图8-8.
12
10
8
6
4
2
HS Switch Max Current
Rated Output Current
0
0
0.2
0.4 0.6 0.8 1
Duty Cycle
图8-8. HS Switch Maximum Current as a Function of Duty Cycle for the LM63460-Q1
When the LS switch is turned on, the switch current is also sensed and monitored. Like the HS device, the LS
switch turns off as commanded by the voltage control loop and low-side current limit. If the LS switch current is
higher than IL-LS at the end of a switching cycle, the switching cycle is extended until the LS current reduces
below the limit. The LS switch is turned off after the LS current falls below its limit, and the HS switch is turned
on again as long as at least one clock period has passed since the last time the HS device has turned on.
VSW
VIN
tON < tON(max)
0
t
Typically, tSW > clock setting
iL
IL-HS
IL-LS
IOUT
t
0
图8-9. Current Limit Waveforms
Because the current waveform assumes values between IL-HS and IL-LS, the maximum output current is very
close to the average of these two values. Hysteretic control is used and current does not increase as output
voltage approaches zero.
The converter employs hiccup overcurrent protection if there is an extreme overload, and the following
conditions are met for 128 consecutive switching cycles:
• The output voltage is below approximately 0.4 times the output voltage setpoint.
• Greater than tSS2 has passed since soft start has started; see Soft Start and Recovery from Dropout.
• The converter is not operating in dropout, which is defined as having minimum off time controlled duty cycle.
In hiccup mode, the device shuts itself down and attempts to soft start after tW. Hiccup mode helps reduce the
device power dissipation under severe overcurrent conditions and short circuits. See 图 8-10. After the overload
is removed, the device recovers as though in soft start; see 图8-11.
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VOUT 2 V/DIV
VOUT 2 V/DIV
IL 5 A/DIV
IL 5 A/DIV
20 ms/DIV
20 ms/DIV
图8-10. Inductor Current Bursts During Hiccup
图8-11. Short-Circuit Recovery
8.3.13 Thermal Shutdown
Thermal shutdown prevents the device from extreme junction temperatures by turning off the internal switches
when the IC junction temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C.
After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature
drops to approximately 158°C. When the junction temperature falls below 158°C (typical), the converter attempts
to soft start.
While the converter is shut down due to high junction temperature, power continues to be provided to VCC. To
prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced
current limit while the converter is disabled due to high junction temperature. The VCC current limit is reduced to
a few milliamperes during thermal shutdown.
8.3.14 Input Supply Current
The converter is designed to have very low input supply current when regulating at light loads. This is achieved
by powering much of the internal circuits from the output. The BIAS pin is the input to the LDO that powers the
majority of the control circuits. By connecting BIAS to the regulator output, a small amount of current is drawn
from the output. This current is reduced at the input by the ratio of VOUT / VIN. 方程式 4 defines the current
consumed by the operating (switching) buck converter at no load:
(4)
where
• IQ_VIN is the current into the VIN pins –see the Electrical Characteristics.
• IEN is current into the EN/SYNC pin –see the Electrical Characteristics. Include this current if EN/SYNC is
connected to VIN. Note that this current drops to a very low value if EN/SYNC connects to a voltage less than
5 V.
• IDIV is the current consumption of the feedback divider used to set output voltage.
• ηeff is the light-load efficiency when IQ_VIN is removed from the input current of the buck converter. ηeff = 0.8
is a conservative value that can be used under normal operating conditions.
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8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN/SYNC pin provides electrical ON and OFF control of the device. When the EN/SYNC voltage is less
than 0.4 V, both the regulator and the internal LDO have no output voltage. The converter is in shutdown mode,
and the quiescent current drops to 0.6 µA typical.
8.4.2 Standby Mode
The internal LDO has a lower enable threshold than the output of the converter. When the EN/SYNC pin voltage
is above 1.1 V (maximum) and below the precision enable threshold, the internal LDO regulates the VCC voltage
at 3.3 V typical. The precision enable circuitry is ON after VCC is above its UVLO. The internal power MOSFETs
remain off unless the voltage on EN/SYNC goes above its precision enable threshold. The converter also
employs UVLO protection. If the VCC voltage is below its UVLO level, the output of the converter is turned off.
8.4.3 Active Mode
The converter is in active mode whenever the EN/SYNC voltage is above its threshold voltage, VIN, is high
enough to satisfy VIN_OPERATE, and no other fault conditions are present. The simplest way to enable operation is
to connect EN/SYNC to VIN, which allows self start-up when the applied input voltage exceeds the minimum
VIN_OPERATE
.
In active mode, depending on the load current, input voltage, and output voltage, the converter is in one of five
modes:
• Continuous conduction mode (CCM) with fixed switching frequency when the load current is above half of the
inductor current ripple.
• AUTO mode –Light-load operation with PFM where the switching frequency decreases at very light load.
• FPWM mode –Light-load operation that maintains constant switching frequency across the full load range.
• Minimum on time: The switching frequency reduces to maintain regulation with high step-down conversion
ratios, that is, high input voltage to low output voltage.
• Dropout mode: The switching frequency reduces to minimize the dropout voltage.
8.4.3.1 CCM Mode
The following operating description of the converter refers to the Functional Block Diagram and to the waveforms
in 图 8-12. In CCM, the converter supplies a regulated output voltage by turning on the internal high-side (HS)
and low-side (LS) NMOS switches with varying duty cycle (D). During the HS switch on time, the SW voltage,
VSW, swings up to approximately VIN, and the inductor current, iL, increases with a linear slope. The HS switch is
turned off by the control logic. During the HS switch off time, tOFF, the LS switch is turned on. Inductor current
discharges through the LS switch, which forces VSW to swing below ground by the voltage drop across the LS
switch. The control loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on time
of the HS switch over the switching period:
D = tON / tSW
(5)
In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage:
D = VOUT / VIN
(6)
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VSW
VIN
tON
tSW
VOUT
VIN
D =
tOFF
tON
0
t
–IOUT RDS(on)LS
tSW
iL
ILPK
IOUT
ILripple
0
t
图8-12. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
8.4.3.2 AUTO Mode –Light-Load Operation
The converter can have two behaviors while lightly loaded. AUTO mode operation allows for a seamless
transition between normal current-mode operation while heavily loaded and in highly efficient light-load
operation. The other behavior, called FPWM mode, maintains full frequency even when unloaded. Which mode
the converter operates in depends on which factory option is employed. See 节 5. Note that the converter
operates in FPWM mode when synchronizing frequency to an external clock signal.
In AUTO mode, the converter employs two techniques to improve efficiency during light-load operation:
• Diode emulation, which allows DCM operation
• Switching frequency reduction
Note that while these two features operate together to create excellent light-load behavior, they operate
independently of each other.
8.4.3.2.1 Diode Emulation
Diode emulation prevents reverse current through the inductor, which requires a lower frequency to regulate
given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced. With a
fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to maintain
regulation.
VSW
tON
tSW
VOUT
VIN
D =
VIN
tOFF
tON
tHIGHZ
0
t
tSW
iL
ILPK
IOUT
0
t
In AUTO mode, the low-side MOSFET is turned off after the inductor current is near zero. As a result, after the output current is less
than half of what the inductor ripple is in CCM, the converter operates in DCM and diode emulation is active.
图8-13. PFM Mode Operation at Light Loads
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The converter has a minimum peak inductor current setting while operating in AUTO mode. After current is
reduced to a low value with fixed input voltage, the on time remains constant. Regulation is then achieved by
adjusting the switching frequency. This mode of operation is called PFM mode regulation.
8.4.3.2.2 Frequency Foldback
The converter reduces its switching frequency whenever the output voltage is higher than the setpoint. This
function is enabled whenever COMP, an internal signal, is low and there is an offset between the FB regulation
setpoint and the voltage applied at FB. The net effect is that there is a larger output impedance while lightly
loaded in AUTO mode than in normal operation. The output voltage is approximately 1% high when the
converter is completely unloaded.
VOUT
Current
Limit
1% Above
Set point
VOUT Set
Point
IOUT
Output Current
0
In AUTO mode, after the output current drops below approximately 1/10th the rated current of the converter, the output resistance
increases so that output voltage is 1% high while the converter is completely unloaded.
图8-14. Steady-State Output Voltage Versus Output Current in AUTO Mode
In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The
lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable,
use a dummy load at the output or select FPWM mode to reduce or eliminate this offset.
8.4.3.3 FPWM Mode –Light-Load Operation
Like AUTO mode operation, FPWM mode is selected as a factory option. FPWM applies by default during
synchronization. In FPWM mode, the switching frequency is maintained constant while lightly loaded by allowing
negative current to flow in the inductor. Negative current is limited to –3 A by a reverse current limit circuit.
VSW
tON
tSW
VOUT
VIN
D =
VIN
tOFF
tON
0
t
tSW
iL
ILPK
ILripple
IOUT
0
t
In FPWM mode, continuous conduction (CCM) is possible even if IOUT is less than half of Iripple
.
图8-15. FPWM Mode Operation
Frequency reduction is still available in FPWM mode if the output voltage is high enough to command minimum
on time even while lightly loaded, allowing good behavior during faults that involve the output being pulled up.
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8.4.3.4 Minimum On-Time (High Input Voltage) Operation
The converter continues to regulate the output voltage even if the input-to-output voltage ratio requires an on
time less than the minimum on time of the converter with a given clock setting. This is accomplished using valley
current control as shown in 图8-16.
VSW
tON
tSW
VOUT
VIN
D =
VIN
tON = tON(min)
tOFF
0
t
–IOUT RDS(on)LS
tSW > clock setting
iL
IOUT
ILVLY
ILripple
0
t
In valley control mode, the inductor valley current is regulated, not inductor peak current.
图8-16. Valley Current Operation
At all times, the compensation circuit dictates maximum peak and valley inductor currents. If for any reason, the
valley current setpoint is exceeded, the clock cycle is extended until the valley current falls below that
determined by the compensation circuit. If the converter is not operating in current limit, the maximum valley
current is set above the peak inductor current, preventing valley control from being used unless there is a failure
to regulate solely using peak current. If the input-to-output voltage ratio is too high, even though current exceeds
the peak value dictated by compensation, the high-side switch cannot be turned off quickly enough to regulate
the output voltage. As a result, the compensation circuit reduces both peak and valley currents. After a low
enough current is established, the valley inductor current matches that being commanded by the compensation
circuit. Under these conditions, the low-side switch is kept on and the next clock cycle is delayed until the
inductor current drops below the desired valley current threshold. Because the on time is fixed at its minimum
value, this type of operation resembles that of a device using a constant on-time (COT) control scheme.
8.4.3.5 Dropout
Dropout operation is defined as any input-to-output voltage ratio that requires the switching frequency to
decrease in order to achieve the required duty cycle. At a given clock frequency, the duty cycle is limited by the
converter minimum off time. After this limit is reached, if the clock frequency were maintained, the output voltage
falls. Instead of allowing the output voltage to drop, the converter extends its on time past the end of the clock
cycle until the required peak inductor current is achieved. The clock is allowed to start a new cycle once the
required peak inductor current is reached or once a pre-determined maximum on time, tON(max), of approximately
9 µs passes. As a result, after the required duty cycle cannot be achieved at the selected clock frequency due to
the minimum off-time requirement, the switching frequency decreases to maintain regulation. If the input voltage
is low enough such that output voltage cannot be regulated even with an on time of tON(max), the output voltage
drops to slightly below the input voltage, VDROP1. See the Systems Characteristics. Refer to 图 8-7 for additional
information on recovery from dropout.
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VDROP2 if
frequency =
1.85 MHz
Input
Voltage
iL
VDROP1
Output
Output
Setting
Voltage
VIN
0
Input Voltage
iL
Frequency
Setting
~100kHz
0
VIN
Input Voltage
Output voltage and switching frequency vs. input voltage: if there is little difference between the input voltage and output voltage
setpoint, the converter reduces switching frequency to maintain regulation. If the input voltage is too low to provide the desired output
voltage at approximately 110 kHz, the output voltage tracks the input voltage.
图8-17. Switching Frequency and Output Voltage in Dropout
VSW
tON
tSW
VOUT
VIN
D =
VIN
tOFF = tOFF(min)
tON < tON(max)
0
t
–IOUT RDS(on)LS
tSW > clock setting
iL
ILPK
IOUT
ILripple
0
t
The inductor current takes longer than a normal clock period to reach the desired peak value, and consequently the switching frequency
decreases to maintain regulation. This frequency reduction is limited by tON(max)
.
图8-18. Dropout Waveforms
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The LM63460-Q1 synchronous buck converter requires only a few external components to convert from a wide
range of supply voltages to a fixed output voltage at an output current up to 6 A. A comprehensive LM63460-Q1
quickstart calculator is available by download to expedite and streamline the process of designing of an
LM63460-Q1-based regulator circuit.
9.2 Typical Applications
For the circuit schematic, bill of materials, PCB layout files, and test results of an LM63460-Q1 implementation,
see the LM63460-Q1 EVM.
9.2.1 Design 1 –Automotive Synchronous Buck Regulator at 2.1 MHz
图 9-1 shows the schematic diagram of a synchronous buck regulator with an output voltage set at 5 V and a
rated load current of 6 A. In this example, the target half-load and full-load efficiencies are 94.5% and 92.5%,
respectively, based on a nominal input voltage of 13.5 V that ranges from 5 V to 36 V. The switching frequency is
set at 2.1 MHz with resistor RRT of 6.04 kΩ. The BIAS input is connected to the 5-V output, thus reducing IC
bias power dissipation and improving efficiency performance.
VIN = 5 V...36 V
U1
VIN1
VIN2
CIN1
10
CIN2
10
CIN-HF1
10 nF
CIN-HF2
10 nF
F
F
PGND1
PGND2
Precision
enable for
VIN UVLO
VCC
LM63460-Q1
Optional external bias
LO
VOUT = 5 V
IOUT = 6 A
BIAS
RPG
100 k
RENT
Synchronization
(200 kHz to 2.2 MHz)
SW
365 k
0.76
CBOOT
H
PGOOD
COUT
PGOOD indicator
CSYNC
0.1
F
2 ꢀ 47
F
SYNC
EN/SYNC
RT
CBOOT
FB
1 nF
RFBT
RENB
optional
VCC
100 k
102 k
RRT
6.04 k
GND
CVCC
RFBB
1
F
25.5 k
RFF
1 k
CFF
10 pF
Feedforward network
图9-1. Application Circuit 1 –5 V, 6 A at 2.1 MHz
备注
This application example is provided herein to showcase the LM63460-Q1 buck converter in several
different implementation scenarios. Depending on the source impedance of the input supply bus, an
electrolytic capacitor can be required at the input for stability, particularly at low input voltage and high
output current operating conditions. See the Power Supply Recommendations for more detail.
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9.2.1.1 Design Requirements
表 9-1 shows the intended input, output, and performance parameters for this application example. The
converter operates in dropout during cold crank when the input voltage decreases to 5 V, with the output voltage
slightly below its 5-V setpoint.
表9-1. Design Parameters
DESIGN PARAMETER
VALUE
6 V to 18 V
5 V
Input voltage range (for constant fSW
)
Minimum transient input voltage, cold crank
Maximum transient input voltage, load dump
Output voltage and full-load current
Switching frequency
36 V
5 V, 6 A
2.1 MHz
±1%
Output voltage regulation
IC input current, no-load
< 10 µA
< 1 µA
IC shutdown current
表 9-2 gives the selected buck converter power-stage components with availability from multiple vendors. This
design uses a low-DCR inductor and all-ceramic output capacitor implementation.
表9-2. List of Materials for Application Circuit 1
REF DES
QTY
SPECIFICATION
VENDOR(1)
Samsung
TDK
PART NUMBER
CL31Y106KBKVPNE
CGA5L1X7R1H106K
GCM32EC71H106KA03
CGA6P3X7S1H106M
GCM32ER70J476KE19L
CGA6P1X7S1A476M
GCM32EC71A476KE02
CGA6P1X7R1C226M
XGL4030-761MEC
10 µF, 50 V, X7R, 1206, ceramic, AEC-Q200
CIN
2
Murata
10 µF, 50 V, X7S, 1210, ceramic, AEC-Q200
47 µF, 6.3 V, X7R, 1210, ceramic, AEC-Q200
47 µF, 10 V, X7S, 1210, ceramic, AEC-Q200
TDK
Murata
2
3
TDK
COUT
Murata
22 µF, 16 V, X7R, 1210, ceramic, AEC-Q200
TDK
Coilcraft
Cyntec
0.76 µH, 4.9 mΩ, 11.8 A, 4.0 × 4.0 × 3.1 mm, AEC-Q200
1 µH, 9.1 mΩ, 7.9 A, 4.2 × 4.0 × 2.1 mm, AEC-Q200
1 µH, 9.6 mΩ, 14.7 A, 5.3 × 5.1 × 3.0 mm, AEC-Q200
1 µH, 12 mΩ, 11.6 A, 4.1 × 4.1 × 3.1 mm, AEC-Q200
LM63460-Q1 synchronous buck converter, AEC-Q100
VCHA042A-1R0M
LO
U1
1
1
TDK
SPM5030VT-1R0M-D
74438357010
Würth Electronik
Texas Instruments
LM63460AASQRYFRQ1
(1) See the Third-Party Products Disclaimer.
More generally, the LM63460-Q1 converter is designed to operate with a wide range of external components and
system parameters. However, the integrated loop compensation is optimized for a certain range of buck
inductance and output capacitance. As a starting point, 表 9-3 provides typical component values for several
common application configurations.
表9-3. Typical External Component Values
Typical COUT Components
fSW (kHz) VOUT (V) LO (µH) COUT-EFF(min) (µF)
CFF (pF)
RFBT (kΩ) RFBB (kΩ)
RFF (kΩ)
(1210, X7R)
2100
2100
400
3.3
5
0.68
0.76
2.2
50
30
3 × 47 µF, 6.3 V or 4 × 22 µF, 16 V
2 × 47 µF, 10 V or 3 × 22 µF, 16 V
3 × 100 µF, 4 V
100
100
80.6
100
100
43.2
24.9
100
10
10
22
15
15
1
1
1
1
1
1.8
3.3
5
120
70
400
3.3
3 × 47 µF, 6.3 V or 5 × 22 µF, 16 V
3 × 47 µF, 10 V or 4 × 22 µF, 16 V
43.2
24.9
400
4.7
50
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表9-3. Typical External Component Values (continued)
Typical COUT Components
(1210, X7R)
fSW (kHz) VOUT (V) LO (µH) COUT-EFF(min) (µF)
CFF (pF)
RFBT (kΩ) RFBB (kΩ)
100 9.09
RFF (kΩ)
400
12
6.8
20
3 × 22 µF, 25 V
4.7
1
Note that the minimum output capacitances listed in 表 9-3 represents effective values for ceramic capacitors
derated for DC bias voltage and temperature.
9.2.1.2 Detailed Design Procedure
The following design procedure applies to the schematic of 图9-1.
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM63460-Q1 converter with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Setting the Output Voltage
The LM63460-Q1 uses a feedback divider network to set the output voltage. The divider network comprises top
and bottom feedback resistors designated as RFBT and RFBB, respectively. The resistances of the feedback
divider are a compromise between excessive noise pickup and quiescent current consumption. Lower resistance
values reduce noise sensitivity but also impact light-load efficiency. The recommended value for RFBT is 100 kΩ
with a maximum value of 1 MΩ. If 1 MΩ is selected for RFBT, then use a feedforward capacitor in parallel to
provide adequate loop phase margin. Use 方程式 1 to find RFBB for a given value of RFBT. Choosing RFBT and
R
FBB values of 102 kΩand 25.5 kΩ, respectively, sets the output voltage at exactly 5 V.
9.2.1.2.3 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses, resulting in higher system efficiency and less
power dissipated in the converter. However, higher switching frequency enables the use of smaller inductors and
capacitors, enabling a more compact design.
Many automotive applications require that the AM radio band be strictly avoided. Such applications tend to
operate at either 2.1 MHz or 400 kHz, above and below the AM band, respectively. To achieve small solution
size, set the LM63460-Q1 switching frequency at 2.1 MHz for this application example by installing a 6.04-kΩ
resistor from RT to GND.
9.2.1.2.4 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current, which is normally chosen to be in the range of 20% to 40% of the
maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current for systems with a fixed input voltage. For systems with a variable input voltage such as
the 12-V automotive battery, 25% is commonly used.
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When selecting the ripple current for applications with lower maximum load than the maximum available from the
device, the maximum device current must still be used. Use 方程式 7 to determine the value of inductance. The
constant K is the percentage of peak-to-peak inductor current ripple to rated output current. Choose K = 0.3 for
this 5-V, 6-A, 2.1-MHz example, resulting in an inductance of approximately 0.8 µH.
(7)
The saturation current rating of the inductor must be higher than the high-side switch current limit, IL-HS (see the
Electrical Characteristics). This prevents inductor saturation during an overload condition on the output. While an
output short-circuit condition causes the LM63460-Q1 to enter hiccup mode, an overload condition can hold the
output current at current limit without triggering hiccup. When the inductor core material saturates, the
inductance can fall to a low value, causing the inductor current to rise rapidly. Although the valley current limit,
IL-LS, reduces the risk of current runaway, a saturated inductor causes the instantaneous current to increase to a
high value. This can lead to component damage, so it is crucial to avoid inductor saturation.
Inductors with a ferrite core material have hard saturation characteristics but usually have lower core losses than
powdered iron cores. Powdered iron cores exhibit a soft saturation, allowing some relaxation in the current rating
of the inductor. However, they typically have higher core losses at frequencies above 1 MHz.
To avoid subharmonic oscillation, the inductance value must not be less than that given by 方程式 8. The
maximum inductance is limited by the minimum current ripple required for current-mode control to perform
correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the
converter maximum rated current under nominal conditions.
(8)
方程式8 assumes that this design must operate with the input voltage near or in dropout. Use 方程式9 instead if
the minimum input voltage for a given design is high enough to limit the duty cycle to less than 40%.
(9)
9.2.1.2.5 Output Capacitor Selection
The value of the output capacitor and its ESR determine the output voltage ripple and load transient
performance. The output capacitor is usually determined by load transient and stability requirements rather than
the output voltage ripple. Use 表 9-4 to select the output capacitance and CFF feedforward capacitance values
for a few common applications. Use a 1-kΩRFF in series with CFF to further improve noise performance.
表9-4. Recommended Output Capacitors and CFF Values
3.3-V OUTPUT
5-V OUTPUT
CONFIGURATIO
N
COUT
CFF
COUT
CFF
2.1 MHz –
Ceramic
4 × 22 µF, 16 V ceramic
10 pF
2 × 47 µF, 10-V ceramic
10 pF
2.1 MHz –
Alternative
2 × 22 µF, 16-V ceramic + 100 µF, 10-mΩ
2 × 47 µF, 10-V ceramic + 100 µF, 10-mΩ
–
–
electrolytic
electrolytic
400 kHz –
Ceramic
5 × 22 µF, 16-V ceramic
15 pF
3 × 47 µF, 10-V ceramic
15 pF
400 kHz –
Alternative
2 × 22 µF, 16-V ceramic + 100 µF, 10-mΩ
1 × 47 µF, 10 V ceramic + 100 µF, 10-mΩ
–
–
electrolytic
electrolytic
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备注
Most ceramic capacitors deliver less capacitance than the rating of the capacitor indicates. Be sure to
check selected capacitors for initial accuracy, temperature derating, and particularly voltage derating.
表 9-4 assumes typical derating for X7R-dielectric capacitors. If lower voltage or lower temperature-
rated capacitors are used, more capacitance than listed can be required.
More conveniently, 方程式10 calculates the required effective ceramic capacitance for a given application:
(10)
where FC is the target loop crossover frequency in units of kHz, which can be set at 10% to 15% of switching
frequency and up to a maximum of 100 kHz.
This example requires improved transient performance, resulting in two 47-µF, 10-V, X7R ceramics as the output
capacitance and 10 pF for CFF. An alternative configuration is to use a low-ESR electrolytic capacitor in parallel
with a reduced ceramic capacitance.
9.2.1.2.6 Input Capacitor Selection
Input capacitors are necessary to limit the input ripple voltage of the converter due to switching-frequency AC
currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over a
wide temperature range. 方程式 11 gives the input capacitor RMS current, where D = VOUT/VIN is the converter
duty cycle. The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of
the capacitors must be greater than half the output current.
DIL2
12
≈
’
D∂ IOUT2 ∂ 1-D +
∆
÷
÷
◊
ICIN,rms
=
(
)
∆
«
(11)
Ideally, the DC and AC components of input current to the buck stage are provided by the input voltage source
and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source current of
amplitude (IOUT – IIN) during the D interval and sink IIN during the 1 – D interval. Thus, the input capacitors
conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resultant capacitive
component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, 方程
式12 gives the peak-to-peak ripple voltage amplitude:
IOUT ∂D ∂ 1- D
(
)
+ IOUT ∂RESR
DV
=
IN
FSW ∂CIN
(12)
(13)
方程式13 gives the input capacitance required for a particular load current:
D∂ 1-D ∂I
(
)
OUT
CIN
í
FSW ∂ DVIN -RESR ∂IOUT
where
• ΔVIN is the input voltage ripple specification.
The Enhanced HotRod QFN package of the LM63460-Q1 provides two input voltage pins and two power ground
pins on opposite sides of the package. This allows the input capacitors to be split and placed optimally with
respect to the internal power MOSFETs, thus improving the effectiveness of the input bypassing. The converter
requires a minimum of two 4.7-µF ceramic input capacitors, preferably with X7R or X7S dielectric and in 1206 or
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1210 footprint. In this example, place two 10-μF, 50-V ceramic capacitors in a symmetrical layout immediately
adjacent to the converter –one at each input-to-ground pin pair: [VIN1, PGND1] and [VIN2, PGND2].
Install additional capacitance for automotive applications to meet conducted EMI specifications, such as CISPR
25 Class 5 (that limits EMI over a frequency range from 150 kHz to 108 MHz). For example, place a 10-nF, 0402
ceramic capacitor at each input-to-ground pin pair immediately adjacent to the converter. These capacitors
minimize the parasitic inductance in the switching loops and can suppress switch-node voltage overshoot and
ringing, which reduces high-frequency EMI. The two 10-nF capacitors, designated as CIN-HF1 and CIN-HF2 in 图
9-1, must be rated at 50 V with an X7R or better dielectric.
As discussed in 节 9.3, a moderate-ESR electrolytic bulk capacitance (68 µF to 100 µF) at the input in parallel
with the ceramics provides low-frequency filtering and parallel damping to mitigate the effects of input parasitic
inductance resonating with the low-ESR, high-Q ceramic input capacitors. This is especially true if long leads or
traces are used to connect the input supply to the converter.
9.2.1.2.7 Bootstrap Capacitor
The LM63460-Q1 requires a bootstrap capacitor connected between the CBOOT and SW pins. This capacitor
stores energy that is used to supply the gate driver for the integrated high-side power MOSFET. Use a 100-nF,
X7R-dielectric, ceramic capacitor rated for at least 10 V.
9.2.1.2.8 VCC Capacitor
The VCC pin is the output of the internal LDO subregulator used to supply the control circuits of the converter.
Connect a 1-μF, 16-V ceramic capacitor from VCC to AGND for proper operation. In general, avoid loading VCC
with any external circuitry. However, VCC can be used as the pullup supply for the PGOOD indicator – a 100-
kΩ pullup resistor is a good choice in this case. Note that VCC remains high when VEN-WAKE < VEN < VEN-TH
.
The nominal VCC voltage is 3.3 V. Do not short VCC to ground or connect to an external voltage.
9.2.1.2.9 BIAS Power Connection
Because the output voltage is 5 V in this design, connect the BIAS pin to VOUT to reduce the VCC LDO power
loss. The output voltage is supplying the LDO current instead of the input voltage. The power saving is IVCC
×
(VIN – VOUT). The power saving is more significant when VIN is much higher than VOUT and at high switching
frequencies. To prevent output voltage noise and transients from coupling to BIAS, add a series resistor between
1 Ωand 10 Ωbetween VOUT and BIAS. In addition, add a bypass capacitor with a value of 1 μF or higher close
to the BIAS pin to filter noise. Note the maximum allowed voltage on BIAS is 16 V.
9.2.1.2.10 Feedforward Network
Use a feedforward capacitor, CFF, to improve the phase margin and transient response of converter circuits that
have low-ESR output capacitors. Because this capacitor can conduct noise from the output of the circuit directly
to the FB node of the IC, connect a 1-kΩ resistor, designated as RFF in 图 9-1, in series with CFF. If the ESR
zero of the output capacitor is below 200 kHz, feedforward network components are not required.
Capacitor CFF has little effect if the output voltage is less than 2.5 V, so it can be omitted. If the output voltage
setpoint is greater than 14 V, do not use CFF because it introduces too much gain at higher frequencies. Use the
LM63460-Q1 quickstart calculator to review bode plot performance for a given combination of output
capacitance and feedforward capacitance.
9.2.1.2.11 Input Voltage UVLO
In some cases, an input UVLO level different than that provided internal to the device is required. Based on the
circuit shown in 图9-1, VIN(on) and VIN(off) designate the input voltages thresholds at which the converter turns on
and off, respectively. First, choose a value for the lower resistance RENB in the range of 10 kΩ to 100 kΩ. Then
use 方程式14 to calculate the upper resistance RENT based on a target input voltage turn-on threshold of 5.9 V.
(14)
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Selecting upper and lower resistances of 365 kΩand 100 kΩgives input voltage turn-on and turn-off thresholds
of 5.87 V and 4.23 V, respectively.
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9.2.1.3 Application Curves
Unless otherwise indicated, VIN = 13.5 V, VOUT = 5 V, IOUT = 6 A, fSW = 2.1 MHz, AUTO mode, and TA = 25°C. 图
9-1 shows the circuit schematic with relevant BOM components specified in 表9-2.
100
95
90
85
80
75
5.1
5.05
5
4.95
4.9
VIN = 8 V
VIN = 8 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
图9-3. LM63460-Q1 Load and Line Regulation
图9-2. LM63460-Q1 Efficiency
EN 2 V/DIV
VIN 2 V/DIV
VOUT 1 V/DIV
IOUT 2 A/DIV
VOUT 1 V/DIV
IOUT 2 A/DIV
2 ms/DIV
2 ms/DIV
图9-4. LM63460-Q1 Start-Up,
6-A Resistive Load
图9-5. LM63460-Q1 Enable On and Off,
6-A Resistive Load
VOUT 200 mV/DIV
VOUT 200 mV/DIV
IOUT 2 A/DIV
IOUT 2 A/DIV
100 ꢀs/DIV
100 ꢀs/DIV
图9-6. LM63460-Q1 Load Transient,
图9-7. LM63460-Q1 Load Transient,
IOUT = 3 A to 6 A
IOUT = 0 A to 6 A
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VOUT 2 V/DIV
VOUT 2 V/DIV
IL 5 A/DIV
IL 5 A/DIV
20 ms/DIV
20 ms/DIV
图9-8. LM63460-Q1 Short-Circuit Hiccup
图9-9. LM63460-Q1 Short-Circuit Recovery to No
Load
VIN 5 V/DIV
VIN 2 V/DIV
VOUT 2 V/DIV
VOUT 5 V/DIV
IL 1 A/DIV
IL 2 A/DIV
10 ꢀs/DIV
2 ms/DIV
图9-10. LM63460-Q1 Line Transient and Recovery
图9-11. LM63460-Q1 Frequency Foldback in
from Dropout
Dropout, VIN = 3 V
76-mm × 38-mm, 4-layer PCB
76-mm × 38-mm, 4-layer PCB
图9-12. Thermal Performance, 4-A Load
图9-13. Thermal Performance, 6-A Load
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Peak detector
Average detector
Peak detector
Average detector
S t a r t 3 0 M H z
S t o p 1 0 8 M H z
S t a r t 150 k H z
S t o p
3 0 M H z
图9-15. CISPR 25 Class 5 Conducted EMI,
图9-14. CISPR 25 Class 5 Conducted EMI,
30 MHz to 108 MHz
150 kHz to 30 MHz
PK detector
PK detector
QPK detector
AVG detector
QPK detector
AVG detector
图9-17. CISPR 25 Class 5 Radiated EMI, Bicon
Antenna, Vertical Polarization, 30 MHz to 200 MHz
图9-16. CISPR 25 Class 5 Radiated EMI, Bicon
Antenna, Horizontal Polarization, 30 MHz to 200
MHz
PK detector
QPK detector
AVG detector
PK detector
QPK detector
AVG detector
图9-19. CISPR 25 Class 5 Radiated EMI, Log
图9-18. CISPR 25 Class 5 Radiated EMI, Log
Antenna, Vertical Polarization, 200 MHz to 1 GHz
Antenna, Horizontal Polarization, 200 MHz to 1 GHz
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9.2.2 Design 2 –Automotive Synchronous Buck Regulator at 400 kHz
图 9-20 shows the schematic diagram of a synchronous buck regulator with an output voltage set at 3.3 V and a
rated load current of 6 A. The RT resistor of 33.2 kΩsets the switching frequency at 400 kHz.
In this example, the target half-load and full-load efficiencies are 94.5% and 91.5%, respectively, based on a
nominal input voltage of 12 V that ranges from 4 V to 36 V. The switching frequency is set at 400 kHz. The BIAS
input is connected to the 3.3-V output, thus reducing IC bias power dissipation and improving efficiency
performance.
VIN = 4 V...36 V
U1
VIN1
VIN2
CIN1
2 ꢀ 10
CIN2
CIN-HF1
10 nF
CIN-HF2
10 nF
2 ꢀ 10
F
F
PGND1
PGND2
Precision
enable for
VIN UVLO
VOUT
LM63460-Q1
Optional external bias
LO
VOUT = 3.3 V
IOUT = 6 A
BIAS
RPG
100 k
RENT
Synchronization
(200 kHz to 2.2 MHz)
SW
175 k
3.3
H
PGOOD
COUT
2 ꢀ 100
CBOOT
PGOOD indicator
CSYNC
0.1
F
F
SYNC
EN/SYNC
RT
CBOOT
FB
1 nF
RFBT
RENB
optional
VCC
100 k
RRT
33.2 k
100 k
GND
CVCC
RFBB
1
F
43.2 k
RFF
1 k
CFF
15 pF
Feedforward network
图9-20. Application Circuit 2 –3.3 V, 6 A at 400 kHz
备注
Depending on the source impedance of the input supply bus, an electrolytic capacitor can be required
at the input for stability, particularly at low input voltage and high output current operating conditions.
See the Power Supply Recommendations for more detail.
9.2.2.1 Design Requirements
表 9-5 shows the intended input, output, and performance parameters for this application example. Note that
during cold-crank operation when the input voltage decreases to 4 V, the converter operates close to dropout but
the output voltage remains at its 3.3-V setpoint.
表9-5. Design Parameters
DESIGN PARAMETER
Input voltage range, steady state
Maximum transient input voltage, load dump
Output voltage and full-load current
Switching frequency
VALUE
4 V to 36 V
42 V
3.3 V, 6 A
400 kHz
±1%
Output voltage regulation
IC input current, no-load
< 10 µA
< 1 µA
IC shutdown current
表 9-6 gives the selected buck converter power-stage components with availability from multiple vendors. This
design uses a low-DCR inductor and all-ceramic output capacitor implementation.
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表9-6. List of Materials for Application Circuit 2
REF DES QTY
SPECIFICATION
VENDOR(1)
PART NUMBER
AVX
12105C106K4T2A
CNA6P1X7R1H106K
GCM32EC71H106KA03
CGA6P3X7S1H106M
GRT32EC70J107ME13
GCM32ER70J476KE19L
JMK325B7476KMHTR
XGL5030-332MEC
10 µF, 50 V, X7R, 1210, ceramic, AEC-Q200
TDK
CIN
4
Murata
10 µF, 50 V, X7S, 1210, ceramic, AEC-Q200
100 µF, 6.3 V, X7S, 1210, ceramic, AEC-Q200
47 µF, 6.3 V, X7R, 1210, ceramic, AEC-Q200
TDK
2
3
Murata
COUT
Murata
Taiyo Yuden
Coilcraft
Coilcraft
Cyntec
3.3 µH, 13.3 mΩ, 8.4 A, 5.0 × 5.0 × 3.1 mm, AEC-Q200
3.3 µH, 10 mΩ, 8.6 A, 5.5 × 5.3 × 5.1 mm, AEC-Q200
3.3 µH, 22.5 mΩ, 8.3 A, 6.9 × 6.8 × 2.8 mm, AEC-Q200
3.3 µH, 19 mΩ, 16.6 A, 7.3 × 6.6 × 4.8 mm, AEC-Q200
3.3 µH, 17.1 mΩ, 7.6 A, 7.0 × 6.5 × 4.5 mm, AEC-Q200
XGL5050-332MEC
LO
1
1
VCMT063T-3R3MN5TM
74437349033
Würth Electronik
TDK
SPM6545VT-3R3M-D
LM63460AASQRYFRQ1
LM63460AFSQRYFRQ1
AUTO
U1
LM63460-Q1 synchronous buck converter, AEC-Q100
Texas Instruments
FPWM
(1) See the Third-Party Products Disclaimer.
9.2.2.2 Detailed Design Procedure
Refer to 节9.2.1.2 for detail related to component selection for this 400-kHz design.
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9.2.2.3 Application Curves
Unless otherwise indicated, VIN = 12 V, VOUT = 3.3 V, IOUT = 6 A, fSW = 400 kHz, AUTO mode, and TA = 25°C. 图
9-20 shows the circuit schematic with relevant BOM components specified in 表9-6.
100
95
90
85
80
75
3.36
3.34
3.32
3.3
VIN = 5 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 5 V
3.28
3.26
VIN = 12 V
VIN = 24 V
VIN = 36 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
图9-22. LM63460-Q1 Load and Line Regulation
图9-21. LM63460-Q1 Efficiency
EN/SYNC 2 V/DIV
VIN 2 V/DIV
VOUT 1 V/DIV
IOUT 2 A/DIV
VOUT 1 V/DIV
IOUT 2 A/DIV
1 ms/DIV
1 ms/DIV
图9-24. LM63460-Q1 Enable On/Off,
图9-23. LM63460-Q1 Start-Up,
6-A Resistive Load
6-A Resistive Load
VOUT 200 mV/DIV
VOUT 200 mV/DIV
IOUT 2 A/DIV
IOUT 2 A/DIV
100 ꢀs/DIV
100 ꢀs/DIV
图9-25. LM63460-Q1 Load Transient,
图9-26. LM63460-Q1 Load Transient,
IOUT = 3 A to 6 A
IOUT = 0 A to 6 A
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VOUT 2 V/DIV
VOUT 2 V/DIV
IL 5 A/DIV
IL 5 A/DIV
20 ms/DIV
20 ms/DIV
图9-27. LM63460-Q1 Short Circuit Hiccup
图9-28. LM63460-Q1 Short Circuit Recovery to No
Load
9.3 Power Supply Recommendations
The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and
Recommended Operating Conditions in this data sheet. In addition, the input supply must be capable of
delivering the required input current to the loaded converter. Estimate the average input current with 方程式15.
VOUT ∂IOUT
IIN
=
V ∂ h
IN
(15)
where
• ηis the efficiency.
If the converter is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can
have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability and voltage
transients each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to
dip during a load transient. If the converter is operating close to the minimum input voltage, this dip can cause
false UVLO triggering and a system reset.
The best way to solve such issues is to reduce the distance from the input supply to the converter and use an
electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps
damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range
of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage
steady during large load transients. An ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input circuit
configurations.
The input voltage must not be allowed to suddenly fall below the output voltage. In this scenario, such as a
shorted input test, the output capacitors discharge through the body diode of the internal high-side power
MOSFET. The current is effectively uncontrolled during this condition, possibly causing damage to the device. If
this scenario is considered likely, then connect a Schottky bypass diode between the output and the input supply.
9.4 Layout
9.4.1 Layout Guidelines
Proper PCB design and layout is important in high-current, fast-switching converter circuits (with high current
and voltage slew rates) to achieve reliable device operation and design robustness. Furthermore, the EMI
performance of the converter depends to a large extent on PCB layout.
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图 9-29 denotes the high-frequency switching power loops of the LM63460-Q1 power stage. The topological
architecture of a buck converter means that particularly high di/dt current flows in the power MOSFETs and input
capacitors, and it becomes mandatory to reduce the parasitic inductance by minimizing the effective power loop
areas. For the LM63460-Q1 in particular, note the dual and symmetrical arrangement of the input capacitors
based on the VIN and PGND pins located on each side of the IC package. The high-frequency currents are split
in two and effectively flow in opposing directions such that the related magnetic fields contributions cancel each
other, leading to improved EMI performance.
VIN1
VIN2
High-side
MOSFET
SW
CIN-HF1
CIN-HF2
Low-side
MOSFET
PGND1
PGND2
图9-29. Input Current Loops
The following list summarizes the essential guidelines for PCB layout and component placement to optimze
DC/DC converter performance, including thermals and EMI signature. 图 9-30 shows a recommended layout of
the LM63460-Q1 with optimized placement and routing of the power-stage and small-signal components.
• Place the input capacitors as close as possible to the input pin pairs [VIN1, PGND1] and [VIN2, PGND2]: The
respective VIN and PGND pins pairs are close together (with an NC pin in between to increase clearance),
thus simplifying input capacitor placement. The Enhanced HotRod QFN package provides VIN and PGND
pins on either side of the package to enable a symmetrical layout that helps to minimize switching noise and
EMI.
– Use low-ESR ceramic capacitors with X7R or X7S dielectric from VIN1 to PGND1 and VIN2 to PGND2.
Place an 0402 capacitor close to each pin pair for high-frequency bypass as shown in 图9-30. Use an
adjacent 1206 or 1210 capacitor on each side for bulk capacitance.
– Ground return paths for both the input and output capacitors must consist of localized top-side planes that
connect to the PGND1 and PGND2 pins.
– Use a wide polygon plane on a lower PCB layer to connect VIN1 and VIN2 together and to the input
supply.
• Use a solid ground plane on the PCB layer beneath the top layer with the IC: This plane acts as a noise
shield and a heat dissipation path. Using the PCB layer directly below the IC minimizes the magnetic field
associated with the currents in the switching loops, thus reducing parasitic inductance and switch voltage
overshoot and ringing. Use numerous thermal vias near PGND1 and PGND2 for heatsinking to the inner
ground planes.
• Make the VIN, VOUT, and GND bus connections as wide as possible: These paths must be wide and direct
as possible to reduce any voltage drops on the input or output paths of the converter, thus maximizing
efficiency.
• Locate the buck inductor close to the SW1, SW2, and SW3 pins: Use a short, wide connection trace from the
converter SW pins to the inductor. At the same time, minimize the length (and area) of this high-dv/dt surface
to help reduce capacitive coupling and radiated EMI. Connect the dotted terminal of the inductor to the SW
pins.
• Place the VCC and BOOT capacitors close to their respective pins: The VCC and BOOT capacitors represent
the supplies for the internal low-side and high-side MOSFET gate drivers, respectively, and thus carry high-
frequency currents. Locate CVCC close to the VCC pin and place a GND via at its return terminal to connect to
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the GND plane and thus back to IC GND at the exposed pad. Connect CBOOT close to the CBOOT and SW4
pins.
• Place the feedback divider as close as possible to the FB pin: Reduce noise sensitivity of the output voltage
feedback path by placing the resistor divider close to the FB pin, rather than close to the load. This reduces
the FB trace length and related noise coupling. The FB pin is the input to the voltage-loop error amplifier and
represents a high-impedance node sensitive to noise. The connection to VOUT can be somewhat longer.
However, this latter trace must not be routed near any noise source (such as the switch node) that can
capacitively couple into the feedback path of the converter.
• Provide enough PCB area for proper heatsinking: Use sufficient copper area to achieve a low thermal
impedance commensurate with the maximum load current and ambient temperature conditions. Provide
adequate heatsinking for the LM63460-Q1 to keep the junction temperature below 150°C. For operation at
full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking
vias to connect the exposed pad (GND) of the package to the PCB ground plane. If the PCB has multiple
copper layers, connect these thermal vias to inner-layer ground planes. Make the top and bottom PCB layers
preferably with two-ounce copper thickness (and no less than one ounce).
9.4.1.1 Thermal Design and Layout
For a DC/DC converter to be useful over a particular temperature range, the package must allow for the efficient
removal of the heat produced while keeping the junction temperature within rated limits. The LM63460-Q1
converter is available in a small 3.5-mm × 4-mm 22-pin Enhanced HotRod QFN (RYF) package to cover a range
of application requirements. The Thermal Information table summarizes the thermal metrics of this package, with
related detail provided by the Semiconductor and IC Package Thermal Metrics Application Report.
The 22-pin Enhanced HotRod QFN package offers a means of removing heat from the semiconductor die
through the exposed thermal pad at the base of the package. The exposed pad of the package is thermally
connected to the substrate of the LM63460-Q1 device (ground). This allows a significant improvement in
heatsinking, and it becomes imperative that the PCB is designed with thermal lands, thermal vias, and one or
more ground planes to complete the heat removal subsystem. The exposed pad of the LM63460-Q1 is soldered
to the ground-connected copper land on the PCB directly underneath the device package, reducing the IC
thermal resistance to a very low value.
Preferably, use a four-layer board with 2-oz copper thickness for all layers to provide low impedance, proper
shielding and lower thermal resistance. Numerous vias with a 0.3-mm diameter connected from the thermal land
(and from the area around the PGND1 and PGND2 pins) to the internal and solder-side ground planes are vital
to promote heat transfer. In a multi-layer PCB design, a solid ground plane is typically placed on the PCB layer
below the power-stage components. Not only does this provide a plane for the power-stage currents to flow, but
it also represents a thermally conductive path away from the heat-generating devices.
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9.4.2 Layout Example
Legend
Top layer copper
Layer-2 GND plane
Top solder
VOUT
Inductor
Output
capacitors
Output
capacitors
Keep the switch node
copper area small
Position the output
capacitors adjacent to the
inductor to provide shielding
Place several PGND
vias close to the IC
for heat spreading
SW
PGND2
Input
capacitor
Input
capacitor
PGND1
Position the input
capacitors very close to
the VIN and PGND pins
GND
VIN1
VIN2
Place the boot capacitor close
to the CBOOT and SW pins
Place the feedback
components close
to the FB pin
VCC
FB
BIAS
GND
图9-30. PCB Layout Example
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10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.1.2 Development Support
With an input operating voltage as low as 3 V and up to 36 V as specified in 表 10-1, the LM6k-Q1 family of
automotive synchronous buck converters from TI provides flexibility, scalability and optimized solution size for a
range of applications. These converters enable DC/DC solutions with high density, low EMI and increased
flexibility. Available EMI mitigation features include pseudo-random spread spectrum (PRSS), integrated input
bypass capacitors, RBOOT-configured switch-node slew rate control, and optimized package design with
symmetrical VIN and PGND pins that shield a small switch-node copper area. All converters are rated for a
maximum operating junction temperature of 150°C, have AEC-Q100 grade 1 qualification, and are functional
safety capable.
表10-1. Automotive Synchronous Buck DC/DC Converter Family
DC/DC CONVERTER
RATED IOUT
PACKAGE
FEATURES
EMI MITIGATION
LM60430-Q1, LM60440-Q1 3 A, 4 A
WQFN (13)
400 kHz fixed fSW, 3 × 2-mm package
Shielded switch node
LM63610-Q1, LM63615-Q1, 1 A, 1.5 A, 2.5 A, WSON (12),
RT adjustable fSW, MODE/SYNC
RT adjustable fSW, EN/SYNC
PRSS
LM63625-Q1, LM63635-Q1 3.25 A
HTSSOP (16)
LM61430-Q1, LM61435-Q1, 3 A, 3.5 A, 4 A,
LM61440-Q1, LM61460-Q1 6 A
PRSS, RBOOT
LM62435-Q1, LM62440-Q1 3.5 A, 4 A
2.1 MHz default fSW, MODE/SYNC
RT adjustable fSW, EN/SYNC
VQFN-HR (14)
LMQ61460-Q1
LMQ62440-Q1
6 A
4 A
PRSS, RBOOT,
integrated capacitors
2.1 MHz default fSW, MODE/SYNC
LM62460-Q1, LM61480-Q1,
LM61495-Q1
6 A, 8 A, 10 A
6 A
VQFN-HR (16) RT adjustable fSW, MODE/SYNC
DRSS, RBOOT
PRSS
LM63460-Q1
LM64460-Q1
RT adjustable fSW, EN/SYNC, pin FMEA
VQFN-FCRLF
(22)
2.1 MHz default fSW, MODE/SYNC, pin FMEA
For development support see the following:
• LM63460-Q1 EVM User's Guide
• LM63460-Q1 Quickstart Calculator
• LM63460-Q1 Simulation Models
• LM63460-Q1 EVM Altium Layout Files
• For TI's reference design library, visit TI Designs.
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center.
• To design a low-EMI power supply, review TI's comprehensive EMI Training Series.
• TI Reference Designs:
– 30-W Power For Automotive Dual USB Type-C™ Charge Port Reference Design
– High Efficiency, Low Noise, 5-V/3.3-V/1.8-V/1.1-V Automotive Display Reference Design
• Technical Articles:
– How Device-level Features And Package Options Can Help Minimize EMI In Automotive Designs
– Optimizing Flip-chip IC Thermal Performance In Automotive Designs
– Powering Levels Of Autonomy: A Quick Guide To DC/DC Solutions For SAE Autonomy Levels
– Powering Infotainment Systems Of The Future
• To view related devices of this product, see the LM64460-Q1 6-A converter and the TPSM63606 6-A power
module.
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10.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM63460-Q1 converter with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
• Texas Instruments, Enhanced HotRod™ QFN Package: Achieving Low EMI Performance in Industry’s
Smallest 4-A Converter application report
• Texas Instruments, Designing High Performance, Low-EMI, Automotive Power Supplies application report
• Texas Instruments, EMI Filter Components And Their Nonidealities For Automotive DC/DC Regulators
technical brief
• Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report
• Texas Instruments, AN-2162 Simple Success With Conducted EMI From DC/DC Converters Application
Report application report
• Texas Instruments, Practical Thermal Design With DC/DC Power Modules application report
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
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10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PLM63460AASQRYFTQ1
ACTIVE VQFN-FCRLF
RYF
22
250
TBD
Call TI
Call TI
-40 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
VQFN-FCRLF - 1.05 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RYF0022A
3.6
3.4
A
B
(0.2)
4.1
3.9
PIN 1 INDEX AREA
0.1 MIN
(0.1)
SECTION A-A
TYPICAL
C
1.05
0.95
SEATING PLANE
0.08
C
0.01
0.00
2X 2.5
(0.20) TYP
1.7±0.1
12
7
0.6
0.5
18X
SYMM
2X 3
℄
2.2±0.1
22X (0.18)
18X
A
A
0.3
0.2
1
0.1
C A
B
0.05
C
22
18
SYMM
0.3
0.2
8X
PIN 1 ID
22X (0.5)
℄
0.1
C A B
0.05
C
4226203/B 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-FCRLF - 1.05 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RYF0022A
2X (2.5)
SYMM
℄
22X (0.25)
22X (0.5)
(0.6)
22
19
18
1
18X (0.75)
SYMM
(3.65)
2X (3)
(2.2)
℄
(0.85)
13
7
(R0.05) TYP
(Ø0.2) TYP
8
12
(1.7)
(3.15)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226203/B 12/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-FCRLF - 1.05 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RYF0022A
2X (2.5)
SYMM
22X (0.5)
22X (0.25)
℄
19
22
18
1
18X (0.75)
(0.59)
SYMM
(3.65)
2X (3)
℄
2X (0.98)
13
7
(R0.05) TYP
8
12
2X (1.55)
(3.15)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD:
81% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
4226203/B 12/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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SI9137LG
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SI9122E
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