POPA210IDBVR [TI]
OPAx210 2.2-nV/âHz Precision, Low-Power, 36-V Operational Amplifiers;
| 型号： | POPA210IDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OPAx210 2.2-nV/âHz Precision, Low-Power, 36-V Operational Amplifiers |
| 文件： | 总38页 (文件大小：2408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA210,OPA2210
SBOS924F – SEPTEMBER 2018 – REVISED JANUARY 2021
OPAx210 2.2-nV/√Hz Precision, Low-Power, 36-V Operational Amplifiers
1 Features
3 Description
•
Precision super beta input performance:
– Low offset voltage: 5 µV (typical)
– Ultra-low drift: 0.1 µV/°C (typical)
– Low input bias current: 0.3 nA (typical)
Ultra-low noise:
– Low 0.1-Hz to 10-Hz noise: 90 nVPP
– Low voltage noise: 2.2 nV/√ Hz at 1 kHz
High CMRR: 132 dB (minimum)
Gain bandwidth product: 18 MHz
Slew rate: 6.4 V/µs
Low quiescent current: 2.5 mA/channel (maximum)
Short-circuit current: ±65 mA
Wide supply range: ±2.25 V to ±18 V
No phase reversal
Rail-to-rail output
Industry-standard packages
The OPA210 and OPA2210 (OPAx210) are the next
generation of OPAx209 operational amplifier (op
amp). The OPAx210 precision op amps are built on
TI's precision, super-beta, complementary bipolar
semiconductor process, which offers ultra-low flicker
noise, low offset voltage, and low offset voltage
temperature drift.
•
The OPAx210 achieve very low voltage noise density
(2.2 nV/√Hz) while consuming only 2.5 mA
(maximum) per amplifier. These devices also offer
rail-to-rail output swing, which helps maximize
dynamic range.
•
•
•
•
•
•
•
•
•
In precision data-acquisition applications, the
OPAx210 provide fast settling time to 16-bit accuracy,
even for 10-V output swings. Excellent ac
performance, combined with only 35 µV (maximum) of
offset and 0.6 µV/°C (maximum) drift over
temperature, makes the OPAx210 an excellent choice
for high-speed, high-precision applications.
2 Applications
•
•
•
•
•
•
•
•
Ultrasound scanner
The OPAx210 are specified over a wide dual power-
supply range of ±2.25 V to ±18 V, or single-supply
operation from 4.5 V to 36 V, are specified from –40°C
to +125°C,.
Multiparameter patient monitor
Merchant network and server PSU
Semiconductor test
Spectrum analyzer
Lab and field instrumentation
Data acquisition (DAQ)
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
3.00 mm × 3.00 mm
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
3.00 mm × 3.00 mm
SOIC (8)
Professional microphone and wireless systems
OPA210 (Preview)
VSSOP (8)
SOIC (8)
OPA2210
VSSOP (8)
WSON (8)
(1) For all available packages, see the package option
addendum at the end of the data sheet.
20%
17.5%
15%
12.5%
10%
7.5%
5%
2.5%
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2 0.3 0.4 0.5 0.6
Time (1 s/div)
Offset Voltage Drift (mV/èC)
OPAx210 0.1-Hz to 10-Hz Noise
OPAx210 Offset Voltage Drift Distribution
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
OPA210, OPA2210
SBOS924F – SEPTEMBER 2018 – REVISED JANUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information: OPA210 ................................... 5
6.5 Thermal Information: OPA2210 ................................. 5
6.6 Electrical Characteristics ............................................6
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................18
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Application.................................................... 20
8.3 System Example.......................................................21
9 Power Supply Recommendations................................22
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................23
11.1 Device Support........................................................23
11.2 Documentation Support.......................................... 24
11.3 Receiving Notification of Documentation Updates..24
11.4 Support Resources................................................. 24
11.5 Trademarks............................................................. 24
11.6 Electrostatic Discharge Caution..............................24
11.7 Glossary..................................................................24
12 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (Novembver 2020) to Revision F (January 2021)
Page
•
Added OPA210 device with D and DGK packages as advanced information (preview).................................... 1
Changes from Revision D (January 2020) to Revision E (November 2020)
Page
•
Changed OPA2210 DRG package from advanced information (preview) to production data (active)............... 1
Changes from Revision C (September 2019) to Revision D (January 2020)
Page
•
Added OPA2210 DRG package to data sheet as advanced information (preview)............................................1
Changes from Revision B (March 2019) to Revision C (September 2019)
Page
•
•
Changed super-ß to super beta for easier searching ........................................................................................ 1
Added SOIC package.........................................................................................................................................1
Changes from Revision A (December 2018) to Revision B (February 2019)
Page
Changed "OPAx145" to "OPA2210"..................................................................................................................19
Fixed link to TIDA-01427 ................................................................................................................................. 21
•
•
Changes from Revision * (September 2018) to Revision A (December 2018)
Page
•
First release of production-data data sheet ....................................................................................................... 1
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5 Pin Configuration and Functions
NC
–IN
+IN
V–
1
2
3
4
8
7
6
5
NC
V+
–
+
OUT
NC
Not to scale
Figure 5-1. OPA210: D (8-Pin SOIC, Preview) and DGK (8-Pin VSSOP, Preview) Packages, Top View
Table 5-1. Pin Functions: OPA210
PIN
I/O
DESCRIPTION
NAME
–IN
NO.
2
I
Inverting input
+IN
NC
3
I
Noninverting input
1, 5, 8
—
O
—
—
No internal connection
Output
OUT
V–
6
4
7
Negative (lowest) power supply
Positive (highest) power supply
V+
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
A
OUT B
-IN B
+IN B
B
Figure 5-2. OPA2210: D (SOIC-8), DGK (VSSOP-8), and DRG (WSON-8) Packages, Top View
Table 5-2. Pin Functions: OPA2210
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
I
I
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
3
6
I
5
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) power supply
Positive (highest) power supply
V+
8
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
(V–) – 0.5
–10
MAX
UNIT
V
Supply voltage, VS = (V+) – (V–)
40
Voltage
Signal input pins(2)
(V+) + 0.5
Signal input pins
Differential
1
Signal input pins(2)
Output short circuit(3)
Junction, TJ
10
mA
Current
Continuous
150
150
Temperature
°C
Storage temperature, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the de vice. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under
Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device
reliability.
(2) For input voltages beyond the power-supply rails, voltage orcurrent must be limited.
(3) Short circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2.25
–40
MAX
±18
UNIT
Specified voltage, VS
V
Specified temperature
Operating temperature, TA
125
150
°C
°C
–55
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6.4 Thermal Information: OPA210
OPA210
THERMAL METRIC(1)
D (SOIC)
8 PINS
135.5
73.7
DGK (VSSOP)
8 PINS
142.6
46.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
61.9
63.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
19.7
5.3
ψJB
54.8
62.8
RθJC(bottom)
N/A
N/A
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
6.5 Thermal Information: OPA2210
OPA2210
THERMAL METRIC(1)
D (SOIC)
8 PINS
126.1
65.7
DGK (VSSOP) DRG (SON)
UNIT
8 PINS
132.7
38.5
52.1
2.4
8 PINS
52.1
51.8
24.8
1.1
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
69.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
17.4
ψJB
68.9
52.8
n/a
24.8
9.0
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
at VS = ±15 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM =VOUT = midsupply (unless otherwise noted)
PARAMETER
OFFSET VOLTAGE
VOS Input offset voltage
dVOS/dT Input offset voltage drift
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VS = ±15 V, VCM = 0 V
±5
±35
µV
TA = –40°C to 125°C
±0.1
±0.5 µV/°C
VOS -
Input offset voltage
matching
±5
±35
µV
matching
TA = 25°C
0.05
0.5
±1
PSRR
vs power supply
VS = ±2.25 V to ±18 V
DC
µV/V
µV/V
TA = –40°C to 125°C
Channel separation
±0.1
±0.3
INPUT BIAS OPERATION
TA = 25°C
±2
±4
±7
±2
±4
±7
IB
Input bias current
Input offset current
VCM = 0 V
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 25°C
nA
nA
±0.1
IOS
VCM = 0 V
TA = –40°C to 85°C
TA = –40°C to 125°C
NOISE
en p-p
Input voltage noise
Noise density
f = 0.1 Hz to 10 Hz
f = 10 Hz
0.09
2.5
µVPP
en
f = 100 Hz
2.25
2.2
nV/√Hz
f = 1 kHz
Input current noise
density
In
f = 1 kHz
400
fA/√Hz
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
(V–) + 1.5
132
(V+) – 1.5
V
(V–) + 1.5 V < VCM < (V+) – 1.5 V
140
130
Common-mode rejection
ratio
CMRR
dB
(V–) + 1.5 V < VCM < (V+) – 1.5 V,
TA = –40°C to 125°C
120
INPUT IMPEDANCE
Differential
400 || 9
kΩ || pF
Ω || pF
Common-mode
OPEN-LOOP GAIN
109 || 0.5
TA = 25°C
126
120
114
110
132
120
(V–) + 0.2 V < VO < (V+) –
0.2 V, RL = 10 kΩ
TA = –40°C to 125°C
TA = 25°C
AOL
Open-loop voltage gain
dB
(V–) + 0.6 V < VO < (V+) –
0.6 V, RL = 600 Ω(1)
TA = –40°C to 85°C
FREQUENCY RESPONSE
GBW
SR
Gain bandwidth product
18
6.4
80
MHz
V/µs
Slew rate
Phase margin (Φm)
RL = 10 kΩ, CL = 25 pF
degrees
0.1%, G = –1, 10-V step, CL = 100 pF
0.0015% (16-bit), G = –1, 10-V step, CL = 100 pF
G = –10
2.1
2.6
0.5
tS
Settling time
µs
Overload recovery time
µs
%
Total harmonic distortion
+ noise (THD+N)
G = +1, f = 1 kHz, VO = 20 VPP, 600 Ω
0.000025
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6.6 Electrical Characteristics (continued)
at VS = ±15 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM =VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
RL = 10 kΩ, AOL > 130 dB
(V–) + 0.2
(V–) + 0.6
(V–) + 0.2
(V+) – 0.2
(V+) – 0.6
(V+) – 0.2
Voltage output swing
Short-circuit current
RL = 600 Ω, AOL > 114 dB
RL = 10 kΩ, AOL > 120 dB, TA = –40°C to 125°C
VS = ±18 V
V
ISC
±65
mA
Capacitive load drive
(stable operation)
CLOAD
See Section 6.7
See Section 6.7
Open-loop output
impedance
ZO
POWER SUPPLY
TA = 25°C
2.2
2.5
Quiescent current
(per amplifier)
IQ
IO = 0 A
mA
TA = –40°C to 125°C
3.25
(1) Temperature range limited by thermal performance of the package.
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6.7 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
15%
10%
5%
0
20%
17.5%
15%
12.5%
10%
7.5%
5%
2.5%
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2 0.3 0.4 0.5 0.6
-35 -30 -25 -20 -15 -10 -5
0
5
10 15 20 25 30 35
Offset Voltage Drift (mV/èC)
Input-Referred Offset Voltage (mV)
Figure 6-2. Offset Voltage Drift Distribution
Figure 6-1. Offset Voltage Production Distribution
100
10
10
1
1
100m
0.1
100m
1
10
100
Frequency (Hz)
1k
10k
100k
1
10
100
Frequency (Hz)
1k
10k
100k
Figure 6-3. Input Voltage Noise Spectral Density vs Frequency
Figure 6-4. Input Current Noise Spectral Density vs Frequency
0.01
-80
G -1
G +1
0.001
-100
-120
-140
0.0001
1E-5
100
1k
Frequency (Hz)
10k
Time (1 s/div)
VOUT = 3.5 VRMS
RL = 600 Ω
Figure 6-5. 0.1-Hz to 10-Hz Voltage Noise
Figure 6-6. THD+N Ratio vs Frequency
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
1
0.1
-40
120
90
G -1
G +1
-60
60
0.01
-80
30
0
0.001
0.0001
1E-5
-100
-120
-140
-30
-60
-90
-120
10m
100m 1
Output Amplitude (VRMS
10
)
-50
-25
0
25
50
75
100
125
Temperature (èC)
f = 1 kHz
RL = 600 Ω
5 typical units
Figure 6-8. Input Offset Voltage vs Temperature
Figure 6-7. THD+N vs Output Amplitude
50
30
50
40
Vcm = 13.5 V
Vcm = -13.5 V
30
20
10
10
0
-10
-30
-50
-10
-20
-30
-40
-50
-15
-10
-5
Input Common-mode Voltage (V)
0
5
10
15
0
4
8
12
16
Supply Voltage (V)
20
24
28
32
36
5 typical units
5 typical units
Figure 6-10. Offset Voltage vs Supply Voltage
Figure 6-9. Offset Voltage vs Common-Mode Voltage
160
160
150
140
130
120
0.01
PSRR+
PSRR-
140
120
100
80
0.1
60
40
20
0
100m
1
125
1
10
100
1k
Frequency (Hz)
10k 100k
1M
10M
-50
-25
0
25
50
75
100
Temperature (èC)
Figure 6-11. PSSR vs Frequency
Figure 6-12. PSRR vs Temperature
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
160
140
120
100
80
160
150
140
130
120
0.01
0.1
1
CMRR
60
40
20
100
1k
10k 100k
Frequency (Hz)
1M
10M
-50
-25
0
25
50
75
100
125
Temperature (èC)
Figure 6-13. CMRR vs Frequency
Figure 6-14. CMRR vs Temperature
1000
100
10
140
120
100
80
180
160
140
120
100
80
Gain
Phase
60
40
20
60
0
40
1
10
-20
100m
20
100
1k
10k 100k
Frequency (Hz)
1M
10M
100M
1
10
100 1k 10k 100k 1M 10M
Frequency (Hz)
Figure 6-15. Open-Loop Output Impedance vs Frequency
Figure 6-16. Open-Loop Gain and Phase vs Frequency
160
150
140
130
120
110
100
0.01
0.1
1
20%
10 kW Load
600 W Load
15%
10%
5%
0
10
125
-50
-25
0
25
50
75
100
-2
-1.5
-1
-0.5
0
0.5
1
Positive Input Bias Current (nA)
1.5
2
Temperature (èC)
Figure 6-18. Positive Input Bias Current Production Distribution
Figure 6-17. Open-Loop Gain vs Temperature
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
20%
16%
12%
8%
4%
0
20%
15%
10%
5%
0
-2
-1.5
-1
Negative Input Bias Current (nA)
-0.5
0
0.5
1
1.5
2
-2
-1.5
-1
-0.5
Input Offset Current (nA)
0
0.5
1
1.5
2
Figure 6-19. Negative Input Bias Current Production
Distribution
Figure 6-20. Input Offset Current Production Distribution
1.2
1000
800
600
0.9
400
Ib+
200
0.6
0
Ib-
-200
-400
-600
-800
-1000
0.3
0
Ios
-0.3
-14 -12 -10 -8 -6 -4 -2
0
2
4
6
Input Common-mode Voltage (V)
8
10 12 14
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
Figure 6-22. Positive Input Bias Current vs Common-Mode
Voltage
Figure 6-21. Input Bias and Input Offset Currents vs
Temperature
1000
800
1000
800
600
600
400
400
200
200
0
0
-200
-400
-600
-800
-1000
-200
-400
-600
-800
-1000
-14 -12 -10 -8 -6 -4 -2
0
2
Input Common-mode Voltage (V)
4
6
8
10 12 14
-14 -12 -10 -8 -6 -4 -2
0
2
Input Common-mode Voltage (V)
4
6
8
10 12 14
Figure 6-23. Negative Input Bias Current vs Common-Mode
Voltage
Figure 6-24. Input Offset Current vs Common-Mode Voltage
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
2.5
2.4
2.3
2.2
2.1
2
3.25
3
2.75
2.5
2.25
2
1.9
1.8
1.7
1.6
1.5
1.75
1.5
1.25
1
-50
-25
0
25
50
75
100
125
0
4
8
12
16
20
Supply Voltage (V)
24
28
32
36
Temperature (èC)
Figure 6-26. Quiescent Current vs Temperature
-12
Figure 6-25. Quiescent Current vs Supply Voltage
15
25èC
-12.5
-13
14.5
-40èC
14
13.5
13
125èC
85èC
-13.5
-14
85èC
-40èC
125èC
-14.5
-15
12.5
12
25èC
0
10
20
30
Output Current (mA)
40
50
60
0
10
20
30
Output Current (mA)
40
50
60
A.
A.
Figure 6-28. Output Voltage vs Output Current (Sinking)
Figure 6-27. Output Voltage vs Output Current (Sourcing)
65
Vin (V)
Vout (V)
60
55
50
45
Sinking
Sourcing
40
-50
-25
0
25
50
75
100
125
Time (100 ms/div)
Temperature (èC)
Figure 6-29. Short-Circuit Current vs Temperature
Figure 6-30. No Phase Reversal
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
VOUT
VIN
VOUT
VIN
Time (500 ns/div)
Time (500 ns/div)
G = –10
G = –10
Figure 6-31. Positive Overload Recovery
Figure 6-32. Negative Overload Recovery
Time (1 ms/div)
Time (1 ms/div)
G = +1
10-mV step, CL = 100 pF, RL = 600 Ω
G = –1
10-mV step, CL = 100 pF, RL = 600 Ω
Figure 6-33. Small-Signal Step Response
Figure 6-34. Small-Signal Step Response
Time (1 ms/div)
Time (1 ms/div)
G = +1
10-V step, CL = 100 pF, RL = 600 Ω
G = –1
10-V step, CL = 100 pF, RL = 600 Ω
Figure 6-35. Large-Signal Step Response
Figure 6-36. Large-Signal Step Response
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
80
Falling
Rising
G +1
G -1
60
40
20
0
20
100
Capactiance (pF)
1000
2000
Time (4 ms/div)
10-V step
Figure 6-38. Settling Time
Figure 6-37. Small-Signal Overshoot vs Capacitive Load
140
130
120
110
100
90
80
70
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
PRF = –10 dBm
Figure 6-39. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx210 are the next generation of the OPAx209 operational amplifiers. The OPAx210 offer improved input
offset voltage, offset voltage temperature drift, input bias current, and lower 1/f noise corner frequency. In
addition, these devices offer excellent overall performance with high CMRR, PSRR, and AOL.The OPAx210
precision operational amplifiers are unity-gain stable, and free from unexpected output and phase reversal.
Applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the
device pins. In most cases, 0.1-µF capacitors are adequate. Section 7.2 shows a simplified schematic of the
OPAx210. The die uses a SiGe bipolar process and contains 180 transistors.
7.2 Functional Block Diagram
V+
Pre-Output Driver
OUT
IN-
IN+
V-
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7.3 Feature Description
7.3.1 Operating Voltage
The OPAx210 op amps can be used with single or dual supplies within an operating range of VS = 4.5 V (±2.25
V) up to 36 V (±18 V).
CAUTION
Supply voltages greater than 40 V total can permanently damage the device.
In addition, key parameters are specified over the temperature range of TA = –40°C to +125°C. Parameters that
vary significantly with operating voltage or temperature are shown in Section 6.7.
7.3.2 Input Protection
The input pins of the OPAx210 are protected from excessive differential voltage with back-to-back diodes, as
shown in Figure 7-1. In most circuit applications, the input protection circuitry has no consequence. However, in
low-gain or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the
amplifier cannot respond rapidly enough to the input ramp. This effect is illustrated in Figure 6-35 and Figure
6-36 in Section 6.7. If the input signal is fast enough to create this forward-bias condition, the input signal current
must be limited to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can
be used to limit the signal input current. This input series resistor degrades the low-noise performance of the
OPAx210. See Section 7.3.3 for further information on noise performance.
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Figure 7-1 shows an example configuration that implements a current-limiting feedback resistor.
RF
-
Output
RI
+
Input
Figure 7-1. Pulsed Operation
7.3.3 Noise Performance
Figure 7-2 shows the total circuit noise for varying source impedances with the op amp in a unity-gain
configuration (no feedback resistor network, and therefore, no additional noise contributions). Two different op
amps are shown with the total circuit noise calculated. The OPAx210 have very low voltage noise, making these
devices a great choice for low source impedances (less than 2 kΩ). As a comparable, precision FET-input op
amp (very low current noise), the OPA827 has somewhat higher voltage noise, but lower current noise. The
device provides excellent noise performance at moderate to high source impedance (10 kΩ and up). For source
impedance lower than 300 Ω, the OPA211 may provide lower noise.
The equation in Figure 7-2 shows the calculation of the total circuit noise, with these parameters:
•
•
•
•
•
en = voltage noise,
in = current noise,
RS = source impedance,
k = Boltzmann's constant = 1.38 × 10–23 J/K, and
T = temperature in kelvins
For more details on calculating noise, see Section 8.1.1.
10k
EO
1k
RS
OPAx210
100
OPA827
10
Resistor Noise
EO2 = en2 + (in RS)2 + 4kTRS
1
100
1k
10k
100k
1M
Source Resistance, RS (Ω)
Figure 7-2. Noise Performance of the OPAx210 and OPA827 in Unity-Gain Buffer Configuration
7.3.4 Phase-Reversal Protection
The OPAx210 have internal phase-reversal protection. Many FET- and bipolar-input op amps exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input circuitry of the OPAx210 prevents phase reversal
with excessive common-mode voltage; instead, the output limits into the appropriate rail (see Figure 6-30).
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7.3.5 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress
event. See Figure 7-3 for an illustration of the ESD circuits contained in the OPAx210 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where they meet at an absorption device internal
to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-
current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device has a trigger, or threshold voltage, that is greater than the normal operating voltage of the
OPAx210 but less than the device breakdown voltage level. After this threshold is exceeded, the absorption
device quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit such as the one Figure 7-3 shows, the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.
If this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and
conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption
device.
Figure 7-3 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage, +VS, by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier,
and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise
to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
power supplies +VS, –VS, or both are at 0 V.
Again, the answer depends on the supply characteristic while at 0 V, or at a level less than the input signal
amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be
supplied by the input source through the current steering diodes. This state is not a normal bias condition; the
amplifier will not operate normally. If the supplies are low impedance, then the current through the steering
diodes can become quite high. The current level depends on the ability of the input source to deliver current, and
any resistance in the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external transient voltage
suppressor (TVS) diodes may be added to the supply pins as shown in Figure 7-3. The breakdown voltage must
be selected so that the diode does not turn on during normal operation. However, the breakdown voltage must
be low enough so that the TVS diode conducts if the supply pin begins to rise to greater than the safe operating
supply voltage level.
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TVS(2)
RF
+VS
+V
OPAx210
RI
ESD Current-
Steering Diodes
-In
Out
Op Amp
Core
(3)
RS
+In
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
-V
-VS
TVS(2)
(1) VIN = +VS + 500 mV.
(2) TVS: +VS(max) > VTVSBR (Min) > +VS.
(3) Suggested value approximately 1 kΩ.
Figure 7-3. Equivalent Internal ESD Circuitry and Relation to a Typical Circuit Application
7.4 Device Functional Modes
The OPAx210 are operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum
power-supply voltage for the OPAx210 is 36 V (±18 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx210 are unity-gain stable, precision operational amplifiers with very low noise. Applications with noisy
or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate.
8.1.1 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 7-2. The source impedance is usually fixed; consequently, select the
op amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 8-1 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the
op amp reacts with the feedback resistors to create additional noise components. However, the extremely low
current noise of the OPAx210 means that the device current noise contribution can be neglected.
Generally, the feedback resistor values are chosen to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations.
(A) Noise in Noninverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
42
41 „ 42
2
2
2
¨
:
:
;
;
:
;
:
;
:
;
>
?
84/5
1
'
= l1 + p „ A5
+
A0 + kA4 2 o2
+
E0 „ 45 + lE0 „ d
hp
1
æ4
1
41
41 + 42
GND
œ
EO
8
2
A5
=
4 „ G$ „ 6(-) „ 45
d
h
¥
Thermal noise of RS
+
*V
¾
RS
4
1 „ 42
8
:
3
;
A4
= 4 „ G$ „ 6(-) „ d
¨
h
d
h
Thermal noise of R1 || R2
æ4
2
1
41 + 42
*V
¾
+
,
h
VS
Source
GND
œ
:
:
;
;
4
G$ = 1.38065 „ 10F23
d
Boltzmann Constant
-
Temperature in kelvins
>
?
-
5
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
:
;
42
45 + 41 „ 42
p „ A0 2 + kA4
2 o2 + FE0 „ H
+4 æ4
5
IG
¨
:
:
:
;
;
;
>
84/5
?
6
'
= l1 +
1
1
45 + 41
45 + 41 + 42
RS
œ
EO
:
;
45 + 41 „ 42
8
+
7
A4
=
¨
4 „ G$ „ 6(-) „ H
I
d
h
Thermal noise of (R1 + RS) || R2
+4 æ4
5
1
2
45 + 41 + 42
*V
¾
+
VS
œ
,
GND
G$ = 1.38065 „ 10F23
d
h
:
:
;
;
8
Boltzmann Constant
Source
GND
-
>
?
9
6(-) = 237.15 + 6(°%)
-
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
Where eN is the voltage noise of the amplifier. For the OPAx210 op amp, eN = 2.2 nV/√Hz at 1 kHz.
Where iN is the current noise of the amplifier. For the OPAx210 op amp, iN = 400 fA/√Hz at 1 kHz.
NOTE: For additional resources on noise calculations visit the TI Precision Labs Series.
Figure 8-1. Noise Calculation in Gain Configurations
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8.2 Typical Application
R4
2.94 kꢀ
C5
1 nF
œ
R1
590 ꢀ
R3
499 ꢀ
Output
+
OPAx210
C2
39 nF
Figure 8-2. Low-Pass Filter
8.2.1 Design Requirements
Low-pass filters are commonly used in signal processing applications to reduce noise and prevent aliasing. The
OPAx210 are designed to construct high-speed, high-precision active filters. Figure 8-2 shows a second-order,
low-pass filter commonly encountered in signal-processing applications.
Use the following parameters for this design example:
•
•
•
Gain = 5 V/V (inverting gain)
Low-pass cutoff frequency = 25 kHz
Second-order Chebyshev filter response with 3-dB gain peaking in the pass band
8.2.2 Detailed Design Procedure
The infinite-gain, multiple-feedback circuit for a low-pass network function is shown in Figure 8-2. Use Equation
1 to calculate the voltage transfer function.
-1/ R1R3C2C5
s2 + (s / C2)(1/ R1 +1/ R3 +1/ R4) +1/ R3R4C2C5
Output
Input
(s) =
(1)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by Equation 2:
R4
Gain =
R1
1
fc =
(1/ R3R4C2C5)
2p
(2)
8.2.3 Application Curve
Figure 8-3. OPAx210 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
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8.3 System Example
8.3.1 Time Gain Control System for Ultrasound Applications
During an ultrasound send-receive cycle, the magnitude of reflected signal depends on the depth of penetration.
The ultrasound signal incident on the receiver decreases in amplitude as a function of the time elapsed since
transmission. The time gain control (TGC) system helps achieve the best possible signal-to-noise ratio (SNR),
even with the decreasing signal amplitude. When the image is displayed, similar materials have similar
brightness, regardless of depth. Linear-in-dB gain, which means the decibel gain is a linear function of the
control voltage (VCNTL), is used to generate this image.
There are multiple approaches for a TGC control circuit that are based on the type of DAC. Figure 8-4 shows a
high-level block diagram for the topology using a current-output multiplying DAC (MDAC) to generate the drive
for VCNTL. The op amp used for current-to-voltage (I-to-V) conversion must have low-voltage noise, as well as
low-current noise density. The current density helps reduce the overall noise performance because of the DAC
output configuration. The DAC output can go up to ±10 V; therefore, the op amp must have bipolar operation.
The OPAx210 is used here because of the low-voltage noise density of 2.2 nV/√Hz, low-current noise density of
500 fA/√Hz, rail-to-rail output, and the ability to accept a wide supply range of ±2.25 V to ±18 V and provide rail-
to-rail output. The low offset voltage and offset drift of the OPAx210 facilitate excellent dc accuracy for the circuit.
The OPAx210 is used to filter and buffer the 10-V reference voltage generated by the REF5010. The REF5010
serves as the reference voltage for the DAC8802, which generates a current output on IOUT corresponding to the
digital input code. The IOUT pin of the DAC8802 is connected to the virtual ground (negative terminal) of the
OPAx210; the feedback resistor (RFB is internal to the DAC8802) is connected to the output of the OPAx210, and
results in a current-to-voltage conversion. The output of the OPAx210 has a range of –10 V to 0 V, which is fed
to the THS4130 configured as a Sallen-Key filter. Finally, the 10-V range is attenuated down to a 1.5-V range,
with a common-mode voltage of 0.75 V using a resistive attenuator. See the 2.3-nV/√Hz, Differential, Time Gain
Control DAC Reference Design for Ultrasound for an in-depth analysis of Figure 8-4.
2nd Order Filter (fc = 150
kHz)
I-to-V Converters
+13 V -13 V
+5 V
+13 V-13 V
VCNTL-P
FPGA or
SPI
Controller
Interface
VCNTL (0 to 1.5V)
with
VCM (0.75V)
Passive
Attenuator
DAC8802
OPA2210
THS4130
VCM
VCNTL-M
REF+ REF-
+13 V -13 V
Required
VCM as
per AFE
+13 V
Resistor
Divider
10V from
REF5010
10 V
REF5010
10 V
0.75 V
OPA2210
-10 V
+15 V
-15 V
+13 V
+5 V to 12 V
TPS7A39
TPS7A47
LM5160
-13 V
+5 V
Used only if +/-15 V is not
available
Figure 8-4. Block Diagram for Time Gain Control System for Ultrasound
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9 Power Supply Recommendations
The OPAx210 are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –
40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in Section 6.7.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including
the following guidelines:
•
•
•
Noise from the amplifier can propagate into other analog circuits through the power pins of the amplifiers.
Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
•
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than running
in parallel with the noisy trace.
•
•
Place the external components as close to the device as possible.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
•
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
For best performance, clean the PCB following board assembly.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB to remove moisture introduced into
the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.
10.2 Layout Example
Place components
close to device and to
each other to reduce
parasitic errors
VS+
Run the input traces
as far away from
the supply lines
as possible
RF
GND
OUT A
V+
RG
GND
œIN A
+IN A
Vœ
OUT B
Use a low-ESR,
ceramic bypass capacitor
VIN
œIN B
+IN B
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
VSœ
GND
VOUT A
Figure 10-1. OPA2210 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ Simulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™
simulation software is a free, fully-functional version of the TINA software, preloaded with a library of macro
models in addition to a range of both passive and active models. TINA-TI simulation software provides all the
conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the
ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-
start tool.
Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI software from the TINA-TI software folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small, surface-mount integrated circuits
(ICs). The EVM includes footprint options for the following TI packages:
•
•
•
•
•
•
D or U (SOIC-8)
PW (TSSOP-8)
DGK (VSSOP-8)
DBV (SOT23-6, SOT23-5 and SOT23-3)
DCK (SC70-6 and SC70-5)
DRL (SOT563-6)
The DIP Adapter EVM may also be used with terminal strips or may be wired directly to existing circuits.
11.1.1.3 Universal Operational Amplifier EVM
The Universal Op Amp evalutaion module (EVM) is a series of general-purpose, blank circuit boards that simplify
prototyping circuits for a variety of IC package types. The EVM board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
The PDIP, SOIC, VSSOP, TSSOP, and SOT-23 packages are all supported.
Note
These boards are unpopulated, so users must provide their own ICs. TI recommends requesting
several op amp device samples when ordering the Universal Op Amp EVM.
11.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts. These designs
offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of
materials, and measured performance of many useful circuits.
11.1.1.5 WEBENCH® Filter Designer
The WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers
and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, the WEBENCH® Filter Designer allows you
to design, optimize, and simulate complete multistage active filter solutions within minutes.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
SBOS924F – SEPTEMBER 2018 – REVISED JANUARY 2021
www.ti.com
11.2 Documentation Support
11.2.1 Related Documentation
The following documents are relevant to using the OPAx210 and recommended for reference. All are available
for download at www.ti.com (unless otherwise noted):
•
•
•
•
•
•
•
Texas Instruments, OPA827 Low-Noise, High-Precision, JFET-Input Operational Amplifier data sheet
Texas Instruments, OPA2x11 1.1-nv/√Hz Noise, Low-Power, Precision Operational Amplifier data sheet
Texas Instruments, OPA210, OPA2210, OPA4210 EMI Immunity Performance technical brief
Texas Instruments, OPAx209 2.2-nV/√Hz, Low-Power, 36-V Operational Amplifier data sheet
Texas Instruments, Microcontroller PWM to 12-Bit Analog Out design guide
Texas Instruments, Capacitive Load Drive Solution Using an Isolation Resistor design guide
Texas Instruments, Noise Measurement Post Amp design guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TINA™ is a trademark of DesignSoft, Inc.
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: OPA210 OPA2210
PACKAGE OPTION ADDENDUM
www.ti.com
19-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DGK
D
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA210IDGKR
OPA210IDR
PREVIEW
VSSOP
SOIC
8
8
2500 RoHS (In work)
& Non-Green
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
PREVIEW
2500 RoHS (In work)
& Non-Green
Call TI
OPA2210ID
OPA2210IDGKR
OPA2210IDGKT
OPA2210IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
8
8
8
8
8
8
75
2500 RoHS & Green
250 RoHS & Green
RoHS & Green
NIPDAU
NIPDAUAG
NIPDAUAG
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OP2210
DGK
DGK
D
1OHQ
1OHQ
OP2210
O2210
O2210
2500 RoHS & Green
3000 RoHS & Green
OPA2210IDRGR
OPA2210IDRGT
POPA210ID
SON
DRG
DRG
D
NIPDAU
SON
250
75
RoHS & Green
NIPDAU
SOIC
RoHS (In work)
& Non-Green
Call TI
POPA210IDGK
POPA210IDGKT
POPA210IDR
ACTIVE
PREVIEW
PREVIEW
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
80
RoHS (In work)
& Non-Green
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
250
RoHS (In work)
& Non-Green
2500 RoHS (In work)
& Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Feb-2021
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2210IDGKR
OPA2210IDGKT
OPA2210IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
2500
250
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
5.3
5.3
6.4
3.3
3.4
3.4
5.2
3.3
1.4
1.4
2.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q2
2500
3000
OPA2210IDRGR
SON
DRG
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2210IDGKR
OPA2210IDGKT
OPA2210IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
2500
250
366.0
366.0
853.0
367.0
364.0
364.0
449.0
367.0
50.0
50.0
35.0
35.0
2500
3000
OPA2210IDRGR
SON
DRG
Pack Materials-Page 2
PACKAGE OUTLINE
DRG0008B
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.05 C
DIMENSION A
0.05
0.00
OPTION 01
OPTION 02
(0.1)
(0.2)
(DIM A) TYP
OPT 01 SHOWN
EXPOSED
THERMAL PAD
1.45 0.1
4
1
5
2X
1.5
2.4 0.1
8
6X 0.5
0.3
0.2
0.1
0.08
8X
0.6
0.4
PIN 1 ID
(OPTIONAL)
8X
C A B
C
4218886/A 01/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.45)
SYMM
8X (0.7)
1
8
8X (0.25)
(2.4)
(0.95)
5
6X (0.5)
4
(R0.05) TYP
(0.475)
(
0.2) VIA
(2.7)
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218886/A 01/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.7)
1
8X (0.25)
SYMM
8
(0.635)
6X (0.5)
(1.07)
5
4
(R0.05) TYP
(1.47)
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218886/A 01/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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