PPS36BA38ACADDFRQ1 [TI]
具有窗口看门狗计时器的汽车类纳安级静态电流精密监控器 | DDF | 8 | -40 to 125;
| 型号： | PPS36BA38ACADDFRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有窗口看门狗计时器的汽车类纳安级静态电流精密监控器 | DDF | 8 | -40 to 125 监控 |
| 文件： | 总39页 (文件大小：1757K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS36-Q1
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
TPS36-Q1 具有精密窗口看门狗计时器的汽车类毫微级IQ 精密电压监控器
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性：
TPS36-Q1 是一款超低功耗（典型值为 250nA）器
件，可提供具有可编程窗口看门狗计时器的精密电压监
控器。TPS36-Q1 支持用于欠压监控的宽阈值电平，在
额定温度范围内的精度为1.2%。
– 器件温度等级1：-40°C 至125°C 的环境工作温
度范围
• 出厂编程或用户可编程的看门狗超时
– ±10% 精确计时器（最大值）
TPS36-Q1 可提供具有多种功能的高精度窗口看门狗计
时器，广泛适用于各种应用。关闭窗口计时器可以由工
厂编程或用户使用外部电容器进行编程。可以使用逻辑
引脚的组合来动态更改打开窗口与关闭窗口的比率。看
门狗还提供独特的功能，例如启用/禁用、启动延迟、
独立的WDO 引脚选项。
– 出厂编程的关闭窗口：1 毫秒至100 秒
• 出厂编程或用户可编程的复位延迟
– ±10% 精确计时器（最大值）
– 出厂编程选项：2 毫秒至10 秒
• 输入电压范围：VDD = 1.04 V 至6.0 V
• 固定阈值电压(VIT-)：1.05 V 至5.4 V
– 步长为50mV 的阈值电压
– 1.2% 电压阈值精度（最大值）
– 内置迟滞(VHYS)：5%（典型值）
• 超低电源电流：IDD = 250nA（典型值）
• 开漏、推挽；低电平有效输出
• 各种可编程选项：
RESET 或 WDO 延迟可设定为出厂编程的默认延迟设
置或通过外部电容器进行编程。该器件还提供锁存输出
操作，监控器或看门狗故障清除之前会锁存输出。
TPS36-Q1 提供了 TPS3852-Q1 器件系列的性能升级
替代产品。TPS36-Q1 采用小型 8 引脚 SOT-23 封
装。
– 看门狗启用/禁用
器件信息
封装(1)
– 看门狗启动延迟：无延迟至10 秒
– 打开窗口与关闭窗口比率选项：1X 至511X
– 锁存输出选项
封装尺寸（标称值）
器件型号
TPS36-Q1
DDF (8)
2.90mm × 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• MR 功能支持
2 应用
• 车载充电器(OBC) 和无线充电器
• 驾驶员监控
• 电池管理系统(BMS)
• 前置摄像头
• 环视系统ECU
10
Supply
Device lot 1
Device lot 2
Device lot 3
VDD
VDD
RESET
WDO
RESET
NMI
5
0
MR
TPS36-Q1
µC
WDI
GPIO
GPIO
CRST
CWD
WD-EN
SET[0:1]
GPIO
-5
GND
GND
GND
TPS36-Q1 offers various pinout options to support different features.
Choose suitable pinout based on application needs
-10
-40
-7
26
59
92
125
典型应用电路
Ambient Temperature (C)
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
Table of Contents
8.1 Overview...................................................................15
8.2 Functional Block Diagrams....................................... 15
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................25
9 Application and Implementation..................................26
9.1 Application Information............................................. 26
9.2 Typical Applications.................................................. 27
9.3 Power Supply Recommendations.............................29
9.4 Layout....................................................................... 29
10 Device and Documentation Support..........................30
10.1 接收文档更新通知................................................... 30
10.2 支持资源..................................................................30
10.3 Trademarks.............................................................31
10.4 静电放电警告.......................................................... 31
10.5 术语表..................................................................... 31
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 器件比较............................................................................ 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics ............................................8
7.6 Timing Requirements .................................................9
7.7 Switching Characteristics .........................................10
7.8 Timing Diagrams....................................................... 11
7.9 Typical Characteristics..............................................12
8 Detailed Description......................................................15
Information.................................................................... 31
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2022) to Revision A (December 2022)
Page
• 将“预告信息”更改为“量产数据发布”...........................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
2
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
5 器件比较
图 5-1 显示了 TPS36-Q1 的器件命名规则。对于所有可能的输出类型、阈值电压选项、看门狗时间选项和输出断
言延迟选项，请参阅节 8 了解更多详细信息。有关其他选项的详细信息和可用性，请联系 TI 销售代码或访问 TI
的E2E 论坛。
TPS36 X X XX X X X XXX X Q1
Threshold
Tape/Reel
Voltage
R: Reel
T: Tape
Pinout Op on
Package
DDF: SOT23-8
01: 1.05 V
02: 1.10 V
...
87: 5.35 V
88: 5.40 V
A*
B*
C
D
Output Assert
Time
Output Topology,
Watchdog
Watchdog
Close Time
A: External
Capacitor **
B: 1 msec
A: External
Capacitor **
B: 2 msec
C: 10 msec
D: 25 msec
E: 50 msec
F: 100 msec
G: 200 msec
H: 1 sec
Startup Delay
A: DL, No Delay
B: DL, 200 msec
C: DL, 500 msec
D: DL, 1 sec
Open Time
Ra o
A: 2, 4, 16
B: 4, 8 , 32
C: 8, 16, 64
D: 16, 32, 128
E: 32, 64, 256
F: 64, 128, 512
C: 5 msec
E: DL, 5 sec
D: 10 msec
E: 20 msec
F: 50 msec
G: 100 msec
H: 200 msec
I: 1 sec
J = 1.4 sec
K = 1.6 sec
L = 10 sec
M = 50 sec
N = 100 sec
F: DL, 10 sec
G: PL, No Delay
H: PL, 200 msec
I: PL, 500 msec
J: PL, 1 sec
I: 10 sec
J = Latched
output
K: PL, 5 sec
L: PL, 10 sec
DL – Open Drain output
PL – Push Pull output
* Pinout op on supports Start up Delay se ngs of “No Delay” and “10 sec” only.
** Capacitor programmable me feature available with pinout op ons A & B. For xed me
and latched output features use pinout op ons C & D.
Refer ‘Mechanical, Packaging and Orderable Informa on’ sec on for list of released orderable.
For any other orderable, contact local TI support.
图5-1. 器件命名规则
TPS36-Q1 属于引脚兼容的器件系列，提供了不同的功能集，详见表5-1。
表5-1. 引脚兼容的器件系列
器件
电压监控器
看门狗类型
TPS35-Q1
TPS36-Q1
TPS3435-Q1
TPS3436-Q1
Timeout
是
是
否
否
窗口
Timeout
窗口
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
6 Pin Configuration and Functions
8
7
VDD
8
7
VDD
SET0
CWD
MR
1
2
1
2
CWD
RESET
RESET
CRST
GND
3
6
5
WDI
CRST
GND
3
6
5
WDI
4
SET0
4
SET1
Not to scale
Not to scale
图6-1. Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View
图6-2. Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View
8
7
VDD
8
7
VDD
SET0
MR
SET0
1
2
1
2
RESET
WD-EN
RESET
WDO
WDI
3
6
5
WD-EN
SET1
WDI
3
6
5
GND
4
GND
4
SET1
Not to scale
Not to scale
Pinout PREVIEW
图6-3. Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View
图6-4. Pin Configuration Option D
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View
Copyright © 2023 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
表6-1. Pin Functions
PIN NUMBER
PINOUT A PINOUT B PINOUT C PINOUT D
PIN
NAME
I/O
DESCRIPTION
Programmable reset timeout pin. Connect a capacitor between this pin and GND to
program the reset timeout period. See 节8.3.4 for more details.
CRST
3
3
I
I
—
—
Programmable watchdog timeout input. Watchdog close time is set by connecting a
capacitor between this pin and ground. See 节8.3.2.1 for more details.
CWD
GND
MR
2
4
1
2
4
—
4
—
4
Ground pin
—
Manual reset pin. A logic low on this pin asserts the RESET. See 节8.3.3 for more
details.
2
I
—
—
Reset output. Connect RESET to VDD using a pull up resistance when using open
drain output. RESET is asserted when the voltage at the VDD pin goes below the
undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do
not support independent WDO pin, RESET is also asserted for watchdog error. See
节8.3.4 for more details.
RESET
7
5
7
7
7
O
Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and
enable-disable the watchdog; see 节8.3.2.5 for more details.
SET0
SET1
VDD
1
5
8
1
5
8
6
3
1
5
8
2
3
I
I
I
I
I
Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and
enable-disable the watchdog; see 节8.3.2.5 for more details.
—
Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is
recommended.
8
Logic input. Logic high input enables the watchdog monitoring feature. See 节8.3.2.3
for more details.
WD-EN
WDI
—
—
Watchdog input. A falling transition (edge) must occur at this pin during the open
window in order for RESET / WDO to not assert. See 节8.3.2 for more details.
6
6
Watchdog output. Connect WDO to VDD using pull up resistance when using open
drain output. WDO asserts when a watchdog error occurs. WDO only asserts when
RESET is high. When a watchdog error occurs, WDO asserts for the set RESET
timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog
functionality is disabled. See 节8.3.4 for more details.
WDO
6
O
—
—
—
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted(1)
MIN
MAX
UNIT
Voltage
Voltage
VDD
6.5
V
–0.3
CWD, CRST, WD–EN, SETx, WDI, MR (2), RESET (Push
Pull), WDO (Push Pull)
VDD+0.3 (3)
–0.3
V
RESET (Open Drain), WDO (Open Drain)
RESET, WDO pin
6.5
20
–0.3
–20
–40
–65
Current
mA
Temperature (4)
Temperature
Operating ambient temperature, TA
Storage, Tstg
125
150
℃
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
(3) The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller
(4) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±2000
±750
V(ESD) Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.9
0
NOM
MAX
6
UNIT
VDD (Active Low output)
CWD, CRST, WD–EN, SETx, WDI, MR (1)
RESET (Open Drain) , WDO (Open Drain)
RESET (Open Drain) , WDO (Push Pull)
RESET, WDO pin current
VDD
6
Voltage
V
0
0
VDD
5
Current
CRST
CWD
TA
mA
nF
nF
–5
1.5
1.5
–40
CRST pin capacitor range
1800
1000
125
CWD pin capacitor range
Operating ambient temperature
℃
(1) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
6
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
7.4 Thermal Information
TPS36-Q1
THERMAL METRIC(1)
DDF (SOT23-8)
8 PINS
175.3
94.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
92.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.4
ψJT
91.9
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
7.5 Electrical Characteristics
At 1.04 V ≤VDD ≤6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩto VDD, WDO pull-up resistor (Rpull-up) = 100
kΩto VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃to 125℃, unless otherwise
noted. VDD ramp rate ≤1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
Input supply voltage
Active LOW output
1.04
–1.4
–1.2
3
6
1.4
1.2
7
V
%
%
VIT– = 1.05 V to 1.95 V
VIT– = 2.0 V to 5.4 V
VIT– = 1.05 V to 5.4 V
±0.5
±0.5
5
Negative-going input threshold accuracy
VIT–
VHYS
(1)
Hysteresis VIT– pin
TA = –40℃to
85℃
VDD = 2 V
VIT– = 1.05 V to 1.95
V
0.25
0.25
0.25
0.25
0.8
3
0.8
IDD
Supply current into VDD pin (2)
µA
V
TA = –40℃to
85℃
VDD = 6 V
VIT– = 1.05 V to 5.4 V
3
Low level input voltage WD–EN, WDI,
VIL
0.3VDD
SETx, MR (3)
High level input voltage WD–EN, WDI,
VIH
0.7VDD
V
SETx, MR (3)
RMR
Manual reset internal pull-up resistance
100
kΩ
RESET / WDO (Open-drain active-low)
VDD =1.5 V, 1.55 V ≤VIT– ≤3.35 V
IOUT(Sink) = 500 µA
300
300
Low level output voltage
VOL
mV
VDD = 3.3 V, 3.4 V ≤VIT– ≤5.4 V
IOUT(Sink) = 2 mA
VDD = VPULLUP = 6V
TA = –40℃to 85℃
10
10
30
nA
nA
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6V
120
RESET / WDO (Push-pull active-low)
VOL(max) = 300 mV
IOUT(Sink) = 15 µA
VPOR
Power on RESET voltage (5)
Low level output voltage
900
300
300
300
mV
mV
VDD = 0.9 V, 1.05 V ≤VIT– ≤1.5 V
IOUT(Sink) = 15 µA
VDD = 1.5 V, 1.55 V ≤VIT– ≤3.35 V
IOUT(Sink) = 500 µA
VOL
VDD = 3.3 V, 3.4 V ≤VIT– ≤5.4 V
IOUT(Sink) = 2 mA
VDD = 1.8 V, 1.05 V ≤VIT– ≤1.4 V
IOUT(Source) = 500 µA
0.8VDD
0.8VDD
0.8VDD
High level output voltage
VDD = 3.3 V, 1.45 V ≤VIT– ≤3.0 V
IOUT(Source) = 500 µA
VOH
V
VDD = 6 V, 3.05 V ≤VIT– ≤5.4 V
IOUT(Source) = 2 mA
(1) VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
(3) VPOR is the minimum VDD voltage level for a controlled output state
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
8
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
7.6 Timing Requirements
At 1.04 V ≤VDD ≤6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩto VDD, WDO pull-up resistor (Rpull-up) = 100
kΩto VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃to 125℃,
unless otherwise noted. VDD ramp rate ≤1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
5% VIT– overdrive(1)
MIN
TYP
MAX
UNIT
tGI_VIT–
tMR_PW
tP-WD
Glitch immunity VIT–
15
µs
MR pin pulse duration to assert reset
WDI pulse duration to start next frame (2)
100
ns
VDD > VIT–
VDD > VIT–
500
200
ns
WD-EN hold time to enable or disable WD
operation (2)
tHD-WDEN
tHD-SETx
µs
µs
SETx hold time to change WD timer setting
VDD > VIT–
150
(2)
Orderable Option TPS36xxxxB
Orderable Option TPS36xxxxC
Orderable Option TPS36xxxxD
Orderable Option TPS36xxxxE
Orderable Option TPS36xxxxF
Orderable Option TPS36xxxxG
Orderable Option TPS36xxxxH
Orderable Option TPS36xxxxI
Orderable Option TPS36xxxxJ
Orderable Option TPS36xxxxK
Orderable Option TPS36xxxxL
Orderable Option TPS36xxxxM
Orderable Option TPS36xxxxN
0.8
4
1
5
1.2
6
9
10
11
18
20
22
ms
45
50
55
90
100
200
1
110
220
1.1
1.54
1.76
11
tWC
Watchdog close window time period
180
0.9
1.26
1.44
9
1.4
1.6
10
s
45
50
55
90
100
110
(n-1) X
tWO
Watchdog open window time period
SETx pin decide multipler n
ms
tWC
(1) Overdrive % = [(VDD/ VIT–) –1] × 100%
(2) Not production tested
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
7.7 Switching Characteristics
At 1.04 V ≤VDD ≤6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩto VDD, WDO pull-up resistor (Rpull-up) = 100
kΩto VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃to 125℃,
unless otherwise noted. VDD ramp rate ≤1 V/µs. Typical values are at TA = 25℃
PARAMETER
Startup delay(4)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSTRT
tP_HL
500
µs
RESET detect delay for VDD falling below
VIT–
VDD : (VIT+ + 10%) to (VIT–
10%)(1)
–
30
0
50
µs
Orderable part number TPS36xA,
TPS36xG
Orderable part number TPS36xB,
TPS36xH
180
450
0.9
4.5
9
200
500
1
220
550
1.1
5.5
11
ms
Orderable part number TPS36xC,
TPS36xI
tSD
Watchdog startup delay
Orderable part number TPS36xD,
TPS36xJ
Orderable part number TPS36xE,
TPS36xK
5
s
Orderable part number TPS36xF,
TPS36xL
10
2
Orderable part number
TPS36xxxxxxB
1.6
9
2.4
11
ms
ms
ms
ms
ms
ms
s
Orderable part number
TPS36xxxxxxC
10
25
50
100
200
1
Orderable part number
TPS36xxxxxxD
22.5
45
27.5
55
Orderable part number
TPS36xxxxxxE
tD
Reset time delay (3)
Orderable part number
TPS36xxxxxxF
90
110
220
1.1
11
Orderable part number
TPS36xxxxxxG
180
0.9
9
Orderable part number
TPS36xxxxxxH
Orderable part number
TPS36xxxxxxI
10
tD
s
s
tWDO
Watchdog timeout delay
Propagation delay from MR low to reset
assertion
VDD ≥VIT– + 0.2 V,
MR = VMR_H to VMR_L
tMR_RES
100
ns
VDD = 3.3 V,
MR = VMR_L to VMR_H
tMR_tD
Delay from MR release to reset deassert
tD
s
(1) tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS
(2) Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is
deasserted after the startup delay (tSTRT) + tD delay.
(3) VDD voltage transitions from (VIT–- 10%) to (VIT– + 10%)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
10
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
7.8 Timing Diagrams
VIT+
VIT-
VDD
VPOR
tSTRT + tD
ttDt
tP-HL
tSD
RESET
WDO
ttWO
t
tWC
tWC
tWC
ttWO
t
ttWO
t
ttSD
t
ttDt
ttSDt
tP-WD
Ignore
WDI
Ignore
Ignore
Devices with only RESET output, the output will be AND
operation of RESET and WDO signals.
图7-1. Functional Timing Diagram
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
7.9 Typical Characteristics
all curves are taken at TA = 25°C (unless otherwise noted)
1
60
48
36
24
12
0
Device1
Device2
Device3
0.5
0
-0.5
-1
-0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2 0.3 0.4 0.5
-40
-7
26
59
92
125
VIT- Accuracy (%)
Ambient Temperature (C)
图7-3. VIT- Accuracy Histogram
图7-2. VIT- Accuracy vs Temperature
5.5
5.3
5.1
4.9
4.7
4.5
30
25
20
15
10
TA = 25C
TA = 125C
TA = −40C
Device1
Device2
Device3
-40
-7
26
59
92
125
0
10
20
30
40
50
Ambient Temperature (C)
Overdrive (%)
图7-4. VIT- Hysteresis Vs Temperature
图7-5. Supply Glitch Immunity vs Overdrive
10
60
48
36
24
12
0
Device lot 1
Device lot 2
Device lot 3
5
0
-5
-10
-40
-7
26
59
92
125
-5
-4
-3
-2
-1
Time Accuracy (%)
图7-7. Timer Accuracy Histogram
0
1
2
3
4
5
Ambient Temperature (C)
图7-6. Timer Accuracy vs Temperature
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
12
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
7.9 Typical Characteristics (continued)
all curves are taken at TA = 25°C (unless otherwise noted)
100
80
60
40
20
TA = 25C
TA = 125C
TA = −40C
0
0
200
400
600
800
1000
CWD Capacitance (nF)
图7-8. tWC vs Capacitance
图7-9. tD vs Capacitance
1
0.8
0.6
0.4
0.2
0
TA = −40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
1
2
3
4
5
Sink current (mA)
图7-10. RESET VOL vs I sink, VDD = 1.5 V
图7-11. WDO VOL vs I sink, VDD = 1.5 V
0.5
0.4
0.3
0.2
0.1
0
TA = −40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
1
2
3
4
5
Sink current (mA)
图7-12. RESET VOL vs I sink, VDD = 3.3 V
图7-13. WDO VOL vs I sink, VDD = 3.3 V
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
7.9 Typical Characteristics (continued)
all curves are taken at TA = 25°C (unless otherwise noted)
2
2
1.6
1.2
0.8
0.4
0
1.6
1.2
0.8
0.4
TA = −40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
TA = −40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
0
1
2
3
4
5
1
2
3
4
5
Source current (mA)
Source current (mA)
图7-14. RESET VOH vs I source, VDD = 2.0 V
图7-15. WDO VOH vs I source, VDD = 2.0 V
6
5.6
5.2
4.8
4.4
4
6
5.6
5.2
4.8
4.4
4
TA = −40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
TA = −40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
1
2
3
4
5
1
2
3
4
5
Source Current (mA)
Source current (mA)
图7-16. RESET VOH vs I source, VDD = 6.0 V
图7-17. WDO VOH vs I source, VDD = 6.0 V
图7-18. Supply Current vs Power-Supply Voltage
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
14
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
8 Detailed Description
8.1 Overview
The TPS36-Q1 is a high-accuracy under voltage supervisor with an integrated window watchdog timer device.
The device family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package.
The devices are available in 4 different pinout configurations. Each pinout offers access to different features to
meet the various application requirements. The device family is rated for -Q100 applications.
8.2 Functional Block Diagrams
MR
RESET
RESET
Logic
Capacitive
Divider
VDD
+
–
Reference
GND
Oscillator
Capacitance
Detection
Watchdog Timer
Logic
GND
CRST
CWD
WDI
SET0
图8-1. Pinout Option A
Capacitive
Divider
RESET
Logic
+
–
RESET
VDD
Reference
GND
Oscillator
Capacitance
Detection
Watchdog Timer
Logic
GND
CRST
CWD
WDI
SET0
SET1
图8-2. Pinout Option B
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
MR
RESET
Logic
RESET
Capacitive
Divider
VDD
+
–
Reference
GND
Oscillator
Watchdog Timer
Logic
GND
WDI
SET0
SET1 WD-EN
图8-3. Pinout Option C
RESET
WDO
Capacitive
Divider
RESET and
WDO
Logic
VDD
+
Reference
GND
–
Oscillator
Watchdog Timer
Logic
GND
WDI
SET0
SET1 WD-EN
图8-4. Pinout Option D
8.3 Feature Description
8.3.1 Voltage Supervisor
The TPS36-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage
supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO
outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level
when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time
after the VDD > VIT+ (VIT- + VHYS). Refer 节 8.3.4 for the tD value computation. For a capacitor based tD delay
option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open.
Device pinout options A to C offer only RESET output. In these devices the internal RESET output from
supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output.
The supervisor offers wide range of fixed monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV.
The device asserts the RESET output when the VDD signal falls below VIT- threshold. The device offers
hysteresis functionality for voltage supervision. This ensures the supply has recovered above the monitoring
threshold before the RESET output is deasserted. The TPS36-Q1 typical voltage hysteresis (VHYS) is 5%. Along
with the voltage hysteresis, the device keeps the RESET output asserted for time duration tD after the supply has
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
16
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
risen above VIT+. The RESET output assert duration changes from tD to tSTRT + tD if the VDD signal is ramping
from voltage < VPOR. The tD time duration can be programmable using an external capacitor or fixed time options
offered by the device.
The typical timing behavior for a voltage supervisor and the RESET output is showcased in 图 8-5. The voltage
supervisor monitoring output has higher priority over watchdog functionality. If the device voltage supervisor
output is asserted, the watchdog functionality will be disabled including WDO assert control. The device resumes
watchdog related functionality only after the supply is stable and the tD time duration has elapsed.
VIT+
VIT-
VDD
VPOR
tSTRT + tD
ttDt
tP-HL
tSD
RESET
ttWO
t
tWC
tWC
tWC
ttWO
t
ttWO
t
ttSD
t
ttDt
ttSDt
WDO
WDI
tP-WD
Ignore
Ignore
Ignore
Devices with only RESET output, the output will be AND
operation of RESET and WDO signals.
图8-5. Voltage Supervisor Timing Diagram
8.3.2 Window Watchdog Timer
The TPS36-Q1 offers high precision window watchdog timer monitoring. The device is available in multiple
pinout options A to D which support multiple features to meet ever expanding needs of various applications.
Ensure a correct pinout is selected to meet the application needs.
The window watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is
deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled. TPS36-
Q1 family offers various startup time delay options to ensure enough time is available for the host to complete
boot operation. Please refer 节8.3.2.4 section for additional details.
The window watchdog timer frame consists of two windows namely close window (tWC) followed by open window
(tWO). The device monitors the WDI pin for falling edge. User is expected to provide a valid falling edge on WDI
pin in the open window. Refer 节 5 to arrive at the relevant close window and open window values needed for
application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWO time duration. An
early fault is reported if a WDI falling edge is detected in close window. A late fault is reported if WDI falling edge
is not detected in both close and open window. The device asserts RESET output for pinout options A, B and C
or WDO output for pinout D for time tD in event of watchdog fault. Refer 节8.3.4 to arrive at the relevant tD value
needed for application.
图 8-6 shows the basic operation for window watchdog timer operation. The TPS36-Q1 watchdog functionality
supports multiple features. Details are available in following sub sections.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
ttSD
t
ttSDt
ttWO
t
ttWO
t
ttWOt
ttDt
ttDt
WDO
WDI
ttWC
t
ttWCt
tP-WD
ttWC
t
Ignore
Ignore
NO fault
Early fault
Late fault
Devices with only RESET output, the RESET output will be
asserted when watchdog error occurs.
图8-6. Window Watchdog Timer Operation
8.3.2.1 tWC (Close Window) Timer
The window watchdog frame consists of two sub frames tWC followed by tWO. The host is not expected to drive
valid WDI transition during tWC time. A valid WDI transition during tWC frame results in early fault condition and
the WDO output is asserted. RESET output is asserted if pinout does not offer independent WDO output. The
tWC timer for TPS36-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This
feature is available with pinout options A or B. Applications which are space constrained or need timer values
which meet offered timer options, can benefit when using pinout options C or D. The TPS36-Q1 offers multiple
fixed timer options ranging from 1 msec up-to 100 sec.
The TPS36-Q1 when using capacitance based timer, senses the capacitance value during the power up or after
a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to
sense the capacitance value. The sensed value is used to arrive at tWC timer for the watchdog operation. This
unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus
reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time
(no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of
capacitance. The unique implementation of TPS36-Q1 helps avoid the dead time as the capacitance is not
continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate
calibration of capacitance. The close time window is decided based on SETx pin combination and the CWD
capacitance. 表 8-1 to 表 8-3 highlights the relationship between tWC in second and CWD capacitance in farad.
The tWC timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on
the tWC time. Ensure the capacitance meets the recommended operating range. Capacitance outside the
recommended range can lead to incorrect operation of the device.
表8-1. tWC Equation 1 SET Pin (Pin Configuration A)
SET pin value
Equation
0
1
tWC (sec) = 79.2 x 106 x CCWD (F)
tWC (sec) = 39.6 x 106 x CCWD (F)
表8-2. tWC Equation 2 SET Pin, WD-EN = 1 (Pin Configuration C, D)
Equation
SET Pin Value
00
01
10
11
tWC (sec) = 79.2 x 106 x CCWD (F)
tWC (sec) = 79.2 x 106 x CCWD (F)
tWC (sec) = 39.6 x 106 x CCWD (F)
tWC (sec) = 9.9 x 106 x CCWD (F)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
18
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
SET Pin Value
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
表8-3. tWC Equation 2 SET Pin, WD-EN Not Available (Pin Configuration B)
Equation
00
01
10
11
tWC (sec) = 79.2 x 106 x CCWD (F)
Watchdog disabled
tWC (sec) = 39.6 x 106 x CCWD (F)
tWC (sec) = 9.9 x 106 x CCWD (F)
The TPS36-Q1 also offers wide selection of high accuracy fixed tWC timer options starting from 1 msec to 100
sec including various industry standard values. The TPS36-Q1 fixed time options are ±10% accurate for tWC ≥
10 msec. For tWC < 10 msec, the accuracy is ±20%. tWC value relevant to application can be identified from the
orderable part number. Refer 节5 to identify mapping of orderable part number to tWC value.
8.3.2.2 tWO (Open Window) Timer
The window watchdog frame consists of two sub frames tWC followed by tWO. The host is expected to drive valid
WDI transition during tWO time. A valid WDI transition before beginning of tWO frame causes early fault condition.
Failure to offer valid WDI transition during tWC and tWO frames results in late fault condition. When a fault
condition is detected the WDO output is asserted. RESET output is asserted if pinout does not offer independent
WDO output.
The tWO value is derived using tWC value and the window open time ratio value n. Equation highlights the
relationship between tWO and tWC. Refer 节5 to select available ratio options.
tWO = (n - 1) x tWC
(1)
Each orderable can offer up to 3 ratio options based on the available SET pins. Refer 节 8.3.2.5 to identify
mapping of ratio value to SET pin control. The maximum tWO value is limited to 640 second. Ensure selected tWC
and ratio combination does not lead to tWO value greater than 640 second.
8.3.2.3 Watchdog Enable Disable Operation
The TPS36-Q1 supports watchdog enable or disable functionality. This functionality is critical for different use
cases as listed below.
• Disable watchdog during firmware update to avoid host RESET.
• Disable watchdog during software step-by-step debug operation.
• Disable watchdog when performing critical task to avoid watchdog error interrupt.
• Keep watchdog disabled until host boots up.
The TPS36-Q1 supports watchdog enable or disable functionality through either WD-EN pin (pin configuration
C,D) or SET[1:0] = 0b'01 (pin configuration B) logic combination. For a given pinout only one of these two
methods is available for the user to disable watchdog operation.
For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state
of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog
operation. The WD-EN pin can be toggled any time during the device operation. The 图 8-7 diagram shows
timing behavior with WD-EN pin control.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
VIT+
VDD
RESET
WD-EN
ttWCt
tWC
ttWO
t
WDO
WDI
ttDt
Ignore
Ignore
Devices with only RESET output, the output will be AND
operation of RESET and WDO signals.
图8-7. Watchdog Enable: WD-EN Pin Control
SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and
SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during
watchdog operation. Refer 节8.3.2.5 section for additional details regarding SET[1:0] pin behavior.
Pinout options A, B offer watchdog timer control using a capacitance connected between CWD and GND pin. A
capacitance value higher than recommended or connect to GND leads to watchdog functionality getting
disabled. Capacitance based disable operation overrides the other two options mentioned above. Changing
capacitance on the fly does not enable or disable watchdog operation. A power supply recycle or device
recovery after UV fault, MR low event is needed to detect change in capacitance.
Ongoing watchdog frame is terminated when watchdog is disabled. WDO stays deasserted when watchdog
operation is disabled. For a pinout with only RESET output, the RESET can assert if supply supervisor error
occurs. When enabled the device immediately enters tWC frame and start watchdog monitoring operation.
8.3.2.4 tSD Watchdog Start Up Delay
The TPS36-Q1 supports watchdog startup delay feature. This feature is activated after power up or after a
RESET assert event or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but
the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog
monitoring can take over. The start up delay helps avoid unexpected WDO or RESET assert events during boot.
The tSD time is predetermined based on the device part number selected. Refer 节 5 section for details to map
the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options.
The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on
the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD
frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI
pin triggers the watchdog error by asserting the WDO output pin. For devices with only RESET output, the
RESET pin is asserted.
The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or
WDI float functionality as described in 节8.3.2.3 section.
图8-8 shows the operation for tSD time frame.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
20
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
VIT+
VDD
VPOR
tSTRT + tD
RESET
ttSD
t
ttSD
t
ttWO
t
ttDt
WDO
WDI
ttWC
t
ttWC
t
Ignore
Ignore
Devices with only RESET output, the output will be AND
operation of RESET and WDO signals.
图8-8. tSD Frame Behavior
8.3.2.5 SET Pin Behavior
The TPS36-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the
user to program the tWO timer on the fly to meet various application requirements. Typical use cases where SET
pin can be used are
• Use wide open window timer when host is in sleep mode, change to small timeout operation when host is
operational. Watchdog can be used to wake up the host after long duration to perform the application related
activities before going back to sleep.
• Change to wide open window timer when performing system critical tasks to ensure watchdog does not
interrupt the critical task. Change timer to application specified interval after the critical task is complete.
The tWO timer value for the device is combination of tWC timer selection based on the CWD pin or fixed timer
value along with SET pin logic level. The tWC timer value is decided based on the Watchdog Close Time selector
in the 节 5 section. The SET pin logic level is decoded during the device power up. The SET pin value can be
changed any time during the operation. SETx pin change which leads to change of watchdog timer value or
enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when
WDO or RESET output is asserted as well. The updated tWO timer value will be applied after output is
deasserted and the tSD timer is over or terminated.
For a pinout which offers only SET0 pin to the user, the tWO ratio value is decided based on the Watchdog Open
Time Ratio selector field in the orderable part number. Refer 节 5 for available options. 表 8-4 showcases an
example of the tWO values for different SET0 logic levels when using Watchdog Close Time setting as option D =
10 msec.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
表8-4. tWO Values with SET0 Pin Only (Pin Configuration A)
tWO
Watchdog Open Time Ratio Selection
SET0 = 0
10 msec
30 msec
70 msec
150 msec
310 msec
630 msec
SET0 = 1
30 msec
A
B
C
D
E
F
70 msec
150 msec
310 msec
630 msec
1270 msec
Pinout which offer both SET0 & SET1 pins to the user, the tWO ratio value is decided based on the Watchdog
Open Time Ratio selector field in the orderable part number. Refer 节 5 for available options. Two SETx pins
offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. 表 8-5
showcases an example of the tWO values for different SET[1:0] logic levels when using Watchdog Close Time
setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.
表8-5. tWO Values with SET0 & SET1 Pins, WD-EN Pin Not Available (Pin Configuration B)
tWO
Watchdog Open Time
Ratio selection
SET[1:0] = 0b'00
100 msec
SET[1:0] = 0b'01
Watchdog disable
Watchdog disable
Watchdog disable
Watchdog disable
Watchdog disable
Watchdog disable
SET[1:0] = 0b'10
300 msec
SET[1:0] = 0b'11
1500 msec
A
B
C
D
E
F
300 msec
700 msec
1500 msec
3100 msec
6300 msec
700 msec
3100 msec
6300 msec
12700 msec
25500 msec
51100 msec
1500 msec
3100 msec
6300 msec
12700 msec
1. Example for Watchdog Close Time setting = 100 msec.
Selected pinout option can offer WD-EN pin along with SET[1:0] pins (Pin Configuration C, D). With this pinout,
the WD-EN pin controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as
SET[1:0] = 0b'00.
Ensure the tWO value with SETx ratio does not exceed 640 sec. If a selection of close window timer and ratio
results in tWO > 640 sec, the timer value will be restricted to 640 sec.
图8-9 to 图8-11 show the timing behavior with respect to SETx status changes.
WD_EN = 1
WD ratio = y
WD ratio = z
WD ratio = x
SETx
ttWO=tWC*(y – 1)t
ttWO=tWC*(z – 1)t
ttWO=tWC*(x – 1)t
ttWO=tWC*(x – 1)t
WDO
WDI
ttWC
t
ttWCt
ttWC
t
ttWCt
ttWC
t
tWO
图8-9. Watchdog Behavior with SETx Pin Status
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
22
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
SET Pin (2 Pins) Operation; WD_EN Pin Not Available
00 = WD ratio = x
tWO = tWC*(x–1)
01 = WD Disabled
10 = WD ratio = y
tWO = tWC*(y–1)
11 = WD ratio = z
tWO = tWC*(z–1)
SET[1:0]
Open Window
time value
WD Disabled
SET Pin (2 Pins) Operation; WD_EN Available = 1
SET[1:0]
00 or 01 = WD ratio = x
10 = WD ratio = y
tWO = tWC*(y–1)
11 = WD ratio = z
tWO = tWC*(z–1)
Open Window
time value
tWO = tWC*(x–1)
tWC = Fixed based on OPN or programmable using capacitor
x, y, z = Fixed based on ratio chosen
图8-10. Watchdog Operation with 2 SET Pins
SET0
1 = WD ratio = y
tWO = tWC*(y–1)
0 = WD ratio = x
tWO = tWC*(x–1)
1 = WD ratio = y
tWO = tWC*(y–1)
0 = WD ratio = x
tWO = tWC*(x–1)
Open Window
time value
tWC = Fixed based on OPN or programmable using capacitor
X, y = Fixed based on ratio chosen
图8-11. Watchdog Operation with 1 SET Pin
8.3.3 Manual RESET
The TPS36-Q1 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than
0.3 x VDD, asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating.
The internal pull up will ensure the output is not asserted due to MR pin trigger.
The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer 图
8-12 for more details.
MR
0.7 x VDD
0.3 x VDD
ttDt
tP-HL
ttSDt
RESET
图8-12. MR Pin Response
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
8.3.4 RESET and WDO Output
The TPS36-Q1 device can offer RESET or RESET with independent WDO output pin. The output configuration
is dependent on the pinout variant selected. For a pinout which has only RESET output, the RESET output is
asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold or
watchdog timer error is detected. For a pinout which has independent RESET and WDO output pins, the RESET
output is asserted when VDD voltage is below the monitored threshold or MR pin voltage is lower than threshold.
WDO output is asserted only when watchdog timer error is detected. RESET error has higher priority than WDO
error. If RESET is asserted when WDO is asserted, the device deasserts the WDO pin and watchdog is disabled
until RESET pin is deasserted and startup delay frame is terminated.
The output will be asserted for tD time when any relevant events described above are detected. The time tD can
be programmed by connecting a capacitor between CRST pin and GND or device will assert tD for fixed time
duration as selected by orderable part number. Refer 节5 section for all available options.
方程式 2 describes the relationship between capacitor value and the time tD. Ensure the capacitance meets the
recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of
the device.
tD (sec) = 4.95 x 106 x CCRST (F)
(2)
TPS36-Q1 also offers a unique option of latched output. An orderable with latched output will hold the output in
asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is
latched due to voltage supervisor undervoltage detection, the output latch will be released when VDD voltage
rises above the VIT- + VHYS level. If the output is latched due to MR pin low voltage, the output latch will be
released when MR pin voltage rises above 0.7 x VDD level. If the output is latched due to watchdog timer error,
the output latch will be released when a WDI negative edge is detected or the device is shutdown and powered
up again. 图8-13 shows timing behavior of the device with latched output configuration.
VIT+
VIT-
VDD
VDDMIN
WDI
ttSD
t
ttSD
t
tWC
ttWC
t
ttWO
t
WDO
tSTRT + tD
RESET
Devices with only RESET output, the output will be AND
operation of RESET and WDO signals.
图8-13. Output Latch Timing Behavior
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
24
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
8.4 Device Functional Modes
表8-6 summarizes the functional modes of the TPS36-Q1.
表8-6. Device Functional Modes
VDD
WATCHDOG STATUS
Not Applicable
Not Applicable
Disabled
WDI
WDO
Undefined
High
RESET
Undefined
Low
VDD < VPOR
—
Ignored
V
POR ≤VDD < VIT-
Ignored
High
High
WC(max) ≤tpulse 1 ≤tWC(max)
+
Enabled
High
High
t
tWO(min)
VDD ≥VIT+
1
Enabled
Enabled
tWC(max) > tpulse
Low
Low
High
High
1
tWC(max) + tWO(max) < tpulse
(1) Where tpulse is the time between falling edges on WDI.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail proper device implementation, depending on the final application
requirements.
9.1.1 CRST Delay
The TPS36-Q1 features two options for setting the reset delay (tD): using a fixed timing and programming the
timing through an external capacitor.
9.1.1.1 Factory-Programmed Reset Delay Timing
Fixed reset delay timings are available using pinouts C and D. Using these timings enables a high-precision,
10% accurate reset delay timing.
9.1.1.2 Adjustable Capacitor Timing
The TPS36-Q1 also offers programmable reset delay option when using pinout A and B. The TPS36-Q1 can be
programmed to have a desired reset delay by connecting a capacitor between CRST pin and GND. The typical
delay time resulting from a given external capacitance on the CRST pin can be calculated by 方程式3 , where tD
is the reset delay time in seconds and CCRST is the capacitance in farads.
tD (sec) = 4.95 × 106 × CCRST (F)
(3)
To minimize the difference between the calculated reset delay time and the actual reset delay time, use a use a
high-quality ceramic dielectric COG capacitor and minimize parasitic board capacitance around this pin. 表 9-1
lists the reset delay time ideal capacitor values for CCRST
.
表9-1. Reset Delay Time for Common Ideal Capacitor Values
RESET
DELAY TIME (tD)
CCRST
UNIT
MIN (1)
39.6
TYP
49.5
495
MAX (1)
59.4
10 nF
100 nF
1 μF
ms
ms
ms
396
594
3960
4950
5940
(1) Minimum and maximum values are calculated using ideal capacitors.
9.1.2 Watchdog Window Functionality
The TPS36-Q1 features two options for setting the close window watchdog timer (tWC): using a fixed timing and
programming the timing through an external capacitor.
9.1.2.1 Factory-Programmed watchdog Timing
Fixed watchdog window close timings are available using pinout C and D. Using these timings enables a high-
precision, 10% accurate watchdog timer tWC
.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
26
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
9.1.2.2 Adjustable Capacitor Timing
Pinout options A and B support adjustable tWC timing. This is achievable by connecting a capacitor between
CWD and GND pin. Consult 表 8-1, 表 8-2, and 表 8-3 for calculating typical tWC values using ideal capacitors.
Capacitor tolerances will cause additional deviation. For the most accurate timing, use ceramic capacitors with
COG dielectric material.
9.2 Typical Applications
9.2.1 Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes
The TPS36-Q1 can utilize high-accuracy voltage monitoring and on-the-fly SETx assigning to monitor a
microcontroller that has both an operational and sleep mode.
1.8V
V
TPS36-Q1
DD
RESET
RESET
GPIO
VDD
Microcontroller
WDI
WD-EN
MR
GPIO
GPIO
SET0
GND
SET1
GND
Copyright © 2023, Texas Instruments Incorporated
图9-1. Monitoring Microcontroller Supply and Watchdog During Operation and Sleep
9.2.1.1 Design Requirements
表9-2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Typical Voltage Threshold of 1.65 V
Typical tWC of 50 ms
Voltage Threshold
Window Close Time During Operation
Window Open Time During Operation
Window Close Time During Sleep
Window Open Time During Sleep
RESET Delay
Typical Voltage Threshold of 1.65 V
Typical tWC of 50 ms during opertation
Typical tWO of 1.4 s during operation
Typical tWC of 50 ms during sleep
Typical tWO of 12 s during operation
Typical tWO of 1.55 s
Typical tWC of 50 ms
Typical tWO of 12.75 s
200 ms
Open-drain
20 μA
200 ms
Open-drain
Output Logic
Maximum Device Current Consumption
250 nA typical, 3 μA maximum
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Setting Voltage Threshold
The negative-going threshold voltage, VIT-, is set by the device variant. 方程式 4 shows how to calculate the
"Threshold Voltage" section of the orderable part number.
OPN "Threshold Voltage" number = (VIT- - 1) / 0.05
(4)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
In this example, the nominal supply voltage for the microcontroller is 1.8 V. The minimum supply voltage is 10%
lower than the nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the device is reset just
before the supply voltage reaches the minimum allowed. Thus a 1.65 V threshold is chosen and, using 方程式 4,
the part number is reduced to TPS36xx13xxxxxxxQ1. The hysteresis is 5% typical, resulting in a positive-going
threshold voltage, VIT+, of 1.73 V.
9.2.1.2.2 Determining Window Timings During Operation and Sleep Modes
The TPS36-Q1 allows for precise 10% accurate watchdog timings. This application requires two different window
timings in order to maximize power efficiency: one for the microcontroller's operational state and one for its sleep
state. To achieve this, the host can reassign the SETx pins when it transitions between states. A window close
time, tWC, of 50 ms typical is chosen because of the application's 50 ms typical tWC requirement. The application
requires a minimum watchdog open time, tWO, of 1.4 s during operation and a tWO of 12 s during sleep. Thus, the
possible variant options are narrowed to TPS36xx13FExDDFRQ1.
9.2.1.2.3 Meeting the Minimum Reset Delay
The TPS36-Q1 features two options for selecting reset delays: fixed delays and capacitor-programmable delays.
The TPS36-Q1 supports only fixed watchdog timings and fixed reset delays or programmable watchdog timings
and programmable reset delays. The application requires a 200 ms minimum reset delay, thus reset delay option
G is used. Because of these requirements and no need for a startup delay, the TPS36CA13FEGDDFRQ1 is
used.
9.2.1.2.4 Setting the Watchdog Window
In this application, the watchdog timing options are based on the WDI signal that is provided to the TPS36-Q1. A
watchdog WDI setting must be chosen such that a transition must always occur within the open watchdog
window. There are several ways to achieve these window parameters. An external capacitor can be placed on
the CWD pin and calculated to have a sufficient window close time. Another option is to use one of the factory-
programmed timing options. An additional advantage of choosing one of the factory-programmed options is the
ability to reduce the number of components required, thus reducing overall BOM cost.
9.2.1.2.5 Calculating the RESET Pullup Resistor
The TPS36-Q1 uses an open-drain configuration for the RESET output, as shown in 图9-2.When the FET is off,
the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to
ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL
is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in
mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum
VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin
below 0.3 V with IRST kept below 2 mA for VDD ≥3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU
=VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum
consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected,
which sinks a maximum of 180 μA when RESET is asserted.
VDD
RESET
RESET
CONTROL
图9-2. Open-Drain RESET Configuration
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
28
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
9.3 Power Supply Recommendations
This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input
supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is
to place a 0.1-µF capacitor between the VDD pin and the GND pin.
9.4 Layout
9.4.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends
placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the
CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected.
• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
• Place CCRST capacitor as close as possible to the CRST pin.
• Place CCWD capacitor as close as possible to the CWD pin.
• Place the pullup resistor on the RESET pin as close to the pin as possible.
9.4.2 Layout Example
Pull up
Open Drain
Output
TPS36-Q1
8
7
VDD
SET0
MR
1
2
RESET
WDI
3
6
5
WD-EN
SET1
GND
4
Not to scale
Copyright © 2023, Texas Instruments Incorporated
图9-3. Typical Layout for the pinout C of TPS36-Q1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
10 Device and Documentation Support
10.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGE9
30
Submit Document Feedback
Product Folder Links: TPS36-Q1
TPS36-Q1
www.ti.com.cn
ZHCSO90A –NOVEMBER 2022 –REVISED APRIL 2023
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TPS36-Q1
English Data Sheet: SLVSGE9
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS36BA12ACADDFRQ1
TPS36BA38ACADDFRQ1
TPS36CA66BECDDFRQ1
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDF
DDF
DDF
8
8
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
NLLOA
Samples
Samples
Samples
NIPDAU
NIPDAU
NLHOB
NLHOD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS36BA12ACADDFRQ1 SOT-23-
THIN
DDF
DDF
DDF
8
8
8
3000
3000
3000
180.0
180.0
180.0
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
TPS36BA38ACADDFRQ1 SOT-23-
THIN
TPS36CA66BECDDFRQ1 SOT-23-
THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS36BA12ACADDFRQ1
TPS36BA38ACADDFRQ1
TPS36CA66BECDDFRQ1
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
DDF
DDF
DDF
8
8
8
3000
3000
3000
210.0
210.0
210.0
185.0
185.0
185.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明