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PPS74533PQWDRBRQ1 [TI]

TPS745-Q1 500-mA LDO With Power-Good in Small Wettable Flank WSON Packages;
PPS74533PQWDRBRQ1
型号： PPS74533PQWDRBRQ1
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

TPS745-Q1 500-mA LDO With Power-Good in Small Wettable Flank WSON Packages
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TPS745-Q1  
SBVS355A –JUNE 2019–REVISED OCTOBER 2019  
TPS745-Q1 500-mA LDO With Power-Good in Small Wettable Flank WSON Packages  
1 Features  
3 Description  
The TPS745-Q1 is  
a 500-mA ultra-low-dropout  
1
•
AEC-Q100 qualified for automotive applications:  
Temperature grade 1: –40°C to +125°C, TA  
regulator (LDO) with power-good functionality. This  
device is available in a small 6-pin, 2-mm × 2-mm  
and a small 8-pin, 3-mm × 3-mm WSON package  
with wettable flanks to facilitate optical inspection.  
The TPS745-Q1 consumes low quiescent current and  
provides fast line and load transient performance.  
–
•
•
Device junction temperature: –40°C to 150°C  
Package:  
–
–
2-mm × 2-mm wettable flank WSON  
3-mm × 3-mm wettable flank WSON (preview)  
The TPS745-Q1 is  
a flexible device for post-  
•
•
Input voltage range: 1.5 V to 6.0 V  
Output voltage range:  
regulation by supporting an input voltage range from  
1.5 V to 6.0 V and an externally adjustable output  
range of 0.55 V to 5.5 V. The device also features  
fixed output voltages for powering common voltage  
rails.  
–
–
Fixed option: 0.65 V to 5.0 V  
Adjustable option: 0.55 V to 5.5 V  
•
•
•
High PSRR: 45 dB at 100 kHz  
The TPS745-Q1 has a power-good (PG) output that  
monitors the voltage at the feedback pin to indicate  
the status of the output voltage. The EN input and PG  
output can be used for sequencing multiple power  
supplies in the system.  
Output accuracy: ±0.85% (25ºC), ±1.5% maximum  
Power-good output options:  
–
Open-drain and push-pull  
Ultra-low dropout:  
160 mV (max) at 500 mA (3.3 VOUT  
Stable with a 1-µF or larger capacitor  
•
The TPS745-Q1 is stable with small ceramic output  
capacitors, allowing for a small overall solution size.  
A precision band-gap and error amplifier provides  
high accuracy of ±0.85% (max) at 25°C and ±1.5%  
(max) over temperature. This device includes  
integrated thermal shutdown, current limit, and  
undervoltage lockout (UVLO) features. The TPS745-  
Q1 has an internal foldback current limit that helps  
reduce the thermal dissipation during short-circuit  
events.  
–
)
•
•
•
•
Low IQ: 25 µA (typical), 1.5 µA (shutdown)  
Active output discharge  
Low thermal resistance:  
–
–
DRV (6-pin WSON), RθJA = 80.3°C/W  
DRB (8-pin WSON), RθJA = 62.0°C/W  
(preview)  
Device Information(1)  
2 Applications  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
•
•
•
•
•
Automotive head units  
Wettable flank  
WSON (6)  
2.00 mm × 2.00 mm  
Front and rear cameras  
Automotive cluster displays  
Telematics control units  
Medium, short range radar  
TPS745-Q1  
Wettable flank  
WSON (8)(2)  
3.00 mm × 3.00 mm  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
(2) Preview package.  
Typical Application: Fixed Voltage Version  
Typical Application: Adjustable Voltage Version  
VIN  
VOUT  
VIN  
VOUT  
IN  
OUT  
IN  
OUT  
FB  
Cff  
RPG*  
TPS745-Q1  
TPS745-Q1  
CIN  
COUT  
CIN  
COUT  
R1  
R2  
EN  
PG  
EN  
RPG*  
PG  
*Pull-up resistor not required  
for push-pull option  
GND  
*Pull-up resistor not required  
for push-pull option  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
 
TPS745-Q1  
SBVS355A –JUNE 2019–REVISED OCTOBER 2019  
www.ti.com  
Table of Contents  
7.4 Device Functional Modes........................................ 19  
Application and Implementation ........................ 20  
8.1 Application Information............................................ 20  
8.2 Typical Application .................................................. 27  
Power Supply Recommendations...................... 28  
1
2
3
4
5
6
Features.................................................................. 1  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
6.1 Absolute Maximum Ratings ...................................... 4  
6.2 ESD Ratings.............................................................. 4  
6.3 Recommended Operating Conditions....................... 4  
6.4 Thermal Information.................................................. 5  
6.5 Electrical Characteristics........................................... 5  
6.6 Timing Requirements................................................ 6  
6.7 Typical Characteristics.............................................. 7  
Detailed Description ............................................ 15  
7.1 Overview ................................................................. 15  
7.2 Functional Block Diagrams ..................................... 15  
7.3 Feature Description................................................. 17  
8
9
10 Layout................................................................... 28  
10.1 Layout Guidelines ................................................. 28  
10.2 Layout Examples................................................... 29  
11 Device and Documentation Support ................. 30  
11.1 Device Support...................................................... 30  
11.2 Documentation Support ........................................ 30  
11.3 Receiving Notification of Documentation Updates 30  
11.4 Community Resources.......................................... 30  
11.5 Trademarks........................................................... 30  
11.6 Electrostatic Discharge Caution............................ 30  
11.7 Glossary................................................................ 31  
7
12 Mechanical, Packaging, and Orderable  
Information ........................................................... 31  
4 Revision History  
Changes from Original (June 2019) to Revision A  
Page  
•
Changed document status from advance information to production data.............................................................................. 1  
2
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Product Folder Links: TPS745-Q1  
 
TPS745-Q1  
www.ti.com  
SBVS355A –JUNE 2019–REVISED OCTOBER 2019  
5 Pin Configuration and Functions  
DRV Package  
6-Pin Adjustable WSON  
Top View  
DRV Package  
6-Pin Fixed WSON  
Top View  
OUT  
FB  
1
2
3
6
5
4
IN  
OUT  
NC  
1
2
3
6
5
4
IN  
Thermal  
Pad  
Thermal  
Pad  
PG  
EN  
PG  
EN  
GND  
GND  
Not to scale  
Not to scale  
DRB Package (Preview)  
8-Pin Adjustable WSON  
Top View  
DRB Package (Preview)  
8-Pin Fixed WSON  
Top View  
OUT  
NC  
1
2
3
4
8
7
6
5
IN  
OUT  
NC  
1
2
3
4
8
7
6
5
IN  
NC  
PG  
EN  
NC  
PG  
EN  
Thermal  
Pad  
Thermal  
Pad  
FB  
NC  
GND  
GND  
Not to scale  
Not to scale  
Pin Functions  
PIN  
I/O  
DESCRIPTION  
DRV  
(Fixed)  
DRV  
(Adjust)  
DRB  
(Fixed)  
DRB  
(Adjust)  
NAME  
Enable pin. Drive EN greater than VEN(HI) to turn on the regulator.  
Drive EN less than VEN(LO) to put the low-dropout regulator (LDO) into  
shutdown mode.  
EN  
4
4
5
5
Input  
This pin is used as an input to the control loop error amplifier and is  
used to set the output voltage of the LDO.  
FB  
—
3
2
3
—
4
3
4
—
—
GND  
Ground pin.  
Input pin. For best transient response and to minimize input  
impedance, use the recommended value or larger ceramic capacitor  
from IN to ground as listed in the Recommended Operating  
Conditions table and the Input and Output Capacitor Selection section.  
Place the input capacitor as close to the output of the device as  
possible.  
IN  
6
2
1
6
—
1
8
2, 3, 7  
1
8
2, 7  
1
Input  
—
No internal connection. Ground this pin for better thermal  
performance.  
NC  
OUT  
Regulated output voltage pin. A capacitor is required from OUT to  
ground for stability. For best transient response, use the nominal  
recommended value or larger ceramic capacitor from OUT to ground;  
see the Recommended Operating Conditions table and the Input and  
Output Capacitor Selection section. Place the output capacitor as  
close to output of the device as possible.  
Output  
Power-good output. Available in open-drain and push-pull topologies.  
A pullup resistor is only required for the open-drain type. For the open-  
PG  
5
5
6
6
Output drain version, if the power-good functionality is not being used, ground  
this pin or leave floating. For the push-pull version, if the power-good  
functionality is not being used, leave this pin floating.  
Copyright © 2019, Texas Instruments Incorporated  
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TPS745-Q1  
SBVS355A –JUNE 2019–REVISED OCTOBER 2019  
www.ti.com  
Pin Functions (continued)  
PIN  
I/O  
DESCRIPTION  
DRV  
(Fixed)  
DRV  
(Adjust)  
DRB  
(Fixed)  
DRB  
(Adjust)  
NAME  
The thermal pad is electrically connected to the GND node. Connect  
to the GND plane for improved thermal performance.  
Thermal Pad  
—
6 Specifications  
6.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
MAX  
UNIT  
Supply, VIN  
Enable, VEN  
6.5  
6.5  
Voltage  
Feedback, VFB  
Power-good, VPG  
Output, VOUT  
2.0  
V
6.5  
VIN + 0.3(2)  
Internally limited  
±10  
Output, IOUT  
Current  
Power-good, IPG  
Operating junction, TJ  
Storage, Tstg  
mA  
°C  
–40  
–65  
150  
Temperature  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The absolute maximum rating is VIN + 0.3 V or 6.0 V, whichever is smaller.  
6.2 ESD Ratings  
VALUE  
±2000  
±750  
UNIT  
Human-body model (HBM), per AEC Q100-002(1)  
Electrostatic discharge Charged-device model (CDM), per AEC Q100-011, corner pins  
Charged-device model (CDM), per AEC Q100-011, other pins  
V(ESD)  
V
±500  
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.  
6.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
MIN  
1.5  
0.55  
0.65  
0
NOM  
MAX  
6.0  
UNIT  
VIN  
Input voltage  
V
Adjustable only  
Fixed only  
5.5  
VOUT  
Output voltage  
V
5.0  
IOUT  
CIN  
Output current  
500  
mA  
μF  
μF  
nF  
V
Input capacitor  
Output capacitor(1)  
1
COUT  
CFF  
VEN  
fEN  
1
220  
Feed-forward capacitor  
Enable voltage  
10  
0
6.0  
10  
Enable toggle frequency  
PG voltage  
kHz  
V
VPG  
TJ  
0
6.0  
150  
Junction operating temperature  
–40  
°C  
(1) Minimum derated capacitance of 0.47 µF is required for stability.  
4
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SBVS355A –JUNE 2019–REVISED OCTOBER 2019  
6.4 Thermal Information  
TPS745-Q1  
THERMAL METRIC(1)  
DRV (WSON)  
6 PINS  
80.3  
DRB (WSON)(2)  
UNIT  
8 PINS  
62.0  
73.1  
35.1  
6.3  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
98.7  
44.8  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
6.1  
ψJB  
45.0  
35.1  
18.2  
RθJC(bot)  
20.8  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
(2) Preview package.  
6.5 Electrical Characteristics  
at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA,  
VEN = VIN, and CIN = COUT = 1 μF, unless otherwise noted. All typical values are at TJ = 25°C.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VFB  
Feedback voltage  
Adjustable only  
TJ = 25°C  
0.55  
V
–0.85%  
–1.00%  
–1.50%  
0.85%  
1.00%  
1.50%  
7.5  
Output accuracy(1)  
-40°C ≤ TJ ≤ 85°C  
-40°C ≤ TJ ≤ 150°C  
VOUT(NOM) + 0.5 V(2) ≤ VIN ≤ 6.0 V  
Line regulation  
Load regulation  
2
0.030  
25  
mV  
V/A  
0.1 mA ≤ IOUT ≤ 500 mA, VIN ≥ 2.0 V  
TJ = 25°C  
32  
36  
IGND  
Ground current  
IOUT = 0 mA  
µA  
-40°C ≤ TJ ≤ 150°C  
25  
-40°C ≤ TJ ≤ 125°C  
-40°C ≤ TJ ≤ 150°C  
0.1  
1
V
EN ≤ 0.3 V,  
ISHDN  
IFB  
Shutdown current  
µA  
µA  
1.5 V ≤ VIN ≤ 6.0 V  
0.1  
1.55  
0.1  
Feedback Pin Current  
Adjustable only  
0.01  
VOUT(NOM) < 1.0 V,  
VOUT = VOUT(NOM) - 0.2 V, VIN = 2.0 V  
ICL  
Output current limit  
515  
720  
350  
865  
400  
mA  
mA  
VOUT(NOM) ≥ 1.0 V,  
VOUT = VOUT(NOM) x 0.85, VIN = VOUT(NOM) + 1.0 V  
VOUT(NOM) < 1.0 V,  
VIN = 2.0 V  
VOUT = 0 V  
ISC  
Short-circuit current limit  
VOUT(NOM) ≥ 1.0 V,  
VIN = VOUT(NOM) + 1.0 V  
0.65 V ≤ VOUT < 0.8 V(3)  
0.8 V ≤ VOUT < 1.0 V  
1.0 V ≤ VOUT < 1.2 V  
1.2 V ≤ VOUT < 1.5 V  
1.5 V ≤ VOUT < 1.8 V  
1.8 V ≤ VOUT < 2.5 V  
2.5 V ≤ VOUT < 3.3 V  
3.3 V ≤ VOUT < 5.5 V  
f = 1 kHz  
720  
585  
420  
285  
180  
140  
105  
95  
910  
780  
600  
430  
265  
215  
170  
160  
IOUT = 500 mA,  
VOUT = 0.95 ×  
VOUT(NOM)  
VDO  
Dropout voltage  
mV  
VOUT = 1.8 V,  
VIN = 2.8 V,  
IOUT = 500 mA,  
COUT = 2.2 µF  
57  
f = 100 kHz  
42  
PSRR  
Power-supply rejection ratio  
dB  
f = 1 MHz  
35  
VN  
Output noise voltage  
Undervoltage lockout  
BW = 10 Hz to 100 kHz, VOUT = 0.9 V, VIN = 1.9 V  
53  
1.30  
1.34  
µVRMS  
V
VIN falling  
VIN rising  
1.17  
1.21  
1.42  
1.47  
VUVLO  
(1) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.  
(2) VIN = 1.5 V for VOUT < 1.0 V.  
(3) Dropout is not tested for nominal output voltages below 0.65 V since the input voltage may be below UVLO.  
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Electrical Characteristics (continued)  
at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA,  
VEN = VIN, and CIN = COUT = 1 μF, unless otherwise noted. All typical values are at TJ = 25°C.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Undervoltage lockout  
hysteresis  
VUVLO,HYST  
tSTR  
VEN(HI)  
VEN(LO)  
VIN hysteresis  
40  
mV  
From EN low-to-high transition to VOUT = VOUT(NOM)  
0.95  
x
Startup time  
500  
650  
µs  
V
EN pin high voltage  
(enabled)  
1.0  
EN pin low voltage  
(disabled)  
0.3  
V
IEN  
Enable pin current  
Pulldown resistance  
PG high threshold  
PG low threshold  
PG hysteresis  
VIN = VEN = 6.0 V  
VIN = 6.0 V  
10  
95  
92  
90  
2
nA  
RPULLDOWN  
PGHTH  
PGLTH  
PGHYST  
Ω
VOUT increasing  
VOUT decreasing  
89  
86  
96  
93  
%VOUT  
%VOUT  
%Vout  
VOUT ≥ 1.5V, ISINK = 1.0 mA  
VOUT ≥ 2.75V, ISINK = 2.0 mA  
VOUT ≥ 1.0V, ISOURCE = 0.04 mA  
VOUT ≥ 1.4V, ISOURCE = 0.2 mA  
VOUT ≥ 2.5V, ISOURCE = 0.5 mA  
VOUT ≥ 4.5V, ISOURCE = 1.0 mA  
PG pin low-level output  
voltage  
VOL(PG)  
300  
mV  
PG pin high-level output  
voltage(4)  
VOH(PG)  
0.8 x VOUT  
V
Ilkg(PG)  
TSD  
PG pin leakage current(5)  
Thermal shutdown  
VOUT > PGHTH, VPG = 6.0 V  
7
170  
155  
50  
nA  
°C  
Shutdown, temperature increasing  
Reset, temperature decreasing  
(4) Push-pull version only. The push-pull option is supported only for VOUT ≥ 1.0 V.  
(5) Open-drain version only.  
6.6 Timing Requirements  
MIN  
135  
4.5  
TYP  
MAX  
178  
5.5  
UNIT  
165  
5
µs  
PG delay time rising, time from 92% VOUT to 20%  
tPGDH  
of PG(1)  
'B' version(2)  
ms  
PG delay time falling, time from 90% VOUT to 80%  
of PG(1)  
tPGDL  
1.5  
7
10  
µs  
(1) Output overdrive = 10%.  
(2) See the Device Nomenclature table for more information on available PG timings.  
6
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6.7 Typical Characteristics  
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and  
CIN = COUT = 1 µF (unless otherwise noted)  
3.33  
3.32  
3.31  
3.3  
0.555  
0.553  
0.551  
0.549  
0.547  
0.545  
VIN = 3.8 V  
VIN = 6 V  
VIN = 1.5 V  
VIN = 6 V  
3.29  
3.28  
3.27  
-50  
-25  
0
25  
50  
75  
100 125 150 175  
-50  
-25  
0
25  
50  
75  
100 125 150 175  
Temperature (èC)  
Temperature (èC)  
D003  
D004  
VOUT = 0.55 V, IOUT = 1 mA  
VOUT = 3.3 V, IOUT = 1 mA  
Figure 1. Output Voltage vs Ambient Temperature  
Figure 2. Output Voltage vs Ambient Temperature  
5.05  
5.03  
5.01  
4.99  
4.97  
4.95  
25%  
20%  
15%  
10%  
5%  
VIN = 5.5 V  
VIN = 6 V  
0
-50  
-25  
0
25  
50  
75  
100 125 150 175  
Drift (ppm/èC)  
Temperature (èC)  
D005  
D001  
VOUT = 5 V, IOUT = 1 mA  
0.65-V, 3.3-V, and 5-V options, IOUT = 1 mA  
Figure 3. Output Voltage vs Ambient Temperature  
Figure 4. Temperature Drift Histogram (–40°C to +25°C)  
0.6  
25%  
20%  
15%  
10%  
5%  
0.45  
0.3  
0.15  
0
-0.15  
-0.3  
-0.45  
-0.6  
TJ  
œ20èC  
0èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
0
3.8  
4
4.2 4.4 4.6 4.8  
5
Input Voltage (V)  
5.2 5.4 5.6 5.8  
6
Drift (ppm/èC)  
D002  
0.65-V, 3.3-V, and 5-V options, IOUT = 1 mA  
VOUT = 3.3 V, IOUT = 1 mA  
Figure 5. Temperature Drift Histogram (25°C to 150°C)  
Figure 6. 3.3-V Line Regulation vs VIN  
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Typical Characteristics (continued)  
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and  
CIN = COUT = 1 µF (unless otherwise noted)  
0.6  
0.45  
0.3  
0.3  
0.2  
0.1  
0
0.15  
0
-0.15  
-0.3  
-0.45  
-0.6  
-0.1  
-0.2  
-0.3  
TJ  
œ20èC  
0èC  
TJ  
œ20èC  
0èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
1.5  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
6
5.5  
5.6  
5.7  
5.8  
5.9  
6
Input Voltage (V)  
VOUT = 0.55 V, IOUT = 1 mA  
Input Voltage (V)  
VOUT = 5.5 V, IOUT = 1 mA  
Figure 7. 0.55-V Line Regulation vs VIN  
Figure 8. 5.5-V Line Regulation vs VIN  
160  
140  
120  
100  
80  
900  
870  
840  
810  
780  
750  
720  
690  
660  
TJ  
œ20èC  
0èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
60  
40  
TJ  
20  
œ50èC  
œ40èC  
œ20èC  
0èC  
25èC  
85èC  
125èC  
150èC  
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5  
Output Current (A)  
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5  
Output Current (A)  
Figure 9. 3.3-V Dropout Voltage vs IOUT  
Figure 10. 0.55-V Dropout Voltage vs IOUT  
1,000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
160  
140  
120  
100  
80  
TJ  
œ20èC  
0èC  
TJ  
œ20èC  
0èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
60  
40  
20  
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5  
Output Current (A)  
0.5  
1
1.5  
2
2.5  
3
Output Voltage (V)  
3.5  
4
4.5  
5
IOUT = 500 mA  
Figure 11. 5.5-V Dropout Voltage vs IOUT  
Figure 12. VDO vs VOUT  
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Typical Characteristics (continued)  
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and  
CIN = COUT = 1 µF (unless otherwise noted)  
2,100  
1,800  
1,500  
1,200  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
TJ  
œ20èC  
0èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
600  
300  
TJ  
œ20èC  
0èC  
0
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
-300  
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5  
Output Current (A)  
0
0.6 1.2 1.8 2.4  
3
Input Voltage (V)  
3.6 4.2 4.8 5.4  
6
VEN = 0 V  
Figure 13. IGND vs IOUT  
Figure 14. ISHDN vs VIN  
560  
480  
400  
320  
240  
160  
80  
1
0.75  
0.5  
TJ  
œ20èC  
0èC  
TJ  
œ20èC  
0èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
0.25  
0
-0.25  
-0.5  
-0.75  
-1  
0
-80  
0
0.6 1.2 1.8 2.4  
3
Input Voltage (V)  
3.6 4.2 4.8 5.4  
6
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5  
Output Current (A)  
VOUT = 3.3 V, IOUT = 0 mA  
VIN = 3.8 V, VOUT = 3.3 V  
Figure 15. IQ vs VIN  
Figure 16. 3.3-V Load Regulation vs IOUT  
0.6  
0.45  
0.3  
1
0.75  
0.5  
TJ  
œ20èC  
0èC  
TJ  
œ20èC  
0èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
0.15  
0
0.25  
0
-0.15  
-0.3  
-0.45  
-0.6  
-0.25  
-0.5  
-0.75  
-1  
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5  
Output Current (A)  
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5  
Output Current (A)  
VIN = 2 V, VOUT = 0.55 V  
VIN = 6 V, VOUT = 5.5 V  
Figure 17. 0.55-V Load Regulation vs IOUT  
Figure 18. 5.5-V Load Regulation vs IOUT  
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Typical Characteristics (continued)  
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and  
CIN = COUT = 1 µF (unless otherwise noted)  
640  
560  
480  
400  
320  
240  
160  
80  
92.5  
92.25  
92  
TJ  
œ20èC  
0èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
91.75  
91.5  
91.25  
91  
90.75  
90.5  
90.25  
90  
89.75  
89.5  
89.25  
89  
PGLTH  
PGHTH  
0
0
0.5  
1
1.5  
2
2.5  
3
Pulldown Current (mA)  
3.5  
4
4.5  
5
-50 -30 -10 10  
30  
50  
70 90 110 130 150  
Temperature (èC)  
Figure 19. VOUT vs IOUT Pulldown Resistor  
Figure 20. PGLTH and PGHTH vs Temperature  
40  
35  
30  
25  
20  
15  
10  
5
300  
270  
240  
210  
180  
150  
120  
90  
TJ  
œ20èC  
0èC  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
0
60  
-5  
30  
PG = 3.3 V  
50 75  
PG = 5.5 V  
-10  
-50  
0
0.2  
-25  
0
25  
100  
125  
150  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
1.8  
2
Temperature (èC)  
PG Pin Sink Current (mA)  
VIN = 3.8 V, VOUT = 3.3 V  
Figure 21. IIkg(PG) vs Temperature and PG Pin Voltage  
210  
Figure 22. VOL(PG) vs PG Pin Sink Current  
166  
164  
162  
160  
158  
156  
154  
152  
150  
TJ  
œ20èC  
0èC  
tPGDH  
œ50èC  
œ40èC  
25èC  
85èC  
125èC  
150èC  
180  
150  
120  
90  
60  
30  
0
0.2  
0.3  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1
-50  
-25  
0
25  
50  
75  
100  
125  
150  
PG Pin Sink Current (mA)  
VIN = 1.5 V, VOUT = 0.55 V  
Temperature (èC)  
Figure 23. VOL(PG) vs PG Pin Sink Current  
Figure 24. tPGDH vs Temperature  
10  
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Typical Characteristics (continued)  
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and  
CIN = COUT = 1 µF (unless otherwise noted)  
4.96  
4.94  
4.92  
4.9  
6.5  
6.1  
5.7  
5.3  
4.9  
4.5  
4.1  
3.7  
3.3  
2.9  
2.5  
tPGDH  
tPGDL  
4.88  
4.86  
4.84  
4.82  
4.8  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
Temperature (èC)  
Temperature (èC)  
B version  
Figure 25. tPGDH vs Temperature (For TPS746B Only)  
Figure 26. tPGDL vs Temperature  
840  
800  
760  
720  
680  
640  
600  
560  
520  
480  
440  
300  
250  
200  
150  
100  
50  
VEN(LO)  
VEN(HI)  
TJ  
œ20èC  
0èC  
œ50èC  
œ40èC  
125èC  
85èC  
125èC  
150èC  
0
-50  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
Temperature (èC)  
Input Voltage (V)  
VEN = 5.5 V  
Figure 27. VEN(HI) and VEN(LO) vs Temperature  
Figure 28. IEN vs VIN  
14  
13  
12  
11  
10  
9
25  
5
4.5  
4
TJ  
-20èC  
0èC  
Vin  
Vout  
20  
15  
10  
5
-50èC  
-40èC  
25èC  
85èC  
125èC  
3.5  
3
0
8
-5  
2.5  
2
7
-10  
-15  
-20  
-25  
-30  
-35  
-40  
-45  
6
5
1.5  
1
4
3
2
0.5  
0
1
0
0
100  
200  
300  
400  
Output Current (mA)  
500  
600  
700  
0
0.5  
1
Time (ms)  
1.5  
2
VOUT = 0.55 V, IOUT = 1 mA, VIN slew rate = 1 V/µs  
Figure 30. 0.55-V Line Transient  
Figure 29. 3.3-V VOUT vs IOUT  
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Typical Characteristics (continued)  
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and  
CIN = COUT = 1 µF (unless otherwise noted)  
10  
9.5  
9
120  
100  
80  
4
3.5  
3
200  
150  
100  
50  
Iout  
Vout  
Vin  
Vout  
8.5  
8
60  
40  
2.5  
2
7.5  
7
20  
0
0
1.5  
1
-50  
6.5  
6
-20  
-40  
-60  
-80  
-100  
-120  
-140  
-160  
-100  
-150  
-200  
-250  
-300  
5.5  
5
0.5  
0
4.5  
4
-0.5  
-1  
3.5  
3
0
50 100 150 200 250 300 350 400 450 500  
Time (us)  
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8  
Time (ms)  
2
VIN = 3.8 V, VOUT = 3.3 V, IOUT slew rate = 1 A/µs  
VOUT = 3.3 V, IOUT = 1 mA, VIN slew rate = 1 V/µs  
Figure 32. 3.3-V, 1-mA to 500-mA Load Transient  
Figure 31. 3.3-V Line Transient  
4
200  
150  
100  
50  
4
3.5  
3
200  
Iout  
Vout  
Iout  
Vout  
3.5  
3
150  
100  
50  
2.5  
2
2.5  
2
0
0
1.5  
1
-50  
1.5  
1
-50  
-100  
-150  
-200  
-250  
-300  
-100  
-150  
-200  
-250  
-300  
0.5  
0
0.5  
0
-0.5  
-1  
-0.5  
-1  
0
50 100 150 200 250 300 350 400 450 500  
Time (us)  
0
50 100 150 200 250 300 350 400 450 500  
Time (us)  
VIN = 2 V, VOUT = 0.55 V, IOUT slew rate = 1 A/µs  
VIN = 5.5 V, VOUT = 5 V, IOUT slew rate = 1 A/µs  
Figure 33. 0.55-V, 1-mA to 500-mA Load Transient  
Figure 34. 5-V, 1-mA to 500-mA Load Transient  
5
5
4.5  
4
4
3
3.5  
3
2.5  
2
2
1.5  
1
1
0.5  
0
Vout  
Venable  
Vin  
0
Vout  
Vin  
-0.5  
-1  
-1  
0
200  
400  
600  
800  
1,000  
0
200  
400  
600  
800  
1,000  
Time (us)  
Time (us)  
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 1 mA  
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 1 mA  
Figure 35. VIN Power-Up  
Figure 36. Start-Up With EN  
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Typical Characteristics (continued)  
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and  
CIN = COUT = 1 µF (unless otherwise noted)  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VIN = 3.5 V  
VIN = 3.6 V  
VIN = 3.7 V  
VIN = 3.8 V  
VIN = 3.9 V  
VIN = 4.0 V  
VIN = 4.1 V  
VIN = 4.2 V  
VIN = 4.3 V  
10  
100  
1k  
10k  
Frequency (Hz)  
100k  
1M  
10M  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
D001  
VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF  
VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF  
Figure 37. PSRR vs Frequency and VIN  
Figure 38. PSRR vs Frequency and VIN  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VIN = 3.5 V  
VIN = 3.6 V  
VIN = 3.7 V  
VIN = 3.8 V  
VIN = 3.9 V  
VIN = 4.0 V  
VIN = 4.1 V  
VIN = 4.2 V  
VIN = 4.3 V  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
VOUT = 3.3 V, IOUT = 250 mA, COUT = 2.2 µF  
VOUT = 3.3 V, IOUT = 250 mA, COUT = 2.2 µF  
Figure 39. PSRR vs Frequency and VIN  
Figure 40. PSRR vs Frequency and VIN  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VIN = 1.9 V, VOUT = 0.9 V  
VIN = 2.8 V, VOUT = 1.8 V  
VIN = 4.3 V, VOUT = 3.3 V  
COUT = 1 mF  
COUT = 2.2 mF  
COUT = 4.7 mF  
COUT = 47 mF  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
IOUT = 500 mA, COUT = 2.2 µF  
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA  
Figure 41. PSRR vs Frequency  
Figure 42. PSRR vs Frequency and COUT  
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Typical Characteristics (continued)  
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and  
CIN = COUT = 1 µF (unless otherwise noted)  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
CFF = 0 nF  
CFF = 1 nF  
CFF = 10 nF  
CFF = 100 nF  
ILOAD = 10 mA  
ILOAD = 100 mA  
ILOAD = 250 mA  
ILOAD = 500 mA  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA  
VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF  
Figure 43. PSRR vs Frequency and CFF  
Figure 44. PSRR vs Frequency and ILOAD  
20  
20  
IOUT= 10mA, 159mVRMS  
IOUT= 100mA, 160mVRMS  
IOUT= 500mA, 160mVRMS  
CFF = 0 nF, 160 mVRMS  
CFF = 1 nF, 108 mVRMS  
CFF = 10 nF, 74 mVRMS  
CFF = 100 nF, 44 mVRMS  
10  
5
10  
5
2
1
2
1
0.5  
0.5  
0.2  
0.1  
0.2  
0.1  
0.05  
0.05  
0.02  
0.01  
0.02  
0.01  
0.005  
0.005  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF,  
VRMS BW = 10 Hz to 100 kHz  
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF,  
VRMS BW = 10 Hz to 100 kHz  
Figure 45. Output Spectral Noise Density vs  
Frequency and IOUT  
Figure 46. Output Spectral Noise Density vs  
Frequency and CFF  
20  
10  
5
20  
COUT = 2.2mF, 160 mVRMS  
COUT = 4.7mF, 170 mVRMS  
COUT = 47mF, 138 mVRMS  
VIN=1.9V, VOUT=0.9V, 53mVRMS  
10  
VIN=2.8V, VOUT=1.8V, 96mVRMS  
5
VIN=3.8V, VOUT=3.3V, 160mVRMS  
2
1
2
1
0.5  
0.5  
0.2  
0.1  
0.2  
0.1  
0.05  
0.05  
0.02  
0.01  
0.02  
0.01  
0.005  
0.005  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
10  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 100 mA, CFF = 0 µF,  
VRMS BW = 10 Hz to 100 kHz  
IOUT = 500 mA, COUT = 2.2 µF, VRMS BW = 10 Hz to 100 kHz  
Figure 48. Output Spectral Noise Density vs Frequency  
Figure 47. Output Spectral Noise Density vs  
Frequency and COUT  
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7 Detailed Description  
7.1 Overview  
The TPS745-Q1 is a low-dropout regulator (LDO) that consumes low quiescent current and delivers excellent  
line and load transient performance. These characteristics, combined with low noise, good PSRR with low  
dropout voltage, make this device ideal for automotive applications.  
This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature  
for this device is –40°C to +150°C.  
7.2 Functional Block Diagrams  
IN  
OUT  
Current  
Limit  
Thermal  
Shutdown  
95 Ω  
œ
+
FB  
UVLO  
PG  
œ
+
0.90 x VREF  
EN  
Band Gap  
GND  
Logic  
Figure 49. Adjustable Version With Open-Drain Power-Good  
IN  
OUT  
Current  
Limit  
Thermal  
Shutdown  
95 Ω  
œ
+
FB  
UVLO  
PG  
œ
+
0.90 x VREF  
EN  
Band Gap  
GND  
Logic  
Figure 50. Adjustable Version With Push-Pull Power-Good  
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Functional Block Diagrams (continued)  
IN  
OUT  
Current  
Limit  
Thermal  
Shutdown  
95 Ω  
œ
+
UVLO  
PG  
œ
+
0.90 x VREF  
EN  
Band Gap  
GND  
Logic  
Figure 51. Fixed Voltage Version With Open-Drain Power-Good  
IN  
OUT  
Current  
Limit  
Thermal  
Shutdown  
95 Ω  
œ
+
UVLO  
PG  
œ
+
0.90 x VREF  
EN  
Band Gap  
GND  
Logic  
Figure 52. Fixed Voltage Version With Push-Pull Power-Good  
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7.3 Feature Description  
7.3.1 TPS745-Q1 Comparison  
Table 1 lists the three different power-good (PG) options for the TPS745-Q1.  
Table 1. TPS745-Q1 Comparison Table  
DEVICE  
POWER-GOOD DELAY  
POWER-GOOD  
TYPE  
TPS745xxPQWDRVRQ1, TPS745xxPQWDRBRQ1  
TPS745xxPBQWDRVRQ1  
150 µs  
5 ms  
Open-drain  
Open-drain  
Push-pull  
TPS745xxPCQWDRVRQ1  
150 µs  
7.3.2 Undervoltage Lockout (UVLO)  
The TPS745-Q1 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is  
greater than the rising UVLO voltage (VUVLO). This circuit ensures that the device does not exhibit any  
unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. When  
VIN is less than VUVLO, the output is connected to ground with a pulldown resistor (RPULLDOWN). When the device  
enters UVLO, the PG output is pulled low.  
7.3.3 Shutdown  
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device  
by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN. When the  
device is disabled, the PG output pin is pulled low.  
The TPS745-Q1 has an internal pulldown MOSFET that connects an RPULLDOWN resistor to ground when the  
device is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load  
resistance (RL) in parallel with the pulldown resistor (RPULLDOWN ). Equation 1 calculates the time constant:  
τ = ( RPULLDOWN × RL) / (RPULLDOWN + RL) × COUT  
(1)  
7.3.4 Foldback Current Limit  
The device has an internal current limit circuit that protects the regulator during transient high-load current faults  
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a  
brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the  
output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the  
voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output  
voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-  
circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.  
For this device, VFOLDBACK = 0.4 V × VOUT(NOM)  
.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the  
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current  
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output  
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the  
device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If  
the output current fault condition continues, the device cycles between current limit and thermal shutdown. For  
more information on current limits, see the Know Your Limits application report.  
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Figure 53 shows a diagram of the foldback current limit.  
VOUT  
Brickwall  
VOUT(NOM)  
VFOLDBACK  
Foldback  
0 V  
IOUT  
IRATED  
0 mA  
ISC  
ICL  
Figure 53. Foldback Current Limit  
7.3.5 Thermal Shutdown  
Thermal shutdown protection disables the output when the junction temperature rises to approximately 170°C.  
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the  
junction temperature cools to approximately 155°C, the output circuitry is again enabled. Depending on power  
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.  
This cycling limits regulator dissipation, protecting the regulator from damage as a result of overheating.  
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product  
of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to 150°C  
maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the  
thermal protection is triggered; use worst-case loads and signal conditions.  
The TPS745-Q1 internal protection circuitry protects against overload conditions but is not intended to be  
activated in normal operation. Continuously running the TPS745-Q1 into thermal shutdown degrades device  
reliability.  
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7.4 Device Functional Modes  
7.4.1 Device Functional Mode Comparison  
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of  
operation. See the Electrical Characteristics table for parameter values.  
Table 2. Device Functional Mode Comparison  
PARAMETER  
OPERATING MODE  
VIN  
VEN  
IOUT  
TJ  
Normal operation  
Dropout operation  
VIN > VOUT(nom) + VDO and VIN > VIN(min)  
VIN(min) < VIN < VOUT(nom) + VDO  
VEN > VEN(HI)  
VEN > VEN(HI)  
IOUT < IOUT(max)  
IOUT < IOUT(max)  
TJ < TSD(shutdown)  
TJ < TSD(shutdown)  
Disabled  
(any true condition  
disables the device)  
VIN < VUVLO  
VEN < VEN(LOW)  
Not applicable  
TJ > TSD(shutdown)  
7.4.2 Normal Operation  
The device regulates to the nominal output voltage when the following conditions are met:  
•
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO  
The output current is less than the current limit (IOUT < ICL  
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD  
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to  
less than the enable falling threshold  
)
)
)
7.4.3 Dropout Operation  
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other  
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage  
tracks the input voltage. During this mode, the transient performance of the device becomes significantly  
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load  
transients in dropout can result in large output-voltage deviations.  
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO  
,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the  
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output  
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time  
while the device pulls the pass transistor back into the linear region.  
7.4.4 Disabled  
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN  
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned  
off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal  
discharge circuit from the output to ground.  
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8 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
8.1 Application Information  
8.1.1 Adjustable Device Feedback Resistors  
Figure 54 shows that the output voltage of the TPS745P-Q1 can be adjusted from 0.55 V to 5.5 V by using a  
resistor divider network.  
VIN  
VOUT  
IN  
OUT  
FB  
Cff  
TPS745-Q1  
CIN  
COUT  
R1  
R2  
EN  
RPG  
*
PG  
GND  
*Pull-up resistor not required  
for push-pull option  
Figure 54. Adjustable Operation  
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set  
using the feedback divider resistors, R1 and R2, according to the following equation:  
VOUT = VFB × (1 + R1 / R2)  
(2)  
To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin  
current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series  
resistance, as shown in the following equation:  
R1 + R2 ≤ VOUT / (IFB × 100)  
(3)  
8.1.2 Input and Output Capacitor Selection  
The TPS745-Q1 requires an output capacitance of 0.47 µF or larger for stability. Use X5R- and X7R-type  
ceramic capacitors because these capacitors have minimal variation in value and equivalent series resistance  
(ESR) over temperature. When choosing a capacitor for a specific application be mindful of the DC bias  
characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. For best  
performance, the maximum recommended output capacitance is 220 µF.  
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor  
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input  
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves  
transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of  
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a  
higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several  
inches from the input power source.  
8.1.3 Dropout Voltage  
The TPS745-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the  
dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output  
resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the  
PMOS device behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient  
response degrade as (VIN – VOUT) approaches dropout operation.  
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Application Information (continued)  
8.1.4 Exiting Dropout  
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.  
As with other LDOs, the output can overshoot on recovery from these conditions. A ramping input supply causes  
an LDO to overshoot on start-up, as shown in Figure 55, when the slew rate and voltage levels are in the correct  
range. Use an enable signal to avoid this condition.  
Input Voltage  
Response time for  
LDO to get back into  
regulation.  
Load current discharges  
output voltage.  
VIN = VOUT(nom) + VDO  
Output Voltage  
Dropout  
VOUT = VIN - VDO  
Output Voltage in  
normal regulation.  
Time  
Figure 55. Start-Up Into Dropout  
Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are  
caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to  
the correct voltage for proper regulation. Figure 56 illustrates what is happening internally with the gate voltage  
and how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS  
)
is pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if a  
line transient occurs when the device is in dropout, the loop is not in regulation and can cause the output to  
overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If  
these transients are not acceptable, then continue to add input capacitance in the system until the transient is  
slow enough to reduce the overshoot.  
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Application Information (continued)  
Transient response  
time of the LDO  
Input Voltage  
Load current  
discharges  
output  
voltage  
Output Voltage  
VDO  
Output Voltage in  
normal regulation  
Dropout  
VOUT = VIN - VDO  
VGS voltage  
(pass device  
fully off)  
Input Voltage  
VGS voltage for  
normal operation  
VGS voltage for  
normal operation  
Gate Voltage  
VGS voltage in  
dropout (pass device  
fully on)  
Time  
Figure 56. Line Transients From Dropout  
8.1.5 Reverse Current  
As with most LDOs, excessive reverse current can damage this device.  
Reverse current flows through the body diode on the pass element instead of the normal conducting channel. At  
high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the  
following conditions:  
•
•
•
Degradation caused by electromigration  
Excessive heat dissipation  
Potential for a latch-up condition  
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute  
maximum rating of VOUT > VIN + 0.3 V:  
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current  
The output is biased when the input supply is not established  
The output is biased above the input supply  
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Application Information (continued)  
If reverse current flow is expected in the application, external protection must be used to protect the device.  
Figure 57 shows one approach of protecting the device.  
Schottky Diode  
Internal Body Diode  
IN  
OUT  
Device  
COUT  
CIN  
GND  
Figure 57. Example Circuit for Reverse Current Protection Using a Schottky Diode  
8.1.6 Power Dissipation (PD)  
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit  
board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no  
other heat-generating devices that cause added thermal stress.  
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference  
and load conditions. Equation 4 calculates power dissipation (PD).  
PD = (VIN – VOUT) × IOUT  
(4)  
NOTE  
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by  
correct selection of the system voltage rails. For the lowest power dissipation use the  
minimum input voltage required for correct output regulation.  
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal  
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an  
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.  
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.  
According to Equation 5, power dissipation and junction temperature are most often related by the junction-to-  
ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient  
air (TA).  
TJ = TA + (RθJA × PD)  
(5)  
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB  
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The  
junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC  
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.  
Figure 58 and Figure 59 illustrate the functions of RθJA and ψJB versus copper (Cu) area and thickness. These  
plots are generated with a 101.6-mm x 101.6-mm x 1.6-mm printed circuit board (PCB) of two and four layers.  
For the four-layer board, the inner planes use a 1-oz copper thickness. Outer layers are simulated with both 1-oz  
and 2-oz copper thickness. A 2 x 1 array of thermal vias of 300-µm drill diameter and 25-µm Cu plating is located  
beneath the thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case  
of the 4-layer board, the first inner GND plane.  
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Application Information (continued)  
140  
130  
120  
110  
100  
90  
2 layer PCB, 1 oz copper  
2 layer PCB, 2 oz copper  
4 layer PCB, 1 oz copper  
4 layer PCB, 2 oz copper  
80  
70  
60  
50  
40  
30  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
Cu Area Per Layer (cm2)  
thet  
Figure 58. RθJA versus Cu Area for the WSON (DRV) Package  
36  
34  
32  
30  
28  
26  
24  
22  
20  
2 layer PCB, 1 oz copper  
2 layer PCB, 2 oz copper  
4 layer PCB, 1 oz copper  
4 layer PCB, 2 oz copper  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
Cu Area Per Layer (cm2)  
psyJ  
Figure 59. ψJB versus Cu Area for the WSON (DRV) Package  
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Application Information (continued)  
As shown in Figure 60, each layer has a copper plane of equal area.  
A
2-mm  
A
1-mm  
Buried plane and bottom layer Cu ground  
planes are modeled with Area = A×A  
Figure 60. Board parameters used for simulation  
For a more comprehensive study of how thermal resistance varies with copper area and thickness, see the An  
empirical analysis of the impact of board layout on LDO thermal performance application report. As shown in  
Figure 61, modifying board layout to be more thermally enhanced can lower the RθJA value from 80.3°C/W to  
46.8°C/W or better.  
Figure 61. TPS745-Q1 (WSON) RθJA versus Board Layout  
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Application Information (continued)  
8.1.7 Power-Good Function  
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage.  
When the output voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages  
and pulls the PG pin close to GND. When the output voltage exceeds PGHTH, the PG pin becomes high  
impedance. The open-drain output requires a pullup resistor. By connecting a pullup resistor to an external  
supply, any downstream device can receive power-good as a logic signal that can be used for sequencing.  
Additionally, the open-drain output can be tied to other open-drain outputs to implement AND logic. Make sure  
that the external pullup supply voltage results in a valid logic signal for the receiving device. Using a pullup  
resistor from 10 kΩ to 100 kΩ is recommended. The push-pull power-good option does not require the pullup  
resistor and instead has a high logic signal that correlates with the output voltage of the device. The push-pull  
option is supported only for VOUT ≥ 1.0 V. The push-pull option is supported only for VOUT ≥ 1.0 V. Do not tie the  
push-pull output to other logic outputs.  
When using a feed-forward capacitor (CFF), the time constant for the LDO start-up is increased whereas the  
power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output.  
To avoid this issue, and to receive a valid PG output, make sure that the time constant of both the LDO start-up  
and the power-good output match, which can be done by adding a capacitor in parallel with the power-good  
pullup resistor. For more information, see the Pros and Cons of Using a Feedforward Capacitor with a Low-  
Dropout Regulator application report.  
The state of PG is only valid when the TPS745-Q1 operates above the minimum input voltage of the device and  
power-good is asserted, regardless of the output voltage state when the input voltage falls below the UVLO  
threshold minus the UVLO hysteresis. When the input voltage falls below approximately 0.8 V, there is not  
enough gate drive voltage to keep the open-drain, power-good device turned on and the power-good output  
pulled high. Connecting the power-good pullup resistor to the output voltage can help minimize this effect.  
8.1.8 Feed-Forward Capacitor (CFF)  
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to  
the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.  
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF  
can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros and  
Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.  
8.1.9 Start-Up Sequencing  
If VEN is greater than VUVLO rising (min), the input pin (IN) must sink 1 mA of current to avoid the device being  
turned on with a floating input pin.  
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8.2 Typical Application  
VIN  
VOUT  
IN  
OUT  
PG  
RPG*  
TPS745-Q1  
CIN  
COUT  
EN  
*Pull-up resistor not required  
for push-pull option  
Figure 62. TPS745-Q1 Typical Application  
8.2.1 Design Requirements  
Table 3 summarizes the design requirements for Figure 62.  
Table 3. Design Parameters  
PARAMETER  
Input voltage  
DESIGN REQUIREMENT  
3.3 V  
Output voltage  
1.8 V, ±1%  
Input current  
300 mA, maximum  
300-mA DC  
Output load  
Maximum ambient temperature  
105°C  
8.2.2 Detailed Design Procedure  
Input and output capacitors are required to achieve the output voltage transient requirements. Capacitance  
values of 2.2 µF are selected to give the maximum output capacitance in a small, low-cost package; see the  
Input and Output Capacitor Selection section for details.  
8.2.2.1 Input Current  
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.  
During start-up, the input current is higher as a result of the inrush current charging the output capacitor. Use  
Equation 6 to calculate the current through the input.  
C
OUT ´ dVOUT(t)  
VOUT(t)  
RLOAD  
IOUT(t)  
=
+
dt  
where:  
•
•
•
VOUT(t) is the instantaneous output voltage of the turn-on ramp  
dVOUT(t) / dt is the slope of the VOUT ramp  
RLOAD is the resistive load impedance  
(6)  
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8.2.2.2 Thermal Dissipation  
The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total  
power dissipation (PD). Use Equation 7 to calculate the power dissipation. Multiply PD by RθJA as Equation 8  
shows and add the ambient temperature (TA) to calculate the junction temperature (TJ).  
PD = (IGND+ IOUT) × (VIN – VOUT  
)
(7)  
(8)  
TJ = RθJA × PD + TA  
Calculate the maximum ambient temperature according to Equation 9 and Equation 10. The maximum ambient  
temperature is 113.86°C for the example conditions.  
TA(MAX) = TJ(MAX) – RθJA × PD  
(9)  
TA(MAX) = 150°C – 80.3°C/W × (3.3 V – 1.8 V) × (0.3 A) = 113.86°C  
(10)  
8.2.3 Application Curves  
3.5  
3
0.35  
0.3  
0.012  
0.01  
0.4  
0.3  
0.2  
0.1  
0
VOUT  
IOUT  
0.008  
0.006  
0.004  
0.002  
0
2.5  
2
0.25  
0.2  
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
-0.6  
-0.7  
1.5  
1
0.15  
0.1  
-0.002  
-0.004  
-0.006  
-0.008  
-0.01  
0.5  
0
0.05  
0
VIN  
VOUT  
0.0008  
IOUT  
-0.5  
-0.05  
0.001  
0
0.0005  
0.001  
Time (s)  
0.0015  
0.002  
0
0.0002  
0.0004  
0.0006  
Time (s)  
D007  
D006  
Figure 64. Load Transient  
Figure 63. Startup  
9 Power Supply Recommendations  
The TPS745-Q1 is designed to operate from an input voltage supply range from 1.5 V to 6.0 V. The input voltage  
range provides adequate headroom for the device to have a regulated output. This input supply must be well  
regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve output noise  
performance. Connect a low output impedance power supply directly to the IN pin of the TPS745-Q1.  
10 Layout  
10.1 Layout Guidelines  
•
•
•
•
Place input and output capacitors as close to the device as possible.  
Use copper planes for device connections to optimize thermal performance.  
Place thermal vias around the device to distribute heat.  
Only place tented thermal vias directly beneath the thermal pad of the DRV or DRB package. An untented via  
can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a  
compromised solder joint on the thermal pad.  
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10.2 Layout Examples  
COUT  
CIN  
1
2
6
5
*
RPG  
Cff  
R1  
3
4
R2  
GND PLANE  
*Pull-up resistor not required for push-pull option  
Signal via to Pin1  
Figure 65. Layout Example for the DRV Package  
CIN  
COUT  
1
2
3
4
8
7
6
5
Cff  
R1  
*
RPG  
R2  
GND PLANE  
*Pull-up resistor not required for push-pull option  
Signal via to Pin1  
Figure 66. Layout Example for the DRB Package  
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11 Device and Documentation Support  
11.1 Device Support  
11.1.1 Device Nomenclature  
Table 4. Device Nomenclature(1)(2)  
PRODUCT  
VOUT  
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used  
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V; 01 =  
adjustable).  
P indicates an active output discharge feature. All members of the TPS745-Q1 family actively discharge  
the output when the device is disabled.  
v indicates the topology of the power-good output and the timing associated with the power-good delay.  
•
•
•
If unused, indicates an open-drain power-good output with a 150-µs delay.  
If B, indicates a open-drain power-good output with a 5-ms delay.  
If C, indicates a push-pull power-good output with a 150-µs delay.  
TPS745xx(x)PvQWyyyzQ1  
Q indicates that this device is a Grade-1 device in accordance with the AEC-Q100 standard.  
W indicates the package has wettable flanks.  
yyy is the package designator.  
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).  
Q1 indicates that this device is an automotive grade (AEC-Q100) device.  
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the  
device product folder on www.ti.com.  
(2) Output voltages from 0.65 V to 5.0 V in 50-mV increments are available. Contact the factory for details and availability.  
11.2 Documentation Support  
11.2.1 Related Documentation  
For related documentation see the following:  
•
•
•
Texas Instruments, An empirical analysis of the impact of board layout on LDO thermal performance  
application report  
Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator  
application report  
11.3 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on Alert me to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
11.4 Community Resources  
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight  
from the experts. Search existing answers or ask your own question to get the quick design help you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do  
not necessarily reflect TI's views; see TI's Terms of Use.  
11.5 Trademarks  
E2E is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
11.6 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
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11.7 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
12 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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TPS745-Q1  
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www.ti.com  
PACKAGE OUTLINE  
DRV0006C  
WSON - 0.8 mm max height  
SCALE 5.500  
PLASTIC SMALL OUTLINE - NO LEAD  
2.1  
1.9  
A
B
PIN 1 INDEX AREA  
2.1  
1.9  
0.1 MIN  
(0.05)  
A
-
A
4
0
.
0
0
0
SECTION A-A  
TYPICAL  
0.8 MAX  
C
SEATING PLANE  
0.08 C  
(0.2) TYP  
0.05  
0.00  
0.9 0.1  
EXPOSED  
THERMAL PAD  
3
4
2X  
A
A
1.6 0.1  
7
1.3  
6
1
4X 0.65  
0.35  
0.25  
6X  
PIN 1 ID  
(OPTIONAL)  
0.35  
0.25  
6X  
0.1  
C A B  
C
0.05  
4223939/A 09/2017  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
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SBVS355A –JUNE 2019–REVISED OCTOBER 2019  
EXAMPLE BOARD LAYOUT  
DRV0006C  
WSON - 0.8 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
6X (0.5)  
6X (0.3)  
(0.9)  
1
6
(1.6)  
SYMM  
7
(1.1)  
4X (0.65)  
4
3
SYMM  
(1.9)  
(R0.05) TYP  
(
0.2) TYP  
VIA  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:25X  
0.07 MIN  
ALL AROUND  
0.07 MAX  
ALL AROUND  
EXPOSED  
METAL  
EXPOSED  
METAL  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
SOLDER MASK  
OPENING  
NON SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4223939/A 09/2017  
NOTES: (continued)  
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).  
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown  
on this view. It is recommended that vias under paste be filled, plugged or tented.  
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EXAMPLE STENCIL DESIGN  
DRV0006C  
WSON - 0.8 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
SYMM  
6X (0.5)  
METAL  
1
6
6X (0.3)  
(0.45)  
SYMM  
7
4X (0.65)  
(0.7)  
4
3
(R0.05) TYP  
(0.9)  
(1.9)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
EXPOSED PAD #7:  
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE  
SCALE:30X  
4223939/A 09/2017  
NOTES: (continued)  
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
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PACKAGE OUTLINE  
VSON - 1 mm max height  
DRB0008J  
PLASTIC QUAD FLAT PACK- NO LEAD  
3.1  
2.9  
B
A
PIN 1 INDEX AREA  
3.1  
2.9  
0.1 MIN  
(0.13)  
SECTION A-A  
TYPICAL  
1 MAX  
C
SEATING PLANE  
0.08 C  
0.05  
0.00  
1.75  
1.55  
(0.2) TYP  
6X 0.65  
(0.19)  
4
5
SYMM  
9
2.5  
2.3  
1.95  
1
8
0.36  
0.26  
8X  
PIN 1 ID  
(OPTIONAL)  
0.1  
0.05  
C A B  
SYMM  
C
0.5  
0.3  
8X  
4225036/A 06/2019  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.  
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www.ti.com  
EXAMPLE BOARD LAYOUT  
VSON - 1 mm max height  
DRB0008J  
PLASTIC QUAD FLAT PACK- NO LEAD  
(2.8)  
(1.65)  
8X (0.6)  
SYMM  
8X (0.31)  
1
8
6X (0.65)  
SYMM  
9
(1.95) (2.4)  
(0.95)  
(R0.05) TYP  
4
5
(Ø 0.2) VIA  
TYP  
(0.575)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE: 20X  
0.07 MAX  
ALL AROUND  
0.07 MIN  
ALL AROUND  
METAL  
SOLDER MASK  
OPENING  
EXPOSED METAL  
EXPOSED METAL  
SOLDER MASK  
OPENING  
METAL  
NON- SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4225036/A 06/2019  
NOTES: (continued)  
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature  
number SLUA271 (www.ti.com/lit/slua271).  
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown  
on this view. It is recommended that vias under paste be filled, plugged or tented.  
www.ti.com  
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SBVS355A –JUNE 2019–REVISED OCTOBER 2019  
EXAMPLE STENCIL DESIGN  
VSON - 1 mm max height  
DRB0008J  
PLASTIC QUAD FLAT PACK- NO LEAD  
(2.8)  
2X  
(1.51)  
8X (0.6)  
8X (0.31)  
SYMM  
1
8
2X  
(1.06)  
6X (0.65)  
SYMM  
(1.95)  
(0.63)  
9
(R0.05) TYP  
4
5
METAL  
TYP  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
EXPOSED PAD  
81% PRINTED COVERAGE BY AREA  
SCALE: 20X  
4225036/A 06/2019  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
www.ti.com  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Aug-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
PPS74501PQWDRBRQ1  
PPS74510PQWDRBRQ1  
PPS74511PQWDRBRQ1  
PPS74512PQWDRBRQ1  
PPS74518PQWDRBRQ1  
PPS74533PQWDRBRQ1  
TPS74501PBQWDRVRQ1  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SON  
SON  
SON  
SON  
SON  
SON  
WSON  
DRB  
DRB  
DRB  
DRB  
DRB  
DRB  
DRV  
8
8
8
8
8
8
6
3000  
3000  
3000  
3000  
3000  
3000  
3000  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
-40 to 125  
-40 to 150  
-40 to 150  
-40 to 150  
-40 to 150  
-40 to 150  
-40 to 125  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
1S36  
1ZF6  
TPS74501PCQWDRVRQ1  
ACTIVE  
WSON  
DRV  
6
3000  
Green (RoHS  
& no Sb/Br)  
Call TI  
Level-1-260C-UNLIM  
-40 to 125  
TPS74501PQWDRBRQ1  
TPS74501PQWDRVRQ1  
PREVIEW  
ACTIVE  
SON  
DRB  
DRV  
8
6
3000  
3000  
TBD  
Call TI  
Call TI  
Call TI  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
1S26  
1S66  
1S56  
1S76  
TPS74507PQWDRBRQ1  
TPS745105PQWDRVRQ1  
PREVIEW  
ACTIVE  
SON  
DRB  
DRV  
8
6
3000  
3000  
TBD  
Call TI  
Call TI  
Call TI  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
TPS74510PQWDRBRQ1  
TPS74510PQWDRVRQ1  
PREVIEW  
ACTIVE  
SON  
DRB  
DRV  
8
6
3000  
3000  
TBD  
Call TI  
SN  
Call TI  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
TPS74511PQWDRBRQ1  
TPS74511PQWDRVRQ1  
PREVIEW  
ACTIVE  
SON  
DRB  
DRV  
8
6
3000  
3000  
TBD  
Call TI  
SN  
Call TI  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
TPS745125PQWDRBRQ1  
TPS74512PQWDRBRQ1  
TPS74512PQWDRVRQ1  
PREVIEW  
PREVIEW  
ACTIVE  
SON  
SON  
DRB  
DRB  
DRV  
8
8
6
3000  
3000  
3000  
TBD  
TBD  
Call TI  
Call TI  
SN  
Call TI  
Call TI  
-40 to 125  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
1S86  
TPS74513PQWDRBRQ1  
TPS74515PQWDRBRQ1  
PREVIEW  
PREVIEW  
SON  
SON  
DRB  
DRB  
8
8
3000  
3000  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
-40 to 125  
-40 to 125  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Aug-2020  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TPS74515PQWDRVRQ1  
ACTIVE  
WSON  
DRV  
6
3000  
Green (RoHS  
& no Sb/Br)  
SN  
Level-1-260C-UNLIM  
-40 to 125  
1S96  
TPS74517PQWDRBRQ1  
TPS74518PQWDRBRQ1  
TPS74518PQWDRVRQ1  
PREVIEW  
PREVIEW  
ACTIVE  
SON  
SON  
DRB  
DRB  
DRV  
8
8
6
3000  
3000  
3000  
TBD  
TBD  
Call TI  
Call TI  
SN  
Call TI  
Call TI  
-40 to 125  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
1SA6  
1SB6  
TPS74522PQWDRVRQ1  
ACTIVE  
WSON  
DRV  
6
3000  
Green (RoHS  
& no Sb/Br)  
SN  
Level-1-260C-UNLIM  
-40 to 125  
TPS74525PQWDRBRQ1  
TPS74525PQWDRVRQ1  
PREVIEW  
ACTIVE  
SON  
DRB  
DRV  
8
6
3000  
3000  
TBD  
Call TI  
SN  
Call TI  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
1SC6  
1SD6  
1SE6  
1ZE6  
1SF6  
1T36  
TPS74528PQWDRBRQ1  
TPS74528PQWDRVRQ1  
PREVIEW  
ACTIVE  
SON  
DRB  
DRV  
8
6
3000  
3000  
TBD  
Call TI  
SN  
Call TI  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
TPS74529PQWDRBRQ1  
TPS74529PQWDRVRQ1  
PREVIEW  
ACTIVE  
SON  
DRB  
DRV  
8
6
3000  
3000  
TBD  
Call TI  
SN  
Call TI  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
TPS74530PQWDRBRQ1  
TPS74533PCQWDRVRQ1  
PREVIEW  
ACTIVE  
SON  
DRB  
DRV  
8
6
3000  
3000  
TBD  
Call TI  
Call TI  
Call TI  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
TPS74533PQWDRBRQ1  
TPS74533PQWDRVRQ1  
PREVIEW  
ACTIVE  
SON  
DRB  
DRV  
8
6
3000  
3000  
TBD  
Call TI  
SN  
Call TI  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
TPS74550PQWDRBRQ1  
TPS74550PQWDRVRQ1  
PREVIEW  
ACTIVE  
SON  
DRB  
DRV  
8
6
3000  
3000  
TBD  
Call TI  
SN  
Call TI  
-40 to 125  
-40 to 125  
WSON  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Aug-2020  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF TPS745-Q1 :  
Catalog: TPS745  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-Dec-2019  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS74501PBQWDRVRQ WSON  
1
DRV  
DRV  
6
6
3000  
3000  
180.0  
8.4  
2.2  
2.2  
1.2  
4.0  
8.0  
Q2  
TPS74501PCQWDRVRQ WSON  
1
180.0  
8.4  
2.2  
2.2  
1.2  
4.0  
8.0  
Q2  
TPS74501PQWDRVRQ1 WSON  
TPS745105PQWDRVRQ1 WSON  
TPS74510PQWDRVRQ1 WSON  
TPS74511PQWDRVRQ1 WSON  
TPS74512PQWDRVRQ1 WSON  
TPS74515PQWDRVRQ1 WSON  
TPS74518PQWDRVRQ1 WSON  
TPS74522PQWDRVRQ1 WSON  
TPS74525PQWDRVRQ1 WSON  
TPS74528PQWDRVRQ1 WSON  
TPS74529PQWDRVRQ1 WSON  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
6
6
6
6
6
6
6
6
6
6
6
6
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
180.0  
180.0  
180.0  
180.0  
180.0  
180.0  
180.0  
180.0  
180.0  
180.0  
180.0  
180.0  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
TPS74533PCQWDRVRQ WSON  
1
TPS74533PQWDRVRQ1 WSON  
TPS74550PQWDRVRQ1 WSON  
DRV  
DRV  
6
6
3000  
3000  
180.0  
180.0  
8.4  
8.4  
2.2  
2.2  
2.2  
2.2  
1.2  
1.2  
4.0  
4.0  
8.0  
8.0  
Q2  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-Dec-2019  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS74501PBQWDRVRQ1  
TPS74501PCQWDRVRQ1  
TPS74501PQWDRVRQ1  
TPS745105PQWDRVRQ1  
TPS74510PQWDRVRQ1  
TPS74511PQWDRVRQ1  
TPS74512PQWDRVRQ1  
TPS74515PQWDRVRQ1  
TPS74518PQWDRVRQ1  
TPS74522PQWDRVRQ1  
TPS74525PQWDRVRQ1  
TPS74528PQWDRVRQ1  
TPS74529PQWDRVRQ1  
TPS74533PCQWDRVRQ1  
TPS74533PQWDRVRQ1  
TPS74550PQWDRVRQ1  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
DRV  
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
203.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
Pack Materials-Page 2  
GENERIC PACKAGE VIEW  
DRV 6  
WSON - 0.8 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
Images above are just a representation of the package family, actual package may vary.  
Refer to the product data sheet for package details.  
4206925/F  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you  
permission to use these resources only for development of an application that uses the TI products described in the resource. Other  
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third  
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,  
damages, costs, losses, and liabilities arising out of your use of these resources.  
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on  
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable  
warranties or warranty disclaimers for TI products.  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2020, Texas Instruments Incorporated  

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