PTB48511AAH [TI]
2-OUTPUT 65W DC-DC REG PWR SUPPLY MODULE, ROHS COMPLIANT, DIP-8;型号: | PTB48511AAH |
厂家: | TEXAS INSTRUMENTS |
描述: | 2-OUTPUT 65W DC-DC REG PWR SUPPLY MODULE, ROHS COMPLIANT, DIP-8 输出元件 |
文件: | 总17页 (文件大小:572K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Not Recommended for New Designs
PTB48510
PTB48511
www.ti.com
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
DUAL COMPLEMENTARY-OUTPUT DC/DC CONVERTER FOR DSL
Check for Samples: PTB48510, PTB48511
1
FEATURES
•
Dual Complementary Outputs
(±5 V, ±12 V, or ±15 V)
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Range: 36 V to 75 V
On/Off Enable for Sequencing
1500 VDC Isolation
Overcurrent Protection
Overvoltage Protection (PTB48511 only)
Over Temperature Shutdown
Undervoltage Lockout
DESCRIPTION
The PTB4851x series of isolated DC/DC converter
modules produce a complementary pair of regulated
supply voltages for powering line-driver devices in
xDSL telecom applications. The modules operate
from a standard telecom (–48 V) central office (CO)
supply and can provide up to a 72 W of power in a
balanced load configuration.
Temperature Range: –40°C to 85°C
Industry Standard Outline
Fixed Frequency Operation
Synchronizes with PTB48500
Powers Line Drivers for AC-7 and Other xDSL
Chipsets
The A-suffix module (±5 V) is designed to power the
line driver devices for the AC-7 ADSL chipset. Other
voltage options powers other analog applications
requiring a complementary supply with relatively
balanced loads.o
•
Safety Approvals:
–
–
EN 60950
UL/cUL 60950
STAND-ALONE APPLICATION
Both the PTB48510 and PTB48511 include an
“on/off” enable control, output current limit, over-
temperature protection, and input under-voltage
lockout (UVLO). The PTB48511 adds output
overvoltage protection (OVP).
PTB4851x
+V
I
1
5
+V
V
O1
I
I
O1
L
O
A
D
The control inputs, Enable and Sync In, are
compatible with the EN Out and Sync Out signals of
the PTB48500 DC/DC converter. This allows the
power-up and switching frequency of the PTB4851x
modules to be directly controlled from a PTB48500.
Together the PTB48500 and PTB4851xA converters
meet all the system power and sequencing
requirements of the AC- ADSL chipset.
COM
2
3
4
Sync In
Enable
COM
6
7
8
I
O2
L
O
A
D
V Adj
O
The PTB4851x uses double-sided surface mount
technology contruction. The package size is based on
the industry standard outline and does not require a
heatsink. Both through-hole and surface mount pin
configurations are available.
-V
I
-V
*V
I
O2
*V @ | V
|
O1
O2
*V is the negative voltage.
O2
UDG-07040
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
Not Recommended for New Designs
PTB48510
PTB48511
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
www.ti.com
ORDERING INFORMATION
BASE DEVICE NUMBER. (PTB4851xxx)
OUTPUT VOLTAGE
(PTB4851xx)
PACKAGE OPTIONS (PT4851xx)
ORDER
VOLTAGE
PACKAGE
DESCRIPTION
PREFIX
CODE
(V)
CODE
DESCRIPTION
REFERENCE(1)
PTB48510xxx Basic model
A
B
C
±5
AH
AS
Horizontal T/H
SMD, Standard(3)
ERK
ERL
Adds output overvoltage protection(2)
±12
±15(4)
PTB48511xxx
(1) Reference the applicable package reference drawing for the dimensions and PC board layout
(2) Output overvoltage protection
(3) Standard option specifies 63/37, Sn/Pb pin solder material
(4) ±15-V output is not available with the PTB48511
Environmental and General Specifications
(Unless otherwise stated, all voltages are with respect to VI2)
VALUE
36 to 75
UNIT
VDC
V
VI
Input Voltage Range
Isolation Voltage
Capacitance
Over output load range
Input-output/input/case
Input to output
1500
1500
10
pF
Resistance
Input to output
mΩ
TA
Operating Temperature Range
Over VI Range
–40 to 85
115(1)
10
Shutdown threshold
Hysterisis
OTP
Over-Temperature Protection
°C
Treflow
Ts
Solder Reflow Temperature
Storage Temperature
Surface temperature of module body or pins
235(2)
–55 to 125
500
Per Mil-STD-883D, Method 2002.3 T/H
Mechanical Shock
G
1 ms, 1/2 Sine, mounted
SMD
250
T/H
10
Mil-STD-883D, Method 2007.2
20-2000 Hz
Mechanical Vibration Mil-STD-883D
G
SMD
5
Weight
28
grams
Flammability
Meets UL 94V-O
(1) This parameter is assured by design.
(2) During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated
maximum.
2
Copyright © 2004–2007, Texas Instruments Incorporated
Not Recommended for New Designs
PTB48510
PTB48511
www.ti.com
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, TA = 25°C, VI = 48 V, CI = 0 μF, CO = 0 μF, IO1 = IO2 = 3.25 A maximum)
PTB4851xA
TYP
PARAMETER
TEST CONDITIONS
MIN
0
MAX UNIT
(1)
PO
Output Power
Total output power from VO1 or VO2
65
W
A
IO1, IO2
IO1 - IO2
Output Current
Over VI range, IO1 ≤ 0.1 A or IO2 ≤ 0.1 A
0
6.5(2)
1(3)
Output Load Imbalance
I
O1 ≤ 0.1 A or IO2 ≤ 0.1 A
0
A
Includes set point, line, load, IO1 ≤ 0.1 A or IO2 ≤ 0.1 A
–40°C ≤ TA ≤ 85°C
VO1, VO2
Output Voltage
4.75(2)
5
5.25(2)
V
VO1
±1
±1
–40°C ≤ TA ≤ 85°C, IO1 ≤ 0.1 A or IO2 ≤ 0.1
A
ΔRegtemp
Temperature Variation
%VO
VO2
ΔRegline
ΔRegload
η
Line Regulation
Load Regulation
Efficiency
Over VI range, balanced load
VO1 or VO2
VO1 or VO2
±0.1
±0.2
86%
20
±0.4
±0.4
%VO
%VO
Over IO1, IO2range, balanced load
Vr
VO Ripple (pk-pk)
20 MHz bandwidth, CO = 10-μF tantalum capacitor
0.11 A/μs load step, 50% to 75% IO1 or IO2 maximum
VO1 or VO2 overshoot/undershoot
30(4) mVpp
ttr
30
μs
Transient Response
Overcurrent Threshold
Overvoltage Threshold
ΔVtr
±1.0
7.5
%VO
IOtrip
VI = 36 V, reset followed by auto-recovery
6.8
NA
5.9
10
NA
7
A
V
A
PTB48510
VO1(trip)
,
(5)
Outputs latched off
VO2(trip)
PTB48511
IO1(pk) IO2(pk)
Duty
12.5
10%
Short Circuit Current
Continuous overcurrent trip, IO1 = IO2
VO1 or VO2 adjust simultaneously
VO1(adj)
,
Output Voltage Adjust
Range
3.5
5.5
V
VO2(adj)
f S
Switching Frequency
Over VI and IO ranges
VI increasing
440
470(6)
33
500
kHz
VI on
VI off
Undervoltage lockout
V
VI decreasing
32
On/Off Enable (pin 3)
High-level input voltage
Low-level input voltage
Low-level input current
Standby Input Current
Start-up Time
VIH
VIL
IIL
3.6
75(7)
0.8
Referenced to VI (pin 4)
Pin 3 connected
V
–0.2
–1
mA
mA
ms
μF
II standby
2
10
3
tON
CI
IO1 ≤ 0.1 A or IO2 ≤ 0.1 A, VO1 or VO2 rising 0 to 0.95 (typ)
6
0
22
Internal Input Capacitance
External Output
Capacitance
5000(8
CO
Capacitance from either output to COM (pin 6)
μF
)
PTB48510A
PTB48511A
2.7
2.5
Per Telcordia SR-332 50% stress,
TA = 40°C, ground benign
MTBF
Reliability
106 hrs
(1) See Safe Operating Area curves or contact the factory for the appropriate derating.
(2) Under balanced load conditions, load current flowing out of VO1 is balanced to within ±0.1 A of that flowing into VO2
.
(3) A load imbalance is the difference in current flowing from VO1 to VO2. The module can operate with a higher imbalance but with reduced
specifications.
(4) Output voltage ripple is measured with a 10-μF tantalum capacitor connected from VO1 (pin 5) or VO2 (pin 8), to COM (pin 6).
(5) If the overvoltage threshold is exceeded by either regulated output the module will shut down, turning both outputs off. This is a latched
condition, which can only by reset by removing and then re-applying the module's input power.
(6) This is the free-running frequency. The module can be made to synchronize with the PTB48500 when both modules are used together
in a system.
(7) The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is
diode protected and may be connected to VI. The open-circuit voltage is 5 V maximum. If it is left open circuit the converter operates
when input power is applied.
(8) Electrolytic capacitors with very low equivalent series resistance (ESR) may induce instability when used on the output. Consult the
factory before using capacitors with organic, or polymer-aluminum type electrolytes.
Copyright © 2004–2007, Texas Instruments Incorporated
3
Not Recommended for New Designs
PTB48510
PTB48511
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
www.ti.com
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, TA = 25°C, VI = 48 V, CI = 0 μF, CO = 0 μF, IO1 = IO2 = 3.25 A maximum)
PTB4851xB
TYP
PARAMETER
TEST CONDITIONS
MIN
0
MAX
72(1)
3(2)
UNIT
W
PO
Output Power
Total output power from VO1or VO1
IO1 or IO2
IO1 - IO2
Output Current
Over VI range, IO1 ≤ 0.1 A or IO2 ≤ 0.1 A ≤ 0.1 A
0
A
Output Load Imbalance
IO1 ≥ 0.1 A, IO2 ≥ 0.1 A
0
1(3)
A
Includes set point, line, load, IO1 ≤ 0.1 A or IO2 ≤ 0.1 A ≤
0.1 A
–40°C ≤ TA ≤ 85°C
VO1 or VO2 Output Voltage
11.6(2)
12 12.4(2)
±1
V
–40°C ≤ TA ≤ 85°C, IO1 ≤ 0.1 A or IO2 ≤ 0.1 VO1 or VO2
ΔRegtemp
Temperature Variation
%VO
A
ΔRegline
ΔRegload
η
Line Regulation
Load Regulation
Efficiency
Over VI range, balanced load
VO1 or VO2
VO1 or VO2
±0.05
±0.5
±1
%VO
%VO
Over IO1 or IO2 range, balanced load
±0.1
89%
20
Vr
VO Ripple (pk-pk)
20 MHz bandwidth, CO = 10 μF tantalum capacitor
0.1 A/μs load step, 50% to 75% IO1 or IO2 maximum
VO1 or VO2 overshoot/undershoot
80(4)
mVpp
μs
ttr
30
Transient Response
Overcurrent Threshold
Overvoltage Threshold
ΔVtr
±1
%VO
A
IOtrip
VI = 36 V, reset followed by auto-recovery
3.3
NA
14
3.8
5
NA
17
PTB48510A
VO1(trip)
,
(5)
Outputs latched off
V
A
VO2(trip)
PTB48511A
IO1(pk) IO2(pk)
Duty
15.8
6
Short Circuit Current
Continuous overcurrent trip, IO1 = IO2
VO1 and VO2 adjust simultaneously
10%
VO1(adj)
,
Output Voltage Adjust
Range
6.5
13.4
500
V
VO2(adj)
f S
Switching Frequency
Over VI and IO ranges
VI increasing
440
480(6)
33
kHz
VI on
VI off
Under-Voltage Lockout
V
VI decreasing
32
On/Off Enable (pin 3)
High-level input voltage
Low-level input voltage
Low-level input current
Standby Input Current
Start-up Time
Referenced to VI (pin 4)
VIH
VIL
IIL
3.6
75(7)
0.8
V
–0.2
–1
mA
mA
ms
μF
II standby
Pin 3 open circuit
2
12
3
tON
CI
IO1 ≤ 1 A or IO2 ≤ 1 A, VO1 or VO2 rising 0 to 0.95 (typ)
6
0
18
Internal Input Capacitance
External Output
Capacitance
3000(8
CO
Capacitance from either output to COM (pin 6)
μF
)
PTB48510B
PTB48511B
2.8
2.5
Per Telcordia SR-332 50% stress,
TA = 40°C, ground benign
MTBF
Reliability
106 Hrs
(1) See Safe Operating Area curves or contact the factory for the appropriate derating.
(2) Under balanced load conditions, load current flowing out of VO1 is balanced to within ±0.1 A of that flowing into VO2
.
(3) A load imbalance is the difference in current flowing from VO1 to VO2. The module can operate with a higher imbalance but with reduced
specifications.
(4) Output voltage ripple is measured with a 10 μF tantalum capacitor connected from VO1 (pin 5) or VO2 (pin 8), to COM (pin 6).
(5) If the overvoltage threshold is exceeded by either regulated output the module will shut down, turning both outputs off. This is a latched
condition, which can only by reset by removing and then re-applying the module's input power.
(6) This is the free-running frequency. The module can be made to synchronize with the PTB48500 when both modules are used together
in a system.
(7) The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is
diode protected and may be connected to VI. The open-circuit voltage is 5 V maximum. If it is left open circuit the converter operates
when input power is applied.
(8) Electrolytic capacitors with very low equivalent series resistance (ESR) may induce instability when used on the output. Consult the
factory before using capacitors with organic, or polymer-aluminum type electrolytes.
4
Copyright © 2004–2007, Texas Instruments Incorporated
Not Recommended for New Designs
PTB48510
PTB48511
www.ti.com
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, TA = 25°C, VI = 48 V, CI = 0 μF, CO = 0 μF, IO1 = IO2 = 3.25 A maximum)
PTB4851xC
TYP
PARAMETER
TEST CONDITIONS
MIN
0
MAX
66(1)
2.2(2)
1(3)
UNIT
W
PO
Output Power
Total output power from VO1 or VO2
IO1 or IO2
IO1 - IO2
Output Current
Over VI range, IO1 ≤ 0.1 A or IO2 ≤ 0.1 A
0
A
Output Load Imbalance
I
O1 ≤ 0.1 A or IO2 ≤ 0.1 A
0
A
Includes set point, line, load, IO1 - IO2 ≤ 0.1 A,
–40°C ≤ TA ≤ 85°C
VO1 or VO2 Output Voltage
14.5(2)
15 15.5(2)
±1
V
–40°C ≤ TA ≤ 85°C, IO1 ≤ 0.1 A or IO2 ≤ 0.1 VO1 or VO2
A
ΔRegtemp
Temperature Variation
%VO
ΔRegline
ΔRegload
η
Line Regulation
Load Regulation
Efficiency
Over VI range, balanced load
Over IO1 or IO2 range, balanced load
IO1 = IO2
VO1 or VO2
VO1 or VO2
±0.05
±0.5
±1
%VO
%VO
±0.1
90%
Vr
VO Ripple (pk-pk)
20 MHz bandwidth, CO = 10 μF tantalum capacitor
0.1 A/μs load step, 50% to 75% IO1 or IO2 maximum
VO1 or VO2 overshoot/undershoot
50 100(4)
mVpp
μs
ttr
30
±1
Transient Response
Over Current Threshold
Short Circuit Current
ΔVtr
%VO
A
IOtrip
VI = 36 V, reset followed by auto-recovery
2.45
3
4.5
3.85
IO1(pk) IO2(pk)
Duty
A
Continuous overcurrent trip, IO1 = IO2
VO1 and VO2 adjust simultaneously
10%
VO1(adj)
VO2(adj)
,
Output Voltage Adjust
Range
7.2
16.7
520
V
f S
Switching Frequency
Over VI and IO ranges
VI increasing
440
480(5)
33
kHz
VI on
VI off
Under-Voltage Lockout
V
VI decreasing
32
On/Off Enable (pin 3)
High-level input voltage
Low-level input voltage
Low-level input current
Standby Input Current
Start-up Time
Referenced to –VI (pin 4)
VIH
VIL
IIL
3.6
75(6)
0.8
V
–0.2
–1
mA
mA
ms
μF
II standby
Pin 3 open circuit
2
12
3
tON
CI
IO1 ≤ 1 A or IO2 ≤ 1 A, VO1 or VO2 or rising 0 to 0.95 (typ)
6
18
Internal Input Capacitance
External Output
Capacitance
3000(7
CO
Capacitance from either output to COM (pin 6)
0
μF
)
Per Telcordia SR-332 50% stress,
TA = 40°C, ground benign
MTBF
Reliability
2.8
106 hrs
(1) See Safe Operating Area curves or contact the factory for the appropriate derating.
(2) Under balanced load conditions, load current flowing out of VO1 is balanced to within ±0.1 A of that flowing into VO2
.
(3) A load imbalance is the difference in current flowing from VO1 to VO2. The module can operate with a higher imbalance but with reduced
specifications.
(4) Output voltage ripple is measured with a 10-μF tantalum capacitor connected from VO1 (pin 5) or VO2 (pin 8), to COM (pin 6).
(5) This is the free-running frequency. The module can be made to synchronize with the PTB48500 when both modules are used together
in a system.
(6) The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is
diode protected and may be connected to VI. The open-circuit voltage is 5 V maximum. If it is left open circuit the converter operates
when input power is applied.
(7) Electrolytic capacitors with very low equivalent series resistance (ESR) may induce instability when used on the output. Consult the
factory before using capacitors with organic, or polymer-aluminum type electrolytes.
Copyright © 2004–2007, Texas Instruments Incorporated
5
Not Recommended for New Designs
PTB48510
PTB48511
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
www.ti.com
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
The positive input supply for the module with respect to VI (or ground return). When powering the module from
a –48 V telecom central office supply, this input is connected to the primary system ground.
(1)
+VI
1
This pin is used when the PTB4851x and PTB4850x DC/DC converter modules are used together. Connecting
this pin to the Sync Out of the PTB4850x module allows the PTB4851x to be synchronized to the same switch
conversion frequency as the PTB4850x.
Sync In
Enable
2
3
This is an open-collector (open-drain) negative logic input that enables the module output. This pin is
referenced to –VI . A logic 0 at this pin enables the module's outputs, and a high impedance disables the
outputs. If this feature is not used the pin should be connected to –VI .
(2)
Note: Connecting this input directly to the EN Out pin of the PTB4850x enables the output voltages from both
converters (PTB4850x and PTB4851x) to power up in sequence.
The negative input supply for the module, and the 0 VDC reference for the Enable, and Sync In signals. When
the module is powered from a +48-V supply, this input is connected to the 48-V Return.
-VI
4
5
8
6
7
The positive output supply voltage, which is referenced to the COM node. The voltage at VO1 has the same
VO1
magnitude, but is the complement to that at VO2
The negative output supply voltage, which is referenced to the COM node. The voltage at VO2 has the same
magnitude, but is the complement to that at VO1
.
VO2
.
The secondary return reference for the module's regulated output voltages. This node is dc isolated from the
input supply pins.
COM
VOAdj
Using a single resistor, this pin allows the magnitude of both VO1 and VO2 to be adjusted together, either higher
or lower than their preset value. If not used, this pin should be left open circuit.
(1) Shaded functions indicate signals that are referenced to -VI
(2) Denotes negative logic: Open = Output Off, –VI = Normal operation.
6
Copyright © 2004–2007, Texas Instruments Incorporated
Not Recommended for New Designs
PTB48510
PTB48511
www.ti.com
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
TYPICAL CHARACTERISTICS
(1) (2)
PTB4851xA CHARACTERISTIC DATA at VI = 48 V
Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the
converter.
EFFICIENCY
vs
POWER DISSIPATION
vs
LOAD CURRENT
LOAD CURRENT
CROSS REGULATION
300
200
100
90
12
10
D V with I = 1 A
O1
O1
100
8
6
80
0
70
60
-100
4
2
-200
-300
50
0
0
1
2
I
3
4
- Load Current - A
5
6
0
1
2
3
4
(I = I ) - Load Current - A
5
6
0
1
2
3
4
(I = I ) - Load Current - A
5
6
O2
O1
O2
O1
O2
(1)
(1)
Figure 3.
Figure 1.
Figure 2.
CROSS REGULATION
SAFE OPERATING AREA
90
300
200
D V with I = 1 A
O2
O2
80
70
400 LFM
100
0
200 LFM
100 LFM
60
50
-100
-200
-300
40
30
20
Natural
Convection
V = 48 V
I
DC
0
1
2
I
3
4
- Load Current - A
5
6
0
1
2
3
4
(I = I ) - Load Current - A
5
6
O1
O1
O2
(1) (2)
Figure 4.
Figure 5.
(1) Under a balanced load, current flowing out of VO1 is equal to that flowing into VO2
.
(2) SOA curves represent the conditions at which internal components are at or below the manufacturer's maximum operating
temperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in. double-sided PCB with 1 oz. copper.
Copyright © 2004–2007, Texas Instruments Incorporated
7
Not Recommended for New Designs
PTB48510
PTB48511
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
www.ti.com
TYPICAL CHARACTERISTICS (Continued)
(1) (2)
PTB4851xB CHARACTERISTIC DATA at VI = 48 V
Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the
converter.
EFFICIENCY
vs
POWER DISSIPATION
vs
LOAD CURRENT
LOAD CURRENT
CROSS REGULATION
400
200
0
100
90
12
10
D V with I = 1 A
O1 O1
8
6
80
70
60
4
2
-200
-400
50
0
0
0.5
1.0
1.5
2.0
- Load Current - A
2.5
3.0
0
0.5
1.0
1.5
2.0
(I = I ) - Load Current - A
2.5
3.0
0
0.5
1.0
1.5
2.0
(I = I ) - Load Current - A
2.5
3.0
I
O2
O1
O2
O1
O2
(1)
(1)
Figure 8.
Figure 6.
Figure 7.
CROSS REGULATION
SAFE OPERATING AREA
400
90
80
70
D V with I = 1 A
O2
O2
200
400 LFM
200 LFM
60
50
0
100 LFM
40
30
20
-200
-400
Natural
Convection
V = 48 V
I
DC
0
0.5
1.0
1.5
2.0
- Load Current - A
2.5
3.0
0
0.5
1.0
1.5
2.0
(I = I ) - Load Current - A
2.5
3.0
I
O1
O1
O2
(1) (2)
Figure 9.
Figure 10.
(1) Under a balanced load, current flowing out of VO1 is equal to that flowing into VO2
.
(2) SOA curves represent the conditions at which internal components are at or below the manufacturer's maximum operating
temperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in. double-sided PCB with 1 oz. copper.
8
Copyright © 2004–2007, Texas Instruments Incorporated
Not Recommended for New Designs
PTB48510
PTB48511
www.ti.com
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
TYPICAL CHARACTERISTICS (Continued)
(1) (2)
PTB4851xC CHARACTERISTIC DATA at VI = 48 V
Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the
converter.
EFFICIENCY
vs
POWER DISSIPATION
vs
LOAD CURRENT
LOAD CURRENT
CROSS REGULATION
300
200
100
90
10
8
D V with I = 1 A
O1
O1
100
6
80
0
4
2
70
60
-100
-200
-300
0
50
0
0.3
0.6
0.9
1.2
1.5
(I = I ) - Load Current - A
1.8
2.1
0
0.3
0.6
0.9
1.2
1.5
- Load Current - A
1.8
2.1
0
0.3
0.6
0.9
1.2
1.5
(I = I ) - Load Current - A
1.8
2.1
I
O2
O1
O2
O1
O2
(1)
(1)
Figure 13.
Figure 11.
Figure 12.
CROSS REGULATION
SAFE OPERATING AREA
90
80
70
300
D V with I = 1 A
O2
O2
200
100
400 LFM
200 LFM
100 LFM
60
50
0
Natural
Convection
-100
40
30
20
-200
-300
V = 48 V
I
DC
0
0.3
0.6
0.9
1.2
1.5
- Load Current - A
1.8
2.1
0
0.5
1.0
1.5
2.0
(I = I ) - Load Current - A
2.5
3.0
I
O1
O1
O2
(1) (2)
Figure 14.
Figure 15.
(1) Under a balanced load, current flowing out of VO1 is equal to that flowing into VO2
.
(2) SOA curves represent the conditions at which internal components are at or below the manufacturer's maximum operating
temperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in. double-sided PCB with 1 oz. copper.
Copyright © 2004–2007, Texas Instruments Incorporated
9
Not Recommended for New Designs
PTB48510
PTB48511
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
www.ti.com
APPLICATION INFORMATION
ADJUSTING THE OUTPUT VOLTAGE OF THE PTB4851x SERIES OF DC/DC CONVERTERS
The PTB48510 and PTB48511 DC/DC converters produce a balanced pair of complimentary output voltages.
They are identified VO1 and VO2, respectively. The magnitude of both output voltages can be adjusted together as
a pair, higher or lower, by up to ±10% of their nominal. The adjustment method uses a single external resistor.1
The value of the resistor determines the adjustment magnitude, and its placement determines whether the
magnitude is increased or decreased. The resistor values can be calculated using the appropriate formula (see
below). The formula constants are given in Table 1. The placement of each resistor is as follows.
Adjust Up: To increase the magnitude of both output voltages, place a resistor R1 between VO 1Adj (pin 7) and
the VO2 (pin 8) voltage rail; see Figure 16.
Adjust Down: To decrease the magnitude of both output voltages, add a resistor (R2), between VOAdj (pin 7)
and the VO1 (pin 5) voltage rail; see Figure 17.
PTB48510
V
PTB48510
V
5
6
7
5
V
V
O1
O1
O1
O1
R
2
Adjust Down
COM
7
6
8
V Adj
O
V Adj
O
R
COM
1
Adjust Up
8
V
V
V
V
O2
O2
O2
O2
UDG-07041
UDG-07042
Figure 16. Adjust Up Resistor Placement
ADJUST RESISTOR CALCULATION
Figure 17. Adjust Down Resistor Placement
The value of the adjust resistor is calculated using one of the following equations. Use the equation for R1 to
adjust up, or (R2) to adjust down.
V R
r
o
R
[Adjust Up] +
2ǒV * VoǓ * R kW
s
1
a
(1)
(2)
oǒ2 V * VrǓ
2 ǒVo * VaǓ
R
a
ǒR2Ǔ [Adjust Down] +
* R kW
s
Where:
VO = Magitude of the original VO1 or VO2
Va = Magnitude of the adjusted voltage
Vr = The reference voltage from Table 1
RO = The resistance value in Table 1
RS = The series resistance from Table 1
10
Copyright © 2004–2007, Texas Instruments Incorporated
Not Recommended for New Designs
PTB48510
PTB48511
www.ti.com
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
Table 1. Adjustment Range and Formula Parameters
PARAMETERS
PTB4851xA
PTB4851xB
12
PTB48510C
15
VO(nom) (V)
Va(min) (V)
Va(max) (V)
Vr (V)
5
3.5
6.5
7.2
5.5
13.4
16.7
2.495
7.5
2.495
18.2
2.495
22.1
Rn (kΩ)
Rs (kΩ)
9.09
16.9
16.9
NOTES:
1. A 0.05 W rated resistor may be used. The tolerance should be 1%, with a temperature stability of 100
ppm/°C or better. Place the resistor in either the R1 or (R2) location, as close to the converter as possible.
2. Never connect capacitors to the Vo Adj pin. Capacitance added to this pin can affect the stability of the
regulated output.
3. The overvoltage protection (PTB48511x) is nominally set to 25% above the original output voltage set-
point. Increasing the magnitude of the output voltages reduces the margin between the output voltage and
the overvoltage (OV) protection threshold. This could make the module more sensitive to OV faults, as a
result of random noise and load transients.
Note: An OV fault is a latched condition that shuts down the converter's outputs. The fault can be cleared by
cycling the Enable pin, or by momentarily removing input power to the module.
CONFIGURING THE PTB4850x and PTB4851x DC/DC CONVERTERS FOR DSL APPLICATIONS
When operated as a pair, the PTB4850x and PTB4851x converters are specifically designed to provide all the
required supply voltages for powering xDSL chipsets. The PTB4850x produces two logic voltages. They include
a 3.3-V source for logic and I/O, and a low-voltage for powering a digital signal processor core. The PTB4851x
produces a balanced pair of complementary supply voltages that is required for the xDSL transceiver ICs. When
used together in these types of applications, the PTB4850x and PTB4851x may be configured for power-up
sequencing, and also synchronized to a common switch conversion frequency. Figure 19 shows the required
cross-connects between the two converters to enable these two features.
SWITCHING FREQUENCY SYNCHRONIZATION
Unsynchronized, the difference in switch frequency introduces a beat frequency into the input and output AC
ripple components from the converters. The beat frequency can vary considerably with any slight variation in
either converter’s switch frequency. This results in a variable and undefined frequency spectrum for the ripple
waveforms, which would normally require separate filters at the input of each converter. When the switch
frequency of the converters are synchronized, the ripple components are constrained to the fundamental and
higher. This simplifies the design of the output filters, and allows a common filter to be specified for the treatment
of input ripple.
POWER-UP SEQUENCING
The desired power-up sequence for the AC7 supply voltages requires that the two logic-level voltages from the
PTB4850x converter rise to regulation prior to the two complementary voltages that power the transceiver ICs.
This sequence cannot be assured if the PTB4850x and PTB4851x are allowed to power up independently,
especially if the 48-V input voltage rises relatively slowly. To ensure the desired power-up sequence, the EN Out
pin of the PTB4850x is directly connected to the activelow Enable input of the PTB4851x (see Figure 19). This
allows the PTB4850x to momentarily hold off the outputs from the PTB4851x until the logic-level voltages have
risen first. Figure 19 shows the power-up waveforms of all four supply voltages from the schematic of Figure 19.
Copyright © 2004–2007, Texas Instruments Incorporated
11
Not Recommended for New Designs
PTB48510
PTB48511
SLTS219F –FEBRUARY 2004–REVISED MARCH 2007
www.ti.com
V
CCIO
(1 V/div)
V
CORE
(1 V/div)
+V
TCVR
(5 V/div)
+V
TCVR
(5 V/div)
T - Time - 10 ms/div
Figure 18. Power-Up Sequencing Waveforms
9
V Adj
O
PTB48500A
+
1
3
5
10
6
-48 V
+V
V
V
V
V
RTN
I
O1
O2
CCIO
Input
Filter
CORE
Enable
POR
8
POR
-48 V
-V
I
COM
7
EN Out Sync Out
4
2
2
7
Sync In
V Adj
O
PTB48510A
1
3
4
5
6
8
+V
V
+V
TCVR
I
O1
Enable
COM
-V
V
-V
TCVR
I
O2
UDG-07043
Figure 19. Example of PTB4850x and PTB4851x Modules Configured for DSL Applications
12
Copyright © 2004–2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
PACKAGING INFORMATION
Orderable Device
PTB48510AAH
PTB48510BAH
PTB48510BAS
PTB48510BAZ
PTB48510CAH
PTB48510CAZ
PTB48511AAH
PTB48511AAS
PTB48511BAH
PTB48511BAZ
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
NRND
Through-
Hole Module
ERK
8
8
8
8
8
8
8
8
8
8
9
Pb-Free
(RoHS)
SN
SN
N / A for Pkg Type
NRND
NRND
Through-
Hole Module
ERK
ERL
ERL
ERK
ERL
ERK
ERL
ERK
ERL
9
9
9
9
9
9
Pb-Free
(RoHS)
N / A for Pkg Type
Surface
Mount Module
TBD
SNPB
SNAGCU
SN
Level-1-235C-UNLIM/
Level-3-260C-168HRS
NRND
Surface
Mount Module
Pb-Free
(RoHS)
Level-3-260C-168 HR
N / A for Pkg Type
Level-3-260C-168 HR
N / A for Pkg Type
Call TI
NRND
Through-
Hole Module
Pb-Free
(RoHS)
NRND
Surface
Mount Module
Pb-Free
(RoHS)
SNAGCU
SN
NRND
Through-
Hole Module
Pb-Free
(RoHS)
OBSOLETE
NRND
Surface
Mount Module
TBD
Call TI
SN
Through-
Hole Module
9
9
Pb-Free
(RoHS)
N / A for Pkg Type
Level-3-260C-168 HR
NRND
Surface
Pb-Free
(RoHS)
SNAGCU
Mount Module
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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