PTMUX6222DGSR_技术文档

TMUX6221, TMUX6222

ZHCSOX0 –MARCH 2023

TMUX622x 具有1.8V 逻辑器件的36V、低RON、1:1 (SPST)、2 沟道开关

1 特性

3 说明

• 双电源电压范围：±4.5V 至±18 V

• 单电源电压范围：4.5V 至36 V

• 低导通电阻：2.1 Ω

• –40°C 至+125°C 工作温度

• 兼容1.8V 逻辑电平

• 逻辑引脚具有集成的下拉电阻器

• 失效防护逻辑

• 轨到轨运行

TMUX622x 是互补金属氧化物半导体 (CMOS) 开关，

采用双通道 1:1 (SPST) 配置。该器件支持单电源

（4.5V 至 36 V）、双电源（±4.5V 至 ±18 V）或非对

称电源（例如， V_DD= 12V ， V_SS= –5V ）。

TMUX622x 可在源极 (Sx) 和漏极 (D) 引脚上支持从

V_SS到V_DD范围的双向模拟和数字信号。

TMUX622x 可以通过控制 SEL 引脚打开信号路径 1

（S1 至 D1）或信号路径 2（S2 至 D2）来启用或禁

用。所有逻辑控制输入均支持 1.8V 到 V_DD的逻辑电

平，因此，当器件在有效电源电压范围内运行时，可确

保TTL 和CMOS 逻辑兼容性。失效防护逻辑电路允许

先在控制引脚上施加电压，然后在电源引脚上施加电

压，从而保护器件免受潜在的损害。

• 双向运行

2 应用

• 有线网络

• 远程无线电单元

• 患者监护和诊断

• 超声波扫描仪

• 光学测试设备

• 光纤网络

• 工厂自动化和工业控制

• 可编程逻辑控制器(PLC)

• 模拟输入模块

• 交流充电（桩）站

• 半导体测试

TMUX622x 是精密开关和多路复用器系列器件。这些

器件具有非常低的导通和关断漏电流 (50pA)，因此可

用于高精度测量应用。

封装信息⁽¹⁾

封装尺寸（标称值）

器件型号

TMUX6221

TMUX6222

封装

DGS（VSSOP，

10）

3.00mm × 3.00mm

• 数据采集系统

• 燃气表

• 流量变送器

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

V_DD

V_SS

V_DD

V_SS

SW

S1

D1

D2

S1

S2

D1

D2

SW

S2

SEL1

SEL2

SEL1

SEL2

TMUX6221

(SELx = Logic 1)

TMUX6222

(SELx = Logic 1)

方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCDS452

TMUX6221, TMUX6222

ZHCSOX0 –MARCH 2023

www.ti.com.cn

Table of Contents

7.9 Crosstalk...................................................................19

7.10 Bandwidth............................................................... 19

7.11 THD + Noise............................................................20

7.12 Power Supply Rejection Ratio (PSRR)...................20

8 Detailed Description......................................................21

8.1 Overview...................................................................21

8.2 Functional Block Diagram.........................................21

8.3 Feature Description...................................................21

8.4 Device Functional Modes..........................................23

8.5 Truth Tables.............................................................. 23

9 Application and Implementation..................................24

9.1 Application Information............................................. 24

9.2 Typical Applications.................................................. 24

9.3 Power Supply Recommendations.............................26

9.4 Layout....................................................................... 26

10 Device and Documentation Support..........................28

10.1 Documentation Support.......................................... 28

10.2 Receiving Notification of Documentation Updates..28

10.3 支持资源..................................................................28

10.4 Trademarks.............................................................28

10.5 静电放电警告.......................................................... 28

10.6 术语表..................................................................... 28

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Thermal Information....................................................5

6.4 Recommended Operating Conditions.........................5

±15 V Dual Supply: Electrical Characteristics ..................6

±15 V Dual Supply: Switching Characteristics .................7

36 V Single Supply: Electrical Characteristics ................. 8

36 V Single Supply: Switching Characteristics ................ 9

12 V Single Supply: Electrical Characteristics ............... 10

12 V Single Supply: Switching Characteristics ...............11

±5 V Dual Supply: Electrical Characteristics ..................12

±5 V Dual Supply: Switching Characteristics .................13

7 Parameter Measurement Information..........................14

7.1 On-Resistance.......................................................... 14

7.2 Off-Leakage Current................................................. 14

7.3 On-Leakage Current................................................. 15

7.4 t_ON(EN)and t_OFF(EN).................................................. 16

7.5 t_{ON (VDD)}Time............................................................17

7.6 Propagation Delay.................................................... 17

7.7 Charge Injection........................................................18

7.8 Off Isolation...............................................................18

Information.................................................................... 28

11.1 Tape and Reel Information......................................29

11.2 Mechanical Data..................................................... 31

4 Revision History

DATE

REVISION

NOTES

March 2023

*

Initial Release

2

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English Data Sheet: SCDS452

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5 Pin Configuration and Functions

S1

S2

1

2

3

4

5

10

9

D1

D2

N.C.

GND

VDD

8

VSS

SEL2

SEL1

7

6

Not to scale

图5-1. DGS Package,

10-Pin VSSOP

(Top View)

表5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION⁽²⁾

NAME

S1

NO.

1

I/O

Drain pin. Can be an input or output.

S2

2

Source pin 1. Can be an input or output.

N.C.

GND

3

No internal connection. Can be shorted to GND or left floating.

Ground (0 V) reference

—

4

P

Positive power supply. This pin is the most positive power-supply potential. For reliable operation,

connect a decoupling capacitor ranging from 0.1 µF to 10 µF between V_DDand GND.

V_DD

5

6

7

P

I

Logic control input, has internal pull-down resistor. Controls the switch connection. For more

information, see 节8.5.

SEL1

SEL2

Logic control input, has internal pull-down resistor. Controls the switch connection. For more

information, see 节8.5.

I

Negative power supply. This pin is the most negative power-supply potential. In single-supply

applications, this pin can be connected to ground. For reliable operation, connect a decoupling

capacitor ranging from 0.1 µF to 10 µF between V_SSand GND.

V_SS

8

P

D2

D1

9

I/O

Drain pin. Can be an input or output.

10

(1) I = input, O = output, I/O = input and output, P = power.

(2) For what to do with unused pins, refer to 节8.4.

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Product Folder Links: TMUX6221 TMUX6222

English Data Sheet: SCDS452

TMUX6221, TMUX6222

ZHCSOX0 –MARCH 2023

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

MAX

UNIT

V

38

V_DD–V_SS

V_DD

Supply voltage

38

V

–0.5

–38

V_SS

0.5

V

V_SELor V_EN

I_SELor I_EN

V_Sor V_D

I_IK

Logic control input pin voltage (SELx)

Logic control input pin current (SELx)

Source or drain voltage (Sx, Dx)

Diode clamp current⁽³⁾

38

V

–0.5

30

V_DD+0.5

30

mA

V

–30

V_SS–0.5

–30

mA

°C

I_Sor I_{D (CONT)}

T_A

Source or drain continuous current (Sx, Dx)

Ambient temperature

I_DC+ 10 %⁽⁴⁾

150

–55

–65

T_stg

Storage temperature

150

T_J

Junction temperature

150

(1) Operation outside the Absolute Maximum Rating may cause permanent device damage. Absolute Maximum Rating do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Condition. If

used outside the Recommended Operating Condition but within the Absolute Maximum Rating, the device may not be fully functional,

and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltages are with respect to ground, unless otherwise specified.

(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.

(4) Refer to Source or Drain Continuous Current table for I_DCspecifications.

6.2 ESD Ratings

VALUE

UNIT

TMUX622x

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

±500

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/

JEDEC JS-002, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

English Data Sheet: SCDS452

4

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6.3 Thermal Information

TMUX622x

DGS (VSSOP)

10 PINS

TBD

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

TBD

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

TBD

Ψ_JT

TBD

Ψ_JB

R_θJC(bot)

TBD

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

V_SS

0

NOM

MAX

36

UNIT

V

(1)

Power supply voltage differential

V_DD–V_SS

V_DD

Positive power supply voltage

36

V

V_Sor V_D

V_SELor V_EN

Signal path input/output voltage (source or drain pin) (Sx, D)

Address or enable pin voltage

V_DD

36

V

(2)

I_Sor I_{D (CONT)}Source or drain continuous current (Sx, D)

T_AAmbient temperature

I_DC

mA

°C

125

–40

(1) V_DDand V_SScan be any value as long as 4.5 V ≤(V_DD–V_SS) ≤36 V, and the minimum V_DDis met.

(2) Refer to Source or Drain Continuous Current table for I_DCspecifications.

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English Data Sheet: SCDS452

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MAX UNIT

±15 V Dual Supply: Electrical Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

ANALOG SWITCH

25°C

2.1

2.9

3.8

Ω

V_S= –10 V to +10 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

4.5

Ω

0.05

0.5

0.25

0.3

Ω

On-resistance mismatch between V_S= –10 V to +10 V

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

Ω

channels

I_D= –10 mA

0.35

0.6

Ω

V_S= –10 V to +10 V

I_S= –10 mA

0.7

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.85

Ω

0.01

0.05

V_S= 0 V, I_S= –10 mA

Ω/°C

nA

0.15

1.6

15

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

V_D= –10 V / + 10 V

–0.15

–1.6

–15

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

0.05

0.15

1.6

15

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

V_D= –10 V / + 10 V

–0.15

–1.6

–15

I_D(OFF)

–40°C to +85°C

–40°C to +125°C

25°C

0.15

1.6

15

–0.15

–1.6

–15

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is on

V_S= V_D= ±10 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

36

0.8

2.5

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

1.5

µA

pF

I_IL

–0.1 –0.005

C_IN

3.5

POWER SUPPLY

25°C

39

7

60

70

85

25

30

45

µA

V_DD= 16.5 V, V_SS= –16.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= 16.5 V, V_SS= –16.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

English Data Sheet: SCDS452

6

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±15 V Dual Supply: Switching Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ± 10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

100

170

185

200

180

195

210

ns

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

–40°C to +85°C

–40°C to +125°C

25°C

ns

100

ns

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

ns

t_OFF

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

25°C

ns

0.19

0.2

ms

ps

V_DDrise time = 1 µs

R_L= 300 Ω, C_L= 35 pF

Device turn on time

(V_DDto output)

t_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

25°C

0.2

t_PD

Propagation delay

Charge injection

500

-15

R_L= 50 Ω, C_L= 5 pF

Q_INJ

V_S= 0 V, C_L= 100 pF

25°C

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

O_ISO

X_TALK

BW

Off-isolation

Crosstalk

25°C

dB

–70

–50

–114

–93

60

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

dB

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Crosstalk

dB

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V

MHz

dB

–3dB Bandwidth

Insertion loss

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

I_L

–0.18

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–40

V_PP= 15 V, V_BIAS= 0 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0005

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

33

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 0 V, f = 1 MHz

25°C

120

pF

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English Data Sheet: SCDS452

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MAX UNIT

36 V Single Supply: Electrical Characteristics

V_DD= +36 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +36 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

T_A

MIN

TYP

25°C

2.5

3.2

4.2

4.9

0.2

0.25

0.3

1

Ω

V_S= 0 V to 30 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.1

0.3

Ω

V_S= 0 V to 30 V

I_D= –10 mA

On-resistance mismatch between

channels

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

Ω

V_S= 0 V to 30 V

I_S= –10 mA

1.5

2

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.009

0.05

V_S= 18 V, I_S= –10 mA

Ω/°C

nA

0.25

3.5

26

V_DD= 39.6 V, V_SS= 0 V

Switch state is off

V_S= 30 V / 1 V

–0.25

–3.5

–26

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 30 V

0.05

0.25

3.5

26

V_DD= 39.6 V, V_SS= 0 V

Switch state is off

V_S= 30 V / 1 V

–0.25

–3.5

–26

I_D(OFF)

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 30 V

0.25

3.5

26

–0.25

–3.5

–26

V_DD= 39.6 V, V_SS= 0 V

Switch state is on

V_S= V_D= 30 V or 1 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

36

0.8

2.5

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

1.5

µA

pF

I_IL

–0.1 –0.005

C_IN

3.5

POWER SUPPLY

25°C

30

60

70

85

µA

V_DD= 39.6 V, V_SS= 0 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

English Data Sheet: SCDS452

8

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36 V Single Supply: Switching Characteristics

V_DD= +36 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +36 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

110

180

190

200

180

195

200

ns

V_S= 18 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

–40°C to +85°C

–40°C to +125°C

25°C

ns

90

ns

V_S= 18 V

R_L= 300 Ω, C_L= 35 pF

ns

t_OFF

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

25°C

ns

0.17

0.19

500

ms

ps

V_DDrise time = 1 µs

R_L= 300 Ω, C_L= 35 pF

Device turn on time

(V_DDto output)

t_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

25°C

t_PD

Propagation delay

Charge injection

R_L= 50 Ω, C_L= 5 pF

Q_INJ

V_S= 18 V, C_L= 100 pF

25°C

pC

–13

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

O_ISO

X_TALK

BW

Off-isolation

Crosstalk

25°C

dB

–70

–50

–112

–93

65

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

dB

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Crosstalk

dB

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V

MHz

dB

–3dB Bandwidth

Insertion loss

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

I_L

–0.19

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–60

V_PP=18 V, V_BIAS= 18 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0004

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 18 V, f = 1 MHz

25°C

35

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 18 V, f = 1 MHz

25°C

120

pF

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English Data Sheet: SCDS452

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MAX UNIT

12 V Single Supply: Electrical Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

T_A

MIN

TYP

25°C

4.6

6

7.5

8.4

0.2

0.32

0.35

2

Ω

V_S= 0 V to 10 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.08

1.2

Ω

V_S= 0 V to 10 V

I_D= –10 mA

On-resistance mismatch between

channels

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

Ω

V_S= 0 V to 10 V

I_S= –10 mA

2.2

2.4

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.017

0.05

V_S= 6 V, I_S= –10 mA

Ω/°C

nA

0.5

2

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

–0.5

–2

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 10 V

12

0.5

2

–12

–0.5

–2

0.05

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

I_D(OFF)

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 10 V

12

0.5

2

–12

–0.5

–2

V_DD= 13.2 V, V_SS= 0 V

Switch state is on

V_S= V_D= 10 V or 1 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

12

–12

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

36

0.8

2.5

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

1.5

µA

pF

I_IL

–0.1 –0.005

C_IN

3.5

POWER SUPPLY

25°C

15

45

55

65

µA

V_DD= 13.2 V, V_SS= 0 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

English Data Sheet: SCDS452

10

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12 V Single Supply: Switching Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

120

180

210

230

210

235

250

ns

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

–40°C to +85°C

–40°C to +125°C

25°C

ns

130

ns

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

ns

t_OFF

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

25°C

ns

0.19

0.2

ms

ps

V_DDrise time = 1 µs

R_L= 300 Ω, C_L= 35 pF

Device turn on time

(V_DDto output)

t_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

25°C

0.2

t_PD

Propagation delay

Charge injection

500

–6

R_L= 50 Ω, C_L= 5 pF

Q_INJ

V_S= 6 V, C_L= 100 pF

25°C

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

O_ISO

X_TALK

BW

Off-isolation

Crosstalk

25°C

dB

–70

–50

–112

–93

75

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

dB

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Crosstalk

dB

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V

MHz

dB

–3dB Bandwidth

Insertion loss

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

I_L

–0.3

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–65

V_PP= 6 V, V_BIAS= 6 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0009

C_S(OFF)

C_D(OFF)

C_S(ON)

C_D(ON)

Source off capacitance

Drain off capacitance

V_S= 6 V, f = 1 MHz

25°C

38

pF

,

On capacitance

V_S= 6 V, f = 1 MHz

25°C

110

pF

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MAX UNIT

±5 V Dual Supply: Electrical Characteristics

V_DD= +5 V ± 10%, V_SS= –5 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +5 V, V_SS= –5 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

ANALOG SWITCH

25°C

4

7.2

8.6

10

Ω

V_DD= +4.5 V, V_SS= –4.5 V

V_S= –4.5 V to +4.5 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.1

1.3

0.3

0.35

0.4

2.2

2.5

2.8

Ω

On-resistance mismatch between V_S= –4.5 V to +4.5 V

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

Ω

channels

I_D= –10 mA

Ω

V_S= –4.5 V to +4.5 V

I_D= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.019

0.05

V_S= 0 V, I_S= –10 mA

Ω/°C

nA

0.25

1

V_DD= +5.5 V, V_SS= –5.5 V

Switch state is off

V_S= +4.5 V / –4.5 V

V_D= –4.5 V / + 4.5 V

–0.25

–1

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

12

0.25

1

–12

–0.25

–1

0.05

V_DD= +5.5 V, V_SS= –5.5 V

Switch state is off

V_S= +4.5 V / –4.5 V

V_D= –4.5 V / + 4.5 V

I_D(OFF)

–40°C to +85°C

–40°C to +125°C

25°C

12

0.25

1

–12

–0.25

–1

V_DD= +5.5 V, V_SS= –5.5 V

Switch state is on

V_S= V_D= ±4.5 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

12

–12

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

36

0.8

2.5

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

1.5

µA

pF

I_IL

–0.1 –0.005

C_IN

3.5

POWER SUPPLY

25°C

26

5

45

55

65

11

14

22

µA

V_DD= +5.5 V, V_SS= –5.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= +5.5 V, V_SS= –5.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

English Data Sheet: SCDS452

12

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±5 V Dual Supply: Switching Characteristics

V_DD= +5 V ± 10%, V_SS= –5 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +5 V, V_SS= –5 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

220

300

350

380

280

330

350

ns

V_S= 3 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

–40°C to +85°C

–40°C to +125°C

25°C

ns

210

ns

V_S= 3 V

R_L= 300 Ω, C_L= 35 pF

ns

t_OFF

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

25°C

ns

0.19

500

–5

ms

ps

V_DDrise time = 1 µs

R_L= 300 Ω, C_L= 35 pF

Device turn on time

(V_DDto output)

t_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

25°C

t_PD

Propagation delay

Charge injection

R_L= 50 Ω, C_L= 5 pF

Q_INJ

V_S= 0 V, C_L= 100 pF

25°C

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

O_ISO

X_TALK

BW

Off-isolation

Crosstalk

25°C

dB

–70

–50

–117

–94

78

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

dB

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Crosstalk

dB

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V

MHz

dB

–3dB Bandwidth

Insertion loss

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

I_L

–0.35

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–68

V_PP= 5 V, V_BIAS= 0 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.001

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

40

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 0 V, f = 1 MHz

25°C

110

pF

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7 Parameter Measurement Information

7.1 On-Resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.

The on-resistance varies with input voltage and supply voltage. The symbol R_ONis used to denote on-

resistance. 图 7-1 shows the measurement setup used to measure R_ON. Voltage (V) and current (I_SD) are

measured using the following setup, where R_ONis computed as R_ON= V / I_SD

:

V

I_SD

Sx

Dx

V_S

RON

图7-1. On-Resistance

7.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state:

1. Source off-leakage current.

2. Drain off-leakage current.

Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is

off. This current is denoted by the symbol I_S(OFF)

Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.

This current is denoted by the symbol I_D(OFF)

图7-2 shows the setup used to measure both off-leakage currents.

.

V_DD

V_SS

V_DD

V_SS

I_{s (OFF)}

I_{D (OFF)}

D1

D2

D1

D2

S1

S2

S1

S2

A

I_{s (OFF)}

I_{D (OFF)}

V_D

V_S

A

GND

V_S

V_D

I_S(OFF)

I_D(OFF)

图7-2. Off-Leakage Measurement Setup

English Data Sheet: SCDS452

14

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7.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch

is on. This current is denoted by the symbol I_S(ON)

.

Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is

on. This current is denoted by the symbol I_D(ON)

.

Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for

measuring the on-leakage current, denoted by I_S(ON)or I_D(ON)

.

V_DD

V_SS

V_DD

V_SS

I_{s (ON)}

I_{D (ON)}

S1

S2

D1

D2

D1

D2

S1

S2

N.C.

A

N.C.

A

I_{s (ON)}

I_{D (ON)}

V_D

A

N.C.

V_S

GND

V_D

V_S

I_S(ON)

I_D(ON)

图7-3. On-Leakage Measurement Setup

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7.4 t_ON(EN)and t_OFF(EN)

Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen

past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level

timing can then account for the time constant added from the load resistance and load capacitance. 图 7-4

shows the setup used to measure turn-on time, denoted by the symbol t_ON(EN)

.

Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen

past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level

timing can then account for the time constant added from the load resistance and load capacitance. 图 7-4

shows the setup used to measure turn-off time, denoted by the symbol t_OFF(EN)

.

V_DD

V_SS

0.1 µF

3 V

V_SEL

0 V

V_DD

V_SS

t_r< 20 ns

t_f< 20 ns

50%

V_S

Sx

Dx

Output

t_ON

t_OFF

90%

R_L

C_L

Output

0 V

10%

GND

V_SELx

图7-4. Turn-On and Turn-Off Time Measurement Setup

English Data Sheet: SCDS452

16

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7.5 t_{ON (VDD)}Time

The t_{ON (VDD)}time is defined as the time taken by the output of the device to rise to 90% after the supply has

risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in

the system. 图7-5 shows the setup used to measure turn on time, denoted by the symbol t_{ON (VDD)}

.

V_SS

0.1 µF

V_DD

Supply

V_DD

V_SS

t_r= 10 µs

4.5 V

Ramp

V_S

D1

D2

Output

C_L

S1

0 V

t_ON

R_L

Output

V_S

S2

90%

Output

0 V

C_L

3 V

SELx

GND

图7-5. t_{ON (VDD)}Time Measurement Setup

7.6 Propagation Delay

Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal

has risen or fallen past the 50% threshold. 图 7-6 and 方程式 1 shows the setup used to measure propagation

delay, denoted by the symbol t_PD

.

V_DD

V_SS

0.1 µF

250 mV

Input

V_DD

S1

V_SS

50%

t_r< 40 ps

t_f< 40 ps

(V_S)

50 Ω

Output

C_L

D1

D2

V_S

0 V

t_PD

1

t_{PD 2}

R_L

S2

Output

V_S

Output

0 V

50%

R_L

C_L

GND

图7-6. Propagation Delay Measurement Setup

t

= max t 1, t 2

PD

(1)

Prop Delay

PD

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7.7 Charge Injection

The TMUX622x has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS

transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.

The amount of charge injected into the source or drain of the device is known as charge injection, and is

denoted by the symbol Q_C. 图 7-7 shows the setup used to measure charge injection from source (Sx) to drain

(D).

V_DD

V_SS

0.1 µF

V_S

3 V

V_SEL

V_DD

V_SS

t_r< 20 ns

t_f< 20 ns

S1

S2

Output

C_L

D1

D2

0 V

V_S

Output

C_L

Output

V_S

V_OUT

SELx

Q_INJ= C_L×

V_OUT

V_SEL

GND

图7-7. Charge-Injection Measurement Setup

7.8 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the

source pin (Sx) of an off-channel. The characteristic impedance, Z₀, for the measurement is 50 Ω. 图7-8 and 方

程式2 shows the setup used to measure off isolation. Use off isolation equation to compute off isolation.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

S1

D1

50

V_OUT

V_SIG

50

Sx/Dx

50

GND

图7-8. Off Isolation Measurement Setup

V

OUT

Off Isolation = 20 × LOG

(2)

V

S

English Data Sheet: SCDS452

18

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7.9 Crosstalk

Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied

at the source pin (Sx) of an on-channel. 图 7-9 shows the setup used to measure, and 方程式 3 shows the

equation used to calculate crosstalk.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_OUT

S1

S2

D1

50

Vs

D2

50

GND

V_SIG

图7-9. Crosstalk Measurement Setup

V

OUT

Crosstalk = 20 × LOG

(3)

V

S

7.10 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied

to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The

characteristic impedance, Z₀, for the measurement is 50 Ω. 图 7-10 and 方程式 4 shows the setup used to

measure bandwidth.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

Sx

Dx

50

V_OUT

V_SIG

50

GND

图7-10. Bandwidth Measurement Setup

V

OUT

Bandwidtℎ = 20 × Log

(4)

V

S

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7.11 THD + Noise

The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as

the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the

mux output. The on-resistance of the device varies with the amplitude of the input signal and results in distortion

when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as

THD + N.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Audio Precision

S_X

40 Ω

Dx

V_OUT

V_S

R_L

GND

图7-11. THD + N Measurement Setup

7.12 Power Supply Rejection Ratio (PSRR)

PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage

pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave

of 100 mV_PP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the

AC PSRR.

V_DD

Network Analyzer

V_SS

DC Bias

Injector

With and Without

Capacitor

50 Ω

0.1 µF

V_DD

S1

V_SS

620 mV_PP

V_IN

V_BIAS

Other Sx/

Dx pins

50 Ω

V_OUT

D1

GND

R_L

C_L

图7-12. AC PSRR Measurement Setup

V

OUT

PSRR = 20 × Log

(5)

V

IN

English Data Sheet: SCDS452

20

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8 Detailed Description

8.1 Overview

The TMUX622x is a 1:1, 2-channel switch. Each input is turned on or turned off based on the state of the select

line and enable pin.

8.2 Functional Block Diagram

The following figure shows the functional block diagram of the TMUX622x.

V_DD

V_SS

V_DD

V_SS

SW

S1

S2

D1

D2

S1

S2

D1

D2

SW

SEL1

SEL2

SEL1

SEL2

TMUX6221

(SELx = Logic 1)

TMUX6222

(SELx = Logic 1)

8.3 Feature Description

8.3.1 Bidirectional Operation

The TMUX622x conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each

channel has very similar characteristics in both directions and supports both analog and digital signals.

8.3.2 Rail-to-Rail Operation

The valid signal path input and output voltage for TMUX622x ranges from V_SSto V_DD

.

8.3.3 1.8 V Logic Compatible Inputs

The TMUX622x has 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs allows the

device to interface with processors that have lower logic I/O rails and eliminates the need for an external

translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations, refer to

Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.4 Integrated Pull-Down Resistor on Logic Pins

The TMUX622x have internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The

value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at higher voltages. This

feature integrates up to four external components and reduces system size and cost.

8.3.5 Fail-Safe Logic

The TMUX622x supports Fail-Safe Logic on the control input pins (EN and SEL) allowing for operation up to 36

V above ground, regardless of the state of the supply pins. This feature allows voltages on the control pins to be

applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system

complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-

Safe Logic feature allows the logic input pins of the TMUX622x to be ramped to +36 V while V_DDand V_SS= 0 V.

The logic control inputs are protected against positive faults of up to +36 V in powered-off condition, but do not

offer protection against negative overvoltage conditions.

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8.3.6 Latch-Up Immune

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the

low impedance path.

The TMUX622x family of devices are constructed on silicon-on-insulator (SOI) based process where an oxide

layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures

from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events

due to overvoltage or current injections. The latch-up immunity feature allows the TMUX622x family of switches

and multiplexers to be used in harsh environments.

8.3.7 Ultra-Low Charge Injection

The TMUX622x has a transmission gate topology, as shown in 图 8-1. Any mismatch in the stray capacitance

associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

OFF ON

C_GDN

C_GSN

D

S

C_GSP

C_GDP

OFF ON

图8-1. Transmission Gate Topology

The TMUX622x contains specialized architecture to reduce charge injection on the Drain (Dx). To further reduce

charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (Sx). This

will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the

Source (Sx) instead of the Drain (Dx). As a general rule, Cp should be 20x larger than the equivalent load

capacitance on the Drain (Dx). 图8-2 shows charge injection variation with different compensation capacitors on

the Source side. This plot was captured on the TMUX6219 as part of the TMUX62xx family with a 100 pF load

capacitance.

图8-2. Charge Injection Compensation

English Data Sheet: SCDS452

22

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8.4 Device Functional Modes

The TMUX622x devices have two independently selectable single-pole, single-throw switches that are turned-on

or turned-off based on the state of the corresponding select pin. The control pins can be as high as 36 V.

The TMUX622x devices can be operated without any external components except for the supply decoupling

capacitors. The SEL pins has internal pull-down resistor of 4 MΩ. If unused, tie the SEL pins to GND so that the

device does not consume additional current. For more information, see Implications of Slow or Floating CMOS

Inputs. Unused signal path inputs (S1, S2, D1, or D2) should be connected to GND.

8.5 Truth Tables

表8-1 provides the truth tables for the TMUX622x.

表8-1. TMUX6221 Truth Table

SEL x

CHANNEL x

Channel x OFF

Channel x ON

0

1

表8-2. TMUX6222 Truth Table

CHANNEL x

SEL x

0

1

Channel x ON

Channel x OFF

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

TMUX622x is part of the precision switches and multiplexers family of devices. TMUX622x offers low RON, low

on and off leakage currents and ultra-low charge injection performance. These properties make TMUX622x ideal

for implementing high precision industrial systems requiring selection of one of two inputs or outputs.

9.2 Typical Applications

9.2.1 Switched Gain Amplifier –Discrete PGA

Switches and multiplexers are commonly used in the feedback path of the amplifier circuits to provide

configurable gain control. By using various resistor values on each switch path, the TMUX622x allows the

system to have multiple gain settings. An external resistor, ensures the amplifier is not operating in an open loop

configuration, and gives up to 4 gain settings. The leakage current, on-resistance, and charge injection

performance of the TMUX622x are key specifications to evaluate when selecting a device for gain control.

图9-1 shows the TMUX622x configured to select the gain of an op-amp, creating a discrete PGA.

For more information on how to use TI's analog switches in Discrete Programmable Gain Amplifier (PGA) such

as the impact of On-Capacitance, see Choosing the Right Multiplexer for a Discrete Programmable Gain

Amplifier (PGA)

V

^DDV_SS

0.1µF

V_I/O

Processor

SEL1

SEL2

720

110

1.8V Logic I/O

Digital Processing

900

V_I/O

V_DD

-

OP

AMP

Gain / Filter

Network

ADC

V_IN

+

V_SS

图9-1. Gain Switching

English Data Sheet: SCDS452

24

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9.2.1.1 Design Requirements

For this design example, use the parameters listed in 表9-1.

表9-1. Design Parameters

PARAMETERS

Supply (V_DD

Supply (V_SS

VALUES

15 V

)

-15 V

Input or output signal range

Control logic thresholds

-15 V to 15 V (Rail-to-Rail)

1.8 V compatible

9.2.1.2 Detailed Design Procedure

The TMUX622x device can operate without any external components except for the supply decoupling

capacitors. All inputs signals passing through the switch must fall within the recommend operating conditions of

the TMUX622x including signal range and continuous current. For this design example, with a supply of +15 V

and -15 V, the signals can range from +15 V to -15 V when the device is powered.

The application shown in Switching Gain Settings demonstrates how to use the TMUX622x to control the

feedback gain of a precision op-amp. This feedback design can very sensitive to induced voltage and current

offsets. The TMUX622x has a typical on-leakage current of 100 pA which would lead to an accuracy well within

1% of a full scale 1 µA signal, thus minimizing errors from current offsets. The low on-resitance of the

TMUX622x leads to a low error in the feedback resistance and resulting gain. This additionally minimizes any

voltage offsets.

表9-2. Programable Gain and Error

SEL1

SEL2

Gain

10x

5x

Gain Error

0%

0

1

0

1

0.13%

0.16%

2x

9.2.1.3 Application Curves

The TMUX622x is capable of switching signals with minimal distortion because of the ultra-low leakage currents

and excellent on-resistance flatness. 图9-2 shows how the on-resistance for the TMUX622x varies with different

supply voltages.

T_A= 25°C

图9-2. On-Resistance vs Source or Drain Voltage

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9.3 Power Supply Recommendations

The TMUX622x operates across a wide supply range of of ±4.5 V to ±18 V (4.5 V to 36 V in single-supply

mode). The device also performs well with asymmetrical supplies such as V_DD= 12 V and V_SS= –5 V.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails

to other components. Good power-supply decoupling is important to achieve optimum performance. For

improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the

V_DDand V_SSpins to ground. Place the bypass capacitors as close to the power supply pins of the device as

possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs)

that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply

decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use

of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple

vias in parallel lowers the overall inductance and is beneficial for connections to ground and power planes.

Always ensure the ground (GND) connection is established before supplies are ramped.

9.4 Layout

9.4.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners. 图 9-3 shows progressively better techniques of rounding corners. Only the last example (BEST)

maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

2W

1W min.

W

图9-3. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance

changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via

introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference

from the other layers of the board. Be careful when designing test points, through-hole pins are not

recommended at high frequencies.

Some key considerations are:

• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and

GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as

possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.

• Keep the input lines as short as possible.

• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground

planes.

English Data Sheet: SCDS452

26

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9.4.2 Layout Example

S1

S2

D1

D2

TMUX622x

NC

VSS

SEL1

SEL2

GND

VDD

Wide (low inductance)

trace for power

C

Wide (low inductance)

trace for power

Via to ground plane

图9-4. TMUX622x Layout Example

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

• Texas Instruments, Improve Stability Issues with Low CON Multiplexers.

• Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment.

• Texas Instruments, Multiplexers and Signal Switches Glossary.

• Texas Instruments, QFN/SON PCB Attachment.

• Texas Instruments, Quad Flatpack No-Lead Logic Packages.

• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.

• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.

• Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit.

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

10.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: SCDS452

28

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11.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

K0

P1

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

W

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

PTMUX6221DGSR

PTMUX6222DGSR

VSSOP

DGS

10

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

H

W

L

Device

Package Type

Package Drawing Pins

SPQ

2500

Length (mm) Width (mm)

Height (mm)

50.0

PTMUX6221DGSR

PTMUX6222DGSR

VSSOP

DGS

10

366.0

364.0

50.0

English Data Sheet: SCDS452

30

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11.2 Mechanical Data

PACKAGE OUTLINE

DGS0010A

VSSOP - 1.1 mm max height

S

C

A

L

E

3

.

2

0

SMALL OUTLINE PACKAGE

C

SEATING PLANE

0.1 C

5.05

4.75

TYP

PIN 1 ID

AREA

A

8X 0.5

10

1

3.1

2.9

NOTE 3

2X

2

5

6

0.27

0.17

10X

3.1

2.9

1.1 MAX

0.1

C A

B

NOTE 4

0.23

0.13

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.7

0.4

0 - 8

DETAIL A

TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

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EXAMPLE BOARD LAYOUT

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

(R0.05)

TYP

SYMM

10X (0.3)

1

10

SYMM

6

5

8X (0.5)

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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English Data Sheet: SCDS452

32

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EXAMPLE STENCIL DESIGN

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

SYMM

(R0.05) TYP

10X (0.3)

1

10

SYMM

8X (0.5)

6

5

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221984/A 05/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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English Data Sheet: SCDS452

PACKAGE OUTLINE

DGS0010A

VSSOP - 1.1 mm max height

S

C

A

L

E

3

.

2

0

SMALL OUTLINE PACKAGE

C

SEATING PLANE

0.1 C

5.05

4.75

TYP

PIN 1 ID

AREA

A

8X 0.5

10

1

3.1

2.9

NOTE 3

2X

2

5

6

0.27

0.17

10X

3.1

2.9

1.1 MAX

0.1

C A

B

NOTE 4

0.23

0.13

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.7

0.4

0 - 8

DETAIL A

TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

www.ti.com

EXAMPLE BOARD LAYOUT

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

(R0.05)

TYP

SYMM

10X (0.3)

1

5

10

SYMM

6

8X (0.5)

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

SYMM

(R0.05) TYP

10X (0.3)

8X (0.5)

1

5

10

SYMM

6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221984/A 05/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	PTMUX6222DGSR
厂家：	TEXAS INSTRUMENTS
描述：	具有 1.8V 逻辑电平和闩锁效应抑制的 36V、1:1 (SPST) 2 通道精密开关（低电平有效） \| DGS \| 10 \| -40 to 125 开关
文件：	总39页 (文件大小：1885K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PTMUX6222DGSR [TI]

相关型号：

SI9130DB

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