PTPS25850A0QRPQTQ1_技术文档

TPS25850-Q1, TPS25851-Q1, TPS25852-Q1

ZHCSLZ4D –MAY 2020 –REVISED SEPTEMBER 2021

具有热管理功能和可编程电流限制的TPS2585x-Q1 2.2MHz 低EMI 双路3A USB

Type-C^®充电端口转换器

• 符合USB-IF 标准

1 特性

– Type-C 1.3 版

• 符合面向汽车应用的AEC-Q100 标准：

• 在CC 上具有3A 电流通告能力

– 温度等级1：T_A范围–40°C 至+125°C

– HBM ESD 分类等级H2

– CDM ESD 分类等级C5

• V_BUS应用和放电

• V_CONN拉电流：200mA

• USB 电缆极性检测(POL) (TPS25851-Q1)

• 针对超低EMI 要求进行了优化：

– 自动DCP 模式(TPS25850-Q1)：

– 符合CISPR25 5 类标准

• 符合BC1.2 和YD/T 1591 2009 要求的短路

模式

• 1.2V 模式

– HotRod^™封装可更大限度地减少开关节点振铃

– 展频可降低峰值发射

• 同步降压稳压器

• 2.7V 分压器3 模式

– 在2.1MHz 下具有高效率：V_IN= 13.5V、

I_{PA_BUS}= 3A 且I_{PB_BUS}= 3A 时效率为93.4%

– 18mΩ/10mΩ 低R_DS(ON)降压稳压器MOSFET

– 工作电压范围：5.5V 至26V，可承受36V 输入

– 频率可调节：200kHz 至3MHz

– 具有展频频谱抖动的FPWM

• 甩负荷和可编程T_A

• 器件T_J范围：–40°C 至+150°C

• 故障标志报告（TPS25851-Q1 和TPS25852-

Q1）：USB 过流、热关断

• USB 端口开/关控制(TPS25852-Q1)

2 应用

– 可选输出电压：5.1V、5.17V、5.3V、5.4V

• 内部电源路径：

• 汽车USB 充电端口

• 汽车USB 媒体中心

– 7mΩ/7mΩ 低R_DS(ON)内部USB 功率MOSFET

– USB 端口的高精度可编程电流限制：3.4A 下为

±10%

3 说明

TPS258x-Q1 是一款集成式 USB 充电端口解决方案，

其中包括一个能够提供最大6.6A 电流的同步直流/直流

转换器，而且它还集成了检测和控制功能，可充当

USB 电池充电1.2 和Type-C 端口。

– OUT：用于辅助负载的5.1V、200mA 电源

• 线路压降补偿：2.4A 负载下为90mV

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

3.50mm × 4.50mm

TPS25850-Q1

TPS25851-Q1

TPS25852-Q1

VQFN-HR (25)

(1) 如需了解所有不同可用选件的详细器件型号，请参阅数据表末

尾的可订购产品附录。

100

95

90

85

80

75

70

BOOT

SW

BATT

IN

SENSE

BIAS

OUT

SENSE

EN/UV

PA_BUS

PA_DP

PA_DM

PA_CC1

PA_CC2

TPS25850-Q1

TS

VIN=6V

2.1MHz

65

60

VIN=13.5V 2.1MHz

VIN=18V 2.1MHz

PB_CC2

PB_CC1

ILIM

FREQ/SYNC

VSET

0.1

1

2

3

4

5

6

PB_DM

PB_DP

Load Current(A)

PB_BUS

效率与输出电流间的关系

简化版原理图TPS25850-Q1

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSEM3

TPS25850-Q1, TPS25851-Q1, TPS25852-Q1

ZHCSLZ4D –MAY 2020 –REVISED SEPTEMBER 2021

www.ti.com.cn

Table of Contents

10.2 Functional Block Diagram.......................................24

10.3 Feature Description.................................................25

10.4 Device Functional Modes........................................42

11 Application and Implementation................................ 43

11.1 Application Information............................................43

11.2 Typical Applications.................................................43

12 Power Supply Recommendations..............................52

13 Layout...........................................................................52

13.1 Layout Guidelines................................................... 52

13.2 Layout Example...................................................... 53

13.3 Ground Plane and Thermal Considerations............53

14 Device and Documentation Support..........................55

14.1 接收文档更新通知................................................... 55

14.2 支持资源..................................................................55

14.3 Trademarks.............................................................55

14.4 Electrostatic Discharge Caution..............................55

14.5 术语表..................................................................... 55

15 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................3

6 Device Comparison Table...............................................4

7 Pin Configuration and Functions...................................5

8 Specifications.................................................................. 9

8.1 Absolute Maximum Ratings ....................................... 9

8.2 ESD Ratings .............................................................. 9

8.3 Recommended Operating Conditions ......................10

8.4 Thermal Information .................................................11

8.5 Electrical Characteristics ..........................................11

8.6 Timing Requirements ...............................................14

8.7 Switching Characteristics .........................................15

8.8 Typical Characteristics..............................................17

9 Parameter Measurement Information..........................22

10 Detailed Description....................................................23

10.1 Overview.................................................................23

Information.................................................................... 56

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (March 2021) to Revision D (September 2021)

Page

• 添加了TSP25851-Q1 和TPS25852-Q1 信息.................................................................................................... 1

Changes from Revision B (October 2020) to Revision C (March 2021)

Page

• 向特性部分添加了EMI 要求要点....................................................................................................................... 1

• 更新了文档标题...................................................................................................................................................1

• Added 图11-4 to the Application Curves section............................................................................................. 47

Changes from Revision A (June 2020) to Revision B (October 2020)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1

Changes from Revision * (May 2020) to Revision A (June 2020)

Page

• Updated IN pin description................................................................................................................................. 5

• Added USB Port Operating Modes ..................................................................................................................39

• Added Device Functional Modes .....................................................................................................................42

2

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5 说明（续）

TPS2585x-Q1 是高度集成的USB Type-C^®充电控制器系列，适用于双USB 端口应用。

该系列器件集成了一个具有内部功率MOSFET 的单片、同步、整流、降压开关模式转换器和两个具有充电端口自

动检测功能的 USB 限流开关。TPS2585x-Q1 提供了一种紧凑型解决方案，可在宽输入电源电压范围内实现6.6A

的连续输出电流以及出色的负载和线路调节。该同步降压稳压器具有峰值电流模式控制，而且采用了内部补偿，

可简化设计。FREQ 引脚上有一个电阻器，可用于在 200kHz 和 3MHz 之间设置开关频率。在低于 400kHz 的频

率下运行可实现更高的系统效率，在高于 2.1MHz 的频率下运行则可以避开 AM 无线电频带，并且能够使用较小

的电感器。

TPS2585x-Q1 集成了标准USB Type-C 端口控制器功能，包括用于3A 和1.5A 电流广播的配置通道(CC) 逻辑。

电池充电（1.2 版）集成提供了利用 USB 数据线信号来确定 USB 端口拉电流能力的传统非 Type-C USB 设备所

需的电气特性。TPS2585x-Q1 还集成了VCONN 电源，可满足USB3.1 电源要求。由于系统集成度高且占用空间

小，该器件特别适用于双端口应用。

TPS2585x-Q1 支持智能热管理。USB 输出电压和 Type-C 电流广播可以根据温度感应通过TS 引脚进行调节。它

必须在 TS 引脚上连接一个 NTC 热敏电阻以监控环境温度或 PCB 板温度，具体取决于 NTC 热敏电阻在 USB 充

电模块或PCB 板中的放置位置。选择不同的NTC 热敏电阻和底部串联电阻可以改变切负荷的温度阈值。

TPS2585x-Q1 具有四种可选的 USB 输出电压设置：5.1V、5.17V、5.3V 和 5.4V。TPS2585x-Q1 集成了一个精

密电流检测放大器，用于实现电缆压降补偿和用户可编程电流限制调整。电缆补偿仅在输出电压设置为 5.17V 时

可用。在输出电流为 2.4A 时，电缆补偿电压为 90mV。电缆补偿可使降压稳压器输出电压随负载电流线性改变，

以抵消由于汽车电缆布线中的导线电阻引起的压降，从而帮助便携式设备在重载下实现更理想的电流和电压充

电。无论负载电流如何，在连接的便携式器件上测得的总线电压都保持大致恒定，这样，便携式器件的电池充电

器就能够保持理想工作状态。

TPS2585x-Q1 提供针对 USB 充电和系统运行的多种安全特性，包括外部负热敏电阻监控、逐周期电流限制、断

续短路保护、欠压锁定、总线过流、输出过流以及裸片过热保护。

该器件系列采用25 引脚3.5mm x 4.5mm QFN 封装。

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6 Device Comparison Table

DEVICE NUMBER

Type-C ports number

TPS25850-Q1

TPS25851-Q1

TPS25852-Q1

Dual

Support Type-C protocol

NTC Thermistor Input (TS)

USB load switch ON/OFF control

Fault event indication

Yes

No

Yes

No

Yes

Thermal warning indication

External clock synchronization

BC1.2 DCP

No

Yes

No

Apple or Samsung charging scheme

Cable compensation

Yes

No

Yes⁽¹⁾

Selectable output voltage

Adjustable output short current limit

FPWM/PFM

Yes

FPWM

DCDC always ON (EN pull High)

Spread spectrum

No

Yes

Package

QFN-25 3.5 mm × 4.5 mm

(1) VSET short to GND to set 5.17-V output voltage. Compensation voltage is 90 mV when either USB port A or USB port B output 2.4-A

current.

4

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7 Pin Configuration and Functions

PGND SW

IN

BOOT

21

VSET

1

24

23

22

TS

BIAS

EN/UV

2

20

3

FREQ/SYNC

PB_DP

19

18

PA_DP

4

5

PA_DM

PB_DM

PGND

17

16

25

11

6

7

AGND

PB_CC1

PB_CC2

PA_CC1

15

14

PA_CC2

8

10

12

9

13

ILIM

PB_BUS

OUT

PA_BUS SENSE

图7-1. TPS25850-Q1 RPQ Package 25-Pin (QFN) Top View

VSET

1

PGND SW

IN

BOOT

21

24

23

22

TS

BIAS

EN/UV

2

3

20

19

FREQ/SYNC

4

5

18 /PB_FAULT

17 /PB_POL

/PA_FAULT

/PA_POL

25

11

PGND

6

7

16

AGND

PB_CC1

PB_CC2

PA_CC1

15

14

PA_CC2

8

10

12

9

13

ILIM

PB_BUS

OUT

PA_BUS SENSE

图7-2. TPS25851-Q1 RPQ Package 25-Pin (QFN) Top View

PGND SW

IN

BOOT

21

VSET

1

24

23

22

TS

BIAS

EN/UV

2

3

20

19

FREQ/SYNC

4

5

18 /PB_FAULT

17 PB_EN

/PA_FAULT

PA_EN

25

11

PGND

6

7

16

AGND

PB_CC1

PB_CC2

PA_CC1

15

14

PA_CC2

8

10

12

9

13

ILIM

PB_BUS

OUT

PA_BUS SENSE

图7-3. TPS25852-Q1 RPQ Package 25-Pin (QFN) Top View

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表7-1. Pin Functions for TPS25850-Q1 RPQ Package

NAME

NO.

TYPE ⁽¹⁾

DESCRIPTION

Output Voltage Setting. Short to GND to set the 5.17-V output voltage. Float or pull up to

V_SENSEto set 5.1-V output voltage. Tie to GND through a 40.2-KΩ resistor to set 5.3-V

output voltage. Tie to GND through a 80.6-KΩ resistor to set 5.4-V output voltage.

VSET

1

A

TS

2

3

A

P

Temperature Sense terminal. Connect the TS input to the NTC thermistor.

Input of internal bias supply. Must connect to the SENSE pin directly. Power the internal

circuit.

BIAS

PA_DP

PA_DM

AGND

4

5

6

7

8

A

P

A

D+ data line. Connect to USB Port A connector.

D- data line. Connect to USB Port A connector.

Analog ground terminal. Connect AGND to PGND.

Connect to Type-C Port A CC1 pin. Analog input, output, or both.

Connect to Type-C Port A CC2 pin. Analog input, output, or both.

PA_CC1

PA_CC2

Current Limit program. Connect a resistor to set the current limit threshold. Short to GND

to set the default 3.55-A current limit.

ILIM

9

A

P

PA_BUS

SENSE

PB_BUS

OUT

10

11

12

13

Port A BUS output.

Output Voltage Sensing. External load on this pin is strictly prohibited. Connect to the

other side of the external inductor.

Port B BUS output.

Output pin. Provide 5.1-V voltage to power external load with max 200-mA capability. The

voltage follows the VSET setting.

PB_CC2

PB_CC1

14

15

A

Connect to Type-C Port B CC2 pin. Analog input, output, or both.

Connect to Type-C Port B CC1 pin. Analog input, output, or both.

Power Ground terminal. Connected to the source of LS FET internally. Connect to system

ground, AGND, and the ground side of the C_INand C_OUTcapacitors. The path to C_INmust

be as short as possible.

PGND

16,24,25

P

PB_DM

PB_DP

17

18

A

D–data line. Connect to USB port B connector.

D+ data line. Connect to USB port B connector.

Switching Frequency Program and External Clock Input. Connect a resistor from FREQ to

GND to set the switching frequency.

FREQ/ SYNC

EN/UV

BOOT

IN

19

20

21

22

23

A

P

Enable pin. Precision enable controls the regulator switching action and type-C. Do not

float. High = on, Low = off. Can be tied to SENSE directly. Precision enable input allows

adjustable UVLO by external resistor divider if tie to IN pin.

Bootstrap capacitor connection. Internally, the BOOT connects to the cathode of the

boost-strap diode. Connect the 0.1-μF bootstrap capacitor from SW to BOOT.

Input power. Connected to external DC supply. Expected range of bypass capacitors is 1

μF to 10 μF, connect from IN to PGND. Can withstand up to 36 V without damage but

operating is suspended if VIN is above the 26-V OVP threshold.

Switching output of the regulator. Internally connected to source of the HS FET and drain

of the LS FET. Connect to output inductor.

SW

(1) A = Analog, P = Power, G = Ground.

表7-2. Pin Functions for TPS25851-Q1 RPQ Package

NAME

NO.

TYPE ⁽¹⁾

DESCRIPTION

Output voltage setting. Short to GND to set the 5.17-V output voltage. Float or pull up to

V_SENSEto set 5.1-V output voltage. Tie to GND through a 40.2-KΩ resistor to set 5.3-V

output voltage. Tie to GND through a 80.6-KΩ resistor to set 5.4-V output voltage.

VSET

1

A

TS

2

3

A

P

Temperature Sense terminal. Connect the TS input to the NTC thermistor.

Input of internal bias supply. Must connect to the SENSE pin directly. Power the internal

circuit.

BIAS

USB Port A Fault indication. /PA_FAULT indicates overcurrent on PA_BUS or

overtemperature conditions. /PA_FAULT is an open drain in normal conditions. Pull /

PA_FAULT low during fault conditions.

PA_FAULT

4

A

6

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表7-2. Pin Functions for TPS25851-Q1 RPQ Package (continued)

NAME

NO.

TYPE ⁽¹⁾

DESCRIPTION

Polarity open-drain logic output. Signals which Type-C CC pin is connected to the CC line.

This gives the information needed to mux the super speed lines. Asserted when the Port A

CC2 pin is connected to the CC line in cable.

PA_POL

5

A

AGND

PA_CC1

PA_CC2

6

7

8

P

A

Analog ground terminal. Connect AGND to PGND.

Connect to Type-C Port A CC1 pin. Analog input, output, or both.

Connect to Type-C Port A CC2 pin. Analog input, output, or both.

Current Limit program. Connect a resistor to set the current limit threshold. Short to GND

to set the default 3.55-A current limit.

ILIM

9

A

P

PA_BUS

SENSE

PB_BUS

OUT

10

11

12

13

Port A BUS output.

Output Voltage Sensing. External load on this pin is strictly prohibited. Connect to the

other side of the external inductor.

Port B BUS output.

Output pin. Provide 5.1-V voltage to power external load with max 200-mA capability. The

voltage follows the VSET setting.

PB_CC2

PB_CC1

14

15

A

Connect to Type-C Port B CC2 pin. Analog input, output, or both.

Connect to Type-C Port B CC1 pin. Analog input, output, or both.

Power Ground terminal. Connected to the source of LS FET internally. Connect to system

ground, AGND, and the ground side of the C_INand C_OUTcapacitors. Path to C_INmust be

as short as possible.

PGND

16,24,25

17

P

A

Polarity open-drain logic output. Signals which Type-C CC pin is connected to the CC line.

This gives the information needed to mux the super speed lines. Asserted when the port B

CC2 pin is connected to the CC line in cable.

PB_POL

USB Port B Fault Indication. /PB_FAULT indicates overcurrent on PB_BUS or

overtemperature conditions. /PB_FAULT is an open drain in normal conditions. Pull /

PB_FAULT low during fault conditions.

PB_FAULT

FREQ/ SYNC

EN/UV

BOOT

18

19

20

21

22

23

A

P

Switching Frequency Program and External Clock Input. Connect a resistor from FREQ to

GND to set the switching frequency.

Enable pin. Precision enable controls the regulator switching action and type-C. Do not

float. High = on, Low = off. Can be tied to SENSE directly. Precision enable input allows

adjustable UVLO by external resistor divider if tie to IN pin.

Bootstrap capacitor connection. Internally, the BOOT is connected to the cathode of the

booststrap diode. Connect the 0.1-μF bootstrap capacitor from SW to BOOT.

Input power. Connected to external DC supply. Expected range of bypass capacitors is 1

μF to 10 μF, connect from IN to PGND. Withstand up to 36 V without damage but

operating is suspended if VIN is above the 26-V OVP threshold.

IN

Switching output of the regulator. Internally connected to source of the HS FET and drain

of the LS FET. Connect to output inductor.

SW

(1) A = Analog, P = Power, G = Ground.

表7-3. Pin Functions for TPS25852-Q1 RPQ Package

NAME

NO.

TYPE ⁽¹⁾

DESCRIPTION

Output Voltage Setting. Short to GND to set the 5.17-V output voltage. Float or pull up to

V_SENSEto set 5.1-V output voltage. Tie to GND through a 40.2-KΩ resistor to set 5.3-V

output voltage. Tie to GND through a 80.6-KΩ resistor to set 5.4-V output voltage.

VSET

1

A

TS

2

3

A

P

Temperature Sense terminal. Connect the TS input to the NTC thermistor.

Input of internal bias supply. Must connect to the SENSE pin directly. Power the internal

circuit.

BIAS

USB Port A Fault Indication. /PA_FAULT indicates overcurrent on PA_BUS or

overtemperature conditions. /PA_FAULT is an open drain in normal conditions. Pull /

PA_FAULT low during fault conditions.

PA_FAULT

4

A

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表7-3. Pin Functions for TPS25852-Q1 RPQ Package (continued)

NAME

NO.

TYPE ⁽¹⁾

DESCRIPTION

USB Port A Enable pin. To control the USB port A channel load switch ON/OFF. When

pull-low, the pin turns off the port A USB power and CC1/2 current and voltage. When pull-

high, the pin turns on the port A USB power and CC1/2 current and voltage. Can be tied to

SENSE directly to automatically turn on USB port.

PA_EN

5

A

AGND

PA_CC1

PA_CC2

6

7

8

P

A

Analog ground terminal. Connect AGND to PGND.

Connect to Type-C Port A CC1 pin. Analog input, output, or both.

Connect to Type-C Port A CC2 pin. Analog input, output, or both.

Current Limit program. Connect a resistor to set the current limit threshold. Short to GND

to set the default 3.55-A current limit.

ILIM

9

A

P

PA_BUS

SENSE

PB_BUS

OUT

10

11

12

13

Port A BUS output.

Output Voltage Sensing, external load on this pin is strictly prohibited. Connect to the other

side of the external inductor.

Port B BUS output,

Output pin. Provide 5.1-V voltage to power external load with max 200-mA capability. The

voltage follows the VSET setting.

PB_CC2

PB_CC1

14

15

A

Connect to Type-C Port B CC2 pin. Analog input, output, or both.

Connect to Type-C Port B CC1 pin. Analog input, output, or both.

Power Ground Terminal. Connected to the source of LS FET internally. Connect to system

ground, AGND, and the ground side of C_INand C_OUTcapacitors. Path to C_INmust be as

short as possible.

PGND

16,24,25

17

P

A

USB Port B Enable pin. To control the USB port B channel load switch ON/OFF. When

pull-low, the pin turns off the port B USB power and CC1/2 current and voltage. When pull-

high, the pin turns on the port B USB power and CC1/2 current and voltage. Can be tied to

SENSE directly to automatically turn on USB port.

PB_EN

USB Port B Fault Indication. /PB_FAULT indicates overcurrent on PB_BUS or

overtemperature conditions. /PB_FAULT is an open drain in normal conditions. Pull /

PB_FAULT low during fault conditions.

PB_FAULT

FREQ/ SYNC

EN/UV

BOOT

18

19

20

21

22

23

A

P

Switching Frequency Program and External Clock Input. Connect a resistor from FREQ to

GND to set the switching frequency.

Enable pin. Precision enable controls the regulator switching action and type-C. Do not

float. High = on, Low = off. Can be tied to SENSE directly. Precision enable input allows

adjustable UVLO by external resistor divider if tie to IN pin.

Bootstrap capacitor connection. Internally, the BOOT is connected to the cathode of the

booststrap diode. Connect the 0.1-μF bootstrap capacitor from SW to BOOT.

Input power. Connected to external DC supply. Expected range of bypass capacitors is 1

μF to 10 μF. Connect from IN to PGND. Withstand up to 36 V without damage but

operating is suspended if VIN is above the 26-V OVP threshold.

IN

Switching output of the regulator. Internally connected to source of the HS FET and drain

of the LS FET. Connect to output inductor.

SW

(1) A = Analog, P = Power, G = Ground.

8

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8 Specifications

8.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of -40°C to +150°C and AGND = PGND (unless otherwise

noted)⁽¹⁾

PARAMETER

IN to PGND

MIN

–0.3

-0.3

MAX

40⁽²⁾

35

6

UNIT

IN to SW

BIAS, SENSE to PGND

EN to AGND

11

6

Input voltage

V

FREQ/SYNC to AGND

PA_EN, PB_EN to AGND

VSET, ILIM to AGND

AGND to PGND

6

0.3

35

6

–0.3

–3.5

–0.3

SW to PGND

SW to PGND (less than 10 ns transients)

BOOT to SW

Output voltage

Voltage range

V

PA_BUS, PB_BUS, OUT to PGND

CC1, CC2 to AGND

DP, DM to AGND

6

PA_POL , PB_POL to AGND

PA_FAULT, PB_FAULT to AGND

TS to AGND

6

Pin positive sink current, I_SNKCC1, CC2 (while applying VCONN)

1

A

I/O current

DP to DM in BC1.2 DCP Mode

Junction temperature

35

150

mA

°C

–35

-40

T_J

T_stg

Storage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) VIN rising slew rate below 20V/ms if in 0-V to 40-V transient, room temperature, maximum 500-uF cap at SENSE.

8.2 ESD Ratings

VALUE

±2000⁽²⁾

±750⁽³⁾

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

V_(ESD)Electrostatic discharge

Corner pins

V

Charged device model (CDM), per

AEC Q100-011

Other pins

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) The passing level per AEC-Q100 Classification H2.

(3) The passing level per AEC-Q100 Classification C5

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8.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of -40°C to 150°C. Voltages are with respect to GND (unless

otherwise noted)

MIN

NOM

MAX UNIT

IN to PGND

5.5

26

EN

0

VSENSE

V_I

Input voltage

TS

0

VSENSE

3.3

PA_EN, PB_EN

0

V

FREQ/SYNC when driven by external clock

PA_FAULT, PB_FAULT, PA_POL, PB_POL

PA_BUS, PB_BUS, OUT

0

V_PU

V_O

Pull up voltage

Output voltage

0

5

VSENSE

5.5

PA_BUS, PB_BUS

0

3

A

OUT

0

0.2

I_O

Output current

DP to DM Continuous current in BC1.2 DCP Mode

15

–15

CC1 or CC2 source current when supplying

VCONN

mA

I_SRC

I_SNK

Source current

Sink current

250

PA_FAULT, PB_FAULT, PA_POL, PB_POL

10

100

R_VSET

0

kΩ

uF

R_ILIM

R_EXT

External resistnace

External capacitance

R_FREQ

R_IMON

C_EXT

T_J

C_BOOT

0.1

Operating junction temperature

150

°C

–40

10

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8.4 Thermal Information

TPS2585x-Q1

THERMAL METRIC^{(1) (2)}

RPQ (VQFN)

25 PINS

37.7

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

17.2

8.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

Ψ_JT

8.8

Ψ_JB

R_θJC(bot)

20.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Power rating at a specific ambient temperature T_Ashould be determined with a maximum junction temperature of 150 °C.

8.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of -40°C to +150°C; V_IN= 13.5 V, f_SW

=2.1MHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY VOLTAGE (IN PIN)

Shutdown quiescent current;

measured at IN pin.

I_SD

I_Q

34

63

200

uA

µA

VEN/UV = 0, -40C ≤T_J≤85C

Operating quiescent current (DCDC

disable)

V_EN=V_SENSE, CCx=open, -40C ≤T_J

≤85C

Voltage on VIN pin when buck

regulator stops switching

V_{OVLO_R}

26.6

1.26

27.5

0.5

28.4

V

V_{OVLO_HYS}

Hysteresis

ENABLE AND UVLO (EN/UVLO PIN)

Rising threshold for not in External

UVLO

V_{EN/UVLO_R}

V_EN/UVrising threshold

V_EN/UVLOfalling

1.3

1.34

1.98

V

V_{EN/UVLO_HYS}

Hysteresis

100

mV

PA_EN, PB_EN input level required to

turn on PA_BUS and PB_BUS Load

Switch (TPS25852-Q1)

V_{PA/B_EN_H}

V_{PA_EN}or V_{PB_EN}rising threshold

1.6

V

PA_EN, PB_EN input level required to

turn off PA_BUS and PB_BUS Load

Switch (TPS25852-Q1)

V_{PA/B_EN_L}

V_{PA_EN}or V_{PB_EN}falling threshold

0.97

1.5

V

V_{EN1/2_HYS}

BOOTSTRAP

V_{BTST_UVLO}

R_BOOT

Hysteresis(TPS25852-Q1)

100

mV

Bootstrap voltage UVLO threshold

Bootstrap pull-up resistence

2.2

7.7

V

VSENSE-BOOT=0.1V

Ω

BUCK REGULATOR

I_L-SC-HS

I_L-SC-LS

I_L-NEG-LS

I_ZC

High-side current limit

BOOT-SW=5V

SENSE=5V

10.2

8.5

-7

11.4

10

12.6

11.5

-3

A

Low-side current limit

Low-side negative current limit

Zero current detector threshold

-5

0.01

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8.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of -40°C to +150°C; V_IN= 13.5 V, f_SW

=2.1MHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CC1 or CC2 pulldown resistance = R_d,

VSET float or pull up to V_SENSE

,

-1%

5.1

+1%

V

T_J=25℃

CC1 or CC2 pulldown resistance = R_d,

VSET short to AGND, T_J=25℃

-1%

5.17

5.3

+1%

2

V

V_SENSE

BUCK Output voltage

CC1 or CC2 pulldown resistance = R_d,

R_VSET=40.2KΩ, T_J=25℃

CC1 or CC2 pulldown resistance = R_d,

R_VSET=80.6KΩ, T_J=25℃

5.4

V

CC1 or CC2 pulldown resistance = R_d,

-40℃≤T_J≤150℃

V_SENSE

BUCK Output voltage accuracy

%

–2

SENSE input level to enable DCDC

switching

V_SENSErising, CC1 or CC2 pull down

resistance = R_d

V_{DCDC_UVLO_R}

V_{DCDC_UVLO_HYS}

V_DROP

3.85

4

0.4

300

18

4.15

V

V_SENSEfalling, CC1 or CC2 pull down

resistance = R_d

Hysteresis

V

V_IN= V_SENSE+ V_DROP,V_SENS= 5.1V,

I_{PA_BUS}=3A, I_{PB_BUS}=3A

Dropout voltage ( V_IN-V_SENSE

)

mV

mΩ

I_{PA_BUS}=3A, I_{PB_BUS}=3A, BOOT-

SW=5V, -40℃≤T_J≤150℃

R_DS-ON-HS

R_DS-ON-LS

High-side MOSFET ON-resistance

Low-side MOSFET ON-resistance

34

I_{PA_BUS}=3A, I_{PB_BUS}=3A, V_SENSE=5V,

-40℃≤T_J≤150℃

9.5

18.5

POWER SWITCH AND CURRENT LIMIT

USB Load Switch MOSFET ON-

I_{PA_BUS}=3A, I_{PB_BUS}=3A;

-40℃≤T_J≤150℃

R_{DS-ON_USB}

6.8

11.73

mΩ

resistance

OUT Load Switch MOSFET ON-

resistance

R_{DS-ON_OUT}

I_OUT= 0.3 A

230

R_{DS-ON_VCONN}

On-state resistance

T_J= 25°C, I_CCn= 0.25 A

410

550

740

mΩ

–40°C ≤T_J≤150°C, I_CCn= 0.25 A

Voltage on SENSE pin that will enable

the USB Load Switch

V_{USBLS_UVLO_R}

3.95

4.1

200

500

4.25

V

V_{USBLS_UVLO_HYS}Hysteresis

mV

Ω

Discharge resistance for Port A or Port Apply 5V on PA_BUS or PB_BUS,

B BUS

R_{BUS_DCHG}

250

670

750

730

CC1 or CC2= Rd

Rising threshold voltage for BUS not

discharged

V_{TH_R_BUS_DCHGb}

700

100

150

mV

KΩ

V_{TH_HYS_BUS_DCHG}Hysteresis

V_{Px_BUS}=4V, No sink termination on

CC lines, Time>t_{W_BUS_DCHG}

V_{BUS_DCHG_BLEED}BUS bleed resistance

100

200

849

2434

3018

3748

4040

4876

4828

4265

1061

2704

3354

4165

4490

5418

5680

4490

1273

2974

3689

4581

4938

5960

6532

4714

mA

R_ILIM=48.7KΩ

R_ILIM=19.1KΩ

R_ILIM=15.4KΩ

R_ILIM=12.4KΩ

BUS output short-circuit secondary

current limit

I_{OS_HI}

R_ILIM=11.5KΩ

R_ILIM=9.53KΩ

R_ILIM=0Ω(short to GND)

R_ILIM=11.5KΩ, T_J=25℃

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8.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of -40°C to +150°C; V_IN= 13.5 V, f_SW

=2.1MHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

530.4

1521

TYP

MAX UNIT

663

800

mA

R_ILIM=48.7KΩ

1690

1859

R_ILIM=19.1KΩ

1886.4

2342.7

2525.4

3047.4

3017.5

2666

2096 2305.6

2603 2863.3

2806 3086.6

3386 3724.6

3550 4082.5

R_ILIM=15.4KΩ

R_ILIM=12.4KΩ

I_{OS_BUS}

BUS output short-circuit current limit

OUT output short-circuit current limit

R_ILIM=11.5KΩ

RILIM=9.53KΩ

R_ILIM=0Ω(short to GND)

R_ILIM=11.5KΩ, T_J=25℃

Short circuit current limit

2806

450

2946

495

I_{OS_OUT}

390

VCONN output short-circuit current

limit

I_{OS_VCONN}

Short circuit current limit

240

70

300

360

mA

CABLE COMPENSATION VOLTAGE

Cable compensation

V_{DROP_COM}

I_{PA_BUS}or I_{PB_BUS}=2.4A,

VSET=GND(set 5.17V output)

90

110

mV

voltage(TPS25850/1/2)

CC CONNECT MANAGEMENT

I_{SRC_CC_3A}

Sourcing current

304

167

330

180

356

194

µA

CC pin voltage: 0 V ≤V_CCn≤2.45 V

Sourcing current in thermal

management(Temp warm)

CC pin voltage: 0 V ≤V_CCn≤1.5 V ,

T_A> 85℃

I_{SRC_CC_1.5A}

Sourcing current in thermal

management(Temp hot)

CC pin voltage: 0 V ≤V_CCn≤1.5 V ,

T_A> 85℃

I_{SRC_CC_DFLT}

64

80

105

10

µA

CCx is the CC pin under test, CCy is

the other CC pin. CC pin voltage

VCCx = 5.5 V, CCy floating, V_{EN_UV}

0 V or V_SENSE, 0 V ≤V_IN≤26 V

I_REVis current into CCx pin

=

I_REV

Reverse leakage current

2.75

Rising threshold voltage for VCONN

not discharged

CC pin that was providing VCONN in

previous SINK state

V_{TH_R}

670

700

100

730

mV

V_{TH_HYS}

Hysteresis

FAULT, POL(TPS25851/2-Q1)

PA_FAULT, PB_FAULT Output low

voltage (TPS25851/2-Q1)

V_OL

I_OFF

V_OL

I_OFF

I_{SNK_PIN}= 1 mA

V_PIN= 5.5 V

250

2.2

250

1.8

mV

µA

PA_FAULT, PB_FAULT Off-state

leakage (TPS25851/2-Q1)

PA_POL, PB_POL Output low voltage

(TPS25851-Q1)

I_{SNK_PIN}= 1 mA

V_PIN= 5.5 V

mV

µA

PA_POL, PB_POL Off-state

leakage (TPS25851-Q1)

BC 1.2 DOWNSTREAM CHARGING PORT (TPS25850-Q1)

R_{DPM_SHORT}DP and DM shorting resistance

DIVIDER 3 MODE (TPS25850-Q1)

70

200

Ω

V_{DP_DIV3}

V_{DM_DIV3}

R_{DP_DIV3}

R_{DM_DIV3}

DP output voltage

2.57

24

2.7

30

2.84

36

V

DM output voltage

DP output impedance

DM output impedance

I_{DP_IN}= –5 µA

I_{DM_IN}= –5 µA

kΩ

24

30

36

1.2-V MODE (TPS25850-Q1)

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8.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of -40°C to +150°C; V_IN= 13.5 V, f_SW

=2.1MHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

1.12

84

TYP

MAX UNIT

V_{DP_1.2V}

V_{DM_1.2V}

R_{DP_1.2V}

R_{DM_1.2V}

DP output voltage

DM output voltage

DP output impedance

DM output impedance

1.2

1.26

126

V

1.2

100

I_{DP_IN}= –5 µA

kΩ

84

I_{DM_IN}= –5 µA

FREQ/SYNC THRESHOLD

FREQ/SYNC high threshold for

Amplitude of SYNC clock AC signal

(measured at FREQ/SYNC pin)

V_{IH_FREQ/SYNC}

2

V

external clock synchronization

FREQ/SYNC low threshold for

external clock synchronization

Amplitude of SYNC clock AC signal

(measured at FREQ/SYNC pin)

V_{IL_FREQ/SYNC}

0.8

0.525

0.683

TEMPERATURE SENSING

V_{WARN_HIGH}Temperature warning threshold rising As percentage to V_SENSE

V_{WARN_HYS}

0.475

0.618

0.5

0.1

V/V

Hysteresis

As percentage to V_SENSE

Temperature Hot assert threshold

rising to reduce SENS voltage

V_{HOT_HIGH}

V_{HOT_HYS}

V_{R_VSENS}

As percentage to V_SENSE

0.65

0.1

V/V

V

Hysteresis

As percentage to V_SENSE

V_SENSEvoltage decay when

Temperature Hot assert

TS pin voltage rise above 0.65*V_SENSE

4.77

THERMAL SHUTDOWN

T_{LS_SD}USB Load Switch Over Temperature

Shutdown threshold

Recovery threshold

Shutdown threshold

Recovery threshold

160

150

166

154

°C

T_SD

Thermal shutdown

8.6 Timing Requirements

Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)

MIN NOM MAX UNIT

POL(TPS25851-Q1)

t_{DEGLA_POL}Asserting deglitch time

t_{DEGLD_POL}De-asserting deglitch time

100

8.2

150

200 ms

18 ms

12.5

FAULT (TPS25851/2-Q1)

(Thermal SD Fault assertion is

instantaneous, not subject to this timing)

t_{DEGLA_FAULT}Asserting deglitch time

2.94

4.1 5.42 ms

t_{DEGLD_FAULT}De-asserting deglitch time

11.09 16.38 23.03 ms

BUS DISCHARGE

t_{DEGA_BUS_DC}

Discharge asserting deglitch

5.6

12.3 21.2 ms

260 360 ms

HG

V_BUSdischarge time after sink termination

removed from CC lines

V_BUS= 1 V, time I_{SNK_OUT}> 1 mA after sink

termination removed from CC lines

t_{W_BUS_DCHG}

170

POWER SWITCH TIMING

Deglitch time for USB power switch current

limit enable

t_{IOS_HI_DEG}

t_{IOS_HI_RST}

t_{r_USB}

USB port enter overcurrent (per ILIM setting) 1.228 2.048 2.867 ms

9.6 16 22.4 ms

1.67 ms

MFI OCP reset timing

C_L= 1 µF, R_L= 100 Ω(measured from 10%

to 90% of final value)

PA_BUS, PB_BUS, BUS voltage rise time

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8.6 Timing Requirements (continued)

Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)

MIN NOM MAX UNIT

C_L= 1 µF, R_L= 100 Ω(measured from 90%

to 10% of final value)

t_{f_USB}

PA_BUS, PB_BUS, BUS voltage fall time

0.49

ms

t_{on_USB}

t_{off_USB}

PA_BUS, PB_BUS, BUS voltage turnon-time

PA_BUS, PB_BUS, BUS voltage turnoff-time

2.59

2.07

ms

C_L= 1 µF, R_L= 100 Ω

PA_BUS, PB_BUS, BUS short-circuit

response time

t_{IOS_USB}

t_{r_OUT}

1

us

C_L= 1 µF, R_L= 1 Ω

C_L= 1 µF, R_L= 100 Ω(measured from 10%

to 90% of final value)

OUT voltage rise time

OUT voltage fall time

0.12

0.16

0.2 0.28 ms

0.22 0.28 ms

C_L= 1 µF, R_L= 100 Ω(measured from 90%

to 10% of final value)

t_{f_OUT}

t_{on_OUT}

OUT voltage turnon-time

0.6

1.1 1.65 ms

0.54 0.62 ms

C_L= 1 µF, R_L= 100 Ω

C_L= 1 µF, R_L= 1 Ω

t_{off_OUT}

OUT voltage turnoff-time

0.45

t_{IOS_OUT}

t_{IOS_VCONN}

OUT short-circuit response time

CC-VCONN short circuit response time

1.4

1

4

us

3.5 µs

C_L= 1 µF, R_L= 100 Ω(measured from 10%

to 90% of final value); 5.1KΩ on CC1 and

1KΩ on CC2

t_{r_VCONN}

VCONN output voltage rise time

VCONN output voltage fall time

0.2

0.28 0.36 ms

0.23 0.28 ms

C_L= 1 µF, R_L= 100 Ω(measured from 90%

to 10% of final value); 5.1KΩ on CC1 and

1KΩ on CC2

t_{f_VCONN}

0.18

C_L= 1 µF, R_L= 100 Ω; 5.1KΩ on CC1 and

1KΩ on CC2

t_{on_VCONN}

VCONN output voltage turnon time

VCONN output voltage turnoff time

0.7

1.2

1.7 ms

C_L= 1 µF, R_L= 100 Ω; 5.1KΩ on CC1 and

1KΩ on CC2

t_{off_VCONN}

0.37

0.44 0.51 ms

HICCUP MODE

T_{HICP_ON}

OUT, PA_BUS, PB_BUS output hiccup mode

ON time

OC, V_OUT, V_{PA_BUS}, V_{PB_BUS}drop 10%

2.94

367

4.1 5.42 ms

OUT, PA_BUS, PB_BUS output hiccup mode OC, OUT, PA_BUS, PB_BUS connect to

OFF time GND

T_{HICP_OFF}

524

715 ms

8.7 Switching Characteristics

Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SW (SW PIN)

T_{ON_MIN}

Minimum turnon-time

84

6

ns

µs

Maximum turnon-time, HS timeout in

dropout

T_{ON_MAX}

T_{OFF_MIN}

D_max

Minimum turnoff time

81

98

ns

%

Maximum switch duty cycle

TIMING RESISTOR AND INTERNAL CLOCK

Switching frequency range using

FREQ mode

f_{SW_RANGE}

200

3000

kHz

9 kΩ≤R_FREQ≤99 kΩ

228

360

253

400

278

440

kHz

R_FREQ= 80.6 kΩ

R_FREQ= 49.9 kΩ

R_FREQ= 8.45 kΩ

f_SW

Switching frequency

1980

2200

2420

Frequency span of spread spectrum

operation

FS_SS

±6

%

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MAX UNIT

8.7 Switching Characteristics (continued)

Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

EXTERNAL CLOCK(SYNC)

Switching frequency using external

clock on FREQ/SYNC pin

f_FREQ/SYNC

200

3000

kHz

ns

f_SYNC= 400kHz, V_FREQ/SYNC

V_{IH_FREQ/SYNC}, V_FREQ/SYNC< V_{IL_FREQ/}

>

T_{SYNC_MIN}

Minimum SYNC input pulse width

PLL lock time

100

SYNC

T_{LOCK_IN}

100

µs

Attach asserting deglitch in the

Detached Mode

t_{DEGA_CC_ATT_DETM}

1.29

8.2

2.05

3.05

18

ms

t_{DEGA_CC_DETACH_S}Detach asserting deglitch for exiting

12.5

ms

SINK Mode

INKM

t_{DEGA_CC_SHORT}

t_{DEGA_CC_LONG}

Detach, Rd and Ra asserting deglitch

Long deglitch

92

192

148

339

200

µs

103

ms

16

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8.8 Typical Characteristics

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2.1 MHz, L = 0.68 µH, C_SENSE= 66 µF, C_{PA_BUS}

= 1 µF, C_{PB_BUS}= 1 µF, T_A= 25 °C.

70

60

50

40

30

20

200

180

160

140

120

100

-40C

25C

150C

-40C

25C

150C

4

8

12

16 20

Input Voltage (V)

24

28

32

4

8

12

16 20

Input Voltage (V)

24

28

32

V_EN/EULVO= 0 V

PA_CC1 = R_d

PB_CC1 = R_d

V_EN/UVLO= V_SENSEPA_CC1/2 = OPEN PB_CC1/2 = OPEN

图8-1. Shutdown Quiescent Current

图8-2. Standby Quiescent Current

1.68

1.36

1.34

1.32

1.3

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

1.67

1.66

1.65

1.64

1.63

1.62

1.61

1.6

1.59

1.58

1.57

1.28

1.26

-40 -20

0

20

40

Temperature (C)

60

80 100 120 140 160

-50

-25

0

25

50

75

Temperature (C)

100

125

150

图8-4. Precision USB PA/PB Enable Threshold

图8-3. Precision Device Enable Threshold

5.2

5.46

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

5.19

5.18

5.17

5.16

5.15

5.14

5.44

5.42

5.4

5.38

5.36

5.34

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

VSET = GND

R_VSET= 80.6 kΩ

图8-5. V_SENSEVoltage vs Junction Temperature

图8-6. V_SENSEVoltage vs Junction Temperature

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8.8 Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2.1 MHz, L = 0.68 µH, C_SENSE= 66 µF, C_{PA_BUS}

= 1 µF, C_{PB_BUS}= 1 µF, T_A= 25 °C.

3.94

3.96

3.98

4

11.7

11.6

11.5

11.4

11.3

11.2

Vin = 5.5V

Vin = 13.5V

Vin = 26V

-40C

25C

150C

4.02

4.04

4.06

-50

-25

0

25

Temperature (C)

50

75

100

125

150

4

8

12

16

Input Voltage (V)

20

24

28

图8-8. High-side Current Limit vs Input Voltage

V_EN/EULVO= V_SENSE

PA_CC1= R_d

PB_CC1= R_d

图8-7. DCDC UVLO Threshold

10.3

10.2

10.1

10

40

-40C

25C

150C

Vin = 5.5V

Vin = 13.5V

Vin = 26V

35

30

25

20

15

9.9

9.8

4

8

12

16

Input Voltage (V)

20

24

28

-50

-25

0

25

50

75

Temperature (C)

100

125

150

图8-9. Low-side Current Limit vs Input Voltage

I_{PA_BUS}= 3 A

I_{PB_BUS}= 3 A

图8-10. High-side MOSFET on Resistance vs Junction

Temperature

18

16

14

12

3640

Vin = 5.5V

Vin = 13.5V

Vin = 26V

3600

3560

3520

3480

3440

3400

10

Vin = 5.5V

Vin = 13.5V

Vin = 26V

8

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

I_{PA_BUS}= 3 A

I_{PB_BUS}= 3 A

ILIM = GND

图8-11. Low-side MOSFET on Resistance vs Junction

图8-12. USB Power Switch Current Limit vs Junction

Temperature

18

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8.8 Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2.1 MHz, L = 0.68 µH, C_SENSE= 66 µF, C_{PA_BUS}

= 1 µF, C_{PB_BUS}= 1 µF, T_A= 25 °C.

3520

3480

3440

3400

3360

3320

3280

2200

2160

2120

2080

2040

2000

1960

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

R_ILIM= 9.53 kΩ

R_ILIM= 15.4 kΩ

图8-13. USB Power Switch Current Limit vs Junction

图8-14. USB Power Switch Current Limit vs Junction

Temperature

520

328

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

500

480

460

440

420

400

320

312

304

296

288

280

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

图8-15. OUT Power Switch Current Limit vs Junction

图8-16. V_CONNPower Switch Current Limit vs Junction

Temperature

100

96

92

88

84

80

9.6

8.8

8

7.2

6.4

Vin = 5.5V

Vin = 13.5V

Vin = 26V

5.6

4.8

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

图8-18. USB Power Switch On Resistance vs Junction

I_{PA/B_BUS}= 2.4 A

VSET = GND

Temperature

图8-17. Cable Compensation Voltage vs Junction Temperature

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8.8 Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2.1 MHz, L = 0.68 µH, C_SENSE= 66 µF, C_{PA_BUS}

= 1 µF, C_{PB_BUS}= 1 µF, T_A= 25 °C.

400

360

320

280

240

200

160

600

550

500

450

400

350

300

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

图8-19. OUT Power Switch On Resistance vs Junction

图8-20. V_CONNPower Switch On Resistance vs Junction

Temperature

424

2280

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

416

408

400

392

384

376

2240

2200

2160

2120

2080

2040

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

R_FREQ= 49.9 kΩ

R_FREQ= 8.45 kΩ

图8-21. Switching Frequency vs Junction Temperature

图8-22. Switching Frequency vs Junction Temperature

450

0.56

UFP 1.5A

UFP 3A

400

0.54

0.52

0.5

350

300

250

200

150

0.48

0.46

0.44

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

图8-23. CC Sourcing Current vs Junction Temperature

图8-24. TS Temperature Wam Threshold vs Junction

Temperature

20

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8.8 Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2.1 MHz, L = 0.68 µH, C_SENSE= 66 µF, C_{PA_BUS}

= 1 µF, C_{PB_BUS}= 1 µF, T_A= 25 °C.

0.72

4.82

0.7

4.8

0.68

0.66

0.64

0.62

0.6

4.78

4.76

4.74

4.72

4.7

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

图8-25. TS Temperature Hot Threshold vs Junction

图8-26. SENSE Voltage in Temperature Hot vs Junction

Temperature

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9 Parameter Measurement Information

OUT

90%

R_(L)

t_r

C_(L)

t_f

V_(OUT)

10%

图9-1. OUT Rise-Fall Test Load Figure

图9-2. Power-On and Power-Off Timing

V_(EN)

50%

5 V

t_on

t_off

t_(DCHG)

V_(OUT)

90%

V_(OUT)

0 V

10%

图9-3. OUT Discharge During Mode Change

图9-4. Enable Timing, Active-High Enable

I_OS

I_(OUT)

t_(IOS)

图9-5. Output Short-Circuit Parameters

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10 Detailed Description

10.1 Overview

The TPS2585x-Q1 is a full-featured solution for implementing a compact USB charging port with support for both

Type-C and BC1.2 standards. The device contain an efficient buck regulator power source. For dual Type-C

ports, the TPS2585x-Q1 is capable of providing up to 6.6 A of output current at 5.17 V (nominal), 3 A for each

Type-C port, 200 mA for the OUT pin, and 200 mA for each VCONN power. The TPS2585x-Q1 is an automotive-

focused USB charging controller and offers a robust solution, so TI recommends to add adequate protection

(TVS3300 equivalent or better but auto qualified) on the IN pin to protect systems from high-power transients or

lightning strikes.

System designers can optimize efficiency or solution size through careful selection of switching frequency in the

range of 200 KHz–2400 KHz with sufficient margin to operate above or below the AM radio frequency band. For

switching frequency higher than 2400 KHz, the power dissipation significantly increases, so in a high ambient

temperature application, the 6.6-A output current capability is not ensured. The TPS2585x-Q1 buck regulator

operates in forced PWM mode, ensuring fixed switching frequency regardless of load current. Spread-spectrum

frequency dithering reduces harmonic peaks of the switching frequency, potentially simplifying EMI filter design

and easing compliance.

Current sensing through a precision FET current sense amplifier on the USB port enables an accurate, user-

programmable overcurrent limit setting, and linear cable compensation to overcome IR losses when powering

remote USB ports.

The TPS2585x-Q1 includes a TS input for user-programmable thermal protection using a negative temperature

coefficient (NTC) resistor.

The device can support the USB Type-C protocol. The TPS25850-Q1 also supports the legacy Battery Charging

Specification Rev 1.2 (BC1.2) DCP mode with an auto-detect feature to charge not only BC1.2-compliant

handheld devices, but also popular phones and tablets that incorporate their own propriety charging algorithm.

The TPS25851-Q1 supports USB cable polarity detection and fault condition detect for each port. The

TPS25852-Q1 can enable each port individually and can report fault condition for each port.

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10.2 Functional Block Diagram

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10.3 Feature Description

10.3.1 Power-Down or Undervoltage Lockout

The device is in low power mode if the IN terminal voltage is less than VUVLO, so the part is considered dead

and all the terminals are high impedance. Once the IN voltage rises above the VUVLO threshold, the IC enters

sleep mode or active mode, depending on the EN/UVLO voltage.

The voltage on the EN/UVLO pin controls the ON/OFF operation of the TPS2585x-Q1. An EN/UVLO pin voltage

higher than V_EN/UVLO-His required to start the internal regulator and begin monitoring the CCn lines for a valid

Type-C connection. The internal USB monitoring circuitry is on when V_INis within the operation range and the

EN/UVLO threshold is cleared. For TPS25850-Q1, the buck regulator and the USB ports load switch remains

OFF until a valid Type-C detection has been made. For TPS25851-Q1 and TPS25852-Q1, the buck regulator

starts to operate, however, the USB ports load switch remains OFF until a valid Type-C detection has been

made. This feature ensures the cold socket (0 V) USB Type-C V_BUSrequirement is met.

The EN/UVLO pin is an input and cannot be left open or floating. The simplest way to enable the operation of the

TPS2585x-Q1 is to connect EN to SENSE. This connection allows self-startup of the TPS2585x-Q1 when V_INis

within the operation range. Note that you cannot connect the EN to IN pin directly for self-startup.

Many applications benefit from the employment of enable dividers R_ENTand R_ENBto establish a precision

system UVLO level for the TPS2585x-Q1 shown in 图 10-1. The system UVLO can be used for sequencing,

ensuring reliable operation, or supply protection, such as a battery discharge level. To ensure the USB port V_BUS

is within the 5-V operating range as required for USB compliance (for the latest USB specifications and

requirements, refer to USB.org), TI suggests that the R_ENTand R_ENBresistors be chosen such that the

TPS2585x-Q1 enables when V_INis approximately 6 V. Considering the dropout voltage of the buck regulator and

IR losses in the system, 6 V provides adequate margin to maintain V_BUSwithin USB specifications. If system

requirements, such as a warm crank (start) automotive scenario, require operation with V_IN< 6 V, the values of

R_ENTand R_ENBcan be calculated assuming a lower V_IN. An external logic signal can also be used to drive the

EN/UVLO input when a microcontroller is present and it is desirable to enable or disable the USB port remotely

for other reasons.

IN

RENT

EN

RENB

图10-1. System UVLO by Enable Divider

UVLO configuration using external resistors is governed by the following equations:

V_{IN ON}

≈

’

÷

◊

(

)

R_ENT

=

- 1 ì R

∆

÷

ENB

∆

V_{EN/UVLO _H}

«

(1)

(2)

≈

’

V_{EN/UVLO _HYS}

V_{IN OFF}= V_{IN ON}ì 1 -

∆

÷

(

)

(

)

∆

V_{EN/UVLO _H}

«

◊

For example:

V_IN(ON)= 6 V

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R_ENT= 20 kΩ

R_ENB= [(V_EN-VOUT-H) / (V_IN(ON)–V_EN)] × R_ENT

(3)

R_ENB= 5 kΩ

Therefore, V_IN(OFF)= 5.5 V

10.3.2 Input Overvoltage Protection (OVP) - Continuously Monitored

The operation voltage range of the TPS2585x-Q1 is up to 26 V. If the input source applies an overvoltage, the

buck regulator HSFET/LSFET turns off immediately. Thus, the USB ports and OUT pin loses their power as well.

Once the overvoltage returns to a normal voltage, the buck regulator continues switching and provides power on

the USB ports and OUT pin.

During the overvoltage condition, the internal regulator regulates the SENSE voltage at 5 V, so the SENSE

always has power for the internal bias circuit and external NTC pullup reference.

10.3.3 Buck Converter

The following operating description of the TPS2585x-Q1 refers to the Functional Block Diagram. The TPS2585x-

Q1 integrates a monolithic, synchronous, rectified, step-down, switch-mode converter with internal power

MOSFETs and USB current-limit switches with charging ports auto-detection. The TPS2585x-Q1 offers a

compact solution that achieves up to 6.6 A of continuous output current with excellent load and line regulation

over a wide input supply range. The TPS2585x-Q1 supplies a regulated output voltage by turning on the high-

side (HS) and low-side (LS) NMOS switches with controlled duty cycle. During high-side switch ON time, the SW

pin voltage swings up to approximately V_IN. The inductor current i_Lincreases with linear slope (V_IN– V_OUT) / L.

When the HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through dead

time. Inductor current discharges through the LS switch with a slope of –V_OUT/ L. The control parameter of a

buck converter is defined as Duty Cycle D = t_ON/ T_SW, where t_ONis the high-side switch ON time and T_SWis the

switching period, shown in 图 10-2. The regulator control loop maintains a constant output voltage by adjusting

the duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage

and inversely proportional to the input voltage: D = V_OUT/ V_IN.

V_SW

D = t_ON/ T_SW

V_IN

t_ON

t_OFF

t

0

-V_D

T_SW

i_L

I_LPK

I_OUT

Di_L

t

0

图10-2. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The TPS2585x-Q1 operates in a fixed-frequency, peak-current-mode control to regulate the output voltage. A

voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak current command

based on voltage offset. The peak inductor current is sensed from the high-side switch and compared to the

peak current threshold to control the ON time of the high-side switch. The voltage feedback loop is internally

compensated, which allows for fewer external components, making it easy to design, and provides stable

operation with a reasonable combination of output capacitors. The TPS2585x-Q1 operates in FPWM mode for

low output voltage ripple, tight output voltage regulation, and constant switching frequency.

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10.3.4 FREQ/SYNC

The switching frequency of the TPS2585x-Q1 can be programmed by the resistor R_FREQfrom the FREQ/SYNC

pin and AGND pin. To determine the FREQ resistance, for a given switching frequency, use 方程式4:

-1.0483

R_FREQkW = 26660ì ƒ

kHz

(

)

(

)

SW

(4)

70

65

60

55

50

45

40

35

30

25

20

15

10

5

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

Switching Frequency (kHz)

D024

图10-3. FREQ Set Resistor vs Switching Frequency

The normal method of setting the buck regulator switching frequency is by selecting an appropriate value FREQ

resistor, the typical FREQ resistors value are listed in 表10-1.

表10-1. Setting the Switching Frequency with FREQ

SWITCHING FREQUENCY (KHz)

FREQ (KΩ)

80.6

253

400

49.9

19.1

1000

2100

2200

8.87

8.45

The FREQ/SYNC pin can be used to synchronize the internal oscillator to an external clock. The internal

oscillator can be synchronized by AC coupling a positive edge into the FREQ/SYNC pin. When using a low

impedance signal source, the frequency setting resistor FREQ is connected in parallel with an AC coupling

capacitor, C_COUP, to a termination resistor, R_TERM(for example, 50 Ω). The two resistors in series provide the

default frequency setting resistance when the signal source is turned off. A 10-pF ceramic capacitor can be used

for C_COUP. The AC coupled peak-to-peak voltage at the FREQ/SYNC pin must exceed the SYNC amplitude

threshold of 1.2 V (typ.) to trip the internal synchronization pulse detector, and the minimum SYNC clock HIGH

and LOW time must be longer than 100 ns (typ). A 2.5-V or higher amplitude pulse signal coupled through a 1-

nF capacitor, C_SYNC, is a good starting point. 图 10-4 shows the device synchronized to an external system

clock. The external clock must be off before start-up to allow proper start-up sequencing.

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CCOUP

RT

PLL

Lo-Z

Hi-Z

Clock

Source

FREQ/

SYNC

Clock

RTERM

RT

SYNC

Source

图10-4. Synchronize to External Clock

The TPS2585x-Q1 switching action can be synchronized to an external clock from 200 KHz to 3 MHz. Even the

switching frequency can be set to higher than 2.4 MHz, but TI recommends to set the switching frequency below

2.4 MHz due to the power dissipation, the higher switching frequency results in more power loss on IC, cause

the junction temperature and also the board temperature rising, then the device can enter load shedding under

high ambient temperature.

图 10-5, 图 10-6 and 图 10-7 show the device switching frequency and behavior under different VIN voltage and

R

_FREQ= 8.45 kΩ.

图10-8, 图10-9 and 图10-10 show the device switching frequency and behavior under different VIN voltage and

synchronized to an external 2.2-MHz system clock.

VIN

10V/Div

VIN

10V/Div

SW

10V/Div

SW

10V/Div

IL

5A/Div

500.0ns/Div

VIN = 8 V

L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 3 A

VIN = 13.5 V

L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 3 A

图10-5. Switching Frequency When R_FREQ= 8.45

kΩ

图10-6. Switching Frequency When R_FREQ= 8.45

kΩ

VIN

5V/Div

SYNC

VIN

10V/Div

2V/Div

SW

10V/Div

SW

10V/Div

IL

5A/Div

IL

5A/Div

500.0ns/Div

VIN = 18 V

L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 3 A

VIN = 8 V

L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 3 A

图10-7. Switching Frequency When R_FREQ= 8.45

kΩ

图10-8. Synchronizing to External 2.2-MHz Clock

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VIN

10V/Div

VIN

10V/Div

SYNC

2V/Div

SYNC

2V/Div

SW

10V/Div

SW

10V/Div

IL

5A/Div

500.0ns/Div

VIN = 13.5 V

L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 3 A

VIN = 18 V

L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 3 A

图10-9. Synchronizing to External 2.2-MHz Clock

图10-10. Synchronizing to External 2.2-MHz Clock

10.3.5 Bootstrap Voltage (BOOT)

The TPS2585x-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and

SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the

high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is

100 nF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is

recommended for stable performance over temperature and voltage. The BOOT rail has a UVLO to protect the

chip from operation with too little bias, and is typically 2.2 V. If the BOOT capacitor voltage drops below the

UVLO threshold, the device initiates a charging sequence using the low-side FET before attempting to turn on

the high-side device.

10.3.6 Minimum ON-Time, Minimum OFF-Time

Minimum ON-time, T_{ON_MIN}, is the smallest duration of time that the HS switch can be on. T_{ON_MIN}is typically 84

ns in the TPS2585x-Q1. Minimum OFF-time, T_{OFF_MIN}, is the smallest duration that the HS switch can be off.

T_{OFF_MIN}is typically 81 ns in the TPS2585x-Q1. In CCM (FPWM) operation, T_{ON_MIN}and T_{OFF_MIN}limit the

voltage conversion range given in a selected switching frequency.

The minimum duty cycle allowed is:

D_MIN= T_{ON_MIN}× f_SW

(5)

And the maximum duty cycle allowed is:

D_MAX= 1 –T_{OFF_MIN}× f_SW

(6)

Given fixed T_{ON_MIN}and T_{OFF_MIN}, the higher the switching frequency, the narrower the range of the allowed

duty cycle.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution

size, and efficiency. The maximum operation supply voltage can be found by:

V_OUT

V

=

IN_MAX

f

ì T_{ON_MIN}

(

)

SW

(7)

At lower supply voltage, the switching frequency is limited by T_{OFF_MIN}. The minimum V_INcan be approximated

by:

V_OUT

V

=

IN_MIN

1- f

(

ì T_{OFF _MIN}

)

SW

(8)

Considering power losses in the system with heavy load operation, V_{IN_MAX}is higher than the result calculated in

方程式7.

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If minimum ON-time or minimum OFF-time do not support the desired conversion ratio, frequency is reduced,

automatically allowing regulation to be maintained during load dump and with very low dropout during cold crank

even with high operating-frequency setting.

10.3.7 Internal Compensation

The TPS2585x-Q1 is internally compensated. The internal compensation is designed such that the loop

response is stable over the specified operating frequency and output voltage range. The TPS2585x-Q1 is

optimized for transient response over the range of 200 kHz ≤fsw ≤3000 kHz.

10.3.8 Selectable Output Voltage (VSET)

The TPS2585x-Q1 provides four different output voltage options. The voltage can be set by an external resistor

across the VSET pin. The normal method of setting the buck output voltage is by selecting an appropriate value

VSET resistor as shown in 表10-2.

表10-2. VSET Configuration vs BUS Output Voltage

VSET CONFIGURATION

Float or pull up to V_SENSE

Short to GND

V_SENSE

5.1 V

5.17 V

5.3 V

R_VSET= 40.2 KΩ

5.4 V

R_VSET= 80.6 KΩ

Note that the VSET has an internal weak 20-µA current source to overdrive the pin to SENSE. If this pin is

floated, the voltage on this pin approaches the SENSE voltage, and sets the output voltage to 5.1 V. TI does not

recommend to float this pin if there is external noise from the PCB board, because the noise interferes with the

VSET internal logic block.

10.3.9 Current Limit and Short Circuit Protection

For maximum versatility, the TPS2585x-Q1 includes both a precision, programmable current limit as well cycle-

by-cycle current limit to protect the USB port from extreme overload conditions. The R_ILIMresistor determines the

overload threshold on the USB ports in the event ILIM is shorted to ground to set the default USB current limit.

The cycle-by-cycle current limit serves as a backup means of protection.

10.3.9.1 USB Switch Programmable Current Limit (ILIM)

Because the TPS2585x-Q1 integrates two USB current-limit switches, it provides adjustable current limit to

prevent USB port overheating. The device engages the two-level current limit scheme, which has one typical

current limit, I_{OS_BUS}, and the secondary current limit, I_{OS_HI}. The secondary current limit, I_{OS_HI}, is 1.6x the

primary current limit, I_{OS_BUS}. The secondary current limit acts as the current limit threshold for a deglitch time,

t_{IOS_HI_DEG}, then the USB power switch current limit threshold is set back to I_{OS_BUS}. 方程式 9 calculates the

value of resistor for adjusting the typical current limit.

32273

R_ILIMKꢀ =

(

)

I_{OS _BUS}(mA)

(9)

This equation assumes an ideal-no variation-external adjusting resistor. To take resistor tolerance into account,

first determine the minimum and maximum resistor values based on its tolerance specifications and use these

values in the equations. Because of the inverse relationship between the current limit and the adjusting resistor,

use the maximum resistor value in the I_OS(min)equation and the minimum resistor value in the I_OS(max)equation.

Typical R_ILIMresistor value are listed in 表10-3.

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表10-3. Setting the Current Limit with R_ILIM

I_{OS_BUS}- Current Limit Threshold (mA)

R_ILIM(KΩ)

19.1

1690

2096

2806

3386

3550

15.4

11.5

9.53

Short to GND

For the normal application, it can short the ILIM pin to GND directly, which sets a default 3.55-A current limit with

a maximum ±15% variation on each USB port to follow the Type-C specification. The TPS2585x-Q1 provides

built-in soft-start circuitry that controls the rising slew rate of the output voltage to limit inrush current and voltage

surges.

The secondary current limit, I_{OS_HI}, allows the USB port pull out a larger current for a short time during transient

overload conditions, which can bring benefits for USB port special overload testing like MFi OCP. In a normal

application, once the device is powered on and USB port is not in UVLO, the USB port current limit threshold is

overridden by the secondary current limit, I_{OS_HI}, so the USB port can output as high as a 1.6 × I_{OS_BUS}current

for typically 2 ms. After the deglitch time, t_{IOS_HI_DEG}, the current limit threshold is set back to the typical current

with I_{OS_BUS}. The secondary current limit threshold does not resume until after the t_{IOS_HI_RST}deglitch time,

which is typically 16 ms. If there is an inrush current higher than the I_{OS_HI}threshold, the current limit is set back

to I_{OS_BUS}immediately, without waiting for a t_{IOS_HI_DEG}

.

The TPS2585x-Q1 responds to overcurrent conditions by limiting output current to I_{OS_BUS}as shown in previous

equation. When an overload condition occurs, the device maintains a constant output current and the output

voltage reduces accordingly. Three possible overload conditions can occur:

• The first condition is when a short circuit or overload is applied to the USB output when the device is powered

up or enabled. There can be inrush current and once it triggers the approximate 8-A threshold, a fast turnoff

circuit is activated to turn off the USB power switch within t_{IOS_USB}before the current limit control loop is able

to respond (shown in 图10-11). After the fast turnoff is triggered, the USB power switch current-sense

amplifier is over-driven during this time and momentarily disables the internal N-channel MOSFET to turn off

USB port. The current-sense amplifier then recovers and ramps the output current with a soft start. If the USB

port is still in overcurrent condition, the short circuit and overload hold the output near zero potential with

respect to ground and the power switch ramps the output current to I_{OS_BUS}. If the overcurrent limit condition

lasts longer than 4.1 ms, the corresponding USB channel enters hiccup mode with 524 ms of off-time and 4.1

ms of on-time.

IBUS

IOS_BUS

t

hiccup OFF

hiccup ON

tIOS

图10-11. Response Time to BUS Short-Circuit

• The second condition is the load current increases above I_{OS_BUS}but below the I_{OS_HI}setting. The device

allows the USB port to output this large current for t_{IOS_HI_DEG}, without limiting the USB port current to

I_{OS_BUS}. After the t_{IOS_HI_DEG}deglitch time, the device limits the output current to I_{OS_BUS}and works in a

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constant current-limit mode. If the load demands a current greater than I_{OS_BUS}, the USB output voltage

decreases to I_{OS_BUS}× R_LOADfor a resistive load, which is shown in 图10-12. If the overcurrent limit

condition lasts longer than 4.1 ms, the corresponding USB channel enters hiccup mode with 524 ms of off-

time and 4.1 ms of on-time. Another USB channel still works normally.

I

BUS(A)

V

BUS(V)

5

IOS_HI

IOS_BUS

0

hiccup OFF

hiccup ON

tIOS_HI_DEG

t

图10-12. BUS Overcurrent Protection

• The third condition is the load current increases just over the I_{OS_HI}setting. In this case, the load current does

not trigger the fast turnoff. The USB power switch current limit threshold is set back to the primary current

limit, I_{OS_BUS}, immediately. If the load still demands a current greater than I_{OS_BUS}, the USB output voltage

decreases to I_{OS_BUS}× R_LOADfor a resistive load, which is shown in 图10-13. If the overcurrent limit

condition lasts longer than 4.1 ms, the corresponding USB channel enters hiccup mode with 524 ms of off-

time and 4.1 ms of on-time. Another USB channel still works normally.

I

BUS(A)

V

BUS(V)

5

IOS_HI

IOS_BUS

0

hiccup OFF

hiccup ON

t

图10-13. BUS Overcurrent Protection: Two-Level Current Limit

The TPS2585x-Q1 thermal cycles if an overload condition is present long enough to activate thermal limiting in

any of the previously mentioned cases. Thermal limiting turns off the internal NFET and starts when the NFET

junction temperature exceeds 160°C (typical). The device remains off until the NFET junction temperature cools

10°C (typical) and then restarts. This extra thermal protection mechanism can help prevent further junction

temperature rise, which can cause the device to turn off due to junction temperature exceeding the main thermal

shutdown threshold, T_SD

.

10.3.9.2 Interlocking for Two-Level USB Switch Current Limit

The TPS2585x-Q1 has two USB ports. Because the secondary current limit, I_{OS_HI}, is 1.6x of the primary current

limit, I_{OS_BUS}, if the two USB ports pull out large current at the same time, then the DC/DC regulator is

overloaded, and DC/DC regulator output voltage can be crashed. To avoid these potential issues, the

TPS2585x-Q1 adopts the interlocking scheme to manage the current limits of the two USB ports.

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For interlocking, if one USB port current is beyond the primary current limit threshold, I_{OS_BUS}, then another USB

port current limit threshold is overridden to the primary current limit, I_{OS_BUS}, immediately. With this control

scheme, the TPS2585x-Q1 only allows one USB port to output a large current, which can be as high as 1.6x of

the primary current limit, I_{OS_BUS}, at the same time. Ensure the DC/DC regulator has enough energy to sustain

its output voltage. That means in MFi OCP testing, the DC/DC regulator supports up to 8.4 A output current

during the t_{IOS_HI_DEG}deglitch time, which 4.8 A for the USB type-C port which under testing, 3 A for another

USB type-C port, and maximum 0.6 A total for VCONN and OUT.

10.3.9.3 Cycle-by-Cycle Buck Current Limit

There is a buck regulator cycle-by-cycle current limit on both the peak and valley of the inductor current.

High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The

HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is

compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. The peak

current of HS switch is limited by a clamped maximum peak current threshold, I_{HS_LIMIT}, which is constant. The

peak current limit of the high-side switch is not affected by the slope compensation and remains constant over

the full duty cycle range.

The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor

current begins to ramp down. The LS switch does not turn OFF at the end of a switching cycle if its current is

above the LS current limit, I_{LS_LIMIT}. The LS switch is kept ON so that the inductor current keeps ramping down

until the inductor current ramps below the LS current limit, I_{LS_LIMIT}. Then, the LS switch is turned OFF and the

HS switch is turned on after a dead time. This action is somewhat different than the more typical peak current

limit, and results in 方程式10 for the maximum load current.

V

_IN- V_OUT

(

)

ì

V_OUT

I_{OUT _MAX}= I_{LS _LIMIT}

+

2ì f_SWìL

V

IN

(10)

10.3.9.4 OUT Current Limit

The TPS2585x-Q1 can provide 200-mA current at the OUT pin to power the auxiliary loads, such as USB HUB,

LEDs. The input of the OUT power switch comes from the buck regulator output, so the OUT voltage is same

with the SENSE voltage, but deduct the OUT R_DS-ONvoltage loss.

Because the OUT power is provided by buck regulator, for TPS25850-Q1, the buck regulator is not operating

unless Rd is inserted. In normal application, if no USB Type-C cable plug-in, then TPS25850-Q1 OUT voltage is

zero. For TPS25851-Q1 and TPS25852-Q1, the buck regulator will operate even though Rd is not inserted, so

even if no USB Type-C cable plug-in, the TPS25851-Q1 and TPS25852-Q1 OUT still have a voltage same with

the SENSE voltage.

If the OUT current reaches the current limit level, the OUT pin MOSFET works in a constant current-limit mode.

If the overcurrent limit condition lasts longer than 4.1 ms, it enters hiccup mode with 4.1 ms of on-time and 524

ms of off-time.

10.3.10 Cable Compensation

When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to

the load. In the vehicle from the voltage regulator output V_OUTto V_BUS(input voltage of portable device), the total

resistance of PCB trace, connector, and cable resistances causes an IR drop at the portable device input, so the

charging current of most portable devices is less than their expected maximum charging current. The voltage

drop is shown in 图10-14.

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5.x

V(DROP)

VOUT with compensation

VBUS with compensation

VBUS without compensation

3

1

2

Output Current (A)

图10-14. Voltage Drop

To handle this case, the TPS2585x-Q1 has a built-in cable compensation function where the droop

compensation linearly increases the voltage at the SENSE pin of the TPS2585x-Q1 as load current increases, to

maintain a fairly constant output voltage at the load-side voltage.

The TPS2585x-Q1 internal comparator compares the current-sense output voltage of the two current-limit

switches and uses the larger current-sense output voltage to compensate for the line drop voltage. The cable

compensation amplitude increases linearly as the load current increases. The cable compensation also has an

upper limitation. The cable compensation at output currents greater than 2.4 A is 90 mV and is shown in 图

10-15. Note the cable compensation only works when you short the VSET to GND. For the other VSET

configuration, the cable compensation is not available.

VSENSE

5.26V

5.17V

IPA/B_BUS

2.4A

图10-15. Dual Ports Cable Compensation

10.3.11 Thermal Management With Temperature Sensing (TS) and OTSD

The TS input pin allows for user-programmable thermal protection (for the TS pin thresholds, see the Electrical

Characteristics). The TS input pin threshold is ratiometric with V_SENSE. The external resistor divider setting, V_TS,

must be connected to the TPS2585x-Q1 SENSE pin to achieve accurate results (refer to the 图 10-16). When

V_TS= 0.5 × V_SENSE, the TPS2585x-Q1 performs below action:

• If operating with 3-A Type-C advertisement, the Px_CC1, Px_CC2 pin automatically reduces advertisement to

the 1.5-A level.

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VSENSE

RSER

VSENSE

RPARA

RNTC

TS

CC override

(3A -> 1.5A)

Vth9 ≈ 0.5 x VSENSE

RB

Vhys ≈ 500mV

TS_TEMP_HOT

Vth9 ≈ 0.65 x VSENSE

Vhys ≈ 500mV

图10-16. TS Input

If the overtemperature condition persists, causing V_TS= 0.65 × V_SENSE, the TPS2585x-Q1 performs below

actions:

• Broadcasts the default USB power mode, in default USB power, the charging is ideally reduced further per

the USB2.0 and USB3.0 specification.

• Buck regulator output voltage at the SENS pin is reduced to 4.77 V.

If the overtemperature condition persists, causing T_Jto reach the OTSD threshold, then the device thermal shuts

down.图 10-17 shows the TPS25850-Q1 behavior when TS pin voltage trigger the Temp Warm and Temp Hot

threshold.

ICCx (uA)

VBUS (V)

BUS Voltage

5.1

4.77

330

CC Broad Current

180

80

T1(Temp Warm)

T2(Temp Hot)

OTSD

图10-17. TPS25850-Q1 Behavior When Trigger Temp Warm/Hot Threshold

The NTC thermistor must be placed near the hottest point on the PCB. In most cases, this placement is close to

the SW node of the TPS2585x-Q1, near the buck inductor.

Tuning the V_NTCthreshold levels of V_{TEMP_WARM}and V_{TEMP_HOT}is achieved by adding R_SER, R_PARA, or both

R_SERand R_PARAin conjunction with R_NTC. 图 10-18 is an example illustrating how to set the V_{TEMP_WARM}

threshold between 81°C and 90°C with a ΔT between TEMP_WARM assertion and TEMP_HOT assertion of

18°C to 29°C. Consult the chosen NTC manufacturer's specification for the value of β. Establishing the desired

warning and shutdown thresholds can take some iteration.

Below is NTC spec and resistor value used in 图10-18 example.

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• R₀= 470 kΩ. β= 4750. R_NTC= R₀× exp β× (1/T –1/T₀).

• R_PARA= 100 kΩ.

• R_SER= 5.1 kΩ.

• R_B= R_NTC(at TEMP_WARM) = 27 kΩ.

5

4.5

4

3.5

3

VTS (V)

VTS w/ top ser (V)

VTS w/ top || (V)

VTS w/ para + ser (V)

TEMP_WARM

TEMP_HOT

2.5

2

1.5

1

0.5

0

20

40

60

80

100

120

140

NTC Temperature (°C)

T NTC (°C)

90

Rising Thresholds

Temp Warm

Temp Hot

V (V)

T NTC || (°C) T NTC ser (°C) T NTC || + ser (°C)

=VSENSE * 0.5

=VSENSE * 0.65

2.55

3.315

81

103

22

95

121

26

89

118

29

108

TEMP_HOT - TEMP_WARM

18

图10-18. V_TSThreshold Design Examples

10.3.12 Thermal Shutdown

The device has an internal overtemperature shutdown threshold, T_SD, to protect the device from damage and

overall safety of the system. When the device temperature exceeds T_SD, the device is turned off when thermal

shutdown activates. Once the die temperature falls below 154°C (typ.), the device reinitiates the power-up

sequence controlled by the internal soft-start circuitry.

10.3.13 USB Enable On/Off Control (TPS25852-Q1)

The PA_EN and PB_EN are the on/off control input pins for PA_USB and PB_USB, respectively. The USB

switch is active when Px_EN is pulled high. Pull the Px_EN voltage to logic low to shut down the USB switch

with an output discharge. Connect Px_EN to SENSE for automatic start-up, or control them by an external on/off

signal from the microcontroller or USB HUB.

10.3.14 FAULT Indication (TPS25851-Q1 and TPS25852-Q1)

For the TPS25851-Q1 and TPS25852-Q1, PA_FAULT and PB_FAULT are the fault indication pins for PA_USB

and PB_USB, respectively. FAULT is in an open-drain state during shutdown, start-up, or normal condition.

When the USB switch enters hiccup mode, or overtemperature thermal shutdown (OTSD) is triggered,

Px_FAULT is pulled low. FAULT asserts (logic low) on an individual USB switch during an over-current or

overtemperature condition. Px_FAULT switches high after the fault condition is removed, and the USB output

voltage goes high again.

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The device features an active-low, open-drain fault output. Connect a 100-kΩ pullup resistor from Px_FAULT to

SENSE or other suitable I/O voltage. Px_FAULT can be left open or tied to GND when not used.

表10-4 summarizes the conditions that generate a fault and actions taken by the device.

表10-4. Fault Conditions

EVENT

CONDITION

ACTION

Px_BUS load switch enter hiccup mode. The fault indicator

asserts with a 4.1-ms deglitch and de-asserts with a 16.4-ms

deglitch. The fault indicator remains asserted during the

Px_BUS overload condition.

Over-current on Px_BUS

I_{Px_BUS}> Programmed I_ILIM

The device immediately disables and asserts fault indicator

with no deglitch. The device attempts to power up once the

die temperature decreases below the thermal hysteresis

threshold as specified.

TPS2585x-Q1

overtemperature

T_J> T_SD

10.3.15 USB Specification Overview

All USB ports are capable of providing a 5-V output, making them a convenient power source for operating and

charging portable devices. USB specification documents outline specific power requirements to ensure

interoperability. In general, a USB 2.0 port host port is required to provide up to 500 mA; a USB 3.0 or USB 3.1

port is required to provide up to 900 mA; ports adhering to the USB Battery Charging 1.2 Specification provide

up to 1500 mA; newer Type-C ports can provide up to 3000 mA. Though USB standards governing power

requirements exist, some manufacturers of popular portable devices created their own proprietary mechanisms

to extend allowed available current beyond the 1500-mA maximum per BC 1.2. While not officially part of the

standards maintained by the USB-IF, these proprietary mechanisms are recognized and implemented by

manufacturers of USB charging ports.

The TPS2585x-Q1 device supports five of the most-common USB-charging schemes found in popular hand-held

media and cellular devices:

• USB Type-C (1.5-A and 3-A advertisement)

• USB Battery Charging Specification BC1.2 DCP mode

• Chinese Telecommunications Industry Standard YD/T 1591-2009

• Divider 3 mode

• 1.2-V mode

10.3.16 USB Type-C^®Basics

For a detailed description of the Type-C specification, refer to the USB-IF website to download the latest

released version. Some of the basic concepts of the Type-C spec that pertains to understanding the operation of

the TPS2585x-Q1 (a DFP device) are described as follows.

USB Type-C removes the need for different plug and receptacle types for host and device functionality. The

Type-C receptacle replaces both the Type-A and Type-B receptacles because the Type-C cable is plug-able in

either direction between the host and device. A host-to-device logical relationship is maintained by the

configuration channel (CC). Optionally, hosts and devices can be either providers or consumers of power when

USB PD communication is used to swap roles.

All USB Type-C ports operate in one of following data modes:

• Host mode: The port can only be a host (provider of power).

• Device mode: The port can only be a device (consumer of power).

• Dual-Role mode: The port can be either a host or device.

Port types:

• DFP (Downstream Facing Port): Host

• UFP (Upstream Facing Port): Device

• DRP (Dual-Role Port): Host or Device

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Valid DFP-to-UFP connections:

• 表10-5 describes valid DFP-to-UFP connections.

• Host-to-Host or Device-to-Device have no functions.

表10-5. DFP-to-UFP Connections

DEVICE-MODE

PORT

HOST-MODE PORT

DUAL-ROLE PORT

Host-Mode Port

Device-Mode Port

Dual-Role Port

No function

Works

No function

Works

Works⁽¹⁾

(1) This port can be automatic or manually driven.

10.3.16.1 Configuration Channel

The function of the configuration channel is to detect connections and configure the interface across the USB

Type-C cables and connectors.

Functionally, the Configuration Channel (CC) is used to serve the following purposes:

• Detect connect to the USB ports.

• Resolve cable orientation and twist connections to establish USB data bus routing.

• Establish DFP and UFP roles between two connected ports.

• Discover and configure power: USB Type-C current modes or USB Power Delivery.

• Discover and configure optional Alternate and Accessory modes.

• Enhances flexibility and ease of use.

Typical flow of DFP-to-UFP configuration is shown in 图10-19.

图10-19. Flow of DFP-to-UFP Configuration

10.3.16.2 Detecting a Connection

DFPs and DRPs fulfill the role of detecting a valid connection over USB Type-C. 图 10-20 shows a DFP-to-UFP

connection made with a Type-C cable. As shown in 图 10-20, the detection concept is based on being able to

detect terminations in the product that have been attached. A pull-up and pull-down termination model is used. A

pull-up termination can be replaced by a current source.

• In the DFP-UFP connection, the DFP monitors both CC pins for a voltage lower than the unterminated

voltage.

• An UFP advertises Rd on both its CC pins (CC1 and CC2).

• A powered cable advertises Ra on only one of the CC pins of the plug. Ra is used to inform the source to

apply VCONN.

• An analog audio device advertises Ra on both CC pins of the plug, which identifies it as an analog audio

device. VCONN is not applied on either CC pin in this case.

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UFP monitors for

connection

DFP monitors for

connection

Cable

CC

Rp

Rds

Ra

DFP monitors for

connection

UFP monitors for

connection

图10-20. DFP-UFP Connection

For USB Type-C solutions, two pins (CC1, CC2) on the connector are used to establish and manage the source-

to-sink connection. The general concept for setting up a valid connection between a source and a sink is based

on being able to detect terminations residing in the product being attached. To aid in defining the functional

behavior of CC, a pull-up (Rp) and pull-down (Rd 5.1 kΩ) termination model is used based on a pull-up resistor

and pull-down resistor.

Initially, a source exposes independent Rp terminations on its CC1 and CC2 pins, and a sink exposes

independent Rd terminations on its CC1 and CC2 pins. The source-to-sink combination of this circuit

configuration represents a valid connection. To detect this connection, the source monitors CC1 and CC2 for a

voltage lower than its unterminated voltage. The choice of Rp is a function of the pull-up termination voltage and

the detection circuit of the source. This indicates that either a sink, a powered cable, or a sink connected by a

powered cable has been attached. Prior to the application of VCONN, a powered cable exposes Ra (typically 1

kΩ) on its VCONN pin. Ra represents the load on VCONN plus any resistive elements to ground. In some cable

plugs, this can be a pure resistance, and in others, it can simply be the load.

The source must be able to differentiate between the presence of Rd and Ra to know whether there is a sink

attached and where to apply VCONN. The source is not required to source VCONN unless Ra is detected. Two

special termination combinations on the CC pins as seen by a source are defined for directly attached accessory

modes: Ra/Ra for audio adapter accessory mode and Rd/Rd for debug accessory mode.

10.3.16.3 Plug Polarity Detection (TPS25851-Q1)

Reversible Type-C plug orientation is reported by the Px_POL pin when a UFP is connected. However, when

there is no UFP attached, Px_POL remains de-asserted irrespective of cable plug orientation. 表 10-6 describes

the Px_POL state based on which device CC pin detects V_RDfrom an attached UFP pulldown.

表10-6. Plug Polarity Detection

Px_CC1

Rd

Px_CC2

Open

Rd

Px_POL

STATE

Hi-Z

UFP connected

Open

Asserted (pulled low)

UFP connected with reverse plug orientation

10.3.17 USB Port Operating Modes

10.3.17.1 USB Type-C^®Mode

The TPS2585x-Q1 is a Type-C controller that supports all Type-C functions in a downstream facing port. The

TPS2585x-Q1 is also used to manage current advertisement and protection to a connected UFP and active

cable. When V_SENSEexceeds the undervoltage lockout threshold, the device samples the EN pin. A high level on

this pin enables the device and normal operation begins. Having successfully completed its start-up sequence,

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the device now actively monitors its CC1 and CC2 pins for attachment to a UFP. When a UFP is detected on

either the CC1 or CC2 pin the USB power switch turn-ons. If Ra is detected on the other CC pin (not connected

to UFP), VCONN is applied to allow current to flow to the CC pin connected to Ra.

10.3.17.2 Dedicated Charging Port (DCP) Mode (TPS25850-Q1 Only)

A DCP only provides power and does not support data connection to an upstream port. As shown in the

following sections, a DCP is identified by the electrical characteristics of the data lines. The TPS25850-Q1 only

emulates one state, DCP-auto state. In the DCP-auto state, the device charge-detection state machine is

activated to selectively implement charging schemes involved with the shorted, Divider 3 and 1.2-V modes. The

shorted DCP mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009,

whereas the Divider 3 and 1.2-V modes are employed to charge devices that do not comply with the BC1.2 DCP

standard.

10.3.17.2.1 DCP BC1.2 and YD/T 1591-2009

Both standards specify that the D+ and D– data lines must be connected together with a maximum series

impedance of 200 Ω, as shown in 图10-21.

V_BUS

5 V

D–

200 Ω

(ma x.)

D+

GND

图10-21. DCP Supporting BC1.2 and YD/T 1591-2009

10.3.17.2.2 DCP Divider-Charging Scheme

The device supports Divider 3, as shown in 图 10-22. In the Divider 3 charging scheme the device applies 2.7 V

and 2.7 V to D+ and D–data lines.

V_BUS

5 V

D–

D+

2.7 V

GND

图10-22. Divider 3 Mode

10.3.17.2.3 DCP 1.2-V Charging Scheme

The DCP 1.2-V charging scheme is used by some hand-held devices to enable fast charging at 2 A. The

TPS25850-Q1 device supports this scheme in DCP-auto state before the device enters BC1.2 shorted mode. To

simulate this charging scheme, the D+ and D– lines are shorted and pulled up to 1.2 V for a fixed duration.

Then the device moves to DCP shorted mode as defined in the BC1.2 specification and as shown in 图10-23.

V_BUS

5 V

200 Ω (ma x.) D–

D+

1.2 V

GND

图10-23. 1.2-V Mode

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10.3.17.3 DCP Auto Mode (TPS25850-Q1)

The TPS25850-Q1 device integrates an auto-detect state machine that supports all the DCP charging schemes

as shown in 图 10-24. The auto-detect state machine starts in the Divider 3 scheme. If a BC1.2 or YD/T

1591-2009 compliant device is attached, the TPS25850-Q1 device responds by turning the power switch back

on without output discharge and operating in 1.2-V mode briefly before entering BC1.2 DCP mode. Then, the

auto-detect state machine stays in that mode until the device releases the data line, in which case, the auto-

detect state machine goes back to the Divider 3 scheme. When a Divider 3-compliant device is attached, the

TPS25850-Q1 device stays in the Divider 3 state.

5 V

S1

Divider 3 Mode

V_BUS

S1, S2: ON

S3, S4: OFF

DM_IN

DP_IN

GND

D–

D+

S2

S3

S4

Shorted Mode

S4 ON

S1, S2, S3: OFF

GND

1.2-V Mode

S1, S2: OFF

S3, S4: ON

2.7 V 2.7 V 1.2 V

图10-24. DCP Auto Mode

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10.4 Device Functional Modes

10.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the TPS2585x-Q1. When V_ENis below 1.2 V (typical), the

device is in shutdown mode. The TPS2585x also employs V_INovervoltage lock out protection and V_SENSE

undervoltage lock out protection. If V_INvoltage is above its respective OVLO level V_OVLO, or V_SENSEvoltage is

below its respective UVLO level V_{DCDC_UVLO}, the DC/DC converter turns off.

10.4.2 Active Mode

The TPS2585x-Q1 is in active mode when V_ENis above the precision enable threshold, V_SENSEis above its

respective UVLO levels and a valid detection has been made on the CC lines. The simplest way to enable the

TPS2585x-Q1 is to connect the EN pin to SENSE pin. This connection allows self startup when the input voltage

is in the operating range (5.5 V to 26 V) and a UFP detection is made.

In active mode, the TPS25850-Q1 buck regulator does not operate unless Rd is inserted, the TPS25851-Q1 and

TPS25852-Q1 buck regulator operates even though Rd is not inserted. Then the buck regulator operates with

Forced Pulse Width Modulation (FPWM), also referred to as Forced Continuous Conduction Mode (FCCM). This

action ensures the buck regulator switching frequency remains constant under all load conditions. FPWM

operation provides low output voltage ripple, tight output voltage regulation, and constant switching frequency.

Built-in spread-spectrum modulation aids in distributing spectral energy across a narrow band around the

switching frequency programmed by the FREQ/SYNC pin. Under light load conditions the inductor current is

allowed to go negative. A negative current limit of I_L-NEG-LSis imposed to prevent damage to the regulator's low

side FET. During operation, the TPS2585x-Q1 synchronizes to any valid clock signal on the FREQ/SYNC input.

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11 Application and Implementation

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

11.1 Application Information

The TPS2585x-Q1 is a step down DC-to-DC regulator and USB charge port controller. The device typically used

in automotive systems to convert a DC voltage from the vehicle battery to 5-V DC with a maximum output

current of 6.6-A in dual Type-C ports applications. The TPS2585x-Q1 engages a high efficiency buck converter,

letting the device operate at as high as 85°C ambient temperature with full load. The following design procedure

can be used to select components for the TPS2585x-Q1.

11.2 Typical Applications

The TPS2585x-Q1 only requires a few external components to convert from a wide voltage range supply to a 5-

V output to power USB devices. 图 11-1 shows the TPS25850-Q1 typical application schematic for Dual Type-C

charging ports.

SW

IN

22mF

22mF 22mF

BATT

100nF

BOOT

PGND

22mF

0.1mF

VSENSE

EN

VSENSE

SENSE

OUT

BIAS

1mF

TPS25850-Q1

1mF

IBUS=3A

VSENSE

PA_BUS

PA_DM

PA_DP

1mF

TS

PA_CC1

PA_CC2

1mF

IBUS=3A

PB_BUS

VSET

ILIM

PB_DM

PB_DP

FREQ/SYNC

AGND

PB_CC1

PB_CC2

1mF

图11-1. TPS25850-Q1 Typical Application Circuit for 2.1-MHz f_SW

As a quick start guide, 表 11-1 provides typical component values for some of the most common configurations.

The values given in 表 11-1 are typical. Other values can be used to enhance certain performance criterion as

required by the application. The integrated buck regulator of TPS2585x-Q1 is internally compensated and

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optimized for a reasonable selection of external inductance and capacitance. The external components have to

fulfill the needs of the application, but also the stability criteria of the control loop of the device.

表11-1. L and C_OUTTypical Values

V_OUTWITHOUT CABLE

f_SW

L

C_HF+ C_IN

C_BOOT

RATED C_OUT

COMPENSATION

400 KHZ

2.1 MHz

5.17 V

3.3 µH

1 × 100 nF + 1 × 47 µF

1 × 100 nF + 1 × 22 µF

1 × 100 nF

3 × 47 µF

3 × 22 µF

5.17 V

0.68 µH

1. The inductance value is calculated based on max V_IN= 18 V.

2. All the C_OUTvalues are after derating and use low ESR ceramic capacitors.

3. The C_OUTis the buck regulator output capacitors at the SENSE pin.

11.2.1 Design Requirements

The detailed design procedure is described based on a design example. For this design example, use the

parameters listed in 表11-2 as the input parameters.

表11-2. Design Example Parameters

Input voltage, V_IN

13.5-V typical, range from 8 V to 18 V

Output voltage, V_SENSE

Maximum output current

Switching frequency, f_SW

5.17 V

6.6 A

2.1 MHz

11.2.2 Detailed Design Procedure

11.2.2.1 Output Voltage Setting

The output voltage of TPS2585x-Q1 is programmed by the VSET pin, and if short VSET to GND, sets the output

voltage at 5.17 V and enables the cable compensation function, and the output voltage increases linearly with

increasing load current. Refer to 表 10-2 for more details on output voltage setting. Cable compensation can be

used to increase the voltage on the SENSE pin linearly with increasing load current. Refer to the list item in

Ground Plane and Thermal Considerations section for more details on cable compensation setting. If cable

compensation is not desired, use a 0-ΩR_IMONresistor.

11.2.2.2 Switching Frequency

The recommended switching frequency of the TPS2585x-Q1 is in the range of 250 KHz–400 KHz for high

efficiency. Choose R_FREQ= 49.9 kΩ for 400-KHz operation. To choose a different switching frequency, refer to

表10-1.

The choice of switching frequency is a compromise between conversion efficiency and overall solution size.

Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.

However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence, a

more compact design. In automotive USB charging applications, it tends to operate at either 400 kHz below the

AM band, or 2.1 MHz above the AM band. In this example, 2.1 MHz is chosen.

11.2.2.3 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The

inductance is based on the desired peak-to-peak ripple current, Δi_L. Because the ripple current increases with

the input voltage, the maximum input voltage is always used to calculate the minimum inductance L_MIN. Use 方

程式 12 to calculate the minimum value of the output inductor. K_INDis a coefficient that represents the amount of

inductor ripple current relative to the maximum output current of the device. A reasonable value of K_INDmust be

20% to 40%. Note that when selecting the ripple current for applications with much smaller maximum load than

the maximum available from the device, the maximum device current must still be used. During an instantaneous

short or overcurrent operation event, the RMS and peak inductor current can be high. The inductor current rating

must be higher than the current limit of the device.

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V_OUTì V

- V_OUT

(

)

IN_MAX

Di_L=

V_{IN_MAX}ìL ì f_SW

(11)

(12)

V

- V_OUT

V_OUT

IN_MAX

L_MIN

=

ì

I_OUTìK_IND

V

_{IN_MAX}ì f_SW

In general, Choose lower inductance in switching power supplies because it usually corresponds to faster

transient response, smaller DCR, and reduced size for more compact designs. Too low of an inductance can

generate too large of an inductor current ripple such that overcurrent protection at the full load can be falsely

triggered. Too low of an inductance also generates more conduction loss and inductor core loss. Larger inductor

current ripple also implies larger output voltage ripple with the same output capacitors. With peak current mode

control, TI does not recommend to have too small of an inductor current ripple. A larger peak current ripple

improves the comparator signal to noise ratio.

For this design example, choose K_IND= 0.3, and find an inductance of approximately 0.682 µH. Select the next

standard value of 0.68 μH.

11.2.2.4 Output Capacitor Selection

The output capacitor or capacitors, C_OUT, must be chosen with care because it directly affects the steady state

output voltage ripple, loop stability, and the voltage overshoot or undershoot during load current transients.

The value of the output capacitor and its ESR, determine the output voltage ripple and load transient

performance. The output capacitor is usually limited by the load transient requirements rather than the output

voltage ripple if the system requires tight voltage regulation with presence of large current steps and fast slew

rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor

current can slew up to the appropriate level. The control loop of the regulator usually needs four or more clock

cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the

current difference for four clock cycles to maintain the output voltage within the specified range. 表 11-3 can be

used to find output capacitors for a few common applications. In this example, good transient performance is

desired giving 3 x 22-µF ceramic as the output capacitor.

表11-3. Selected Output Capacitor

FREQUENCY

2.1 MHz

C_OUT

SIZE AND COST

TRANSIENT PERFORMANCE

3 × 22 µF ceramic

Small size

Good

Better

2.1 MHz

2 × 47 µF ceramic

Small size

2.1 MHz

2 × 22 µF ceramic

Smallest size

Small size

Minimum

Good

400 KHz

3 × 47 µF ceramic

2 × 47 µF ceramic

Small size

Minimum

Good

Larger size, low cost

4 × 22 µF + 1 × 260 µF, < 50-mΩ electrolytic

1 × 4.7 µF + 2 × 10 µF + 1 × 260 µF, < 50-

400 KHz

Lowest cost

Minimum

mΩ electrolytic

where

• K_IND= Ripple ratio of the inductor ripple current (Δi_L/ I_OUT

• I_OL= Low level output current during load transient

• I_OH= High level output current during load transient

• V_US= Target output voltage undershoot

)

• V_OS= Target output voltage overshoot

11.2.2.5 Input Capacitor Selection

The TPS2585x-Q1 device requires a high frequency input decoupling capacitor or capacitors, depending on the

application. A high-quality ceramic capacitor type X5R or X7R with sufficient voltage rating is recommended. The

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ceramic input capacitors provide a low impedance source to the converter in addition to supplying the ripple

current and isolating switching noise from other circuits. The typical recommended value for the high frequency

decoupling capacitor is 10 μF of ceramic capacitance. This must be rated for at least the maximum input

voltage that the application requires; preferably twice the maximum input voltage. This capacitance can be

increased to help reduce input voltage ripple, maintain the input voltage during load transients, or both. In

addition, a small case size 100-nF ceramic capacitor must be used at IN and PGND, immediately adjacent to the

converter. This action provides a high frequency bypass for the control circuits internal to the device. For this

example a 10-μF, 50-V, X7R (or better) ceramic capacitor is chosen, and the 100-nF ceramic capacitor must

also be rated at 50 V with an X7R or better dielectric.

Additionally, an electrolytic capacitor on the input in parallel with the ceramics can be required, especially if long

leads from the automotive battery to the IN pin of the TPS2585x-Q1, cold or warm engine crank requirements,

and so forth. The moderate ESR of this capacitor is used to provide damping to the voltage spike due to the lead

inductance of the cable or the trace.

11.2.2.6 Bootstrap Capacitor Selection

The TPS2585x-Q1 design requires a bootstrap capacitor (C_BOOT). The recommended capacitor is 100 nF and

rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap

capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. The bootstrap capacitor

must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.

11.2.2.7 Undervoltage Lockout Set-Point

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENTand

R_ENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down

or brownouts when the input voltage is falling. 方程式13 can be used to determine the V_INUVLO level.

R_ENT+ R_ENB

R_ENB

V

= V_ENHì

IN_RISING

(13)

The EN rising threshold (V_ENH) for the TPS2585x-Q1 is set to be 1.3 V (typical). Choose 10 kΩ for R_ENBto

minimize input current from the supply. If the desired V_INUVLO level is at 6.0 V, then the value of R_ENTcan be

calculated using 方程式14:

V

≈

’

IN_RISING

R_ENT

=

-1 ìR

∆

÷

ENB

÷

V_ENH

«

◊

(14)

方程式 14 yields a value of 36.1 kΩ. The resulting falling UVLO threshold equals 5.5 V and can be calculated by

方程式15, where EN hysteresis (V_{EN_HYS}) is 0.1 V (typical).

R_ENT+ R_ENB

R_ENB

V

= V_ENH- V_{EN_HYS}

(

ì

)

IN_FALLING

(15)

Note that it cannot connect EN to IN pin directly for self-start up. Because the voltage rating of EN pin is 11 V,

tying it to VIN directly damages the device. The simplest way to enable the operation of the TPS2585x-Q1 is to

connect the EN to V_SENSE. This connection allows the automatic start up when VIN is within the operation range.

11.2.2.8 Cable Compensation Set-Point

The TPS2585x-Q1 must short the VSET pin to ground to enable the cable compensation. With that setting, the

buck regulator increases its output voltage linearly as the load current increases, and the voltage compensation

at the currents of the USB ports greater than 2.4 A is 90 mV.

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11.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2100 kHz, L = 0.68 µH, C_SENSE= 66 µF,

C_{PA_BUS}= 1 µF, C_{PB_BUS}= 1 µF, ILIM = GND, T_A= 25 °C.

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

VIN=6V

VIN=13.5V

VIN=18V

VIN=26V

VIN=6V

VIN=13.5V

VIN=18V

0.1

1

6

0.1

1

6

Load Current(A)

VSET = GND

f_SW= 400 kHz

L = 3.3 uH

VSET = GND

f_SW= 2100 kHz

L = 0.68 uH

图11-2. Buck Only Efficiency

图11-3. Buck Only Efficiency

0.4

Level[dBuV]

VIN=6V

VIN=13.5V

VIN=18V

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

PA_BUS = 3A,

PB_BUS = 3A

f_SW= 2100 kHz

L = 0.68 uH

-1.2

-1.4

3

0

6

图11-4. 2.1-Mhz EMI Results (Without CM Filter)

Load Current(A)

VSET = GND

f_SW= 2100 kHz

图11-5. Load Regulation

Load=2A

0.1

Load=4A

Load=6A

VPA_BUS

200mV/Div

-0.1

-0.3

-0.5

-0.7

-0.9

-1.1

-1.3

-1.5

IPA_BUS

2A/Div

200.0us/Div

5

12

18

26

VSET =

V_SENSE

I_{PA_BUS}= 0 A to 3 A

I_{PB_BUS}= 3 A f_SW= 2100

kHZ

Input Voltage(V)

VSET = GND

f_SW= 2100 kHz

图11-7. Load Transient Without Cable

图11-6. Line Regulation

Compensation

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VPB_BUS

200mV/Div

VPA_BUS

200mV/Div

IPB_BUS

2A/Div

IPA_BUS

2A/Div

200.0us/Div

VSET =

V_SENSE

I_{PB_BUS}= 0 A to 3 A

I_{PA_BUS}= 3 A f_SW= 2100

kHZ

VSET =

V_SENSE

I_{PA_BUS}= 0.75 A to I_{PB_BUS}= 0 A

2.25 A

f_SW= 400

kHZ

图11-8. Load Transient Without Cable

图11-9. Load Transient Without Cable

Compensation

VPA_BUS

200mV/Div

VPA_BUS

200mV/Div

IPA_BUS

2A/Div

IPA_BUS

2A/Div

2.0ms/Div

VSET =

GND

I_{PA_BUS}= 0 A to 3 A

I_{PB_BUS}= 3 A f_SW= 2100

kHZ

VSET = I_{PA_BUS}= 0.75 A to

GND 2.25 A

I_{PB_BUS}= 0 A f_SW= 400

kHZ

图11-10. Load Transient With Cable Compensation

图11-11. Load Transient With Cable Compensation

5.2

Load=2A

Load=4A

SW

5V/Div

5.15

Load=6A

5.1

5.05

VPA_BUS

10mV/Div

5.0

4.95

500.0ns/Div

4.9

5.5

10.5

15.5

20.5

26

VSET = GND I_{PA_BUS}= 3 A I_{PB_BUS}= 3 A f_SW= 2100

kHZ

Input Voltage(V)

图11-12. Dropout Characteristic

图11-13. 6-A Output Ripple

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SW

5V/Div

SW

5V/Div

VPA_BUS

10mV/Div

VPA_BUS

10mV/Div

500.0ns/Div

VSET =

GND

I_{PA_BUS}= 0.1 A I_{PB_BUS}= 0 A f_SW= 2100

kHZ

VSET = GND I_{PA_BUS}= 0 A I_{PB_BUS}= 0 A f_SW= 2100

kHZ

图11-14. 100-mA Output Ripple

图11-15. No Load Output Ripple

EN

5V/Div

EN

5V/Div

VIN

5V/Div

VIN

5V/Div

VPA_BUS

5V/Div

VPA_BUS

5V/Div

VSENSE

5V/Div

VSENSE

5V/Div

50ms/Div

20ms/Div

VIN = 0 V to 13.5 V PA_CC1 = R_d

I_{PA_BUS}= 3 A

VIN = 13.5 V to 0 V PA_CC1 = R_d

I_{PA_BUS}= 3 A

图11-16. Startup Relate to VIN

图11-17. Shutdown Relate to VIN

EN

5V/Div

EN

5V/Div

VIN

2V/Div

VIN

5V/Div

VPB_BUS

5V/Div

VPB_BUS

5V/Div

VSENSE

5V/Div

VSENSE

5V/Div

50ms/Div

EN = 0 V to 5 V

PB_CC1 = R_d

I_{PB_BUS}= 3 A

EN = 5 V to 0 V

PB_CC1 = R_d

I_{PB_BUS}= 3 A

图11-18. Startup Relate to EN

图11-19. Shutdown Relate to EN

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VIN

10V/Div

VIN

10V/Div

VPA_BUS

2V/Div

VPA_BUS

2V/Div

VPA_CC1

2V/Div

VPA_CC1

2V/Div

VPA_CC2

2V/Div

VPA_CC2

2V/Div

20ms/Div

50ms/Div

PA_CC1 = R_dto

Open

PA_CC2 = Open

I_{PA_BUS}= 3 A

PA_CC1 = Open to

R_d

PA_CC2 = Open I_{PA_BUS}= 3 A

图11-21. Rd Desert

图11-20. Rd Assert

EN

5V/Div

EN

5V/Div

VPB_BUS

2V/Div

VPB_BUS

2V/Div

VPA_BUS

2V/Div

VPA_BUS

2V/Div

IPA_BUS

5A/Div

IPA_BUS

5A/Div

200.0ms/Div

EN to High

PA_BUS = GND

PB_BUS = GND

图11-23. Short Circuit Recovery

图11-22. Enable Into Short

EN

5V/Div

EN

5V/Div

VPB_BUS

2V/Div

VPB_BUS

2V/Div

VPA_BUS

3V/Div

VPA_BUS

3V/Div

IPA_BUS

3A/Div

IPA_BUS

3A/Div

500.0ms/Div

EN to High

PA_BUS = 1 Ω

PB_BUS = 1 Ω

图11-25. 1-ΩLoad Recovery

图11-24. Enable Into 1-ΩLoad

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VPA_CC1

2V/Div

EN

5V/Div

VPA_BUS

3V/Div

VPA_CC2

2V/Div

VPA_BUS

2V/Div

IPA_CC2

200mA/Div

IPA_BUS

5A/Div

2ms/Div

PA_CC1 = R_d

PA_CC2 = R_a

图11-26. VBUS Hot Short to GND

图11-27. PA_CC2 Hot Short to GND

EN

5V/Div

EN

5V/Div

VOUT

2V/Div

VOUT

2V/Div

VPA_BUS

2V/Div

VPA_BUS

2V/Div

IOUT

500mA/Div

IOUT

500mA/Div

5ms/Div

PA_CC1 = R_d

PA/B_BUS NO

LOAD

OUT = 5.1 Ω

PA_CC1 = R_d

OUT = GND

PA/B_BUS NO

LOAD

图11-28. OUT short to 5.1-ΩLoad

图11-29. OUT Hot Short to GND

VTS

2V/Div

VTS

2V/Div

VPA_BUS

5V/Div

VPA_BUS

5V/Div

VPA_CC1

2V/Div

VPA_CC1

2V/Div

SW

10V/Div

100.0ms/Div

SW

10V/Div

100.0ms/Div

V_TS= 0 V to 4 V

PA_CC1 = R_d

PA_CC2 = OPEN

V_TS= 0 V to 2.6 V PA_CC1 = R_d

PA_CC2 = OPEN

图11-31. Thermal Sensing - NTC Temperature HOT

图11-30. Thermal Sensing - NTC Temperature

Behavior

WARM Behavior

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12 Power Supply Recommendations

The input supply must be able to withstand the maximum input current and maintain a stable voltage. The

resistance of the input supply rail must be low enough that an input current transient does not cause a high

enough drop at the TPS2585x-Q1 supply voltage that it causes a false UVLO fault triggering and system reset. If

the TPS2585x-Q1 is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. An additional bulk capacitance can be required in addition to the ceramic input

capacitors. The amount of bulk capacitance is not critical, but a 100-μF electrolytic capacitor is a typical choice.

The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input

test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of

the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If

this scenario is considered likely, then a Schottky diode between the input supply and the output must be used.

13 Layout

13.1 Layout Guidelines

The PCB layout of any bulk converter is critical to the optimal performance of the design. Bad PCB layout can

disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB

layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,

the EMI performance of the converter is dependent on the PCB layout to a great extent. The following guidelines

will help users design a PCB with the best power conversion performance, thermal performance, and minimized

generation of unwanted EMI.

1. The input bypass capacitor, C_IN, must be placed as close as possible to the IN and PGND pins. The high

frequency ceramic bypass capacitors at the input side provide a primary path for the high di/dt components

of the pulsing current. Use a wide VIN plane on a lower layer to connect both of the VIN pairs together to the

input supply. Grounding for both the input and output capacitors must consist of localized top-side planes

that connect to the PGND pin and PAD.

2. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.

3. Use wide traces for the C_BOOTcapacitor. Place the C_BOOTcapacitor as close to the device with short, wide

traces to the BOOT and SW pins.

4. The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load

current without excessive heating. Short, thick traces or copper pours (shapes) must be used for a high

current conduction path to minimize parasitic resistance. The output capacitors must be placed close to the

V_SENSEend of the inductor and closely grounded to PGND pin and exposed PAD.

5. R_ILIMand R_FREQresistors must be placed as close as possible to the ILIM and FREQ pins and connected to

AGND. If needed, these components can be placed on the bottom side of the PCB with signals routed

through small vias, and the traces need far away from noisy nets like SW, BOOT.

6. Make V_IN, V_SENSE, and ground bus connections as wide as possible. This action reduces any voltage drops

on the input or output paths of the converter and maximizes efficiency.

7. Provide enough PCB area for proper heat sinking. Enough copper area must be used to ensure a low R_θJA

commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB

layers with two-ounce copper; and no less than one ounce. If the PCB design uses multiple copper layers

(recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note

,

that the package of this device dissipates heat through all pins. Wide traces must be used for all pins except

where noise considerations dictate minimization of area.

8. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.

If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-

spreading ground planes. Ensure enough copper area is used for heat-sinking to keep the junction

temperature below 150°C.

9. Keep the CC lines close to the same length. Do not create stubs or test points on the CC lines.

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13.2 Layout Example

EMI Filter

PGND

BATT

PGND

C_IN

L

VIN

RBOOT

20

19

18

17

16

15

14

13

21

22

CBOOT

RBOOT

12

11

VIN

SW

PB_BUS

SENSE

23

USB

24 PGND

PA_BUS ¹⁰

2

3

4

5

6

7

8

9

1

L

VSENSE

PGND

Top Trace/Plane

Inner GND Plane

Top

Inner GND Plane

Signal Layers

VIA to Signal Layer

VIA to GND Planes

VIA to Strap

Power and GND

图13-1. Layout Example

13.3 Ground Plane and Thermal Considerations

TI recommends to use one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. Ground plane also provides a quiet reference potential for the control circuitry. The

AGND and PGND pins must be connected to the ground plane using vias right next to the bypass capacitors.

The PGND pin is connected to the source of the internal low-side MOSFET switch, and also connected directly

to the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and

can bounce due to load variations. The PGND trace, as well as VIN and SW traces, must be constrained to one

side of the ground plane. The other side of the ground plane contains much less noise and must be used for

sensitive routes.

TI recommends to provide adequate device heat sinking by using the PAD of the IC as the primary thermal path.

Use a minimum 4 × 2 array of 12-mil thermal vias to connect the PAD to the system ground plane heat sink. The

vias must be evenly distributed under the PAD. Use as much copper as possible, for system ground plane, on

the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the

four layers, starting from the top of 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough copper thickness

provide low current conduction impedance, proper shielding, and lower thermal resistance.

The thermal characteristics of the TPS2585x-Q1 are specified using the parameter θ_JA, which characterizes the

junction temperature of silicon to the ambient temperature in a specific system. Although the value of θ_JAis

dependent on many variables, it still can be used to approximate the operating junction temperature of the

device. To obtain an estimate of the device junction temperature, one can use the following relationship:

T_J= P_D× θ_JA+ T_A

(16)

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where

• T_J= Junction temperature in °C

• P_D= V_IN× I_IN× (1 –Efficiency) –1.1 × I_OUT²× DCR in Watt

• DCR = Inductor DC parasitic resistance in Ω

• θ_JA= Junction-to-ambient thermal resistance of the device in °C/W

• T_A= Ambient temperature in °C

The maximum operating junction temperature of the TPS2585x-Q1 is 150°C. θ_JAis highly related to PCB size

and layout, as well as environmental factors such as heat sinking and air flow.

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14 Device and Documentation Support

14.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

14.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

14.3 Trademarks

HotRod^™and TI E2E^™are trademarks of Texas Instruments.

USB Type-C^®is a registered trademark of USB Implementers Forum.

所有商标均为其各自所有者的财产。

14.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

14.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OUTLINE

RPQ0025A

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

3.6

3.4

A

B

PIN 1 INDEX AREA

4.6

4.4

SIDE WALL

METAL THICKNESS

DIM A

OPTION 1

0.1

OPTION 2

0.2

C

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

1.325 0.1

0.75

0.55

PINS 7,8,14 & 15

0.975

0.775

4X

2X 1

8X (0.25)

10

EXPOSED

THERMAL PAD

SYMM

(DIM A) TYP

12

9

13

1.45

1.25

3X

0.65 0.1

PKG

25

2X 4

0.7

0.5

PINS 3 &19

PIN 1 ID

20X 0.5

0.3

24X

0.2

1

21

24

22

0.1

C A B

1.8

1.6

0.725

0.525

PINS 2 & 20

3X

0.05

0.9

0.7

PINS 4-6 & 16-18

4224966/B 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RPQ0025A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.1)

(3.05)

(1.325)

4X (1.075)

4X (0.675)

3X

(1.9)

SYMM

24

22

4X (0.575)

21

2X (0.825)

1

4X (0.25)

2X (0.8)

20X (0.5)

6X (1)

(1.5)

PKG

25

(0.65)

(R0.05) TYP

(1.675)

20X (0.25)

4X (0.85)

SEE SOLDER MASK

DETAIL

13

9

10

12

3X

(1.55)

(2.9)

(3.075)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

SOLDER MASK DEFINED

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224966/B 08/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RPQ0025A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.1)

(3.05)

4X (1.075)

4X (0.675)

SYMM

6X (0.85)

22

24

4X (0.575)

21

1

2X (0.825)

4X (0.25)

20X (0.5)

2X (0.8)

(2.025)

6X (1)

(0.975)

2X

(0.563)

PKG

25

2X (0.325)

(1.237)

2X (0.65)

26X (0.25)

(2.112)

4X (0.85)

13

9

(R0.05) TYP

10

12

6X

(0.675)

EXPOSED METAL

TYP

(0.763)

(2.9)

(3.075)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 25

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4224966/B 08/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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型号：	PTPS25850A0QRPQTQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有可编程电流限制和热管理功能的双路 3A USB Type-C 充电端口控制器 \| RPQ \| 25 \| -40 to 125 控制器
文件：	总65页 (文件大小：5837K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PTPS25850A0QRPQTQ1 [TI]

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