PTPS259480AYWPR [TI]
具有真正反向电流阻断保护功能的 3.5V 至 23V、13mΩ、8A 电子保险丝 | YWP | 12 | -40 to 125;
| 型号： | PTPS259480AYWPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有真正反向电流阻断保护功能的 3.5V 至 23V、13mΩ、8A 电子保险丝 | YWP | 12 | -40 to 125 电子 |
| 文件： | 总54页 (文件大小：4597K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS25948
ZHCSQ77 –FEBRUARY 2023
TPS25948xx 具有真正反向电流阻断功能的3.5V 至23V、13mΩ、8A 电子保险丝
成的背对背 FET，始终可以阻止从输出端到输入端的
反向电流流动，从而使该器件非常适合电源多路复用器
1 特性
• 宽工作输入电压范围：3.5 V 至23 V
和 ORing 应用以及需要负载侧能量保持存储解决方案
的系统（如果输入电源发生故障）。此类器件采用基于
线性 ORing 的方案，以确保实现几乎为零的直流反向
电流，并以更小的正向压降和功率耗散来仿真理想的二
极管行为。该器件还提供了一个外部引脚控制选项，以
禁用反向电流阻断并允许稳态双向电流流动。
– 绝对最大值为28V
– 可以从IN 或OUT 供电
• 具有低导通电阻的集成式背对背FET：RON
13mΩ（典型值）
=
• 具有真反向电流阻断功能的理想二极管运行状态
(RCB)
可以使用单个外部电容器来调节输出压摆率和浪涌电
流。通过在输入超过可调过压阈值时切断输出，可以保
护负载免受输入过压情况的影响。此类器件通过主动限
制电流来响应输出过载。用户可以调节输出电流限制阈
值以及瞬态过流消隐计时器。电流限制控制引脚还用作
模拟负载电流监控器。
– 外部引脚控制(RCBCTRL)，可禁用RCB 并允
许双向电流在稳态下流动，以支持USB OTG 操
作
• 快速过压保护
– 可调节过压锁定(OVLO)，响应时间为1μs（典
型值）
• 过流保护，具有负载电流监控器输出(ILM)
– 有效电流限制响应
这些器件采用 2.4mm × 1.7mm 12 焊球 power wafer
chip scale package (PowerWCSP)，旨在改善热性能
并减小系统尺寸。
– 可调节阈值(ILIM) 1A 至9A
这些器件的额定工作结温范围为-40°C 至+125°C。
• ILIM > 2 A 时精度为±10%
– 可调瞬态消隐计时器(ITIMER)，支持> ILIM 的
峰值电流
封装信息
封装(1)
封装尺寸（标称值）
器件型号
– 输出负载电流监控精度：±6% (IOUT ≥3A)
• 通过快速跳变响应实现短路保护
– 响应时间< 1μs（典型值）
– 可调节和固定阈值
TPS25948xxYWP
PWCSP (12)
2.40mm × 1.70mm
(1) 如需了解所有可用型号，请参阅数据表末尾的可订购产品附
录。
• 具有可调节欠压锁定阈值(UVLO) 的高电平有效使
能输入
VOUT
VIN = 2.7 to 23 V
IN
OUT
VLOGIC
• 可调节的输出压摆率控制(dVdt)
• 过温保护
COUT
EN/UVLO
TPS259480x
• 数字输出：电源正常(SPLYGD/SPLYGD) 和故障指
示(FLT)
SPLYGD
FLT
OVLO
• UL 2367 认证（已计划）
• IEC 62368-1 CB 认证（已计划）
• 小尺寸：PowerWCSP 2.4mm × 1.7mm，0.5mm
间距
ITIMER dVdt
GND
ILM
RILM
CITIMER
CDVDT
2 应用
简化版原理图
• 适配器和充电器输入保护
• USB PD 保护：智能手机、平板电脑、PC、笔记本
电脑、显示器、扩展坞
• 服务器主板、附加卡
• 企业级存储：HBA、SAN 和eSSD
• 电源多路复用和ORing
3 说明
TPS25948xx 系列电子保险丝是采用小型封装的高度集
成的电路保护和电源管理解决方案。此类器件提供使用
很少外部组件的多种保护模式，能够非常有效地抵御过
载、短路、电压浪涌、反极性和过多浪涌电流。借助集
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGT9
TPS25948
ZHCSQ77 –FEBRUARY 2023
www.ti.com.cn
Table of Contents
9.1 Application Information............................................. 30
9.2 Single Device, Self-Controlled.................................. 30
9.3 Typical Application.................................................... 31
9.4 Active ORing.............................................................35
9.5 Priority Power MUXing..............................................37
9.6 Parallel Operation..................................................... 42
9.7 USB PD Port Protection............................................44
9.8 Power Supply Recommendations.............................45
9.9 Layout....................................................................... 47
10 Device and Documentation Support..........................49
10.1 Documentation Support.......................................... 49
10.2 接收文档更新通知................................................... 49
10.3 支持资源..................................................................49
10.4 Trademarks.............................................................49
10.5 静电放电警告.......................................................... 49
10.6 术语表..................................................................... 49
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 绝对最大额定值...........................................................5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 电气特性......................................................................6
7.5 Timing Requirements..................................................8
7.6 Switching Characteristics............................................9
7.7 Typical Characteristics..............................................10
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................29
9 Application and Implementation..................................30
Information.................................................................... 50
11.1 Tape and Reel Information......................................50
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
February 2023
*
Initial Release
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5 Device Comparison Table
Steady-state
fast-trip threshold
Part Number
SPLYGD polarity
FLT or RCBCTRL
Response to Fault
TPS259480AYWP
TPS259480LYWP
TPS259482AYWP
TPS259482LYWP
TPS259481AYWP
TPS259481LYWP
Auto-Retry
Latch-Off
Auto-Retry
Latch-Off
Auto-Retry
Latch-Off
FLT
Adjustable (2 × ILIM
)
Active High
RCBCTRL
Fixed
Active Low
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6 Pin Configuration and Functions
VIN
12
VOUT
11
EN/UVLO
1
ITIMER
ILM
10
9
OVLO
2
SPLYGD/
SPLYGD
3
4
GND
8
7
6
5
FLT/
RCBCTRL
DVDT
VIN
VOUT
图6-1. YWP Package, 12-Ball PWCSP (Top View)
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Active high enable for the device. A resistor divider on this pin from input supply to GND
can be used to adjust the undervoltage lockout threshold. Do not leave floating. Refer to 节
8.3.1 for details.
Analog
input
EN/UVLO
1
A resistor divider on this pin from supply to GND can be used to adjust the overvoltage
lockout threshold. This pin can also be used as an Aactive low enable for the device. Do
not leave floating. Refer to 节8.3.2 for details.
Analog
input
OVLO
2
3
TPS259480x/2x: Active high Supply Good indication. This is an open drain signal which is
asserted high when the input supply is valid and channel has completed inrush sequence.
This can be used to enable/disable the auxiliary supply eFuse to facilitate smooth
switchover in a priority power MUXing configuration. Refer to 节8.3.8 for more details.
Digital
output
SPLYGD
TPS259481x: Active low Supply Good indication. This is an open drain signal which is
asserted Low when the input supply is valid and channel has completed inrush sequence.
This can be used to enable/disable the auxiliary supply eFuse to facilitate smooth
switchover in a priority power MUXing configuration. Refer to 节8.3.8 for more details.
Digital
output
SPLYGD
TPS259480x: Active low fault event indicator. This is an open drain signal which will be
pulled low when a fault is detected. Refer to 节8.3.7 for more details.
Digital
output
FLT
4
TPS259481x/2x: Active high reverse current blocking enable input. Leave the pin floating
or pull it high to enable reverse current blocking at all times. Pull the pin low to disable
reverse current blocking in steady-state to enable bi-directional current flow.
Digital
input
RCBCTRL
IN
5, 12
6, 11
Power Power input.
Power Power output.
OUT
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating
for the fastest turn on slew rate. Refer to 节8.3.3.1 for details.
Analog
output
DVDT
GND
7
8
Ground This is the ground reference for all internal circuits and must be connected to system GND.
This is a dual function pin used to limit and monitor the output current. An external resistor
from this pin to GND sets the output current limit threshold during start-up as well as
steady state. The pin voltage can also be used as analog output load current monitor
signal. Do not leave floating. Refer to 节8.3.3.2 for more details.
Analog
output
ILM
9
A capacitor from this pin to GND sets the overcurrent blanking interval during which the
output current can temporarily exceed set current limit (but lower than fast-trip threshold)
before the device overcurrent response takes action. Leave this pin open for fastest
response to overcurrent events. Refer to 节8.3.3.2 for more details.
Analog
output
ITIMER
10
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7 Specifications
7.1 绝对最大额定值
在自然通风条件下的工作温度范围内测得（除非另有说明）(1)
参数
引脚
最小值
OUT –21
OUT –22
最大值
单位
VIN
VIN
IN
IN
28
V
最大输入电压范围，–40℃≤TJ ≤125℃
最大输入电压范围，–10℃≤TJ ≤125℃
V
V
28
V
最小值
+
21）
VOUT
OUT
-0.3 （28，VIN
最大输出电压范围，–40℃≤TJ ≤125℃
最大输出电压范围，-10℃≤TJ ≤125℃
最小值
+
VOUT
OUT
OUT
-0.3 （28，VIN
22）
VOUT,PLS
VEN/UVLO
VOV
-0.8
–0.3
–0.3
最小输出电压脉冲(< 1µs)
最大使能引脚电压范围
EN/UVLO
OVLO
6.5
6.5
V
V
最大OVLO 引脚电压范围
最大dVdT 引脚电压范围
最大ITIMER 引脚电压范围
最大RCBCTRL 引脚电压范围
最大SPLYGD/SPLYGD 引脚电压范围
最大FLT 引脚电压范围
VdVdt
dVdt
V
受内部限制
VITIMER
VRCBCTRL
VSPLYGD
VFLTB
VILM
ITIMER
V
受内部限制
–0.3
RCBCTRL
SPLYGD/SPLYGD
FLT
6.5
6.5
6.5
V
V
–0.3
V
–0.3
ILM
V
最大ILM 引脚电压范围
受内部限制
受内部限制
受内部限制
IMAX
A
IN 至OUT
最大持续开关电流
结温
TJ
°C
°C
°C
TLEAD
Tstg
300
150
最高引线温度
存储温度
-65
(1) 超出绝对最大额定值运行可能会对器件造成永久损坏。绝对最大额定值并不表示
器件在这些条件下以及在建议运行条件以外的任何其他条件下能够正常运行。
如果在建议运行条件之外但又在绝对最大额定值范围内使用，器件可能不会完全
正常运行，这可能会影响器件的可靠性、功能性和性能，并缩短器件的寿命。
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001((1))
±2000
±500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101((2))
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
MAX
UNIT
VIN
Input Voltage Range
IN
2.7
23
V
min (23, VIN
+ 20)
VOUT
Output Voltage Range
OUT
V
VEN/UVLO
VOV
Enable Pin Voltage Range
OVLO Pin Voltage Range
dVdT Capacitor Voltage Rating
EN/UVLO
OVLO
5(1)
V
V
V
0.5
1.5
VdVdt
dVdt
VIN + 5 V((2))
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7.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
RCBCTRL
MIN
MAX
UNIT
VRCBCTRL
VFLTB
VSPLYGD
VITIMER
RILM
RCBCTRL Pin Voltage Range
FLTB Pin Voltage Range
5
5
5
V
V
V
V
FLTB
SPLYGD/SPLYGD Pin Voltage Range
ITIMER Pin Capacitor Voltage Rating
ILM Pin Resistance
SPLYGD/SPLYGD
ITIMER
4
ILM
536
4834
8
Ω
IMAX
IN to OUT
A
Continuous Switch Current, , TJ ≤125℃
Junction temperature
TJ
125
°C
–40
(1) For supply voltages below 5 V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5 V, it is recommended
to use a resistor divider to step down the voltage.
(2) In a PowerMUX scenario with unequal supplies, the dVdt capacitor rating for each device should be chosen based on the highest of
the 2 rails.
7.4 电气特性
（测试条件，除非另有说明）–40°C ≤TJ ≤125°C，VIN = 12V，OUT = 开路，VEN/UVLO = 2V，VOVLO = 0V，RILM
=
536Ω，dVdT = 开路，ITIMER = 开路，SPLYGD/SPLYGD = 开路，FLT = 对于TPS259480x 为开路，RCBCTRL = 对于
TPS259481x/2x 为开路。所有电压均以GND 为基准。
测试参数
输入电源(IN)
VUVP(R)
说明
最小值
典型值
最大值
单位
3.026
2.433
448
V
V
IN 电源欠压保护上升阈值
IN 电源欠压保护下降阈值
VUVP(F)
IQ(ON,IN)
ISD(IN)
µA
µA
V
从IN 供电时的IN 电源开启状态静态电流，VEN > VUVLO(R)
从IN 供电时的IN 电源关断电流，VEN < VSD(F)
OUT 电源欠压保护上升阈值
7
VUVP(R)
3.026
2.433
VUVP(F)
V
OUT 电源欠压保护下降阈值
输出电源(OUT)
从OUT 供电时的OUT 电源开启状态静态电流，VEN
>
IQ(ON,OUT)
440
6.3
µA
µA
VUVLO(R)
ISD(OUT)
从OUT 供电时的OUT 电源关断电流，VEN < VSD(F)
导通电阻(IN - OUT)
VIN = 12V，IOUT = 3A，TJ = 25℃
13
mΩ
mΩ
RON
3.5 ≤VIN ≤23V，IOUT = 3A，–40℃≤TJ ≤125℃
待定
使能/欠压锁定(EN/UVLO)
VUVLO(R)
VUVLO(F)
VSD(F)
1.20
1.09
0.76
V
V
可开启FET 的EN/UVLO 引脚上升阈值
可关闭FET 的UVLO 引脚下降阈值
最低关断电流的EN/UVLO 下降阈值
EN/UVLO 引脚漏电流
V
IENLKG
-0.1
-0.1
0.1
0.1
µA
过压锁定(OVLO)
VOV(R)
VOV(F)
IOVLKG
1.20
1.09
V
V
OVLO 引脚上升阈值
OVLO 引脚下降阈值
µA
OVLO 引脚漏电流，0.5V < VOVLO < 1.5V
输出负载电流监测器(IMON)
模拟负载电流监测器增益（IMON：IOUT），IOUT = 1A
至8A，IOUT < ILIM
GIMON
135
µA/A
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGT9
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7.4 电气特性(continued)
（测试条件，除非另有说明）–40°C ≤TJ ≤125°C，VIN = 12V，OUT = 开路，VEN/UVLO = 2V，VOVLO = 0V，RILM
=
536Ω，dVdT = 开路，ITIMER = 开路，SPLYGD/SPLYGD = 开路，FLT = 对于TPS259480x 为开路，RCBCTRL = 对于
TPS259481x/2x 为开路。所有电压均以GND 为基准。
测试参数
说明
最小值
典型值
最大值
单位
过流保护(OUT)
1
3
5
9
A
A
过流阈值，RILM = 4.81kΩ
过流阈值，RILM = 1.62kΩ
过流阈值，RILM = 965Ω
过流阈值，RILM = 536Ω
ILIM
A)
A
断路器阈值，ILM 引脚断开（单点
失效）
0.1
1.5
A)
A
IFLT
断路器阈值，ILM 引脚短接至GND（单点
失效）
可扩展快速跳变阈值(ISC)：ILIM 比率，仅限TPS259480x/2x
型号
ISCGain
200
%
23.5
21.6
1.89
A)
A)
V
固定快速跳变电流阈值，仅限TPS259480x/2x 型号
固定快速跳变电流阈值，仅限TPS259481x 型号
退出折返电流限制的VOUT 阈值
IFFT
VFB
过流故障计时器(ITIMER)
VINT
2.57
15
V
kΩ
µA
V
ITIMER 引脚内部上拉电压
ITIMER 引脚内部上拉电阻
ITIMER 引脚放电电流，IOUT > ILIM
ITIMER 放电差分电压阈值
RITIMER
IITIMER
ΔVITIMER
1.95
1.5
反向电流阻断(IN - OUT)
VFWD
10.2
mV
mV
VIN –VOUT 正向调节电压，IOUT = 10mA
用于快速BFET 关断的VIN –VOUT 阈值（进入反向电流阻
断）
VREVTH
-28.7
用于快速BFET 开启的VIN –VOUT 阈值（退出反向电流阻
断）
VFWDTH
IREVLKG
106
mV
µA
0.13
反向电流阻断条件下的反向漏电流
电源正常指示(SPLYGD/SPLYGD)
VSPLYGD
100
658
793
1
mV
mV
mV
µA
SPLYGD 引脚低电压VIN > 3.3V，强上拉
SPLYGD 引脚低电压VIN < 3.3V，EN < VSD(F)，弱上拉
SPLYGD 引脚低电压VIN < 3.3V，EN < VSD(F)，强上拉
SPLYGD 高位漏电流
VSPLYGD
VSPLYGD
ISPLYGDLKG
ISPLYGDBLKG
0.2
µA
SPLYGD 高位漏电流
故障指示(FLT) 或反向阻断控制(RCBCTRL)
IFLTBLKG
RFLTB
-1
1
µA
FLT 漏电流
12.3
5
FLT 引脚内部下拉电阻，仅限TPS259480x 型号
RCBCTRL 引脚内部上拉电流，仅限TPS259481x/2x 型号
Ω
IRCBCTRL
µA
RCBCTRL 引脚逻辑高电平检测阈值，仅限TPS259481x/2x
型号
VIH,RCBCTRL
VIL,RCBCTRL
1.15
1.04
V
V
RCBCTRL 引脚逻辑低电平检测阈值，仅限TPS259481x/2x
型号
过热保护(OTP)
TSD
154
°C
热关断上升阈值，TJ 上升
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7.4 电气特性(continued)
（测试条件，除非另有说明）–40°C ≤TJ ≤125°C，VIN = 12V，OUT = 开路，VEN/UVLO = 2V，VOVLO = 0V，RILM
=
536Ω，dVdT = 开路，ITIMER = 开路，SPLYGD/SPLYGD = 开路，FLT = 对于TPS259480x 为开路，RCBCTRL = 对于
TPS259481x/2x 为开路。所有电压均以GND 为基准。
测试参数
TSDHYS
压摆率控制(DVDT)
Idvdt
说明
最小值
典型值
最大值
单位
10
°C
热关断迟滞，TJ 下降
5.4
µA
dVdt 引脚充电电流
7.5 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
tOVLO
tLIM
tSC
tFT
Overvoltage lock-out response time
1
µs
VOVLO > VOV(R) to VOUT
↓
IOUT > 1.2 × ILIM & ITIMER expired to IOUT
settling to within 5 % of ILIM
Current limit response time
250
µs
Scalable fast-trip response time
(TPS259480x/2x only)
900
750
103
ns
ns
IOUT > 3 × ILIM to IOUT
IOUT > IFFT to IOUT
↓
Fixed fast-trip response time
↓
Auto-Retry interval after fault (TPS25948xA
only)
tRST
ms
tSWOV
OVLO fast recovery response time
85
43
µs
µs
VOVLO < VOV(F) to VOUT
↑
tSWRCB
Reverse Current Blocking recovery time
(VIN –VOUT) > VFWDTH to VOUT
↑
Reverse Current Blocking comparator
response time
tRCB
1.1
µs
(VOUT –VIN) > 1.3 × VREVTH to BFET OFF
tSPLYGDA Supply Good assertion de-glitch
tSPLYGDD Supply Good de-assertion de-glitch
14.7
14.3
µs
µs
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7.6 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn
on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin
to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt)
section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load
capacitance (COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up
sequence where the supply is available in steady state condition and the load voltage is completely discharged before the
device is enabled. Typical values are taken at TJ = 25°C unless specifically noted otherwise. ROUT = 100 Ω, COUT = 1 µF
PARAMETER
VIN
CdVdt = Open
0.15
CdVdt = 3.3 nF
CdVdt = 6.8 nF
UNITS
3.5
0.78
1.04
1.60
1.25
1.36
1.44
2.12
7.04
12.83
2.88
8.09
14.66
17.30
15.80
13.50
1.31
ms
tD,ON
SRON
tR
Turn on delay 12
0.17
2.04
23
0.18
3.44
3.5
14.40
25.30
38.30
0.20
0.58
V/ms
ms
Output rising
slew rate
12
0.60
23
0.65
3.5
4.59
Rise time
12
23
3.5
0.36
17.08
27.70
5.89
0.47
0.41
ms
tON
Turn on time 12
0.55
19.14
31.20
17.30
15.80
13.50
23
0.65
3.5
17.30
15.80
13.50
µs
tD,OFF
Turn off delay 12
23
3.5
tF
Fall time
12
23
Depends on ROUT and COUT
µs
VEN/UVLO
VUVLO(R)
VUVLO(F)
EN/UVLO
0
tON
tD,OFF
90%
VIN
SRON
OUT
10%
0V
tR
tF
tD,ON
Time
图7-1. Timing Diagram: Switching Characteristics
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7.7 Typical Characteristics
100000
10000
1000
100
10
1
0.2
0
20
40
60
80
100
120
140
Power Dissipation (W)
图7-2. Time to Thermal Shut-Down During Inrush State
VIN = 12 V, COUT = 220 μF, CdVdt = Open, VEN/UVLO stepped
up to 2 V
图7-3. Start Up With Enable
VEN/UVLO = 2 V, COUT = 220 μF, CdVdt = 10 nF, VIN ramped up
COUT = 220 μF, CdVdt = 10 nF, EN/UVLO connected to IN
to 12 V
through resistor ladder, 12 V hot-plugged to IN
图7-4. Start Up With Supply
图7-5. Input Hot-Plug
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7.7 Typical Characteristics (continued)
VIN = 12 V, COUT = 220 μF, CdVdt = 10 nF, VEN/UVLO stepped
VIN = 12 V, COUT = 220 μF, ROUT = 2 Ω, CdVdt = 3300 pF,
up to 2 V
VEN/UVLO stepped up to 2 V
图7-6. Inrush Current With Capacitive Load
图7-7. Inrush Current With Resistive and Capacitive Load
VIN Overvoltage threshold set to 16.5 V, VIN ramped up from
12 V to 16 V
VIN = 12 V, COUT = 690 μF, ROUT = 4 Ω, CdVdt = 3300 pF,
VEN/UVLO stepped up to 2 V
图7-9. Overvoltage Lockout Response
图7-8. Inrush Current With Resistive and Capacitive Load
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7.7 Typical Characteristics (continued)
VIN = 12 V, CITIMER = 22 nF, COUT = 220 μF, ILIM = 4.5 A, IOUT
ramped from 3 A →8 A→3 A within 9 ms
VIN = 12 V, CITIMER = 22 nF, COUT = 220 μF, ILIM = 4.5 A, IOUT
stepped from 3 A →9 A
图7-10. Transient Overcurrent Blanking Timer Response
图7-11. Active Current Limit Response Followed by TSD
VIN = 12 V, ILIM = 9 A, VEN/UVLO = 2 V, OUT stepped from
VIN = 12 V, ILIM = 9 A, VEN/UVLO = 2 V, OUT stepped from
Open →Short-circuit to GND
Open →Short-circuit to GND
图7-12. Output Short-Circuit During Steady State
图7-13. Output Short-Circuit During Steady State (Zoomed In)
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7.7 Typical Characteristics (continued)
VIN = 12 V, OUT short-circuit to GND, ILIM = 4.5 A, VEN/UVLO
stepped from 0 V to 2 V
VIN = 22 V, OUT short-circuit to GND, ILIM = 9 A, VEN/UVLO
stepped from 0 V to 2 V
图7-15. Power Up Into Short-Circuit
图7-14. Power Up Into Short-Circuit
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8 Detailed Description
8.1 Overview
The TPS25948xx is an eFuse with integrated power path that is used to ensure safe power delivery in a system.
The device starts its operation by monitoring the IN and OUT bus voltage. When the supply voltage (VIN or VOUT
)
exceeds the Undervoltage Protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (>
VUVLO) on this pin enables the internal power path (BFET+HFET) to start conducting and allow current to flow
between IN and OUT. When EN/UVLO is held low (< VUVLO), the internal power path is turned off to block
current flow between IN and OUT.
After a successful start-up sequence, the device now actively monitors its load current and bus voltage and
controls the internal HFET to ensure that the user adjustable overcurrent limit threshold (ILIM) is not exceeded
and overvoltage spikes are cut-off once they cross the user adjustable overvoltage lockout threshold (VOVLO).
The device also provides fast protection against severe overcurrent during short-circuit events. This keeps the
system safe from harmful levels of voltage and current. At the same time, a user adjustable overcurrent blanking
timer allows the system to pass moderate transient peaks in the load current profile without tripping the eFuse.
This ensures a robust protection solution against real faults which is also immune to transients, thereby ensuring
maximum system uptime.
The device has integrated reverse current blocking FET (BFET) which operates like an ideal diode. The BFET is
linearly regulated to maintain a small constant forward drop (VFWD) in forward conduction mode and turned off
completely to block reverse current if output voltage exceeds the input voltage. In some device variants, the
reverse current blocking can be disabled using an external pin control (RCBCTRL) to allow bi-directional current
flow to support applications such as USB On-the-go or DRP (Dual Role Port).
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device
temperature (TJ) exceeds the recommended operating conditions.
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8.2 Functional Block Diagram
FFT
TPS259480x
10.4 mV
Temp Sense &
Overtemperature
protection
TSD
6,
11
5,
12
IN
OUT
INRUSH_DONE
BFET
HFET
DVDT
CP
7
5.4
A
+
UVPb
3.04V
-
135 A/A
GHI
FFT
GHI
2.43V
RCB
-
2x
1x
-
SC
OC
2
OVLO
OVLOb
UVLOb
HFET Control
Current Limit Amplifier
1.20V
1.09V
+
-
+
+
BFET Control
1
EN/UVLO
+
ILM
9
1.20V
1.09V
-
SWEN
Short
Detect
ILM Pin Short
-
SD
+
RETRY#
0.76V
1.07 V
2.57 V
SD
UVPb
R
S
/Q
Q
RETRY#
110 ms
TIMER#
+
-
ITIMER_EXPIRED
TSD
FLT
10
ITIMER
GND
ILM Pin Short
RCB
ITIMER_EXPIRED
OC
1.95
A
8
4
FLT
# Not applicable to Latch-off variant (TPS259480L)
3
SPLYGD
图8-1. TPS259480x Block Diagram
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FFT
TPS259481x
10.4 mV
Temp Sense &
Overtemperature
protection
TSD
6,
11
5,
12
IN
OUT
INRUSH_DONE
BFET
HFET
DVDT
CP
7
5.4
A
+
UVPb
3.04V
-
135 A/A
GHI
FFT
GHI
2.43V
RCB
-
2x
1x
-
SC
OC
2
OVLO
OVLOb
UVLOb
HFET Control
Current Limit Amplifier
1.20V
1.09V
+
-
+
+
BFET Control
1
EN/UVLO
+
ILM
9
1.20V
1.09V
-
SWEN
Short
Detect
ILM Pin Short
-
SD
+
RETRY#
0.76V
1.07 V
2.57 V
SD
UVPb
R
S
/Q
Q
RETRY#
110 ms
TIMER#
+
-
ITIMER_EXPIRED
TSD
FLT
10
ITIMER
GND
ILM Pin Short
OC
1.95
A
8
4
3
SPLYGD
RCBCTRL
# Not applicable to Latch-off variant (TPS259481L)
图8-2. TPS259481x Block Diagram
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FFT
TPS259482x
10.4 mV
Temp Sense &
Overtemperature
protection
TSD
6,
11
5,
12
IN
OUT
INRUSH_DONE
BFET
HFET
DVDT
CP
7
5.4
A
+
UVPb
3.04V
2.43V
135 A/A
-
GHI
FFT
GHI
RCB
-
2x
1x
-
SC
OC
2
OVLO
OVLOb
UVLOb
HFET Control
Current Limit Amplifier
1.20V
1.09V
+
-
+
BFET Control
+
1
EN/UVLO
+
ILM
9
1.20V
1.09V
-
SWEN
Short
Detect
ILM Pin Short
-
SD
+
RETRY#
0.76V
1.07 V
2.57 V
SD
UVPb
R
S
/Q
Q
RETRY#
110 ms
TIMER#
+
-
ITIMER_EXPIRED
TSD
FLT
10
ITIMER
GND
ILM Pin Short
OC
1.95
A
8
4
3
SPLYGD
RCBCTRL
# Not applicable to Latch-off variant (TPS259482L)
图8-3. TPS259482x Block Diagram
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8.3 Feature Description
The TPS25948x eFuse is a compact, feature rich power management device that provides detection, protection
and indication in the event of system faults.
8.3.1 Undervoltage Lockout (UVLO & UVP)
The TPS25948xx implements Undervoltage Protection on IN and OUT in case the applied voltage becomes too
low for the system or device to properly operate. The Undervoltage Protection has a default lockout threshold of
VUVP which is fixed internally. Also, the UVLO comparator on the EN/UVLO pin allows the Undervoltage
Protection threshold to be externally adjusted to a user defined value. 图 8-4 and 方程式 1 show how a resistor
divider can be used to set the UVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/UVLO
R2
GND
图8-4. Adjustable Undervoltage Protection
R1 + R2
R2
VIN(UV) = VUVLO(F) ×
(1)
8.3.2 Overvoltage Lockout (OVLO)
The TPS25948xx allows the user to implement Overvoltage protection on the bus to shield the system against
supply overvoltage conditions. The internal fast comparator on the OVLO pin allows the Overvoltage Lockout
threshold to be adjusted to a user defined value. Once the voltage at the OVLO pin crosses the OVLO rising
threshold VOV(R), the device turns off both the FETs to cut off the power path. Thereafter, the devices wait for the
voltage at the OVLO pin to fall below the OVLO falling threshold VOV(F) before the FETs are turned ON again.
The rising and falling thresholds are slightly different to provide hysterisis. 图 8-5 and 方程式 2 show how a
resistor divider can be used to set the OVLO set point for a given voltage supply.
Power
Supply
IN
R1
OVLO
R2
GND
图8-5. Adjustable Overvoltage Protection
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R1 + R2
R2
VIN(OV) = VOV(F) ×
(2)
While recovering from a OVLO event, the TPS25948xx bypasses the inrush control (dVdt) and starts up in a
current limited manner to provide faster turn ON and minimize power supply droop during supply transient
conditions.
Input Overvoltage Event
Input Overvoltage Removed
IN
0
VOV(R)
VOV(F)
OVLO
tOVLO
0
tSWOV
OUT
Current Limited
Start-up
0
VFLT
FLT(1)
0
VSPLYGD
0
SPLYGD(2)
SPLYGD(3)
VSPLYGD
0
Time
(1) Applicable only to TPS259480x variants
(2) Applicable only to TPS259480x/2x variants
(3) Applicable only to TPS259481x variants
图8-6. TPS25948xx Overvoltage Lockout and Recovery
8.3.3 Inrush Current, Overcurrent, and Short Circuit Protection
TPS25948xx incorporates four levels of protection against overcurrent:
1. Adjustable slew rate (dVdt) for inrush current control
2. Adjustable threshold (ILIM) for overcurrent protection during start-up or steady-state
3. Adjustable threshold (ISC) for fast-trip response to severe overcurrent during start-up or steady-state
4. Fixed threshold (IFT) for fast-trip response to quickly protect against hard output short-circuits during steady-
state
8.3.3.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large
inrush current. If the inrush current is not managed properly, it can damage the input connectors and/or cause
the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current
during turn on is directly proportional to the load capacitance and rising slew rate.
方程式 3 can be used to find the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load
capacitance (COUT):
IINRUSH (mA) = COUT (µF) × SRON (V/ms)
(3)
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A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during
turn on. The required CdVdt capacitance to produce a given slew rate can be calculated using the equation:
5000
SRON (V/ms)
CDVDT (pF) =
(4)
The fastest output slew rate is achieved by leaving the dVdt pin open.
备注
1. Slew rate control during start-up is provided only on the HFET which enables inrush current
control from IN to OUT.
2. For CdVdt > 10 nF, it's recommended to add a 100-Ωresistor in series with the capacitor on the
dVdt pin.
8.3.3.2 Active Current Limiting
The TPS25948xx responds to output overcurrent conditions by actively limiting the current after a user
adjustable transient fault blanking interval. When the load current exceeds the set overcurrent threshold (ILIM) set
by the ILM pin resistor (RILM), but stays lower than the short-circuit threshold (2 × ILIM or IFFT depending on the
variant), the device starts discharging the ITIMER pin capacitor using an internal 1.95-μA pull-down current. If
the load current drops below the overcurrent threshold before the ITIMER capacitor (CITIMER) discharges by
ΔVITIMER, the ITIMER is reset by pulling it up to VINT internally and the current limit action is not engaged. This
allows short load transient pulses to pass through the device without getting current limited. If the overcurrent
condition persists, the CITIMER continues to discharge and once it discharges by ΔVITIMER, the current limit starts
regulating the HFET to actively limit the current to the set overcurrent threshold (ILIM). At the same time, the
CITIMER is charged up to VINT again so that it is at its default state before the next overcurrent event. This
ensures the full blanking timer interval is provided for every overcurrent event. 方程式 5 can be used to calculate
the RILM value for a desired overcurrent threshold.
4834
ILIM (A)
RILM (Ω) =
(5)
备注
1. The TPS259480x/2x variants allow a maximum transient load current up to 2 × ILIM for the ITIMER
duration. The TPS259481x variants allow a maximum transient load current up to IFFT for the
ITIMER duration.
2. Leaving the ILM pin Open sets the current limit to nearly zero and results in the part entering
current limit with the slightest amount of loading at the output.
3. The current limit circuit employs a foldback mechanism. The current limit threshold in the foldback
region (0 V < VOUT < VFB) is lower than the steady state current limit threshold (ILIM).
4. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the
part shuts down. There’s a minimum current (IFLT) which the part allows in this condition before
the pin short condition is detected.
The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER
pin to ground. The CITIMER value needed to set the desired transient overcurrent blanking interval can be
calculated using 方程式6 below.
tITIMER (ms) × IITIMER (µA)
CITIMER (nF) =
(6)
ΔVITIMER (V)
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Overload Removed
Persistent Output Overload
Transient Overcurrent
Persistent Output Overload
ITIMER expired
ITIMER expired
tLIM
Thermal shutdown
IFFT
(1)
2 x ILIM
tLIM
IOUT
ILIM
Current limiting
operation
Current limiting
operation
0
tITIMER
tITIMER
VINT
∆VITIMER
ITIMER
OUT
0
VIN
0
VFLT
FLT(2)
0
TSD
TSDHYS
TJ
TJ
Time
(1) Applicable only to TPS259480x/2x variants
(2) Applicable only to TPS259480x variants
图8-7. TPS25948xx Active Current Limit Response
备注
1. Leave the ITIMER pin open to allow the part to limit the current with the minimum possible delay.
2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to
ITIMER pin open condition), but increases the device current consumption. This is not a
recommended mode of operation.
3. Active current limiting based on RILM is active during startup. In case the startup current exceeds
ILIM, the device regulates the current to the set limit. However, during startup the current limit is
engaged without waiting for the ITIMER delay.
4. Increasing the CITIMER value extends the overcurrent blanking interval, but it also extends the time
needed for the CITIMER to recharge up to VINT. If the next overcurrent event occurs before the
CITIMER is recharged fully, it will take lesser time to discharge to the ITIMER expiry threshold,
thereby providing a shorter blanking interval than intended.
During active current limit, the output voltage will drop resulting in increased device power dissipation across the
HFET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the HFET is turned
off. Once the part shuts down due to TSD fault, it would either stay latched off (TPS25948xL variants) or restart
automatically after a fixed delay (TPS25948xA variants). See Overtemperature Protection (OTP) for more details
on device response to overtemperature.
8.3.3.3 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When a severe
overcurrent condition is detected, the device triggers a fast-trip response to limit the current to a safe level. For
the TPS259480x/2x variants, the internal fast-trip comparator employs a scalable threshold (ISC = 2 × ILIM). This
enables the user to adjust the fast-trip threshold rather than using a fixed threshold which can be too high for
some low current systems. The device also employs a fixed fast-trip threshold (IFFT) to protect fast protection
against hard short-circuits during steady state. The fixed fast-trip threshold is higher than the maximum
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recommended user adjustable scalable fast-trip threshold. The TPS259481x variants employ only the fixed fast-
trip threshold. Once the current exceeds ISC or IFFT, the HFET is turned off completely within tFT. Thereafter, the
devices tries to turn the HFET back on after a short de-glitch interval (30 μs) in a current limited manner instead
of a dVdt limited manner. This ensures that the HFET has a faster recovery after a transient overcurrent event
and minimizes the output voltage droop. However, if the fault is persistent, the device will stay in current limit
causing the junction temperature to rise and eventually enter thermal shutdown. See Overtemperature
Protection (OTP) section for details on the device response to overtemperature.
图8-8. TPS259480x/2x Short-Circuit Response
Persistent Severe Overcurrent
Thermal Shutdown
Overcurrent Removed
Retry Timer Elapsed (2)
Transient Severe Overcurrent
Output Hard Short-circuit to ground
Thermal Shutdown
Short-circuit Removed
Retry Timer Elapsed (2)
VIN
IN
0
tFT
tSC
tSC
IFT
(3)
2 x ILIM
IOUT
ILIM
0
VIN
OUT
dVdt Limited
Start-up
dVdt Limited
Start-up
Current Limited
Start-up
0
VFLT
FLT (1)
0
tRST
tRST
TSD
TSDHYS
TJ
Time
(1) Applicable only to TPS259480x variants
(2) Applicable only to TPS25948xA variants
(3) Applicable only to TPS259480x/2x variants
图8-9. TPS259481x Short-Circuit Response
Persistent Severe Overcurrent
Thermal Shutdown
Overcurrent Removed
Retry Timer Elapsed (1)
Transient Severe Overcurrent
Output Hard Short-circuit to ground
Thermal Shutdown
Short-circuit Removed
Retry Timer Elapsed (1)
VIN
IN
0
tFT
tFT
tFT
IFFT
IOUT
ILIM
0
VIN
OUT
dVdt Limited
Start-up
dVdt Limited
Start-up
Current Limited
Start-up
0
tRST
tRST
TSD
TSDHYS
TJ
Time
(1) Applicable only to TPS259481A variants
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8.3.4 Analog Load Current Monitor
The TPS25948xx allows the system to accurately monitor the output load current by providing an analog current
sense output on the ILM pin which is proportional to the current through the FET. The user can sense the voltage
(VILM) across the RILM to get a measure of the output load current.
VIMON (µV)
RILM (Ω) × GIMON (µA/A)
ILOAD (A) =
(7)
VIN = 12 V, COUT = 220 μF, RILM = 536 Ω, IOUT varied dynamically between 3 A and 8 A
图8-10. Analog Load Current Monitor Response
备注
The ILM pin is sensitive to capacitive loading. Careful design and layout is needed to ensure the
parasitic capacitive loading on the ILM pin is < 50 pF for stable operation.
8.3.5 Reverse Current Protection
The device functions like an ideal diode and blocks reverse current flow from OUT to IN under all conditions. The
device has integrated back-to-back MOSFETs connected in a common drain configuration. The voltage drop
between the IN and OUT pins is constantly monitored and the gate drive of the blocking FET (BFET) is adjusted
as needed to regulate the forward voltage drop at VFWD. This closed loop regulation scheme (linear ORing
control) enables graceful turn off of the MOSFET during a reverse current event and ensures there's almost no
DC reverse current flow.
The device also uses a conventional comparator (VREVTH) based reverse blocking mechanism to provide fast
response (tRCB) to transient reverse currents. Once the device enters reverse current blocking condition, it waits
for the (VIN - VOUT) forward drop to exceed the VFWDTH before it performs a fast recovery to reach full forward
conduction state. This provides sufficient hysterisis to prevent supply noise or ripple from affecting the reverse
current blocking response. The recovery from reverse current blocking is very fast (tSWRCB). This ensures
minimum supply droop which is helpful in applications such as supply MUXing/ORing and USB Fast Role Swap
(FRS).
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IOUT
1/RON
VFWD/RON
VIN-OUT
VFWD
VFWD
IN
OUT
OUT
IN
BFET operating state
Linear ORing loop response
RCB fast comparator response
BFET turned OFF
BFET regulation
BFET full conduction
BFET fast disable
(RCB entry)
BFET fast enable
(RCB exit)
VIN - VOUT
IIN
0 V
0 A
VFWD
VREVTH
VFWTH
Forward
Reverse
图8-11. Reverse Current Blocking Response
The waveforms below illustrate the reverse current blocking performance in various scenarios.
During fast voltage step at output (e.g. hot-plug), the fast comparator based reverse blocking mechanism
ensures minimum jump/glitch on the input rail.
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图8-12. Reverse Current Blocking Performance During Fast Voltage Step at Output
During slow voltage ramp at output, the linear ORing based reverse blocking mechanism ensures there's almost
no DC current flow from OUT to IN, thereby avoiding input rail from getting slowly charged up to output voltage.
图8-13. Reverse Current Blocking Performance During Slow Voltage Ramp at Output
When the input supply droops or gets disconnected while the output storage element (bulk capacitor or super
capacitor) is charged to the full voltage, the linear ORing scheme minimizes the self-discharge from OUT to IN.
This ensures maximum hold-up time for the output storage element in critical power back-up applications.
It also prevents incorrect supply presence indication in applications which sense the input voltage to detect if the
supply is connected.
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图8-14. Reverse Current Blocking Performance During Input Supply Failure
The TPS259481x/2x variants provide the option of disabling the reverse current blocking scheme using the
RCBCTRL pin. Leaving the RCBCTRL pin floating or pulling it high enables the reverse current blocking during
steady-state, while pulling the pin low disables it.
备注
RCBCTRL pin controls the reverse current blocking mechanism only during steady-state. It has no
effect during disabled or fault state where the reverse current blocking is always active.
8.3.6 Overtemperature Protection (OTP)
The device monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device will
not turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD - TSDHYS).
When the TPS25948xL (latch-off variant) detects thermal overload, it will be shut down and remain latched-off
until the device is power cycled or re-enabled. When the TPS25948xA (auto-retry variant) detects thermal
overload, it will remain off until it has cooled down by TSDHYS. Thereafter, it will remain off for an additional delay
of tRST after which it will automatically retry to turn on if it is still enabled.
表8-1. Thermal Shutdown
Device
Enter TSD
Exit TSD
TJ < TSD - TSDHYS
VIN cycled to 0 V and then above VUVP(R) OR EN/UVLO
TPS25948xL
(Latch-Off)
TJ ≥TSD
toggled below VSD(F)
TJ < TSD - TSDHYS
VIN cycled to 0 V and then above VUVP(R) OR EN/UVLO
toggled below VSD(F) OR tRST timer expired
TPS25948xA
(Auto-Retry)
TJ ≥TSD
8.3.7 Fault Response and Indication (FLT)
The following table summarizes the device response to various fault conditions. Additionally, an active low
external fault indication (FLT) pin is available on the TPS259480x variants.
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表8-2. Fault Summary
Fault Latched Internally FLT Pin status (1)
Event
Protection Response
FLT Assertion Delay(1)
Overtemperature
Shutdown
Y
N
N
N
N
N
L
Undervoltage (UVP or
UVLO)
Shutdown
Shutdown
None
H
H
L
Input Overvoltage
Transient Overcurrent (ILIM
< IOUT < 2 × ILIM or IFFT
)
Persistent Overcurrent
Current Limit
L
tITIMER
Output Short-Circuit to
GND
Circuit Breaker followed by
Current Limit
H
ILM Pin Open
(During Steady State)
Shutdown
N
Y
N
L
L
H
tITIMER
ILM Pin Shorted to GND
Shutdown
Reverse Current ((VOUT
-
Reverse Current Blocking
VIN) > VREVTH
)
(1) Applicable to TPS259480x variants only
Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by
pulling the EN/UVLO pin voltage below VSD. This also releases the FLT pin pull-down for the TPS259480x
variants and resets the tRST timer for the TPS25948xA (auto-retry) variants.
During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This is
true for both TPS25948xL (latch-off) & TPS25948xA (auto-retry) variants.
For TPS25948xA (auto-retry) variants, on expiry of the tRST timer after a fault, the device restarts automatically
and the FLT pin is de-asserted (TPS259480A variant).
8.3.8 Supply Good Indication (SPLYGD/SPLYGD)
The TPS25948xx provides a digital output (SPLYGD/SPLYGD) which is asserted to indicate when the priority
input supply is in a valid range (above UVP/UVLO and below OVLO thresholds) and the device has successfully
completed its inrush sequence. The SPLYGD/SPLYGD pin is an open-drain signal which needs to be pulled up
to an external supply. For the TPS259480x/2x variants, SPLYGD is an active high output. For the TPS259481x
variant, SPLYGD is an active low output.
After power up, SPLYGD/SPLYGD pin is de-asserted initially. The device initiates a inrush sequence in which the
HFET is turned on in a controlled manner. When the FET gate voltage has reached the full overdrive indicating
that the inrush sequence is complete and device is capable of delivering full power, the SPLYGD/SPLYGD pin is
asserted. Thereafter, the SPLYGD/SPLYGD pin is de-asserted only if the input supply becomes invalid (below
UVP/UVLO or above OVLO thresholds). No load side events/faults have any control over the SPLYGD/SPLYGD
de-assertion.
This pin is used to control the auxiliary channel when 2 TPS25948xx devices are connected in a priority power
MUX configuration. It can also be used as a supply valid status indication to the downstream load or system
supervisor.
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Overload Event
Overcurrent blanking timer expired
Overload Removed
Device Enabled
VUVLO(R)
EN/UVLO
0
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
Active current limiting
VIN
OUT
0
VSPLYGD
SPLYGD(1)
SPLYGD(2)
VSPLYGD
0
VIN
dVdt
0
VOUT + 2.8V
VHGate
0
tITIMER
ILIM
IINRUSH
IOUT
0
Time
(1) Applicable only to TPS259480x/2x variants
(2) Applicable only to TPS259481x variants
图8-15. TPS25948xx SPLYGD behavior
表8-3. TPS25948xx SPLYGD/SPLYGD Indication Summary
Event/Condition
SPLYGD Pin(1)
SPLYGD Pin(2)
Supply Brownout (UVP)
L
L
L
L
L
H
L
Shutdown (EN < VSD
)
L
Undervoltage (UVLO)
Overvoltage (OVLO)
Inrush
H
H
H
L
Steady State
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表8-3. TPS25948xx SPLYGD/SPLYGD Indication Summary (continued)
Event/Condition
SPLYGD Pin(1)
SPLYGD Pin(2)
Overcurrent
H
H
H
H
H
L
L
L
L
L
Short-Circuit
ILM Pin Open
ILM Pin Shorted to GND
Reverse current ((VOUT –VIN) >
VREVTH
)
Overtemperature
H
L
(1) Applicable only to TPS259480x/2x variants.
(2) Applicable only to TPS259481x variants.
When there is no supply to the device, the SPLYGD pin is expected to stay low. However, there is no active pull-
down in this condition to drive this pin all the way down to 0 V. If the SPLYGD pin is pulled up to an independent
supply which is present even if the device is unpowered, there can be a small voltage seen on this pin
depending on the pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the
sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external
circuits in this condition. This also ensures that the auxiliary channel is not turned off inadvertently in a priority
power MUX configuration.
8.4 Device Functional Modes
表8-4. TPS259481x/2x Reverse Current Blocking Operation
RCBCTRL Pin Connection
Reverse Current Blocking in Steady-State
Low
Disabled
Enabled
Open or High
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS25948x is a 3.5 V to 23 V, 8-A eFuse that is typically used for power rail protection applications . It
operates from 3.5 V to 23 V with adjustable overvoltage and undervoltage protection. It provides ability to control
inrush current and protection against reverse current conditions. It can be used in a variety of systems such as
Adapter/Charger input protection, USB PD protection in Smartphone/Tablets/PC/notebook/monitors/docks,
Server/PC motherboard/add-on cards, Enterprise storage – RAID/HBA/SAN/eSSD, Power MUXing/ORing. The
design procedure explained in the subsequent sections can be used to select the supporting component values
based on the application requirement. Additionally, a spreadsheet design tool TPS25948x Design Calculator is
available in the web product folder.
9.2 Single Device, Self-Controlled
VOUT
VIN = 2.7 to 23 V
IN
OUT
VOUT
VIN = 2.7 to 23 V
IN
OUT
VLOGIC
VLOGIC
COUT
COUT
EN/UVLO
EN/UVLO
TPS259480x
TPS259482x
SPLYGD
FLT
SPLYGD
OVLO
OVLO
RCBCTRL
ITIMER dVdt
ILM
GND
ITIMER dVdt
ILM
GND
VOUT
VIN = 2.7 to 23 V
IN
OUT
VLOGIC
COUT
EN/UVLO
TPS259481x
SPLYGD
OVLO
RCBCTRL
ITIMER dVdt
ILM
GND
图9-1. Single Device, Self-Controlled
Other variations:
In a Host MCU controlled system, EN/UVLO or OVLO can also be driven from the host GPIO to control the
device.
ILM pin can be connected to the MCU ADC input for current monitoring purpose.
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备注
It's recommended to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation.
9.3 Typical Application
Smartphones come equipped with USB OTG functionality that allows their USB port to be used not only for
charging the phone battery but also allow the smartphone to act as a USB host and deliver power to external
accessories such as headphones, pen drives, and so forth. Some smartphones also support a wireless charging
path which can also be used to wirelessly share power to other devices. TPS259482 can be used as a bi-
directional power switch in such applications as shown in 图 9-3. For the USB power path, when an external
charger is connected at the port, TPS259482 provides a conduction path from IN pin to OUT pin and the battery
charger IC is configured to charge the battery and also power the internal circuits. TPS259482 also provides
overvoltage and overcurrent protection in this case. In another use case scenario where an accessory such as
headphone is connected to the USB port, the phone MCU detects this and the battery charger is configured in
OTG boost mode to provide power from battery to the USB port. MCU will also pull down RCBCTRL pin to allow
current flow from OUT pin to IN pin of TPS259482 and enables the TPS259482 and establishes a low
impedance power path capable of delivering high power to the accessory. Similarly, the TPS259482 also
provides controlled bi-directional power flow in the wireless charging and power share sub-system.
VBUS = 5 to 20 V
IN
OUT
SYS
System Load
VBUS
VLOGIC
CBUS
TVS2200
PMID
BAT
BQ25898x
OVLO
SPLYGD
TPS259482x
EN/UVLO
RCBCTRL
ITIMER
dVdt
ILM
GND
RILM
CITIMER
CDVDT
System MCU
IN
OUT
Wireless Charger
VLOGIC
OVLO
SPLYGD
TPS259482x
EN/UVLO
RCBCTRL
ITIMER
dVdt
ILM
GND
Current monitor ADC
RILM
CITIMER
CDVDT
图9-2. Smartphone Power Path Example
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V
BUS = 5 to 20 V
VOUT
IN
OUT
SYS
System Load
VBUS
VLOGIC
R1
470 k
COUT
47 uF
CBUS
D1*
10 uF
BQ25713
OVLO
TVS2200
SPLYGD
EN/UVLO
RCBCTRL
TPS259482x
R2
System
MCU
26.7 k
BAT
ITIMER dVdt
ILM
GND
RILM
866
CITIMER
2.2 nF
CDVDT
3000 pF
* Optional circuit components needed for transient protection depending on input and output inductance. Please
refer to Transient Protection section for details.
图9-3. USB On-The-Go Port Protection Design Example
9.3.1 Design Requirements
表9-1. Design Parameters
PARAMETER
VALUE
Bus voltage during charging (VIN)
20 V
Overvoltage protection threshold during charging (VIN(OV)
)
22 V
5 A
Max continuous charging current
Load transient blanking interval during charging (tITIMER
)
2 ms
47 μF
12 ms
5.5 A
Output capacitance (COUT
Output rise time (tR)
)
Overcurrent threshold (ILIM) during charging
9.3.2 Detailed Design Procedure
9.3.2.1 Setting Overvoltage Threshold
The supply overvoltage threshold is set using the resistors, R1 and R2, whose values can be calculated as:
VOV(R) x (R1 + R2)
VIN(OV) =
(8)
R2
Where VOV(R) is the OVLO rising threshold. Because R1, R2 leak the current from input supply VIN, these
resistors must be selected based on the acceptable leakage current from input power supply VIN. The current
drawn by R1, R2 from the power supply is IR12 = VIN / (R1 + R2). However, leakage currents due to external
active components connected to the resistor string can add error to these calculations. So, the resistor string
current, IR12, must be chosen to be 20 times greater than the leakage current expected on the OVLO pin.
From the device electrical specifications, OVLO leakage current is 0.1 μA (maximum), VOV(R) = 1.2 V. From
design requirements, VIN(OV) = 22 V. To solve the equation, first choose the value of R1 = 470 kΩ and use the
above equation to solve for R2 = 27.11 kΩ.
Using the closest standard 1% resistor values, we get R1 = 470 kΩ, R2 = 26.7 kΩ.
9.3.2.2 Setting Output Voltage Rise Time (tR)
For a successful design, the junction temperature of device must be kept below the absolute maximum rating
during both dynamic (start-up) and steady-state conditions. Dynamic power stresses often are an order of
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magnitude greater than the static stresses, so it is important to determine the right start-up time and inrush
current limit required with system capacitance to avoid thermal shutdown during start-up.
The slew rate (SR) needed to achieve the desired output rise time can be calculated as:
VIN V
tR ms
20 V
12 ms
SR (V/ms) =
=
= 1.67 V/ms
(9)
The CdVdt needed to achieve this slew rate can be calculated as:
5000
SR V/ms
5000
1.67
CdVdt pF =
=
= 2994 pF
(10)
Choose the nearest standard capacitor value as 3000 pF.
For this slew rate, the inrush current can be calculated as:
IINRUSH mA = SR (V/ms) x COUT µF = 1.67 x 47 = 79 mA
(11)
(12)
The average power dissipation inside the part during inrush can be calculated as:
IINRUSH A x VIN V
2
0.079 x 20
= 0.8 W
2
PDINRUSH W =
=
For the given power dissipation, the thermal shutdown time of the device must be greater than the ramp-up time
tR to avoid start-up failure. 图 9-4 shows the thermal shutdown limit, for 0.8 W of power, the shutdown time is
more than 10 s which is very large as compared to tR = 12 ms. Therefore, it is safe to use 12 ms as the startup
time for this application.
100000
10000
1000
100
10
1
0.2
0
20
40
60
80
100
120
140
Power Dissipation (W)
图9-4. Thermal Shut-Down Plot During Inrush
9.3.2.3 Setting Overcurrent Threshold (ILIM
)
The overcurrent protection threshold can be set using the RILM resistor whose value can be calculated as:
4834
ILIM A
4834
5.5 A
RILM Ω =
=
= 879 Ω
(13)
Choose nearest 1% standard resistor value as 866 Ω.
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9.3.2.4 Setting Overcurrent Blanking Interval (tITIMER
)
The overcurrent blanking timer interval can be set using the CITIMER capacitor whose value can be calculated as:
tITIMER (ms) x IITIMER (µA)
2 x 1.95
1.51
CITIMER (nF) =
=
= 2.6 nF
(14)
∆ VITIMER (V)
Choose nearest standard capacitor value as 2.2 nF.
9.3.3 Application Curves
图9-5. Power Up
图9-6. Overvoltage Protection
图9-7. Overcurrent Protection
图9-8. Short at Output Protection
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图9-9. Wake up into Short Protection
图9-10. Power Up in OTG Mode
9.4 Active ORing
A typical redundant power supply configuration is shown in 图 9-11 below. Schottky ORing diodes have been
popular for connecting parallel power supplies, such as parallel operation of wall adapter with a battery or a hold-
up storage capacitor. The disadvantage of using ORing diodes is high voltage drop and associated power loss.
The TPS25948xx with integrated, low-ohmic, back-to-back FETs provide a simple and efficient solution. 图 9-11
below shows the Active ORing implementation using TPS249480x devices.
IN
OUT
VOUT
VIN1
VLOGIC
COUT
EN/UVLO
TPS259480x
SPLYGD
SPLYGD_SYS
OVLO
ITIMER dVdt
GND
ILM
VIN1
VIN2
Hotswap protection
IN
OUT
VIN2
VLOGIC
EN/UVLO
TPS259480x
OVLO
SPLYGD
ITIMER dVdt
GND
ILM
图9-11. Two Devices, Active ORing Configuration
The linear ORing mechanism in TPS25948xx ensures that there's no reverse current flowing from one power
source to the other during fast or slow ramp of either supply.
The following waveform illustrates the active ORing behavior when the supply rails are being ramped up
sequentially.
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图9-12. Active ORing Response
图9-13. Active ORing Response
When the bus voltages (IN1 and IN2) are matched, device in each path sees a forward voltage drop and is ON
delivering the load current. During this period, current is shared between the rails in the ratio of differential
voltage drop across each device.
In addition to supply ORing, the devices protect the system from overvoltage, excessive inrush current, overload
and short-circuit faults at all times.
备注
ORing can be done either between two similar rails or between dissimilar rails. For ORing cases with
skewed voltage combinations, the dVdt pin capacitor rating should be chosen based on the highest of
the 2 supplies. Refer to Recommended Operating Conditions table for more details.
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9.5 Priority Power MUXing
Applications having two energy sources such as PCIe cards, Tablets and Portable battery powered equipment
require preference of one source to another. For example, mains power (wall-adapter) has the priority over the
internal battery back-up power. These applications demand for switchover from mains power to backup power
only when main input voltage falls below a user defined threshold. The TPS25948xx devices provide a simple
solution for priority power multiplexing needs.
图 9-14 below shows a typical priority power multiplexing implementation using TPS259480x devices. When
primary (priority) power source (IN1) is present and within the valid range (not in UV/OV condition), the primary
path device path powers the OUT bus irrespective of whether auxiliary supply voltage (VIN2) is greater than,
equal to or less than primary supply voltage (VIN1). The device in auxiliary path is held in off condition by forcing
its OVLO pin to high using the SPLYGD signal from the primary path device.
Once the primary supply voltage falls outside the user-defined valid operating range (UV/OV condition), the
primary path device de-asserts the SPLYGD which signals the auxiliary path device to turn on and the system
starts operating from the auxiliary supply. During this transition, the auxiliary path device bypasses its dVdt
limited startup and performs a fast recovery to start delivering power within tSWOV
.
When the primary supply is restored, the primary path device turns on fully at a defined slew rate and then
asserts its SPLYGD pin high to turn the auxiliary path device off, allowing a seamless transition from auxiliary to
the primary supply with minimal output voltage droop and with no shoot-through current.
A key consideration in power MUXing applications is the minimum voltage the output bus droops to during the
switchover from one supply to another. This in turn depends on multiple factors including the output load current
(ILOAD), output bus hold-up capacitance (COUT) and switchover time (tSW).
While switching from primary supply (VIN1) to auxiliary supply (VIN2), the minimum bus voltage can be calculated
using 方程式 15. Here, the switchover time (tSW) is equal to the fast OVLO recovery time (tSWOV) taken by the
TPS259480x variants to turn on fully and start delivering current to the load.
tSW (µs) × ILOAD (A)
VOUT,min (V) = min (VIN1, VIN2) ‐
(15)
COUT (µF)
While switching from auxiliary supply (VIN2) to primary supply (VIN1), the minimum bus voltage can be calculated
using 方程式 16. Here the maximum switchover time is equal to the RCB recovery time (tSWRCB), depending on
whether VIN1 is equal to or lower than VIN2 to start with.
tSWRCB (µs) × ILOAD (A)
VOUT,min (V) = min (VIN1, VIN2) ‐ VFWDTH (V) ‐
(16)
COUT (µF)
The SPLYGD pins of the devices can be used as a digital indication to identify which of the 2 supplies is active
and delivering power to the load.
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IN
OUT
VIN1
VOUT
VLOGIC
COUT
EN/UVLO
TPS259480x
FLT
OVLO
ITIMER dVdt
IN1 supply active
SPLYGD
GND
ILM
IN
OUT
VIN2
VLOGIC
EN/UVLO
TPS259480x
FLT
IN2 supply active
SPLYGD
ITIMER dVdt
OVLO
GND
ILM
图9-14. Priority Power MUXing with 2 × TPS259480x - Option 1
This configuration provides the most compact priority power MUXing solution with multiple benefits, including
active current limit protection on both channels as well as overvoltage protection on primary channel. It also
provides the fastest switchover time from primary to auxiliary, but at the cost of a slightly increased quiescent
current on the auxiliary path while primary path is active. Also, it uses the fewest external components, but at the
cost of bypassing overvoltage protection on auxiliary channel.
The following waveforms illustrate the TPS259480x performance in a priority power MUXing configuration.
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图9-15. TPS259480x Power MUX - Switchover between Primary and Auxiliary Supplies
图9-16. TPS259480x Power MUX - Switchover between Primary and Auxiliary Supplies
There's a possible variation to the above configuration in case overvoltage protection is needed on both
channels. This needs an additional signal N-FET to drive the OVLO pin of the auxiliary path device as shown in
图9-17 below. The switchover times are similar to the previous configuration.
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IN
OUT
VIN1
VOUT
VLOGIC
COUT
EN/UVLO
TPS259480x
FLT
OVLO
ITIMER dVdt
SPLYGD
IN1 supply active
GND
ILM
IN
OUT
VIN2
VLOGIC
EN/UVLO
TPS259480x
FLT
IN2 supply active
SPLYGD
OVLO
ITIMER dVdt
GND
ILM
图9-17. Priority Power MUXing with 2 × TPS259480x - Option 2
Another variation of the previous configuration ensures minimum quiescent current on the auxiliary chanel while
primary channel is active, but at the cost of additional N-FET to drive the EN/UVLO pin of auxiliary path device
as shown in 图9-18 below. At the same time, it has a higher switchover delay from primary to auxiliary supply as
compared to the previous configuration.
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IN
OUT
VIN1
VOUT
VLOGIC
COUT
EN/UVLO
TPS259480x
FLT
OVLO
ITIMER dVdt
IN1 supply active
SPLYGD
GND
ILM
IN
OUT
VIN2
VLOGIC
EN/UVLO
OVLO
TPS259480x
FLT
IN2 supply active
SPLYGD
ITIMER dVdt
GND
ILM
图9-18. Priority Power MUXing with 2 × TPS259480x - Option 3
While switching from a higher supply rail to lower supply rail, the minimum bus voltage can be calculated using
方程式 17. Here, the switchover time is equal to the time taken by the device to come out of reverse current
blocking state (tSWRCB).
tSWRCB (µs) × ILOAD (A)
VOUT,min (V) = min (VIN1, VIN2) ‐ VFWDTH (V) ‐
(17)
COUT (µF)
While switching from a lower supply rail to higher supply rail, the minimum bus voltage can be calculated using
方程式 18. Here, the switchover time (tSW) is the time taken by the device to turn on fully and start delivering
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current to the load, which is equal to the device turn-on time (tON), which in turn includes the turn-on delay (tD,ON
)
and rise time (tR) determined by the dVdt capacitor (CdVdt) and bus voltage.
tSW (µs) × ILOAD (A)
VOUT,min (V) = min (VIN1, VIN2) ‐
(18)
COUT (µF)
备注
1. Power MUXing can be done either between two similar rails (such as 12-V Primary & 12-V Aux,
3.3-V Primary & 3.3-V Aux) or between dissimilar rails (such as 12-V Primary & 5-V Aux or or vice
versa).
2. For power MUXing cases with skewed voltage combinations, care must be taken to design circuit
components on EN/OVLO pins for the lower voltage channel devices such that the Absolute
maximum ratings on those pins are not exceeded when higher voltage is present on the other
channel. Also, the dVdt pin capacitor rating should be chosen based on the highest of the 2
supplies. Refer to Recommended Operating Conditions table for more details.
9.6 Parallel Operation
Applications which need higher steady current can use 2 TPS25948x devices connected in parallel as shown in
图 9-19 below. In this configuration, the first device turns on initially to provide the inrush current limiting. The
second device is held in an OFF state by driving its EN/UVLO pin low using the SPLYGD signal of the first
device. Once the inrush sequence is complete, the first device asserts its SPLYGD pin high and turns on the
second device. The second device asserts its SPLYGD signal to indicate when it has turned on fully, thereby
indicating to the system that the parallel combination is ready to deliver the full steady state current.
Once in steady state, both devices share current nearly equally. There could be a slight skew in the currents
depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch.
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IN
OUT
VIN
VOUT
VLOGIC
COUT
EN/UVLO
TPS259480x
FLT
OVLO
ITIMER dVdt
SPLYGD
GND
ILM
IN
OUT
VLOGIC
EN/UVLO
TPS259480x
FLT
To downstream enable
SPLYGD
ITIMER dVdt
OVLO
GND
ILM
图9-19. Two Devices Connected in Parallel for Higher Steady State Current Capability
The waveforms below illustrate the behavior of the parallel configuration during start-up as well as during steady
state.
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图9-20. Parallel Devices Sequencing During Start-Up
图9-21. Parallel Devices Load Current During Steady State
9.7 USB PD Port Protection
End equipments like PC, Notebooks, Docking Stations, Monitors etc.. have USB PD ports which can be
configured as DFP (Source), UFP (Sink) or DRP (Source+Sink). TPS25948xx can be used to as a fully
integrated power path solution for USB PD ports as shown in 图9-22 below.
TPS25948xx provides all the basic protection functions needed on the USB power path e.g. overvoltage,
overcurrent and short-circuit protection along with monitoring and control. The linear ORing mechanism in
TPS25948xx ensures that there's no reverse current flowing from one power source to the other during fast or
slow ramp of either supply.
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VPP_HV = 5 V to 20 V
IN
OUT
OVLO
TPS259480x
ILM
dVdt
EN/UVLO
GND
FLT SPLYGD
VBUS = 5 V to 20V
CDVDT
PD Controller
5 V
PP_5V
VBUS
图9-22. USB PD Port Protection
9.8 Power Supply Recommendations
The TPS25948x devices are designed for a supply voltage range of 3.5 V ≤ VIN or VOUT ≤ 23 V. An input
ceramic bypass capacitor higher than 0.1 μF is recommended if the input supply is located more than a few
inches from the device. The power supply must be rated higher than the set current limit to avoid voltage droops
during overcurrent and short-circuit conditions.
9.8.1 Transient Protection
In the case of a short-circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
• Minimize lead length and inductance into and out of the device.
• Use a large PCB GND plane.
• Connect a Schottky diode from the OUT pin ground to absorb negative spikes.
• Connect a low ESR capacitor larger than 1 μF at the OUT pin very close to the device.
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• Use a low-value ceramic capacitor CIN = 1 μF to absorb the energy and dampen the transients. The
capacitor voltage rating should be atleast twice the input supply voltage to be able to withstand the positive
voltage excursion during inductive ringing.
The approximate value of input capacitance can be estimated with the equation:
LIN
CIN
VSPIKE(ABSOLUTE) = VIN +ILOAD ×
(19)
where
– VIN is the nominal supply voltage.
– •ILOAD is the load current.
– LIN equals the effective inductance seen looking into the source.
– CIN is the capacitance present at the input.
• Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients
from exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude
of the transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive
energy dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which
can couple to the internal control circuits and cause unexpected behavior.
• For applications such as USB-C ports where a powered cable can be plugged to the output of the device,
there could be excess voltage stress from OUT to IN which exceeds the absolute maximum rating of the
device. It's recommended to add a TVS diode from OUT to IN to clamp the voltage to a safe level.
The circuit implementation with optional protection components is shown in 图9-23.
VOUT
VIN = 2.7 to 23 V
IN
OUT
R1
R2
COUT
D2
EN/UVLO
TPS259480x
SPLYGD
FLT
CIN
D1
OVLO
ITIMER dVdt
GND
ILM
R3
RILM
CITIMER
CDVDT
图9-23. Circuit Implementation with Optional Protection Components
9.8.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
•Source bypassing
•Input leads
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•Circuit layout
•Component selection
•Output shorting method
•Relative location of the short
•Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
9.9 Layout
9.9.1 Layout Guidelines
• For all applications, a ceramic decoupling capacitor of 0.1 μF or greater is recommended between the IN
terminal and GND terminal.
• The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC.
• High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
• The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible
trace. The PCB ground must be a copper plane or island on the board. It's recommended to have a separate
ground plane island for the eFuse. This plane doesn't carry any high currents and serves as a quiet ground
reference for all the critical analog signals of the eFuse. The device ground plane should be connected to the
system power ground plane using a star connection.
• The IN and OUT pads are used for heat dissipation. Connect to as much copper area on top and bottom PCB
layers using as possible with thermal vias. The vias under the device also help to minimize the voltage
gradient accross the IN and OUT pads and distribute current unformly through the device, which is essential
to achieve the best on-resistance and current sense accuracy.
• Locate the following support components close to their connection pins:
– RILM
– CdVdT
– CITIMER
– Resistors for the EN/UVLO and OVLO pins
• Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the RILM, CITIMER and CdVdt components to the device must be as short as possible to reduce
parasitic effects on the current limit , overcurrent blanking interval and soft start timing. It's recommended to
keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. These traces must not have
any coupling to switching signals on the board.
• Since the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB
routing of this node must be kept away from any noisy (switching) signals.
• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, a protection Schottky diode is recommended to address negative transients due to
switching of inductive loads. It's also recommended to add a ceramic decoupling capacitor of 1 μF or greater
between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to
minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin and the GND
terminal of the IC.
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9.9.2 Layout Example
Inner GND layer
Top Power layer
Bo om Power layer
OUT
IN
OUT
IN
1
图9-24. Layout Example
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• TPS25948EVM eFuse Evaluation Board
• TPS25948x Design Calculator
• Application brief - eFuses for USB Type-C protection
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
11.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
PTPS259840AYWPR
PTPS259842LYWPR
TPS259840AYWPR
TPS259840LYWPR
TPS259841AYWPR
TPS259841LYWPR
TPS259842AYWPR
TPS259842LYWPR
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YWP
YWP
YWP
YWP
YWP
YWP
YWP
YWP
12
12
12
12
12
12
12
12
3000
3000
3000
3000
3000
3000
3000
3000
180
180
180
180
180
180
180
180
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.88
1.88
1.88
1.88
1.88
1.88
1.88
1.88
2.59
2.59
2.59
2.59
2.59
2.59
2.59
2.59
0.53
0.53
0.53
0.53
0.53
0.53
0.53
0.53
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
Length (mm) Width (mm)
Height (mm)
PTPS259840AYWPR
PTPS259842LYWPR
TPS259840AYWPR
TPS259840LYWPR
TPS259841AYWPR
TPS259841LYWPR
TPS259842AYWPR
TPS259842LYWPR
DSBGA
YWP
YWP
YWP
YWP
YWP
YWP
YWP
YWP
12
12
12
12
12
12
12
12
3000
182
182
182
182
182
182
182
182
182
182
182
182
182
182
182
182
20
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
3000
3000
3000
3000
3000
3000
3000
20
20
20
20
20
20
20
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS259480AYWPR
PTPS259482LYWPR
ACTIVE
ACTIVE
DSBGA
DSBGA
YWP
YWP
12
12
3000
3000
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
Samples
Samples
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
Addendum-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
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