PTPS25990ARQPR_技术文档

TPS25990

ZHCSOF7B –SEPTEMBER 2022 –REVISED JUNE 2023

TPS25990 带PMBus^®数字遥测的2.9V – 16V、0.79mΩ、60A 可堆叠电子保险丝

1 特性

2 应用

• 输入工作电压范围：2.9 V 至16 V

• 服务器和高性能计算

• 网络接口卡

– 输入端的绝对最大值为20V

• 显卡和硬件加速器卡

• 数据中心交换机和路由器

• 输入热插拔

– 输出端可耐受高达-1V 的负电压

• 集成低导通电阻FET：0.79mΩ（典型值）

– 额定电流为50A RMS 和60A 峰值电流

• 可用作独立电子保险丝或在并联配置中用作主控制

器

• 风扇托盘

3 说明

– 支持多个电子保险丝并行连接，从而支持更高的

电流

– 启动和稳态期间的主动器件状态同步和负载共

TPS25990 是采用小型封装的集成式大电流电路保护和

电源管理器件。该器件只需很少的外部元件即可提供多

种保护模式，能够非常有效地抵御过载、短路和过多浪

涌电流。

享，可实现巨大的可扩展性

• 用于遥测、控制、配置和调试的PMBus® 接口

集成的 PMBus® 接口允许主机控制器实时监测、控制

和配置系统。关键系统参数可以通过远程遥测进行回

读。各种保护、警告阈值和系数可通过 PMBus® 进行

配置或存储在非易失性配置存储器中。黑盒故障记录功

能有助于调试现场故障和退货。

– P_IN/E_IN/V_IN/V_OUT/I_IN/温度/故障监控

– 使用单个命令进行下电上电

– 片上非易失性配置存储器

– 多个事件的黑盒故障记录，具有相对时间戳和存

储在外部EEPROM 上的选项

• 强大的过流保护

该器件可用作独立电子保险丝，也可作为并联电子保险

丝配置中的主控制器进行连接，以支持更高的电流。所

有器件在启动和稳态期间均主动同步其运行状态并共享

电流，以避免某些器件上出现过载情况而导致并行链过

早关闭或部分关闭。

– 可编程过流阈值(I_OCP)：7 A 至50 A，精度为

±5%（最大）

– 稳态期间的断路器响应，具有可编程瞬态消隐计

时器(OC_TIMER)，可支持峰值负载电流

封装信息

封装⁽¹⁾

– 启动期间运行模式下的有效电流限制(I_LIM

)

器件型号

封装尺寸

• 强大的短路保护

TPS25990ARQPR

RQP (QFN, 26)

4.50mm × 5.00mm

– 快速跳变响应(280ns)

– 可编程阈值和固定阈值

– 不受电源线路瞬变影响- 无干扰性跳变

• 可编程过热保护(OTP)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

TPS25990x

ADDR0

SCL

SDA

– 确保FET SOA：8W√s

• 集成式FET 运行状况监测和报告

ADDR1

AUX

SDA

SMBA#

LOAD

IN

OUT

IREF/DAC2

TEMP/CMP

SUPPLY

VDD

• 精确的模拟负载电流监控(IMON)

IMON

EN/UVLO

EN

PG

– ±2% 精度

PG

SWEN

FLT

GND

ILIM

DVDT

– 模拟带宽大于500kHz

• 快速过压保护，具有可编程

TPS25985x

IN

OUT

IREF

TEMP

IMON

VDD

阈值

EN/UVLO

PG

FLT

• 可编程输出转换率控制(dVdt)

• 可编程插入延迟计时器

• 可编程欠压锁定(UVLO)

• 模拟芯片温度监测器输出(TEMP)

• 4 个可配置通用I/O 引脚

SWEN

MODE GND

ILIM

DVDT

TPS25985x

IN

OUT

IREF

TEMP

IMON

VDD

EN/UVLO

SWEN

PG

FLT

• 小尺寸：QFN 封装（4.5mm × 5mm，间距为

0.6mm）

MODE GND ILIM DVDT

– 电源引脚和GND 引脚之间的间隙为29mil

• 100% 无铅

简化原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSGG4

TPS25990

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ZHCSOF7B –SEPTEMBER 2022 –REVISED JUNE 2023

Table of Contents

8.1 Overview...................................................................28

8.2 Functional Block Diagram.........................................29

8.3 Feature Description...................................................29

8.4 Device Functional Modes........................................117

9 Application and Implementation................................ 118

9.1 Application Information............................................118

9.2 Typical Application: 12-V, 4-kW Power Path

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings........................................ 7

7.2 ESD Ratings............................................................... 7

7.3 Recommended Operating Conditions.........................8

7.4 Thermal Information....................................................8

7.5 Electrical Characteristics.............................................9

7.6 Logic Interface DC Characteristics........................... 12

7.7 Telemetry.................................................................. 12

7.8 PMBus Interface Timing Characteristics...................15

7.9 External EEPROM Interface Timing

Protection with PMBus^®Interface in Datacenter

Servers......................................................................124

9.3 Best Design Practices.............................................133

9.4 Power Supply Recommendations...........................134

9.5 Layout..................................................................... 135

10 Device and Documentation Support........................138

10.1 Documentation Support........................................ 138

10.2 接收文档更新通知................................................. 138

10.3 支持资源................................................................138

10.4 Trademarks...........................................................138

10.5 静电放电警告........................................................ 138

10.6 术语表................................................................... 138

11 Mechanical, Packaging, and Orderable

Characteristics.............................................................15

7.10 Timing Requirements..............................................16

7.11 Switching Characteristics........................................17

7.12 Typical Characteristics............................................18

8 Detailed Description......................................................28

Information.................................................................. 138

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (September 2022) to Revision B (June 2023)

Page

• 将器件状态从预告信息更改为量产数据 ............................................................................................................ 1

• 更新了器件说明.................................................................................................................................................. 1

• Revised the graphs and experimental waveforms in typical characteristics.....................................................18

• Updated the functional block diagram.............................................................................................................. 29

• Updated the feature description........................................................................................................................29

• Deleted the WRITE_PROTECT (10h) register................................................................................................. 53

• Added the MFR_WRITE_PROTECT (F8h) register......................................................................................... 53

• Deleted the EEPROM_DET_CMD (F4h) register.............................................................................................53

• Changed the STATUS_MFR_SPECIFIC_2 register command code from 7Fh to F3h ....................................53

• Changed the SMBus transaction type of STATUS_MFR_SPECIFIC_2 register from Read Byte to Read Word

..........................................................................................................................................................................53

• Updated the default value of the MFR_REVISION (9Bh) register from 0x61 to 0x01 ..................................... 53

• Changed the READ_BB_EEPROM register command code from BCh to F4h ...............................................53

• Changed the CABLE_RESISTANCE register command name to CABLE_DROP ..........................................53

• Deleted the MFR_SPECIFIC_RESERVED (B0h) register................................................................................53

• Revised the bit definitions of the STATUS_BYTE (78h), STATUS_WORD (79h), STATUS_IN (7Ch),

STATUS_IOUT (7Bh), STATUS_TEMP (7Dh), STATUS_MFR_SPECIFIC (80h), STATUS_MFR_SPECIFIC_2

(F3h), STATUS_CML (7Eh), DEVICE_CONFIG (E4h), ADC_CONFIG_2 (E9h), ALERT_MASK (DBh)

registers............................................................................................................................................................53

• Revised the Blackbox timestamp tick interval................................................................................................ 101

• Revised the overcurrent blanking timer values...............................................................................................102

• Revised the retry delay timer values.............................................................................................................. 103

• Revised the insertion delay timer values.........................................................................................................111

• Revised the ADC sampling frequency from 500 KSPS to 460 KSPS.............................................................112

• Added high performance ADC sampling mode...............................................................................................112

2

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• Updated the m, b, R coefficients used in DIRECT format conversion............................................................ 114

• A minor modification to the application schematic..........................................................................................124

• Revised the application performance plots.....................................................................................................132

5 说明（续）

集成的快速、准确检测模拟负载电流监测器有助于进行预测性维护，并且先进的动态平台电源管理技术（如Intel^®

PSYS 和 PROCHOT）可更大限度地提高系统吞吐量和电源利用率。这与集成的数字示波器功能和黑盒相结合，

有助于在关键系统中进行预测性维护。

此类器件的额定工作结温范围为–40°C 至+125°C。

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6 Pin Configuration and Functions

14

13

22

VIN

23

VOUT

26

1

10

9

图6-1. TPS25990 RQP Package 26-pin QFN Top View

表6-1. Pin Functions

TYPE

DESCRIPTION

NAME

NO.

PMBus device I2C address configuration pin. Pin strap options to generate

different address combinations in conjunction with ADDR0. Refer to 节8.3.14.1

for more details.

ADDR1

1

O

I

PMBus device I2C address configuration pin. Pin strap options to generate

different address combinations in conjunction with ADDR1. Refer to 节8.3.14.1

for more details.

ADDR0

AUX

2

3

4

Auxiliary ADC input channel which can be used to monitor external analog

signal through PMBus. Also functions as analog input for fast comparator with

internal programmable threshold.

Start-up output slew rate control pin. Leave this pin open to allow fastest start-

up. Connect capacitor to ground to slow down the slew rate to manage inrush

current. Refer to 节8.3.4.1 for more details.

DVDT

O

4

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ZHCSOF7B –SEPTEMBER 2022 –REVISED JUNE 2023

表6-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

Dual function pin (digitally configurable)

1. Die junction temperature monitor analog voltage output. Can be tied

together with TEMP outputs of multiple devices in a parallel configuration to

indicate the peak temperature of the chain. Refer to 节8.3.8 for more

details.

TEMP/CMP

5

I/O

2. Analog input for fast comparator with internal programmable threshold.

Refer to 节8.3.12 for more details.

Programmable General Purpose DAC analog current output. Refer to 节

8.3.14.9 for more details.

DAC1

IMON

6

7

I/O

O

An external resistor from this pin to GND sets the overcurrent protection

threshold and fast-trip threshold during steady-state. This pin also acts as a fast

and accurate analog output load current monitor signal during steady-state. Do

not leave floating. Refer to 节8.3.6 for more details.

An external resistor from this pin to GND sets the current limit threshold and

fast-trip threshold during start-up. This also sets the active current sharing

threshold during steady-state. Do not leave floating. Refer to 节8.3.4.3 for more

details.

ILIM

8

O

Dual function pin (digitally configurable)

1. Programmable reference voltage for overcurrent, short-circuit protection

and active current sharing blocks. Generated using internal DAC. Refer to

IREF/DAC2

9

I/O

节8.3.4.2 for more details.

2. Programmable analog voltage output generated using internal general-

purpose DAC. Refer to 节8.3.14.9 for more details.

Power output. Must be soldered to output power plane uniformly to ensure

proper heat dissipation and to maintain optimal current distribution through the

device.

OUT

10, 11, 12, 13

P

GND

14

15

16

G

Device ground reference pin. Connect to system ground.

SDA

I/O

I2C data line for PMBus interface. Refer to 节8.3.14 for more details.

I2C clock line for PMBus interface. Refer to 节8.3.14 for more details.

SCL

GPIO4/SMBA#/

General purpose digital I/O pin. Can be configured for various functions through

PMBus. Refer to 节8.3.14.7.1.59 register for more details. Default function is

SMBus Alert output.

COMP1/COMP2/

EEDATA/EECLK

17

18

19

I/O

I

Active high enable input. Connect resistor divider from input supply to set the

undervoltage threshold. Do not leave floating.

EN/UVLO

GPIO1/PG/

General purpose digital I/O pin. Can be configured for various functions through

PMBus. Refer to 节8.3.14.7.1.58 register for more details. Default function is

Power-Good output (PG) indication. Refer to 节8.3.10.2 for more details.

COMP1/COMP2/

EEDATA/EECLK

I/O

GPIO2/FLT/

General purpose digital I/O pin. Can be configured for various functions through

PMBus. Refer to 节8.3.14.7.1.58 register for more details. Default function is

Fault output (FLT) indication. Refer to 节8.3.10.1 for more details.

COMP1/COMP2/

EEDATA/EECLK

20

21

22

I/O

P

General purpose digital I/O pin. Can be configured for various functions through

PMBus. Refer to 节8.3.14.7.1.59 register for more details. Default pin function

is set to SWEN, which is used to synchronize multiple eFuses in a parallel

configuration. Refer to 节8.3.10.3 for more details.

GPIO3/SWEN/

COMP1/COMP2/

EEDATA/EECLK

Controller power input pin. Can be used to power the internal control circuitry

with a filtered and stable supply which is not affected by system transients.

Connect this pin to VIN through a series resistor and add a decoupling capacitor

to GND.

VDD

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表6-1. Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NO.

Power input. Must be soldered to input power plane uniformly to ensure proper

heat dissipation and to maintain optimal current distribution through the device.

IN

23, 24, 25, 26

P

6

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

Parameter

MIN

–0.3

–1

MAX

UNIT

V

V_INMAX

Maximum Input Voltage Range

Maximum Supply Voltage Range

IN

20

V_DDMAX

VDD

OUT

20

V

V_OUTMAXMaximum Output Voltage Range

V_ENMAXMaximum Enable Pin Voltage Range

V_IREFMAXMaximum IREF/DAC2 Pin Voltage Range

I_IREFMAXMaximum IREF/DAC2 Pin Current

Min(20, V_IN+ 0.3)

V

EN/UVLO

IREF/DAC2

AUX

20

5.5

10

V

mA

V

V_AUXMAXMaximum AUX Pin Voltage Range

V_DVDTMAXMaximum DVDT Pin Voltage Range

5.5

DVDT

Internally Limited

V

V_I2CMAX

Maximum I2C Signal Pin Voltage Range

SCL, SDA

GPIO1/2/3/4

IREF/DAC2

ADDR0/1

DAC1

5.5

10

V

V_GPIOMAXMaximum GPIO Pin Voltage Range

I_GPIOMAXMaximum GPIO Pin Sink Current

V_DAC2MAXMaximum DAC2 Output Voltage Range

V_ADDRMAXMaximum ADDR0/1 Pin Voltage Range

I_ADDRMAXMaximum ADDR0/1 Pin Sink Current

V

mA

V

Internally Limited

V

µA

I_DAC1MAXMaximum DAC1 Pin Current

Internally Limited

mA

V_TEMPMAXMaximum TEMP/CMP Pin Voltage Range

V_ILIMMAXMaximum ILIM pin voltage

TEMP/CMP

ILIM

5.5

V

Internally Limited

V_IMONMAXMaximum IMON pin voltage

IMON

V

I_MAX

Maximum Continuous Switch Current

Junction temperature

IN to OUT

A

T_JMAX

T_LEAD

T_STG

°C

Maximum Soldering Temperature

Storage temperature

300

150

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/

JEDEC JS-002⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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MAX UNIT

ZHCSOF7B –SEPTEMBER 2022 –REVISED JUNE 2023

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

Parameter

MIN

V_IN

Input Voltage Range

IN

2.9

16

V

Supply Voltage Range (with in-system NVM programming

support)

V_DD

VDD

10

Supply Voltage Range (without in-system NVM

programming support)

V_DD

VDD

OUT

4.5

16

V_IN

V

V_OUT

Output Voltage Range

V_EN/

Enable Pin Voltage Range

EN/UVLO

Min(V_DD+ 1, V_IN+ 1)

UVLO

V_DVDT

V_I2C

DVDT Pin Cap Voltage Rating

I2C Pull-up Voltage Range

I2C Parasitic Capacitance

GPIOx Pin Pull-up Voltage Range

IREF Pin Voltage Range

DVDT

4

V

SCL, SDA

GPIO1/2/3/4

IREF/DAC2

ILIM

1.8

5

200

5

C_I2C

pF

V

V_GPIO

V_IREF

V_ILIM

V_IMON

0.3

1.2

0.4

1.2

V

ILIM Pin Voltage Range

V

IMON Pin Voltage Range

IMON

V

V_TEMPC

TEMP/CMP Pin Voltage Range

TEMP/CMP

1.2

V

MP

V_AUX

I_MAX

I_{MAX, PLS}

T_J

AUX Pin Voltage Range

AUX

1.2

50

V

A

IN to OUT

RMS Switch Current, T_J≤125 ℃

Peak Output Current with 20% duty cycle, T_J≤125 ℃

Junction temperature

60

A

125

°C

–40

7.4 Thermal Information

TPS25990X

RQP (QFN)

26 PINS

19.9

THERMAL METRIC^{(1) (2)}

UNIT

R_θJA

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

°C/W

0.2

4.2

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Based on simulations conducted with the device mounted on a JEDEC 8-layer PCB (4s4p)

English Data Sheet: SLVSGG4

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7.5 Electrical Characteristics

(Test conditions unless otherwise noted) –40°C ≤T_J≤125°C, V_IN= 12 V, VDD = 12 V, OUT = Open, V_EN/UVLO= 2 V,

SWEN = 10 kΩ pull-up to 5 V, R_ILIM= 550 Ω, R_IMON= 1.1 kΩ, DVDT = Open, FLT = 10 kΩ pull-up to 5 V, PG = 10 kΩ pull-up

to 5 V, TEMP = Open, ADDR0 = Open, ADDR1 = Open, SCL, SDA and SMBA# pulled up to 3.3 V. All voltages referenced to

GND.

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

INPUT SUPPLY (VDD)

V_DD

VDD input operating voltage range

VDD ON state quiescent current

VDD OFF state current

4.5

16

V

I_QON(VDD)

I_QOFF(VDD)

I_SD(VDD)

3.7

4

5.5 mA

V_VDD> V_UVP(R), V_EN≥V_UVLO(R)

V_SD(R)< V_EN< V_UVLO(F)

V_EN< V_SD(F)

VDD shutdown current

6

4.5

4.4

mA

V

V_UVP(R)

VDD undervoltage protection threshold

VDD Rising

4

4.26

V_UVP(F)

VDD Falling

3.9 4.07

V

INPUT SUPPLY (IN)

V_IN

VIN input operating voltage range

V_INundervoltage protection threshold

2.9

16

V

V_UVPIN(R)

2.71 2.81 2.91

2.59 2.59 2.60

V_UVPIN(F)

VIN Rising, VIN_UV_FLT = 0x8D (Default

register value)

10.8

V_UVLOIN(R)

V_UVLOIN(F)

V_INundervoltage protection threshold

11.02 11.17

2

V

VIN Falling, VIN_UV_FLT = 0x8D (Default

register value)

10.5

2

10.9

7

10.78

I_QON(IN)

I_QOFF(IN)

I_SD(IN)

IN ON state quiescent current

IN OFF state current

2.6

2.7

3.5 mA

V_EN≥V_UVLO(R)

V_SD(R)< V_EN< V_UVLO(F)

V_EN< V_SD(F)

IN shutdown current

ENABLE / UNDERVOLTAGE LOCKOUT (EN/UVLO)

EN/UVLO pin voltage threshold for turning

V_UVLO(R)

EN/UVLO Rising

EN/UVLO Falling

1.12

1.2 1.28

1.1 1.18

V

on, rising

EN/UVLO pin voltage threshold for turning

off and engaging QOD, falling

V_UVLO(F)

1.02

0.6

V

V_SD(F)

I_ENLKG

Shutdown threshold

EN/UVLO Falling

EN/UVLO pin leakage current

V_EN< Min(V_IN+ 1 V, V_DD+ 1 V)

0.1 µA

OVERVOLTAGE PROTECTION (IN)

VIN_OV_FLT = 0x0E (Default setting), V_IN

rising

16.3

9

17.0

V_OVP(R)

V_OVP(F)

V_OVP(R)

V_OVP(F)

V_INovervoltage protection threshold (rising)

16.73

V

8

VIN_OV_FLT = 0x0E (Default setting), V_IN

falling

V_INovervoltage protection threshold (rising)

16.1 16.48 16.8

13.3

2

14.1

5

V_INovervoltage protection threshold (rising) VIN_OV_FLT = 0x0B, V_INrising

V_INovervoltage protection threshold (falling) VIN_OV_FAULT = 0x0B, V_INfalling

13.74

13.8

9

13.1 13.49

V_OVP(R)

V_OVP(F)

ON-RESISTANCE (IN - OUT)

V_INovervoltage protection threshold (falling) VIN_OV_FAULT = 0x01, V_INrising

3.77 3.94 4.15

3.53 3.69 3.86

V_INovervoltage protection threshold (falling) VIN_OV_FAULT = 0x01. V_INfalling

R_ON

ON resistance

0.79 1.05

1.4

T_J= 25 ℃

mΩ

T_J= –40 to 125 ℃

OUTPUT CURRENT MONITOR AND OVERCURRENT PROTECTION (IMON)

17.8

7

18.5

5

G_IMON

Current Monitor Gain (IMON:IOUT)

IMON pin leakage/offset current

Device in steady state (PG asserted)

18.18

µA/A

I_LKG(IMON)

1.1 uA

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7.5 Electrical Characteristics (continued)

(Test conditions unless otherwise noted) –40°C ≤T_J≤125°C, V_IN= 12 V, VDD = 12 V, OUT = Open, V_EN/UVLO= 2 V,

SWEN = 10 kΩ pull-up to 5 V, R_ILIM= 550 Ω, R_IMON= 1.1 kΩ, DVDT = Open, FLT = 10 kΩ pull-up to 5 V, PG = 10 kΩ pull-up

to 5 V, TEMP = Open, ADDR0 = Open, ADDR1 = Open, SCL, SDA and SMBA# pulled up to 3.3 V. All voltages referenced to

GND.

PARAMETER

TEST CONDITIONS

R_IMON= 1.1 kΩ, V_IREF= 1 V

R_IMON= 1.1 kΩ, V_IREF= 0.5 V

R_IMON= 1.1 kΩ, V_IREF= 0.3 V

R_IMON= 7.87 kΩ, V_IREF= 0.1 V

MIN TYP MAX UNIT

48.3

24

50 51.7

25 26

15 15.6

A

Steady-state overcurrent protection (Circuit-

Breaker) threshold

I_OCP

14.4

6.72

7

7.28

CURRENT LIMIT (ILIM)

17.8

7

18.5

5

G_ILIM(LIN)

Current Monitor Gain (ILIM:IOUT) vs. IOUT. Device in steady state (PG asserted)

18.18

23.33

µA/A

%

Ratio of start-up current limit reference to

CL_REF(SAT)

steady-state circuit-breaker reference

threshold

V_OUT> V_FB, PG not asserted

28

35 43.5

14 18.2

A

R_ILIM= 314 Ω, V_IREF= 1.182 V, V_OUT> V_FB

R_ILIM= 1.1 kΩ, V_IREF= 1.182 V, V_OUT> V_FB

9.8

I_LIM

Start-up current limit regulation threshold

R_ILIM= 1.54 kΩ, V_IREF= 1.182 V, V_OUT

V_FB

>

7

10

13

A

V

V_FB

Foldback voltage

1.5

2.0

2.5

CURRENT LIMIT REFERENCE (IREF/DAC2)

VIREF = 0x32

(Default), DEVICE_CONFIG[6] = 0

0.99

0.29

1.0 1.01

0.3 0.31

V

Current Limit Reference DAC output

voltage

VIREF

VIREF = 0x00, DEVICE_CONFIG[6] = 0

VIREF = 0x3F, DEVICE_CONFIG[6] = 0

V

1.17 1.182 1.19

DAC2 OUTPUT (IREF/DAC2)

GPDAC2 = 0x00, DEVICE_CONFIG[6] = 1

GPDAC2 = 0x1F, DEVICE_CONFIG[6] = 1

GPDAC2 = 0x3F, DEVICE_CONFIG[6] = 1

291 300 308 mV

725 733 742 mV

1174 1180 1189 mV

VDAC2

General purpose DAC 2 output voltage

DAC1 OUTPUT

GPDAC1[6:0] = 0000000b

GPDAC1[6:0] = 0011111b

5.66 5.98 6.28 µA

27.7

2

30.5

7

29.21

53.19

µA

IDAC1

General purpose DAC 1 sink current

50.5

2

55.5

6

GPDAC1[6:0] = 0111111b

GPDAC1[6:0] = 1xxxxxxb

0.05 µA

SHORT-CIRCUIT PROTECTION

158.

A

I_FFT

Fixed fast-trip threshold

PG asserted High

90 113.2

8

DEVICE_CONFIG[12:11] = 11

DEVICE_CONFIG[12:11] = 10

DEVICE_CONFIG[12:11] = 01

DEVICE_CONFIG[12:11] = 00

225

200

175

150

%

Scalable fast-trip threshold (IMON) to

overcurrent protection threshold reference

(IREF) ratio during steady-state

SFT_REF(LIN)

Scalable fast-trip threshold (ILIM) to

overcurrent protection threshold reference

(IREF) ratio during inrush

SFT_REF(SAT)

50

%

ACTIVE CURRENT SHARING

Maximum R_ONduring steady-state active

current sharing

R_ON(ACS)

V_ILIM> CL_REF(ACS)%× V_IREF

1

1.81

mΩ

English Data Sheet: SLVSGG4

10

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7.5 Electrical Characteristics (continued)

(Test conditions unless otherwise noted) –40°C ≤T_J≤125°C, V_IN= 12 V, VDD = 12 V, OUT = Open, V_EN/UVLO= 2 V,

SWEN = 10 kΩ pull-up to 5 V, R_ILIM= 550 Ω, R_IMON= 1.1 kΩ, DVDT = Open, FLT = 10 kΩ pull-up to 5 V, PG = 10 kΩ pull-up

to 5 V, TEMP = Open, ADDR0 = Open, ADDR1 = Open, SCL, SDA and SMBA# pulled up to 3.3 V. All voltages referenced to

GND.

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

IMON:IOUT ratio during active current

sharing

PG asserted High, V_ILIM> CL_REF(ACS)%

V_IREF

×

18.7

G_IMON(ACS)

18.0 18.36

36.67

µA/A

%

7

Ratio of active current sharing trigger

threshold to steady state overcurrent

protection threshold

CL_REF(ACS)

PG asserted High

INRUSH CURRENT PROTECTION (DVDT)

DEVICE_CONFIG[10:9] = 11

DEVICE_CONFIG[10:9] = 10

DEVICE_CONFIG[10:9] = 01

DEVICE_CONFIG[10:9] = 00

2.38

1.4

1

3

2

4

µA

2.9 µA

µA

I_DVDT

dVdt pin charging current

1.5

1

2

0.79

1.33 µA

G_DVDT

R_DVDT

GHI

dVdt gain

20.7

510

V/V

dVdt pin to GND discharge resistance

Ω

R_ON(GHI)

R_ONwhen PG is asserted

1

1.81

mΩ

QUICK OUTPUT DISCHARGE (QOD)

Quick output discharge internal pull-down

current on OUT

OVERTEMPERATURE PROTECTION (OTP)

I_QOD

V_SD(F)< V_EN< V_UVLO(F)

10.8 22.1

38 mA

TSD

Thermal shutdown threshold

Thermal shutdown hysteresis

T_JRising

T_JFalling

149

11

°C

TSD_HYS

TEMPERATURE SENSOR OUTPUT (TEMP/CMP)

mV/

℃

G_TMP

TEMP sensor gain

2.58 2.65 2.72

V_TMP

TEMP pin output voltage

TEMP pin sourcing current

TEMP pin sinking current

672 678 685 mV

75 93.4 115.6 µA

T_J= 25 ℃

I_TMPSRC

I_TMPSNK

7.6

10

14 µA

COMPARATORS (TEMP/CMP, AUX)

I_CMPLKGTEMP/CMP input leakage current

I_AUXLKG

0 ≤V_TEMP/CMP≤1.2 V, TEMP/CMP pin

configured as comparator 1 input

1

µA

AUX input leakage current

0 ≤V_AUX≤1.2 V

VCMPXREF[3:0] = 0000

VCMPXREF[3:0] = 0011

VCMPXREF[3:0] = 0111

176 199.5 224 mV

476 501.8 524 mV

876 900.4 923 mV

1700.

V_CMP1REF

Comparator 1 reference voltage

VCMPXREF[3:0] = 1111

1676

1722 mV

4

VCMPXREF[7:4] = 0000

VCMPXREF[7:4] = 0011

VCMPXREF[7:4] = 0111

176 199.4 224 mV

476 500.1 524 mV

876 899.7 923 mV

1699.

V_CMP2REF

Comparator 2 reference voltage

VCMPXREF[7:4] = 1111

1677

1722 mV

2

FET HEALTH MONITOR

V_DSFLT

FET D-S Fault Threshold

SWEN = L

0.35 0.49 0.59

V

ADDRESS SELECT (ADDR0/1)

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7.5 Electrical Characteristics (continued)

(Test conditions unless otherwise noted) –40°C ≤T_J≤125°C, V_IN= 12 V, VDD = 12 V, OUT = Open, V_EN/UVLO= 2 V,

SWEN = 10 kΩ pull-up to 5 V, R_ILIM= 550 Ω, R_IMON= 1.1 kΩ, DVDT = Open, FLT = 10 kΩ pull-up to 5 V, PG = 10 kΩ pull-up

to 5 V, TEMP = Open, ADDR0 = Open, ADDR1 = Open, SCL, SDA and SMBA# pulled up to 3.3 V. All voltages referenced to

GND.

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

3.85 5.05 6.25 µA

ADDR0 pin pull-up current

ADDR1 pin pull-up current

I_ADDR

SINGLE POINT FAILURE (ILIM, IMON, IREF)

Back-up overcurrent protection threshold

I_{OC_BKP(LIN)}

65

55

90 131

90 112

A

(steady -state)

Back-up overcurrent protection threshold

(start-up)

I_{OC_BKP(SAT)}

7.6 Logic Interface DC Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

GPIOx

Pin configured as output, de-asserted

Low. Sink current = 20 mA.

V_OL

GPIOx output logic low

GPIOx output logic high

0.27

V

Pin configured as output, asserted

high

V_OH

1.7

V_IH

V_IL

GPIOx input logic high

GPIOx input logic low

Pin configured as input

1.65

V

0.75

13

Pin configured as output, de-asserted

Low

R_GPIO

GPIOx pin pull-down resistance

GPIOx pin leakage current

Ω

Pin configured as output, asserted

high

I_GPIOLKG

1

µA

PMBus (SCL/SDA)

C_PMB-BUS

PMBus Bus Capacitance

PMBus Pin Capacitance - SCL

PMBus Pin Capacitance - SDA

PMBus interface pull ups

SDA Input logic low

400

10

pF

V

C_PMB-PIN

10

V_{PULLUP_PMBus}

V_{IL_PMBus}

1.62

3.63

0.85

V

V_{IL_PMBus}

SCL Input logic low

V

V_{IH_PMBus}

SCL Input logic high

1.35

V

V_{IH_PMBus}

SDA Input logic high

V

V_{OL_PMBus}

Low-level output voltage - SCL

Low-level output voltage - SDA

I_OL= -20 mA

0.4

V

7.7 Telemetry

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Telemetry

ADC Resolution

10

bits

V

ADC Voltage reference (V_REF

Analog Input Range

)

1.95

0

V_REF

V

English Data Sheet: SLVSGG4

12

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7.7 Telemetry (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC normal mode (Default)

460

KHz

Sampling rate

DNL

ADC high performance mode

(DEVICE_CONFIG[3] = 1)

270

KHz

LSB

ADC normal mode (Default)

4

0.75

6

ADC high performance mode

(DEVICE_CONFIG[3] = 1)

ADC normal mode (Default)

INL

ADC high performance mode

(DEVICE_CONFIG[3] = 1)

2.9

ADC normal mode (Default), V_AUX= 1.95 V

(Full-scale), 1 sample

1.5

1

%FS

–1.5

–1

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_AUX= 1.95 V

(Full-scale), 1 sample

V_AUXAbsolute error

ADC normal mode (Default), V_AUX= 1.95 V

(Full-scale), 128 sample average

1

–1

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_AUX= 1.95 V

(Full-scale), 128 sample average

0.5

–0.5

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_IN= 12 V, 1

sample

1.5

0.75

1.5

0.75

10

%FS

–1.5

–0.75

–1.5

–0.75

–10

–8

V_INAbsolute error

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_IN= 12 V, 128

sample average

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_OUT= 12 V, 1

sample

V_OUTAbsolute error

V_TEMPAbsolute error

IMON Absolute error

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_OUT= 12 V,

128 sample average

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_TEMP= 1.95 V

(Full-scale) , 1 sample

℃

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_TEMP= 1.95 V

(Full-scale), 128 sample average

8

℃

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_IMON= 0.8 V, 1

sample

1

%FS

–1

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_IMON= 0.8 V,

128 sample average

0.5

2

–0.5

–2

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_IN= 12 V,

V_IMON= 1.95 V (Full-scale), 1 sample

P_INAbsolute error

ADC high performance mode

(DEVICE_CONFIG[3] = 1), V_IN= 12 V,

V_IMON= 1.95 V (Full-scale) , 128 sample

average

1.25

%FS

–1.25

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7.7 Telemetry (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC high performance mode

(DEVICE_CONFIG[3] = 1), Accumulated

energy over 5 ms interval, V_IN= 12 V,

V_IMON= 0.8 V

E_INabsolute error

2.5

%

–2.5

English Data Sheet: SLVSGG4

14

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7.8 PMBus Interface Timing Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

PMBus Timing Characteristics

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PMB_CLKR

t_PMB-BUF

PMBus clock frequency range

PMBus Clock Requirements

0.05

0.5

1.2

MHz

µs

PMBus Free time between STOP and

START conditions

t_PMB-HD-STA

t_PMB-SU-STO

t_PMB-HD-DAT

t_PMB-SU-DAT

t_PMB-TIMEOUT

t_PMB-LOW

Hold time after Repeated Start Condition

Stop condition Setup time

SDA Hold Time

0.26

0

µs

ns

ms

µs

ns

SDA Setup Time

50

SCLK low timeout

25

35

SCLK low time

0.5

0.26

t_PMB-HIGH

SCLK high time

50

300

120

1000

300

120

100 kHz Class

400 kHz Class

1000 kHz Class

100 kHz Class

400 kHz Class

1000 kHz Class

SDA/SCLK rise time

(V_IL(MAX)-150 mV to V_IH(MIN)+150 mV)

t_R-PMB

SDA/SCLK fall time,

(V_IH(MIN)+150 mV to V_IL(MAX)+ 150 mV)

t_F-PMB

7.9 External EEPROM Interface Timing Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EE Interface Timing Characteristics

EE_CLKR

EECLK clock frequency range

0.4

MHz

µs

t_EE-SU-STO

t_EE-HD-DAT

t_EE-SU-DAT

Stop condition Setup time

EEDATA Hold Time

0.26

0

µs

EEDATA Setup Time

50

ns

Hold time after (REPEATED) START

Condition

t_HD-STA

0.6

µs

t_EE-LOW

t_EE-HIGH

EECLK low time

EECLK high time

0.5

µs

0.26

50

EEDATA/EECLK rise time

(V_IL(MAX)-150 mV to V_IH(MIN)+150 mV)

t_R-EE

t_F-EE

400 kHz Class

300

ns

EEDATA/EECLK fall time,

(V_IH(MIN)+150 mV to V_IL(MAX)+ 150 mV)

300

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ZHCSOF7B –SEPTEMBER 2022 –REVISED JUNE 2023

7.10 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

t_OVP

Overvoltage protection response time

1.2

µs

V_IN> V_OVP(R)to SWEN↓

V_DD> V_UVP(R)to SWEN↑, INS_DLY =

0x00

14

ms

t_Insdly

Insertion delay

V_DD> V_UVP(R)to SWEN↑, INS_DLY =

0x07

560

Fixed Fast-Trip response time Hard

Short

t_FFT

267

343

377

ns

I_OUT> 1.3 × I_FFTto I_OUT

I_OUT> 3 × I_OCPto I_OUT

↓

t_SFT

Scalable Fast-Trip response time

↓

VCMP1THR = 1 V, V_TEMP/CMP> 1.2 ×

VCMP1THR to CMP1OUT↑

TEMP/CMP pin comparator (COMP1)

response time

t_CMP1

VCMP2THR = 1 V, V_AUX> 1.2 ×

VCMP1THR to CMP2OUT↑

AUX pin comparator (COMP2)

response time

t_CMP2

377

0

ns

ms

I_OUT= 1.3 × I_OCP, OC_TIMER = 0x00

I_OUT= 1.3 × I_OCP, OC_TIMER = 0x14

(Default)

t_{OC_TIMER}

Overcurrent blanking interval

2.1

I_OUT= 1.3 × I_OCP, OC_TIMER = 0xFF

RETRY_CONFIG[2:0] = 000

27.3

55

ms

µs

t_RETRY

Auto-Retry Interval

RETRY_CONFIG[2:0] = 111

6940

12.2

232

t_EN(DG)

t_{SU_TMR}

t_QOD

EN/UVLO de-glitch time

Start-up timeout interval

QOD enable timer

ms

SWEN↑to FLT↓

V_SD(F)< V_EN/UVLO< V_UVLO(F)

4.38

QOD discharge time (90% to 10% of

V_SD(F)< V_EN/UVLO< V_UVLO(F), V_IN= 12

V, C_OUT= 1 mF

t_Discharge

488

ms

V_OUT

)

DEVICE_CONFIG[15] = 0, Device in

steady state, V_OUT> VOUT_PGTH to

PG↑

t_PGA

PG assertion delay

98

µs

DEVICE_CONFIG[15] = 1, Device in

steady state, V_OUT> VOUT_PGTH to

PG↑

t_PGA

PG assertion delay

36.6

34

ms

µs

Device in steady state, V_OUT

<

t_PGD

PG De-assertion de-glitch

VOUT_PGTH to PG↓

English Data Sheet: SLVSGG4

16

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7.11 Switching Characteristics

The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn

on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin

to ground. As C_dVdtis increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt)

section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load

capacitance (C_OUT) and Load Resistance (R_L). The Switching Characteristics are only valid for the power-up

sequence where the supply is available in steady state condition and the load voltage is completely discharged before the

device is enabled. Typical values are taken at T_J= 25°C unless specifically noted otherwise. V_IN= 12 V, R_OUT= 500 Ω, C_OUT

= 1 mF

C_dVdt= 22 nF, C_dVdt= 22 nF, C_dVdt= 22 nF, C_dVdt= 33 nF, C_dVdt= 33 nF, C_dVdt= 33 nF,

PARAMETER

DEVICE_CONF DEVICE_CONF DEVICE_CONF DEVICE_CONF DEVICE_CONF DEVICE_CONF UNITS

IG[10:9] = 10 IG[10:9] = 00 IG[10:9] = 11 IG[10:9] = 10 IG[10:9] = 00 IG[10:9] = 11

Output rising

slew rate

SR_ON

1.99

0.96

2.92

1.34

0.66

2.01

V/ms

t_D,ON

t_R

Turn on delay

Rise time

1.47

5.07

6.55

1.1

2.99

10.36

13.36

1.1

0.98

3.41

4.39

1.1

2.19

7.40

9.53

1.1

4.37

15.2

19.57

1.1

1.42

4.94

6.36

1.1

ms

t_ON

Turn on time

t_D,OFFTurn off delay

t_FFall time

Depends on R_OUTand C_OUT

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7.12 Typical Characteristics

1100

1050

1000

950

900

850

800

750

700

650

600

4.5

4

3.5

3

Rising

Falling

Hysteresis

2.5

2

1.5

1

V_IN(V)

3.3

12

16

0.5

-40

-20

0

20

40

T_A(C)

60

80

100 120 140

0

-40

-20

0

20

40

T_A(C)

60

80

100 120 140

图7-1. ON Resistance Across Temperature

图7-2. VDD Undervoltage Thresholds Across Temperature

3

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

5

4.5

4

3.5

Rising

Falling

Hysteresis

Rising

Falling

Hysteresis

3

2.5

2

1.5

1

0.5

0

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

T_A(C)

图7-3. VIN Undervoltage Thresholds Across Temperature

图7-4. VIN Undervoltage Thresholds Across Temperature

(VIN_UV_FLT = 0x38)

18

16

14

12

Rising

10

8

Falling

Hysteresis

6

4

2

0

-40

-20

0

20

40

60

80

100 120 140

T_A(C)

图7-6. VIN Overvoltage Protection Threshold Across

Temperature (VIN_OV_FLT = 0x0E (Default))

图7-5. VIN Undervoltage Thresholds Across Temperature

(VIN_UV_FLT = 0x8D)

18

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7.12 Typical Characteristics (continued)

4

3.5

3

14

12

10

8

2.5

Rising

Falling

Rising

Falling

Hysteresis

2

1.5

1

Hysteresis

6

4

2

0.5

0

-40

-20

0

20

40

T_A(C)

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

T_A(C)

图7-7. VIN Overvoltage Protection Threshold Across

图7-8. VIN Overvoltage Protection Threshold Across

Temperature (VIN_OV_FLT = 0x01)

Temperature (VIN_OV_FLT = 0x0B)

0.92

0.9

1.4

1.2

0.88

1

Rising

Falling

0.86

Rising

Falling

0.8

Hysteresis

0.84

0.82

0.8

0.6

0.4

0.2

0

0.78

-40

-20

0

20

40

T_A(C)

60

80

100 120 140

-40

-20

0

20

40

T_A(C)

60

80

100 120 140

图7-10. EN/UVLO Based Shutdown Thresholds Across

Temperature

图7-9. EN/UVLO Based Turn-off Thresholds Across

Temperature

18.31

2.5

2

I_OUT(A)

15

18.28

18.25

18.22

18.19

18.16

18.13

18.1

20

35

1.5

Max

Typ

Min

1

0.5

0

-0.5

-1

-1.5

-40

-20

0

20

40

60

80

100 120 140

T_A(C)

-2

14 16 18 20 22 24 26 28 30 32 34 36

I_OUT(A)

图7-11. IMON Gain Across Load and Temperature

图7-12. IMON Gain Accuracy Across Process, Voltage and

Temperature Corners

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7.12 Typical Characteristics (continued)

1.2

6

4

T_A(C)

1.1

1

-40

25

125

0.9

0.8

0.7

0.6

0.5

0.4

0.3

2

Min

Typ

Max

0

-2

-4

-6

0

5

10 15 20 25 30 35 40 45 50 55 60 63

VIREF Decimal Code

5

10

15

20

25

I_OCP(A)

30

35

40

45

50

图7-13. VIREF DAC Transfer Function

图7-14. Steady-state Overcurrent Protection Threshold (Circuit-

Breaker) Accuracy

18.3

18.27

18.24

18.21

18.18

18.15

18.12

18.09

18.06

18.03

18

35

30

25

20

15

10

Min

Typ

Max

5

0

-5

-10

-15

-20

-25

-30

-35

-40

-20

0

20

40

T_A(C)

60

80

100 120 140

5

10

15

20

25

I_LIM(A)

30

35

40

45

图7-15. ILIM Gain Across Load and Temperature

图7-16. Startup Overcurrent Protection Threshold (Current

Limit) Accuracy

4

0.5

0.499

0.498

0.497

0.496

0.495

0.494

0.493

0.492

0.491

0.49

DEVICE_CONFIG[12:11]

11

10

01

00

3.5

3

2.5

2

1.5

1

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

T_A(C)

图7-18. Scalable Fast-trip Threshold Ratio Across Temperature

图7-17. Scalable Fast-trip Threshold Ratio Across Temperature

(Startup)

(Steady-state)

20

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7.12 Typical Characteristics (continued)

112

111

110

109

108

-40

-20

0

20

40

60

80

100 120 140

T_A(C)

图7-20. Backup Overcurrent Protection Threshold (Startup)

图7-19. Fixed Fast-trip Threshold Across Temperature

Accuracy

92

91.5

91

3.25

3

2.75

DEVICE_CONFIG[10:9]

11

10

01

00

2.5

90.5

90

2.25

2

89.5

89

1.75

1.5

1.25

1

88.5

88

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

T_A(C)

图7-21. Backup Overcurrent Protection Threshold (Steady-

图7-22. DVDT Pin Charging Current Across Temperature

state) Accuracy

20.8

20.78

20.76

20.74

20.72

20.7

1

0.5

0

-0.5

-1

-1.5

-2

20.68

20.66

-2.5

-3

-40

-20

0

20

40

60

80

100 120 140

0

128

256

384

512

640

768

896 1024

T_A(C)

ADC Digital Code

图7-23. DVDT Gain Across Temperature

ADC high performance mode (DEVICE_CONFIG[3] = 1)

图7-24. ADC INL

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7.12 Typical Characteristics (continued)

55

50

45

40

35

30

25

20

15

10

5

507 508 509 510 511 512 513 514 515

T_A(C)

-40

10000

ADC Sampling Mode

Normal Mode No Averaging

Normal Mode 128 Sample Averaging

High Performance Mode No Averaging

9000

25

125

8000

High Performance Mode 128 Sample Averaging

7000

6000

5000

4000

3000

2000

1000

0

5

10 15 20 25 30 35 40 45 50 55 60 65

GPDAC1 Decimal Code

ADC Output Code

图7-25. ADC Histogram (Mid-scale Analog Input)

1.2

图7-26. General Purpose DAC1 Transfer Function

1.8

T_A(C)

1.1

1

1.6

1.4

1.2

1

-40

25

125

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.8

0.6

0.4

0.2

0

T_A(C)

-40

25

125

0

5

10 15 20 25 30 35 40 45 50 55 60 63

GPDAC2 Decimal Code

0

2

4

6

8

10

12

14

16

VCMPXREF Decimal Code

图7-27. General Purpose DAC2 Transfer Function

图7-28. General Purpose Comparators Reference DAC Transfer

Function

2

0.24

0.22

0.2

V_IL

V_IH

1.75

1.5

1.25

1

0.18

0.16

0.14

0.12

0.75

0.5

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

T_A(C)

图7-29. SWEN/General Purpose Input Pin Logic Thresholds

图7-30. PGOOD/FLT/General Purpose Output Pin Logic Level

Across Temperature

22

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7.12 Typical Characteristics (continued)

30

28

26

24

22

20

18

16

130

120

110

100

90

T_A(C)

70

55

25

80

70

60

50

-40

-20

0

20

40

T_A(C)

60

80

100 120 140

40

42

44

46

48

50

52

54

56

Load Current (A)

图7-31. QOD Sink Current Across Temperature

图7-32. Junction Temperature vs Load Current (No Air-Flow)

80

75

70

65

60

55

50

45

40

35

Airflow (LFM)

100

200

400

EN held high, IN supply ramped up to 12 V. C_OUT= 18 mF,

C_dVdt= 33 nF

40

42

44

46

48

50

52

54

56

58

60

Load Current (A)

图7-34. Power Up Using Supply

图7-33. Junction Temperature vs Load Current (With Air-Flow)

IN hot-plugged to 12 V supply. C_OUT= 18 mF, C_dVdt= 33 nF,

Insertion Delay programmed to 25 ms (INS_DLY = 0x01)

IN hot-plugged to 12 V supply. C_OUT= 18 mF, C_dVdt= 33 nF,

Insertion Delay programmed to 560 ms (INS_DLY = 0x07)

图7-35. Input Hot Plug

图7-36. Input Hot Plug

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7.12 Typical Characteristics (continued)

IN supply held steady at 12 V, EN pin held high, PMBus

OPERATION OFF Command. C_OUT= 18 mF, C_dVdt= 33 nF

IN supply held steady at 12 V, EN pin held high, PMBus

OPERATION ON Command. C_OUT= 18 mF, C_dVdt= 33 nF

图7-37. Power Down Using PMBus Command

图7-38. Power Up Using PMBus Command

IN supply held steady at 12 V, EN pin held high, PMBus

POWER_CYCLE Command. C_OUT= 18 mF, C_dVdt= 33 nF,

Default delay setting (RETRY_CONFIG[2:0] = 000b)

IN supply held steady at 12 V, EN pin toggled from low to high.

C_OUT= 18 mF, C_dVdt= 33 nF

图7-40. Power Up Using EN

图7-39. Power Cycle Using PMBus Command

IN supply held steady at 12 V, EN pin toggled from high to low.

C_OUT= 18 mF, C_dVdt= 33 nF, I_LOAD= 50 A

IN supply held steady at 12 V, EN pin toggled from high to low.

C_OUT= 18 mF, C_dVdt= 33 nF, I_LOAD= 0 A

图7-41. Power Down Using EN

图7-42. Power Down Using EN Without Output Discharge

24

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7.12 Typical Characteristics (continued)

IN supply held steady at 12 V, EN pin pulled down to 1 V for >

5 ms. C_OUT= 18 mF, C_dVdt= 33 nF, I_LOAD= 0 A

VIN Undervoltage falling threshold programmed to 10.8 V

(VIN_UV_FLT = 0x8D), EN held high, IN supply ramped down

from 12 V to 10.5 V and then ramped up again to 12 V. C_OUT

18 mF, C_dVdt= 33 nF

=

图7-43. Power Down Using EN With Output Discharge

图7-44. Input Undervoltage Protection

VIN Overvoltage rising threshold programmed to 13.78 V

(VIN_OV_FLT = 0x0B), EN held high, IN supply ramped up

from 12 V to 15 V and then ramped down again to 12 V. C_OUT

= 18 mF, C_dVdt= 33 nF

VIN Overvoltage rising threshold programmed to 13.78 V

(VIN_OV_FLT = 0x0B), EN held high, IN supply ramped up

from 12 V to 15 V and then ramped down again to 12 V. C_OUT

= 18 mF, C_dVdt= 33 nF

图7-45. Input Overvoltage Protection

图7-46. Input Overvoltage Protection

IN supply held steady at 12 V, EN toggled from low to high.

C_OUT= 18 mF, C_dVdt= 33 nF, DVDT scaling at 100 % (default,

DEVICE_CONFIG[10:9] = 10b)

IN supply held steady at 12 V, EN toggled from low to high.

C_OUT= 18 mF, C_dVdt= 33 nF, DVDT scaling at 50 %

(DEVICE_CONFIG[10:9] = 00b)

图7-47. Inrush Current Control

图7-48. Inrush Current Control

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7.12 Typical Characteristics (continued)

IN supply held steady at 12 V, EN toggled from low to high.

C_OUT= 18 mF, C_dVdt= 33 nF, Default PG delay setting

(DEVICE_CONFIG[15] = 0b)

IN supply held steady at 12 V, EN toggled from low to high.

C_OUT= 18 mF, C_dVdt= 33 nF, Higher PG delay setting

(DEVICE_CONFIG[15] = 1b)

图7-49. Power Good Assertion

图7-50. Power Good Assertion

Device in steady-state, Load current ramped up from 50 A to

70 A for 10 ms and then ramped down to 50 A. OCP threshold

set to 55 A, Overcurrent blanking delay set to 15 ms

(OC_TIMER = 0x89)

Device in steady-state, Load current ramped up from 50 A to

70 A for > 15 ms. OCP threshold set to 55 A, Overcurrent

blanking delay set to 15 ms (OC_TIMER = 0x89)

图7-52. Overcurrent Protection

图7-51. Transient Overcurrent Blanking

Device in steady-state, Load current ramped up from 50 A to

70 A for > 15 ms. OCP threshold set to 55 A, Overcurrent

blanking delay set to 15 ms (OC_TIMER = 0x89), Latch-off

configuration (Default, RETRY_CONFIG[5:3] = 000b)

Device in steady-state, Load current ramped up from 50 A to

70 A for 100 ms. OCP threshold set to 55 A, Overcurrent

blanking delay set to 15 ms (OC_TIMER = 0x89), Auto-retry 1

times configuration (RETRY_CONFIG[5:3] = 001b), Auto-retry

delay set to 55 ms (RETRY_CONFIG[2:0] = 000b)

图7-53. Fault Response - Latch-off

图7-54. Fault Response - Auto-retry

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7.12 Typical Characteristics (continued)

Device in steady-state, Load current ramped up from 50 A to

70 A for 100 ms and then ramped down to 0 A. OCP threshold

set to 55 A, Overcurrent blanking delay set to 15 ms

(OC_TIMER = 0x89), Auto-retry 4 times configuration

(RETRY_CONFIG[5:3] = 010b), Auto-retry delay set to 55 ms

(RETRY_CONFIG[2:0] = 000b)

OUT shorted to GND. IN supply held steady at 12 V, EN pin

toggled from low to high.

图7-56. Power Up into Short-Circuit Protection

图7-55. Fault Response Followed By Recovery With Auto-retry

Device in steady-state, OUT shorted to GND. OCP threshold

set to 55 A, Short-circuit fast recovery disabled (Default,

DEVICE_CONFIG[13] = 0b)

Device in steady-state, OUT shorted to GND. OCP threshold

set to 55 A, Short-circuit fast recovery disabled (Default,

DEVICE_CONFIG[13] = 0b)

图7-57. Short-Circuit Protection During Steady-state

图7-58. Short-Circuit Protection During Steady-state

Sudden step in input supply voltage during steady-state

Device in steady-state, OUT shorted to GND. OCP threshold

set to 55 A, Short-circuit fast recovery enabled (Default,

DEVICE_CONFIG[13] = 1b)

causes output current spike without triggering a false fast-trip.

图7-60. Input Line Transient Response

图7-59. Short-Circuit Protection During Steady-state With Fast

Recovery Enabled

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8 Detailed Description

8.1 Overview

The TPS25990 is an eFuse with integrated power switch to manage load voltage and load current. The device is

equipped with a PMBus compatible digital interface which allows a host to control, configure, monitor and debug

the device. The device starts its operation by monitoring the VDD and IN bus. When V_DDand V_INexceed the

respective Undervoltage Protection (UVP) thresholds, the device waits for the insertion delay timer duration to

wait for the supply to stabilize before starting up. Next the device samples the EN/UVLO pin and SWEN pins. A

high level on both these pins enables the internal MOSFET to start conducting and allows current to flow from IN

to OUT. When either EN/UVLO or SWEN is held low, the internal MOSFET is turned off.

After a successful start-up sequence, the TPS25990 device now actively monitors its load current and input

voltage, and controls the internal FET to ensure that the programmed overcurrent threshold is not exceeded and

input overvoltage spikes are cut off. This action keeps the system safe from harmful levels of voltage and

current. At the same time, a user-programmable overcurrent blanking timer allows the system to pass transient

peaks in the load current profile without tripping the eFuse. Similarly, voltage transients on the supply line are

intelligently masked to prevent nuisance trips. This feature ensures a robust protection solution against real

faults which is also immune to transients, thereby ensuring maximum system uptime.

The TPS25990 allows the host to monitor various system parameters and status over the PMBus interface. It is

also possible to change the device configuration over the PMBus interface to control device behavior as per

system needs. This includes various warning/fault thresholds, timers and pin functions. The configuration values

can also be stored in the internal non-volatile OTP memory or an external EEPROM so that the device can start

up with some pre-defined configuration without host intervention at every power-up.

The TPS25990 also provides advanced telemetry features such as high speed ADC sample buffering ("digital

oscilloscope") and Blackbox fault recording which simplify system design and debugging and facilitate predictive

maintenance.

The device has an integrated high accuracy and high bandwidth analog load current monitor, which allows the

system to precisely monitor the load current in steady state as well as during transients. This feature facilitates

the implementation of advanced dynamic platform power management techniques such as Intel PSYS to

maximize system power usage and throughput without sacrificing safety and reliability.

For systems needing higher load current support, the TPS25990 can be connected in parallel with other high

current eFuses like TPS25985x. The TPS25990 acts as a primary controller and enables control, telemetry and

configuration of the whole chain over PMBus.

All devices share current during start-up as well as steady-state to avoid over-stressing some of the devices

more than others which can result in premature or partial shutdown of the parallel chain. The devices

synchronize their operating states to ensure graceful start-up, shutdown and response to faults. This makes the

whole chain function as a single very high current eFuse rather than a bunch of independent eFuses operating

asynchronously.

The device has integrated protection circuits to ensure device safety and reliability under recommended

operating conditions. The internal FET SOA is protected at all times using a thermal shutdown mechanism,

which turns off the FET whenever the junction temperature (T_J) becomes too high for the FET to operate safely.

English Data Sheet: SLVSGG4

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8.2 Functional Block Diagram

DEVICE_CONFIG[2]

TPS25990

VTEMP

TSD

VIN_SNS

Temperature Sense and

Overtemperature protection

5

TEMP/CMP

OUT

+

-

VOUT_SNS

÷10

OVP

UVP

V_OV

÷10

23

24

25

26

10

11

12

13

IN

V_UVP

+

-

QOD_EN

22.1 mA

CP

Back-up

OC

detector

+

-

VDD

22

VINT

CMPOUT1

18.18

µA/A

18.18

µA/A

DEVICE_CONFIG[10:9]

VIMON

7

IMON

+

DVDT

4

SFT

VIN

TRAN

V_SD

+

-

IREF_LIN

SFTREF

IREF_SAT

SD

Driver/Controller

-

EN/UVLO

18

UVP

UVLO

+

DAC1

ILIM

6

8

-

OC_IMON

V_UVLO

+

-

GPDAC1[6]

+

OC_ILIM

DEVICE_CONFIG[6]

-

GHI

FB

REF GEN

9

IREF/DAC2

DEVICE_CONFIG[12:11]

V_CMP2REFV_OV

V_IREFV_DAC2

I_DAC1

V_CMP1REF

15

16

SDA

SCL

+

-

CMPOUT2

V_REF

V_CMP2REF

4

6

4

AUX

3

Extended

Telemetry

Computed

Parameters

Telemetry

Status

CMPOUT1

CMPOUT2

PG_INT

VIN_SNS

VOUT_SNS

VTEMP

Telemetry

Basic

Parameters

10

GPIO4/SMBA#/COMP1/

COMP2/EEDATA/EECLK

17

19

20

ADC

Computation

/Logic Block

GPIO

Driver

FLT_GLBL

VIMON

GND

GPIO1/PG/COMP1/COMP2/

EEDATA/EECLK

MUX

SWEN_INT

SWEN_SNS

VREF

Configuration

Registers

ADDR1

ADDR0

1

2

ADC

CTRL

GPIO2/FAULTB/COMP1/

COMP2/EEDATA/EECLK

GPIO3/SWEN/COMP1/

COMP2/EEDATA/EECLK

21

14

Configuration

NVM

I_ADDR

GND

STORE RESTORE

WRITE PROTECT

BB

CTRL

BB Shadow

RAM

BB_TIMER

BB_RAM

RETRY_DLY

OC_TIMER

INS_DLY

FLT_GLBL

OC_IMON

UVP

PMBus Digital Engine

EEPROM I2C Controller

OPERATION

POWER_CYCLE

STORE

Control

RESTORE

CLEAR_FAULTS

WRITE_PROTECT

STORE

RESTORE

WRITE_PROTECT

图8-1. TPS25990 Functional Block Diagram

8.3 Feature Description

The TPS25990 eFuse is a highly integrated, advanced power management device that provides monitoring,

detection, protection and reporting in the event of system faults.

8.3.1 Undervoltage Protection

The TPS25990 implements undervoltage lockout on VDD and VIN in case the applied voltage becomes too low

for the system or device to properly operate. The undervoltage lockout has a default internal threshold (V_UVP) on

VDD and programmable threshold (V_UVLOIN) on VIN. Alternatively, the UVLO comparator on the EN/UVLO pin

allows the undervoltage protection threshold to be externally adjusted to a user defined value. 图8-2 and 方程式

1 show how a resistor divider can be used to set the UVLO set point for a given voltage supply.

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Power

Supply

IN

R₁

EN/UVLO

R₂

GND

图8-2. Adjustable Undervoltage Protection

R

+ R

2

1

V

= V

(1)

IN UV

UVLO R

R

2

The VIN UVLO fault threshold can also be programmed using PMBus® writes to VIN_UV_FLT register.

The EN/UVLO pin implements a bi-level threshold and can be used to control the device from an external host.

1. V_EN> V_UVLO(R): Device is fully ON.

2. V_SD(F)< V_EN< V_UVLO(F): The FET along with most of the controller circuitry is turned OFF, except for some

critical bias and digital circuitry. Holding the EN/UVLO pin in this state for a duration greater than t_QOD

activates the Output Discharge function.

3. V_EN< V_SD(F): All active circuitry inside the part is turned OFF and it retains no digital state memory. It also

resets latched faults, status flags and configuration values written to the registers through PMBus® writes.

8.3.2 Insertion Delay

The TPS25990 implements insertion delay at start-up to ensure the supply has stabilized before the device tries

to turn on the power to the load. This is helpful in hotswap applications where a card is hot-plugged into a live

backplane and can have some contact bounce before the card is firmly plugged into the connector. The device

initially waits for the VDD supply to rise above the V_UVPthreshold and all the internal bias voltages to settle. After

that, the device remains off for an additional delay of t_INSDLYirrespective of the EN/UVLO pin condition. This

action helps to prevent any unexpected behavior in the system if the device tries to turn on before the card has

made firm contact with the backplane or if there is any supply ringing or noise during start-up.

The insertion delay can be changed by programming the INS_DLY register value in the Non-volatile memory/

EEPROM using PMBus®.

8.3.3 Overvoltage Protection

The TPS25990 implements overvoltage lockout to protect the load from input overvoltage conditions. If the input

voltage on IN exceeds the OVP rising threshold, the power FET is turned OFF within t_OVP. The OVP comparator

on the IN pin uses a default internal overvoltage protection threshold of V_OVP(R), which can be changed by

programming the non-volatile configuration memory or dynamically through PMBus® register writes to the

VIN_OV_FLT register. The OVP comparator has in-built hysteresis for improved noise immunity. After the

voltage on IN falls below the OVP falling threshold (V_OVP(F)), the FET is turned ON in a dVdt controlled manner.

English Data Sheet: SLVSGG4

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Input Overvoltage Event

Input Overvoltage Removed

(1)

V_OVP(R)

V_OVP(F)

IN

0

t_OVP

V_IN

OUT

dVdt limited Start-up

0

V_L

0

SWEN

PG

V_L

0

V_L

0

FLT

Time

⁽¹⁾Depends on VIN_OV_FLT register setting

图8-3. Input Overvoltage Protection Response

8.3.4 Inrush Current, Overcurrent, and Short-Circuit Protection

TPS25990 incorporates four levels of protection against overcurrent:

1. Adjustable slew rate (dVdt) for inrush current control

2. Active current limit with an adjustable threshold (I_LIM) for overcurrent protection during start-up

3. Circuit-breaker with an adjustable threshold (I_OCP) and blanking timer (t_{OC_TIMER}) for overcurrent protection

during steady-state

4. Fast-trip response to severe overcurrent faults with a programmable threshold to quickly protect against

severe short-circuits under all conditions, as well as a fixed threshold (I_FFT) during steady state

8.3.4.1 Slew rate (dVdt) and Inrush Current Control

During hot-plug events or while trying to charge a large output capacitance, there can be a large inrush current.

If the inrush current is not managed properly, it can put excessive stress on the system power supply causing it

to droop and even damage the input connectors. This action can lead to unexpected restarts elsewhere in the

system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. 方

程式 2 can be used to find the slew rate (SR) required to limit the inrush current (I_INRUSH) for a given load

capacitance (C_LOAD):

I

mA

V

ms

INRUSH

SR

=

(2)

C

µF

OUT

A capacitor can be added to the DVDT pin to control the rising slew rate and lower the inrush current during turn-

on. This is also a function of the dVdt rate scaling factor which can be digitally programmed through PMBus®

writes to the DEVICE_CONFIG register. The required C_dVdtcapacitance to produce a given slew rate can be

calculated using 方程式3.

42000 × k

C

pF =

(3)

dVdt

V

SR

ms

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where k = 1, if DEVICE_CONFIG[10:9] = 10 (Default)

k = 0.5, if DEVICE_CONFIG[10:9] = 00

k = 0.75, if DEVICE_CONFIG[10:9] = 01

k = 1.5, if DEVICE_CONFIG[10:9] = 11

The fastest output slew rate is achieved by leaving the dVdt pin open and setting DEVICE_CONFIG[10:9] = 11.

备注

High turn-on slew rates in combination with high input power path inductance can result in oscillations

during start-up. This can be mitigated using one or more of the following steps:

1. Reduce the input inductance.

2. Increase the capacitance on VIN pin.

3. Increase the DVDT pin capacitor value or change the DVDT scaling factor using

DEVICE_CONFIG[10:9] register bits to reduce the slew rate or increase the start-up time. TI

recommends using a minimum start-up time of 5 ms.

8.3.4.1.1 Start-Up Timeout

If the start-up is not completed, that is, the FET is not fully turned on within a certain timeout interval (t_{SU_TMR}

)

after SWEN is asserted, the device registers it as a fault. The fault status is reported in the

STATUS_MFR_SPECIFIC register Bit[6]. FLT is asserted low and the device goes into latch-off or auto-retry

mode depending on the RETRY_CONFIG register setting.

8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)

The TPS25990 responds to output overcurrent conditions during steady-state by performing a circuit-breaker

action after a user-adjustable transient fault blanking interval. This action allows the device to support a higher

peak current for a short user-defined interval but also ensures robust protection in case of persistent output

faults.

The device constantly senses the output load current and provides an analog current output (I_IMON) on the IMON

pin which is proportional to the load current, which in turn produces a proportional voltage (V_IMON) across the

IMON pin resistor (R_IMON) as per 方程式4.

V

= I

× G

× R

IMON

(4)

IMON

OUT

IMON

Where G_IMONis the current monitor gain (I_IMON: I_OUT

)

The overcurrent condition is detected by comparing this voltage against the voltage on the IREF pin as a

reference. The reference voltage (V_IREF) can be controlled in two ways, which sets the overcurrent protection

threshold (I_OCP) accordingly.

• The reference voltage (V_IREF) can be generated using internal DAC and can be changed by programming the

non-volatile configuration memory or dynamically through PMBus® writes to the VIREF register.

• It is also possible to drive the IREF pin from an external low impedance precision reference voltage source.

The overcurrent protection threshold during steady-state (I_OCP) can be calculated using 方程式5.

V

IREF

I

=

(5)

OCP

G

× R

IMON

备注

TI recommends to add a 1 nF capacitor from IREF pin to GND for improved noise immunity.

After an overcurrent condition is detected, that is the load current exceeds the programmed current limit

threshold (I_OCP), but stays lower than the short-circuit threshold (I_SCP), the device starts running the internal

overcurrent blanking digital timer (OC_TIMER). If the load current drops below the current limit threshold before

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the OC_TIMER expires, the circuit-breaker action is not engaged. This action allows short overload transient

pulses to pass through the device without tripping the circuit. At the same time, the OC_TIMER is reset so that it

is at its default state before the next overcurrent event. This ensures the full blanking timer interval is provided

for every overcurrent event.

If the overcurrent condition persists, the OC_TIMER continues to run and after it expires, the circuit-breaker

action turns off the FET immediately.

方程式6 can be used to calculate the R_IMONvalue for the desired overcurrent threshold.

V

IREF

× I

R

=

(6)

IMON

G

IMON

OCP

The duration for which transients are allowed can be programmed using OC_TIMER register setting through

PMBus® writes.

图 8-4 illustrates the overcurrent response for TPS25990 eFuse. After the part shuts down due to a circuit-

breaker fault, it either stays latched off or restarts automatically based on the RETRY_CONFIG register setting.

Load transient

Persistent output overload

OC_TIMER starts

OC_TIMER expired

OC_TIMER starts

2 × I_OCP

Circuit-Breaker

operation

I_OUT

I_OCP

0

IMON

V_IREF

(1)

0

t_{OC_TIMER}

V_IN

OUT

0

V_L

FLT

0

V_L

PG

0

V_L

SWEN

0

TSD

TSD_HYS

T_J

Time

Depends on the OC_TIMER register setting

(1)

图8-4. Steady-state Overcurrent (Circuit-Breaker) Response

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When a transient overcurrent condition (the load current exceeds the programmed current limit threshold but the

OC_TIMER does not expire) is detected, the device:

• sets the OC_DET bit in the STATUS_MFR_SPECIFIC_2 register

• fills-up one of the Blackbox RAM registers (if available to write) writing the event identifier as OC_DET and

relative time stamp information

• increases the Blackbox RAM address pointer in the BB_TIMER register by one (1) if it was previously less

than six (6), otherwise resets to zero (0). This change in the address pointer only occurs if one of the

Blackbox RAM registers is available to write.

备注

It is assumed that the VIN_UV_WARN , VIN_OV_WARN, and VOUT_UV_WARN events are not

triggered because of a step load transient.

When a persistent overcurrent condition (the load current exceeds the programmed current limit threshold and

the OC_TIMER expires) is detected, the device:

• sets the FET_OFF and NONE_OF_THE_ABOVE/UNKNOWN bits in the STATUS_BYTE register

• sets the OUT_STATUS, INPUT_STATUS, PGOODB, and NONE_OF_THE_ABOVE/UNKNOWN bits in the

upper byte of the STATUS_WORD register

• sets the VOUT_UV_WARN bit in the STATUS_OUT register

• sets the OC_FLT bit in the STATUS_INPUT register

• sets the PGOODB bit in the STATUS_MFR_SPECIFIC_2 register

• notifies the host by asserting SMBA, if it is not masked setting the STATUS_IN, PGOODB, and

STATUS_OUT bits in the ALERT_MASK register and the GPIO4 pin is configured as SMBA Output in the

GPIO_CONFIG_34 register

• deasserts the external PG signal, if the GPIO1 pin is configured as PGOOD Output in the GPIO_CONFIG_12

register

• asserts the FLT signal, if it is not masked setting the OC_FLT bit high in the FAULT_MASK register and the

GPIO2 pin is configured as FLT Output in the GPIO_CONFIG_12 register

备注

It is assumed that the VIN_UV_WARN and VIN_OV_WARN events are not triggered because of a

step load transient.

8.3.4.3 Active Current Limiting During Start-Up

The TPS25990 responds to output overcurrent conditions during start-up by actively limiting the current. The

device constantly senses the current flowing through the device (I_DEVICE) and provides an analog current output

(I_ILIM) on the ILIM pin, which in turn produces a proportional voltage (V_ILIM) across the ILIM pin resistor (R_ILIM) as

per 方程式7.

V

= I

× G

× R

ILIM

(7)

ILIM

DEVICE

ILIM

Where G_ILIMis the current monitor gain (I_ILIM: I_DEVICE

)

The overcurrent condition is detected by comparing this voltage against a threshold which is a scaled voltage

(CLREF_SAT) derived from the reference voltage (V_IREF) on the IREF pin as presented in 方程式8.

0.7 × V

IREF

CLREF

=

(8)

SAT

3

The reference voltage (V_IREF) can be controlled in two ways, which sets the overcurrent protection threshold

(I_LIM) accordingly.

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• The reference voltage (V_IREF) can be generated using internal DAC and can be changed by programming the

non-volatile configuration memory or dynamically through PMBus® writes to the VIREF register.

• It is also possible to drive the IREF pin from an external low impedance precision reference voltage source.

The active current limit (I_LIM) threshold during start-up can be calculated using 方程式9.

CLREF

SAT

I

=

(9)

ILIM

G

× R

ILIM

When the load current during start-up exceeds I_LIM, the device tries to regulate and hold the load current at I_LIM

.

During current regulation, the output voltage drops, resulting in increased device power dissipation across the

FET. If the device internal temperature (T_J) exceeds the thermal shutdown threshold, the FET is turned off. After

the part shuts down due to a TSD fault, it either stays latched off or restarts automatically after a delay based on

the RETRY_CONFIG register setting. See Overtemperature protection section for more details on device

response to overtemperature.

备注

The active current limit block employs a foldback mechanism during start-up based on the output

voltage (V_OUT). When V_OUTis below the foldback threshold (V_FB), the current limit threshold is further

lowered.

8.3.4.4 Short-Circuit Protection

During an output short-circuit event, the current through the device increases very rapidly. When an output short-

circuit is detected, the internal fast-trip comparator triggers a fast protection sequence to prevent the current from

building up further and causing any damage or excessive input supply droop. This action enables the user to

adjust the fast-trip threshold as per system rating, rather than using a high fixed threshold which may not be

suitable for all systems. The fast-trip comparator employs a scalable threshold (I_SFT) which is a function of the

circuit-breaker threshold (I_OCP) and a digitally programmable scaling factor. The default fast-trip threshold is

equal to 2 × I_OCPduring steady-state and 1.5 × I_LIMduring inrush. The scaling factor for steady-state fast-trip

threshold can be programmed to a different value using the DEVICE_CONFIG[12:11] register bits. Available

programming options are 1.5 ×, 2 ×, 1.75 × and 2.25 ×. After the current exceeds the fast-trip threshold, the

TPS25990 turns off the FET within t_SFT

.

The device also employs a higher fixed fast-trip threshold (I_FFT) to provide fast protection against hard short-

circuits during steady-state (FET in linear region). After the current exceeds I_FFT, the FET is turned off

completely within t_FFT

.

The device response after a fast-trip event can be configured using the SC_RETRY bit in the DEVICE_CONFIG

register through PMBus® register writes or non-volatile configuration memory. There are 2 programming options

available:

1. SC_RETRY = 0 (Default setting): The device latches a fault and remains off till a restart is triggered either

externally or through internal auto-retry mechanism as per the RETRY_CONFIG register setting.

When a short-circuit fault occurs with the SC_RETRY bit in the DEVICE_CONFIG register low, the device:

• sets the FET_OFF and NONE_OF_THE_ABOVE/UNKNOWN bits in the STATUS_BYTE register

• sets the OUT_STATUS, PGOODB, and NONE_OF_THE_ABOVE/UNKNOWN bits in the upper byte of

the STATUS_WORD register

• sets the VOUT_UV_WARN bit in the STATUS_OUT register

• sets the PGOODB and SC_FLT bits in the STATUS_MFR_SPECIFIC_2 register

• notifies the host by asserting SMBA#, if it is not masked setting the PGOODB and STATUS_OUT bits in

the ALERT_MASK register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34

register

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• deasserts the external PG signal, if the GPIO1 pin is configured as PGOOD Output in the

GPIO_CONFIG_12 register

• asserts the FLT signal, if it is not masked setting the SC_FLT bit high in the FAULT_MASK register and

the GPIO2 pin is configured as 'FLT Output' in the GPIO_CONFIG_12 register

2. SC_RETRY = 1: The device attempts to turn the FET back ON fully after a short de-glitch interval (30 μs).

This allows the FET to try and recover quickly after a transient overcurrent event and minimizes the output

voltage droop. However, if the fault is persistent, the device enters current limit causing the junction

temperature to rise and eventually enter thermal shutdown. The device latches a fault and remains off till a

restart is triggered either externally or through internal auto-retry mechanism as per the RETRY_CONFIG

register setting. See Overtemperature Protection section for details on the device response to

overtemperature.

When a short-circuit fault occurs with the SC_RETRY bit in the DEVICE_CONFIG register high, the device:

• sets the FET_OFF, STATUS_TEMP, and NONE_OF_THE_ABOVE/UNKNOWN bits in the

STATUS_BYTE register

• sets the OUT_STATUS, MFR_STATUS, PGOODB, and NONE_OF_THE_ABOVE/UNKNOWN bits in the

upper byte of the STATUS_WORD register

• sets the VOUT_UV_WARN bit in the STATUS_OUT register

• sets the OT_FLT bit in the STATUS_TEMP register

• sets the SOA_FLT bit in the STATUS_MFR_SPECIFIC register

• sets the PGOODB bit in the STATUS_MFR_SPECIFIC_2 register

• notifies the host by asserting SMBA#, if it is not masked setting the PGOODB, MFR_STATUS,

STATUS_TEMP, and STATUS_OUT bits in the ALERT_MASK register and the GPIO4 pin is configured

as SMBA# Output in the GPIO_CONFIG_34 register

• deasserts the external PG signal, if the GPIO1 pin is configured as PGOOD Output in the

GPIO_CONFIG_12 register

• asserts the FLT signal, if it is not masked setting the SOA_FLT and TEMP_FLT bits high in the

FAULT_MASK register and the GPIO2 pin is configured as 'FLT Output' in the GPIO_CONFIG_12

register

图8-5 illustrates the short-circuit response for TPS25990 eFuse.

In some of the systems, for example blade servers and telecom equipment which house multiple hot-pluggable

blades or line cards connected to a common supply backplane, there can be transients on the supply due to

switching of large currents through the inductive backplane. This can result in current spikes on adjacent cards

which can potentially be large enough to trigger the fast-trip comparator of the eFuse. The TPS25990 uses a

proprietary algorithm to avoid nuisance tripping in such cases thereby facilitating uninterrupted system operation.

备注

• The VIN_TRAN status bit in STATUS_MFR_SPECIFIC_2 register is set to indicate if an input line

transient event was detected and masked.

• The input line transient masking feature can be optionally disabled by setting the VIN_TRAN_DIS

bit high in the DEVICE_CONFIG register.

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Retry Timer Elapsed ⁽³⁾

Or

Power/Enable Cycled

Transient Severe Overcurrent

Fast Recovery ⁽¹⁾

Transient Severe Overcurrent

Retry Timer Elapsed ⁽²⁾⁽³⁾

Or

Persistent Severe Overcurrent Fault

Retry Timer Elapsed ⁽³⁾

Or

Power/Enable Cycled

Thermal Shutdown

V_IN

Fault Removed

IN

0

t_SFT

I_FFT

(4)

2 × I_OCP

I_OUT

I_OCP

I_LIM

0

(4)

2 × V_IREF

IMON

V_IREF

0

0.5 × V_IREF

ILIM

0.23 × V_IREF

0

Current limited

Start-up

V_IN

OUT

Current limited recovery

dVdt limited

start-up

dVdt limited

Start-up

0

t_PGD

V_L

PG

0

V_L

FLT

0

V_L

SWEN

0

TSD

TSD_HYS

T_J

⁽¹⁾Fast recovery enabled using DEVICE_CONFIG[13] bit setting

⁽²⁾Fast recovery disabled using DEVICE_CONFIG[13] bit setting

⁽³⁾Device configured for auto-retry response using RETRY_CONFIG register setting

⁽⁴⁾Default SFT threshold using DEVICE_CONFIG[12:11] bit setting

Time

图8-5. Short-Circuit Response

8.3.5 Single Point Failure Mitigation

The TPS25990 relies on the proper component connections and biasing on the IMON, ILIM and IREF pins along

with the appropriate threshold digital configurations to provide overcurrent and short-circuit protection under all

circumstances. As an added safety measure, the device uses the following mechanisms to ensure that the

device provides some form of overcurrent protection even if any of these pins are not connected correctly in the

system or the associated components have a failure in the field or if the configuration registers are not

programmed correctly.

8.3.5.1 IMON Pin Single Point Failure

• IMON pin open: In this case, the IMON pin voltage is internally pulled up to a higher voltage and exceeds the

threshold (V_IREF), causing the part to perform a circuit-breaker action even if there is no significant current

flowing through the device.

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• IMON pin shorted to GND directly or through a very low resistance: In this case, the IMON pin voltage is

held at a low voltage and is not allowed to exceed the threshold (V_IREF) even if there is significant current

flowing through the device, thereby rendering the primary overcurrent protection mechanism ineffective. The

device relies on an internal overcurrent sense mechanism to provide some protection as a backup. If the

device detects that the backup current sense threshold (I_{OC_BKP}) is exceeded but at the same time the

primary overcurrent detection on IMON pin fails, it triggers single point failure detection and latches a fault.

The FET is turned off and the FLT pin is asserted. At the same time, the SPFAIL status bit in

STATUS_MFR_SPECIFIC_2 register is set and the SMBA# signal is asserted.

8.3.5.2 ILIM Pin Single Point Failure

• ILIM pin open: In this case, the ILIM pin voltage is internally pulled up to a higher voltage and exceeds the

V_IREFthreshold, causing the part to engage the current limit even if there is no significant current flowing

through the device.

• ILIM pin shorted to GND directly or through a very low resistance: In this case, the ILIM pin voltage is

held at a low voltage and is not allowed to exceed the start-up current limit threshold even if there is

significant current flowing through the device, thereby rendering the primary current limit mechanism

ineffective during start-up. The device relies on an internal overcurrent detection mechanism to provide some

protection as a backup. If the device detects that the load current exceeds the backup overcurrent threshold

(I_{OC_BKP}) but at the same time the primary overcurrent detection on ILIM pin fails, it triggers single point

failure detection and latches a fault. The FET is turned off and the FLT pin is asserted. At the same time, the

SPFAIL status bit in STATUS_MFR_SPECIFIC_2 register is set and the SMBA# signal is asserted.

8.3.5.3 IREF Pin Single Point Failure

• IREF DAC set incorrectly or externally forced to higher voltage: In this case, the IREF pin (V_IREF) is

pulled up internally or externally to a voltage which is higher than the target value as per the recommended

I_OCPor I_LIMcalculations, preventing the primary circuit-breaker, active current limit, and short-circuit protection

from getting triggered even if there is significant current flowing through the device. The device relies on an

internal overcurrent detection mechanism to provide some protection as a backup. If the device detects that

the load current exceeds backup overcurrent threshold (I_{OC_BKP}) but at the same the primary overcurrent or

short-circuit detection on ILIM or IMON pin fails, it triggers single point failure detection and latches a fault.

The FET is turned off and the FLT pin is asserted. At the same time, the SPFAIL status bit in

STATUS_MFR_SPECIFIC_2 register is set and the SMBA# signal is asserted.

• IREF pin shorted to GND: In this case, the V_IREFthreshold is set to 0 V, causing the part to perform active

current limit or circuit-breaker action even if there is no significant current flowing through the device.

8.3.6 Analog Load Current Monitor (IMON)

The TPS25990 allows the system to monitor the output load current accurately by providing an analog current on

the IMON pin which is proportional to the current through the FET. The benefit of having a current output is that

the signal can be routed across a board without adding significant errors due to voltage drop or noise coupling

from adjacent traces. The current output also allows the IMON pins of multiple eFuse devices (TPS25990 or

TPS25985x) to be tied together to get the total current in a parallel configuration. The IMON signal can be

converted to a voltage by dropping it across a resistor at the point of monitoring. The user can sense the voltage

(V_IMON) across the R_IMONto get a measure of the output load current using 方程式10.

V

IMON

I

=

(10)

OUT

G

× R

IMON

The TPS25990 IMON circuit is designed to provide high bandwidth and high accuracy across load and

temperature conditions, irrespective of board layout and other system operating conditions. This design allows

the IMON signal to be used for advanced dynamic platform power management techniques such as Intel PSYS

or PROCHOT to maximize system power usage and platform throughput without sacrificing safety or reliability.

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图8-6. Analog Load Current Monitor Response

备注

1. The IMON pin provides load current monitoring information only during steady-state. During

inrush, the IMON pin reports zero load current.

2. The ILIM pin reports the individual device load current at all times and can also be used as an

analog load current monitor for each individual device.

3. TI recommends adding a 22 pF capacitor from IMON pin to GND for noise filtering purposes.

4. Care must be taken to minimize parasitic capacitance on the ILIM pin to avoid any impact on the

overcurrent and short-circuit protection timing during start-up.

8.3.7 Overtemperature Protection

The TPS25990 employs an internal thermal shutdown mechanism to protect itself when the internal FET

becomes too hot to operate safely. When the TPS25990 detects thermal overload, it shuts down. Thereafter it

either remains latched-off until the device is power cycled or re-enabled, or restarts automatically after delay

based on the device Auto-retry configuration.

The overtemperature threshold has a default threshold (TSD) which can be digitally programmed to a lower

value using the OT_FLT register based on system needs.

表8-1. Overtemperature Protection Summary

Auto-Retry

Enter TSD

Exit TSD

Configuration

V_TEMP< OT_FLT - OT_Hysor T_J< TSD –TSD_HYS

VDD cycled to 0 V and then above V_UVP(R)or EN/

UVLO toggled below V_SD(F)

Latch-Off

V

_TEMP≥OT_FLT threshold or T_J≥TSD

V_TEMP< OT_FLT - OT_Hysor T_J< TSD –TSD_HYS

Retry Timer expired or VDD cycled to 0 V and then

above V_UVP(R)or EN/UVLO toggled below V_SD(F)

Auto-Retry

_TEMP≥OT_FLT threshold or T_J≥TSD

8.3.8 Analog Junction Temperature Monitor (TEMP)

The TPS25990 allows the system to monitor the junction temperature (T_J) accurately by providing an analog

voltage on the TEMP pin which is proportional to the temperature of the die. This voltage is sensed by an ADC

input and reported using the READ_TEMPERATURE_1 PMBus® command for digital telemetry. In a multi-

device parallel configuration involving TPS25990 and TPS25985x , the TEMP outputs of all devices can be tied

together. In this configuration, the TEMP signal reports the temperature of the hottest device in the chain.

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备注

1. The TEMP pin voltage is used only for external monitoring and does not interfere with the

overtemperature protection scheme of each individual device which is based purely on the internal

temperature monitor.

2. TI recommends to add a capacitance of 22 pF on the TEMP pin to filter out glitches during system

transients.

8.3.9 FET Health Monitoring

The TPS25990 can detect and report certain conditions which are indicative of a failure of the power path FET. If

undetected or unreported, these conditions can compromise system performance either by not providing power

to the load correctly or the necessary level of protection. After a FET failure is detected, the TPS25990 tries to

turn off the internal FET by pulling the gate low and asserts the FLT pin. The specific FET fault type is also

reported in the STATUS_MFR_SPECIFIC status register.

• D-S short: D-S short can result in a constant uncontrolled power delivery path formed from source to load,

either due to a board assembly defect or due to internal FET failure. This condition is detected at start-up by

checking if V_IN-OUT< V_DSFLTbefore the FET is turned ON. If yes, the device engages the internal output

discharge to try and discharge the output. If the V_OUTdoesn’t discharge below V_FBwithin a certain allowed

interval, the device asserts the FLT pin and sets the FET_FAULT_DS bit in the STATUS_MFR_SPECIFIC

status register.

备注

There is an option to disable the D-S fault detection digitally by setting the DIS_VDSFLT bit in the

DEVICE_CONFIG register. This allows the device start-up into a pre-charged output without triggering

the D-S fault.

• G-D short: The TPS25990 detects this kind of FET failure at all times by checking if the gate voltage is close

to V_INeven when the internal control logic is trying to hold the FET in OFF condition. If this condition is

detected, the device asserts the FLT pin and sets the FET_FAULT_GD bit in the STATUS_MFR_SPECIFIC

status register.

• G-S short: The TPS25990 detects this kind of FET failure during start-up by checking if the FET G-S voltage

fails to reach the necessary overdrive voltage within a certain timeout period (t_{SU_TMR}) after the gate driver is

turned ON. While in steady-state, if the G-S voltage becomes low before the controller logic has signaled to

the gate driver to turn off the FET, it is latched as a fault. If this condition is detected, the device asserts the

FLT pin and sets the FET_FAULT_GS bit in the STATUS_MFR_SPECIFIC status register.

8.3.10 General Purpose Digital Input/Output Pins

The TPS25990 has four (4) general purpose digital input/output pins which can be configured for different

functions as per system needs.

1. General Purpose Digital Input

2. General Purpose Digital Output

3. Fault (FLT) Indication Output

4. Power Good (PG) Indication Output

5. SWEN Input/Output

6. SMBus Alert (SMBA#) Indication Output

7. General Purpose Comparator-1 Output

8. General Purpose Comparator-2 Output

9. External EEPROM I2C Clock (EECLK)

10. External EEPROM I2C Data (EEDATA)

8.3.10.1 Fault Response and Indication (FLT)

表8-2 summarizes the device response to various fault conditions.

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表8-2. Fault Summary

Fault Latched

Internally

Pin Indication

Masking Option

Event or Condition

Device Response

None

FLT Pin Status

Delay

Steady-state

Inrush

N/A

Y

H

L

N/A

Y

None

Overtemperature

Shutdown

Undervoltage (EN/UVLO) Shutdown

Undervoltage (VDD UVP) Shutdown

N

H

N/A

N

Undervoltage (VIN UVP)

Overvoltage (VIN OVP)

Transient overcurrent

Shutdown

None

N

Persistent overcurrent

(steady-state)

Circuit-Breaker

Y

L

Y

t_ITIMER

Persistent overcurrent

(start-up)

Current Limit

Fast-trip

N

Y

N

Y

H

L

N/A

Y

Output short-circuit

t_FT

Output short-circuit (Fast

recovery configuration)

Fast-trip followed by

H

L

N/A

Y

current limited Start-up

ILIM pin open (start-up)

ILIM pin short (start-up)

Shutdown

Shutdown (if I_OUT

I_{OC_BKP}

>

L

Y

)

ILIM pin open (steady-

state)

Active current sharing

loop always active

N

Y

H

L

N/A

Y

ILIM pin short (steady-

state)

Active current sharing

loop disabled

IMON pin open (steady-

state)

Shutdown

IMON pin short (steady-

state)

Shutdown (If I_OUT

I_{OC_BKP}

>

Y

45 μs

)

Shutdown (If I_OUT

I_{OC_BKP}

IREF pin open (start-up)

Y

)

IREF pin open (steady-

state)

Shutdown (if I_OUT

I_{OC_BKP}

Y

t_ITIMER

)

IREF pin short (steady-

state)

Shutdown

Y

IREF pin short (start-up)

Start-up timeout

Shutdown

Y

N

L

Y

N

Y

t_{SU_TMR}

FET health fault (G-S)

FET health fault (G-D)

FET health fault (D-S)

External fault (SWEN

10 μs

t_{SU_TMR}

pulled low externally while Shutdown

device is not in UV or OV)

Y

L

Y

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表8-2. Fault Summary (continued)

Fault Latched

Internally

Pin Indication

Masking Option

Event or Condition

Device Response

FLT Pin Status

Configurable through

DEVICE_CONFIG

register

Comparator-1 fault

Y

L

Y

Configurable through

DEVICE_CONFIG

register

Comparator-2 fault

L

备注

GPIO2 pin is configured as FLT by default to provide an active low fault indication. FLT is an open-

drain pin and must be pulled up to an external supply. Refer to GPIO_CONFIG_12 register for more

details and configuration options.

The device response after a fault varies based on the RETRY_CONFIG register setting. The device latches a

fault as per the table above and thereafter follows an auto-retry or latch-off response. For auto-retry

configuration, the latched faults also trigger the start of the Auto-Retry Timer, while keeping the FLT pin pulled

low. On expiry of the timer period (t_RETRY), the FLT pin pull-down is released and the device is ready to restart

automatically. When the device turns on again, it follows the usual DVDT limited start-up sequence.

The only exception to this is during Short-circuit fault when the device is configured for fast recovery using the

SC_RETRY bit in the DEVICE_CONFIG register. In this case, the device turns off quickly and then automatically

turns back on in a current limited manner. This allows the system to try and recover quickly from any transient

faults. See Short-Circuit Protection section for more details.

For faults that are latched internally, power cycling the part or pulling the EN/UVLO pin voltage below V_SD(F)

clears the fault and the FLT pin is de-asserted. This action also clears the Auto-retry timer. Pulling the EN/UVLO

just below the UVLO threshold has no impact on the device in this condition. This is true in case of latch-off and

auto-retry configurations.

In a parallel eFuse configuration involving TPS25990 and TPS25985x, the fault response is determined by the

TPS25990 as the primary device. However, if the primary device fails to register a fault, there is a fail-safe

mechanism in the secondary device to take control and turn off the entire chain by pulling the SWEN pin low and

enter a latch-off condition. Thereafter, the device can be turned on again only by power cycling VDD below

V_UVP(F)or by cycling EN/UVLO pin below V_SD(F)

.

8.3.10.2 Power Good Indication (PG)

Power Good is an active high digital output which is asserted high to indicate when the device is in steady-state

and capable of delivering maximum power.

表8-3. PG Indication Summary

Event or Condition

FET Status

PG Pin Status

PG Delay

Device disabled ( V_EN< V_UVLO

)

OFF

L

t_PGD

VIN Undervoltage (V_IN< V_UVPor

V_IN< VIN_UV_FLT)

VDD Undervoltage (V_DD< V_UVP

)

OFF

L

VIN Overvoltage (V_IN

VIN_OV_FLT)

>

t_PGD

Steady-state

Inrush

ON

H

L

t_PGA

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表8-3. PG Indication Summary (continued)

Event or Condition

FET Status

PG Pin Status

PG Delay

Transient overcurrent

ON

H

L

N/A

Circuit-breaker (persistent

overcurrent followed by

OC_TIMER expiry)

OFF

t_{OC_TIMER}+ t_PGD

L (V_OUT< VOUT_PGTH)

H (V_OUT> VOUT_PGTH)

t_PGD

N/A

Fast-trip

OFF

Overtemperature

Shutdown

L

t_PGD

备注

GPIO1 pin is configured as PG output by default. Refer to GPIO_CONFIG_12 register for more details

and configuration options.

After power up, PG is pulled low initially. The device initiates an inrush sequence in which the gate driver circuit

starts charging the gate capacitance from the internal charge pump. When the FET gate voltage reaches the full

overdrive indicating that the inrush sequence is complete and the device is capable of delivering full power, the

PG pin is asserted high after a de-glitch time (t_PGA). The PG assertion delay can be optionally increased by

setting the PG_DVDT_DLY bit in the DEVICE_CONFIG register.

The PG is de-asserted if the output voltage falls below a threshold at any point during normal operation or the

device detects a fault (except short-circuit). The PG de-assertion threshold can be digitally programmed through

the VOUT_PGTH register. The PG de-assertion de-glitch time is t_PGD

.

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Overload Event

Overcurrent blanking timer expired

Device Enabled

V_UVLO(R)

0

EN/UVLO

SWEN

0

IN

Slew rate (dVdt) controlled

startup/Inrush current limiting

0

V_IN

Circuit-breaker action

(1)

V_PGTH

OUT

0

t_PGA

t_PGD

V_PG

PG

0

dVdt

0

V_OUT+ 2.8 V

V_HGate

0

t_{OC_TIMER}

I_OCP

I_INRUSH

I_OUT

0

Time

⁽¹⁾Depends on VOUT_PGTH register setting

图8-7. TPS25990 PG Timing Diagram

The PG is an open-drain pin and must be pulled up to an external supply.

备注

When there is no supply to the device, the PG pin is expected to stay low. However, there is no active

pulldown in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an

independent supply which is present even if the device is unpowered, there can be a small voltage

seen on this pin depending on the pin sink current, which is a function of the pullup supply voltage and

resistor. Minimize the sink current to keep this pin voltage low enough not to be detected as a logic

HIGH by associated external circuits in this condition.

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8.3.10.3 Parallel Device Synchronization (SWEN)

The SWEN pin is a signal which is driven high when the FET must be turned ON. When the SWEN pin is driven

low (internally or externally), it signals the driver circuit to turn OFF the FET. This pin serves both as a control

and handshake signal and allows multiple devices in a parallel configuration to synchronize their FET ON and

OFF transitions.

表8-4. SWEN Summary

Device State

FET Driver Status

SWEN

Steady-state

Inrush

ON

H

L

Overtemperature shutdown

Auto-retry timer running

OFF

Device disabled ( V_EN< V_UVLO

)

VIN Undervoltage (V_IN< V_UVPor V_IN

VIN_UV_FLT)

<

VDD Undervoltage (V_DD< V_UVP

Insertion delay

)

OFF

ON

L

H

L

VIN Overvoltage (V_IN> VIN_OV_FLT)

Transient overcurrent

Circuit-breaker (persistent overcurrent

followed by OC_TIMER expiry)

OFF

Fast-trip

OFF

L

Fast-trip response mono-shot running

(DEVICE_CONFIG[13] = 1)

Fast-trip response mono-shot running

(DEVICE_CONFIG[13] = 1)

ON

H

L

FET health fault

OFF

External fault (SWEN pulled low by

secondary device in parallel chain)

L (held low by TPS25990 even if secondary

device releases the pull down after some

time)

The SWEN is an open-drain pin and must be pulled up through a 100 kΩ resistance to an external supply

generated using the input voltage to the eFuse.

备注

1. GPIO3 pin is configured as SWEN by default. Refer to GPIO_CONFIG_34 register for more

details and configuration options.

2. The SWEN pullup supply needs to be powered up before the eFuse is turned on. TI recommends

to use a system standby rail which is derived from the input of the eFuse and is powered up

before the eFuse. The exception to this is when TPS25990 is used as a standalone device and

the GPIO3 pin is digitally configured for some function other than SWEN.

In a primary and secondary parallel configuration, the SWEN pin is used by the primary device to control the ON

and OFF transitions of the secondary devices. At the same time, it allows the secondary devices to communicate

any faults or other conditions which can prevent it from turning on the primary device.

To maintain state machine synchronization, the devices rely on SWEN level transitions as well as timing for

handshakes. This ensures all the devices turn ON and OFF synchronously and in the same manner (for

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example, dVdt controlled or current limited start-up). There are also fail-safe mechanisms in the SWEN control

and handshake logic to ensure the entire chain is turned off safely even if the primary device is unable to take

control in case of a fault.

备注

TI recommends to keep the parasitic loading on the SWEN pin to a minimum to avoid synchronization

timing issues.

8.3.11 Stacking Multiple eFuses for Unlimited Scalability

For systems needing higher current than supported by a single TPS25990, it is possible to connect TPS25990 in

parallel with one or more TPS25985x devices to deliver the desired total system current. Conventional eFuses

do not share current evenly between themselves during steady-state due to mismatches in their path resistances

(which includes the individual device R_DSONvariation from part to part, as well as the parasitic PCB trace

resistance). This fact can lead to multiple problems in the system:

1. Some devices always carry higher current as compared to other devices, which can result in accelerated

failures in those devices and an overall reduction in system operational lifetime.

2. As a result, thermal hotspots form on the board, devices, traces, and vias carrying higher current, leading to

reliability concerns for the PCB. In addition, this problem makes thermal modeling and board thermal

management more challenging for designers.

3. The devices carrying higher current can hit their individual circuit-breaker threshold prematurely even while

the total system load current is lower than the overall circuit-breaker threshold. This action can lead to false

tripping of the eFuse chain during normal operation. This has the effect of lowering the current-carrying

capability of the parallel chain. In other words, the current rating of the parallel eFuse chain needs to be de-

rated as compared to the sum of the current ratings of the individual eFuses. This de-rating factor is a

function of the path resistance mismatch, the number of devices in parallel, and the individual eFuse circuit-

breaker accuracy.

The need for de-rating has an adverse impact on the system design. The designer is forced to make one of

these trade-offs:

1. Limit the operating load current of the system to below the derated overcurrent threshold of the eFuse chain.

Essentially, it means lower platform capabilities than are supported by the power supply (PSU).

2. Increase the overall circuit-breaker threshold to allow the desired system load current to pass through

without tripping. As a consequence, the power supply (PSU) must be oversized to deliver higher currents

during faults to account for the degradation of the overall circuit-breaker accuracy.

In either case, the system suffers from poor power supply utilization, which can mean sub-optimal system

throughput or increased installation and operating costs, or both.

The TPS25990 and TPS25985x devices use a proprietary technique to address these problems and provide

unlimited scalability of the solution by paralleling as many eFuses as needed. This is incorporated without

significant current imbalance or any degradation in accuracy.

For this scheme to work correctly, the devices must be connected in the following manner:

• The SWEN pins of all the devices are connected together.

• The IMON pins of all the devices need to be connected together. The R_IMONresistor value on the combined

IMON pin can be calculated using 方程式11.

V

IREF

R

=

(11)

IMON

G

× I

IMON

OCP TOTAL

• The IREF pins of all the devices need to be connected together. The TPS25990 generates the V_IREF

reference voltage for the whole chain using its internal DAC which can be programmed using PMBus® writes

to the VIREF register. This allows the overcurrent protection thresholds to be dynamically adjusted during

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system operation. It is also possible to drive the IREF pin using a low impedance external precision voltage

reference.

• The start-up current limit and active current sharing threshold for each device is set independently using the

ILIM pin. The R_ILIMvalue for the TPS25990 must be selected based on the following equation.

1.1 × 4N − 1 × R

IMON

R

=

(12)

(13)

ILIM 25990

9

The R_ILIMvalue for each TPS25985x must be selected based on the following equation.

1.1 × 4N − 1 × R

IMON

R

=

ILIM 25985

12

Where N = Number of devices in parallel chain (1 × TPS25990 + (N - 1) × TPS25985)

备注

1. The active current sharing scheme is engaged when the current through any eFuse while in

steady-state exceeds the individual current sharing threshold set by the R_ILIMbased on 方程式14.

1.1 × V

IREF

R

=

(14)

ILIM

3 × G

ILIM

× I

LIM ACS

2. The active current sharing scheme is disengaged when the total system current exceeds the

system overcurrent (circuit-breaker) threshold (I_OCP(TOTAL)).

8.3.11.1 Current Balancing During Start-Up

The TPS25990 implements a proprietary current balancing mechanism during start-up, which allows TPS25990

and TPS25985x devices connected in parallel to share the inrush current and distribute the thermal stress

across all the devices. This feature helps to complete a successful start-up with all the devices and avoid a

scenario where some of the eFuses hit thermal shutdown prematurely. This in effect increases the inrush current

capability of the parallel chain. The improved inrush performance makes it possible to support very large load

capacitors on high current platforms without compromising the inrush time or system reliability.

8.3.12 General Purpose Comparators

The device has two (2) general purpose comparators (CMP1 and CMP2) whose inputs, thresholds and outputs

can be digitally configured. This allows the user complete flexibility to use these comparators as per system

needs.

Comparator-1:

• The positive input of the comparator can be connected to either the TEMP/CMP pin, or internally to the IMON

pin. Refer to the DEVICE_CONFIG register for more details and configuration options.

• The comparator threshold can be digitally configured using an internal DAC (CMP1REF). Refer to the

VCMPxREF register for more details and configuration options.

• The comparator output can be digitally configured to be an output on one of the GPIO pins or used to trigger

a fault which controls the FET ON/OFF status internally. Also, the comparator output polarity can be digitally

configured. Refer to the GPIO_CONFIG_12, GPIO_CONFIG_34, and DEVICE_CONFIG registers for more

details and configuration options.

Comparator-2:

• The comparator's positive input is internally connected to the AUX pin.

• The comparator threshold can be digitally configured using an internal DAC (CMP2REF). Refer to the

VCMPxREF register for more details and configuration options.

• The comparator output can be digitally configured to be an output on one of the GPIO pins or used to trigger

a fault which controls the FET ON/OFF status internally. Also, the comparator output polarity can be digitally

configured. Refer to the GPIO_CONFIG_12, GPIO_CONFIG_34, and DEVICE_CONFIG registers for more

details and configuration options.

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These comparators can be used for various purposes. Here is one such example:

• Programmable fast overcurrent detect (PROCHOT#): Comparator-1 is configured to take IMON pin as the

input and an appropriate reference voltage is set using the internal DAC (CMP1REF) in the VCMPxREF

register. The comparator output is configured to be brought out on one of the General Purpose I/O pins. This

pin is connected to the PROCHOT# pin of the processor. When the load current crosses the set threshold,

the GPIOx goes low and signals the processor to throttle down immediately.

DEVICE_CONFIG

+

-

CMPOUT1

V_IMON

IMON

GPIOx

V_CMP1REF

4

CMPXREF

GPIOxx_CONFIG

DEVICE_CONFIG

图8-8. Programmable Fast Overcurrent (PROCHOT#) Detect Using Internal Comparator and General

Purpose I/O

图8-9. PROCHOT# Response Using Internal Comparator

8.3.13 Output Discharge

The TPS25990 has an integrated output discharge function which discharges the capacitors on the OUT pin

using an internal constant current (I_QOD) sink path to GND. The output discharge function is activated when the

EN/UVLO is held low (V_SD(F)< V_EN< V_UVLO(F)) for a minimum interval (t_QOD). The output discharge function

helps to rapidly remove the residual charge left on large output capacitors and prevents the bus from staying at

some undefined voltage for extended periods of time. The output discharge is disengaged when V_OUT< V_FBor if

the device detects a fault.

The output discharge function can result in excessive power dissipation inside the device leading to an increase

in junction temperature (T_J). The output discharge is disabled if the junction temperature (T_J) crosses the device

overtemperature threshold (TSD) to avoid long-term degradation of the part.

备注

In a primary and secondary parallel eFuse configuration, TI recommends to hold EN/UVLO voltage

below the V_UVLO(F)threshold of the secondary eFuse to activate output discharge for all the eFuses in

the chain.

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8.3.14 PMBus^®Digital Interface

The TPS25990 is a PMBus® target device with an embedded digital telemetry controller block. This enables bi-

directional communication with a host controller using a pre-defined set of commands to control, configure,

monitor and debug the system.

The TPS25990 is compliant with PMBus® specifications version 1.3 Part I and Part II.

8.3.14.1 PMBus^®Device Addressing

The TPS25990 uses 7-bit I2C device addressing. Up to 25 different addresses can be generated using different

pin-strapping combinations on the ADDR0 and ADDR1 pins as shown in 表 8-5. This allows multiple devices to

be connected to the same I2C bus.

表8-5. TPS25990 PMBus^®Address Decoding

ADDR0 Pin

ADDR1 Pin

PMBus^®Device Address

Open

0x40 (Default). Can be overwritten with a

user defined address programmed into

PMBUS_ADDR register in the Config NVM

space.

Open

GND

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

75 kΩto GND

150 kΩto GND

267 kΩto GND

Open

GND

75 kΩto GND

150 kΩto GND

267 kΩto GND

Open

75 kΩto GND

150 kΩto GND

267 kΩto GND

GND

75 kΩto GND

150 kΩto GND

267 kΩto GND

Open

GND

75 kΩto GND

150 kΩto GND

267 kΩto GND

Open

GND

75 kΩto GND

150 kΩto GND

267 kΩto GND

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备注

1. TI recommends using low tolerance resistors on ADDR0 and ADDR1 to avoid address decoding

errors.

2. TI recommends connecting 10 pF capacitors in parallel with resistors on ADDR0 and ADDR1 pins

to improve noise immunity for correct address decoding.

8.3.14.2 SMBus^™Protocol

TPS25990 PMBus® interface is implemented over SMBus protocol using an I2C physical interface (SCL, SDA)

for robust link. The following features are supported:

• Fast mode support (up to 1 MHz I2C clock speed)

• Bus timeout

• Support for Byte, Word and Block Read/Write with and without PEC

• Group command support

• SMBus Alert output pin (SMBA#) to alert/interrupt the host during certain system warning/fault events.

• Alert Response Address (ARA) support

8.3.14.3 SMBus^™Message Formats

TPS25990 supports the following SMBus message formats.

备注

All these commands can be used with or without the optional PEC byte.

S

Target Address

W

A

Data Byte

A

P

PEC Byte

A

P

Controller to Target

Target to Controller

S = START, P = STOP, A = ACK, W = WRITE

图8-10. Send Byte

S

Target Address

R

A

Data Byte

N

A

P

PEC Byte

N P

S = START, P = STOP, A = ACK, N = NACK, R = READ

Controller to Target

Target to Controller

图8-11. Receive Byte

S

Target Address

W

A

Command ID

A

Data Byte

A

P

PEC Byte

A

P

Controller to Target

Target to Controller

S = START, P = STOP, A = ACK, W = WRITE

图8-12. Write Byte

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S

Target Address

W

A

Command ID

A

RS Target Address

R

A

Data Byte

N

A

P

PEC Byte

N P

S = START, RS = REPEATED START, P = STOP, A = ACK, N = NACK, R = READ, W = WRITE

Controller to Target

Target to Controller

图8-13. Read Byte

S

Target Address

W

A

Command ID

A

Low Data Byte

A

High Data Byte

A

P

W

PEC Byte

A

P

Controller to Target

Target to Controller

S = START, P = STOP, A = ACK, W = WRITE

图8-14. Write Word

YXXX

S

Target Address

W

A

Command ID

A

RS Target Address

R

A

Low Data Byte

Target Address

Low Data Byte

A

High Data Byte

Command ID

High Data Byte

N P

YXXX

S

W A

A

RS Target Address

A

PEC Byte

N P

S = START, RS = REPEATED START, P = STOP, A = ACK, N = NACK, R = READ, W = WRITE

Controller to Target

Target to Controller

图8-15. Read Word

YXXX

S

Target Address

W

A

Command ID

A

RS Target Address

R

A

YXXX

Byte Count (N)

A

Data Byte 1

A

Data Byte 2

A

Data Byte N

N

A

P

YXXX

S

Target Address

W

A

Command ID

A

RS Target Address

R

A

YXXX

Byte Count (N)

A

Data Byte 1

A

Data Byte 2

A

Data Byte N

PEC Byte

N P

S = START, RS = REPEATED START, P = STOP, A = ACK, N = NACK, R = READ, W = WRITE

Controller to Target

Target to Controller

图8-16. Block Read

8.3.14.4 Packet Error Checking

TPS25990 supports optional PEC for all SMBus transactions.

When using packet error checking, an additional byte is added before the stop bit in each transaction.

For reads, the PEC byte is read from the target and the controller compares it to its own PEC byte calculation.

For writes, the PEC byte is sent to the target from the controller, and the target compares it to its own PEC byte

calculation.

After the comparison, if the PEC bytes differ, the target detects a PEC error. Thereafter, it takes the following

actions as per the PMBus® Specification:

• Does not respond to or act upon the command

• Flushes the command code and any received data

• Sets the CML_ERR bit in the STATUS_BYTE register

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• Sets the INV_PEC bit in the STATUS_CML register

and

• Notifies the controller of a fault condition by pulling the SMBA# line low

8.3.14.5 Group Commands

As required by PMBus® specification, TPS25990 supports the Group Command Protocol. The Group Command

Protocol is used to send commands to more than one PMBus® target device. The commands are sent in one

continuous transmission. When the target devices detect the STOP condition that ends the sending of

commands, they all begin executing the command they received.

It is not necessary that all target devices receive the same command.

No more than one command can be sent to any one device in one Group Command packet.

The Group Command Protocol must not be used with commands that require the receiving device to respond

with data, such as the STATUS_BYTE command.

The Group Command Protocol uses REPEATED START conditions to separate commands for each device. The

Group Command Protocol begins with the START condition, followed by the seven bit address of the first target

device to receive a command and then by the write bit zero (0). The secondary device ACKs and the host

controller sends a command with the associated data byte or bytes.

After the last data byte is sent to the first device, the host controller does NOT send a STOP condition. Instead, it

sends a REPEATED START condition, followed by the seven bit address of the second device to receive a

command, a write bit and the command code and the associated data bytes.

If, and only if, this is the last target device to receive a command, the host controller sends a STOP condition.

Otherwise, the host controller sends a REPEATED START condition and starts transmitting the address of the

third device to receive a command.

This process continues until all target devices have received their command codes, data bytes, and if used and

supported, PEC byte. Then when all target devices have received their information, the host controller sends a

STOP condition.

If PEC is used, then each target device’s sub-packet has its own PEC byte, computed only for that device’s

sub-packet, including that target device’s address.

When the target devices who have received a command through this protocol detect the STOP condition, they

are to begin execution immediately of the received command.

When using Packet Error Checking with the Group Command Protocol, the PEC byte is calculated using only the

address, command and data bytes for each target device. For example, PEC 1 is calculated using Device

Address 1 including the Write bit, Command Code 1, and the data associated with Command Code 1. PEC 1

need only be calculated by the device at Device Address 1.

Similarly, PEC Byte 2 is calculated using Device Address 2 including the Write bit, Command Code 2, and the

data associated with Command Code 2. Device 1 must not continue calculating PEC 1 after it sees the

Repeated Start.

8.3.14.6 SMBus^™Alert Response Address (ARA)

When there are multiple target devices on the bus with their SMBA# pins also tied together, if one or more target

devices assert the SMBA#, the host controller needs a way to identify those target devices on the bus. It does so

using the ARA mechanism, which is initiated by sending a read command to the ARA broadcast address 0x0C.

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S

ARA (0x0C)

R

A

Target Address

X

N

A

P

PEC Byte

N P

S = START, P = STOP, A = ACK, N = NACK, R = READ

Controller to Target

Target to Controller

图8-17. ARA Message Protocol

The ARA Automatic Mask is a mask that is set in response to a successful ARA read. An ARA read operation

returns the PMBus® address of the lowest addressed target device on the bus that has its SMBA# asserted. A

successful ARA read means that this target device was the one that returned its address. When a target device

responds to the ARA read, it releases the SMBA# signal. When the last target device on the bus that has an

SMBA# set has successfully reported its address, the SMBA# signal will de-asserted.

The way that the TPS25990 releases the SMBA# signal is by setting the ARA Automatic mask bit for all fault

conditions present at the time of the ARA read. All status registers will still show the fault condition, but it will not

generate an SMBA# alert on that fault again until the ARA Automatic mask is cleared by the host issuing the

CLEAR_FAULTS command to this part. This must be done as a routine part of servicing an SMBA# condition on

a part, even if the ARA read is not done.

8.3.14.7 PMBus^®Commands

表8-6 shows the list of PMBus® commands supported by the TPS25990 eFuse.

表8-6. TPS25990 PMBus^®Commands List

Stored in

On-chip

Default

Value

Stored in

EEPROM

Command Name Code

Type

Description

PMBus®Transaction

Non-

volatile

Memory

OPERATION

01h

Control

eFuse ON/OFF control

Read/Write byte w/ PEC 0x80

N/A

Clear all fault status bits and

Blackbox RAM

CLEAR_FAULTS 03h

Control

Send byte w/ PEC

N/A

Initialize/Reset all

RESTORE_FACT

12h

configuration registers to their Send byte w/ PEC

factory default values

N/A

ORY_DEFAULTS

STORE_USER_A

Store configuration values to

Send byte w/ PEC

15h

LL

NVM/EEPROM

Initialize all configuration

RESTORE_USER

registers with the user

Send byte w/ PEC

16h

Control

N/A

_ALL

programmed values stored in

NVM/EEPROM

Erase Blackbox data in

Send byte w/ PEC

external EEPROM

BB_ERASE

F5h

F6h

Control

N/A

Fetch Blackbox EEPROM

contents into internal shadow Send byte w/ PEC

registers

FETCH_BB_EEP

ROM

Power down output and

restart after a delay

Send byte w/ PEC

POWER_CYCLE D9h

Control

N/A

programmed through the

RETRY_CONFIG register

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表8-6. TPS25990 PMBus^®Commands List (continued)

Stored in

On-chip

Non-

Default

Value

Stored in

EEPROM

Command Name Code

Type

Description

PMBus®Transaction

volatile

Memory

Enable/Disable write

protection for OPERATION &

MFR_WRITE_PR

F8h

Control

POWER_CYCLE commands, Read/write byte w/ PEC 0x00

configuration registers, NVM,

N/A

OTECT

and EEPROM

CAPABILITY

19h

78h

Telemetry

Supported PMBus® features Read byte w/ PEC

0xD0

Y

N

Y

N

Y

N

STATUS_BYTE

Status register lower byte

Status register word

OUT bus status

Read byte w/ PEC

Read word w/ PEC

Read byte w/ PEC

Undefined

STATUS_WORD 79h

STATUS_OUT

STATUS_IOUT

STATUS_INPUT

STATUS_TEMP

7Ah

7Bh

7Ch

7Dh

OUT current status

IN bus status

Device temperature status

Communications, Memory,

Logic status

STATUS_CML

7Eh

80h

Telemetry

Read byte w/ PEC

Undefined

N

Y

STATUS_MFR_S

PECIFIC

Manufacturer specific fault

status

STATUS_MFR_S

PECIFIC

_2

Additional manufacturer

specific fault status

F3h

98h

Telemetry

Read word w/ PEC

Read byte w/ PEC

Undefined

N

PMBus® Specifications Part I

PMBUS_REVISIO

N

and II rev

1.3

0x33

"TI"

Y

Block read 2 bytes w/

PEC

MFR_ID

99h

9Ah

Telemetry

Manufacturer name

Device name

N

Block read 8 bytes w/

PEC

MFR_MODEL

"TPS25990" Y

Block read 1 byte w/

PEC

MFR_REVISION 9Bh

Device revision

0x01

Y

READ_VIN

READ_VOUT

READ_IIN

88h

8Bh

89h

Telemetry

Input voltage

Output voltage

Input current

Read word w/ PEC

Undefined

N

READ_TEMPERA

TURE_1

8Dh

Telemetry

Device temperature

Read word w/ PEC

Undefined

N

READ_VAUX

READ_PIN

D0h

97h

Telemetry

Auxiliary analog input voltage Read word w/ PEC

Undefined

N

Instantaneous input power

Accumulated input energy

Read word w/ PEC

Block read 6 bytes w/

PEC

READ_EIN

86h

Telemetry

Undefined

N

READ_VIN_AVG DCh

READ_VIN_MIN D1h

Telemetry

Average input voltage

Minimum input voltage

Read word w/ PEC

Undefined

N

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表8-6. TPS25990 PMBus^®Commands List (continued)

Stored in

On-chip

Non-

Default

Value

Stored in

EEPROM

Command Name Code

Type

Description

PMBus®Transaction

volatile

Memory

READ_VIN_PEAK D2h

Telemetry

Peak input voltage

Read word w/ PEC

Undefined

N

Y

READ_VOUT_AV

DDh

Average output voltage

N

G

READ_VOUT_MI

DAh

DEh

Telemetry

Minimum output voltage

Read word w/ PEC

Undefined

N

READ_IIN_AVG

Telemetry

Average input current

Peak input current

Read word w/ PEC

Undefined

N

Y

READ_IIN_PEAK D4h

READ_TEMP_AV

D6h

Telemetry

Average device temperature Read word w/ PEC

Undefined

N

Y

G

READ_TEMP_PE

D7h

Peak device temperature

Read word w/ PEC

AK

READ_PIN_AVG DFh

READ_PIN_PEAK D5h

Telemetry

Average input power

Peak input power

Read word w/ PEC

Undefined

N

READ_SAMPLE_

Block read 64 bytes w/

PEC

D8h

BUF

Telemetry

ADC sample buffer

Undefined

N

Y

Block read 7 bytes w/

PEC

READ_BB_RAM FDh

Blackbox RAM registers

Blackbox EEPROM content

READ_BB_EEPR

Block read 16 bytes w/

PEC

F4h

Telemetry

Undefined

N

Y

OM

BB_TIMER

FAh

FBh

Blackbox tick timer

Read byte w/ PEC

PMBus® device address for

PMBUS_ADDR

Configuration ADDR0 = Open and ADDR1 Read/write byte w/ PEC 0x40

= Open setting

Y

Input undervoltage warning

VIN_UV_WARN

VIN_UV_FLT

58h

59h

57h

55h

Configuration

Read/write word w/ PEC 0x0095

Read/write word w/ PEC 0x008D

Read/write word w/ PEC 0x00A5

Read/write word w/ PEC 0x000E

Read/write word w/ PEC 0x0095

Read/write word w/ PEC 0x008D

Read/write word w/ PEC 0x007E

Read/write word w/ PEC 0x0085

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

threshold

Input undervoltage fault

threshold

Input overvoltage warning

threshold

VIN_OV_WARN

VIN_OV_FLT

Input overvoltage fault

threshold

Output undervoltage warning

threshold

VOUT_UV_WARN 43h

Output threshold for Power

Good de-assertion

VOUT_PGTH

OT_WARN

OT_FLT

5Fh

51h

4Fh

Overtemperature warning

threshold

Overtemperature fault

threshold

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表8-6. TPS25990 PMBus^®Commands List (continued)

Stored in

On-chip

Non-

Default

Value

Stored in

EEPROM

Command Name Code

Type

Description

PMBus®Transaction

volatile

Memory

Input overpower warning

threshold

PIN_OP_WARN

IIN_OC_WARN

6Bh

5Dh

Configuration

Read/write word w/ PEC 0x00FF

N

Input overcurrent warning

threshold

N

Y

N

Y

Reference voltage for current

VIREF

E0h

Configuration regulation and protection

blocks

Read/write byte w/ PEC 0x32

GPIO_CONFIG_1

2

E1h

E2h

Configuration GPIO1 & GPIO2 configuration Read/write byte w/ PEC 0x00

Configuration GPIO3 & GPIO4 configuration Read/write byte w/ PEC 0x00

Y

GPIO_CONFIG_3

4

ALERT_MASK

FAULT_MASK

DBh

E3h

Configuration SMB Alert assertion mask

Configuration FLT assertion mask

Configuration Device configuration

Configuration Blackbox configuration

Read/write word w/ PEC 0x0100

Read/write word w/ PEC 0x0000

Read/write word w/ PEC 0x1400

Read/write byte w/ PEC 0x00

N

Y

N

Y

DEVICE_CONFIG E4h

BB_CONFIG

OC_TIMER

E5h

E6h

Transient overcurrent

Configuration

Read/write byte w/ PEC 0x14

N

blanking timer

RETRY_CONFIG E7h

ADC_CONFIG_1 E8h

ADC_CONFIG_2 E9h

Configuration Auto-retry configuration

Configuration ADC Configuration

Read/write byte w/ PEC 0x84

Read/write byte w/ PEC 0x00

Y

N

Y

N

Peak/Min/Average

Configuration

PK_MIN_AVG

EAh

Read/write byte w/ PEC 0x00

N

configuration

General purpose comparator

Configuration

VCMPxREF

EBh

ECh

EDh

Read/write byte w/ PEC 0xFF

Read/write byte w/ PEC 0x9D

Read/write byte w/ PEC 0xFF

Y

N

Y

N

reference thresholds

PSU_VOLTAGE

CABLE_DROP

Configuration PSU nominal voltage

Maximum cable voltage drop

Configuration

expected

General purpose DAC1

Configuration

GPDAC1

F0h

Read/write byte w/ PEC 0x00

Y

output current

General purpose DAC1

Configuration

GPDAC2

INS_DLY

F1h

F9h

Read/write byte w/ PEC 0x00

Y

output voltage

Configuration Insertion delay

8.3.14.7.1 Detailed Descriptions of PMBus® Commands

8.3.14.7.1.1 OPERATION (01h, Read/Write Byte)

OPERATION is a PMBus® standard command that controls the FET inside the eFuse in conjunction with the

input from the EN/UVLO pin. This command may be used to switch the eFuse ON and OFF under host control. It

is also used to re-enable the eFuse after a fault-triggered shutdown.

This command uses the PMBus® read or write byte protocol.

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表8-7. OPERATION Command Description

Bit

7

Name

ON

Value

Description

Default

Access

Enable

1

0

eFuse output enabled

eFuse output disabled

N/A

1

Read/Write

6:0

RESERVED

0000000

备注

• This command should be preceded by the MFR_WRITE_PROTECT command to unlock the

device first to prevent accidental/spurious writes.

• Writing an OFF command followed by an ON command will clear all the fault and warning bits in

the status registers. Writing only an ON command after a fault-triggered shutdown will not clear the

status registers.

• OFF command engages quick output discharge (QOD).

8.3.14.7.1.2 CLEAR_FAULTS (03h, Send Byte)

CLEAR_FAULTS is a standard PMBus® command that resets all latched warning/fault/status flags and de-

asserts the SMBA# signal. If a fault or warning condition still exists when the CLEAR_FAULTS command is

executed, the SMBA# signal may re-assert almost immediately or may not de-assert at all. Issuing the

CLEAR_FAULTS command alone will not cause the eFuse to switch back ON in the event of a turn-off due to

any fault. That must be done by issuing an OPERATION OFF command followed by OPERATION ON command

or a POWER_CYCLE command after the fault condition is cleared, or through an auto-retry sequence. This

command also clears the BB_RAM contents and resets the BB_TIMER register to zero (0). This command has

no effect on Blackbox EEPROM memory contents.

This command uses the PMBus® send byte protocol. There is no data byte for this command. This command is

write only.

备注

TI recommends sending the CLEAR_FAULTS command after every successful power-up of the

device to clear the warning and fault bits set in the status registers during initialization, if any. This also

ensures the SMBA# is de-asserted.

8.3.14.7.1.3 RESTORE_FACTORY_DEFAULTS (12h, Send Byte)

RESTORE_FACTORY_DEFAULTS is a standard PMBus® command that initializes or resets all the

configuration RAM registers to their hardware defaults. Read the INIT_DONE bit in the

STATUS_MFR_SPECIFIC_2 register to check if initialization was completed successfully.

This command uses the PMBus® send byte protocol. There is no data byte for this command. This command is

write only.

备注

This command should be preceded by the MFR_WRITE_PROTECT command to unlock the device

first to prevent accidental/spurious writes.

8.3.14.7.1.4 STORE_USER_ALL (15h, Send Byte)

STORE_USER_ALL is a standard PMBus® command that writes the contents of the certain Configuration RAM

registers to their respective non-volatile configuration memory (NVM) or EEPROM locations. The TPS25990 has

two (2) one-time programmable banks in the NVM which are available to the users to store their custom

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configurations. This command will try to write to NVM Bank-1 first if it’s not programmed yet. If NVM Bank-1 is

already programmed, it will attempt to write to NVM Bank-2 if it’s not programmed. If NVM Bank-2 is already

programmed, it will attempt to write to Page-2 of an external EEPROM if available and configured.

This command uses the PMBus® send byte protocol. There is no data byte for this command. This command is

write only.

备注

• This command should be preceded by the MFR_WRITE_PROTECT command to unlock the

device first to prevent accidental/spurious writes.

• The external EEPROM needs to be enabled by setting the EXT_EEPROM bit in the

DEVICE_CONFIG register. In addition, it is done by configuring two (2) of the four (4) GPIOs as

EECLK and EEDATA appropriately in the GPIO_CONFIG_12 and GPIO_CONFIG_34 registers.

Make sure those two (2) selected GPIO pins are physically connected to the EEPROM clock and

data pins respectively on the board.

• The MEMORY_FLT bit in the STATUS_CML register gets set if the STORE_USER_ALL command

is unsuccessful. TI recommends reading the STATUS_CML register after sending the

STORE_USER_ALL command to verify whether it was successful or not.

• The NVM inside the TPS25990x eFuse only has two (2) one-time programmable banks available

for user programming. If an external EEPROM is not used, before sending the STORE_USER_ALL

command the user should ensure that at least one bank of internal NVM is available for

programming by reading the CONFIG_NVM_STAT bit in the STATUS_MFR_SPECIFIC_2 register.

8.3.14.7.1.5 RESTORE_USER_ALL (16h, Send Byte)

RESTORE_USER_ALL is a standard PMBus® command that initializes certain configuration RAM registers to

their user programmed values from NVM or EEPROM.

This command uses the PMBus® send byte protocol. There is no data byte for this command. This command is

write only.

The device follows the following sequence in response to the command:

• If NVM Bank-2 is programmed, the device will read from Bank-2. If the computed checksum matches the

saved original checksum, the NVM configuration values will be loaded into the respective registers.

• Next, if an external EEPROM is connected as described in 节8.3.14.7.1.4, and there is a valid configuration

file in Page-2 of the connected EEPROM, the device will try to read from EEPROM Page-2. If the calculated

checksum matches the stored checksum, the configuration values from EEPROM will be transferred into the

device configuration registers.

• If NVM Bank-2 is not programmed, the device reads NVM Bank-1. If the calculated checksum matches the

stored checksum, NVM configuration values will be loaded into the configuration registers. If NVM Bank-1 is

not programmed, factory default values will be retained in the registers.

备注

• This command should be preceded by the MFR_WRITE_PROTECT command to unlock the

device first to prevent accidental/spurious writes.

• Read the MEMORY_FLT bit in the STATUS_CML register and the INIT_DONE bit in the

STATUS_MFR_SPECIFIC_2 register to check if initialization was completed successfully.

8.3.14.7.1.6 BB_ERASE (F5h, Send Byte)

BB_ERASE is a manufacturer specific command which fills the EEPROM Page-0 (where Blackbox information is

stored) with all zeroes (0).

This command uses the PMBus® send byte protocol. There is no data byte for this command. This command is

write only.

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备注

This command should be preceded by the MFR_WRITE_PROTECT command to unlock the device

first to prevent accidental accidental/spurious writes.

8.3.14.7.1.7 FETCH_BB_EEPROM (F6h, Send Byte)

FTECH_BB_EEPROM is a manufacturer specific command which loads the Blackbox contents from the external

EEPROM (Page-0) into the Blackbox shadow registers internal to the device.

Those values can then be read back through PMBus® using the READ_BB_EEPROM command.

This command uses the PMBus® send byte protocol. There is no data byte for this command. This command is

write only.

8.3.14.7.1.8 POWER_CYCLE (D9h, Send Byte)

POWER_CYCLE is a manufacturer specific command used to power down the output and power ON after a

delay. The delay can be configured using the RETRY_CONFIG register.

This command uses the PMBus® send byte protocol. There is no data byte for this command. This command is

write only.

备注

• This command should be preceded by the MFR_WRITE_PROTECT command to unlock the

device first to prevent accidental/spurious writes.

• If the device is turned OFF due a fault, issuing a POWER_CYCLE command alone doesn't alter

the state of the device. This command should be preceded by a CLEAR_FAULTS command.

• This command only attempts to reset the power path. Device state and register contents are

preserved.

• This command also engages quick output discharge (QOD) to discharge the output load and

checks if the output is fully discharged before starting again.

8.3.14.7.1.9 MFR_WRITE_PROTECT (F8h, Read/Write Byte)

MFR_WRITE_PROTECT is a manufacturer specific command used to lock or unlock access to the configuration

registers, NVM and EEPROM to prevent accidental/spurious PMBus® writes from altering the device

configuration. It also blocks access to the OPERATION, RESTORE_FACTORY_DEFAULTS,

STORE_USER_ALL, RESTORE_USER_ALL, BB_ERASE, and POWER_CYCLE commands to prevent

accidental/spurious PMBus® writes from altering the device state. The device is locked by default after power up

or enable recycling.

This command uses the PMBus® read or write byte protocol.

A valid unlock command contains a data byte with Bit[7] equal to one (1) followed by a 7-bit password that

matches a predefined pattern of 0x0100010. Writing 0xA2h in the MFR_WRITE_PROTECT register unlocks the

device. Writing 0x00h in the MFR_WRITE_PROTECT register locks the device.

备注

Writing a data byte other than 0xA2h or 0x00h in the MFR_WRITE_PROTECT register will not change

the lock status of the device, but will generate a CML error and set the INV_DATA bit in STATUS_CML

register.

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表8-8. MFR_WRITE_PROTECT Command Description

Bit

Name

Value

Description

Default

Lock Bit

Configuration

register/NVM space

locked

0

1

7

UNLOCK

0

Configuration

register/NVM space

unlocked

Read/Write

Password

Configuration

register/NVM space

locked

0000000

0100010

6:0

PWD

0000000

Configuration

register/NVM space

unlocked

8.3.14.7.1.10 CAPABILITY (19h, Read Byte)

CAPABILITY is a standard PMBus® command that allows a host system to determine some key capabilities of a

PMBus® device.

This command uses the PMBus® read byte protocol. There is one data byte formatted as shown in 表8-9.

表8-9. CAPABILITY Register Description

Bit

Name

Value

Description

Packet Error

Default

Access

Correction (PEC)

support

7

PEC Support

1

0

PEC supported

1

PEC not supported

Maximum bus

interface speed

00

01

10

100 kHz

400 kHz

1 MHz

6:5

Bus Speed

10

Read

Reserved for future

use

11

SMB Alert/Alert

Response Address

support

SMBA/ARA

supported

4

SMBA/ARA

Reserved

1

SMBA/ARA not

supported

0

3:0

0000

Reserved

0000

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8.3.14.7.1.11 STATUS_BYTE (78h, Read Byte)

The TPS25990 implements all PMBus® status registers relevant to an eFuse/Hot-swap power controller. 图8-18

shows a bit map of the TPS25990 status register.

STATUS_BYTE is a standard PMBus® command that returns one byte of information with a summary of the

most critical faults.

This command uses the PMBus® read byte protocol.

To clear bits in this register, the underlying faults must be removed and the CLEAR_FAULTS command must be

issued by the host controller.

表8-10. STATUS_BYTE Register Description

Bit

Name

Value

Description

Device busy status

Device is busy

Default

Access

1

0

7

BUSY

0

Device is not busy

FET drive status

FET gate driver

disabled

1

6

FET_OFF

0

FET gate drive

enabled

0

5:4

3

Reserved

00

Reserved

00

VIN undervoltage

VIN UV fault detected

1

0

VIN_UV_FLT

0

VIN UV fault not

detected

Overtemperature fault

Active bits set in

STATUS_TEMP

register

1

0

Read

2

STATUS_TEMP

No active bits set in

STATUS_TEMP

register

Communication,

Memory or Logic error

Active bits set in

STATUS_CML

register

1

0

1

0

1

CML_ERR

0

No active bits set in

STATUS_CML

register

An event other than

the ones listed in bits

7:1 has occurred

NONE_OF_THE_AB

OVE

0

An event other than

the ones listed in bits

7:1 has not occurred

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8.3.14.7.1.12 STATUS_WORD (79h, Read Word)

STATUS_WORD is a standard PMBus® command that returns two bytes of information with a summary of the

eFuse fault conditions.

This command uses the PMBus® read word protocol.

To clear the bits in this register, the underlying faults must be removed and the CLEAR_FAULTS command must

be issued by the host controller.

The low byte of STATUS_WORD is the same register as the STATUS_BYTE command. The STATUS_WORD

register contents are described in 图8-18 and 表8-11.

STATUS_WORD (79h)

High Byte

Low Byte [STATUS_BYTE (78h)]

UNKNOWN

RESERVED

BUSY

FET_OFF

RESERVED

VIN_UV_FLT

TEMP_FLT

CML_ERR

PGOODB

MFR_STATUS

INPUT_STATUS

IOUT_STATUS

OUT_STATUS

UNKNOWN

7

6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

STATUS_OUT

STATUS_CML

Register (7Ah)

Register (7Eh)

STATUS_IOUT

Register (7Bh)

STATUS_TEMP

Register (7Dh)

STATUS_IN

Register (7Ch)

STATUS_MFR_

SPECIFIC

STATUS_MFR_

SPECIFIC_2

Register (80h)

Register (F3h)

图8-18. Status Register Bit Map

English Data Sheet: SLVSGG4

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表8-11. STATUS_WORD Register Description

Name

Value

Description

Default

Access

OUTPUT fault status

Active bits set in the

STATUS_OUT

register

1

0

15

14

13

OUT_STATUS

0

No active bits set in

the STATUS_OUT

register

IOUT fault status

Active bits set in the

STATUS_IOUT

register

1

0

IOUT_STATUS

0

No active bits set in

the STATUS_IOUT

register

INPUT fault status

Active bits set in the

STATUS_INPUT

register

1

0

INPUT_STATUS

0

No active bits set in

the STATUS_INPUT

register

Read

Manufacturer specific

fault status

Active bits set in the

STATUS

1

0

_MFR_SPECIFIC

register

12

MFR_STATUS

0

No active bits set in

the STATUS

_MFR_SPECIFIC

register

Power Good status

PGOOD de-asserted

PGOOD asserted

Reserved

1

0

11

PGOODB

Reserved

1

10:9

00

An event other than

the ones listed in bits

15:1 has occurred

1

0

8

UNKNOWN

0

An event other than

the ones listed in bits

15:1 has not occurred

7:0

Same as STATUS_BYTE register

图8-19 depicts the relationship between the STATUS_BYTE register, the STATUS_WORD register and the more

detailed status registers.

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Based on the information in these bytes, the host can get more insight by reading the appropriate status

registers.

STATUS_OUT

RESERVED

STATUS_MFR_

7

6

5

4

3

2

1

0

SPECIFIC_2

15 RESERVED

14 RESERVED

13 PGOODB

12 SPFAIL

RESERVED

VOUT_UV_WARN

RESERVED

11 SC_FLT

RESERVED

10 OC_DET

RESERVED

9

8

7

6

5

4

3

2

1

0

EIN_OF_WARN

VIN_TRAN

STATUS_WORD

(Upper Byte)

EE_DET

STATUS_IOUT

RESERVED

EE_PROG

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

OUT_STATUS

IOUT_STATUS

INPUT_STATUS

MFR_STATUS

PGOODB

AVG_DONE

VIN_CABLE_FLT

RETRY_REC

POWER_CYCLE_REC

INIT_DONE

RESERVED

UNKNOWN

CONFIG_NVM_STAT

STATUS_BYTE

(Lower byte of

STATUS_WORD)

STATUS_TEMP

OT_FLT

STATUS_INPUT

7

6

5

4

3

2

1

0

7

VIN_OV_FLT

VIN_OV_WARN

VIN_UV_WARN

VIN_UV_FLT

RESERVED

OC_FLT

OT_WARN

6

5

4

3

2

1

0

RESERVED

7

6

5

4

3

2

1

0

BUSY

FET_OFF

RESERVED

VIN_UV_FLT

STATUS_TEMP

CML_ERR

UNKNOWN

OC_WARN

IN_OP_WARN

STATUS_MFR_

SPECIFIC

FET_FAULT_GD

FET_FAULT_GS

FET_FAULT_DS

BB_RAM_FULL

SOA_FLT

STATUS_CML

INV_CMD

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

INV_DATA

INV_PEC

MEMORY_FLT

RESERVED

OTHER

EXT_FLT

CMP2_FLT

CMP1_FLT

图8-19. Summary of the Status Registers

8.3.14.7.1.13 STATUS_OUT (7Ah, Read Byte)

STATUS_OUT is a standard PMBus® command that returns one data byte with contents as shown in 表8-12.

This command uses the PMBus® read byte protocol.

To clear the bits in this register, the underlying faults must be removed and the CLEAR_FAULTS command must

be issued by the host controller.

表8-12. STATUS_OUT Register Description

Bit

Name

Value

Description

Default

Access

7:6

Reserved

00

Reserved

00

VOUT undervoltage

warning

VOUT UV warning

threshold crossed

1

5

VOUT_UV_WARN

Reserved

Read

0

VOUT UV warning

0

threshold not crossed

4:0

00

Reserved

00

English Data Sheet: SLVSGG4

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8.3.14.7.1.14 STATUS_IOUT (7Bh, Read Byte)

STATUS_IOUT is a standard PMBus® command that returns one data byte with contents as shown in 表8-13.

表8-13. STATUS_IOUT Register Description

Bit

Name

Value

Description

Default

Access

7:0

Reserved

00000000

Reserved

000000000

Read

备注

The input and output current information is identical for this device, so all the bits in this register are

reserved. Refer to the STATUS_INPUT register instead for status information.

8.3.14.7.1.15 STATUS_INPUT (7Ch, Read Byte)

STATUS_INPUT is a standard PMBus® command that returns the status flags related to input voltage, current,

and power as shown in 表8-14.

This command uses the PMBus® read byte protocol.

To clear the bits in this register, the underlying faults must be removed and the CLEAR_FAULTS command must

be issued by the host controller.

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表8-14. STATUS_INPUT Register Description

Bit

Name

Value

Description

Default

VIN overvoltage fault

VIN OV fault

1

0

7

VIN_OV_FLT

threshold crossed

0

VIN OV fault

threshold not crossed

VIN overvoltage

warning

VIN OV warning

1

0

6

VIN_OV_WARN

threshold crossed

0

VIN OV warning

threshold not crossed

VIN undervoltage

warning

VIN UV warning

1

0

5

VIN_UV_WARN

threshold crossed

0

VIN UV warning

threshold not crossed

VIN undervoltage

fault

Read

VIN UV fault

1

4

3

VIN_UV_FLT

Reserved

threshold crossed

0

VIN UV fault

0

threshold not crossed

Reserved

Overcurrent fault

(Inrush & steady-

state)

Input current crossed

overcurrent fault

threshold (Inrush) or

OC_TIMER expired

after input current

crossed overcurrent

fault threshold

1

2

OC_FLT

0

(steady-state)

Input current below

overcurrent fault

threshold or

0

OC_TIMER not

expired

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表8-14. STATUS_INPUT Register Description (continued)

Name

Value

Description

Default

Access

Overcurrent warning

(Inrush & steady-

state)

Input current crossed

overcurrent warning

threshold

1

0

1

OC_WARN

0

Input current below

overcurrent warning

threshold

Overpower warning

Input overpower

warning threshold

crossed

1

0

IN_OP_WARN

0

Input overpower

warning threshold not

crossed

8.3.14.7.1.16 STATUS_TEMP (7Dh, Read Byte)

STATUS_TEMP is a standard PMBus® command that returns the status flags related to the overtemperature

fault and warning as shown in 表8-15.

This command uses the PMBus® read byte protocol.

To clear the bits in this register, the underlying faults must be removed and the CLEAR_FAULTS command must

be issued by the host controller.

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表8-15. STATUS_TEMP Register Description

Bit

Name

Value

Description

Default

Overtemperature fault

Device temperature

crossed

1

overtemperature fault

threshold (TSD/

OT_FLT)

7

OT_FLT

0

Device temperature

below

0

overtemperature fault

threshold (TSD/

OT_FLT)

Read

Overtemperature

warning

Device temperature

crossed

1

overtemperature

warning threshold

6

OT_WARN

Reserved

0

Device temperature

below

0

overtemperature

warning threshold

5:0

000000

Reserved

000000

8.3.14.7.1.17 STATUS_CML (7Eh, Read Byte)

STATUS_CML is a standard PMBus® command that returns the status flags related to communication, logic,

and memory faults as shown in 表8-16.

This command uses the PMBus® read byte protocol.

To clear the bits in this register, the underlying faults must be removed and the CLEAR_FAULTS command must

be issued by the host controller.

English Data Sheet: SLVSGG4

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表8-16. STATUS_CML Register Description

Name

Value

Description

Default

Access

Command status

Invalid/unsupported

command received

1

0

7

INV_CMD

0

Valid/supported

command received

Data status

Invalid/unsupported

data received

1

0

6

5

INV_DATA

INV_PEC

0

Valid/supported data

received

Packet Error Check

status

1

0

PEC failed

PEC passed

Read

Memory fault status

Memory related fault -

Configuration Memory

Content Invalid

(Empty or corrupted)

OR

1

STORE_USER_ALL

or

4

MEMORY_FLT

0

RESTORE_USER_A

LL commands

unsuccessful

No memory related

fault

0

3:1

0

Reserved

OTHER

000

Reserved

000

0

Other communications failure

备注

The SMBA# signal may be asserted due to a CML fault if the CML_ERR is unmasked in the

ALERT_MASK register. If there are multiple PMBus® devices on the same bus, TI recommends

unmasking the CML_ERR only while communicating with the TPS25990 and masking it at all other

times. This prevents TPS25990 from asserting the SMBA# due to CML faults generated by other

devices on the bus.

8.3.14.7.1.18 STATUS_MFR_SPECIFIC (80h, Read Byte)

STATUS_MFR_SPECIFIC is a standard PMBus® command that returns manufacturer-specific status

information as shown in 表8-17.

This command uses the PMBus® read byte protocol.

To clear the bits in this register, the underlying faults must be removed and the CLEAR_FAULTS command must

be issued by the host controller.

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表8-17. STATUS_MFR_SPECIFIC Register Description

Bit

Name

Value

Description

Default

FET fault type

1

0

Gate to drain fault

No gate to drain fault

FET fault type

7

FET_FAULT_GD

0

1

0

Gate to source fault

6

5

FET_FAULT_GS

FET_FAULT_DS

0

No gate to source

fault

FET fault type

1

0

Drain to source fault

No drain to source

fault

BB RAM fill status

Seven (7) events

1

0

have been recorded

4

3

BB_RAM_FULL

0

Seven (7) events not

yet recorded

FET SOA status

Device turned off due

to SOA limit violation

1

0

SOA_FLT

FET operating within

SOA limit

Read

External fault

Device turned off due

to SWEN pin being

pulled low externally

by another device in

parallel chain

1

0

2

EXT_FLT

0

SWEN pin not pulled

low externally by

another device in

parallel chain

AUX (CMP2)

comparator fault

indication

1

CMP2_FLT

1

0

CMP2 fault detected

0

CMP2 fault not

detected

TEMP/CMP (CMP1)

comparator fault

indication

0

CMP1_FLT

1

0

CMP1 fault detected

0

CMP1 fault not

detected

English Data Sheet: SLVSGG4

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8.3.14.7.1.19 STATUS_MFR_SPECIFIC_2 (F3h, Read Word)

STATUS_MFR_SPECIFIC_2 is a manufacturer specific command which returns additional status information as

shown in 表8-18.

This command uses the PMBus® read word protocol.

To clear the bits in this register, the underlying faults must be removed and the CLEAR_FAULTS command must

be issued by the host controller.

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表8-18. STATUS_MFR_SPECIFIC_2 Register Description

Bit

Name

Value

Description

Default

15:14

Reserved

00

Reserved

00

PGOOD status

PGOOD low

PGOOD high

1

0

13

12

PGOODB

SPFAIL

0

Single point failure

(ILIM/IMON/IREF)

Single point failure

detected

1

0

Single point failure

not detected

Short-circuit fault

threshold crossed

1

0

11

SC_FLT

Short-circuit fault

threshold not crossed

Overcurrent detected

(Inrush & steady-

state)

Input current crossed

overcurrent fault

threshold but

1

0

10

OC_DET

Read

OC_TIMER not

expired

0

Input current below

overcurrent fault

threshold

EIN register overflow

EIN register

overflowed

1

0

9

8

EIN_OF_WARN

0

EIN register not

overflowed

VIN transient warning

indication

VIN transient

detected

1

0

VIN_TRAN

VIN transient not

detected

External EEPROM

detect status

External EEPROM

detected

1

0

7

EE_DET

External EEPROM

not detected

English Data Sheet: SLVSGG4

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表8-18. STATUS_MFR_SPECIFIC_2 Register Description (continued)

Name

Value

Description

Default

Access

External EEPROM

programmed status

External EEPROM

programmed

1

0

6

EE_PROG

0

External EEPROM

not programmed

Average computation

complete status

Average computation

done

1

0

5

4

AVG_DONE

0

Average computation

ongoing

Read

Input cable fault

indication

1

0

Cable fault detected

VIN_CABLE_FLT

Cable fault not

detected

Fault recovery/retry

status

Device has recovered

from fault through

auto-retry

1

0

3

RETRY_REC

0

Normal power up i.e.

Device has not

recovered from fault

through auto-retry

Power Cycle

command status

Device has recovered

from power cycle

1

0

Read

POWER_CYCLE_RE

C

2

Normal power up i.e.

Device has not

recovered from power

cycle

0

Register Initialization

status

Register Initialization

Complete, All default/

Config values loaded

into RAM

1

0

1

INIT_DONE

0

Read

Register Initialization

not complete

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表8-18. STATUS_MFR_SPECIFIC_2 Register Description (continued)

Bit

Name

Value

Description

Default

Access

Configuration NVM

Read

Not available to be

programmed

1

0

CONFIG_NVM_STAT

0

Read

Available to be

programmed

8.3.14.7.1.20 PMBUS_REVISION (98h, Read Byte)

PMBUS_REVISION is a standard PMBus® command which returns the revision of the PMBus® standard to

which the device conforms.

The command has one data byte. Bits[7:4] indicate the revision of PMBus® specification Part I to which the

device is compliant. Bits[3:0] indicate the revision of PMBus® specification Part II to which the device is

compliant. To access this command, use the PMBus® read byte protocol.

This command returns 0x33h from the TPS25990x eFuse. This implies the device is compliant with Part I rev 1.3

and Part II rev 1.3.

8.3.14.7.1.21 MFR_ID (99h, Block Read)

MFR_ID is a standard PMBus® command that returns the manufacturer name.

This command uses the PMBus® block read protocol with a block size of two (2). This register contains

0x5449h, which represents "TI" in ASCII.

8.3.14.7.1.22 MFR_MODEL (9Ah, Block Read)

MFR_MODEL is a standard PMBus® command that returns the device part number.

This command uses the PMBus® block read protocol with a block size of eight (8). This register contains

0x5450533235393930h, which represents "TPS25990" in ASCII.

8.3.14.7.1.23 MFR_REVISION (9Bh, Block Read)

MFR_REVISION is a standard PMBus® command that returns the device revision.

This command uses the PMBus® block read protocol with a block size of one (1). This register contains 0x01h.

8.3.14.7.1.24 READ_VIN (88h, Read Word)

READ_VIN is a standard PMBus® command that returns the 10-bit measured input voltage value.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in V.

表8-19. READ_VIN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

input voltage

15:0

READ_VIN

0x0000 (0 V)

0x03FF (19.48 V)

Read

8.3.14.7.1.25 READ_VOUT (8Bh, Read Word)

READ_VOUT is a standard PMBus® command that returns the 10-bit measured output voltage value.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in V.

English Data Sheet: SLVSGG4

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表8-20. READ_VOUT Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

output voltage

15:0

READ_VOUT

0x0000 (0 V)

0x03FF (19.48 V)

Read

8.3.14.7.1.26 READ_IIN (89h, Read Word)

READ_IIN is a standard PMBus® command that returns the 10-bit measured input current value.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in A.

表8-21. READ_IIN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for input

current

15:0

READ_IIN

0x0000 (0 A)

0x03FF (107250/R_IMONA)

Read

8.3.14.7.1.27 READ_TEMPERATURE_1 (8Dh, Read Word)

READ_TEMPERATURE_1 is a standard PMBus® command that returns the 10-bit measured device

temperature value.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value °C.

表8-22. READ_TEMPERATURE_1 Register Description

Bit

Name

READ_TEMPERATU Value measured for

RE_1 device temperature

Description

Minimum Value

Maximum Value

Access

15:0

0x0000 (-229 °C)

0x03FF (501 °C)

Read

8.3.14.7.1.28 READ_VAUX (D0h, Read Word)

READ_VAUX is a manufacturer specific command that reports the 10-bit measured voltage on the AUX pin.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in V.

表8-23. READ_VAUX Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

auxiliary voltage

source connected at

the AUX pin

15:0

READ_VAUX

0x0000 (0 V)

0x03FF (1.95 V)

Read

备注

Voltages greater than or equal to 1.95 V to ground are reported as full scale (0x03FFh). Voltages less

than or equal to 0 V referenced to ground are reported as 0 V (0x0000h).

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8.3.14.7.1.29 READ_PIN (97h, Read Word)

READ_PIN is a PMBus® standard command which returns the input power (input voltage multiplied by input

current).

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in W.

表8-24. READ_PIN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

input power

15:0

READ_PIN

0x0000 (0 W)

0x03FF (2089230/R_IMONW)

Read

8.3.14.7.1.30 READ_EIN (86h, Block Read)

The READ_EIN command is a standard PMBus® command which returns information to the host for computing

the accumulated energy and average power consumption by a system powered by the eFuse. The information

provided by this command is independent of any device specific averaging period, sampling frequency, or

calculation algorithm.

This command uses the PMBus® block read protocol with a block size of six (6).

This command returns six (6) bytes of data. The first two (2) bytes are the two's complement and signed output

of an accumulator that continuously sums samples of the instantaneous input power (the product of the samples

of the input voltage and input current). These two data bytes are encoded in the DIRECT format as described in

节 8.3.14.10. The accumulator values are scaled so that the units are in “watt-samples”. This value in “watt-

samples” must be multiplied by the effective ADC sampling period to obtain the real world value of energy

accumulation in joules. If Bit[3] of the DEVICE_CONFIG register is set to high, the effective ADC sampling

period is 18 µs (typical). Otherwise, it will be 11 µs (typical) by default.

The third data byte, ROLLOVER_COUNT is a count of rollover events for the accumulator. This byte is an

unsigned integer indicating the number of times the accumulator has rolled over from its maximum positive value

of 7FFFh to zero. The ROLLOVER_COUNT will periodically roll over from its maximum positive value to zero. It

is up to the host to keep track of the state of the ROLLOVER_COUNT and account for the rollovers.

The other three (3) data bytes are a 24-bit unsigned integer that counts the number of samples of the

instantaneous input power accumulated till now. This value will also roll over periodically from its maximum

positive value to zero.

The combination of the accumulator and the rollover count may overflow within a few seconds. It is left to the

host software to detect this overflow and handle it appropriately. Similarly, the sample count value will overflow.

However, this event only occurs every five (5) minutes if Bit[3] of the DEVICE_CONFIG register is set to high,

otherwise every three (3) minutes.

表8-25. READ_EIN Register Description

BYTE

Description

DEFAULT

Access

0

1

2

3

4

5

Power Accumulator Low Byte

Power Accumulator High Byte

Power Accumulator Rollover Count

Sample Count Low byte

0x00

Read

0x00

Sample Count Mid byte

0x00

Sample Count High byte

0x00

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The host uses the accumulator value and rollover count to calculate the current “energy count” in “watt-

samples”using 方程式15.

Energy_Count = Rollover_Count × Accumulator_Roll_Over_Value + Accumulator_Value

(15)

Where the Accumulator_Roll_Over_Value is the maximum possible positive value of the accumulator plus one

(1). It is necessary to add one (1) to the maximum accumulator value to make the average power calculation

correctly. The Accumulator_Roll_Over_Value is calculated using 方程式16.

1

m

−R

1

m

15

−R

Accumulator_Roll_Over_Value =

Y

+ 1 × 10

− b =

2

× 10

− b

(16)

MAX

表 8-67 includes the "m, b, R" coefficients used in 方程式 16. Accumulator_Value is obtained using the

coefficients in 表 8-67 and 方程式 19. The real world value of energy accumulation in joules is calculated using

方程式17.

Accumulated_Energy = Energy_Count × Effective_ADC_Sampling_Period

(17)

If Bit[3] of the DEVICE_CONFIG register is set to high, the Effective_ADC_Sampling_Period is 18 µs (typical).

Otherwise, it will be 11 µs (typical) by default. The host calculates the average power in watt since the last

reading using 方程式18.

Current_Energy_Count − Last_Energy_Count

Current_Sample_Count − Last_Sample_Count

Average_Power =

(18)

备注

The ADC HI PERF bit in the DEVICE_CONFIG register) defines the ADC internal operating modes.

The effective ADC sampling period is 11 µs in normal mode and 18 µs in high performance mode. The

device is configured for normal mode by default. If it is necessary to change the ADC internal modes,

it must be done before the downstream loads are enabled. It should not be changed under normal

operation. This results in the wrong real world value for energy accumulation.

8.3.14.7.1.31 READ_VIN_AVG (DCh, Read Word)

READ_VIN_AVG is a manufacturer-specific command that reports 10-bit average value of input voltage.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in V.

表8-26. READ_VIN_AVG Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

15:0

READ_VIN_AVG

0x0000 (0 V)

0x03FF (19.48 V)

Read

average input voltage

The sample count for averaging can be programmed through PMBus® using Bit[2:0] in the PK_MIN_AVG

register. The contents of READ_VIN_AVG register can be reset to zero (0x0000h) by setting Bit[6] in the

PK_MIN_AVG register.

8.3.14.7.1.32 READ_VIN_MIN (D1h, Read Word)

READ_VIN_MIN is a manufacturer-specific command that reports 10-bit minimum input voltage measured since

a power-on reset or the last RESET_MIN (Bit[5] in the PK_MIN_AVG register) made high.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in V.

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表8-27. READ_VIN_MIN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Value measured for

minimum input

15:0

READ_VIN_MIN

0x0000 (0 V)

0x03FF (19.48 V)

Read

voltage since reset or

last clear

8.3.14.7.1.33 READ_VIN_PEAK (D2h, Read Word)

READ_VIN_PEAK is a manufacturer-specific command that reports 10-bit maximum input voltage measured

since a power-on reset or the last RESET_PEAK (Bit[7] in the PK_MIN_AVG register) command issued.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in V.

表8-28. READ_VIN_PEAK Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

maximum input

voltage since reset or

last clear

15:0

READ_VIN_PEAK

0x0000 (0 V)

0x03FF (19.48 V)

Read

8.3.14.7.1.34 READ_VOUT_AVG (DDh, Read Word)

READ_VOUT_AVG is a manufacturer-specific command that reports 10-bit average values of output voltage

telemetry. Data are updated with each data cycle, reducing averaged telemetry read latency. Average count can

be programmed through PMBus® using Bit[2:0] in the PK_MIN_AVG register. The contents of

READ_VOUT_AVG register can be reset to zero (0x0000h) by setting Bit[6] in the PK_MIN_AVG register high.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in V.

表8-29. READ_VOUT_AVG Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

15:0

READ_VOUT_AVG average output

voltage

0x0000 (0 V)

0x03FF (19.48 V)

Read

8.3.14.7.1.35 READ_VOUT_MIN (DAh, Read Word)

READ_VOUT_MIN is a manufacturer-specific command that reports 10-bit minimum output voltage measured

since a power-on reset or the last RESET_MIN (Bit[5] in the PK_MIN_AVG register) made high.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in V.

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表8-30. READ_VOUT_MIN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

minimum output

voltage since reset or

last clear

15:0

READ_VOUT_MIN

0x0000 (0 V)

0x03FF (19.48 V)

Read

8.3.14.7.1.36 READ_IIN_AVG (DEh, Read Word)

READ_IIN_AVG is a manufacturer-specific command that reports 10-bit average values of input current

telemetry. Data are updated with each data cycle, reducing averaged telemetry read latency. Average count can

be programmed through PMBus® using Bit[2:0] in the PK_MIN_AVG register. The contents of READ_IIN_AVG

register can be reset to zero (0x0000h) by setting Bit[6] in the PK_MIN_AVG register to high.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in A.

表8-31. READ_IIN_AVG Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

average input current

15:0

READ_IIN_AVG

0x0000 (0 A)

0x03FF (107250/R_IMONA)

Read

8.3.14.7.1.37 READ_IIN_PEAK (D4h, Read Word)

READ_IIN_PEAK is a manufacturer-specific command that reports 10-bit maximum input current measured

since a power-on reset or the last RESET_PEAK (Bit[7] in the PK_MIN_AVG register) made high.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in A.

表8-32. READ_IIN_PEAK Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

15:0

READ_IIN_PEAK maximum input current

since reset or last clear

0x0000 (0 A)

0x03FF (107250/R_IMONA)

Read

8.3.14.7.1.38 READ_TEMP_AVG (D6h, Read Word)

The READ_TEMP_AVG command is a manufacturer-specific command that reports 10-bit average values of

device temperature or auxiliary input voltage telemetry based on the state of Bit[7] in the ADC_CONFIG_2

register. If this bit is set high, the READ_TEMP_AVG command reports average values of auxiliary input voltage

telemetry, otherwise average values of device temperature telemetry. Default state of Bit[7] in the

ADC_CONFIG_2 register is low. Data are updated with each data cycle, reducing averaged telemetry read

latency. Average count can be programmed through PMBus® using Bit[2:0] in the PK_MIN_AVG register. The

contents of READ_TEMP_AVG register can be reset to zero (0x0000h) by setting Bit[6] in the PK_MIN_AVG

register high.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in °C or V.

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表8-33. READ_TEMP_AVG Register Description

Bit[7] in the

ADC_CONFIG_2

register

Bit

Name

Description

Minimum Value Maximum Value

Value measured

for average

auxiliary input

voltage

1

0

READ_VAUX_AVG

0x0000 (0 V)

0x03FF (1.95 V)

15:0

Read

Value measured

for average

device

READ_TEMP_AVG

0x0000 (-229 °C) 0x03FF (501 °C)

temperature

Make sure to use the DIRECT format calculation coefficients correctly based on the state of Bit[7] in

the ADC_CONFIG_2 register.

8.3.14.7.1.39 READ_TEMP_PEAK (D7h, Read Word)

READ_TEMP_PEAK is a manufacturer-specific command that reports 10-bit maximum device temperature

measured since a power-on reset or the last RESET_PEAK (Bit[7] in the PK_MIN_AVG register) made high.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in °C.

表8-34. READ_TEMP_PEAK Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

maximum device

temperature since

reset or last clear

15:0

READ_TEMP_PEAK

0x0000 (-229 °C)

0x03FF (501 °C)

Read

8.3.14.7.1.40 READ_PIN_AVG (DFh, Read Word)

READ_PIN_AVG is a manufacturer-specific command that reports 10-bit average values of input power

telemetry. Data are updated with each data cycle, reducing averaged telemetry read latency. Average count can

be programmed through PMBus® using Bit[2:0] in the PK_MIN_AVG register. The contents of this register can

be reset to zero (0x0000h) by setting Bit[6] in the PK_MIN_AVG register high.

This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in W.

表8-35. READ_PIN_AVG Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

average input power

15:0

READ_PIN_AVG

0x0000 (0 W)

0x03FF (2089230/R_IMONW)

Read

8.3.14.7.1.41 READ_PIN_PEAK (D5h, Read Word)

READ_PIN_PEAK is a manufacturer-specific command that reports 10-bit maximum input power measured

since a power-on reset or the last RESET_PEAK (Bit[7] in the PK_MIN_AVG register) made high.

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This command uses the PMBus® read word protocol.

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data read from this register into a real-world value in W.

表8-36. READ_PIN_PEAK Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Access

Value measured for

15:0

READ_PIN_PEAK maximum input power

since reset or last clear

0x0000 (0 W)

0x03FF (2089230/R_IMONW)

Read

8.3.14.7.1.42 READ_SAMPLE_BUF (D8h, Block Read)

READ_SAMPLE_BUF is a manufacturer-specific command used to read the latest sixty-four (64) samples of a

particular parameter from a round-robin ADC buffer available in the device RAM. This allows multiple ADC

samples to be captured at a higher speed and read out at on go without the bottleneck of reading individual

samples sequentially over the PMBus® serial interface. This allows the system designer to reconstruct the time

domain profile/waveform of that parameter in a given time interval. This could be useful during design or system

debugging by functioning like an in-built "digital oscilloscope". The rate at which ADC samples are updated in the

buffer depends on the effective ADC sampling period and the decimation rate/sample skip count. If Bit[3] of the

DEVICE_CONFIG register is set to high, the effective ADC sampling period is 18 µs (typical). Otherwise, it will

be 11 µs (typical) by default. The ADC channel to sample for buffering and the decimation rate/sample skip count

can be configured through the ADC_CONFIG_2 register. By selecting different decimation rates, users can

choose between “fine time resolution with short aperture”and “coarse time resolution with wide aperture”.

This command uses the PMBus® block read protocol with a block size of sixty-four (64).

Follow the PMBus® DIRECT format conversion using the coefficients in 表 8-67 and 方程式 19, to convert the

hexadecimal data bytes into their real-world values in the appropriate unit.

The ADC sample buffer starts buffering as soon as the device powers up. The buffering is paused under two

different conditions:

1. The instant READ_SAMPLE_BUF command is issued. This ensures the sample buffer is not overwritten

with new values while the host is reading out the previous set of values. After sixty-four (64) bytes have been

read, it will again start buffering new samples.

2. In the event of a fault, which is latched internally as shown in 表8-2. This ensures the snapshot of the

samples prior to the fault event is preserved even if there's a delay from host in reading out the sample

buffer. After issuing the CLEAR_FAULTS command, or writing OPERATION OFF command followed by

OPERATION ON command, or toggling the EN/UVLO pin, it will again start buffering new samples.

图8-20. ADC Sample Buffering Example

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f_S

Skip count = 0

10-bits

. . . .

0

1

2

63

64

ADC

ADC raw output

8-bits

0

1

2

PMBus Block Read

ADC sample bu er

f_S

Skip count = 2

10-bits

. . . .

0

1

2

3

4

5

6

187 188 189

190 191 192

ADC

ADC raw output

8-bits

. . . .

PMBus Block Read

ADC sample bu er

63

1

2

备注

The ADC samples are truncated from 10-bits to 8-bits while filling up the ADC sample buffer. Make

sure to use the DIRECT format calculation coefficients correctly.

8.3.14.7.1.43 READ_BB_RAM (FDh, Block Read)

READ_BB_RAM is a manufacturer-specific command used to read the contents of the Blackbox buffer RAM,

which is seven (7) bytes deep as described in 节8.3.14.11.

This command uses the PMBus® block read protocol with a block size of seven (7).

表 8-37 presents details of the Blackbox RAM registers. There are seven (7) Blackbox RAM registers, starting

from BB_RAM_0 to BB_RAM_6. Descriptions of all seven (7) registers (BB_RAM_0 to BB_RAM_6) are identical.

表8-37. BB_RAM Register Description

Bit

Name

Value

Description

Event identifier

VIN_UV_WARN

VIN_OV_WARN

OC_WARN

Default

Access

111

110

101

100

011

010

001

000

OT_WARN

7:5

EVENT_ID

000

OC_DET

VIN_TRAN

IN_OP_WARN

None

Read

Blackbox timer expiry

Blackbox timer

overflowed at least

once since the last

event

1

4

BB_TMR_EXP

BB_TICK

0

Blackbox timer has

not overflowed

0

3:0

0000

Blackbox tick timer

0000

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The Blackbox RAM contents get reset under the following events:

• Input power recycle at VIN or VDD pin

• ENABLE recycling

• CLEAR_FAULTS command

• OPERATION OFF command followed by OPERATION ON command

• Initiation of an auto-retry sequence

8.3.14.7.1.44 READ_BB_EEPROM (F4h, Block Read)

READ_BB_EEPROM is a manufacturer-specific command used to read contents stored in the Blackbox shadow

registers internal to the TPS25990 eFuse. Before issuing this command, the FETCH_BB_EEPROM command

needs to be sent to load the Blackbox contents from the external EEPROM (Page-0) as described in 节

8.3.14.11 into the Blackbox shadow registers. READ_BB_EEPROM retrieves sixteen (16) bytes of Blackbox

information stored in the EEPROM as shown below.

• BB_RAM_0 to BB_RAM_6 [Seven (7) bytes]

• BB_TIMER [One (1) byte]

• STATUS_WORD [Two (2) bytes]

• STATUS_MFR_SPECIFIC [One (1) byte]

• STATUS_INPUT [One (1) byte]

• VIN_PEAK [One (1) byte, Eight (8) MSBs from the 10-bit ADC output data]

• IIN_PEAK [One (1) byte, Eight (8) MSBs from the 10-bit ADC output data]

• TEMPERATURE_PEAK [One (1) byte, Eight (8) MSBs from the 10-bit ADC output data]

• CHECKSUM [One (1) byte]

This command uses the PMBus® block read protocol with a block size of sixteen (16).

VIN_PEAK, IIN_PEAK, and TEMPERATURE_PEAK data use the PMBus® DIRECT format. Use the coefficients

in 表 8-67 and 方程式 19 to convert the hexadecimal data read from these registers into their real-world value in

the appropriate units.

备注

The peak input voltage, input current, and temperature values are truncated from 10-bits to 8-bits

while stored in an external EEPROM. Make sure to use the DIRECT format calculation coefficients

correctly.

8.3.14.7.1.45 BB_TIMER (FAh, Read Byte)

BB_TIMER is a manufacturer-specific command used to read the following:

• Blackbox RAM address pointer, indicating which Blackbox RAM has been filled to date. After filling up all

seven (7) Blackbox RAM locations, it resets to zero.

• Blackbox timer expiry bit, showing if the Blackbox tick timer has overflowed at least once since the last event.

This bit indicates if the Blackbox RAM event entries are relatively recent or old. This bit is latched when the

timer overflows and resets to zero along with the free running timer when the next event occurs.

• Blackbox tick timer, a free running timer, which is reset to zero after every event. The timer update rate can

be configured through the BB_CONFIG register. This allows users to tradeoff between fine resolution and

longer time span depending on their debugging needs.

To access the BB_TIMER register, use the PMBus® read byte protocol. The whole content of this register resets

to zero (0) at the instant the CLEAR_FAULTS command is issued. The details of the BB_TIMER register are

shown in 表8-38.

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表8-38. BB_TIMER Register Description

Bit

Name

Value

Description

Default

BB RAM address

pointer

Either all seven (7)

Blackbox RAM

registers are empty or

all are filled up till

date

000

BB_RAM_0 filled up

till date

001

010

BB_RAM_0 and

BB_RAM_1 filled up

till date

BB_RAM_0,

BB_RAM_1, and

BB_RAM_2 filled up

till date

011

100

BB_RAM_0,

7:5

BB_PTR

BB_RAM_1,

000

BB_RAM_2, and

BB_RAM_3 filled up

till date

BB_RAM_0,

BB_RAM_1,

BB_RAM_2,

BB_RAM_3, and

BB_RAM_4 filled up

till date

Read

101

BB_RAM_0,

BB_RAM_1,

BB_RAM_2,

BB_RAM_3,

BB_RAM_4, and

BB_RAM_5 filled up

till date

110

111

Reserved

Blackbox timer expiry

Blackbox timer

overflowed at least

once since the last

event

1

0

4

BB_TMR_EXP

BB_TICK

0

Blackbox timer has

not overflowed

3:0

Blackbox timer

0000

8.3.14.7.1.46 PMBUS_ADDR (FBh, Read/Write Byte)

PMBUS_ADDR is a manufacturer-specific command used for reading and configuring a user-specific device

address apart from the addresses mentioned in 表 8-5. The device uses this address for I2C communication

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instead of the default value (0x40) when ADDR0 and ADDR1 pins are OPEN. This updated device address can

be stored in the NVM and the device responds to this revised address upon power up next time.

This command uses the PMBus® read or write byte protocol.

8.3.14.7.1.47 VIN_UV_WARN (58h, Read/Write Word)

VIN_UV_WARN is a standard PMBus® command for configuring or reading an 8-bit threshold for the input

undervoltage warning detection. This command uses the PMBus® DIRECT format. When reading and writing to

this register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 to convert between real word units

and hexadecimal values. This command uses the PMBus® read or write word protocol.

Contents of this register are compared to the VIN ADC telemetry value. If the measured VIN value falls below

the value in this register, the VIN_UV_WARN flags are set in the respective registers. The SMBA# signal is

asserted. When the input voltage rises above the VIN_UV_WARN threshold, and the CLEAR_FAULTS

command is sent afterwards, this warning flag and alert are cleared.

表8-39. VIN_UV_WARN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Input undervoltage

warning threshold

15:0

VIN_UV_WARN

0x0000 (0 V)

0x00FF (19.42 V) 0x0095h (11.35 V)

Read/Write

When an input undervoltage warning is detected, the device:

• sets the NONE_OF_THE_ABOVE/UNKNOWN bit in the STATUS_BYTE register

• sets the INPUT_STATUS bit in the upper byte of the STATUS_WORD register

• sets the VIN_UV_WARN bit in the STATUS_INPUT register

• fills-up one of the Blackbox RAM registers (if available to write) writing the event identifier as VIN_UV_WARN

and relative time stamp information

• increases the Blackbox RAM address pointer in the BB_TIMER register by one (1) if it was previously less

than six (6), otherwise resets to zero (0). This change in the address pointer only occurs if one of the

Blackbox RAM registers is available to write.

• notifies the host by asserting SMBA#, if it is not masked setting the STATUS_IN bit in the ALERT_MASK

register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34 register

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.48 VIN_UV_FLT (59h, Read/Write Word)

VIN_UV_FLT is a standard PMBus® command for configuring or reading an 8-bit threshold for the input

undervoltage fault detection. This command uses the PMBus® DIRECT format. When reading and writing to this

register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 to convert between the real world units

and hexadecimal values.

This command uses the PMBus® read or write word protocol.

Contents of this register are compared to the VIN ADC telemetry value. Once the input voltage has fallen below

the undervoltage fault threshold, the output is turned off, and the VIN_UV_FLT flags are set in the respective

registers. The SMBA# signal is asserted. 250 mV (typical) of hysteresis is added to the value in this register. This

is to provide the rising threshold the input voltage must rise above for this fault to clear. Once the input voltage

rises above the rising threshold, the output is turned back on. However, the fault flags and alerts remain until

cleared by the host by sending the CLEAR_FAULTS command.

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表8-40. VIN_UV_FLT Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Input undervoltage

fault threshold

15:0

VIN_UV_FLT

0x0000 (0 V)

0x00FF (19.42 V)

0x008Dh (10.74 V)

Read/Write

When an input undervoltage fault is detected, the device:

• sets the FET_OFF, VIN_UV_FLT, and NONE_OF_THE_ABOVE/UNKNOWN bits in the STATUS_BYTE

register

• sets the OUT_STATUS, INPUT_STATUS, PGOODB, and NONE_OF_THE_ABOVE/UNKNOWN bits in the

upper byte of the STATUS_WORD register

• sets the VOUT_UV_WARN bit in the STATUS_OUT register

• sets the VIN_UV_FLT bit in the STATUS_INPUT register

• sets the PGOODB bit in the STATUS_MFR_SPECIFIC_2 register

• notifies the host by asserting SMBA#, if it is not masked setting the STATUS_IN, PGOODB, and

STATUS_OUT bits in the ALERT_MASK register and the GPIO4 pin is configured as SMBA# Output in the

GPIO_CONFIG_34 register

• deasserts the external PGOOD signal, if the GPIO1 pin is configured as PGOOD output in the

GPIO_CONFIG_12 register

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.49 VIN_OV_WARN (57h, Read/Write Word)

VIN_OV_WARN is a standard PMBus® command for configuring or reading an 8-bit threshold for the input

overvoltage warning detection. This command uses the PMBus® DIRECT format. When reading and writing to

this register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 to convert between the real world

units and hexadecimal values.

This command uses the PMBus® read or write word protocol.

Contents of this register are compared to the VIN ADC telemetry value. If the measured VIN value rises above

the value in this register, the VIN_OV_WARN flags are set in the respective registers. The SMBA# signal is

asserted. When the input voltage falls below the VIN_OV_WARN threshold, and the CLEAR_FAULTS command

is sent afterwards, this warning flag and alert are cleared.

表8-41. VIN_OV_WARN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Input overvoltage

warning threshold

15:0

VIN_OV_WARN

0x0000 (0 V)

0x00FF (19.42 V) 0x00A5h (12.57 V)

Read/Write

When an input overvoltage warning is detected, the device:

• sets the NONE_OF_THE_ABOVE/UNKNOWN bit in the STATUS_BYTE register

• sets the INPUT_STATUS bit in the upper byte of the STATUS_WORD register

• sets the VIN_OV_WARN bit in the STATUS_INPUT register

• fills-up one of the Blackbox RAM registers (if available to write) writing the event identifier as VIN_OV_WARN

and relative time stamp information

• increases the Blackbox RAM address pointer in the BB_TIMER register by one (1) if it was previously less

than six (6), otherwise resets to zero (0). This change in the address pointer only occurs if one of the

Blackbox RAM registers is available to write.

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• notifies the host by asserting SMBA#, if it is not masked setting the STATUS_IN bit in the ALERT_MASK

register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34 register

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.50 VIN_OV_FLT (55h, Read/Write Word)

VIN_OV_FLT is a standard PMBus® command for configuring or reading a 4-bit threshold for the input

overvoltage fault detection. This command uses the PMBus® DIRECT format. When reading and writing to this

register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 to convert between the real world units

and hexadecimal values.

This command uses the PMBus® read or write word protocol.

Contents of this register drive a DAC to set the thresholds for a comparator monitoring the input voltage. Once

the input voltage exceeds the overvoltage fault rising threshold, the output is turned off, and the VIN_OV_FLT

flags are set in the respective registers. The SMBA# signal is asserted. 250 mV (typical) of hysteresis is

subtracted from the value in this register. This is to provide the falling threshold the input voltage must fall below

for this fault to clear. Once the input voltage falls below the falling threshold, the output is turned back on.

However, the fault flags and alerts remain until cleared by the host by sending the CLEAR_FAULTS command.

表8-42. VIN_OV_FLT Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Input overvoltage

fault threshold

15:0

VIN_OV_FLT

0x0000h (2.96 V) 0x000Fh (17.72 V) 0x000Eh (16.74 V)

Read/Write

When an input overvoltage fault is detected, the device:

• sets the FET_OFF and NONE_OF_THE_ABOVE/UNKNOWN bits in the STATUS_BYTE register

• sets the OUT_STATUS, INPUT_STATUS, PGOODB and NONE_OF_THE_ABOVE/UNKNOWN bits in the

upper byte of the STATUS_WORD register

• sets the VOUT_UV_WARN bit in the STATUS_OUT register

• sets the VIN_OV_FLT bit in the STATUS_INPUT register

• sets the PGOODB bit in the STATUS_MFR_SPECIFIC_2 register

• notifies the host by asserting SMBA#, if it is not masked setting the STATUS_IN, PGOODB, and

STATUS_OUT bits in the ALERT_MASK register and the GPIO4 pin is configured as SMBA# Output in the

GPIO_CONFIG_34 register

• deasserts the external PG signal, if the GPIO1 pin is configured as PGOOD output in the GPIO_CONFIG_12

register

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.51 VOUT_UV_WARN (43h, Read/Write Word)

VOUT_UV_WARN is a standard PMBus® command for configuring or reading an 8-bit threshold for the output

undervoltage warning detection. This command uses the PMBus® DIRECT format. When reading and writing to

this register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 to convert between the real world

units and hexadecimal values.

This command uses the PMBus® read or write word protocol.

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Contents of this register are compared to the VOUT ADC telemetry value. If the measured VOUT value falls

below the value in this register, the VOUT_UV_WARN flags are set in the respective registers. The SMBA#

signal is asserted. When the output voltage rises above the VOUT_UV_WARN threshold, and the

CLEAR_FAULTS command is sent afterwards, this warning flag and alert are cleared.

表8-43. VOUT_UV_WARN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Input undervoltage

warning threshold

15:0

VIN_UV_WARN

0x0000h (0 V)

0x00FFh (19.42 V) 0x0095h (11.35 V)

Read/Write

When an output undervoltage warning is detected, the device:

• sets the NONE_OF_THE_ABOVE/UNKNOWN bit in the STATUS_BYTE register

• sets the OUT_STATUS bit in the upper byte of the STATUS_WORD register

• sets the VOUT_OV_WARN bit in the STATUS_OUT register

• notifies the host by asserting SMBA#, if it is not masked setting the STATUS_OUT bit in the ALERT_MASK

register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34 register.

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.52 VOUT_PGTH (5Fh, Read/Write Word)

VOUT_PGTH is a standard PMBus® command for setting or reading an 8-bit output voltage threshold at which

Power Good (PGOOD) is be de-asserted. This command uses the PMBus® DIRECT format. When reading and

writing to this register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 to convert between the

real world units and hexadecimal values.

This command uses the PMBus® read or write word protocol.

Contents of this register are compared to the VOUT ADC telemetry value. Once the output voltage has fallen

below the VOUT_PGTH threshold at any point of time during normal operation or the device detects a fault

(except short-circuit), the PGOOD is de-asserted, and the PGOODB flags are set in the respective registers. The

SMBA# signal is also asserted. 250 mV (typical) of hysteresis is added to the value in this register. In order for

the PGOOD to be asserted again, the output voltage must rise above this rising threshold after clearing all

underlying faults and enabling the FET internal to the device. However, the fault flags and alerts remain until

cleared by the host by sending the CLEAR_FAULTS command.

表8-44. VOUT_PGTH Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Output power good

15:0

VOUT_PGTH de-assertion

threshold

0x0000h (0 V)

0x00FFh (19.42 V)

0x008Dh (10.74 V)

Read/Write

When the output voltage is less than VOUT_PGTH threshold, the device:

• sets the NONE_OF_THE_ABOVE/UNKNOWN bit in the STATUS_BYTE register

• sets the PGOODB and NONE_OF_THE_ABOVE/UNKNOWN bits in the upper byte of the STATUS_WORD

register

• sets the PGOODB bit in the STATUS_MFR_SPECIFIC_2 register

• notifies the host by asserting SMBA#, if it is not masked setting the PGOODB bit in the ALERT_MASK

register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34 register

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备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.53 OT_WARN (51h, Read/Write Word)

OT_WARN is a standard PMBus® command for configuring or reading an 8-bit threshold for the device

overtemperature warning detection. This command uses the PMBus® DIRECT format. When reading and

writing to this register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 to convert between the

real world units and hexadecimal values.

This command uses the PMBus® read or write word protocol.

Contents of this register are compared to the VTEMP ADC telemetry value. If the device temperature rises

above the value in this register, the OT_WARN flags are set in the respective registers. The SMBA# signal is

asserted. When the device temperature falls below the OT_WARN threshold, and the CLEAR_FAULTS

command is sent afterwards, this warning flag and alert are cleared.

表8-45. OT_WARN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Device

15:0

OT_WARN

overtemperature

warning threshold

0x0000h (-229 ºC) 0x00FFh (500 ºC) 0x007Eh (131 ºC)

Read/Write

When an overtemperature warning is detected, the device:

• sets the STATUS_TEMP bit in the STATUS_BYTE register

• sets the OT_WARN bit in the STATUS_TEMP register

• fills-up one of the Blackbox RAM registers (if available to write) writing the event identifier as OT_WARN and

relative time stamp information

• increases the Blackbox RAM address pointer in the BB_TIMER register by one (1) if it was previously less

than six (6), otherwise resets to zero (0). This change in the address pointer only occurs if one of the

Blackbox RAM registers is available to write

• notifies the host by asserting SMBA#, if it is not masked setting the STATUS_TEMP bit in the ALERT_MASK

register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34 register

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.54 OT_FLT (4Fh, Read/Write Word)

OT_FLT is a standard PMBus® command for configuring or reading an 8-bit threshold for the device

overtemperature fault detection. This command uses the PMBus® DIRECT format. When reading and writing to

this register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 to convert between the real world

units and hexadecimal values.

This command uses the PMBus® read or write word protocol.

Contents of this register are compared to the VTEMP ADC telemetry value. Once the device temperature

exceeds the overtemperature fault threshold, the output is turned off, and the OT_FLT flags are set in the

respective registers. The SMBA# signal is asserted. Refer to 节 8.3.7 for more details on thermal shutdown.

After the device recovers from an overtemperature fault, the CLEAR_FAULTS command clears the OT_FLT flag

and alert.

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表8-46. OT_FLT Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Device

15:0

OT_WARN

overtemperature

fault threshold

0x0000h (-229 ºC) 0x00FFh (500 ºC) 0x0085h (151 ºC)

Read/Write

When an overtemperature fault is detected, the device:

• sets the FET_OFF, STATUS_TEMP, and NONE_OF_THE_ABOVE/UNKNOWN bits in the STATUS_BYTE

register

• sets the OUT_STATUS, PGOODB, and NONE_OF_THE_ABOVE/UNKNOWN bits in the upper byte of the

STATUS_WORD register

• sets the VOUT_UV_WARN bit in the STATUS_OUT register

• sets the OT_FLT bit in the STATUS_TEMP register

• sets the PGOODB bit in the STATUS_MFR_SPECIFIC_2 register

• notifies the host asserting SMBA#, if it is not masked setting the STATUS_TEMP, PGOODB, and

STATUS_OUT bits high in the ALERT_MASK register and the GPIO4 pin is configured as SMBA# Output in

the GPIO_CONFIG_34 register

• deasserts the external PGOOD signal, if the GPIO1 pin is configured as PGOOD Output in the

GPIO_CONFIG_12 register

• asserts the FLT signal, if it is not masked setting the TEMP_FLT bit high in the FAULT_MASK register and the

GPIO2 pin is configured as FLT Output in the GPIO_CONFIG_12 register

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.55 PIN_OP_WARN (6Bh, Read/Write Word)

PIN_OP_WARN is a standard PMBus® command for configuring or reading an 8-bit threshold for the input

overpower warning detection. This command uses the PMBus® DIRECT format. When reading and writing to

this register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 to convert between the real world

units and hexadecimal values.

This command uses the PMBus® read or write word protocol.

Contents of this register are compared to the calculated telemetry power value. If the input power rises above

the value in this register, the PIN_OP_WARN flags are set in the respective registers. The SMBA# signal is

asserted. When the input power falls below the PIN_OP_WARN threshold, and the CLEAR_FAULTS command

is sent afterwards, this warning flag and alert are cleared.

表8-47. PIN_OP_WARN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

0x00FFh

(2089230/R_IMON

W)

0x00FFh

(2089230/R_IMON

W)

Input overpower

15:0

PIN_OP_WARN

0x0000h (0 W)

Read/Write

warning threshold

When an input overpower warning is detected, the device:

• sets the NONE_OF_THE_ABOVE/UNKNOWN bit in the STATUS_BYTE register

• sets the INPUT_STATUS and NONE_OF_THE_ABOVE/UNKNOWN bits in the upper byte of the

STATUS_WORD register

• sets the IN_OP_WARN bit in the STATUS_INPUT register

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• may set the EIN_OF_WARN bit in the STATUS_MFR_SPECIFIC_2 register

• fills-up one of the Blackbox RAM registers (if available to write) writing the event identifier as IN_OP_WARN

and relative time stamp information

• increments the Blackbox RAM address pointer in the BB_TIMER register by one (1) if it was previously less

than six (6), otherwise resets to zero (0). This change in the address pointer only occurs if one of the

Blackbox RAM registers is available to write.

• notifies the host by asserting SMBA#, if it is not masked setting the STATUS_IN bit in the ALERT_MASK

register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34 register

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.56 IIN_OC_WARN (5Dh, Read/Write Word)

IIN_OC_WARN is a standard PMBus® command for configuring or reading an 8-bit threshold for the input

overcurrent warning detection. This command uses the PMBus® DIRECT format. When reading and writing to

this register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 to convert between the real world

units and hexadecimal values.

This command uses the PMBus® read or write word protocol.

Contents of this register are compared to the VIMON ADC telemetry value. If the input current rises above the

value in this register, the IIN_OC_WARN flags are set in the respective registers. The SMBA# signal is asserted.

When the input current falls below the IIN_OC_WARN threshold, and the CLEAR_FAULTS command is sent

afterwards, this warning flag and alert are cleared.

表8-48. IIN_OC_WARN Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Input overcurrent

warning threshold

0x00FFh

15:0

IIN_OC_WARN

0x0000h (0 A)

Read/Write

(107250/R_IMONA) (107250/R_IMONA)

When an input overcurrent warning is detected, the device:

• sets the NONE_OF_THE_ABOVE/UNKNOWN bit in the STATUS_BYTE register

• sets the INPUT_STATUS bit in the upper byte of the STATUS_WORD register

• sets the OC_WARN bit in the STATUS_INPUT register

• may set the EIN_OF_WARN bit in the STATUS_MFR_SPECIFIC_2 register

• fills-up one of the Blackbox RAM registers (if available to write) writing the event identifier as OC_WARN and

relative time stamp information

• increments the Blackbox RAM address pointer in the BB_TIMER register by one (1) if it was previously less

than six (6), otherwise resets to zero (0). This change in the address pointer only occurs if one of the

Blackbox RAM registers is available to write.

• notifies the host by asserting SMBA#, if it is not masked setting the STATUS_IN bit high in the ALERT_MASK

register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34 register

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.57 VIREF (E0h, Read/Write Byte)

VIREF is a manufacturer-specific command for configuring or reading a 6-bit reference threshold for overcurrent

& short-circuit protections and active current sharing blocks as described in 节8.3.4.2, 节8.3.4.3, and 节8.3.4.4.

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This command uses the PMBus® DIRECT format. When reading and writing to this register, use the coefficients

shown in 表8-67, 方程式19, and 方程式20 to convert between the real world units and hexadecimal values.

This command uses the PMBus® read or write byte protocol.

Contents of this register drive a DAC to set the threshold for different comparators monitoring the input current.

The details of this register are shown in 表8-49.

表8-49. VIREF Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Programmable

reference voltage

for overcurrent &

short-circuit

7:0

VIREF

0x00h (0.3 V)

0x3Fh (1.186 V)

0x32h (1 V)

Read/Write

protections and

active current

sharing blocks

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.58 GPIO_CONFIG_12 (E1h, Read/Write Byte)

GPIO_CONFIG_12 is a manufacturer-specific command for configuring or reading functionalities of GPIO1

(Pin-19) and GPIO2 (Pin-20) as described in 节8.3.10.

This command uses the PMBus® read byte protocol.

The details of this register are shown in 表8-50.

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表8-50. GPIO_CONFIG_12 Register Description

Name

Value

Description

GPIO1 functionality

Reserved

Default

Access

111

110

101

100

011

EEDATA

EECLK

COMP1 output

COMP2 output

7:5

000

General purpose logic

output

010

GPIO1 configuration

General purpose logic

input

001

000

PGOOD Output

GPIO1 pin state when

configured as general

purpose input/output

4

1

0

Pin set to HI

Pin set to LO

GPIO2 functionality

Reserved

0

Read/Write

111

110

101

100

011

EEDATA

EECLK

COMP1 output

COMP2 output

3:1

000

General purpose logic

output

010

GPIO2 configuration

General purpose logic

input

001

000

FLT output

GPIO2 pin state when

configured as general

purpose input/output

0

1

0

Pin set to HI

Pin set to LO

0

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.59 GPIO_CONFIG_34 (E2h, Read/Write Byte)

GPIO_CONFIG_34 is a manufacturer-specific command for configuring or reading functionalities of GPIO3

(PIN-21) and GPIO4 (PIN-17) as described in 节8.3.10.

This command uses the PMBus® read byte protocol.

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The details of this register are shown in 表8-51.

表8-51. GPIO_CONFIG_34 Register Description

Bit

Name

Value

Description

GPIO3 functionality

Reserved

Default

111

110

101

100

011

EEDATA

EECLK

COMP1 output

COMP2 output

7:5

000

General purpose logic

output

010

GPIO3 configuration

General purpose logic

input

001

000

SWEN

GPIO3 pin state when

configured as general

purpose input/output

4

3:1

0

1

0

Pin set to HI

Pin set to LO

GPIO4 functionality

Reserved

0

Read/Write

111

110

101

100

011

EEDATA

EECLK

COMP1 output

COMP2 output

000

General purpose logic

output

010

GPIO4 configuration

General purpose logic

input

001

000

SMBA# output

GPIO4 pin state when

configured as general

purpose input/output

1

0

Pin set to HI

Pin set to LO

0

备注

• A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

• When using a TPS25990 eFuse with one or more TPS25985x eFuse(s) in parallel, GPIO3 must be

in its default configuration i.e. SWEN.

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8.3.14.7.1.60 ALERT_MASK (DBh, Read/Write Word)

ALERT_MASK is a manufacturer-specific command for configuring or reading the events which are allowed to

assert the SMBA# signal.

This command uses the PMBus® read or write word protocol.

Each bit corresponds to one of the analog or digital faults or warnings that would normally result in SMBA# being

asserted. When the corresponding bit is high, that condition does not cause SMBA# to be asserted. If that

condition occurs, the registers where that condition is captured are still updated (STATUS registers and

Blackbox) and the device ON/OFF control is still active. The details of this register are shown in 表8-52.

表8-52. ALERT_MASK Register Description

Bit

Name

Value

Description

Default

Access

15:9

Reserved

0000000

Reserved

0000000

UNKNOWN status bit doesn’t assert

1

0

SMBA#

8

UNKNOWN

1

UNKNOWN status bit asserts

SMBA#

1

0

1

0

PGOOD falling doesn’t assert SMBA#

PGOOD falling asserts SMBA#

GLBL_FLT doesn’t assert SMBA#

GLBL_FLT asserts SMBA#

7

6

PGOODB

GLBL_FLT

0

Active bits set in STATUS_MFR_SPECIFIC

1

0

1

0

1

0

1

register don’t assert SMBA#

5

4

3

MFR_STATUS

STATUS_TEMP

STATUS_OUT

0

Active bits set in STATUS_MFR_SPECIFIC

register assert SMBA#

Active bits set in STATUS_TEMP register

don’t assert SMBA#

Active bits set in STATUS_TEMP register

assert SMBA#

Read/Write

Active bits set in STATUS_OUT register

don’t assert SMBA#

Active bits set in STATUS_OUT register

assert SMBA#

Active bits set in STATUS_INPUT register

don’t assert SMBA#

2

STATUS_IN

0

Active bits set in STATUS_INPUT register

0

assert

SMBA#

Active bits set in STATUS_CML register

1

0

1

0

don’t assert SMBA#

1

0

CML_ERR

0

Active bits set in STATUS_CML register

assert SMBA#

Active bits set in STATUS_IOUT register

don’t assert SMBA#

STATUS_IOUT

Active bits set in STATUS_IOUT register

assert SMBA#

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备注

• A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

• GLBL_FLT is a logical OR of the status bits unmasked using the FAULT_MASK register.

8.3.14.7.1.61 FAULT_MASK (E3h, Read/Write Word)

FAULT_MASK is a manufacturer-specific command for configuring or reading the events to govern the global

fault (GLBL_FLT) bit in asserting SMBA# as described in the ALERT_MASK register and causing the external

FLT signal to be asserted, if the GPIO2 pin is configured as FLT in the GPIO_CONFIG_12 register.

This command uses the PMBus® read or write word protocol.

The details of this register are shown in 表8-53.

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表8-53. FAULT_MASK Register Description

Bit

Name

Value

Description

Default

Access

15:11

Reserved

00000

Reserved

00000

EXT_FLT doesn’t

1

0

1

assert FLT

10

9

EXT_FLT

0

EXT _FLT asserts

FLT

CMP1_FLT doesn’t

assert FLT

CMP1_FLT

CMP1_FLT asserts

FLT

0

1

0

1

0

CMP2_FLT doesn’t

assert FLT

8

CMP2_FLT

0

CMP2_FLT asserts

FLT

FET_HEALTH

doesn’t assert FLT

7

6

FET_HEALTH

SPFAIL

0

FET_HEALTH asserts

FLT

SPFAIL doesn’t

Read/Write

1

0

1

assert FLT

SPFAIL asserts FLT

SOA_FLT doesn’t

assert FLT

5

4:3

2

SOA_FLT

Reserved

TEMP_FLT

0

00

0

SOA_FLT asserts

FLT

0

00

1

Reserved

TEMP_FLT doesn’t

assert FLT

TEMP_FLT asserts

FLT

0

OC_FLT doesn’t

1

0

1

0

assert FLT

1

0

OC_FLT

SC_FLT

0

OC_FLT asserts FLT

SC_FLT doesn’t

assert FLT

SC_FLT asserts FLT

备注

• A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

• This command only allows the user to choose which events will cause assertion of the FLT pin.

Masking any event in the FAULT_MASK register doesn’t prevent the respective event from

turning OFF the device.

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8.3.14.7.1.62 DEVICE_CONFIG (E4h, Read/Write Word)

DEVICE_CONFIG is a manufacturer-specific command for configuring or reading several key device setup

related information of TPS25990 eFuse.

This command uses the PMBus® read or write word protocol.

The details of this register are shown in 表8-54.

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表8-54. DEVICE_CONFIG Register Description

Name

Value

Description

Default

Access

Internal PG delay for

discharging DVDT

capacitor

15

PG_DVDT_DLY

1

0

38 ms

110 µs

0

Disable FET drain to

source fault detection

at start-up

Low drain to source

voltage doesn’t

trigger a fault

14

DIS_VDSFLT

1

0

Low drain to source

voltage triggers a fault

Retry after short-

circuit fault (Fast-trip)

Retry once into

current limit (Not a

latched fault)

1

0

13

SC_RETRY

0

Remain off (latched

fault)

Read/Write

Scalable fast-trip

threshold

11

10

01

00

225% of I_OCP(TOTAL)

200% of I_OCP(TOTAL)

175% of I_OCP(TOTAL)

150% of I_OCP(TOTAL)

DVDT current scaling

150%

12:11

SPFAIL

10

11

10

01

00

100%

10:9

DVDT_CONFIG

VIN_TRAN_DIS

10

75%

50%

Input transient

blanking control

8

1

0

Disabled

Enabled

0

External EEPROM

connection

External EEPROM

connected

1

0

7

EXT_EEPROM

Read/Write

External EEPROM

not connected

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表8-54. DEVICE_CONFIG Register Description (continued)

Bit

Name

Value

Description

Default

Access

IREF/DAC2 pin

output selection

Read/Write

6

IREF_DAC2_SEL

1

0

DAC2

0

IREF DAC

Comparator-2

(COMP2) polarity

(AUX pin)

Read/Write

5

4

CMP2_POL

CMP1_POL

1

0

Active Low

Active High

0

Comparator-1

(COMP1) polarity

(TEMP/CMP pin)

1

0

Active Low

Active High

Read/Write

ADC performance

and speed selection

High performance

mode (Effective

1

0

3

ADC_HI_PERF

throughput = 18 µs)

0

High speed mode

(Effective throughput

= 11 µs)

Read/Write

+ve input signal for

the Comparator-1

(CMP1) at

2

CMP1_IN_SEL

TEMP/CMP pin

1

0

TEMP pin

IMON pin

0

Comparator-1

(COMP1) fault

(TEMP/CMP pin)

CMP1_FLT is a

latched fault and turns

off the device

Read/Write

1

0

1

CMP1_FLT

0

CMP1_FLT is not a

latched fault and

doesn’t turn off the

device

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表8-54. DEVICE_CONFIG Register Description (continued)

Name

Value

Description

Default

Access

Comparator-2

(COMP2) fault (AUX

pin)

CMP2_FLT is a

latched fault and turns

off the device

1

0

CMP2_FLT

Read/Write

0

CMP2_FLT is not a

latched fault and

doesn’t turn off the

device

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.63 BB_CONFIG (E5h, Read/Write Byte)

BB_CONFIG is a manufacturer-specific command for configuring or reading the behavior of the Blackbox

function as described in 节8.3.14.11.

This command uses the PMBus® read or write byte protocol.

The details of this register are shown in 表8-55.

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表8-55. BB_CONFIG Register Description

Bit

Name

Value

Description

Default

BB EEPROM write

trigger

Power FET turning

OFF triggers write to

BB EEPROM

1

0

7

FET_OFF_WR

0

Power FET turning

OFF doesn’t trigger

write to BB EEPROM

BB EEPROM write

trigger

Global Fault triggers

write to BB EEPROM

1

0

6

FLT_WR

0

Global Fault doesn’t

trigger write to BB

EEPROM

Read/Write

BB EEPROM write

trigger

SMBA# assertion

triggers write to BB

EEPROM

1

5

ALERT_WR

0

SMBA# assertion

doesn’t trigger write

to BB EEPROM

0

4:2

1:0

Reserved

BB_TICK

000

Reserved

000

Blackbox timestamp

tick interval

11

10

01

00

3500 µs

870 µs

220 µs

55 µs

00

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

BB_CONFIG[5] needs to be used in conjunction with the ALERT_MASK register to determine which

events trigger the Blackbox write to the external EEPROM. However, the GLBL_FLT

(ALERT_MASK[6]) signal is excluded from the list of signals driving ALERT for Blackbox write even if

they are unmasked in the ALERT_MASK register.

8.3.14.7.1.64 OC_TIMER (E6h, Read/Write Byte)

OC_TIMER is a manufacturer-specific register used to program the overcurrent blanking digital timer duration as

described in 节8.3.4.2.

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This command uses the PMBus® read/write byte protocol.

The details of this register are shown in 表8-56.

表8-56. OC_TIMER Register Description

Overcurrent

Blanking Timer

Duration (ms)

Bit

Name

Description

Value

Default Value

Access

0x00h

0x01h

0x02h

0x03h

0x04h

0x05h

0x06h

0x07h

...

0

0.109

0.218

0.327

0.436

0.545

0.654

0.763

Overcurrent

7:0

OC_TIMER

blanking digital

timer

0x14h

Read/Write

0x0Ah

...

1.09

2.18

10.9

21.8

27.8

0x14h

...

0x64h

...

0xC8h

...

0xFFh

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.65 RETRY_CONFIG (E7h, Read/Write Byte)

RETRY_CONFIG is a manufacturer-specific command for configuring or reading the retry behavior of the

TPS25990 eFuse in the event of a fault as depicted in 节8.3.10.1.

This command uses the PMBus® read or write byte protocol.

The details of this register are shown in 表8-57.

表8-57. RETRY_CONFIG Register Description

Bit

Name

Value

Description

Default

Access

7:6

RESPONSE

10

Shutdown and retry

10

Read

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表8-57. RETRY_CONFIG Register Description (continued)

Bit

Name

Value

Description

Default

Retry count

111

110

101

100

011

010

001

Retry indefinitely

Retry 64 times

Retry 32 times

Retry 16 times

Retry 8 times

Retry 4 times

Retry 1 times

5:3

RETRY_CNT

000

Retry 0 times (Latch-

off)

000

Read/Write

Retry delay timer

value

111

110

101

100

011

010

001

000

7000 ms

3500 ms

1750 ms

870 ms

435 ms

220 ms

110 ms

55 ms

2:0

RETRY_DLY

100

备注

• A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

• The delay used in the POWER_CYCLE command is also configured through Bit[2:0] of this

register.

8.3.14.7.1.66 ADC_CONFIG_1 (E8h, Read/Write Byte)

ADC_CONFIG_1 is a manufacturer-specific command for configuring or reading channel selections and modes

for ADC sampling as described in 节8.3.14.8.

This command uses the PMBus® read or write byte protocol.

The details of this register are shown in 表8-58.

表8-58. ADC_CONFIG_1 Register Description

Bit

Name

Value

Description

Default

Access

End of conversion

indication (Active

Low)

ADC is busy

(Conversion in

progress)

7

EOC

Read

1

0

Conversion done

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表8-58. ADC_CONFIG_1 Register Description (continued)

Name

Value

Description

Default

Access

Software conversion

start control (used

with MODE = 01)

6

CONVST

1

0

Start conversion

0

Do not start

conversion

ADC sampling mode

Continuous

11

10

01

00

conversion - Single

channel

Single channel single

conversion - External

pin controlled

5:4

MODE

00

Single channel single

conversion –

software controlled

Continuous

conversion –auto

sequenced

Parameter/ADC

Read/Write

Channel selection for

sampling (MODE =

01 or 10 or 11)

1001-1111

1000

Reserved

GND (Applicable only

in MODE = 01 or 10)

VIREF (Applicable

only in MODE = 01 or

10)

0111

0110

0101

ADDR1 (Applicable

only in MODE = 01 or

10)

3:0

CONV_CH_SEL

0000

ADDR0 (Applicable

only in MODE = 01 or

10)

0100

0011

0010

0001

0000

VAUX

VTEMP

IIN

VOUT

VIN

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备注

• A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

• MODE = 10 or 01 are debug-only modes and not recommended to be used during normal

operation as they prevent the ADC from sampling all the necessary signals needed for the eFuse

protection features.

8.3.14.7.1.67 ADC_CONFIG_2 (E9h, Read/Write Byte)

ADC_CONFIG_2 is a manufacturer-specific command for configuring or reading parameter selection and

decimation rate (sample skip count) for high speed ADC sample buffering as described in 节8.3.14.7.1.42.

This command uses the PMBus® read or write byte protocol.

The details of this register are shown in 表8-59.

表8-59. ADC_CONFIG_2 Register Description

Bit

Name

VAUX_VTEMP_SEL

Reserved

Value

Description

Default

Access

Read/Write

Read

Average auxiliary

voltage or average

temperature telemetry

selection

Use VAUX ADC

channel as input for

AUX_AVG

1

7

computation

0

Use TEMP ADC

channel as input for

TEMP_AVG

0

computation

6

Reserved

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表8-59. ADC_CONFIG_2 Register Description (continued)

Name

Value

Description

Default

Access

Parameter selection

for buffering

Reserved (Will default

to IIN)

111

110

101

Reserved (Will default

to IIN)

Reserved (Will default

to IIN)

5:3

BUF_CH_SEL

000

100

011

010

001

000

VAUX

VTEMP

IIN

VOUT

VIN

Decimation rate

(sample skip count)

for ADC sample

buffering

Decimation rate

111

110

101

100

011

010

001

000

(sample skip count) =

7

Read/Write

Decimation rate

(sample skip count) =

6

Decimation rate

(sample skip count) =

5

Decimation rate

2:0

DEC_RATE

(sample skip count) =

4

0000

Decimation rate

(sample skip count) =

3

Decimation rate

(sample skip count) =

2

Decimation rate

(sample skip count) =

1

Decimation rate

(sample skip count) =

0

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备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.68 PK_MIN_AVG (EAh, Read/Write Byte)

PK_MIN_AVG is a manufacturer-specific command that resets all the maximum, minimum, and average

telemetry registers, such as READ_VIN_PEAK, READ_IIN_PEAK, READ_TEMP_PEAK, READ_PIN_PEAK,

READ_VIN_MIN,

READ_VOUT_MIN,

READ_VIN_AVG,

READ_VOUT_AVG,

READ_IIN_AVG,

READ_TEMP_AVG, and READ_PIN_AVG. This register is also used to program the number of ADC samples to

be used for averaging. Averaging a higher number of samples improves the accuracy at the expense of higher

latency.

This command uses the PMBus® read or write byte protocol.

The details of this register are shown in 表8-60.

表8-60. PK_MIN_AVG Register Description

Bit

Name

Value

Description

Default

Access

Reset all peak

registers to 0

1

0

1

0

1

7

RESET_PEAK

0

No action

Reset all average

registers to 0

6

RESET_AVG

0

No action

Reset all minimum

registers to 0

5

RESET_MIN

Reserved

0

No action

Read/Write

4:3

00

Reserved

00

111

110

101

100

011

010

001

000

Average count = 128

Average count = 64

Average count = 32

Average count = 16

Average count = 8

Average count = 4

Average count = 2

Average count = 1

2:0

AVG_CNT

000

备注

• A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

• As soon as the PK_MIN_AVG command is executed to clear the peak, minimum, and average

registers, the RESET_PEAK, READ_MIN, and READ_AVG bits are automatically cleared to zero

(0).

8.3.14.7.1.69 VCMPxREF (EBh, Read/Write Byte)

VCMPxREF is a manufacturer-specific command for configuring or reading reference thresholds for general

purpose comparators as described in 节8.3.12.

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This command uses the PMBus® read or write byte protocol.

A 4-bit reference threshold is defined by VCMPxREF[3:0] for Comparator-1 (CMP1) and by VCMPxREF[7:4] for

Comparator-2 (CMP2). Individually, VCMPxREF[3:0] and VCMPxREF[7:4] use the PMBus® DIRECT format.

When reading and writing to this register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式 20 for

VCMPxREF[3:0] and VCMPxREF[7:4] separately to define each individual comparator's threshold.

Contents of this register drive a DAC to set the thresholds for the two (2) general purpose comparators. The

details of this register are shown in 表8-61.

表8-61. VCMPxREF Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Programmable

reference voltage

for Comparator-2

(CMP2)

7:4

CMP2REF

0x0xh (0.2 V)

0xFxh (1.7 V)

Read/Write

Programmable

reference voltage

for Comparator-1

(CMP1)

3:0

CMP1REF

0xx0h (0.2 V)

0xxFh (1.7 V)

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.70 PSU_VOLTAGE (ECh, Read/Write Byte)

PSU_VOLTAGE is a manufacturer-specific command for configuring or reading an 8-bit data corresponding to

the input power supply voltage for implementing the input cable fault detection feature.

This command uses the PMBus® read or write byte protocol.

• Sending a value to the PSU_VOLTAGE register:

Real world value of input power supply voltage in V is converted into a 10-bit binary data through PMBus®

DIRECT format conversion using 方程式20 and the 'm', 'b', & 'R' coefficients corresponding to READ_VIN in

表8-67. Hexadecimal value corresponding to the eight least significant bits from this 10-bit binary data needs

to be written in the PSU_VOLTAGE register.

• Interpreting the received values from the PSU_VOLTAGE register:

One byte of hexadecimal data read from the PSU_VOLTAGE register needs to be converted into a 10-bit

binary data by appending the READ_VIN[9:8] bits to the left side. The hexadecimal value corresponding to

this 10-bit binary data needs to be converted to a real world value of input power supply voltage in V through

PMBus® DIRECT format conversion using 方程式19 and the 'm', 'b', & 'R' coefficients corresponding to

READ_VIN in 表8-67.

The details of this register are shown in 表8-62.

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表8-62. PSU_VOLTAGE Register Description

Minimum

Value

Bit

Name

Description READ_VIN[9:8]

Maximum Value

Default Value

00

0x00h (0 V)

0xFFh (4.86 V)

0xFFh (9.73 V)

0x9Dh (2.99 V)

0x9Dh (7.86 V)

0x9Dh (12.74 V)

Nominal

01

0x00h (4.87 V)

input power

7:0

PSU_VOLTAGE

Read/Write

10

0x00h (9.75 V) 0xFFh (14.61 V)

supply

voltage

11

0x00h (14.63

0xFFh (19.48 V)

V)

0x9Dh (17.62 V)

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.71 CABLE_DROP (EDh, Read/Write Byte)

CABLE_DROP is a manufacturer-specific command that allows configuring or reading an 8-bit reference

threshold for the maximum cable voltage drop expected to implement the input cable fault detection feature. This

command uses the PMBus® DIRECT format. When reading and writing to this register, use the coefficients

shown in 表8-67, 方程式19, and 方程式20.

This command uses the PMBus® read or write byte protocol.

Contents of this register are compared with the difference between PSU_VOLTAGE and VIN ADC telemetry

values. If this difference value exceeds the value in the CABLE_DROP register, the VIN_CABLE_FAULT flags

are set in the respective registers. The SMBA# signal is asserted. When the difference between PSU_VOLTAGE

and VIN ADC telemetry value falls below the CABLE_DROP threshold, and the CLEAR_FAULTS command is

sent afterwards, this warning flag and alart are cleared. The details of this register are shown in 表8-49.

表8-63. CABLE_DROP Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

Maximum cable

7:0

CABLE_DROP voltage drop

expected

0x00h (0 V)

0xFFh (4.845 V)

Read/Write

When the input cable fault is detected, the device:

• sets the NONE_OF_THE_ABOVE/UNKNOWN bit in the STATUS_BYTE register

• sets the NONE_OF_THE_ABOVE/UNKNOWN bit in the upper byte of the STATUS_WORD register

• sets the VIN_CABLE_FLT bit in the STATUS_MFR_SPECIFIC_2 register

• notifies the host asserting SMBA#, if it is not masked setting the UNKNOWN bit low in the ALERT_MASK

register

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.7.1.72 GPDAC1 (F0h, Read/Write Byte)

GPDAC1 is a manufacturer-specific command that allows configuring or reading a 6-bit data driving a general

purpose DAC to generate a constant current output at PIN-6 (DAC1). This command uses the PMBus® DIRECT

format. When reading and writing to this register, use the coefficients shown in 表 8-67, 方程式 19, and 方程式

20.

110

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This command uses the PMBus® read or write byte protocol.

The details of this register are shown in 表8-64.

表8-64. GPDAC1 Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

General purpose

DAC output-1

7:0

GPDAC1

0x00h (6 µA)

0x3Fh (53.25 µA)

0x00h (6 µA)

Read/Write

备注

• A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

• Writing 1xxxxxxb in this register disconnects the DAC output from the DAC1 pin making the pin

high-impedance and sink no current.

8.3.14.7.1.73 GPDAC2 (F1h, Read/Write Byte)

GPDAC2 is a manufacturer-specific command that allows configuring or reading a 6-bit data driving a general

purpose DAC to generate a constant voltage output on the IREF/DAC2 pin. This command uses the PMBus®

DIRECT format. When reading and writing to this register, use the coefficients shown in 表 8-67, 方程式 19, and

方程式20.

This command uses the PMBus® read or write byte protocol. The details of this register are shown in 表8-65.

表8-65. GPDAC2 Register Description

Bit

Name

Description

Minimum Value

Maximum Value

Default Value

Access

General purpose

DAC output-2

7:0

GPDAC2

0x00h (0.3 V)

0x3Fh (1.186 V)

0x00h (0.3 V)

Read/Write

备注

• A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

• The GPDAC2 output is multiplexed with the VIREF DAC output and either one of them can be

brought out to the IREF/DAC2 pin at a time depending on DEVICE_CONFIG[6] bit setting.

• If the GPDAC2 output is brought out to the IREF/DAC2 pin, the VIREF DAC voltage is still

connected internally to the overcurrent & short-circuit protections and active current sharing blocks.

This ensures the protection thresholds are determined by the VIREF DAC setting and not by the

voltage on the IREF/DAC2pin.

• When using a TPS25990 eFuse with one or more TPS25985 eFuse(s) in parallel, the VIREF

output must be brought out on the IREF/DAC2 pin. The DEVICE_CONFIG[6] setting to bring the

GPDAC2 output on the pin must not be used in this configuration. This is to ensure the VIREF

setting controls the reference for overcurrent & short-circuit protections and active current sharing

for all the devices in the parallel chain.

8.3.14.7.1.74 INS_DLY (F9h, Read/Write Byte)

INS_DLY is a manufacturer-specific command which is used to program the insertion delay at start-up. The

device implements a fixed analog insertion delay of 14 ms (typical). As described in 表 8-66, the INS_DLY

register specifies a delay in addition to the fixed 14 ms delay.

This command uses the PMBus® read/write byte protocol.

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表8-66. INS_DLY Register Description

Effective

Insertion Delay

(ms)

Bit

Name

Description

Value

Default Value

0x00h

0x01h

0x02h

0x03h

0x04h

0x05h

0x06h

0x07h

14

25

68

123

230

340

450

560

Insertion delay at

start-up

7:0

INS_DLY

0x00h

Read/Write

备注

A write command to this register should be preceded by the MFR_WRITE_PROTECT command to

unlock the device first to prevent accidental accidental/spurious writes.

8.3.14.8 Analog-to-digital Converter

The TPS25590x integrates a 10-bit, 460 KSPS SAR ADC preceded by an analog MUX. The following signals

are available for sampling by the ADC:

1. VIN

2. VOUT

3. VIMON

4. VTEMP

5. VAUX

6. ADDR0

7. ADDR1

The ADC uses a 5 kHz low-pass filter at the input to suppress high frequency noise (outside the ADC Nyquist

bandwidth) and prevent aliasing.

备注

The ADC also supports a high performance mode wherein the sampling rate is traded off in favor of

improved DNL and INL. In this mode, the sampling rate is reduced to 270 KSPS. This mode can be

selected by setting the ADC_HI_PERF bit in the DEVICE_CONFIG register.

During normal operation, the ADC automatically sequences the channels. The ADC channel sequencer

manages MUX channel selection for sampling.

备注

• The ADDR0 and ADDR1 signals are sampled only at startup to decode the PMBus® target

address.

• The ADC implements background self-calibration to eliminate offset and gain errors inherent to the

ADC.

The device also supports buffering of multiple samples of a selected parameter in RAM, which can be read by

the host using the ADC_SAMPLE_BUF block read command. This allows the system designer to reconstruct the

time domain profile/waveform of that parameter in a given interval. This can be useful during design/debugging

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by functioning like an in-built "digital oscilloscope". The ADC channel to sample for buffering and the decimation

rate/sample skip count can be user configured using PMBus® writes to the ADC_CONFIG_2 register.

The TPS25990 can post-process raw ADC sampled data to compute the following derived parameters:

1. VIN Average

2. VIN Peak

3. VIN Min

4. VOUT Average

5. VOUT Min

6. IIN Average

7. IIN Peak

8. PIN

9. PIN Average

10. PIN Peak

11. EIN

12. Temperature Average

13. Temperature Peak

14. Cable voltage drop

A single ADC sample can have higher errors due to internal noise. It’s possible to improve the ADC SNR and

the telemetry accuracy by averaging higher number of samples. The number of samples to be averaged is user-

programmable using the PK_MIN_AVG register. The minimum, maximum, and average values can also be reset

using the PK_MIN_AVG register.

The TPS25990 performs digital comparison on the ADC sampled data to detect the following system events.

1. VIN UV WARN

2. VIN UV FAULT

3. VIN OV WARN

4. VOUT PGOOD

5. IIN OC WARN

6. OT WARN

7. OT FAULT

8. PIN OP WARN

9. CABLE FAULT

The results of the comparisons are reflected in the PMBus® status registers and can be configured to trigger

other actions e.g. FET turn OFF (protection response) and FLT output assertion for faults, SMBA# signal

assertion for faults/warnings and Blackbox RAM/EEPROM update.

8.3.14.9 Digital-to-analog Converters

The TPS25990 integrates multiple DACs which are used to set the thresholds or gains of various blocks:

1. VIREF: This is a 6-bit buffered voltage output DAC which provides a programmable threshold for overcurrent

protection, short-circuit protection and active current sharing blocks. This can be programmed using the

VIREF register. This signal is available internally always for these blocks, and optionally can be brought on

the IREF/DAC2 pin to drive other devices in a parallel chain.

2. IDVDT: This is a 2-bit current output DAC which sources current on the DVDT pin to provide output Slew

Rate (DVDT) control. This can be programmed using the DEVICE_CONFIG[10:9] register bits.

3. DAC1: This is a 6-bit general purpose current output DAC which can sink current on the DAC1 pin. This can

be programmed using the GPDAC1 register.

4. DAC2: This is a 6-bit general purpose voltage output DAC. This can be programmed using the GPDAC2

register. This can be brought out to the IREF/DAC2 pin and is multiplexed with the VIREF DAC.

5. VOV: This is a 4-bit DAC which provides a programmable threshold for the VIN overvoltage protection

comparator. This can be programmed using the VIN_OV_FLT register.

6. CMP2REF: This is a 4-bit voltage output DAC which provides a programmable threshold for general purpose

analog comparator-2 (CMP2) on AUX pin. This can be programmed using the VCMPxREF[7:4] register bits.

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7. CMP1REF: This is a 4-bit voltage output DAC which provides a programmable threshold for general purpose

analog comparator-1 (CMP1) on TEMP/CMP pin. This can be programmed using the VCMPxREF[3:0]

register bits.

8.3.14.10 DIRECT format Conversion

For telemetry and configuration parameters, the TPS25990 supports DIRECT format. Digital codes for telemetry

or configuration parameters can be converted to their equivalent real world units using 方程式19 and 方程式20.

• Interpreting received values:

The host system uses 方程式19 to convert the value received from the PMBus® device into a reading of V,

A, °C, or W:

1

m

−R

X =

Y × 10

− b

(19)

Where:

– X, is the calculated, “real world”value in the appropriate units (V, A, °C, or W);

– m, the slope coefficient, is a two byte, two’s complement integer;

– Y, is a two byte two’s complement integer received from the PMBus® device;

– b, the offset, is a two byte, two’s complement integer; and

– R, the exponent, is a one byte, two’s complement integer.

• Sending a value:

To send a value, the host must use 方程式20 to find the value of Y:

R

Y = mX + b × 10

(20)

Where:

– Y is the two byte two’s complement integer to be sent to the unit;

– m, the slope coefficient, is the two byte, two’s complement integer;

– X, a “real world”value, in units such as V, A, °C, or W, to be converted for transmission;

– b, the offset, is the two byte, two’s complement integer; and

– R, the exponent, is the decimal value equivalent to the one byte, two’s complement integer.

表8-67. TPS25990 PMBus^®DIRECT format Conversion Guide

Zero Code

Analog Value

Full scale

Digital Code

Full-scale

Analog Value

Parameter

Units

m

b

R

READ_VIN

V

0

0x3FF

19.48

5251

0

- 2

- 3

- 2

- 3

- 4

- 2

READ_VIN_PEAK

READ_VIN_PEAK_EEPROM

READ_VIN_MIN

READ_VIN_AVG

VIN_UV_WARN

VIN_UV_FLT

0

0x3FF

0xFF

19.48

19.42

19.48

19.42

17.72

19.48

5251

0

13128

5251

0

0x3FF

0xFF

0

5251

0

13128

10163

5251

0

0xFF

VIN_OV_WARN

VIN_OV_FLT

0

0xFF

2.95

0

0xF

− 30081

READ_VOUT

0x3FF

0

READ_VOUT_AVG

READ_VOUT_MIN

0

5251

0

5251

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表8-67. TPS25990 PMBus^®DIRECT format Conversion Guide (continued)

Zero Code

Analog Value

Full scale

Digital Code

Full-scale

Analog Value

Parameter

Units

m

b

R

VOUT_UV_WARN

VOUT_PGTH

V

0

0xFF

19.42

13128

0

- 3

- 4

- 2

- 1

- 4

- 5

- 7

- 2

- 3

- 2

- 3

- 2

- 3

- 2

- 4

V

0

0xFF

0x3FF

0xFF

0x3FF

0xFF

0x3FF

0xFF

0x7FFF

0x3F

19.42

READ_IIN

A

0

107250/R_IMON

501.4

9.538 × R_IMON

READ_IIN_AVG

A

0

9.538 × R_IMON

READ_IIN_PEAK

READ_IIN_PEAK_EEPROM

IIN_OC_WARN

A

0

9.538 × R_IMON

A

0

23.8 × R_IMON

A

0

23.8 × R_IMON

READ_TEMPERATURE_1

READ_TEMP_AVG

READ_TEMP_PEAK

READ_TEMP_PEAK_EEPROM

OT_WARN

°C

V

140

35

32100

− 229.3

501.4

32100

− 229.3

501.4

32100

− 229.3

499.8

8006

− 228.7

499.8

35

8006

− 228.7

OT_FLT

499.8

35

8006

− 228.7

VAUX

0

1.95

5251

0

VAUX_AVG

V

0

1.95

0

READ_PIN

W

J

0

2091375/R_IMON4.901 × R_IMON

2091375/R_IMON12.217 × R_IMON

0

READ_PIN_PEAK

READ_PIN_AVG

0

PIN_OP_WARN

0

READ_EIN

0

-

38.22 × R_IMON

7111

0

VIREF

V

0.3

6

1.186

53.25

1.186

1.7

− 2133

GPDAC1

µA

V

0x3F

1333

− 8000

GPDAC2

0.3

0.2

0

0x3F

7111

− 2133

CMP2REF {VCMPXREF[7:4]}

CMP1REF {VCMPXREF[3:0]}

CABLE_VOLTAGE_DROP

READ_SAMPLE_BUF_VIN

READ_SAMPLE_BUF_VOUT

READ_SAMPLE_BUF_TEMP

READ_SAMPLE_BUF_VAUX

READ_SAMPLE_BUF_IIN

V

0xF

10000

5263

− 2000

V

0xF

1.7

− 2000

V

0xFF

4.845

19.42

499.8

1.94

0

V

0

13128

35

0

V

0

°C

V

-228.7

0

8006

13128

23.8 × R_IMON

0

A

0

107250/R_IMON

8.3.14.11 Blackbox Fault Recording

The Blackbox feature greatly enhances the ability of the system designer to debug power path related issues

during design/development and in case of field returns. Along with a snapshot of the parametric data and event

information through various status registers, the TPS25990 provides additional information which helps to re-

create the sequence of events as they occurred in a certain interval of time. This information is available in both

the on-chip volatile memory and the external I2C EEPROM (connected on the EECLK/EEDATA pins) and can be

accessed through PMBus®.

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备注

The PMBus® engine is up and running as soon as a stable supply is available on VDD, independent

of VIN and other related internal nodes. This ensures that the Blackbox contents can be read back

from a field return unit by applying power on VDD pin even if there’s damage on VIN side or Power

FET .

During the operation of the device, the Blackbox information is stored inside the Blackbox buffer RAM which is

seven (7) bytes deep. At any point of time, issuing the READ_BB_RAM command will retrieve the most recent

seven (7) events in a sequence along with the timestamp relative to each other. Each byte of this buffer RAM

holds the following information about a single event:

1. A 3-bit event identifier

2. A 5-bit value which indicates the time lapse because the previous event. The lower 4 bits of the timer value

represents a snapshot of the free running Blackbox tick timer at the instant of registering the event in the

Blackbox RAM. The 5^thbit indicates whether the timer has overflowed at least once since the last event.

The event identifier and relative timer information help the system designer to reconstruct a timeline of events as

they occurred, thereby enhancing the debug capabilities as compared to viewing a single snapshot of status

registers. The Blackbox tick timer is a free running timer which is reset to zero after every event. The timer

update rate can be configured through the BB_CONFIG register. This allows the users to make a tradeoff

between fine timing resolution and longer time span as per their debug needs. The BB_TMR_EXP bit in the

BB_TIMER register indicates if the Blackbox tick timer has overflowed at least since the last event. This bit

indicates whether the event entries in the RAM are relatively recent or old. This bit is latched when the timer

overflows and reset to zero along with the free running timer when the next event occurs.

Here are the events which will trigger a write to the Blackbox RAM:

1. VIN_UV_WARN

2. VIN_OV_WARN

3. OC_WARN

4. OT_WARN

5. OC_DET

6. VIN_TRAN

7. IN_OP_WARN

Once the device encounters a global fault or alert event (based on the ALERT_MASK), the Blackbox RAM

contents, along with the status registers, peak input voltage, peak input current, peak device temperature, and

Blackbox timer values are written to an external EEPROM through the EECLK/EEDATA pins.

备注

The EEPROM interface is a standard I2C controller and operates at 400 kHz clock speed. TI

recommends using an I2C EEPROM with minimum 1 Kbits of capacity and 16-byte page addressing.

Examples of compatible EEPROM devices include 24LC04, 24AA04, etc.

The contents of the Blackbox RAM along with some status registers (STATUS_WORD,

STATUS_MFR_SPECIFIC, and STATUS_INPUT) and certain parameters (VIN_PEAK, IIN_PEAK, and

TEMPERATURE_PEAK) are stored into Page-0 of an external EEPROM when the following conditions are met.

At the same time, Blackbox RAM contents and Blackbox tick timer values are locked.

1. An external EEPROM is successfully connected by setting the EXT_EEPROM bit high in the

DEVICE_CONFIG register. In addition, it is done by configuring two (2) of the four (4) GPIOs as EECLK and

EEDATA appropriately in the GPIO_CONFIG_12 and GPIO_CONFIG_34 registers. Make sure those two (2)

selected GPIO pins are physically connected to the EEPROM clock and data pins respectively on the board.

2. Any one of the three BB EEPROM write trigger bits is set in the BB_CONFIG register.

Blackbox EEPROM contents:

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1. BB_RAM_0 to BB_RAM_6 [Seven (7) bytes]

2. BB_TIMER [One (1) byte]

3. STATUS_WORD [Two (2) bytes]

4. STATUS_MFR_SPECIFIC [One (1) byte]

5. STATUS_INPUT [One (1) byte]

6. VIN_PEAK [One (1) byte, Eight (8) MSBs from the 10-bit ADC output data]

7. IIN_PEAK [One (1) byte, Eight (8) MSBs from the 10-bit ADC output data]

8. TEMPERATURE_PEAK [One (1) byte, Eight (8) MSBs from the 10-bit ADC output data]

9. CHECKSUM [One (1) byte]

Fault/Alert/

Shutdown

Warning Event 1

Warning Event 2

Warning Event 3

Warning Event 7

Time >

BB_TIMER_MAX

Time >

BB_TIMER_MAX

Time <

BB_TIMER_MAX

. . . .

Time

. . . .

BB_RAM_1

- Event ID 2

- BB_TIMER_EXP - BB_TIMER_EXP

BB_RAM_2

BB_RAM_6

CHECKSUM

TEMP_PEAK

IIN_PEAK

BB_TIMER

BB_RAM_6

BB_RAM_5

BB_RAM_4

BB_RAM_3

BB_RAM_2

BB_RAM_1

BB_RAM_0

- Event ID 7

- BB_TIMER_EXP

= 1

- BB_TICK

current value

- Event ID 1

- BB_TIMER_EXP

= 1

- BB_TICK

current value

- Event ID 3

VIN_PEAK

= 1

- BB_TICK

current value

= 0

- BB_TICK

current value

STATUS_INPUT

STATUS_MFR

STATUS_H

STATUS_L

Write to BB EEPROM

Write to BB RAM

BB_TICK_PER = f(BB_CONFIG[1:0])

BB_TIMER_MAX= 16 * BB_TICK_PER

图8-21. Blackbox Operation Example

8.4 Device Functional Modes

The features of the device depend on the operating mode. 表8-68 summarizes the device functional modes.

表8-68. Device Functional Modes Based on EN/UVLO Pin

Pin Condition

EN/UVLO > V_UVLO(R)

Device State

Output Discharge

Fully ON

FET OFF

Shutdown

Disabled

V_SD(F)< EN/UVLO < V_UVLO(F)(time < t_QOD

V_SD(F)< EN/UVLO < V_UVLO(F)(time > t_QOD

EN/UVLO < V_SD(F)

)

Disabled

Enabled

Disabled

)

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The TPS25990 is a high-current eFuse that is typically used for input power rail protection and monitoring

applications. The device operates from 2.9 V to 16 V and supports various user adjustable and programmable

protection options. The device provides ability to control inrush current and offers protection against overvoltage,

overcurrent, short-circuit and overtemperature conditions. The device can be used in a variety of systems such

as server motherboards, add-on cards, graphics cards, accelerator cards, enterprise switches, routers, and so

forth. The design procedure explained in the subsequent sections can be used to select the supporting

component values based on the application requirements. Additionally, a spreadsheet design tool, TPS25990x

Design Calculator is available in the web product folder.

9.1.1 Single Device, Standalone Operation

TPS25990x

IN

VIN

VOUT

OUT

IREF/DAC2

VDD

IMON

EN

EN/UVLO

VL

VLSTBY

VL VL

VL

PG

SWEN

FLT

SCL

SDA

SCL

SDA

TEMP/CMP

AUX

DAC1

SMBA#

ADDR0 ADDR1 GND

ILIM DVDT

图9-1. Single Device, Standalone Operation

9.1.2 Multiple Devices, Parallel Connection

Applications which need higher current input protection along with digital interface for telemetry, control,

configurability can use one or more TPS25985 devices in parallel with TPS25990 as shown in 图9-2.

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VL VL

VL

TPS25990x

ADDR0

ADDR1

AUX

SCL

SDA

SMBA#

VOUT

IN

OUT

IREF/DAC2

TEMP/CMP

VIN

VDD

IMON

VL VL

EN/UVLO

EN

VLSTBY

PG

SWEN

FLT

GND

ILIM

DVDT

TPS25985x

IN

OUT

IREF

TEMP

IMON

VDD

EN/UVLO

PG

ITIMER

SWEN

FLT

MODE GND

ILIM

DVDT

TPS25985x

IN

OUT

IREF

TEMP

IMON

VDD

EN/UVLO

PG

ITIMER

SWEN

FLT

MODE GND ILIM DVDT

图9-2. TPS25990 Connected in Parallel with TPS25985x For Higher Current Support With PMBus^®

In this configuration, the TPS25990 acts as the primary device and controls the other TPS25985x devices in the

chain which are designated as secondary devices. This configuration is achieved by connecting the primary

device as follows:

1. VDD is connected to IN through an R-C filter.

2. DVDT is connected through capacitor to GND.

3. IREF is connected through capacitor to GND.

4. IMON is connected through resistor to GND.

5. ILIM is connected through resistor to GND.

SWEN is pulled up to a 3.3-V to 5-V standby rail. This rail must be powered up independent of the eFuse

ON/OFF status.

The secondary devices must be connected in the following manner:

1. VDD is connected to IN through a R-C filter.

2. MODE pin is connected to GND.

3. ITIMER pin is left OPEN.

4. ILIM is connected through resistor to GND.

The following pins of all devices must be connected together:

1. IN

2. OUT

3. EN/UVLO

4. DVDT

5. SWEN

6. PGOOD

7. IMON

8. IREF

9. TEMP

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In this configuration, all the devices are powered up and enabled simultaneously.

• The TPS25990 monitors the combined VIN, VOUT, IMON, TEMP and reports it over the PMBus® telemetry

interface.

• The OVLO threshold is set to max value in all devices by default. For TPS25985x devices, the OV threshold

is fixed in hardware and cannot be changed. The TPS25990 OV threshold can be lowered through PMBus®

writes to the VIN_OV_FLT register. In this case, the TPS25990 uses the SWEN pin to turn off the TPS25985x

devices during OV conditions.

• The UVLO threshold for all devices is set by the external resistor divider from IN to GND on the EN/UVLO

pin. The TPS25990 UV threshold can be changed through PMBus® writes to the VIN_UV_FLT register. In

this case, the TPS25990 uses the SWEN pin to turn off the TPS25985x devices during UV conditions.

• During inrush, the output of all the devices are ramped together based on the DVDT capacitor. However, the

TPS25990 DVDT sourcing current can be configured through the PMBus® writes to the

DEVICE_CONFIG[10:9] register to change the inrush behavior of the whole chain. The TPS25990 controls

the DVDT ramp rate for the whole chain and secondary devices simply follow the ramp rate.

• Due to the inherent difference in R_DSON, the current carried by the TPS25990 is lower than the TPS25985x

devices. Accordingly, the start-up current limit threshold and active current sharing threshold for the

TPS25990 has to be set to a relatively lower value as compared to all the TPS25985x devices by connecting

a proportionately higher ILIM resistor.

• The TPS25990 controls the overall overcurrent threshold of the parallel chain by setting the VIREF threshold

voltage using its internal DAC. The VIREF voltage can be programmed through PMBus® to change the

overcurrent threshold.

• The TPS25990 controls the transient overcurrent blanking interval (t_{OC_TIMER}) for the whole system through

PMBus® writes to the OC_TIMER register. Once the digital timer expires, the TPS25990 pulls the SWEN pin

low to signal all devices to break the circuit simultaneously.

• The system Power Good (PGOOD) indication is a combination of all the individual device PGOOD

indications. All the devices hold their respective PGOOD pins low till their power FET is fully turned on. Once

all devices have reached steady-state, they release their respective PGOOD pin pull-down and the PGOOD

signal for the whole chain is asserted high. The TPS25985x secondary devices have control over the system

PGOOD assertion only during startup. Once in steady state, only the TPS25990 controls the de-assertion of

the PGOOD based on the VOUT_PGTH register setting.

• The fault indication (FLT) for the whole system is provided by TPS25990. However, each secondary device

also asserts its own FLT independently.

Power up: After power up or enable, all the eFuse devices initially hold their SWEN low till the internal blocks

are biased and initialized correctly. After that, each device releases its own SWEN. After all devices have

released their SWEN, the combined SWEN goes high and the devices are ready to turn on their respective FETs

at the same time.

Inrush: During inrush, because the DVDT pins are tied together to a single DVDT capacitor all the devices turn

on the output with the same slew rate (SR). Choose the common DVDT capacitor (C_DVDT) as per 方程式 21 and

方程式22.

I

mA

V

ms

INRUSH

SR

=

(21)

(22)

C

µF

OUT

42000 × k

C

pF =

dVdt

V

SR

ms

Refer to 节8.3.4.1 section for more details.

The internal balancing circuits ensure that the load current is shared among all devices during start-up. This

action prevents a situation where some devices turn on faster than others and experience more thermal stress

as compared to other devices. This can potentially result in premature or partial shutdown of the parallel chain,

or even SOA damage to the devices. The current balancing scheme ensures the inrush capability of the chain

scales according to the number of devices connected in parallel, thereby ensuring successful start-up with larger

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output capacitances or higher loading during start-up. All devices hold their respective PGOOD signals low

during start-up. After the output ramps up fully and reaches steady-state, each device releases its own PGOOD

pulldown. Because the DVDT pins of all devices are tied together, the internal gate high detection of all devices

is synchronized. There can be some threshold or timing mismatches between devices leading to PGOOD

assertion in a staggered manner. However, because the PGOOD pins of all devices are tied together, the

combined PGOOD signal becomes high only after all devices have released their PGOOD pulldown. This

signals the downstream load that it is okay to draw power.

Steady-state: During steady-state, all devices share current nearly equally using the active current sharing

mechanism which actively regulates the respective device R_DSONto evenly distribute current across all the

devices in the parallel chain. Once PGOOD is asserted, de-assertion is controlled only by TPS25990 and based

on VOUT_PGTH register setting.

备注

The TPS25985x current can be slightly higher as compared to TPS25990 higher owing to its lower on-

resistance. This must be fine as long as the steady-state current does not exceed the recommended

maximum continuous rating for the device.

Overcurrent during steady-state: The circuit-breaker threshold for the parallel chain is based on the total

system current rather than the current flowing through individual devices. This is done by connecting the IMON

pins of all the devices together to a single resistor (R_IMON) to GND. Similarly, the IREF pins of all devices are tied

together and TPS25990 uses internal programmable DAC (VIREF) to generate a common reference for the

overcurrent protection block in all the devices. This action helps minimize the contribution of V_IREFvariation to

the overall mismatch in overcurrent threshold between devices.

In this case, choose the R_IMONas per the following equation:

V

IREF

R

=

(23)

IMON

G

× I

IMON

OCP(TOTAL)

The start-up current limit and active current sharing threshold for each device is set independently using the ILIM

pin. The R_ILIMvalue for the TPS25990 must be selected based on the following equation:

1.1 × 4N − 1 × R

IMON

R

=

(24)

ILIM 25990

9

The R_ILIMvalue for each TPS25985x must be selected based on the following equation:

1.1 × 4N − 1 × R

IMON

R

=

(25)

ILIM 25985

12

Where N = Number of devices in parallel chain (1 × TPS25990 + (N - 1) × TPS25985x)

Other variations: The IREF pin can be driven from an external precision voltage reference with low impedance.

During an overcurrent event, the overcurrent detection of all the devices is triggered simultaneously. This in turn

triggers the overcurrent blanking timer (OC_TIMER) in TPS25990. The TPS25990 uses the OC_TIMER expiry

event as a trigger to pull the SWEN low for all the devices, thereby initiating the circuit-breaker action for the

whole chain at the same time. This mechanism ensures that mismatches in the current distribution, overcurrent

thresholds and OC_TIMER intervals among the devices do not degrade the accuracy of the circuit-breaker

threshold of the complete parallel chain or the overcurrent blanking interval. However, the secondary devices

also maintain their backup overcurrent timer and can trigger the shutdown of the whole chain if the primary

device fails to do so within a certain interval.

Severe overcurrent (short circuit): If there is a severe fault at the output (for example, output shorted to

ground with a low impedance path), the current builds up rapidly to a high value and triggers the fast-trip

response in each device. The devices use two thresholds for fast-trip protection – a user-adjustable threshold

(I_SFT= 2 × I_OCPin steady-state or I_SFT= 1.5 × I_LIMduring inrush) as well as a fixed threshold (I_FFTonly during

steady-state). After the fast-trip, the TPS25990 relies on the SC_RETRY configuration bit setting in the

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DEVICE_CONFIG register to determine if the whole chain enters a latched fault or performs a fast recovery by

restarting in current limit manner. If it enters a latched fault, the devices remain latched off till the device is power

cycled or re-enabled, or auto-retry after a delay based on the RETRY_CONFIG register setting.

9.1.3 Multiple Devices, Independent Operation (Multi-zone)

Systems which need power from a common source to be distributed to different power zones can use multiple

TPS25990 devices connected as shown in 图 9-3 to provide independent monitoring and protection for each

zone.

TPS25990x

IN

VIN

VOUT1

OUT

IREF/DAC2

VDD

TEMP/CMP

EN/UVLO

EN

VLSTBY

VL VL

VL

SWEN

SCL

PG1

PG

SDA

FLT1

SMBA#

ADDR0

ADDR1

FLT

DAC1

GND

ILIM DVDT IMON

TPS25990x

IN

VOUT2

OUT

IREF/DAC2

VDD

TEMP/CMP

EN/UVLO

VLSTBY

VL VL

SWEN

SCL

PG2

SDA

PG

SMBA#

FLT2

FLT

ADDR0

ADDR1

DAC1

GND

ILIM DVDT IMON

TPS25990x

IN

VOUT3

OUT

IREF/DAC2

VDD

TEMP/CMP

EN/UVLO

VLSTBY

VL VL

SWEN

SCL

SDA

PG3

PG

FLT3

FLT

SMBA#

ADDR0

ADDR1

DAC1

GND

ILIM DVDT IMON

图9-3. Multiple TPS25990 Devices Delivering Power to Different Zones in a System

In this configuration, the following pins of each device are tied to the respective pins on the other devices.

1. IN

2. EN/UVLO

3. SCL

4. SDA

5. SMBA#

备注

The EN/UVLO pins can be separated if each zone needs to have a different hardware control signal or

UVLO threshold.

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In this configuration, all the devices are monitored and controlled independently through the PMBus®. Because

the devices share the same bus, they must have different device addresses, which can be set using different

pin-strapping combinations on the ADDR0 and ADDR1 pins.

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9.2 Typical Application: 12-V, 4-kW Power Path Protection with PMBus^®Interface in Datacenter

Servers

This design example considers a 12 V system operating voltage with a tolerance of ±10%. The maximum

steady-state load current is 333 A. If the load current exceeds 367 A, the eFuse circuit must allow transient

overload currents up to a 10 ms interval. For persistent overloads lasting longer than that, the eFuse circuit must

break the circuit and then latch-off. The eFuse circuit must charge a bulk capacitance of 50 mF and support

approximately 7.5% of the steady-state load during start-up. 图 9-4 shows the application schematic for this

design example.

V_DD-µC

10 pF

10 k

ADDR0

TPS25990x

AUX

SCL

SDA

SMBA#

AUX

IN

ADDR1

OUT

VOUT

VIN

1 nF

R₁

10

0.1 µF

R₂

IREF

TEMP

IMON

VDD

2.2 µF

eFuse - 1

IMON

PG

EN

EN/UVLO

SCL

SDA

PG

SDA

SMBA#

FLT

FLT1

SMBA#

SWEN

1 nF

*Power supply input to

the eFuse(s) must be

used to derive V_SWEN

ILIM DVDT

GND

10 k

22 pF

R_IMON

.

100 k

V_SWEN

C_DVDT

V_DD-PULLUP

*

10 k

(2.5 V

to 5 V)

TPS25985x

V_DD-PULLUP

The non-repetitive peak

forward surge current (I_FSM

IN

OUT

)

of the selected diode must

be more than the fast-trip

threshold (2 × I_OCP(TOTAL)).

Two or more Schottky

diodes in parallel must be

used if a single Schottky

diode is unable to meet the

required I_FSMrating.

10

Maximum Clamping Voltage V_C

specification of the selected TVS

diode at I_pp(10/1000 s) (V) must

be lower than the absolute

maximum rating of the power

input (IN) pin for safe operation of

the eFuse.

0.1 µF

IREF

TEMP

IMON

VDD

2.2 µF

eFuse - 2

EN/UVLO

V_DD-PULLUP

PG

ITIMER

SWEN

N = 6 [One (1) TPS25990 eFuse

+ Five (5) TPS25985 eFuses)

R₁= 1 M

R₂= 124 k

R_IMON= 150

FLT2

FLT

MODE GND

ILIM DVDT

R_ILIM2

R_ILIM1= 422

R_ILIM2= 316

R_ILIM3= 316

R_ILIM4= 316

R_ILIM5= 316

R_ILIM6= 316

C_DVDT= 33 nF

TPS25985x

IN

OUT

10

0.1 µF

IREF

TEMP

IMON

VDD

2.2 µF

eFuse - N

TEMP

FLTN

22 pF

V_DD-PULLUP

10 k

EN/UVLO

PG

ITIMER

SWEN

MODE

FLT

DVDT

GND

ILIM

ꢀꢁV_DD-PULLUPshould be less than 5V.

ꢀꢁV_DD-PULLUPand V_SWENcan be the same

R_ILIMN

pullup supply if both are generated

0

from the input (VIN) of the eFuse(s).

图9-4. Application Schematic for a 12-V, 4-kW Power Path Protection Circuit with PMBus^®Interface

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9.2.1 Design Requirements

表9-1 shows the design parameters for this application example.

表9-1. Design Parameters

PARAMETER

VALUE

Input voltage range (V_IN)

10.8 V –13.2 V

Maximum DC load current (I_OUT(max)

Maximum output capacitance (C_LOAD

Are all the loads off until the PG is asserted?

Load at start-up (R_{LOAD(Startup)}

)

333 A

)

50 mF

No

0.48 Ω(equivalent to approximately 7.5% of the maximum steady-

)

state load)

Maximum ambient temperature

Transient overload blanking timer

55°C

10 ms

1.2 V/ms

Yes

Output voltage slew rate

Need to survive a “hot-short”on output condition?

Need to survive a “power up into short”condition?

Can the board be hotplugged in or power cycled?

Load current monitoring needed?

Yes

Need PMBus® interface

for telemetry, control, and configurability?

Yes

Fault response

Latch-off

9.2.2 Detailed Design Procedure

• Determining the number of eFuse devices to be used in parallel

As the design must have PMBus® functionality or interface for telemetry, control, and configuration, the

TPS25990 eFuse must be used as a primary device in parallel with TPS25985x eFuse(s) as secondary

devices in order to support the required steady-state thermal design current. By factoring in a small variation

in the junction to ambient thermal resistance (R_θJA), each TPS25990 eFuse and TPS25985x eFuse is rated

at maximum RMS currents of 50 A and 60 A respectively with a maximum junction temperature of 125 °C.

Therefore, 方程式26 can be used to calculate the number of TPS25985x eFuses (N-1) to be in parallel with a

TPS25990 eFuse to support the maximum steady state DC load current (I_LOAD(max)), for which the solution

must be designed.

I

− 50

OUT max

N − 1 ≥

(26)

60

According to 表9-1, I_OUT(max)is 333 A. Therefore, one (1) TPS25990 and five (5) TPS25985x eFuses are

connected in parallel to support the desired steady-state load current.

• Setting up the primary and secondary devices in a parallel combination of TPS25990 and TPS25985x

eFuses

The TPS25990 functions as a primary device by default. By connecting the MODE pin of all the TPS25985x

eFuses to GND, they are configured as secondary devices.

• Selecting the C_DVDTcapacitor to control the output slew rate and start-up time

For a robust design, the junction temperature of the device must be kept below the absolute maximum rating

during both dynamic (start-up) and steady-state conditions. Typically, dynamic power stresses are orders of

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magnitude greater than static stresses, so it is crucial to establish the right start-up time and inrush current

limit for the capacitance in the system and the associated loads to avoid thermal shutdown during start-up.

表9-2 summarizes the formulas for calculating the average inrush power loss on the eFuses in the presence

of different loads during start-up if the power good (PG) signal is not used to turn on all the downstream

loads.

表9-2. Calculation of Average Power Loss During Inrush

Type of Loads During Start-Up

Expressions to Calculate the Average Inrush Power Loss

2

V

C

IN LOAD

Only output capacitor of C_LOAD(µF)

(27)

(28)

(29)

(30)

2T

ss

2

Output capacitor of C_LOAD(µF) and constant resistance

2

3

C

V

RTH

IN LOAD

IN

LOAD Startup

1

6

1

2

RTH

1

3

+

−

+

2T

R

V

of R_{LOAD(Startup)}(Ω) with turn-ON threshold of V_RTH(V)

ss

IN

2

Output capacitor of C_LOAD(µF) and constant current of

I_{LOAD(Startup)}(A) with turn-ON threshold of V_CTH(V)

C

V

CTH

IN LOAD

1

2

CTH

1

+ V

I

−

+

2

IN LOAD Startup

2T

V

ss

IN

2

Output capacitor of C_LOAD(µF) and constant power of

P_{LOAD(Startup)}(W) with turn-ON threshold of V_PTH(V)

C

V

PTH

IN LOAD

PTH

+ P

ln

+

− 1

LOAD Startup

2T

V

ss

IN

Where V_INis the input voltage and T_ssis the start-up time.

With the different combinations of loads during start-up, the total average inrush power loss (P_INRUSH) can be

calculated using the formulas described in 表9-2. For a successful start-up, the system must satisfy the

condition stated in 方程式31.

P

W

T

s < 8 + 12 N − 1

(31)

INRUSH

ss

Where N denotes the total number of eFuses in parallel and 8 W√s and 12 W√s are the safe operating area

(SOA) limits of a TPS25990 eFuse and a TPS25985x eFuse respectively. This equation can be used to

obtain the maximum allowed T_ss.

备注

TI recommends to use a T_ssin the range of 5 ms to 120 ms to prevent start-up issues.

A capacitor (C_DVDT) must be added at the TPS25990 DVDT pin to GND to set the required value of T_ssas

calculated above. 方程式32 is used to compute the value of C_DVDT. The DVDT pins of all the eFuses in a

parallel chain must be connected together.

42000 × k

C

pF =

(32)

DVDT

V

V /T ms

IN

ss

Refer to 节8.3.4.1 section for more details. In this design example, C_LOAD= 50 mF, R_{LOAD(Startup)}= 0.48 Ω,

V_RTH= 0 V, V_IN= 12 V, and T_ss= 10 ms. P_INRUSHis calculated to be 410 W using the equations provided in

the 表9-2. It is verified that the system satisfies the condition stated in 方程式31 and therefore capable of

having a successful start-up. If 方程式31 does not hold true, start-up loads or T_ssmust be tuned to prevent

the chances of thermal shutdown during start-up. Using V_IN= 12 V, T_ss= 10 ms, k= 1, and 方程式32, the

required C_DVDTvalue can be calculated to be 35 nF. The closest standard value of C_DVDTis 33 nF with 10%

tolerance and DC voltage rating of 25 V.

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备注

In some systems, there can be active load circuits (for example, DC-DC converters) with low turn-

on threshold voltages which can start drawing power before the eFuse has completed the inrush

sequence. This action can cause additional power dissipation inside the eFuse during start-up and

can lead to thermal shutdown. TI recommends using the Power Good (PG) pin of the eFuse to

enable and disable the load circuit. This action ensures that the load is turned on only when the

eFuse has completed its start-up and is ready to deliver full power without the risk of hitting thermal

shutdown.

• Selecting the V_IREFto set the reference voltage for overcurrent protection and active current sharing

The reference voltage (V_IREF) for overcurrent protection and active current sharing will be at 1 V by default.

However, it can be programmed via PMBus® using the VIREF register if another reference voltage is needed

in the range of 0.3 V to 1.2 V. When the voltage at the IMON pin (V_IMON) is used as an input to an ADC to

monitor the system current or to implement the Platform Power Control (Intel PSYS) functionality inside the

VR controller, V_IREFmust be set to half of the maximum voltage range of the ISYS_IN input of the controller.

This action provides the necessary headroom and dynamic range for the system to accurately monitor the

load current up to the fast-trip threshold (2 × I_OCP(TOTAL)). For improved noise immunity, place a 1 nF ceramic

capacitor from the IREF pin to GND.

备注

Maintain V_IREFwithin the recommended voltage to ensure proper operation of overcurrent

detection circuit.

• Selecting the R_IMONresistor to set the overcurrent (circuit-breaker) and fast-trip thresholds during

steady-state

TPS25990 eFuse responds to the output overcurrent conditions during steady-state by turning off the output

after a user-adjustable transient fault blanking interval. This eFuse continuously senses the total system

current (I_OUT) and produces a proportional analog current output (I_IMON) on the IMON pin. This generates a

voltage (V_IMON) across the IMON pin resistor (R_IMON) in response to the load current, which is defined as 方程

式33.

V

= I

× G

× R

IMON

(33)

IMON

OUT

IMON

G_IMONis the current monitor gain (I_IMON: I_OUT), whose typical value is 18.18 µA/A. The overcurrent condition

is detected by comparing the V_IMONagainst the V_IREFas a threshold. The circuit-breaker threshold during

steady-state (I_OCP(TOTAL)) can be calculated using 方程式34.

V

IREF

I

=

(34)

OCP TOTAL

G

× R

IMON

In this design example, I_OCP(TOTAL)is considered to be around 1.1 times I_OUT(max). Hence, I_OCP(TOTAL)is

required to be set at 367 A, and R_IMONcan be calculated to be 150 Ωwith G_IMONas 18.18 µA/A and V_IREFas

1 V. The value of R_IMONis 150 Ωwith 0.1% tolerance and power rating of 100 mW. This results in a circuit-

breaker threshold of 367 A. For noise immunity, place a 22 pF ceramic capacitor from the IMON pin to GND.

备注

The total system output current (I_OUT) must be considered when selecting R_IMON, not the current

carried by each individual device.

• Selecting the R_ILIMresistor to set the current limit and fast-trip thresholds during start-up and the

active sharing threshold during steady-state

R_ILIMis used in setting up the active current sharing threshold during steady-state and the overcurrent limit

during startup among the devices in a parallel chain. Each device continuously monitors the current flowing

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through it (I_DEVICE) and outputs a proportional analog output current on its own ILIM pin. This in turn produces

a proportional voltage (V_ILIM) across the respective ILIM pin resistor (R_ILIM), which is expressed as 方程式35.

V

= I

× G

× R

ILIM

(35)

ILIM

DEVICE

ILIM

G_ILIMis the current monitor gain (I_ILIM: I_DEVICE), whose typical value is 18.18 μA/A.

– Active current sharing during steady-state: This mechanism operates only after the device reaches

steady-state and acts independently by comparing its own load current information (V_ILIM) with the Active

Current Sharing reference (CLREF_LIN) threshold, defined as 方程式36.

1.1 × V

IREF

CLREF

=

(36)

LIN

3

The typical values of R_DSONfor TPS25990 and TPS25985x eFuses are 0.79 mΩand 0.59 mΩ

respectively. Therefore, when one (1) TPS25990 eFuse and one (1) TPS25985x eFuse are in parallel, it is

expected that the TPS25990 eFuse will carry 0.75 times the current flowing through the TPS25985x

eFuse in steady-state. Therefore, R_{LIM(TPS25990)}must be calculated using 方程式37 to define the active

current sharing threshold as 3×I_OCP(TOTAL)/(4N-1) for TPS25990 eFuse, where N is the total number of

devices in parallel (1 × TPS25990 + (N - 1) × TPS25985x). Whereas, 方程式38 needs to be followed to

obtain the value of R_{LIM(TPS25985)}in setting up the active current sharing threshold as 4×I_OCP(TOTAL)/(4N-1)

for each TPS25985x eFuse. Using N = 6, R_IMON= 150 Ω, and 方程式37, R_{ILIM(TPS25990)}can be

calculated to be 421.6 Ω. The closest standard value of 422 Ωwith 0.1% tolerance and power rating of

100 mW resistance is selected as R_{ILIM(TPS25990)}for TPS25990 eFuse. Using 方程式38, R_{ILIM(TPS25985)}is

obtained as 316.2 Ω.The closest standard value of 316 Ωwith 0.1% tolerance and power rating of 100

mW resistances are selected as R_{ILIM(TPS25985)}for five (5) TPS25985x eFuses.

1.1 × 4N − 1 × R

IMON

R

=

(37)

ILIM TPS25990

9

1.1 × 4N − 1 × R

IMON

R

=

(38)

ILIM TPS25985

12

备注

To determine the value of R_ILIM, 方程式39 must be used if a different threshold for active

current sharing (I_LIM(ACS)) is desired.

1.1 × V

IREF

R

=

(39)

ILIM

3 × G

ILIM

× I

LIM ACS

When computing the current limit threshold during start-up in the next sub-section, ensure to

use this R_ILIMvalue.

– Overcurrent limit during start-up: During inrush, the overcurrent condition for each device is detected

by comparing its own load current information (V_ILIM) with a scaled reference voltage as depicted in 方程

式40.

0.7 × V

IREF

CLREF

=

(40)

SAT

3

The current limit threshold during start-up can be calculated using 方程式41.

CLREF

SAT

I

=

G

(41)

ILIM Startup

× R

ILIM

By using a R_{ILIM(TPS25990)}value of 422 Ω, the start-up current is limited to 30 A for TPS25990 with V_IREF

of 1 V. Whereas, the start-up current is limited to 40 A for TPS25985x with V_IREFof 1 V using a

R_{ILIM(TPS25985)}value of 316 Ω. Hence, the total start-up current limit becomes ~230 A for this design

example.

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备注

The active current limit block employs a foldback mechanism during start-up based on V_OUT

.

When V_OUTis below the foldback threshold (V_FB) of 2 V, the current limit threshold is further

lowered.

• Selecting the overcurrent blanking timer duration (t_{OC_TIMER}

)

The overcurrent blanking timer duration (t_{OC_TIMER}) for the entire parallel chain is controlled by TPS25990

and is set to 2.18 ms by default. However, it can be programmed via PMBus® using the OC_TIMER (E6h)

register to a different value in the range of 0 ms to 27.8 ms in 100 μs steps. The ITIMER pin for all the

secondary TPS25985x devices must be left open.

• Selecting the resistors to set the undervoltage lockout threshold

The undervoltage lockout (UVLO) threshold is adjusted by employing the external voltage divider network of

R₁and R₂connected between IN, EN/UVLO, and GND pins of the device as described in Undervoltage

protection section. The resistor values required for setting up the UVLO threshold are calculated using 方程式

42.

R

+ R

2

1

V

= V

(42)

IN UV

UVLO R

R

2

To minimize the input current drawn from the power supply, TI recommends using higher resistance values

for R₁and R₂. The current drawn by R₁and R₂from the power supply is I_R12= V_IN/ (R₁+ R₂). However, the

leakage currents due to external active components connected to the resistor string can add errors to these

calculations. So, the resistor string current, I_R12must be 20 times greater than the leakage current at the EN/

UVLO pin (I_ENLKG). From the device electrical specifications, I_ENLKGis 0.1 µA (maximum) and UVLO rising

threshold V_UVLO(R)= 1.2 V. From the design requirements, V_INUVLO= 10.8 V. First choose the value of R₁= 1

MΩ and use Equation 13 to calculate R₂= 125 kΩ. Use the closest standard 1% resistor values: R₁= 1 MΩ

and R₂= 124 kΩ. For noise reduction, place a 1 nF ceramic capacitor across the EN/UVLO pin and GND.

• Selecting the R-C filter between VIN and VDD for TPS25990 and TPS25985x

VDD pin is intended to power the internal control circuitry of the eFuse with a filtered and stable supply, not

affected by system transients. Therefore, use an R (10 Ω) –C (2.2 µF) filter from the input supply (IN pin) to

the VDD pin. This helps to filter out the supply noises and to hold up the controller supply during severe faults

such as short-circuit at the output. In a parallel chain, this R-C filter must be employed for each device.

• Selecting the pullup resistors and power supplies for SWEN, PG and FLT pins

FLT, PG, and CMPOUT are open drain outputs. If these logic signals are used, the corresponding pins must

be pulled up to the appropriate voltages (< 5 V) through 10 kΩpull-up resistances.

备注

– SWEN pin must be pulled up to a voltage in the range of 2.5 V to 5 V through a 100-kΩ

resistance. This pullup power supply must be generated from the input to the eFuse and

available before the eFuse is enabled as discussed in 节9.3, without which the eFuse does not

start up.

– There can be some threshold or timing mismatches between devices leading to PG assertion in

a staggered manner. Therefore, it is advisable to connect the PG pins of all the devices in

parallel. This will ensure that the combined PG signal becomes high only after all devices have

released their PG pulldowns.

• Selecting the pullup resistors for PMBus® SCL, SDA, and SMBA# lines

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The SCL, SDA, and SMBA# lines can be pulled up to potentials less than 5 V in general with pull-up resistors

of 10 kΩ. However, to obtain the appropriate values of these pull-up resistors in accordance with the system

specifications, please refer to I2C Bus Pullup Resistor Calculation.

• Configuring the PMBus® target device address

Place appropriate resistors across ADDR0 and ADDR1 to GND or leave these pins floating or connect them

to GND as described in 节8.3.14.1 to set the preferred device address. To improve the noise immunity for

correct address decoding, connect 10 pF ceramic capacitors in parallel with the resistors on ADDR0 and

ADDR1.

• Selection of TVS diode at input and Schottky diode at output

In the case of a short circuit and overload current limit when the device interrupts a large amount of current

instantaneously, the input inductance generates a positive voltage spike on the input, whereas the output

inductance creates a negative voltage spike on the output. The peak amplitudes of these voltage spikes

(transients) are dependent on the value of inductance in series with the input or output of the device. Such

transients can exceed the absolute maximum ratings of the device and eventually lead to failures due to

electrical overstress (EOS) if appropriate steps are not taken to address this issue. Typical methods for

addressing this issue include:

1. Minimize lead length and inductance into and out of the device.

2. Use a large PCB GND plane.

3. Addition of the Transient Voltage Suppressor (TVS) diodes to clamp the positive transient spike at the

input.

4. Using Schottky diodes across the output to absorb negative spikes.

Refer to TVS Clamping in Hot-Swap Circuits and Selecting TVS Diodes in Hot-Swap and ORing Applications

for details on selecting an appropriate TVS diode and the number of TVS diodes to be in parallel to effectively

clamp the positive transients at the input below the absolute maximum ratings of the IN pin (20 V). These

TVS diodes also help to limit the transient voltage at the IN pin during the Hot Plug event. Four (4) SMDJ12A

are used in parallel in this design example.

备注

Maximum Clamping Voltage V_Cspecification of the selected TVS diode at I_pp(10/1000 μs) (V)

must be lower than the absolute maximum rating of the power input (IN) pin for safe operation of

the eFuse.

Selection of the Schottky diodes must be based on the following criteria:

– The non-repetitive peak forward surge current (I_FSM) of the selected diode must be more than the fast-trip

threshold (2 × I_OCP(TOTAL)). Two or more Schottky diodes in parallel must be used if a single Schottky

diode is unable to meet the required I_FSMrating. 方程式43 calculates the number of Schottky diodes

(N_Schottky) that must be used in parallel.

2 × I

OCP TOTAL

N

>

(43)

Scℎottky

I

FSM

– Forward Voltage Drop (V_F) at near to I_FSMmust be as small as possible. Ideally, the negative transient

voltage at the OUT pin must be clamped within the absolute maximum rating of the OUT pin (–1 V).

– DC Blocking Voltage (V_RM) must be more than the maximum input operating voltage.

– Leakage current (I_R) must be as small as possible.

Three (3) SBR10U45SP5 are used in parallel in this design example.

• Selecting C_INand C_OUT

TI recommends to add ceramic bypass capacitors to help stabilize the voltages on the input and output. The

value of C_INmust be kept small to minimize the current spike during hot-plug events. For each device, 0.1 µF

English Data Sheet: SLVSGG4

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of C_INis a reasonable target. Because C_OUTdoes not get charged during hot-plug, a larger value such as 2.2

µF can be used at the OUT pin of each device.

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9.2.3 Application Performance Plots

All the waveforms below are captured on an evaluation setup with one (1) TPS25990 eFuse and five (5)

TPS25985x eFuses in parallel. All the pullup supplies are derived from a separate standby rail.

VIN

VOUT

DVDT

Input Current

图9-6. Start-up with EN/UVLO: V_IN= 12 V, EN/UVLO

Stepped Up From 0 V to 3 V, C_LOAD= 50 mF,

R_{LOAD(Start-up)}= 0.48 Ω, C_DVDT= 33 nF, V_IREF= 1 V,

R_{ILIM(TPS25990)}= 422 Ω, and R_{ILIM(TPS25985)}= 316 Ω

图9-5. Input Hot Plug: V_INStepped Up from 0 V to

12 V, C_LOAD= 50 mF, R_{LOAD(Start-up)}= 0.48 Ω, C_DVDT

= 33 nF, V_IREF= 1 V, R_{ILIM(TPS25990)}= 422 Ω, and

R_{ILIM(TPS25985)}= 316 Ω

图9-8. Power Up into Short (Current distribution

among six devices in parallel): V_IN= 12 V, EN/

UVLO Stepped Up From 0 V to 3 V, V_IREF= 1 V,

R_{ILIM(TPS25990)}= 422 Ω, R_{ILIM(TPS25985)}= 316 Ω, and

OUT Shorted to GND

图9-7. Power Up into Short: V_IN= 12 V, EN/UVLO

Stepped Up From 0 V to 3 V, V_IREF= 1 V,

R_{ILIM(TPS25990)}= 422 Ω, R_{ILIM(TPS25985)}= 316 Ω, and

OUT Shorted to GND

图9-9. Transient Overload: V_IN= 12 V, t_{OC_TIMER}

=

图9-10. Transient Overload (Current distribution

among six devices in parallel): V_IN= 12 V, t_{OC_TIMER}

= 10 ms, C_LOAD= 50 mF, R_IMON= 150 Ω, V_IREF= 1 V,

and Load Current Stepped from 333 A to 500 A

then 333 A within 8.5 ms

10 ms, C_LOAD= 50 mF, R_IMON= 150 Ω, V_IREF= 1 V,

and Load Current Stepped from 333 A to 500 A

then 333 A within 8.5 ms

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图9-11. Circuit-Breaker Response: V_IN= 12 V,

t_{OC_TIMER}= 10 ms, C_LOAD= 50 mF, R_IMON= 150 Ω,

图9-12. Circuit-Breaker Response (Current

distribution among six devices in parallel): V_IN= 12

V_IREF= 1 V, and Load Current Stepped from 333 A V, t_{OC_TIMER}= 17 ms, C_LOAD= 50 mF, R_IMON= 150 Ω,

to 530 A for more than 10 ms

V_IREF= 1 V, and Load Current Stepped from 333 A

to 530 A for more than 17 ms

图9-13. Output Hot-Short Response: V_IN= 12 V,

R_IMON= 150 Ω, V_IREF= 1 V, and OUT Shorted to

GND

图9-14. One (1) TPS25990 eFuse and one (1)

TPS25985x eFuse in Parallel: Temperature Rise

with 110-A DC Current at Room Temperature (No

Air-Flow)

9.3 Best Design Practices

TPS25990 needs the SWEN pin to be pulled up to a supply rail which is powered up before the device is

enabled. Failing this, the device is not able to turn on the output. The SWEN pullup supply must not be derived

from the output of the eFuse. Use one of the following options to derive the pullup supply rail for SWEN.

1. Use an existing standby rail in the system, which is derived from the main power input and comes up before

the eFuse is turned on.

2. Use an LDO (3.3 V or 5 V) powered from the main power input.

LDO

100 k

V_SWEN

eFuse Input

Supply

IN

OUT

GND

SWEN

0.1 µF

图9-15. LDO Used as Pullup Supply for SWEN

3. Use a Zener regular powered from the main power input.

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100 k

eFuse Input

Supply

SWEN

4.7 V Zener

Diode

0.1 µF

图9-16. Zener Regulator Used as Pullup Supply for SWEN

4. Use the ITIMER pin of one of the secondary eFuses (TPS25985x). Ensure the ITIMER pin does not have

excess loading which can interfere with the normal overcurrent blanking timer functionality.

ITIMER of secondary

TPS25985 eFuse

100 k

SWEN

图9-17. ITIMER Pin Used as Pullup Supply for SWEN

The ground connections for the various components around the TPS25990 & TPS25985 must be wired directly

to each other and the GND pins of respective eFuses. This must be followed by connecting them to the system

ground at one point. For more details, refer to TPS25990EVM eFuse Evaluation Board. Do not connect the

various component grounds through the high current system ground line.

9.4 Power Supply Recommendations

The TPS25990 devices are designed for a supply voltage in the range of 2.9 V to 16 V on the IN pin and 4.5 V to

16 V on the VDD pin. TI recommends using a minimum capacitance of 0.1 μF on the IN pin of each device in

parallel chain to avoid coupling of high slew rates during hot plug events. TI also recommends using an R-C filter

from the IN supply to the VDD pin to filter out supply noise and to hold up the controller supply during severe

faults such as short-circuit.

备注

1. If in-system programming of configuration register non-volatile memory is needed, then TI

recommends using a minimum supply of 10 V on VDD.

2. The device can be used with VIN voltage rails down to 2.9 V as long as the VDD rail is supplied

with an independent bias voltage of 4.5 V or higher.

9.4.1 Transient Protection

In the case of a short-circuit or circuit-breaker event, when the device interrupts current flow, the input

inductance generates a positive voltage spike on the input, and the output inductance generates a negative

voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of

inductance in series to the input or output of the device. Such transients can exceed the absolute maximum

ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients

include:

• Minimize lead length and inductance into and out of the device.

• Use a large PCB GND plane.

• Connect a Schottky diode from the OUT pin ground to absorb negative spikes.

• Connect a low ESR capacitor of 2.2 μF or higher at the OUT pin very close to the device.

• Connect a ceramic capacitor C_IN= 0.1 μF or higher at the IN pin very close to the device to dampen the rise

time of input transients. The capacitor voltage rating must be at least twice the input supply voltage to be able

to withstand the positive voltage excursion during inductive ringing.

The approximate value of input capacitance can be estimated with 方程式44.

L

IN

V

= V + I ×

LOAD

(44)

SPIKE Absolute

IN

C

IN

V_INis the nominal supply voltage.

English Data Sheet: SLVSGG4

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ZHCSOF7B –SEPTEMBER 2022 –REVISED JUNE 2023

I_LOADis the load current.

L_INequals the effective inductance seen looking into the source.

C_INis the capacitance present at the input.

• Some applications can require the addition of a Transient Voltage Suppressor (TVS) to prevent transients

from exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude

of the transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive

energy dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which

can couple to the internal control circuits and cause unexpected behavior.

The circuit implementation with optional protection components is shown in 图9-18.

TPS25990x

IN

VIN

VOUT

OUT

*

IREF/DAC2

*

VDD

IMON

EN

EN/UVLO

VL

VLSTBY

VL

PG

SWEN

FLT

SCL

SDA

SCL

SDA

TEMP/CMP

AUX

DAC1

SMBA#

ADDR0 ADDR1 GND

ILIM DVDT

图9-18. Circuit Implementation with Optional Protection Components

9.4.2 Output Short-Circuit Measurements

It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in

results:

• Source bypassing

• Input leads

• Circuit layout

• Component selection

• Output shorting method

• Relative location of the short

• Instrumentation

The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure

that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like

those in this data sheet because every setup is different.

9.5 Layout

9.5.1 Layout Guidelines

• For all applications, TI recommends a ceramic decoupling capacitor of 0.1 μF or greater between the IN

terminal and GND terminal.

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• For all applications, TI recommends a ceramic decoupling capacitor of 2.2 μF or greater between the OUT

terminal and GND terminal.

• The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care

must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the

GND terminal of the IC. See Figure below for a PCB layout example.

• High current-carrying power-path connections must be as short as possible and must be sized to carry at

least twice the full-load current.

• The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground must be a

copper plane or island on the board.

• The IN and OUT pins are used for Heat Dissipation. Connect to as much copper area as possible with

thermal vias.

• Locate the following support components close to their connection pins:

– C_IN

– C_OUT

– C_VDD

– C_TEMP

– R_ILIM

– R_IMON

– C_IREF

– C_DVDT

– Resistors for the EN/UVLO pin

– Resistors for the ADDR0, ADDR1 pins

• Connect the other end of the component to the GND pin of the device with shortest trace length. The trace

routing for the ADDR0, ADDR1, C_IN, C_OUT, C_VDD, C_IREF, R_ILIM, R_IMON, C_TEMPand C_DVDTcomponents to the

device must be as short as possible to reduce parasitic effects on the current limit and soft-start timing. These

traces must not have any coupling to switching signals on the board.

• Because the IMON, ILIM and IREF pins directly control the overcurrent protection behavior of the device, the

PCB routing of these nodes must be kept away from any noisy (switching) signals.

• TI recommends to keep the parasitic loading on SWEN pin to a minimum to avoid synchronization issues.

• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the

device they are intended to protect. These protection devices must be routed with short traces to reduce

inductance. For example, TI recommends a protection Schottky diode to address negative transients due to

switching of inductive loads, and it must be physically close to the OUT pins.

English Data Sheet: SLVSGG4

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9.5.2 Layout Example

Top Power layer

Top Power GND layer

Top Signal GND layer

Bottom Power layer

TPS25990

+

-

VOUT

VIN

TPS25985

图9-19. TPS25990 and TPS25985x Parallel Devices Layout Example

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ZHCSOF7B –SEPTEMBER 2022 –REVISED JUNE 2023

10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed below.

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, TPS25990EVM eFuse Evaluation Board

• Texas Instruments, TPS25990x Design Calculator

10.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.4 Trademarks

SMBus^™is a trademark of Intel.

TI E2E^™is a trademark of Texas Instruments.

PMBus^®is a registered trademark of SMIF.

Intel^®is a registered trademark of Intel.

所有商标均为其各自所有者的财产。

10.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: SLVSGG4

138 Submit Document Feedback

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PACKAGE OUTLINE

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

A

RQP0026A

5.1

4.9

B

PIN 1 IDENTIFICATION

4.6

4.4

C

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

4X TYP (0.15)

0.3

0.2

8X

9

2.55

2.35

4X TYP (0.35)

TYP (0.1)

8X

10

13

0.25

0.15

0.1

4X 1.7

14

14X

4X 1.2

4X 0.8

4X 0.4

C A B

0.05

C

0.0 PKG

0.45

0.35

4X

0.85

0.65

4X

0.1

C A B

22

1

0.05

C

26

23

PIN1 ID

0.4

0.3

4X

(OPTIONAL)

0.6

0.4

0.1

0.05

C A B

18X

C

4225325/B 10/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RQP0026A

26

23

(1.975)

1

22

4X (1.7)

4X (1.2)

(1.125)

8X

(2.65)

4X (0.8)

4X (0.4)

(0.0)

PKG

14X (0.2)

(R0.05) TYP

(1.125)

9

14

(1.975)

4X (0.4)

13

10

4X (0.95)

18X (0.7)

4X (0.35)

8X (0.25)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.05 MIN

ALL AROUND

METAL

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

EXPOSED METAL

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4225325/B 10/2020

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RQP0026A

26

23

METAL TYP

(1.975)

1

22

4X (1.675)

4X (1.2)

4X (0.8)

4X (0.4)

(0.0)

PKG

16X

(1.225)

14X (0.2)

2X (0.4)

(0.2)

(R0.05) TYP

2X (1.8)

(1.975)

9

14

4X (0.35)

13

10

4X (0.95)

4X (0.35)

18X (0.7)

16X (0.21)

SOLDER PASTE EXAMPLE

BASED ON 0.1mm THICK STENCIL

PIN 1,9,14 & 22: 96%; PIN 10-13 & 23-26: 77%

SCALE: 15X

4225325/B 10/2020

NOTES: (continued)

5.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	PTPS25990ARQPR
厂家：	TEXAS INSTRUMENTS
描述：	具有数字遥测控制器的 2.9V 至 16V、0.79mΩ、60A 电子保险丝 \| RQP \| 26 \| -40 to 125 电子控制器遥测
文件：	总146页 (文件大小：11248K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PTPS25990ARQPR [TI]

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