PTPS6521920WRHBRQ1 [TI]
Automotive power management integrated circuit (PMIC) for ARM® Cortex®-A53 processors | RHB | 32 | -40 to 125;型号: | PTPS6521920WRHBRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | Automotive power management integrated circuit (PMIC) for ARM® Cortex®-A53 processors | RHB | 32 | -40 to 125 集成电源管理电路 |
文件: | 总155页 (文件大小:3923K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS65219-Q1
ZHCSNP4A –DECEMBER 2022 –REVISED MAY 2023
TPS65219-Q1 适用于ARM Cortex®—A53 处理器
1 特性
3 说明
• 3 个高达2.3MHz 非固定开关频率或固定频率模式
的降压转换器:
TPS65219-Q1 是一款电源管理 IC (PMIC),旨在为汽
车应用中的各种 SoC 供电。该 PMIC 的额定环境温度
范围为 -40°C 至 +125°C,因此适用于汽车应用。该器
件包括三个同步直流/直流降压转换器和四个线性稳压
器。
– 1 个VIN:2.5V –5.5V;IOUT:3.5A;VOUT
0.6V –3.4V
– 2 个VIN:2.5V –5.5V;IOUT:2A;VOUT 0.6V
–3.4V
• 4 个线性稳压器:
直流/直流转换器能够提供 1 个3.5A 电流和2 个2A 电
流。这些转换器需要一个 470nH 的小型电感器、一个
4.7μF 的输入电容,以及每个电源轨一个最小 10μF
的输出电容。
– 2 个VIN:1.5V –5.5V;IOUT:400mA;
VOUT:0.6V –3.4V(可配置为负载开关和旁路
模式,支持SD 卡)
其中两个 LDO 在0.6V 至3.4V 的输出电压范围内支持
400mA 的输出电流。这些 LDO 支持旁路模式,充当
负载开关,并允许在工作期间改变电压。其他两个
LDO 在 1.2V 至 3.3V 的输出电压范围内支持 300mA
的输出电流。这些LDO 也支持负载开关模式。
– 2x VIN:2.2V –5.5V;IOUT:300mA;VOUT
1.2V –3.3V(可配置为负载开关)
• 所有三个降压转换器上的动态电压调节
• 低IQ/PFM 的PWM 模式(准固定频率)或固定频
率模式
:
• 可编程电源时序和默认电压
• I2C 接口,支持标准模式、快速模式和快速模式增
强版
• 设计为支持具有多达14 个以上电源轨的系统(2 个
TPS65219-Q1,每个7 个电源轨+ GPO 控制的外
部电源轨)
I2C 接口、IO、GPIO 和多功能引脚(MFP) 可实现与各
种SoC 的无缝连接。
封装信息(1)
器件型号
封装
封装尺寸(标称值)
TPS65219-Q1
5.00mm × 5.00mm
32 引脚QFN - 可湿
性侧面
• 2 个GPO、1 个GPIO 和3 个多功能引脚
• EEPROM 可编程性
• 提供功能安全
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
VSYS (2.5 V
PMIC
2 应用
to 5 V)
0.6 – 3.4 V, 3.5 A
0.6 – 3.4 V, 2 A
0.6 – 3.4 V, 2 A
• AM62x-Q1 和AM64x-Q1 等低功耗汽车MPU
• 音响主机、数字仪表组、远程信息处理控制单元、
激光雷达处理器
• DMS/OMS、eMirror 和CMS
• ISP 和深度学习
BUCK1
BUCK2
BUCK3
VSYS
PVIN_Bx
PVIN_LDOx
3
3
0.6 – 3.4 V, 400 mA
0.6 – 3.4 V, 400 mA
VSYS
LDO1
LDO2
1.2 – 3.3 V, 300 mA
1.2 – 3.3 V, 300 mA
LDO3
LDO4
Push-
button
(optional)
SCL
SDA
nINT
EN/PB/VSENSE
nRSTOUT
VSEL_SD
MODE/STBY
RESET
GPIO
GPO1
GPO2
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSGA1
TPS65219-Q1
ZHCSNP4A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
7 Detailed Description......................................................29
7.1 Overview...................................................................29
7.2 Functional Block Diagram.........................................30
7.3 Feature Description...................................................30
7.4 Device Functional Modes..........................................55
7.5 User Registers.......................................................... 61
7.6 Device Registers.......................................................62
8 Application and Implementation................................138
8.1 Application Information........................................... 138
8.2 Typical Application.................................................. 138
8.3 Application Curves .................................................143
8.4 Power Supply Recommendations...........................145
8.5 Layout..................................................................... 145
9 Device and Documentation Support..........................147
9.1 Documentation Support.......................................... 147
9.2 接收文档更新通知................................................... 147
9.3 支持资源..................................................................147
9.4 Trademarks.............................................................147
9.5 静电放电警告.......................................................... 147
9.6 术语表..................................................................... 147
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................9
6.5 System Control Thresholds.........................................9
6.6 BUCK1 Converter..................................................... 11
6.7 BUCK2, BUCK3 Converter....................................... 14
6.8 General Purpose LDOs (LDO1, LDO2).................... 17
6.9 General Purpose LDOs (LDO3, LDO4).................... 20
6.10 GPIOs and multi-function pins (EN/PB/
VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO,
MODE/RESET, MODE/STBY, VSEL_SD/
VSEL_DDR)................................................................ 21
6.11 Voltage and Temperature Monitors......................... 23
6.12 I2C Interface............................................................24
6.13 Typical Characteristics............................................27
Information.................................................................. 148
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2022) to Revision A (May 2023)
Page
• 将器件状态从“预告信息”更改为“量产数据”................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGA1
2
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TPS65219-Q1
ZHCSNP4A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
5 Pin Configuration and Functions
1
2
3
4
5
6
7
8
24 FB_B3
FB_B1
VLDO4
23
22
21
20
LX_B1_1
LX_B1_2
PVIN_LDO34
VLDO3
PVIN_B1_1
PVIN_B1_2
PVIN_LDO1
VLDO1
PVIN_LDO2
19 VLDO2
Thermal Pad
(GND)
nRSTOUT
GPO2
18
17
GPO1
图5-1. RHB Package, 32-pin QFN (Top View)
表5-1. Pin Functions
CONNECTION if not used
(output rails must be
permanently disabled)
PIN NAME
FB_B1
PIN NO.
TYPE
DESCRIPTION
Feedback Input for Buck1. Connect to Buck1
1
I
output filter. Nominal output voltage is configured in Connect to GND
EEPROM.
Switch Pin for Buck1. Connect one side of the
Leave floating
LX_B1_1
LX_B1_2
2
3
PWR
PWR
Buck1-inductor to this pin.
2nd Switch Pin for Buck1. Connect one side of the
Leave floating
Buck1-inductor to this pin. Connect to LX_B1_1.
Power Input for BUCK1. Bypass this pin to ground
with a 4.7 μF or greater ceramic capacitor. Voltage
on PVIN_B1_1 pin must not exceed voltage on
VSYS pin.
PVIN_B1_1
PVIN_B1_2
4
5
PWR
PWR
Connect to VSYS
2nd Power Input for BUCK1. This pin shares the
bypass capacitor from pin 4. Voltage on
PVIN_B1_2 pin must not exceed voltage on VSYS
Connect to VSYS
pin.
Power Input for LDO1. Voltage on PVIN_LDO1 pin
Connect to VSYS
PVIN_LDO1
VLDO1
6
7
PWR
PWR
must not exceed voltage on VSYS pin.
Output Voltage of LDO1. Nominal output voltage is
configured in EEPROM. Bypass this pin to ground Leave floating
with a 2.2 µF or greater ceramic capacitor.
General Purpose Open-Drain Output. Configurable
GPO1
SDA
8
9
O
in the power-up and power-down-sequence to
enable an external rail.
Leave floating
Connect to VIO
Data Pin for the I2C Serial Port. The I2C logic
levels depend on the external pull-up voltage.
I/O
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English Data Sheet: SLVSGA1
TPS65219-Q1
ZHCSNP4A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
表5-1. Pin Functions (continued)
CONNECTION if not used
PIN NAME
SCL
PIN NO.
TYPE
DESCRIPTION
(output rails must be
permanently disabled)
Clock Pin for the I2C Serial Port. The I2C logic
levels depend on the external pull-up voltage.
10
11
I
Connect to VIO
Interrupt Request Output. Open-drain driver is
pulled low for fault conditions. Released if bit is
cleared
nINT
O
Leave floating
n/a (connect to GND)
n/a
Multi-Function-Pin:
Configured as VSEL_SD: SD-card-IO-voltage
select. Connected to SoC. Trigger a voltage
change between 1.8 V and register-based VOUT
on LDO1 or LDO2. Polarity is configurable.
Configured as VSEL_DDR: DDR-voltage selection.
Hard-wired pull-up (1.35 V), pull-down (register
based VOUT) or floating (1.2 V)
VSEL_SD/
VSEL_DDR
12
13
I
Input supply pin for reference system. Bypass this
pin to ground with a 2.2 µF or greater ceramic
capacitor (can be shared with PVIN-capacitors).
VSYS
PWR
Internal Reference Voltage: For Internal Use Only.
Bypass this pin to ground with a 2.2 µF or greater
ceramic capacitor.
VDD1P8
AGND
14
15
PWR
GND
n/a
n/a
Ground pin for Analog GND
GPO-configuration: General Purpose Open-Drain
Output. Configurable in the power-up and power-
down-sequence to enable an external rail.
GPIO-configuration:
GPIO
16
I/O
Leave floating
Synchronizing I/O. Used to synchronize two or
more TPS65219-Q1. The pin is level-sensitive.
General Purpose Open-Drain Output. Configurable
in the power-up and power-down-sequence to
enable an external rail.
GPO2
nRSTOUT
VLDO2
17
18
19
O
O
Leave floating
Leave floating
Reset-output to SoC. Controlled by sequencer.
High in ACTIVE and STBY state.
Output Voltage of LDO2. Nominal output voltage is
configured in EEPROM. Bypass this pin to ground Leave floating
with a 2.2 µF or greater ceramic capacitor.
PWR
Power Input for LDO2. Bypass this pin to ground
with a 2.2 μF or greater ceramic capacitor. Voltage
on PVIN_LDO2 pin must not exceed voltage on
VSYS pin.
PVIN_LDO2 20
PWR
PWR
PWR
Connect to VSYS
Output Voltage of LDO3. Nominal output voltage is
configured in EEPROM. Bypass this pin to ground Leave floating
with a 2.2 µF or greater ceramic capacitor.
VLDO3
21
Power Input for LDO3 and LDO4. Bypass this pin
to ground with a 4.7 μF or greater ceramic
capacitor. Voltage on PVIN_LDO34 pin must not
PVIN_LDO34 22
Connect to VSYS
exceed voltage on VSYS pin.
Output Voltage of LDO4. Nominal output voltage is
VLDO4
FB_B3
23
24
PWR
I
configured in EEPROM.Bypass this pin to ground
with a 2.2 µF or greater ceramic capacitor.
Leave floating
Feedback Input for Buck3. Connect to Buck3
output filter. Nominal output voltage is configured in Connect to GND
EEPROM.
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Product Folder Links: TPS65219-Q1
English Data Sheet: SLVSGA1
TPS65219-Q1
ZHCSNP4A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
PIN NAME
表5-1. Pin Functions (continued)
DESCRIPTION
CONNECTION if not used
(output rails must be
permanently disabled)
PIN NO.
TYPE
ON-request input.
Configured as EN: Device enable pin, high level is
ON-request, low-level is OFF-request.
Configured as PB: Push-button monitor input. 600
ms low-level is an ON-request, 8 s low-level is an
OFF-request.
Configured as VSENSE: Power-fail comparator
input. Set sense voltage using a resistor divider
connected from the input to the pre-regulator to this
pin to ground. Detects rising/falling voltage on pre-
regulator and triggers ON- / OFF-request.
The pin is edge-sensitive with a wait-time in PB-
configuration and deglitch time for EN- and
VSENSE-configuration.
EN/PB/
VSENSE
n/a (configure as EN and connect
to VSYS)
25
I
Power Input for BUCK3. Bypass this pin to ground
with a 4.7 μF or greater ceramic capacitor. Voltage
on PVIN_B3 pin must not exceed voltage on VSYS
pin.
PVIN_B3
LX_B3
26
27
PWR
PWR
Connect to VSYS
Leave floating
Switch Pin for Buck3. Connect one side of the
Buck3-inductor to this pin.
Multi-Function-Pin:
Configured as MODE: Connected to SoC or hard-
wired pull-up/-down. Forces the Buck-converters
into PWM or permits auto-entry in PFM-mode.
Configured as RESET: Connected to SoC. Forces
a WARM or COLD reset (configurable), WARM
reset resetting output voltages to defaults, COLD
reset sequencing down all enabled rails and power
up again.
n/a (tie high or low, dependent on
configuration, see 'PWM/PFM
and Reset (MODE/RESET)'
MODE/RESET 28
I
Polarity is configurable.
The pin is level-sensitive for MODE-configuration,
edge-sensitive for RESET-configuration.
Switch Pin for Buck2. Connect one side of the
Buck2-inductor to this pin.
LX_B2
29
30
PWR
PWR
Leave floating
Power Input for BUCK2. Bypass this pin to ground
with a 4.7 μF or greater ceramic capacitor. Voltage
on PVIN_B2 pin must not exceed voltage on VSYS
pin.
PVIN_B2
Connect to VSYS
Multi-Function-Pin:
Configured as MODE:
Connected to SoC or hard-wired pull-up/-down.
Forces the Buck-converters into PWM or permits
auto-entry in PFM-mode.
n/a (tie high or low, dependent on
configuration, see 'PWM/PFM
MODE/STBY 31
I
I
Configured as STBY: Low-power-mode command, and Low Power Modes (MODE/
STBY)'
disables selected rails.
Both functions, MODE and STBY, can be
combined.
The pin is level-sensitive.
Feedback Input for Buck2. Connect to Buck2
output filter. Nominal output voltage is configured in Connect to GND
EEPROM.
FB_B2
32
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Product Folder Links: TPS65219-Q1
English Data Sheet: SLVSGA1
TPS65219-Q1
ZHCSNP4A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
表5-1. Pin Functions (continued)
CONNECTION if not used
PIN NAME
PGND
PIN NO.
TYPE
DESCRIPTION
(output rails must be
permanently disabled)
Power-Ground. The exposed pad must be
connected to a continuous ground plane of the
printed circuit board by multiple interconnect vias
directly under the TPS65219-Q1 to maximize
electrical and thermal conduction.
PowerPad
GND
n/a
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGA1
6
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ZHCSNP4A –DECEMBER 2022 –REVISED MAY 2023
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
POS
MIN
MAX
UNIT
1.1.1
1.1.2
Input voltage
Input voltage
VSYS
6
V
–0.3
PVIN_B1, PVIN_B2, PVIN_B3, PVIN_LDO1,
PVIN_LDO2, PVIN_LDO34
6
V
–0.3
Input voltage vs. VSYS for
Bucks
PVIN_B1, PVIN_B2, PVIN_B3 maximum voltage
exceeding VSYS
1.1.3
200
mV
Input voltage vs. VSYS for
LDOs
PVIN_LDO1, PVIN_LDO2, PVIN_LDO34 maximum
voltage exceeding VSYS
1.1.4
1.1.5
1.1.6
20
6
mV
V
Input voltage
Input voltage
FB_B1, FB_B2, FB_B3
–0.3
–0.3
EN/PB/VSENSE, MODE/STBY, MODE/RESET,
VSEL_SD/VSEL_DDR
6
V
PVIN_Bx +
0.3 V, up to
6 V
1.2.1
Output voltage
LX_B1, LX_B2, LX_B3
V
–0.3
1.2.2
1.2.3
Output voltage
Output voltage
LX_B1, LX_B2, LX_B3 spikes for maximum 10ns
GPO1, GPO2, GPIO
10
6
V
V
–2
–0.3
PVIN_LDOx
+ 0.3 V, up
to 6 V
1.2.4
Output voltage
VLDO1, VLDO2, VLDO4, VLDO4
V
–0.3
1.2.5
1.2.6
1.2.7
1.4.1
1.4.2
Output voltage
Output voltage
Output voltage
VDD1P8
2
6
V
V
–0.3
–0.3
–0.3
-40
SDA, SCL
nINT, nRSTOUT
6
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
-40
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
POS
2.1
2.2
VALUE
UNIT
Electrostatic discharge, Human Body
Model
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
V(ESD)
V(ESD)
±2000
V
Electrostatic discharge, Charged Device
Model
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
POS
MIN
NOM
MAX
UNIT
3.1.1
VVSYS
Input voltage
2.5 (1)
5.5
V
VPVIN_B1, VPVIN_B2
VPVIN_B3
VLX_B1, VLX_B2
VLX_B3
,
3.1.2
3.1.3
BUCKx Pins
2.5
5.5 (2)
V
,
Voltage by which VPVIN_Bx may exceed VVSYS
0
mV
ΔVVSYS_PVIN_Bx
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Product Folder Links: TPS65219-Q1
English Data Sheet: SLVSGA1
TPS65219-Q1
ZHCSNP4A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
POS
MIN
NOM
MAX
UNIT
Voltage by which VPVIN_LDO1 or VPVIN_LDO2 may
exceed VVSYS
3.1.4
3.1.5
0
mV
ΔVVSYS_PVIN_LDO1,LDO2
Voltage by which VVSYS must exceed LDO
output voltage (VLDO3, VLDO4); VVSYS = 2.5V
to 3.45V; LDO mode
150
n/a
mV
mV
ΔVVSYS_VLDO34
Voltage by which VVSYS must exceed LDO
output voltage (VLDO3, VLDO4); VVSYS = 3.45V
to 5.5V in LDO-mode or VVSYS = 2.5V to 5.5V in
LSW-mode
3.1.6
ΔVVSYS_VLDO34
CPVIN_B1, CPVIN_B2
CPVIN_B3
,
3.1.7
3.1.8
3.1.9a
BUCKx Input Capacitance
BUCKx Output Inductance
3.9
330
10
4.7
µF
nH
µF
LB1, LB2, LB3
470
611
75
COUT_B1, COUT_B2
COUT_B3
,
,
,
,
BUCKx Output Capacitance, forced PWM or
auto-PFM, low bandwidth case
COUT_B1, COUT_B2
COUT_B3
BUCKx Output Capacitance, fixed frequency,
low BW case
3.1.9b
3.1.10a
3.1.10b
3.1.11
12
30
48
0
36
220
µF
µF
µF
V
COUT_B1, COUT_B2
COUT_B3
BUCKx Output Capacitance, forced PWM or
auto-PFM, high bandwidth case
COUT_B1, COUT_B2
COUT_B3
BUCKx Output Capacitance, fixed frequency,
high BW case
144
VFB_B1, VFB_B2
,
BUCKx FB Pins
5.5 (2)
VFB_B3
3.1.12
3.1.13
VPVIN_LDO1, VPVIN_LDO2
VPVIN_LDO1, VPVIN_LDO2
LDO Input Voltage
1.5
1.5
5.5 (2)
3.6
V
V
LDO Input Voltage in bypass mode
Allowable delta between VPVIN_LDOx and
configured VVLDOx in bypass mode
3.1.14
VPVIN_LDO1, VPVIN_LDO2
-200
200
3.4
mV
3.1.15
3.1.16
3.1.17
3.1.18
3.1.19
3.1.20
3.1.21
3.1.22
3.1.23
3.1.24
3.1.25
3.1.26
3.1.27
VVLDO1, VVLDO2
CPVIN_LDO1, CPVIN_LDO2
CVLDO1, CVLDO2
VPVIN_LDO3, VPVIN_LDO4
VVLDO3, VVLDO4
CPVIN_LDO34
LDO Output Voltage Range
LDO Input Capacitance
LDO Output Capacitance
LDO Input Voltage
0.6
1.6
1.6
2.2
1.2
2.2
1.6
0
V
µF
µF
V
2.2
2.2
20
5.5 (2)
3.3
LDO Output Voltage Range
LDO Input Capacitance
LDO Output Capacitance
VDD1P8 pin
V
4.7
2.2
µF
µF
V
CVLDO3, CVLDO4
VVDD1P8
30 (3)
1.8
4
CVDD1P8
Internal Regulator Decoupling Capacitance
VSYS Input Decoupling Capacitance
Digital Outputs
1
2.2
2.2
µF
µF
V
CVSYS
1
VnINT, VnRSTOUT
VGPO1, VGPO2, VGPIO
VSCL, VSDA
0
3.4
5.5 (2)
3.4
Digital Outputs
0
V
I2C Interface
0
V
VEN/PB/VSENSE, VMODE/STBY
,
3.1.28
3.2.1
VMODE/RESET
,
Digital Inputs
0
5.5 (2)
V
VVSEL_SD/VSEL/DDR
Input voltage rising ramp Time, Input voltage
tVSYS_RAMP_RISE
controlled by a pre-regulator. VVSYS
VPVIN_Bx = VPVIN_LDOx = 0V to 5V
=
0.1
600000
ms
Input voltage falling Ramp Time, VVSYS
VPVIN_Bx = VPVIN_LDOx = 5V to 2.5V
=
3.2.2
3.3.1
tVSYS_RAMP_FALL
TA_
0.4
600000
125
ms
°C
Operating free-air temperature
–40
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English Data Sheet: SLVSGA1
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6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
POS
MIN
NOM
MAX
UNIT
3.3.2
TJ_
Operating junction temperature
150
°C
–40
(1) For EEPROM programming, VSYS(min)=3.3V
(2) Must not exceed VSYS
(3) In slow-ramp-mode. Fast-ramp supports 15µF maximum
6.4 Thermal Information
TPS65219-Q1
RHB (QFN)
32 PINS
31.3
THERMAL METRIC(1)
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
20.4
10.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJT
10.8
ΨJB
RΘJC(bot)
2.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 System Control Thresholds
Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGND ground of the device.
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Electrical Characteristics
4.1.1
4.1.2
4.1.3
VSYS
Operating Input Voltage
2.5
2.2
5.5
2.5
V
V
V
VSYSPOR_Rising
VSYS POR rising threshold
Measured on VSYS pin, untrimmed
Measured on VSYS pin, trimmed
VSYSUVLO_Falling VSYS UVLO falling threshold
2.175
2.25
VSYSPOR_Rising_untrimmed
VSYSUVLO_Falling_trimmed
-
4.1.4
4.1.5
4.1.6
VSYSPOR_Hyst
VVSYS_OVP_Rise
VVSYS_OVP_Fall
VSYS UVLO/POR hysteresis
130
mV
V
VSYS OVP rising threshold,
trimmed
Measured on VSYS pin, trimmed
Measured on VSYS pin, trimmed
5.9
5.7
6.1
VSYS OVP falling threshold,
trimmed
5.95
V
VSYSOVP_Rising_trimmed
VSYSOVP_falling_trimmed
-
4.1.7
4.1.8
VVSYS_OVP_Hyst
VVDD1P8
VSYS OVP hysteresis
VDD1P8 voltage
100
1.7
140
1.8
180
1.9
mV
V
Combined Current from VSYS and
Current Consumption in INITIALIZE PVIN_x pins. VSYS = PVIN_Bx =
4.2.1a IINITIALIZE
state,
at 25°C
PVIN_LDOx = 5V. All Monitors are
off.
TJ = 25°C
15
15
22
37
µA
µA
Combined Current from VSYS and
PVIN_x pins. VSYS = PVIN_Bx =
PVIN_LDOx = 5V. All Monitors are
off.
Current Consumption in INITIALIZE
state,
-40°C to 150°C
4.2.1b IINITIALIZE
TJ = -40°C to 150°C
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6.5 System Control Thresholds (continued)
Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGND ground of the device.
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Combined Current from VSYS and
PVIN_x pins. VSYS = PVIN_Bx =
PVIN_LDOx = 5V. All Outputs are
on, all LDOs in LDO-mode, Bucks in
PFM mode. No Load.
ACTIVE State Current
Consumption, all rails on, at 25°C
4.2.2a IACTIVE
250
290
500
µA
µA
TJ = 25°C
Combined Current from VSYS and
PVIN_x pins. VSYS = PVIN_Bx =
PVIN_LDOx = 5V. All Outputs are
on, all LDOs in LDO-mode, Bucks in
PFM mode. No Load.
ACTIVE State Current
Consumption, all rails on,
-40°C to 150°C
4.2.2b IACTIVE
250
TJ = -40°C to 150°C
Combined Current from VSYS and
PVIN_x pins. VSYS = PVIN_Bx =
PVIN_LDOx = 5V. Only LDO1 on in
LDO-mode. No Load.
STBY State Current Consumption,
only LDO1 on, at 25°C
4.2.3a ISTBY
105
105
125
150
µA
µA
TJ = 25°C
Combined Current from VSYS and
PVIN_x pins. VSYS = PVIN_Bx =
PVIN_LDOx = 5V. Only LDO1 on in
LDO-mode. No Load.
STBY State Current Consumption,
only LDO1 on, -40°C to 150°C
4.2.3b ISTBY
TJ = -40°C to 150°C
Combined Current from VSYS and
PVIN_x pins. VSYS = PVIN_Bx =
PVIN_LDOx = 5V. All Outputs are
STBY State Current Consumption, on, all LDOs in LDO-mode, Bucks in
4.2.4a ISTBY
250
290
500
3.2
µA
µA
ms
all rails on, VMON on at 25°C
PFM mode. No Load. Output-
voltage Monitors are on, VSYS-
monitor (UV/OVP) are on.
TJ = 25°C
Combined Current from VSYS and
PVIN_x pins. VSYS = PVIN_Bx =
PVIN_LDOx = 5V. All Outputs are
on, all LDOs in LDO-mode,, Bucks
in PFM mode. No Load. Output-
voltage Monitors are on, VSYS-
monitor (UV/OVP) are on.
STBY State Current Consumption,
all rails on, VMON on,
-40°C to 150°C
4.2.4b ISTBY
250
TJ = -40°C to 150°C
Timing Requirements
Time from VSYS passing
VSYS_POR until entering
INITIALIZE state, including
EEPROM-read, ready for ON-
request
Time from VSYS passing
VSYS_POR until entering
INITIALIZE state. On request
execution gated by HOT and RV
4.3.1
tOFF_TO_INIT
end of
tRAMP +
sample-
and
UV-detection in case a rail does not
reach UV-threshold during ramp-up
4.3.2a tTIMEOUT_UV
deglitch
time
end of
slot-
extensi
on time
(3ms,
Timeout in case a rail does not
reach UV-threshold during ramp-up,
applicable in Multi-PMIC-
configuration only
4.3.2b tTIMEOUT_UV_SLOT
4ms or
13ms)
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6.5 System Control Thresholds (continued)
Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGND ground of the device.
POS
4.3.3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Timeout in case a rail cannot be
tTIMEOUT_Discharge discharged when transitioning from
STBY to ACTIVE state
72
80
88 ms
6.6 BUCK1 Converter
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Electrical Characteristics
Buck supply voltage, maximum
VSYS
5.1.1a VIN_BUCK1
Input voltage(1)
2.5
5.5
3.4
V
V
Output voltage configurable in
25mV-steps for 0.6V ≤VOUT ≤
1.4V, in 100mV steps for 1.4V <
Buck Output Voltage configurable
Range
5.1.1b VOUT_BUCK1
0.6
V
OUT ≤3.4V
Quiescent Current at 25°C, PFM,
low BW case
PFM, BUCK1 enabled, no load,
VIN = 5.0V, VOUT = 1.2V, TJ=25°C
5.1.2a IQ_BUCK1
10
15
13
44
μA
μA
PFM, BUCK1 enabled, no load,
VIN = 5.0V, VOUT = 1.2V, TJ=-40°C
to 125°C
Quiescent Current -40°C to 125°C,
PFM, low BW case
5.1.2b IQ_BUCK1
Quiescent Current -40°C to 150°C, PFM, BUCK1 enabled, no load,
5.1.2c IQ_BUCK1
PFM, low BW case
VIN = 5.0V, VOUT = 1.2V, TJ=-40°C
to 150°C
20
63
μA
Input to Output Voltage
Headroom(2)
Corner cases at maximum load IOUT
= 2.5A
5.1.3a VHEADROOM_PWM
5.1.3b VHEADROOM_PWM
5.1.3c VHEADROOM_FF
5.1.3d VHEADROOM_FF
500
700
mV
mV
mV
mV
Input to Output Voltage
Headroom at IOUT = IOUT_MAX
Corner cases at IOUT = IOUT_MAX
(2)
(2)
Input to Output Voltage
Headroom(2)
Corner cases at maximum load IOUT
= 0.7A
500
Input to Output Voltage
Headroom at IOUT = IOUT_MAX
Corner cases at IOUT = IOUT_MAX
1000
5.1.4
5.1.5
VOUT_STEP_LOW
Output voltage Steps
25
mV
mV
0.6V ≤VOUT ≤1.4V
1.5V ≤VOUT ≤3.4V
VOUT_STEP_HIGH Output voltage Steps
100
IOUT = IOUT_MAX
,
DC Output Voltage Accuracy in
forced PWM mode, low and high
BW case
VOUT_ACC_DC_PW
V
OUT ≥0.7V to 3.4V,
5.1.6a
5.1.6b
1.5%
10
–1.5%
–10
VIN - VOUT > 700 mV
forced PWM, low BW case
M
IOUT = IOUT_MAX
VOUT = 0.6V to 0.7V,
VIN - VOUT > 700 mV
forced PWM, low BW case
,
DC Output Voltage Accuracy in
forced PWM mode, low and high
BW case
VOUT_ACC_DC_PW
mV
M
IOUT = 1mA,
DC Output Voltage Accuracy in
5.1.6c VOUT_ACC_DC_PFM auto-PFM mode, low and high BW
case
VOUT = 0.6V to 3.4V,
VIN - VOUT > 500 mV
auto-PFM, low BW case
3.5%
1.5%
10
–3.0%
–1.5%
–10
IOUT = IOUT_MAX
,
DC Output Voltage Accuracy in
5.1.6d VOUT_ACC_DC_FF Fixed Frequency mode, low and
high BW case
V
OUT ≥0.7V to 3.4V,
VIN - VOUT > 1000 mV
fixed frequency, low BW case
IOUT = IOUT_MAX
VOUT = 0.6V to 0.7V,
VIN - VOUT > 1000 mV
fixed frequency, low BW case
,
DC Output Voltage Accuracy in
5.1.6e VOUT_ACC_DC_FF Fixed Frequency mode, low and
high BW case
mV
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MAX UNIT
6.6 BUCK1 Converter (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
Converter enabled
VIN = 5.0V, VOUT = 1.2V,
IOUT = 0 to IOUT_MAX
forced PWM, low BW case, COUT
40μF
MIN
TYP
5.1.7
RFB_INPUT
Feedback input impedance
2.3
3.75
5.0
MΩ
,
DC Load Regulation, forced PWM,
low BW case
5.2.1a VLOAD_REG_PWM
0.1
0.1
0.16 %/A
0.16 %/A
=
VIN = 5.0V, VOUT = 1.2V,
IOUT = 0 to IOUT_MAX
,
DC Load Regulation, fixed
frequency, low BW case
5.2.1b VLOAD_REG_FF
fixed frequency, low BW case, COUT
= 40μF
VIN = 3.3V to 5.5V,
VOUT = 1.2V,
IOUT = 1mA and IOUT_MAX
DC Line Regulation, forced PWM,
low BW case
5.2.2a VLINE_REG
0.1
0.1
0.16 %/V
0.16 %/V
forced PWM, low BW case, COUT
=
40μF
VIN = 3.3V to 5.5V,
VOUT = 1.2V,
IOUT = 1mA and IOUT_MAX
DC Line Regulation, fixed
frequency, low BW case
5.2.2b VLINE_REG
fixed frequency, low BW case, COUT
= 12μF
VIN = 5.0V, VOUT = 0.75V,
IOUT = 100mA to 1100mA to 100mA,
tR = tF = 500ns,
Load Transient, VOUT=0.75V, auto-
PFM, high BW case
5.2.3a VLOAD_TRANSIENT
27.5
27.5
mV
mV
–27.5
–27.5
auto-PFM, high BW case, COUT
=
80μF
VIN = 5.0V, VOUT = 0.75V,
IOUT = 100mA to 1100mA to 100mA,
tR = tF = 500ns,
Load Transient, VOUT=0.75V, forced
PWM, high BW case
5.2.3b VLOAD_TRANSIENT
forced PWM, high BW case, COUT
=
80 μF
VIN = 5.0V, VOUT = 0.75V,
IOUT = IOUT = 100mA to 1100mA to
100mA,
Load Transient, VOUT=0.75V, fixed
frequency, high BW case
5.2.3c VLOAD_TRANSIENT
27.5
mV
–27.5
tR = tF = 500ns,
fixed frequency, high BW case,
COUT = 60 μF
VIN = 5.0V, VOUT = 1.8V,
IOUT = 1mA to 1A to 1mA,
tR = tF = 1μs,
Load Transient, VOUT=1.8V, auto-
PFM, low BW case
5.2.4a VLOAD_TRANSIENT
-90
-60
90
60
mV
mV
auto-PFM, COUT = 40μF
VIN = 5.0V, VOUT = 1.8V,
IOUT = 1mA to 1A to 1mA,
tR = tF = 1μs,
Load Transient, VOUT=1.8V, forced
PWM, low BW case
5.2.4b VLOAD_TRANSIENT
forced PWM, COUT = 40μF
VIN = 5.0V, VOUT = 1.8V,
IOUT = 1mA to 1A to 1mA,
tR = tF = 1μs,
fixed frequency, low BW case, COUT
= 12μF
Load Transient, VOUT=1.8V, fixed
frequency, low BW case
5.2.4c VLOAD_TRANSIENT
-180
180
50
mV
mV
VIN = 3.3V to 5.5V in 50μs,
VOUT = 1.2V, IOUT = 1mA and
IOUT_MAX,
forced PWM, low BW case, COUT
Line Transient, VOUT=1.2V, forced
PWM, low BW case
5.2.5a VLINE_TRANSIENT
–50
=
40μF
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6.6 BUCK1 Converter (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN = 3.3V to 5.5V in 50μs,
VOUT = 1.2V, IOUT = 1mA and
Line Transient, VOUT=1.2V, fixed
frequency, low BW case
5.2.5b VLINE_TRANSIENT
IOUT_MAX
,
50
mV
–50
fixed frequency, low BW case, COUT
= 12μF
VIN = 5.0V, VOUT = 2.5V,
forced PWM, low BW case, COUT
40uF, X5R, ESR = 10mOhm,
L = 470nH, DCR = 50mΩ
IOUT = 1A
=
5.2.6a VRIPPLE_PP_PWM Forced PWM Mode, low BW case
10
20
20 mVPP
VIN = 5.0V, VOUT = 2.5V,
auto PFM, low BW case, COUT
40uF, X5R, ESR = 10mOhm,
L = 470nH, DCR = 50mΩ
IOUT = 20mA
=
5.2.6b VRIPPLE_PP_PFM
Auto PFM Mode, low BW case
40 mVPP
VIN = 5.0V, VOUT = 2.5V,
fixed frequency, low BW case, COUT
= 12uF, X5R, ESR = 10mOhm,
L = 470nH, DCR = 50mΩ,
IOUT = 1A,
Fixed Frequency Mode, low BW
case, spread spectrum disabled
5.2.6c VRIPPLE_PP_FF
10
20
20 mVPP
Spread-Spectrum disabled
VIN = 5.0V, VOUT = 2.5V,
fixed frequency, low BW case, COUT
= 12uF, X5R, ESR = 10mOhm,
L = 470nH, DCR = 50mΩ,
IOUT = 1A,
Fixed Frequency Mode, low BW
case
5.2.6d VRIPPLE_PP_FF_SS
40 mVPP
Spread-Spectrum enabled
5.3.1
5.3.2
5.3.3
IOUT_MAX
Maximum Operating Current
Peak Current Limit
3.5
6.9
A
A
A
ICURRENT_LIMIT
IREV_CUR_LIMIT
VIN = 2.5V to 5.5V
VIN = 2.5V to 5.5V
4.6
5.7
Reverse Peak Current Limit
–2.0
–1.5
–1.0
High Side MOSFET On Resistance,
5V-supply
5.3.4a RDSON_HS
5.3.4b RDSON_HS
5.3.5a RDSON_LS
5.3.5b RDSON_LS
Measured Pin to Pin, VIN = 5V
Measured Pin to Pin, VIN = 3.3V
Measured Pin to Pin, VIN = 5V
Measured Pin to Pin, VIN = 3.3V
70
80
40
50
mΩ
mΩ
mΩ
mΩ
High Side MOSFET On Resistance,
3.3V-supply
Low Side MOSFET On Resistance,
5V-supply
Low Side MOSFET On Resistance,
3.3V-supply
Active only when converter is
disabled
5.3.6
5.4.1
RDISCHARGE
LSW
Output Discharge Resistance
Output Inductance
60
330
10
125
470
200
611
75
Ω
nH
DCR = 50mΩ max
ESR = 10mΩ max
Output Capacitance in auto-PFM or
forced PWM for low BW case
5.4.2a COUT
μF
μF
μF
μF
Output Capacitance in fixed
frequency for low BW case
5.4.2b COUT_FF
5.4.3a COUT_HIGH_BW
12
30
48
36
220
144
ESR = 10mΩ max
ESR = 10mΩ max
ESR = 10mΩ max
Output Capacitance in auto-PFM or
forced PWM for high BW case
Output Capacitance in fixed
frequency for high BW case
5.4.3b COUT_HIGH_BW_FF
Timing Requirements
Ramp Time in forced PWM, low BW Time from enable to 98% of target
case value, assuming no residual voltage
5.5.1
tRAMP
0.3
2.9
1.65
3.5
ms
DVFS_RISE_
QFF
DVFS timing requirements in forced Step-duration during DVFS voltage
PWM, rising slope adjustments from 0.6V to 1.4V
5.5.2a
3.2
mV/μs
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MAX UNIT
6.6 BUCK1 Converter (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
DVFS_RISE_
FF
DVFS timing requirements in fixed- Step-duration during DVFS voltage
5.5.2b
1.8
2.1
2.5
mV/μs
mV/μs
frequency mode, rising slope
adjustments from 0.6V to 1.4V
DVFS timing requirements in forced
PWM or fixed-frequency mode,
falling slope
Step-duration during DVFS voltage
adjustments from 1.4V to 0.6V
5.5.2c DVFS_FALL
Switching Characteristics
5.6.1a fSW
0.45
0.53
0.61
Forced PWM, VIN = 3.3V to 5V,
VOUT = 0.8V to 1.8V,
IOUT = 1A to 3A
Switching Frequency, forced PWM,
high or low BW case
2.3
2.3
MHz
Switching Frequency, fixed
Fixed - Frequency, VIN = 3.3V to 5V,
5.6.1b fSW
frequency, high or low BW case, no VOUT = 0.8V to 1.8V,
2.18
1.95
2.42 MHz
2.65 MHz
Spread Spectrum
IOUT = 1A to 3A
Fixed - Frequency, VIN = 3.3V to 5V,
VOUT = 0.8V to 1.8V,
IOUT = 1A to 3A
Switching Frequency, fixed
frequency, high or low BW case,
with Spread Spectrum enabled
5.6.2
fSW_SS_EN
Spread spectrum enabled
(1) PVIN_Bx must not exceed VSYS
(2) Refers to DC-regulation only. Transient response may require more headroom. With low headroom, the frequency variation increases
for quasi-fixed frequency.
6.7 BUCK2, BUCK3 Converter
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Electrical Characteristics
Buck supply voltage, maximum
VSYS
6.1.1a VIN_BUCK23
Input Voltage(1)
2.5
5.5
3.4
V
V
Output voltage configurable in
25mV-steps for 0.6V ≤VOUT ≤
1.4V, in 100mV steps for 1.4V <
Buck Output Voltage configurable
Range
6.1.1b VOUT_BUCK23
0.6
V
OUT ≤3.4V
PFM, BUCKx enabled, no load,
VIN = 5.0V, VOUT = 1.2V, TJ=25°C
6.1.2a IQ_BUCK23
Quiescent Current at 25°C, PFM
10
15
13
43
μA
μA
PFM, BUCKx enabled, no load,
VIN = 5.0V, VOUT = 1.2V, TJ=-40°C
to 125°C
Quiescent Current -40°C to 125°C,
PFM, low BW case
6.1.2b IQ_BUCK23
Quiescent Current -40°C to 150°C, PFM, BUCKx enabled, no load,
6.1.2c IQ_BUCK23
PFM, low BW case
VIN = 5.0V, VOUT = 1.2V, TJ=-40°C
to 150°C
20
63
μA
Input to Output Voltage
Headroom(2)
Corner cases at maximum load IOUT
= 1.7A
6.1.3a VHEADROOM_PWM
6.1.3b VHEADROOM_PWM
6.1.3c VHEADROOM_FF
6.1.3d VHEADROOM_FF
500
700
mV
mV
mV
mV
Input to Output Voltage
Headroom at IOUT = IOUT_MAX
Corner cases at IOUT = IOUT_MAX
(2)
(2)
Input to Output Voltage
Headroom(2)
Corner cases at maximum load IOUT
= 0.5A
500
Input to Output Voltage
Headroom at IOUT = IOUT_MAX
Corner cases at IOUT = IOUT_MAX
1000
Output voltage Steps Buck2 and
Buck3
6.1.4
6.1.5
VOUT_STEP_LOW
25
mV
mV
0.6V ≤VOUT ≤1.4V
1.5V ≤VOUT ≤3.4V
VOUT_STEP_HIGH Output voltage Steps Buck2, Buck3
100
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6.7 BUCK2, BUCK3 Converter (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IOUT = IOUT_MAX
,
DC Output Voltage Accuracy in
forced PWM mode, low and high
BW case
VOUT_ACC_DC_PW
V
OUT ≥0.7V to 3.4V,
6.1.6a
1.5%
–1.5%
VIN - VOUT > 700 mV
forced PWM, low BW case
M
IOUT = IOUT_MAX
VOUT = 0.6V to 0.7V,
VIN - VOUT > 700 mV
forced PWM, low BW case
,
DC Output Voltage Accuracy in
forced PWM mode, low and high
BW case
VOUT_ACC_DC_PW
6.1.6b
10
3.5%
1.5%
mV
–10
–3.0%
–1.5%
M
IOUT = 1mA,
DC Output Voltage Accuracy in
VOUT = 0.6V to 3.4V,
VIN - VOUT > 500 mV
auto-PFM, low BW case
6.1.6c VOUT_ACC_DC_PFM auto-PFM mode, low and high BW
case
IOUT = IOUT_MAX
,
DC Output Voltage Accuracy in
6.1.6d VOUT_ACC_DC_FF Fixed Frequency mode, low and
high BW case
V
OUT ≥0.7V to 3.4V,
VIN - VOUT > 1000 mV
fixed frequency, low BW case
IOUT = IOUT_MAX
VOUT = 0.6V to 0.7V,
VIN - VOUT > 1000 mV
fixed frequency, low BW case
,
DC Output Voltage Accuracy in
6.1.6e VOUT_ACC_DC_FF Fixed Frequency mode, low and
high BW case
10
mV
–10
6.1.9
RFB_INPUT
Feedback input impedance
Converter enabled
2.3
3.75
0.1
5.0
MΩ
VIN = 5.0V, VOUT = 1.2V,
IOUT = 0 to IOUT_MAX
forced PWM, low BW case
DC Load Regulation, forced PWM,
low BW case
6.2.1a VLOAD_REG_PWM
,
0.16 %/A
0.16 %/A
VIN = 5.0V, VOUT = 1.2V,
IOUT = 0 to IOUT_MAX
fixed frequency, low BW case, COUT
= 40μF
,
DC Load Regulation, fixed
frequency, low BW case
5.2.1b VLOAD_REG_FF
0.1
0.1
VIN = 3.3V to 5.5V,
VOUT = 1.2V,
IOUT = 1mA and IOUT_MAX
forced PWM, low BW case, COUT
40μF
DC Line Regulation, forced PWM,
low BW case
6.2.2a VLINE_REG
0.16 %/V
0.16 %/V
=
VIN = 3.3V to 5.5V,
VOUT = 1.2V,
IOUT = 1mA and IOUT_MAX
DC Line Regulation, fixed
frequency, low BW case
6.2.2b VLINE_REG
0.1
fixed frequency, low BW case, COUT
= 12μF
VIN = 5.0V, VOUT = 0.75V,
IOUT = 100mA to 1100mA to 100mA,
tR = tF = 500ns,
Load Transient, VOUT=0.75V, auto-
PFM, high BW case
6.2.3a VLOAD_TRANSIENT
27.5
27.5
mV
mV
–27.5
–27.5
auto-PFM, high BW case, COUT
=
80μF
VIN = 5.0V, VOUT = 0.75V,
IOUT = 100mA to 1100mA to 100mA,
tR = tF = 500ns,
Load Transient, VOUT=0.75V, forced
PWM, high BW case
6.2.3b VLOAD_TRANSIENT
forced PWM, high BW case, COUT
=
80 μF
VIN = 5.0V, VOUT = 0.75V,
IOUT = IOUT = 100mA to 1100mA to
100mA,
Load Transient, VOUT=0.75V, fixed
frequency, high BW case
6.2.3c VLOAD_TRANSIENT
27.5
mV
–27.5
tR = tF = 500ns,
fixed frequency, high BW case,
COUT = 60 μF
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MAX UNIT
6.7 BUCK2, BUCK3 Converter (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
VIN = 5.0V, VOUT = 1.8V,
IOUT = 1mA to 1A to 1mA,
tR = tF = 1μs,
Load Transient, VOUT=1.8V, auto-
PFM, low BW case
6.2.4a VLOAD_TRANSIENT
-90
90
60
mV
mV
auto-PFM, COUT = 40μF
VIN = 5.0V, VOUT = 1.8V,
IOUT = 1mA to 1A to 1mA,
tR = tF = 1μs,
Load Transient, VOUT=1.8V, forced
PWM, low BW case
6.2.4b VLOAD_TRANSIENT
-60
forced PWM, COUT = 40μF
VIN = 5.0V, VOUT = 1.8V,
IOUT = 1mA to 1A to 1mA,
tR = tF = 1μs,
fixed frequency, low BW case, COUT
= 12μF
Load Transient, VOUT=1.8V, fixed
frequency, low BW case
6.2.4c VLOAD_TRANSIENT
-180
180
50
mV
mV
mV
VIN = 3.3V to 5.5V in 50μs,
VOUT = 1.2V, IOUT = 1mA and
IOUT_MAX,
forced PWM, low BW case, COUT
Line Transient, VOUT=1.2V, forced
PWM, low BW case
6.2.5a VLINE_TRANSIENT
–50
–50
=
40μF
VIN = 3.3V to 5.5V in 50μs,
VOUT = 1.2V, IOUT = 1mA and
Line Transient, VOUT=1.2V, fixed
frequency, low BW case
6.2.5b VLINE_TRANSIENT
IOUT_MAX
,
50
fixed frequency, low BW case, COUT
= 12μF
VIN = 5.0V, VOUT = 2.5V,
forced PWM, low BW case, COUT
40uF, X5R, ESR = 10mOhm,
L = 470nH, DCR = 50mΩ
IOUT = 1A
=
6.2.6a VRIPPLE_PP_PWM Forced PWM Mode, low BW case
10
20
20 mVPP
VIN = 5.0V, VOUT = 2.5V,
auto PFM, low BW case, COUT
40uF, X5R, ESR = 10mOhm,
L = 470nH, DCR = 50mΩ
IOUT = 20mA
=
6.2.6b VRIPPLE_PP_PFM
Auto PFM Mode, low BW case
40 mVPP
VIN = 5.0V, VOUT = 2.5V,
fixed frequency, low BW case, COUT
= 12uF, X5R, ESR = 10mOhm,
L = 470nH, DCR = 50mΩ,
IOUT = 1A,
Fixed Frequency Mode, low BW
case, spread spectrum disabled
6.2.6c VRIPPLE_PP_FF
10
20
20 mVPP
Spread-Spectrum disabled
VIN = 5.0V, VOUT = 2.5V,
fixed frequency, low BW case, COUT
= 12uF, X5R, ESR = 10mOhm,
L = 470nH, DCR = 50mΩ,
IOUT = 1A,
Fixed Frequency Mode, low BW
case, spread spectrum enabled
6.2.6d VRIPPLE_PP_FF_SS
40 mVPP
Spread-Spectrum enabled
6.3.1
6.3.2
6.3.3
IOUT_MAX
Maximum Operating Current
Peak Current Limit
2.0
4.7
A
A
A
ICURRENT_LIMIT
IREV_CUR_LIMIT
VIN = 2.5V to 5.5V
VIN = 2.5V to 5.5V
3.1
3.9
Reverse Peak Current Limit
–2.0
–1.5
–1.0
High Side MOSFET On Resistance,
5V-supply
6.3.4a RDSON_HS
6.3.4b RDSON_HS
6.3.5a RDSON_LS
Measured Pin to Pin, VIN = 5V
Measured Pin to Pin, VIN = 3.3V
Measured Pin to Pin, VIN = 5V
110
135
110
mΩ
mΩ
mΩ
High Side MOSFET On Resistance,
3.3V-supply
Low Side MOSFET On Resistance,
5V-supply
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6.7 BUCK2, BUCK3 Converter (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Low Side MOSFET On Resistance,
3.3V-supply
6.3.5b RDSON_LS
Measured Pin to Pin, VIN = 3.3V
130
mΩ
Active only when converter is
disabled
6.3.6
6.4.1
RDISCHARGE
LSW
Output Discharge Resistance
Output Inductance
60
330
10
125
470
200
611
75
Ω
nH
DCR = 50mΩ max
ESR = 10mΩ max
Output Capacitance in auto-PFM or
forced PWM for low BW case
6.4.2a COUT
μF
μF
μF
μF
Output Capacitance in fixed
frequency for low BW case
6.4.2b COUT_FF
6.4.3a COUT_HIGH_BW
12
30
48
36
220
144
ESR = 10mΩ max
ESR = 10mΩ max
ESR = 10mΩ max
Output Capacitance in auto-PFM or
forced PWM for high BW case
Output Capacitance in fixed
frequency for high BW case
6.4.3b COUT_HIGH_BW_FF
Timing Requirements
Ramp Time in quasi-fixed-frequency Time from enable to 98% of target
mode value, assuming no residual voltage
6.5.1
tRAMP
0.3
2.9
1.8
1.65
3.5
ms
DVFS_SLOPE_ DVFS timing requirements in forced Step-duration during DVFS voltage
QFF PWM, low BW case adjustments from 0.6V to 1.4V
6.5.2a
6.5.2b
3.2
2.1
mV/μs
mV/μs
DVFS_SLOPE_ DVFS timing requirements in fixed- Step-duration during DVFS voltage
2.5
FF
frequency mode, low BW case
adjustments from 0.6V to 1.4V
Switching Characteristics
DVFS timing requirements in forced
PWM or fixed-frequency mode,
falling slope
Step-duration during DVFS voltage
adjustments from 1.4V to 0.6V
6.5.2c DVFS_FALL
0.45
0.53
2.3
0.61
mV/μs
Forced PWM, VIN = 3.3V to 5V,
VOUT = 0.8V to 1.8V,
IOUT = 1A to 1.8A
Switching Frequency, forced PWM,
high or low BW case
6.6.1a fSW
6.6.1b fSW
MHz
Switching Frequency, fixed
frequency, high or low BW case, no VOUT = 0.8V to 1.8V,
Spread Spectrum
Fixed - Frequency, VIN = 3.3V to 5V,
2.18
1.95
2.3
2.42 MHz
2.65 MHz
IOUT = 1A to 1.8A
Fixed - Frequency, VIN = 3.3V to 5V,
VOUT = 0.8V to 1.8V,
IOUT = 1A to 1.8A
Switching Frequency, fixed
frequency, high or low BW case,
with Spread Spectrum enabled
6.6.2
fSW_SS_EN
Spread spectrum enabled
(1) PVIN_Bx must not exceed VSYS
(2) Refers to DC-regulation only. Transient response may require more headroom. With low headroom, the frequency variation increases
for quasi-fixed frequency.
6.8 General Purpose LDOs (LDO1, LDO2)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Electrical Characteristics
7.1.1
7.1.2
7.1.3
VIN_LDO
Input Voltage (LDO-mode)(1)
Input Voltage (bypass-mode)(1) (5)
Input Voltage (LSW-mode)(1)
LDO-mode, maximum VSYS
Bypass-mode, maximum VSYS
LSW-mode, maximum VSYS
1.5
1.5
1.5
5.5
3.4
5.5
V
V
V
VIN_LDO_BYP
VIN_LDO_LSW
LDO Output Voltage configurable
Range
LDO mode, with 50-mV steps, VIN
VOUT > 300 mV
-
7.1.4
VOUT_LDO
0.6
1.5
3.4
3.4
V
LDO Output Voltage configurable
Range in bypass-mode
Bypass mode, configurable VOUT
range with 50-mV steps
7.1.5
7.1.6
VOUT_LDO_BYP
VOUT_STEP
V
Output Voltage Steps
50
mV
LDO mode, 0.6V ≤VOUT ≤3.4V
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MAX UNIT
6.8 General Purpose LDOs (LDO1, LDO2) (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
–1.1%
–11
TYP
7.1.7
VDROPOUT
Dropout Voltage
150
300
mV
V
INmin ≤VIN ≤VIN, IOUT = 400 mA
Total DC Output Voltage accuracy,
LDO-mode, VIN - VOUT > 300 mV,
OUT ≥1V
VOUT_ACCURACY_ including Voltage References, DC
7.1.8
7.1.9
1.1%
load and line regulations, process
and temperature variations
V
H
Total DC Output Voltage accuracy,
including Voltage References, DC
load and line regulations, process
LDO-mode, VIN - VOUT > 300 mV,
VOUT < 1V
VOUT_ACCURACY_L
11
mV
and temperature variations
Bypass Resistance, high output
voltage
2.5 V ≤VIN ≤3.6 V, VIN ≤VSYS,
IOUT = 400 mA, bypass-mode
7.1.10 RBYPASS_H
7.1.11 RBYPASS_L
7.1.12 RLSW_H
7.1.13 RLSW_L
200
250
200
250
35
mΩ
mΩ
mΩ
mΩ
mV
Bypass Resistance, low output
voltage
1.5 V ≤VIN ≤2.5 V, VIN ≤VSYS,
IOUT = 400 mA, bypass-mode
LSW Resistance, high output
voltage
2.5 V ≤VIN ≤5.5 V, VIN ≤VSYS,
IOUT = 400 mA, LSW-mode
1.5 V ≤VIN ≤2.5 V, VIN ≤VSYS,
IOUT = 400 mA, LSW-mode
LSW Resistance, low output voltage
IOUT = 20% to 80% to 20% of
IOUT_MAX, tr = tf = 1 µs
7.2.1
7.2.2
VLOAD_TRANSIENT
Transient Load Regulation, ΔVOUT
–35
–25
VIN step = 600 mVPP, tR = tF = 10
µs, LDO not in dropout condition,
LDO-mode
VLINE_TRANSIENT Transient Line Regulation
25
mV
100 Hz < f ≤100 kHz, VIN = 3.3 V,
VOUT = 1.8 V, IOUT = 300 mA
7.2.3
7.2.4
NOISERMS
VRIPPLE
RMS Noise
600
980
μVRMS
Voltage Ripple
5
mVPP
V
PVIN_LDOxmin ≤VIN ≤
VPVIN_LDOxmax
,
7.3.1
IOUT_MAX
Output Current
400
mA
Applies to LDO-, bypass- and LSW-
mode
7.3.2
7.3.3
ICURRENT_LIMIT
IIN_RUSH_LDO
Short Circuit Current Limit
LDO Inrush Current
VIN = 3.6V, VOUT = 0V
600
1600
1500
mA
mA
LDO-mode, with maximum 20-µF
load connected to VLDOx, , IOUT = 0
mA or 400mA
Bypass-mode, with maximum 50-µF
load connected to VLDOx
7.3.4
7.3.5
IIN_RUSH_LDO_BYP LDO Inrush Current in bypass-mode
IIN_RUSH_LDO_LSW LDO Inrush Current in LSW-mode
1500
1500
mA
mA
LSW-mode, with maximum 50-µF
load connected to VLDOx
Active only when converter is
disabled. Applies to LDO-, bypass-
and LSW-mode
Pulldown Discharge Resistance at
7.3.6
RDISCHARGE
LDO Output
100
200
50
300
62
Ω
µA
µA
Quiescent Current in ACTIVE state
at 25°C,
LDO-mode
LDO-mode, IOUT = 0 mA,
TJ = 25°C
7.3.7a IQ_ACTIVE_LDO
Quiescent Current in ACTIVE state
-40°C to 125°C,
LDO-mode
LDO-mode, IOUT = 0 mA,
TJ = -40°C to 125°C
7.3.7b IQ_ACTIVE_LDO
50
65
Quiescent Current in ACTIVE state
-40°C to 150°C,
LDO-mode
LDO-mode, IOUT = 0 mA,
TJ = -40°C to 150°C
7.3.7b IQ_ACTIVE_LDO
50
43
66
48
µA
µA
Quiescent Current in ACTIVE state
at 25°C,
bypass-mode
IQ_ACTIVE_LDO_BY
bypass-mode, IOUT = 0 mA,
TJ = 25°C
7.3.8a
P
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6.8 General Purpose LDOs (LDO1, LDO2) (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Quiescent Current in ACTIVE state
-40°C to 125°C,
bypass-mode
IQ_ACTIVE_LDO_BY
bypass-mode, IOUT = 0 mA,
TJ = -40°C to 125°C
7.3.8b
43
50
50
µA
µA
P
Quiescent Current in ACTIVE state
IQ_ACTIVE_LDO_BY -40°C to 150°C,
bypass-mode, IOUT = 0 mA,
TJ = -40°C to 150°C
7.3.8b
43
bypass-mode
P
Quiescent Current in ACTIVE state
at 25°C,
LSW-mode
IQ_ACTIVE_LDO_LS
LSW-mode, IOUT = 0 mA,
TJ = 25°C
7.3.9a
7.3.9b
46
46
53
53
µA
µA
W
Quiescent Current in ACTIVE state
-40°C to 125°C,
LSW-mode
IQ_ACTIVE_LDO_LS
LSW-mode, IOUT = 0 mA,
TJ = -40°C to 125°C
W
Quiescent Current in ACTIVE state
IQ_ACTIVE_LDO_LS -40°C to 150°C,
LSW-mode, IOUT = 0 mA,
TJ = -40°C to 150°C
7.3.9b
7.4.1
46
54
µA
µF
LSW-mode
W
Connected from PVIN_LDOx to
GND
Applies to LDO-, bypass- and LSW-
mode
CIN
Input Filtering Capacitance (2)
1.6
1.6
2.2
2.2
Connected from VLDOx to GND,
LDO-mode
7.4.2
7.4.3
7.4.4
COUT
Output Filtering Capacitance(3)
4
20
50
µF
µF
µF
Total Capacitance at Output (Local
+ POL), LDO-mode(4)
COUT_TOTAL
COUT_TOTAL_BYP
COUT_TOTAL_LSW
CESR
1 MHz < f < 10 MHz
1 MHz < f < 10 MHz
Total Capacitance at Output (Local
+ POL), bypass-mode(4)
Total Capacitance at Output (Local
+ POL), LSW-mode(4)
7.4.5
7.4.6
1 MHz < f < 10 MHz
1 MHz < f < 10 MHz
50
20
µF
Filtering capacitor ESR max
10
mΩ
Timing Requirements
Measured from enable to 98% of
target value, LDO-mode or bypass-
mode, measured when enabled
individually, assuming no residual
voltage
Ramp Time LDO in LDO- and
bypass-mode
7.5.1
tRAMP
950
µs
Ramp up Slew Rate in LDO- and
bypass-mode
7.5.2
7.5.3
tRAMP_SLEW
VOUT from 0.3 V to 90% of VOUT
12 mV/µs
Measured from enable to target
value, LSW-mode, assuming no
residual voltage
tRAMP_LSW
Ramp Time LSW-mode
1250
µs
7.5.4
7.5.5
7.5.6
tRAMP_SLEW
Ramp up Slew Rate in LSW-mode VOUT from 0.3 V to 90% of VOUT
12 mV/µs
tTRANS_1P8_3P3
tTRANS_3P3_1P8
Transition Time 1.8V - 3.3V
Transition Time 3.3V - 1.8V
VIN = 4.0V, IOUT = 300mA
VIN = 4.0V, IOUT = 300mA
2
2
ms
ms
(1) PVIN_LDOx must not exceed VSYS
(2) Input capacitors must be placed as close as possible to the device pins.
(3) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above
therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the
capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of
regulators.
(4) Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable
(5) PVIN_LDOx voltage must be within (configured VOUT) and (configured VOUT + 200mV), maximum 3.6V.
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MAX UNIT
6.9 General Purpose LDOs (LDO3, LDO4)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
Electrical Characteristics
8.1.1
8.1.2
VIN
VIN
Input Voltage (LDO-mode) (1)
Input Voltage (LSW-mode) (1)
LDO-mode, maximum VVSYS
LSW-mode, maximum VVSYS
2.2
2.2
5.5
5.5
V
V
LDO Output Voltage configurable
Range
8.1.3
VOUT
VIN = 2.2V to 5.5V, maximum VVSYS
1.2
3.3
V
8.1.4
8.1.5
VOUT_STEP
VDROPOUT
Output voltage Steps
Dropout Voltage
50
mV
mV
1.2V ≤VOUT ≤3.3V
150
300
1%
V
INmin ≤VIN ≤VIN, IOUT = IOUTmax
Total DC accuracy including DC
load and line regulation for all valid LDO-mode, VIN - VOUT > 300 mV
output voltages
VOUT_DC_ACCURA
8.1.6
8.1.7
8.2.1
–1%
CY
VIN = 3.3V, IOUT = 100mA,
Bypass resistance in LSW-mode
RBYPASS
1
Ω
Loadswitch-mode enabled
VIN = 3.3V, VOUT = 1.80V, IOUT
20% of IOUT_MAX to 80% of IOUT_MAX
in 1µs, COUT = 2.2µF
=
VLOAD_TRANSIENT
25
mV
Transient load regulation, ΔVOUT
–25
–25
On mode, not under dropout
condition, VIN step = 600 mVPP, tr =
tf = 10µs
Transient line regulation,
ΔVOUT / VOUT
8.2.2
8.2.3
VLINE_TRANSIENT
25
mV
LDO-mode, f=100Hz to 100KHz,
VIN = 3.3V, VOUT = 1.8V, IOUT
300mA
NOISERMS
RMS Noise
=
=
=
=
=
15
µVRMS
LDO-mode, VIN = 3.3V, VOUT
1.8V, IOUT = 300mA
8.2.4
8.2.5
8.2.6
PSRR1KHZ
PSRR10KHZ
PSRR100KHZ
Power Supply Ripple Rejection
Power Supply Ripple Rejection
Power Supply Ripple Rejection
71
64
61
26
db
db
db
LDO-mode, VIN = 3.3V, VOUT
1.8V, IOUT = 300mA
LDO-mode, VIN = 3.3V, VOUT
1.8V, IOUT = 300mA
LDO-mode, VIN = 3.3V, VOUT
1.8V, IOUT = 300mA
8.2.7
8.3.1
8.3.2
PSRR1MHZ
IOUT
Power Supply Ripple Rejection
Output Current
db
mA
mA
300
900
VIN = 3.6V, VOUT = 0V, Tested under
a pulsed load condition
ICURRENT_LIMIT
Short Circuit Current Limit
400
120
LDO- or LSW-mode, VIN = 3.3V and
then LDO is enabled, COUT
4µF, IOUT = 0 mA or 300mA
8.3.3
8.3.4
IIN_RUSH
LDO inrush current
=
650
400
30
mA
Active only when converter is
disabled
RDISCHARGE
250
25
Ω
VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LDO-mode,
TJ = 25°C
Quiescent Current in ACTIVE state
at 25°C
8.3.5a IQ_ACTIVE
8.3.5b IQ_ACTIVE
8.3.5b IQ_ACTIVE
8.3.5c IQ_ACTIVE
8.3.5d IQ_ACTIVE
µA
VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LDO-mode,
TJ = -40°C to 125°C
Quiescent Current in ACTIVE state
-40°C to 125°C
25
25
60
70
40
40
µA
µA
µA
µA
Quiescent Current in ACTIVE state VVSYS = VIN = 3.3 V, IOUT = 0 mA,
-40°C to 150°C
Applies to LDO-mode,
TJ = -40°C to 150°C
VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LSW-mode,
TJ = 25°C
Quiescent Current in ACTIVE state
at 25°C
112
145
VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LSW-mode,
TJ = -40°C to 125°C
Quiescent Current in ACTIVE state
-40°C to 125°C
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6.9 General Purpose LDOs (LDO3, LDO4) (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Quiescent Current in ACTIVE state VVSYS = VIN = 3.3 V, IOUT = 0 mA,
8.3.5d IQ_ACTIVE
-40°C to 150°C
Applies to LSW-mode,
TJ = -40°C to 150°C
70
145
µA
8.4.1
8.4.2
CIN
Input Filtering Capacitance (2)
Output Filtering Capacitance (2)
2.2
1.6
4.7
2.2
µF
µF
Connected from VLDOx to GND,
LDO-mode
COUT
4
1 MHz < f < 10 MHz, impedance
between output and point-of-load
maximum 6nH
Total Capacitance at Output (Local
+ POL), fast ramp-time (3)
8.4.3a COUT_TOTAL_FAST
15
µF
1 MHz < f < 10 MHz, impedance
between output and point-of-load
maximum 6nH
Total Capacitance at Output (Local
+ POL), slow ramp-time (3)
8.4.3b COUT_TOTAL_SLOW
8.4.4 CESR
30
20
µF
Filtering capacitor ESR max
1MHz to 10MHz
10
mΩ
Timing Requirements
Measured from enable to 98% of
target value, LDO-mode, measured
when enabled individually,
8.5.1a tRAMP_FAST
Ramp Time fast
660
2.3
µs
assuming no residual voltage
Measured from enable to 98% of
target value, LDO-mode, measured
when enabled individually,
8.5.1b tRAMP_SLOW
Ramp Time slow
ms
assuming no residual voltage
LDO- or LSW-mode, measured
from 0.5V to target value
8.5.2a tRAMP_SLEW_FAST Ramp Up Slew Rate fast
8.5.2b tRAMP_SLEW_SLOW Ramp Up Slew Rate slow
(1) PVIN_LDOx must not exceed VSYS
25 mV/µs
mV/µs
LDO- or LSW-mode, measured
from 0.5V to target value
9
(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above
therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the
capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of
regulators.
(3) Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable
6.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO,
MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Electrical Characteristics
Low-level Output Voltage (open-
drain)
VIO = 3.6V, IOL = 2mA, GPO1,
GPO2, GPIO, nRSTOUT, nINT
9.1.1
9.1.2
VOL
0.40
0.4
V
V
EN/PB, MODE/STBY, MODE/
RESET and VSEL_SD/VSEL_DDR,
GPIO
VIL
Low-level Input Voltage
High-level Input Voltage
EN/PB, MODE/STBY, MODE/
RESET and VSEL_SD/VSEL_DDR,
GPIO
9.1.3
VIH
1.26
V
VSENSE Comparator Threshold
(EN/PB/VSENSE)
9.1.4
9.1.5
VVSENSE
1.08
8
1.20
30
1.32
55
V
VSENSE Comparator Hysteresis
(EN/PB/VSENSE)
VVSENSE_HYS
mV
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6.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO,
MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR) (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input leakage current (GPIO,
EN/PB/VSENSE, MODE/STBY,
MODE/RESET, VSEL_SD/VSEL/
DDR)
9.1.6
ILKG
VIN = 3.3 V
1.0
10
35
μA
pF
Internal input pin
capacitance (GPIO, EN/PB/
VSENSE, MODE/STBY, MODE/
RESET, VSEL_SD/VSEL/DDR)
9.1.7
CIN
on pins GPO1, GPO2, GPIO,
pull-down current, available 100us MODE/STBY, MODE/RESET,
after VSYS is applied
9.1.8
9.1.9
IPD
18
25
nA
VSEL_SD/VSEL_DDR, nINT,
nRSTOUT
Pin leakage when VSYS is present,
but digital supply VDD1P8 is not
ILKG_VSYS_ONLY
SDA only
1
μA
Pin voltage when VSYS is present, GPO1, GPO2, GPIO, nRSTOUT,
9.1.10 VPIN_VSYS_ONLY
Timing Requirements
9.2.1a tFALL
0.4
V
but digital supply VDD1P8 is not
nINT, IOL=2mA
GPO1, GPO2, GPIO, nRSTOUT,
nINT, COUT = 10pF
Output buffer fall time (90% to 10%)
50
5
ns
GPIO Output buffer rise time (10% GPIO, applicable in Multi-PMIC-
9.2.1b tRISE
μs
to 90%)
configuration
COUT = 10pF
Output buffer falling time delay
(input crossing 50% to output
crossing 50%)
9.2.1.1 tDLY_FALL
50
35
ns
ns
Only for nINT and GPO1, SCAN
VSYS voltage = 3.3V for SCAN,
COUT=50pF
Push Pull Output buffer fall time
(90% to 10%)
9.2.1.2 tFALL_PP
9.2.2.1 tDLY_RISE
9.2.2.2 tRISE_PP
Open Drain Output buffer rising time
delay
COUT = 10pF, RPU=1k (external pull
up), VIO = 1.8V
300
35
ns
(digital input to output crossing
50%)
Only for nINT and GPO1, SCAN
VSYS voltage = 3.3V for SCAN,
COUT=50pF
Push Pull Output buffer rise time
(10% to 90%)
ns
Time the digital has allotted for the
9.2.2.3 FLT_HIGHDuration test to see if the pin can be pulled
high internally
COUT = 10pF
COUT = 10pF
15
15
μs
μs
Time the digital has allotted for the
9.2.2.4 FLT_LOWDuration test to see if the pin can be pulled
low internally
EN/PB/VSENSE, Wait Time PB, ON
9.2.2a tPB_ON_SLOW
request, slow
PB, falling Edge
PB, falling Edge
PB, falling Edge
540
180
7.2
115
59
600
200
8.0
200
100
50
660
220
8.8
275
137
55
ms
ms
s
EN/PB/VSENSE, Wait Time PB, ON
9.2.2b tPB_ON_FAST
request, fast
EN/PB/VSENSE, Wait Time PB,
OFF request
9.2.3
9.2.4
9.2.5
9.2.6
tPB_OFF
EN/PB/VSENSE, Deglitch time PB, PB, rising Edge, applicable after the
rising edge
tPB_RISE_DEGL
tPB_INT_DEGL
tDEGL_EN_Rise_Slow
ms
ms
ms
successful long-press-OFF-request
EN/PB/VSENSE, Deglitch time PB,
rising or falling edge
PB, rising or falling Edge
EN/PB/VSENSE, DeglitchTime EN
slow, rising
EN, rising Edge
45
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6.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO,
MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR) (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
EN/PB/VSENSE, DeglitchTime EN
fast, rising
9.2.7
tDEGL_EN_Rise_Fast
EN, rising Edge
60
120
150
93
μs
μs
EN/PB/VSENSE, DeglitchTime EN,
falling
9.2.8
9.2.9
tDEGL_EN_Fall
EN, falling Edge
50
70
VSENSE rising: only gated by
tDEGL_VSENSE_Rise VSYSPOR_Rising and VSENSE-
voltage
VSENSE, rising Edge
N/A
EN/PB/VSENSE, DeglitchTime
9.2.10 tDEGL_VSENSE_Fall VSENSE, falling, regardless of fast/ VSENSE, falling Edge
slow setting
50
70
93
μs
EN/VSENSE falling edge after
previous shutdown request by I2C
(shorter than 9.2.8)
tDEGL_EN/
EN/VSENSE falling edge deglitch
time after I2C-triggered shutdown
9.2.11
12.5
90
25
37.5
150
μs
μs
VSENSE_I2C
MODE/RESET, Deglitch Time
RESET
9.2.12 tDEGL_RESET
RESET, rising and falling Edge
120
Deglitch Time MODE/STBY,
MODE(not/RESET), VSEL_SD/
VSEL_DDR
9.2.13 tDEGL_MFP
9.2.14 tDEGL_GPIO
9.2.15 tREACTION_ON
Rising and falling Edge
Rising and falling Edge
90
120
15.6
75
150
18
μs
μs
µs
Deglitch Time GPIO
6.6
Includes oscillator startup, sampling
delay and reaction delay (excluding
deglitch)
ON-request propagation delay (after
deglitch)
103
Includes sampling delay
and reaction delay (excluding
deglitch)
OFF-request propagation delay
(after deglitch)
9.2.16 tREACTION_OFF
39
56
73.5
µs
6.11 Voltage and Temperature Monitors
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
–5%
MAX UNIT
Electrical Characteristics
Undervoltage monitoring for buck
output, programable low-going
threshold accuracy
VBUCKx_UV_TH_5
VLDOx_UV_TH_5
,
10.1.1
10.1.2
10.1.3
UV_THR = 0x0
Undervoltage monitoring for buck
output and LDO output,
programable low-going threshold
accuracy
VBUCKx_UV_TH_10
VLDOx_UV_TH_10
,
UV_THR = 0x1
–10%
VBUCKx_UV_H_ACC
,
VLDOx_UV_H_ACC
Undervoltage Threshold Accuracy,
OUT ≥1V
-1.5%
+1.5%
V
OUT ≥1V
V
VBUCKx_UV_L_ACC,
Undervoltage Threshold Accuracy,
VOUT < 1V
10.1.4
10.1.5
10.1.6
VOUT < 1V
-10
0.25%
220
+10
mV
VLDOx_UV_L_ACC
VBUCKx_UV_HYS
VLDOx_UV_HYS
,
Undervoltage Hysteresis
1% 1.75%
Short-circuit (SCG) and residual
voltage (RV) detection low-going
threshold
VBUCKx_SCG_TH
VLDOx_SCG_TH
,
260
75
300
mV
mV
Short-circuit (SCG) and residual
voltage (RV) detection threshold
hysteresis
VBUCKx_SCG_HYS
VLDOx_SCG_HYS
,
10.1.7
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MAX UNIT
6.11 Voltage and Temperature Monitors (continued)
over operating free-air temperature range (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
Temperature rising Warning
Threshold (WARM)
10.2.1a TWARM_Rising
for each of the four sensors
130
140
150
145
160
150
°C
°C
°C
Temperature falling Warning
Threshold (WARM)
10.2.1b TWARM_Falling
10.2.2a THOT_Rising
10.2.2b THOT_Falling
for each of the four sensors
for each of the four sensors
for each of the four sensors
125
140
130
135
150
Temperature rising Shutdown
Threshold (TSD, HOT)
Temperature falling Shutdown
Threshold (TSD, HOT)
140
-5
°C
°C
10.2.3 THYS
Temperature Hysteresis for WARM for each of the four sensors
Timing Requirements
Fault Detection Deglitch Time for
10.3.1a tDEGLITCH
Under Voltage (UV) and Short to
GND (SCG)
Measured from UV/SCG event
13
26
20
35
2
27
45
µs
µs
ms
µs
µs
ms
µs
Fault Detection Deglitch Time for
Measured from OC event, rising
edge
10.3.1b tDEGLITCH_OC_short Over Current (OC), rising edge,
short
Fault Detection Deglitch Time for
10.3.1c tDEGLITCH_OC_long Over Current (OC), rising edge,
long
Measured from OC event, rising
edge
1.6
26
2.2
54
Fault Reaction Time for Under
Voltage (UV) and Short to GND
(SCG) (including deglitch time)
Measured from UV/SCG event to
nINT pulled low
10.3.2a tREACTION
40
65
2
Fault Reaction Time for Over
Current (OC) (including deglitch
time)
tREACTION_OC_shor
Measured from UV/OC/SCG event
to nINT pulled low
10.3.2b
45
81
t
Fault Detection Deglitch Time for
Measured from OC event, rising
edge
10.3.2c tREACTION_OC_long Over Current (OC), rising edge,
long
1.6
2.2
525
Fault Reaction Time for
10.3.2d tREACTION_WARM Temperature Warning (WARM),
Thermal Shutdown (TSD / HOT)
Measured from WARM/HOT event
to nINT pulled low
6.12 I2C Interface
Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode
(400 kHz), and fast mode+ (1 MHz) when VIO is 3.3V or 1.8V.
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Electrical Characteristics
VIO = 3.6V, IOL = 3mA for Standard
mode and Fast mode, IOL = 20mA
for Fast mode+, SDA
11.1.1 VOL
Low-level Output Voltage
0.40
0.40
V
11.1.2 VIL
11.1.3 VIH
Low-level Input Voltage
High-level Input Voltage
SDA, SCL
SDA, SCL
V
V
1.26
100
EN_BP/VSENSE, MODE_RESET,
MODE_STBY, SDA, SCL, GPIO
11.1.4 VHYST
Input buffer Hysteresis
500
400
mV
pF
11.1.5 CB
Capacitive Load for SDA and SCL
Timing Requirements
11.2.1
Standard mode
Fast mode
100
400
1
kHz
11.2.2
11.2.3
Serial Clock Frequency
ƒSCL
Fast mode+
MHz
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6.12 I2C Interface (continued)
Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode
(400 kHz), and fast mode+ (1 MHz) when VIO is 3.3V or 1.8V.
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
11.3.1
Standard mode
4.7
11.3.2 tLOW
11.3.3
SCL low Time
Fast mode
1.3
µs
Fast mode+
Standard mode
Fast mode
0.50
4.0
11.4.1
11.4.2 tHIGH
11.4.3
SCL high Time
Data setup Time
Data hold Time
0.60
0.26
250
100
50
µs
Fast mode+
Standard mode
Fast mode
11.5.1
11.5.2 tSU;DAT
11.5.3
ns
Fast mode+
Standard mode
Fast mode
11.6.1
10
3450
11.6.2 tHD;DAT
11.6.6
10
900
ns
µs
µs
µs
µs
Fast mode+
Standard mode
Fast mode
10
11.7.1
4.7
Setup Time for a Start or a
REPEATED Start Condition
11.7.2 tSU;STA
11.7.3
0.60
0.26
4.7
Fast mode+
Standard mode
Fast mode
11.8.1
Hold Time for a Start or a
REPEATED Start Condition
11.8.2 tHD;STA
11.8.3
0.60
0.26
4.7
Fast mode+
Standard mode
Fast mode
11.9.1
Bus free Time between a STOP and
Start Condition
11.9.2 tBUF
11.9.3
1.3
Fast mode+
Standard mode
Fast mode
0.50
0.60
0.60
0.26
11.10.1
11.10.2 tSU;STO
11.10.3
Setup Time for a STOP Condition
Rise Time of SDA Signal
Fast mode+
Standard mode, VIO = 1.8V, RPU
10 kΩand CB = 400 pF
=
11.10.1
1000
300
120
300
300
120
1000
300
120
Fast mode, VIO = 1.8V, RPU = 1 kΩ
and CB = 400 pF
11.10.2 trDA
11.10.3
20
ns
ns
ns
Fast mode+, VIO = 1.8V, RPU = 330
Ωand CB = 400 pF
Standard mode, VIO = 1.8V, RPU
10 kΩand CB = 400 pF
=
11.12.1
Fast mode, VIO = 1.8V, RPU = 1 kΩ
and CB = 400 pF
11.12.2 tfDA
11.12.3
Fall Time of SDA Signal
6.5
6.5
Fast mode+, VIO = 1.8V, RPU = 330
Ωand CB = 400 pF
Standard mode, VIO = 1.8V, RPU
10 kΩand CB = 400 pF
=
11.13.1
Fast mode, VIO = 1.8V, RPU = 1 kΩ
and CB = 400 pF
11.13.2 trCL
11.13.3
Rise Time of SCL Signal
20
Fast mode+, VIO = 1.8V, RPU = 330
Ωand CB = 400 pF
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6.12 I2C Interface (continued)
Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode
(400 kHz), and fast mode+ (1 MHz) when VIO is 3.3V or 1.8V.
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Standard mode, VIO = 1.8V, RPU
10 kΩand CB = 400 pF
=
11.14.1
300
Fast mode, VIO = 1.8V, RPU = 1 kΩ
and CB = 400 pF
11.14.2 tfCL
11.14.3
Fall Time of SCL Signal
6.5
6.5
300
120
ns
ns
Fast mode+, VIO = 1.8V, RPU = 330
Ωand CB = 400 pF
Pulse Width of Spike suppressed
(SCL and SDA Spikes that are less
than the indicated Width are
suppressed)
11.15.1 tSP
Fast mode, and fast mode+
50
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6.13 Typical Characteristics
VIN = 5 V
VOUT = 1.8 V
TA = 25°C
VIN = 5 V
VOUT = 1.8 V
TA = 25°C
图6-1. Efficiency BUCK1
图6-2. Efficiency BUCK23
I(BUCK1) (500mA/div)
I(BUCK2) (500mA/div)
V(BUCK2) (100mV/div, AC)
(20µs/div)
V(BUCK1) (20mV/div, AC)
(20µs/div)
VIN = 5.0 V
VOUT = 0.75 V
TA = 25 °C
VIN = 5.0 V
IOUT = 1 mA to 1 A to 1 mA,
trise=tfall=1μs
VOUT = 3.3 V
TA = 25 °C
IOUT = 100 mA to 1.1 A to 100 mA,
trise=tfall=500ns
COUT_total = 57 μF
COUT_total = 57 μF
图6-3. BUCK1 Load-step response - High
图6-4. BUCK2 Load-step response - Low
Bandwidth, forced PWM
Bandwidth, forced PWM
I(BUCK3) (500mA/div)
I(LDO1) (500mA/div)
V(BUCK3) (100mV/div, AC)
(20µs/div)
V(LDO1) (100mV/div, AC)
(20µs/div)
VIN = 5.0 V
VOUT = 1.2 V
TA = 25 °C
VIN = 3.3 V
VOUT = 1.8 V
TA = 25 °C
IOUT = 1 mA to 1 A to 1 mA,
IOUT = 80 mA to 320 mA to 80 mA,
COUT_total = 57 μF
COUT = 10 μF
trise=tfall=1μs
trise=tfall=1μs
图6-5. BUCK3 Load-step response - Low
图6-6. LDO1 Load-step response
Bandwidth, forced PWM
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I(LDO2) (500mA/div)
I(LDO3) (500mA/div)
V(LDO2) (20mV/div, AC)
(20µs/div)
V(LDO3) (100mV/div, AC)
(20µs/div)
VIN = 3.3 V
VOUT = 0.85 V
TA = 25 °C
VIN = 5 V
VOUT = 3.3 V
TA = 25 °C
IOUT = 80 mA to 320 mA to 80 mA,
IOUT = 60 mA to 240 mA to 60 mA,
COUT = 10 μF
COUT = 10 μF
trise=tfall=1μs
trise=tfall=1μs
图6-7. LDO2 Load-step response
图6-8. LDO3 Load-step response
I(LDO4) (500mA/div)
V(LDO4) (20mV/div, AC)
(20µs/div)
VIN = 3.3 V
VOUT = 1.8 V
TA = 25 °C
IOUT = 60 mA to 240 mA to 60 mA, trise=tfall=1μs
COUT = 10 μF
图6-9. LDO4 Load-step response
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7 Detailed Description
7.1 Overview
The TPS65219-Q1 provides three step-down converters, four LDOs, three general-purpose I/Os and three multi-
Function pins. The system can be supplied by a single cell Li-Ion battery, two primary cells or a regulated supply.
The device is characterized across a -40°C to +125°C temperature range, which makes the PMIC an excellent
choice for various automotive applications.
The I2C interface provides comprehensive features for using TPS65219-Q1. All rails, both GPOs and the GPIO
can be enabled or disabled. Voltage thresholds for the undervoltage monitoring can be customized.
The integrated voltage supervisor monitors Buck 1–3 and LDO1–4 for undervoltage. The monitor has two
sensitivity settings. A power good signal is provided to report the successful ramp of the seven rails and GPOs.
The nRSTOUT pin is pulled low until the device enters ACTIVE state. When powering down from ACTIVE- or
STBY-state, nRSTOUT is pulled low again. The nRSTOUT pin has an open-drain output. A fault-pin, nINT,
notifies the SoC about faults.
Buck1 step-down converter can supply up to 3.5 A of current, Buck2 and Buck3 can supply up to 2 A each. The
default output voltages for each converter can be adjusted through the I2C interface. All three buck-converters
feature dynamic voltage scaling. The step-down converters operate in a low power mode at light load or can be
forced into PWM operation for noise sensitive applications.
LDO1 and LDO2 support output currents of 400 mA at an output voltage range of 0.6 V to 3.4 V. These LDOs
support bypass mode, acting as a load-switch, and allow voltage-changes during operation for applications like
SD-card-supply, adjusting the IO-supply of the SD-card from 3.3 V to 1.8 V after initialization.
LDO3 and LDO4 support output currents of 300 mA at an output voltage range of 1.2 V to 3.3 V. These LDOs
support load-switch-mode, but not bypass mode.
The I2C-interface, IOs, GPIOs, and multi-function-pins (MFP) allow a seamless interface to a wide range of
SoCs.
All configurations of the rails, for example output-voltages, sequencing, are backed up by EEPROM. Please refer
to the Technical Reference Manual (TRM) of the chosen configuration.
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7.2 Functional Block Diagram
TPS65219-Q1
PIN_LDO1
VLDO1
From 1.5-V to VSYS
supply
PVIN_B1
From 2.5-V to VSYS
2.2
2.2
F
F
1.8-V/3.3-V SD-card-IO supply,
0.85V low-power-core supply
or 1.8-V Analog supply
DVS
system power
4.7
F
LDO1
LX_B1_1
LX_B1_2
DVS
(adjustable 0.6V to 3.4V)
0.75-V core supply
(adjustable 0.6V to 3.4V)
10 F (depends on configuration)
Buck1
FB_B1
PIN_LDO2
VLDO2
From 1.5-V to VSYS
supply
2.2
2.2
F
F
1.8-V/3.3-V SD-card-IO supply,
0.85V low-power-core supply
or 1.8-V Analog supply
PVIN_B2
From 2.5-V to VSYS
system power
DVS
LDO2
4.7
10
F
3.3-V IO-supply
(adjustable 0.6V to 3.4V,
(adjustable 0.6V to 3.4V)
LX_B2
FB_B2
DVS
3.3V requires higher min VIN!)
Buck2
F
(depends on configuration)
1.8-V Analog-supply
(adjustable 1.2V to 3.3V)
VLDO3
LDO3
LDO4
PVIN_B3
From 2.5-V to VSYS
system power
2.2
F
4.7
10
F
PIN_LDO34
VLDO4
From 2.2-V to VSYS
supply
LX_B3
FB_B3
1.1-V DDR supply
DVS
(adjustable 0.6V to 3.4V)
F (depends on configuration)
4.7
2.2
F
F
Buck3
1.8-V IO-supply
(adjustable 1.2V to 3.3V)
FB_B1
FB_B2
Supervisor
and up-/
down-
FB_B3
VLDO1
VLDO2
AGND
VLDO3
VLDO4
sequencer
VSYS
From 2.5-V to 5.5-V
system power
F
VIO
10
2.2
VDD1P8
SCL
SDA
INT LDO
From SOC
2.2
F
I2C
VIO
10
VIO
To / from SOC
10
nRSTOUT
nINT
VIO
10
OD
OD
To SOC
To SOC
GPO1
GPO2
OD
OD
VIO
To External rail EN
To External rail EN
10
VIO
10
DIGITAL
MODE/STBY
From SOC
VIO
10
To External rail EN
or to 2nd TPS65219
GPIO
MODE/RESET
OD
From SOC
From SOC
PB/EN/
VSENSE
VSYS
VSEL_SD/
VSEL_DDR
Momentary push-button
Thermal
Pad
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图7-1. Functional Block Diagram
7.3 Feature Description
7.3.1 Power-Up Sequencing
The TPS65219-Q1 allows flexible sequencing of the rails. The order of the rails, including GPO1, GPO2, GPIO
for the external rails, and the nRSTOUT pin is defined by the NVM. Prior to starting the power-up sequence, the
device checks if the voltage on all rails fell below the SCG-threshold to avoid starting into a pre-biased rail. The
sequence is timing based. In addition, the previous rail must have passed the UV-threshold, else the subsequent
rail is not enabled. If UV is masked, the sequence proceeds even if the UV-threshold is not reached. GPO1,
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GPO2, GPIO, and LDOs configured in bypass- or LSW-mode are not monitored for under-voltage, thus their
outputs do not gate subsequent rails.
In case the sequence is interrupted due to an unmasked fault on a rail, the device powers down. The TPS65219-
Q1 attempts to power up two more times. If both of those re-tries fail to enter ACTIVE state, the device remains
in INITIALIZE state until VSYS is power-cycled. While it is encouraged to keep this retry-counter active, one can
disable it by setting bit MASK_RETRY_COUNT in INT_MASK_UV register.
To disable the retry-counter, set bit MASK_RETRY_COUNT in INT_MASK_UV register. When set, the device
attempts to retry infinitely.
The TPS65219-Q1 allows to configure the power-down sequence independent from the power-up sequence.
The sequences are configured in the non-volatile memory.
At initial power-up, the device monitors the VSYS supply voltage and allows power-up and transition to
INITIALZE state only if VSYS passed the VSYSPOR_Rising threshold.
The power-up sequence is configured as follows:
• The slot (respectively the position in the sequence) for each rail and GPO1, GPO2, GPIO, and nRSTOUT is
defined using the corresponding *_SEQUENCE_SLOT registers, the four MSB for the power-up sequence,
the four LSB for the power-down sequence.
• The duration of each slot is defined in the POWER_UP_SLOT_DURATION_x registers and can be
configured as 0 ms, 1.5 ms, 3 ms or 10 ms. In total, 16 slots can be configured, allowing the sequence to
span over multiple TPS65219-Q1-devices if more rails need to be supported.
• In addition to the timing as defined above, the power-up-sequence is also gated by the UV-monitor: a
subsequent rail only gets enabled after the previous one passed the under-voltage threshold (unless UV is
masked). If a rail has not reached the UV-threshold by the end of tRAMP (respectively tRAMP_LSW, tRAMP_SLOW
,
tRAMP_FAST), the sequence is aborted and the device sequences down at the end of the slot-duration. For the
respective rail, the device sets INT_BUCK_x_y_IS_SET respectively INT_LDO_x_y_IS_SET bit in
INT_SOURCE register and BUCKx_UV respectively LDOx_UV bit in INT_BUCK_x_y respectively
INT_LDO_x_y register as well as bit TIMEOUT in the INT_TIMEOUT_RV_SD register.
• The initiation of the sequence is gated by the successful discharge of all rails, irrespective if enabled during
the sequence or not. If the device is unable to discharge all rails below the SCG-threshold, the device sets
INT_BUCK_x_y_IS_SET respectively INT_LDO_x_y_IS_SET bit in INT_SOURCE register and BUCKx_RV
respectively LDOx_RV bit if the residual voltage is still present after 4 ms to 5 ms and the device remains in
INITIALIZE state.
• The initiation of the sequence is gated by the die-temperature: if any one of the WARM detections is
unmasked, the device does not power-up until the temperature on all sensors fell below TWARM_falling
threshold if INITIALIZE state was entered due to a thermal event, respectively until the temperature on all
sensors is below TWARM_rising threshold if INITIALIZE state was entered from OFF-state. If all thermal sensors
are masked (WARM detection not causing a power-down), the device does not power-up until the
temperature on all sensors is below THOT_falling threshold
备注
All rails get discharged prior to enable (irrespective if discharge-function is disabled).
An ON-request is deglitched to not trigger on noise. After the deglitch time, the device takes approximately 300
μs until the first slot of the sequence starts. In case discharging of pre-biased rails is not completed by that time,
the start of the sequence is further gated until all rails have discharged below SCG-voltage level.
Below graphic shows the power-up-sequence for NVM-ID 0x01, revision 0x2 as an example:
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PMIC Rail
Sequence
AM62x Domain
VSYS >
VSYSPOR_Rising
tEEPROM_LOAD = ~2.3ms
ON-Request
tEN_PB_VSENSE_DEGL
*
DVDD3V3
Buck2 / 3.3V
1.5ms
GPO1
DVDD1V8
DDR4 VPP
LDO4 / 2.5V
VDDSHV5_MMC
LDO1 / 3.3V-1.8V
LDO3 / 1.8V
VDDA_1V8
VDDS_DDR
VDD_CORE
VDDR_CORE
4.5ms **
1.5ms
Buck3 / 1.2V
Buck1 / 0.75V
LDO2 / 0.85V
1.5ms
1.5ms
MCU_OSC0_XI
MCU_OSC0_XO
11.5ms
MCU_PORz
nRSTOUT
10ms
until RESET and
STBY are relevant
Slot_0
1.5ms
Slot_1
0ms
Slot_2
3ms
Slot_3
1.5ms
Slot_4
1.5ms
Slot_5
1.5ms
Slot_6
1.5ms
Slot_7
10ms
Slot_8
1.5ms
Slot_9
10ms
*
depends on EN / PB / VSENSE and long/short configuration, ~0 if FSD is enabled
** if applicable, slot-duration needs to adopt for enable- & ramp-time of external rail
图7-2. Power-up sequencing (example)
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For details on ON-requests please see Push Button and Enable Input (PB/EN/VSENSE).
CAUTION
I2C commands must only be issued after EEPROM-load completed.
7.3.2 Power-Down Sequencing
An OFF-request or a shut-down-fault triggers the power-down sequence. The OFF-request can be triggered by a
falling edge on EN/PB/VSENSE if configured for EN or VSENSE respectively a long press of the push-button if
configured as PB or by an I2C-command to I2C_OFF_REQ in MFP_CTRL register. This bit self-clears.
An I2C-triggered shut-down requires a renewed ON-request on the EN/PB/VSENSE pin. In case of EN- or
VSENSE-configuration, a low-going edge followed by a high-going-edge is required on the EN/PB/VSENSE-pin.
The falling-edge deglitch time for EN or VSENSE configuration tDEGL_EN/VSENSE_I2C is shorter than the deglitch-
time for pin-induced OFF-requests (tDEGL_EN_Fall and tDEGL_VSENSE_Fall). The deglitch-times for PB-configuration
remain.
In many cases, the power-down sequence follows the reverse power-up sequence. In some applications, all rails
can be required to shut down at the same time with no delay between rails or require wait-times to allow
discharging of rail.
The power-down sequence is configured as follows:
• The slot (respectively the position in the sequence) for each rail and GPO1, GPO2, GPIO, and nRSTOUT is
defined using the corresponding *_SEQUENCE_SLOT registers, the four MSB for the ON-sequence, the four
LSB for the down-sequencing.
• The duration of each slot is defined in the POWER_DOWN_SLOT_DURATION_x registers and can be
configured as 0 ms, 1.5 ms, 3 ms or 10 ms. In total, 16 slots can be configured, allowing the sequence to
span over multiple TPS65219-Q1-devices if more rails need to be supported.
• In addition to the slot-duration, the power-down sequence is also gated by the previous rail being discharged
below the SCG-threshold, unless active discharge is disabled on the previous rail. If that does not occur, the
power-down of subsequent rails is paused. To allow for power-down in case of biased or shorted rails, the
sequence continues despite an incomplete discharge of the previous rail after eight times the slot-duration (or
12 ms in case of slot-duration of 0 ms).
• To bypass the discharge-check, set the bit BYPASS_RAILS_DISCHARGED_CHECK in register
GENERAL_CONFIG to '1'.
备注
In case active discharge on a rail is disabled, unsuccessful discharge of the rail within the slot duration
does not gate the disable of the subsequent rail, but the sequence is purely timing based. In case of
residual voltage, the RV-bit is be set regardless.
Active discharge is enabled by default and not NVM based. Thus, if desired, discharge need to be disabled after
each VSYS-power-cycle. During RESET or OFF-request, the discharge configuration is not reset, as long as
VSYS is present. However, in INITIALIZE state and prior to the power-up-sequence, all rails get discharged,
regardless of the setting.
During the power-down-sequence, non-EEPROM-backed bits get reset, with the exception of unmasked
interrupt bits and *_DISCHARGE_EN bits.
Below graphic shows the power-down-sequence for NVM-ID 0x01, revision 0x2 as an example:
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PMIC Rail
Sequence
AM62x Domain
OFF-Request
tDEGL_OFF
MCU_PORz
nRSTOUT
VDDS_DDR
Buck3 / 1.2V
LDO2 / 0.85V
VDDR_CORE
MCU_OSC0_XI
MCU_OSC0_XO
10ms *
VDD_CORE
BUCK1 / 0.75V
DVDD1V8
GPO1
LDO3 / 1.8V
LDO1 / 3.3V-1.8V
LDO4 / 2.5V
BUCK2 / 3.3V
VSYS
VDDA_1V8
VDDSHV5_MMC
10ms *
DDR4 VPP
DVDD3V3
10ms
Slot_0
10ms
Slot_1
0ms
Slot_2
10ms
Slot_3
0ms
Slot_4
10ms
* discharge-duration depends on Vout, Cout and load. Slot-duration needs to adopt.
Slot-duration extends up to 8x its configured value.
图7-3. Power-down sequencing (example)
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CAUTION
Do not change the registers related to an ongoing sequence by I2C-command!
Non-NVM-bits are not accessible for approximately 80 μs after starting a transition into INITIALIZE
state.
7.3.3 Push Button and Enable Input (EN/PB/VSENSE)
The EN/PB/VSENSE pin is used to enable the PMIC. The pin can be configured in three ways:
• Device enable (EN):
– This pin needs to be pulled high to enable the device. Pulling this pin low disables the device.
– The deglitch-time of the EN-pin is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
– The power-up sequence starts if the EN input is above the VIL-threshold low for the configured
tDEGL_EN_Rise
.
– To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit
POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert
the nINT pin. Write W1C to clear the bit.
– The power-down sequence starts if the EN input is below the VIH-threshold for tDEGL_EN_Fall
.
– In case of a shut-down fault, no renewed on-request is required. The device automatically executes the
power-up sequence if EN input is still above the VIH-threshold. (EN considered level-sensitive)
– In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required.
The device automatically executes the power-up sequence if EN input is still above the VIH-threshold. (EN
considered level-sensitive)
• Push-Button (PB):
– The PB pin is a CMOS-type input used to power-up the PMIC. Typically, the PB pin is connected to a
momentary switch to ground and an external pullup resistor.
– The hold-time of the push-button is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
– The power-up sequence starts if the PB input is below the VIL-threshold low for the configured tPB_ON
.
– To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit
POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert
the nINT pin. Write W1C to clear the bit.
– The PB pin has a rising-edge deglitch tPB_RISE_DEGL to filter bouncing of the switch
– The power-down sequence starts if the PB input is held low for tPB_OFF-time (not configurable).
– In case of a shut-down fault, no renewed on-request is required. The device automatically executes the
power-up sequence without a PB-press.
– In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required.
The device automatically executes the power-up sequence without a PB-press.
– A push-button press is only recognized after VSYS is above VSYS_POR-threshold or the PB must be held
long enough after VSYS is above VSYS_POR-threshold.
– Following bits in the signify the PB-press events:
• PB_FALLING_EDGE_DETECTED: PB was pressed for a time-interval longer than tPB_INT_DEGL since
the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit
MASK_INT_FOR_PB='0'). Write W1C to clear.
• PB_RISING_EDGE_DETECTED: PB was released for a time-interval longer than tPB_INT_DEGL since
the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit
MASK_INT_FOR_PB='0'). Write W1C to clear.
• PB_REAL_TIME_STATUS: Deglitched (tPB_INT_DEGL) real-time status of PB pin. Valid only when
EN/PB/VSENSE pin is configured as PB. This bit does not assert the nINT pin.
• Power-fail comparator input (VSENSE):
– Connected to a resistor divider from the supply-line of the pre-regulator, this pin can be used to sense the
supply-voltage to the pre-regulator.
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– The deglitch-time of the VSENSE-pin is configurable by EN_PB_VSENSE_DEGL in MFP_2_CONFIG
register.
– Power-up is gated by VSYS being above the VSYSPOR_Rising-threshold and the VSENSE input is above
the VVSENSE-threshold (not deglitched)
– The power-up sequence starts if the VSENSE input rises above VVSENSE
.
– To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit
POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert
the nINT pin. Write W1C to clear the bit.
– The power-down sequence starts if the VSENSE input falls below the VVSENSE-threshold for
tDEGL_VSENSE_Fall, to avoid an un-sequenced power-off due to the loss of VSYS-supply-voltage.
– In case of a shut-down fault, no renewed on-request is required. The device automatically executes the
power-up sequence if VSENSE input is still above the VVSENSE-threshold.
– In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required.
The device automatically executes the power-up sequence if VSENSE input is still above the VVSENSE
-
threshold.
• OFF-request by I2C-command
– An OFF-request can also be triggered by an I2C-command to I2C_OFF_REQ in MFP_CTRL register.
– After an OFF-request, a new ON-request is required:
• In case of EN-configuration, the EN input requires a rising edge (EN considered edge-sensitive)
• In case of PB-configuration, the PB needs to be pressed for a valid ON-request
• In case of VSENSE-configuration, the VSENSE input requires a rising edge (VSENSE considered
edge-sensitive). This ON request can be triggered by power cycling the pre-regulator.
• The falling-edge deglitch time for EN or VSENSE configuration tDEGL_EN/VSENSE_I2C is shorter than the
deglitch-time for pin-induced OFF-requests (tDEGL_EN_Fall and tDEGL_VSENSE_Fall). The deglitch-times for
PB-configuration remain.
• First Supply detection (FSD)
– First Supply detection (FSD) allows power-up as soon as supply voltage is applied, even if EN/PB/
VSENSE pin is at OFF_REQ status.
– FSD can be used in combination with any ON-request configuration, EN, PB or VSENSE.
– FSD can be enabled by setting PU_ON_FSD bit in MFP_2_CONFIG.
– At first power-up the EN/PB/VSENSE pin is treated as if the pin had a valid ON request.
– Once VSYS is above the VSYSPOR_Rising-threshold, the PMIC
• loads the EEPROM
• enters INITIALIZE state
• perform the discharge-check
• initiates the power-up-sequence, regardless of the EN/PB/VSENSE-pin-state.
– To signify the power-up based on FSD, the device sets bit POWER_UP_FROM_FSD in
POWER_UP_STATUS_REG register. The nINT-pin does not toggle based on this bit. Write W1C to clear
the bit.
– Thereafter, the EN/PB/VSENSE-pin is treated as if the pin had a valid ON-request, until we enter ACTIVE
state (at the expiration of the last slot in the power-up-sequence).
– After that the device adheres to post-deglitch EN/PB/VSENSE-pin-status: if pin status has changed prior
to entering ACTIVE state or in ACTIVE state, the device does adhere to the pin state. For example, if the
EN/PB/VSENSE-pin is configured for EN, the device does power down in case the EN-pin is low (for
longer than the deglitch time) at the time the device enters ACTIVE state.
– The duration for how long the ON-request is considered valid, regardless of the pin-state, can be
controlled by length of nRSTOUT slot (and empty slots thereafter), as the PMIC enters ACTIVE state only
after the last slot of the sequence expired.
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7.3.4 Reset to SoC (nRSTOUT)
The reset output (nRSTOUT) is an open-drain output, intended to release the reset to the SoC or FPGA at the
end of the power-up sequence. The timing for nRSTOUT is configured in the sequence. nRSTOUT is driven low
until the device enters ACTIVE state or when powering-down from ACTIVE- or STBY-state. The pin is driven
high during ACTIVE- and STBY-state.
7.3.5 Buck Converters (Buck1, Buck2, and Buck3)
The TPS65219-Q1 integrates three buck converters. Buck1 is capable of supporting up to 3.5 A and Buck2/
Buck3 are capable of supporting up to 2 A of load current. The buck converters have an input voltage range from
2.5 V to 5.5 V, and can be connected either directly to the system power or the output of a another buck
converter. The output voltage is programmable in the range of 0.6 V to 3.4 V: in 25mV-steps up to 1.4V, in
100mV-steps between 1.4V and 3.4V.
• The ON/OFF state of the buck converters in ACTIVE state is controlled by the corresponding BUCKx_EN bit
in the ENABLE_CTRL register.
• The ON/OFF state of the buck converters in STBY state is controlled by the corresponding
BUCKx_STBY_EN bit in the STBY_1_CONFIG register.
• In INITIALIZE state, the buck converters are off, regardless of bit-settings.
CAUTION
In case of buck-regulators that are not to be used at all, the FB_Bx pin must be tied to GND and the
LX_Bx pin must be left floating.
• The converters activity can be controlled by the sequencer or through I2C communication.
Buck-switch-modes:
• Fixed frequency mode
– The converters can be forced into fixed frequency mode for best EMI-control by setting bit
BUCK_FF_ENABLE bit in BUCKS_CONFIG register. If fixed-frequency mode is enabled, the regulators
also support optional spread-spectrum. Spread-spectrum can be enabled by setting bit
BUCK_SS_ENABLE in BUCKS_CONFIG register. Both of these settings are global for all three buck
converters. If fixed-frequency mode is enabled, the regulators support individual out-of-phase switching:
the phase-relation of the buck rails can be configured in 90°-steps in relation to the phase of Buck1 by
BUCKx_PHASE_CONFIG in the BUCKS_CONFIG register. This bit must only change when this regulator
is disabled.
• Quasi-fixed-frequency mode
– The converters can operate in forced-PWM mode, irrespective of load-current, or can be allowed to enter
pulse-frequency-modulation (PFM) for low load-currents. The mode is controlled by either the MODE/
STBY pin or the MODE/RESET pin if either of those is configured as 'MODE', or by an I2C-command to
MODE_I2C_CTRL bit in MFP_1_CONFIG register (see pin-configuration and I2C-command in 'PWM/PFM
and Low Power Modes (MODE/STBY)' and PWM/PFM and Reset (MODE/RESET)' section.
– During a transition to ACTIVE state or to INITIALIZE state, the buck converters are forced to PWM,
irrespective of the pin-state. PFM-entry is only allowed when the device enters ACTIVE state, upon
completion of the sequence and expiration of the last power-up-slot.
– In case of a DVFS-induced output voltage change, the TPS65219-Q1 temporarily forces the buck-
regulators into PWM until the voltage change completed. If PFM is allowed, the entry and exit into PFM is
load-current dependent. PFM starts when the inductor current reaches 0 A, which is the case at a load
current approximately calculated by:
– ILOAD = {[(VPVIN_Bx - VBUCKx) / L] × (VBUCKx / VPVIN_Bx) × (1 / fSW)} / 2
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CAUTION
The user MUST NOT CHANGE the BUCK_FF_ENABLE! The bit is pre-configured by the
manufacturer.
• The converters can be individually configured further for a high-bandwidth-mode for optimum transient-
response or lower bandwidth, allowing minimum output filter capacitance. The selection is done by the
BUCKx_BW_SEL bits in GENERAL_CONFIG register and is available for both configurations, fixed-
frequency and quasi-fixed-frequency. This bit must only change if this regulator is disabled. Please note the
higher output-capacitance requirements for high bandwidth use case!
• If VSEL_SD/VSEL_DRR is configured as 'VSEL_DDR' by the VSEL_DDR_SD bit in MFP_1_CONFIG
register, the output voltage of Buck3 can be controlled by pulling the VSEL_SD/VSEL_DDR pin high, low or
leave the pin floating. These settings supports DDR3LV, DDR4, and DDR4LV supply voltages without an
EEPROM change.
CAUTION
The VSEL_DDR-pin needs to be hard-wired and must not change during operation.
• The buck converters have an active discharge function. The discharge function can be disabled individually
per rail in the DISCHARGE_CONFIG register. If discharge is enabled, the device discharges the output is
discharged to ground whenever a rail is disabled.
• Prior to a sequence into ACTIVE state (from INITIALIZE or STBY state), the device discharges the disabled
rails regardless of the discharge-configuration to avoid starting into a pre-biased output.
• If a rail is enabled by an I2C-command, active discharge is not enforced, but the rail is only enabled if the
output voltage is below the SCG-threshold.
• This register is not EEPROM-backed and does reset if the device enters OFF-state.
• When in INITIALIZE state (during RESET or an I2C-OFF-request), the discharge configuration is not reset.
Note: the power-down-sequence can be violated if the discharge function is disabled.
All Buck Converters support Dynamic Voltage Frequency Scaling (DVFS). The output-voltage can be changed
during the operation to optimize the operating voltage for the operation point of the SoC in the lower output
voltage range between 0.6 V and 1.4 V. The voltage change is controlled by writing to BUCK1_VOUT
respectively BUCK2_VOUT or BUCK3_VOUT registers. During a DVFS-induced voltage transition, the active
discharge function is temporarily enabled, irrespective of the discharge-configuration.
Output Capacitance Requirements
The buck converters require sufficient output-capacitance for stability. The required minimum and supported
maximum capacitance depends on the configuration:
• for fixed-frequency, low-bandwidth configuration, a minimum capacitance of 12uF is required and a maximum
total capacitance of 36uF is supported
• for quasi-fixed-frequency, low-bandwidth configuration, a minimum capacitance of 10uF is required and a
maximum total capacitance of 75uF is supported
• for fixed-frequency, high-bandwidth configuration, a minimum capacitance of 48uF is required and a
maximum total capacitance of 144uF is supported
• for quasi-fixed-frequency, high-bandwidth configuration, a minimum capacitance of 30uF is required and a
maximum total capacitance of 220uF is supported
Buck Fault Handling
• The TPS65219-Q1 detects under voltages on the buck converter outputs. The reaction to the detection of an
under-voltage is dependent on the configuration of the respective BUCKx_UV bit and the MASK_EFFECT bit
in INT_MASK_BUCKS. If not masked, the device sets bit INT_BUCK_1_2_IS_SET respectively
INT_BUCK_3_IS_SET bit in INT_SOURCE register and bit BUCKx_UV in INT_BUCK_1_2 respectively
INT_BUCK_3 register.
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During a voltage transition (for example, when triggered by a DVFS induced voltage change), the device
blanks the undervoltage detection by default and activates the undervoltage detection when the voltage
transition completed.
If the device detects an undervoltage during the sequence into ACTIVE state (from INITIALIZE or STBY) and
UV is not masked, the power-down-sequence starts at the end of the current slot.
If the device detects an undervoltage in ACTIVE-state or STBY-state and UV is not masked, the power-down
sequence starts immediately. OC-detection is not maskable.
• The TPS65219-Q1 provides cycle-by-cycle current-limit on the buck converter outputs. If the device detects
over-current for tDEGLITCH_OC_short, respectively for tDEGLITCH_OC_long (configurable individually per rail with
EN_LONG_DEGL_FOR_OC_BUCKx in OC_DEGL_CONFIG register; applicable for rising-edge only), the
device sets INT_BUCK_1_2_IS_SET respectively INT_BUCK_3_IS_SET bit in INT_SOURCE register and bit
BUCKx_OC (for positive over-current) respectively BUCKx_NEG_OC (for negative over-current) in
INT_BUCK_1_2 respectively INT_BUCK_3 register.
During a voltage transition (for example, when triggered by a DVFS induced voltage change), the over
current detection is blanked and only gets activated when the voltage transition is completed.
If the over-current occurs during the sequence into ACTIVE state (from INITIALIZE or STBY), the device
disables the affected rail immediately and starts the power-down-sequence at the end of the current slot.
If the over-current occurs in ACTIVE-state or STBY-state, the device disables the affected rail immediately
and starts the power-down sequence.
OC-detection is not maskable, but the deglitch-time is configurable. It is strongly recommended to use
tDEGLITCH_OC_short. Extended over-current can lead to increased aging or overshoot upon recovery.
• The TPS65219-Q1 detects short-to-ground (SCG) faults on the buck-outputs. The reaction to the detection of
an SCG event is to set INT_BUCK_1_2_IS_SET respectively INT_BUCK_3_IS_SET bit in INT_SOURCE
register and bit BUCKx_SCG in INT_BUCK_1_2 respectively INT_BUCK_3 register. The affected rail is
disabled immediately. The device sequences down all outputs and transitions into the INITIALIZE state.
SCG-detection is not maskable.
If a rail gets enabled, the device blanks SCG detection initially to allow the rail to ramp above the SCG-
threshold.
• The TPS65219-Q1 detects residual voltage (RV) faults on the buck-outputs. The reaction to the detection of
an RV event is to set INT_RV_IS_SET bit in INT_SOURCE register and bit BUCKx_RV in INT_RV register.
The RV-detection is not maskable, but the nINT-reaction can be configured globally for all rails by
MASK_INT_FOR_RV in INT_MASK_WARM register. The BUCKx_RV-flag is set regardless of masking,
INT_RV_IS_SET bit is only set if nINT is asserted. The fault-reaction time and potential state-transition
depends on the situation when residual voltage is detected:
– If the device detects residual voltage during an ON-request in the INITIALIZE state, the device gates
power-up and the device remains in INITIALIZE state. If the RV-condition exists for more than 4 ms to 5
ms, the device sets BUCKx_RV-bit. If the RV-condition is not present any more, the device transitions to
ACTIVE state.
– If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or
STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.
– If the device detects residual voltage for more than 80 ms on any rail that was disabled during STBY state
during a request to leave STBY state, the device transitions into INITIALIZE state. The device sets the
BUCKx_RV-bit if the condition persists for 4 ms to 5 ms, but less than 80 ms.
– If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or
STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.
– If residual voltage is detected during an EN-command of the rail by I2C, the BUCKx_RV-flag is set
immediately, but no state transition occurs.
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• The buck converters have a local over-temperature sensor. The reaction to a temperature warning is
dependent on the configuration of the respective SENSOR_x_WARM_MASK bit in MASK_CONFIG register
and the MASK_EFFECT bits in INT_MASK_BUCKS register. If the temperature at the sensor exceeds
TWARM_Rising and is not masked, the device sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and
SENSOR_x_WARM bit in INT_SYSTEM register. In case the sensor detects a temperature exceeding
THOT_Rising , the converters power dissipation and junction temperature exceeds safe operating value. The
device powers down all active outputs immediately and sets INT_SYSTEM_IS_SET bit in INT_SOURCE
register and SENSOR_x_HOT bit in INT_SYSTEM register. The TPS65219-Q1 automatically recovers once
the temperature drops below the TWARM_Falling threshold value (or below the THOT_Falling threshold value in
case T_WARM is masked). The _HOT bit remains set and needs to be cleared by writing '1'. The HOT-
detection is not maskable.
CAUTION
The buck can only supply output currents up to the respective current limit, including during start-up.
Depending on the charge-current into the filter- and load-capacitance, the device potentially cannot
drive the full output current to the load while ramping. As a rule of thumb, for a total load-capacitance
exceeding 50 μF, the load current must not exceed 25% of the rated output current. This limit
applies also for dynamic output-voltage changes.
CAUTION
The TPS65219-Q1 does not offer differential feedback pins. The device does not support remote
sensing. Since a single-ended trace is susceptible to noise and must be as short as possible and
thus connect directly to the output filter.
表7-1. BUCK output voltage settings
BUCKx_VSET [decimal]
BUCKx_VSET [binary]
BUCKx_VSET [hexadecimal]
VOUT (Buck1 & Buck2 and
Buck3) [V]
0
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
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表7-1. BUCK output voltage settings (continued)
BUCKx_VSET [decimal]
BUCKx_VSET [binary]
BUCKx_VSET [hexadecimal]
VOUT (Buck1 & Buck2 and
Buck3) [V]
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.500
1.600
1.700
1.800
1.900
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.400
3.400
3.400
3.400
3.400
3.400
3.400
3.400
3.400
3.400
3.400
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7.3.5.1 Dual Random Spread Spectrum (DRSS)
The bucks provide a digital spread spectrum which reduces the EMI of the power supply over a wide frequency
range. Setting BUCK_SS_ENABLE to 1 enables the spread spectrum on all three bucks. Spread Spectrum is
only applicable if the bucks are configured for fixed frequency, BUCK_FF_ENABLE set to 1. The internal
modulator dithers the internal clock when the spread spectrum is enabled.
DRSS (a) combines a low-frequency triangular modulation profile (b) with a high frequency cycle-by-cycle
random modulation profile (c). The low frequency triangular modulation improves performance in lower radio
frequency bands (for example, the AM band), while the high frequency random modulation improves
performance in higher radio frequency bands (for example, the FM band). In addition, the frequency of the
triangular modulation is further modulated randomly to reduce the likelihood of any audible tones. To minimize
output voltage ripple caused by spread spectrum, duty cycle is modified on a cycle-by-cycle basis to maintain a
nearly constant duty cycle when dithering is enabled. See 图7-4 as an example of the modulation.
Frequency
(a) Low + High Frequency
fSW
Random Modulation
(b) Low Frequency
Random Modulation
(c) High Frequency
Random Modulation
Spread Spectrum
Enabled
Spread Spectrum
Disabled
图7-4. Dual Random Spread Spectrum
7.3.6 Linear Regulators (LDO1 through LDO4)
The TPS65219-Q1 offers a total of four linear regulators, where LDO1 and LDO2 share their properties and
LDO3 and LDO4 share theirs.
LDO1 and LDO2: 400 mA, 0.6 V .. 3.4 V
Both, LDO1 and LDO2 are general-purpose LDOs intended to provide power to analog circuitry on the SOC or
peripherals. The LDOs have an input voltage range from 1.5V to 5.5V, and can be connected either directly to
the system power or the output of a Buck converter. The output voltage is programmable in the range of 0.6V to
3.4V in 50mV-steps. Both LDOs support up to 400 mA. The LDOs can be configured in by-pass-mode, acting as
load-switches. If configured in bypass-mode, the desired output voltage still needs to be specified in
LDOx_VOUT register. The LDOs also support output-voltage changes while enabled, supporting functions like
SD-card-IO-supply, changing from 3.3V to 1.8V after initialization, either in LDO-mode at a supply-voltage above
3.3V or with a 3.3V supply changing between bypass-mode and LDO-mode. The LDOs also support Load-switch
mode (LSW_mode): in this case, output voltages of 1.5V up to 5.5V are supported. The desired voltage does not
need to be configured in the LDOx_VOUT register.
• In case of SD-card-supply, one of the LDOs can be controlled by the VSEL_SD/VSEL_DDR, configured as
VSEL_SD. Which LDO is controlled is selected by VSEL_RAIL bit in MFP_1_CONFIG register. The polarity
of the pin can be configured via VSEL_SD_POLARITY bit in MFP_1_CONFIG register.
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Alternatively, an I2C communication to VSEL_SD_I2C_CTRL in MFP_1_CONFIG register controls the
change of the output voltage. Therefore, even if VSEL_SD/VSEL_DDR pin is configured as VSEL_DDR, the
VSEL_RAIL bit still needs to be configured to define which LDO is affected by the I2C-command.
• The LDOs can be configured as linear regulators or operate in bypass-mode or be configured as a load-
switch (LSW-mode). The mode is configured by LDOx_LSW_CONFIG and LSW_BYP_CONFIG bits in
LDOx_VOUT register.
CAUTION
If an LDO is configured in bypass-mode, the output voltage must be configured and the PVIN_LDOx
supply voltage must match the configured output voltage. PVIN_LDOx voltage must be within
(configured VOUT) and (configured VOUT + 200mV). Violation of this can result in instability.
In bypass- or LSW-mode, the LDO acts as a switch, where VOUT is VIN minus the drop over the
FET-resistance (RBYPASS, RLSW).
Output Capacitance Requirements
The LDO regulators require sufficient output-capacitance for stability. The required minimum and supported
maximum capacitance depends on the configuration:
• in LDO-mode, a minimum capacitance of 1.6 uF is required and a maximum total load capacitance (output
filter and point-of-load combined) of 20 uF is supported
• in LSW- or bypass-mode, a minimum capacitance of 1.6 uF is required and a maximum total capacitance
(output filter and point-of-load combined) of 50 uF is supported
LDO3 and LDO4: 300 mA, 1.2 V .. 3.3 V
Both, LDO3 and LDO4 are general-purpose LDOs intended to provide power to analog circuitry on the SoC or
peripherals. The LDOs have an input voltage range from 2.2 V to 5.5 V, and can be connected either directly to
the system power or the output of a Buck converter. Note, these LDOs need a headroom between VSYS and the
LDO-output voltage of minimum 150 mV. The output voltage is programmable in the range of 1.2 V to 3.3 V in 50
mV-steps. Both LDOs support up to 300 mA. The LDOs can be configured to act as load-switches. In this case,
output voltages of 2.2 V up to 5.5 V are supported. The desired voltage does not need to be configured in the
LDOx_VOUT register.
These LDOs support a fast-ramp-mode with limited output capacitance and a slow-ramp-mode, allowing for
larger total load capacitance.
Output Capacitance Requirements
The LDO regulators require sufficient output-capacitance for stability. The required minimum and supported
maximum capacitance depends on the configuration:
• for slow-ramp LDO-mode or LSW-mode, a minimum capacitance of 1.6 uF is required and a maximum total
capacitance (output filter and point-of-load combined) of 30 uF is supported
• for fast-ramp LDO-mode or LSW-mode, a minimum capacitance of 1.6 uF is required and a maximum total
capacitance (output filter and point-of-load combined) of 15 uF is supported
LDO1, LDO2, LDO3 and LDO4
• The ON/OFF state of the LDOs in ACTIVE state is controlled by the corresponding LDOx_EN bit in the
ENABLE_CTRL register.
• The ON/OFF state of the LDOs in STBY state is controlled by the corresponding LDOx_STBY_EN bit in the
STBY_1_CONFIG register.
• In INITIALIZE state, the LDOs are off, regardless of bit-settings.
CAUTION
In case of linear regulators that are not to be used at all, the VLDOx pin must be left floating.
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• Each of the LDOs can be configured as linear regulators or be configured as a load-switch (LSW-mode).
LDO1 and LDO2 can also operate in bypass-mode. The mode is configured by LDOx_LSW_CONFIG and
LSW_BYP_CONFIG bits in LDOx_VOUT register individually per regulator.
CAUTION
A mode change between LDO(/bypass) and LSW-mode must only be performed, when the
regulator is disabled!
(A change between LDO and bypass-mode (supported by LDO1 and LDO2 only) is supported
during operation.)
• The LDOs have an active discharge function. Whenever LDOx is disabled, the output is discharged to
ground. The discharge function can be disabled individually per rail in the DISCHARGE_CONFIG register.
• Prior to a sequence into ACTIVE state (from INITIALIZE or STBY state), the device discharges the disabled
rails regardless of the discharge-configuration to avoid starting into a pre-biased output.
• If a rail is enabled by an I2C-command, active discharge is not enforced, but the rail is only enabled if the
output voltage is below the SCG-threshold.
• This register is not EEPROM-backed and is reset if the device enters OFF-state.
• When in INITIALIZE state (during RESET or an I2C-OFF-request), the discharge configuration is not reset.
Note: the power-down-sequence can be violated if the discharge function is disabled
LDO Fault Handling
• The TPS65219-Q1 detects under-voltages on the LDO-outputs. The reaction to the detection of an under-
voltage is dependent on the configuration of the LDOx_UV_MASK bit in INT_MASK_LDOS register and the
MASK_EFFECT in INT_MASK_BUCKS register. If not masked, the device sets bit INT_LDO_1_2_IS_SET
respectively INT_LDO_3_4_IS_SET bit in INT_SOURCE register and bit LDOx_UV in INT_LDO_1_2 register
respectively INT_LDO_3_4 register.
During a voltage transition (at power-up or triggered by toggling VSEL_SD-pin or an I2C-command), the
device blanks the undervoltage detection by default and activates the undervoltage detection when the
voltage transition completed.
If the device detects an undervoltage during the sequence into ACTIVE state (from INITIALIZE or STBY) and
UV is not masked, the power-down-sequence starts at the end of the current slot.
If the device detects an undervoltage in ACTIVE-state or STBY-state and UV is not masked, the power-down
sequence starts immediately. OC-detection is not maskable.
CAUTION
If a LDO is configured in bypass-mode or LSW-mode, UV-detection is not supported.
• The TPS65219-Q1 provides current-limit on the LDO-outputs. If the PMIC detects over-current for
tDEGLITCH_OC_short, respectively for tDEGLITCH_OC_long (configurable individually per rail with
EN_LONG_DEGL_FOR_OC_LDOx in OC_DEGL_CONFIG register; applicable for rising-edge only), the
device sets INT_LDO_1_2_IS_SET respectively INT_LDO_3_4_IS_SET bit in INT_SOURCE register and bit
LDOx_OC in INT_LDO_1_2 respectively INT_LDO_3_4 register. The effected rail is disabled immediately.
During a voltage transition (at power-up or triggered by toggling VSEL_SD-pin or an I2C-command), the
overcurrent detection is blanked and gets activated when the voltage transition completed.
If the over-current occurs during the sequence into ACTIVE state (from INITIALIZE or STBY), the device
disables the affected rail immediately and starts the power-down-sequence at the end of the current slot.
If the over-current occurs in ACTIVE-state or STBY-state, the device disables the affected rail immediately
and starts the power-down sequence.
OC-detection is not maskable, but the deglitch-time is configurable. It is strongly recommended to use
tDEGLITCH_OC_short. Extended over-current can lead to increased aging or overshoot upon recovery.
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• The TPS65219-Q1 detects short-to-ground (SCG) faults on the LDO-outputs. The reaction to the detection of
an SCG event is to set INT_LDO_1_2_IS_SET respectively INT_LDO_3_4_IS_SET bit in INT_SOURCE
register and bit LDOx_SCG in INT_LDO_1_2 register respectively INT_LDO_3_4 register. The affected rail is
disabled immediately. The device sequences down all outputs and transitions into INTIALIZE state.
SCG-detection is not maskable.
If a rail gets enabled, the device blanks SCG detection initially to allow the rail to ramp above the SCG-
threshold.
• The TPS65219-Q1 detects residual voltage (RV) faults on the LDO-outputs. The reaction to the detection of
an RV event is to set INT_RV_IS_SET bit in INT_SOURCE register and bit LDOx_RV in INT_RV register.
The RV-detection is not maskable, but the nINT-reaction can be configured globally for all rails by
MASK_INT_FOR_RV in INT_MASK_WARM register. The device sets the LDOx_RV-flag regardless of
masking, INT_RV_IS_SET bit is only set if nINT is asserted. The fault-reaction time and potential state-
transition depends on the situation when the faults are detected:
– If the device detects residual voltage during an ON-request in the INITIALIZE state, the PMIC gates
power-up and the device remains in INITIALIZE state. If the RV-condition is detected for more than 4 ms
to 5 ms, the device sets the LDOx_RV-bit but remains in INITIALIZE state as long as the RV-condition
exists. If the RV-condition is not present any more, the device transitions to ACTIVE state, provided the
ON-request is still valid.
– If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or
STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.
– If the device detects residual voltage for more than 80 ms on any rail that was disabled during STBY state
during a request to leave STBY state, the device transitions into INITIALIZE state. The device sets the
LDOx_RV-bit if the condition persists for 4 ms to 5 ms, but less than 80 ms.
– If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or
STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.
– If the device detects residual voltage during an EN-command of the rail by I2C, the LDOx_RV-bit is set
immediately, but no state transition occurs.
• The LDOs have a local over-temperature sensor. The reaction to a temperature warning is dependent on the
configuration of the respective SENSOR_x_WARM_MASK bit in and the MASK_EFFECT bit in
INT_MASK_BUCKS register. If the temperature at the sensor exceeds TWARM_Rising and is not masked, the
device sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and SENSOR_x_WARM bit in INT_SYSTEM
register. In case the sensor detects a temperature exceeding THOT_Rising , the converters power dissipation
and junction temperature exceeds safe operating value. The device powers down all active outputs
immediately and sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and SENSOR_x_HOT bit in
INT_SYSTEM register. The TPS65219-Q1 automatically recovers once the temperature drops below the
TWARM_FAlling threshold value (or below the THOT_FAlling threshold value in case T_WARM is masked). The
_HOT bit remains set and needs to be cleared by writing '1'. The HOT-detection is not maskable.
表7-2. LDO output voltage settings
LDOx_ VSET
[decimal]
LDOx_VSET [binary] LDOx_ VSET [hexa- VOUT (LDO1 and
VOUT (LDO1 and
LDO2, bypass-
mode) [V]
VOUT (LDO3 and
LDO4, LDO mode)
[V]
decimal]
LDO2, LDO mode)
[V]
0
1
2
3
4
5
6
7
000000
000001
000010
000011
000100
000101
000110
000111
00
01
02
03
04
05
06
07
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
1.20
1.20
1.20
1.20
1.20
1.20
1.20
1.20
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表7-2. LDO output voltage settings (continued)
LDOx_ VSET
[decimal]
LDOx_VSET [binary] LDOx_ VSET [hexa- VOUT (LDO1 and
VOUT (LDO1 and
LDO2, bypass-
mode) [V]
VOUT (LDO3 and
LDO4, LDO mode)
[V]
decimal]
LDO2, LDO mode)
[V]
8
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
08
09
0A
0B
0C
0D
0E
0F
10
11
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
1.50
1.20
1.20
1.20
1.20
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
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表7-2. LDO output voltage settings (continued)
LDOx_ VSET
[decimal]
LDOx_VSET [binary] LDOx_ VSET [hexa- VOUT (LDO1 and
VOUT (LDO1 and
LDO2, bypass-
mode) [V]
VOUT (LDO3 and
LDO4, LDO mode)
[V]
decimal]
LDO2, LDO mode)
[V]
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.40
3.40
3.40
3.40
3.40
3.40
3.40
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.40
3.40
3.40
3.40
3.40
3.40
3.40
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
7.3.7 Interrupt Pin (nINT)
During power-up, the output of the nINT pin does depend on whether any INT_SOURCE flags are set and the
configuration of the MASK_EFFECT bit in INT_MASK_BUCKS register-. If one or more flags are set, then nINT
pin is pulled low and is only released high after those flags have been cleared by writing ‘1’ to them. Note,
the nINT-pin can only transition 'high' if a VIO-voltage for the pull-up is available.
In ACTIVE or STBY state, the nINT pin signals any event or fault condition to the host processor. Whenever a
fault or event occurs in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output
is driven low. In case the device transitions to INITIALIZE state, the nINT pin is pulled low as well, regardless if
the transition is triggered by an OFF-request or a fault.
If the fault is no longer present, a W1C (write '1' to clear) needs to be performed on the failure bits. This
command also allows the nINT-pin to release (return to Hi-Z state).
If a failure persists, the corresponding bit remains set and the INT pin remains low.
The UV-faults can be individually masked per rail in INT_MASK_UV registers. The thermal sensors can
individually be masked by SENSOR_x_WARM_MASK in the MASK_CONFIG register. The effect of the masking
for UV and WARM is defined globally by MASK_EFFECT bits in MASK_CONFIG register.
The nINT reaction for RV-faults is defined globally by MASK_INT_FOR_RV bits in MASK_CONFIG register.
• 00b = no state change, no nINT reaction, no bit set
• 01b = no state change, no nINT reaction, bit set
• 10b = no state change, nINT reaction, bit set (same as 11b)
• 11b = no state change, nINT reaction, bit set (same as 10b)
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CAUTION
Masking poses a risk to the device or the system. In case the masking is performed by I2C-
command, the masking bits do get reset to EEPROM-based default after transitioning to INITIALIZE
state. Bits corresponding to faults newly configured via I2C as SD-faults do not get cleared.
It is strongly discouraged to mask OC- and UV-detection on the same rail.
7.3.8 PWM/PFM and Low Power Modes (MODE/STBY)
The TPS65219-Q1 supports low power modes through the I2C-control or through the MODE/STBY pin. The
configuration of the pin is selected by MODE_STBY_CONFIG in MFP_2_CONFIG register. The polarity of this
pin can be configured by writing to MODE_STBY_POLARITY in MFP_1_CONFIG register. The polarity-
configuration must not change after power-up. Only either MODE/RESET or MODE/STBY must be configured as
MODE. If both are configured as MODE, MODE/RESET takes priority and MODE/STBY is ignored.
MODE/STBY configured as 'MODE':
• If configured as 'MODE', the pin-status determines the switching-mode of the buck-converters. This selection
is only applicable in quasi-fixed-frequency mode.
• Forcing this pin for longer than tDEGLITCH_MFP forces the buck-regulators into PWM-mode (irrespective of load
current). De-asserting this pin low allows the buck regulators to enter PFM-mode. The entry into PFM and
exit from PFM is governed by the load current. Only one pin, either MODE/STBY or MODE/RESET must be
configured as 'MODE'.
• The selection of auto-PFM/forced-PWM can also be controlled by writing to the bit MODE_I2C_CTRL in
MFP_1_CONFIG register.
• A change of the MODE does not cause a state-transition.
• During power-up of any one of the three bucks, a MODE change is blanked on this rail and only takes effect
after the ramp completed.
MODE/STBY configured as 'STBY':
• Forcing this pin for longer than tDEGLITCH_MFP sequences down the rails selected to turn off in the
STBY_1_CONFIG respectively the STBY_2_CONFIG register. De-asserting this pin sequences the selected
rails on again.
• A transition into and out of STBY state can also be controlled by writing to the bit STBY_I2C_CTRL in
MFP_CTRL register, provided I2C communication is supported during STBY state.
• A change of the MODE/STBY pin configured as 'STBY' does cause a state-transition by definition.
• Regardless of the pin-setting, the device always powers up into ACTIVE state. The device reacts to the
STBY-pin-state or I2C-commands only after entering ACTIVE state.
MODE/STBY configured as 'MODE & STBY':
• The pin can be configured to perform both functions, MODE and STBY simultaneously
• Forcing this pin for longer than tDEGLITCH_MFP sequences down the rails selected to turn off in the
STBY_1_CONFIG respectively the STBY_2_CONFIG register and allows auto-PFM entry (only applicable in
quasi-fixed-frequency mode). De-asserting this pin sequences the selected rails on again and forces the
buck-regulators to forced-PWM. Polarity settings need to be harmonized for this configuration.
• If a transition into and out of STBY state is commanded by writing to the bit STBY_I2C_CTRL in MFP_CTRL
register (provided I2C communication is supported during STBY state), a separate command for the MODE-
change is required by writing to the bit MODE_I2C_CTRL in MFP_1_CONFIG register.
• A change of the MODE/STBY pin configured as 'MODE&STBY' does cause a state-transition by definition.
• By default STBY is deasserted and the pin is ignored until the device completed the power-up-sequence.
During power-up of any one of the three bucks, a MODE-change is blanked on this rail and only takes effect
after the ramp completed. A state-change commanded by STBY-pin is reacted to even during the ramp of
rails (except during INITIALIZE-to-ACTIVE transition).
Please see the truth-table for pin- and I2C-commands in Section PWM/PFM and Reset (MODE/RESET)
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7.3.9 PWM/PFM and Reset (MODE/RESET)
This pin can be configured as an alternative MODE pin (in case MODE/STBY is configured for STBY-function) or
as a RESET pin. The configuration of the pin is selected by MODE_RESET_CONFIG in MFP_2_CONFIG
register. The polarity of this pin can be configured by writing to MODE_RESET_POLARITY in MFP_1_CONFIG
register. The polarity-configuration must not change after power-up. Only MODE/RESET or MODE/STBY must
be configured as MODE. If both are configured as MODE, MODE/RESET takes priority and MODE/STBY is
ignored.
MODE/RESET configured as 'MODE':
• If configured as 'MODE', the pin-status determines the switching-mode of the buck-converters. This selection
is only applicable in quasi-fixed-frequency mode.
• Forcing this pin for longer than tDEGLITCH_MFP forces the buck-regulators into PWM-mode (irrespective of load
current). De-asserting this pin low allows the buck regulators to enter PFM-mode. The entry into PFM and
exit from PFM is governed by the load current. Only one pin, either MODE/STBY or MODE/RESET must be
configured as 'MODE'.
• The selection of auto-PFM/forced-PWM can also be controlled by writing to the bit MODE_I2C_CTRL in
MFP_1_CONFIG register.
• A change of the MODE does not cause a state-transition.
• During power-up of any one of the three bucks, a MODE-change is blanked on this rail and only takes effect
after the ramp completed.
MODE/RESET configured as 'RESET':
• In RESET configuration, this pin is edge sensitive, but still applies the deglitch time. Consequently, toggling
this pin and holding the pin for longer than tDEGLITCH_RESET causes a reset.
• By default, RESET is deasserted and RESET requests, via pin or I2C, are only serviced if the device is in
ACTIVE state, STBY state, or transitions between these 2 states.
• The TPS65219-Q1 supports WARM or COLD reset. The configuration is made by bit
WARM_COLD_RESET_CONFIG in MFP_2_CONFIG register.
– If configured for COLD reset, the device executes the power down sequence and transitions to INITIALIZE
state. Then, EEPROM is reloaded and rails power-up again in normal power-up-sequence, provided there
are no faults and no OFF-request. The execution of a COLD-reset sets the bit COLD_RESET_ISSUED in
POWER_UP_STATUS_REG register. The read-out of this bit allows to track if a COLD-reset was
performed. The bit gets set regardless if the reset was commanded by I2C or by the pin. The nINT-pin
does not toggle based on this bit. Write W1C to clear the bit.
– If configured for WARM reset, all enabled rails remain on, but the output voltage of rails that support
dynamic voltage change is reset to the boot-voltage. Specifically, following configurations get reset to their
boot-value: BUCK1_VSET, BUCK2_VSET, BUCK3_VSET, LDO1_VSET, LDO2_VSET,
LDO1_BYP_CONFIG, LDO2_BYP_CONFIG and VSEL_SD_I2C_CTRL.
All other bits, even in the same register, remain at their current state. For example, LDOx_LSW_CONFIG,
BUCKx_BW_SEL, BUCKx_UV_THR_SEL and the MFP_1_CONFIG register bits do NOT get reset during
a WARM-reset.
WARM Reset cannot override the VSEL_SD-pin command. In other words: even if a WARM Reset occurs,
if the VSEL_SD pin is commanding 1.8V-LDO mode, that remain in effect.
• A reset can also be triggered by writing to the bit WARM_RESET_I2C_CTRL respectively the bit
COLD_RESET_I2C_CTRL in MFP_CTRL register.
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备注
Shut-down-faults and OFF-requests take priority over a RESET-request. If a RESET-requests occurs
simultaneously with one of those, the device enters INITIALIZE state and requires a new ON-request
to start up.
Reset requests, via pin or I2c, are only serviced in ACTIVE state, STBY state, or a transition between
these two states.
Please see below truth-table for pin- and I2C-commands.
表7-3. MODE/STBY configuration
Pin Name
Pin Configuration
Pin Polarity
Pin state
I2C control
Resulting Function
(MODE_STBY_CON (MODE_STBY_POL (schematic)
(MODE_I2C_CTRL)
FIG)
ARITY)
MODE/STBY
MODE/STBY
MODE/STBY
MODE/STBY
MODE/STBY
MODE/STBY
MODE/STBY
MODE/STBY
MODE/STBY
MODE
MODE
MODE
MODE
MODE
STBY
STBY
STBY
STBY
x
x
1h
0h
0h
0h
0h
x
forced PWM
auto-PFM
forced PWM
forced PWM
auto-PFM
STBY
0h
0h
1h
1h
0
L
H
L
H
L
0
H
L
x
ACTIVE
1
x
ACTIVE
1
H
x
STBY
表7-4. MODE/RESET configuration
Pin Name
Pin Configuration
Pin Polarity
Pin state
I2C control
Resulting Function
(MODE_RESET_CO (MODE_RESET_POL (schematic)
(MODE_I2C_CTRL)
NFIG)
ARIT Y)
MODE/RESET
MODE/RESET
MODE/RESET
MODE/RESET
MODE/RESET
MODE/RESET
MODE/RESET
MODE/RESET
MODE/RESET
MODE*
MODE*
MODE*
MODE*
MODE*
RESET
RESET
RESET
RESET
x
x
1h
0h
0h
0h
0h
x
forced PWM
auto-PFM
0h
0h
1h
1h
0
L
H
L
forced PWM
forced PWM
auto-PFM
H
L
RESET
0
H
L
x
normal operation
normal operation
RESET
1
x
1
H
x
The * for MODE indicates that the MODE/RESET pin takes priority in case both, MODE/RESET and MODE/
STBY are configured as 'MODE', and thus the respective pin to be observed is MODE/RESET.
7.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
The function of this pin is configured by VSEL_DDR_SD in MFP_1_CONFIG.
When configured as VSEL_SD, the bit VSEL_RAIL in MFP_1_CONFIG register selects LDO1 or LDO2 to be
controlled by the pin. The configuration must not change after power-up.
VSEL_SD/VSEL_DDR configured as 'VSEL_SD': SD-card-IO-select:
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The polarity of this pin can be configured by writing to VSEL_SD_POLARITY in MFP_1_CONFIG register.
Toggling the pin changes the output voltage of the selected LDO between hard-coded 1.8 V and the voltage
configured in LDOx_VOUT. For the SD-card-IO-supply, LDOx_VOUT must be configured for 3.3 V. A change of
the VSEL_SD status does not cause a state-transition.
CAUTION
In SD-card-configuration, customer must configure the pin-polarity and drive the pin so that the LDO
delivers 3.3 V at start-up.
VSEL_SD/VSEL_DDR configured as 'VSEL_DDR':
Pulling this pin high sets the output voltage of Buck3 to 1.35 V (DDR3LV), leaving the pin floating sets the output
voltage of Buck3 to 1.2 V (DDR4, LP-DDR3, some LP-DDR2), pulling the pin low sets the output voltage of the
Buck3 voltage configured in BUCK3_VOUT. For LP-DDR4, BUCK3_VOUT must be configured to 1.1 V.
CAUTION
This function needs to be hard-wired and must not change during operation.
CAUTION
The VSEL_RAIL still needs to be configured for the LDO that supplies the SD-card-IO-voltage, as an
I2C-command toggles the selected LDO-rail for the SD-card. The VSEL_SD_POLARITY bit has no
effect if the pin is configured as VSEL_DDR.
The Table below shows the various combinations.
表7-5. VSEL_SD/VSEL_DDR configuration options
PIN state
(schematic)
I2C control
(VSEL_SD_I2C_
Resulting Function
Pin Configuration Pin Polarity
Rail selection
(VSEL_RAIL)
(VSEL_DDR_SD)
(VSEL_SD_POLARITY)
CTRL)
0:DDR
n/a
n/a
n/a
0 =LDO1
1=LDO2
L
0h: LDOx = 1.8V BUCK3 = Buck3_VSET
1h: LDOx =
(needed for I2C
control)
LDOx_VSET
0:DDR
0:DDR
0 =LDO1
1=LDO2
open
H
0h: LDOx = 1.8V BUCK3 = 1.2V
1h: LDOx =
(needed for I2C
control)
LDOx_VSET
0 =LDO1
1=LDO2
0h: LDOx = 1.8V BUCK3 = 1.35
1h: LDOx =
(needed for I2C
control)
LDOx_VSET
1:SD
1:SD
1:SD
1:SD
1:SD
1:SD
1:SD
1:SD
0
0
1
1
0
0
1
1
0 =LDO1
0 =LDO1
0 =LDO1
0 =LDO1
1 =LDO2
1 =LDO2
1 =LDO2
1 =LDO2
L
x
x
x
x
x
x
x
x
LDO1 = 1.8 V
H
L
LDO1 = LDO1_VSET
LDO1 = LDO1_VSET
LDO1 = 1.8 V
H
L
LDO2 = 1.8 V
H
L
LDO2 = LDO2_VSET
LDO2 = LDO2_VSET
LDO2 = 1.8 V
H
7.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
GPO1 and GPO2 pins are always configured as an output.
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The GPIO-pin is an input/output, however, the input-functionality is only used in multi-PMIC configuration. In
single-PMIC configuration, the pin can be used as an output. The state can be read by polling the bit
GPIO_STATUS bit in MFP_CTRL register.
The I/O-configuration of the GPIO-pin is done by the MULTI_DEVICE_ENABLE bit in MFP_1_CONFIG register.
If configured as outputs, these pins can be used to sequence external rails. The GP(I)Os can be included in the
sequence or be controlled via I2C-interface, writing to GPOx_EN respectively GPIO_EN bit in
GENERAL_CONFIG register. The GPO is released high if activated.
The GPIO function is to be used if multiple TPS65219-Q1 need to be synchronized, in case more rails need to
be supplied. See application section on usage. See section "Multi-PMIC operation" for details.
The polarity of these pins is not changeable.
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7.3.12 I2C-Compatible Interface
The default I2C1 7-bit device address of the TPS65219-Q1 is set to 0x30 (0b0110000 in binary), but can be
changed if needed, for example for multi-PMIC-operation.
The I2C-compatible synchronous serial interface provides access to the configurable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the devices
connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL).
Every device on the bus is assigned a unique address and acts as either a controller or a target depending on
whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor
placed somewhere on the line and remain HIGH even when the bus is idle. The TPS65219-Q1 supports
standard mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V.
7.3.12.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
change
allowed
data
change
allowed
data
valid
data
valid
图7-5. Data Validity Diagram
7.3.12.2 Start and Stop Conditions
The device is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning
and end of the I2C session. A START condition is defined as the SDA signal going from HIGH to LOW while the
SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL
signal is HIGH. The I2C controller device always generates the START and STOP conditions.
SDA
SCL
S
P
START
STOP
Condition
Condition
图7-6. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C controller
device can generate repeated START conditions during data transmission. A START and a repeated START
condition are equivalent function-wise. 图 7-7 shows the SDA and SCL signal timing for the I2C-compatible bus.
For timing values, see the Specification section.
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tBUF
SDA
tHD;STA
trCL
tfDA
trDA
tSP
tLOW
tfCL
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
tHD;DAT
S
tSU;DAT
S
RS
P
START
REPEATED
START
STOP
START
图7-7. I2C-Compatible Timing
7.3.12.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse.
The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates
an acknowledge after each byte has been received.
There is one exception to the acknowledge after every byte rule. When the controller device is the receiver, it
must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte
clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse
(generated by the controller device), but the SDA line is not pulled down.
After the START condition, the bus controller device sends a chip address. This address is seven bits long
followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a
WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third
byte contains data to write to the selected register. 图 7-8 shows an example bit format of device address
110000-Bin = 60Hex.
MSB
LSB
1
1
0
0
0
0
0
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Address (chip address)
图7-8. Example Device Address
START
ACK
ACK
ACK STOP
I2C_ID[7:1]
0
ADDR[7:0]
WDATA[7:0]
STOP
SCL
SDA
0x60
0x36
0x16
图7-9. I2C Write Cycle without CRC
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REPEATED
START
STOP
START
ACK
ACK
ACK
NCK
I2C_ID[7:1]
0
ADDR[7:0]
I2C_ID[7:1]
1
RDATA[7:0]
STOP
SCL
0x60
0x36
0x60
0x16
SDA
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
图7-10. I2C Read Cycle without CRC
7.4 Device Functional Modes
OFF
Outputs OFF
From any state:
VSYS < VSYSPOR_Falling ||
VDD1P8 fault
(immediate shut down)
ON_Requests:
(PB = ‘low’ for t > tPB_ON) ||
(EN = ‘high’) ||
(VSENSE > VVSENSE && EN = ‘high’)
Monitors off
nRSTOUT
nINT = ‘0’
OFF_Requests:
(PB = ‘low’ for t = tPB_OFF) ||
(EN = ‘low’) ||
(VSENSE < VVSENSE) ||
(RESET = ‘low’) ||
VSYS > VSYSPOR_Rising
!VDD1P8 fault
&
(OFF-request by I2C)
INITIALIZE
From any state or
during transitions:
(OFF_Request) ||
(RESET = low’) 1)
(SD-fault) 1)
(sequencing down)
(HOT = ‘1’)
(ìmmediate shut-down)
Outputs OFF
SD_Faults:
(VSYS > VSYSOVP) ||
(SCG = ‘1’) ||
Monitors off 2)
nRSTOUT
(UV = ‘1’) *)||
(WARM = ‘1’) *)
(OC = ‘1’) ||
nINT =Fault- & Mask-
dependent
if VIO
is present
(HOT = ‘1’) ||
(RV_SD = ‘1’) ||
(TIMEOUT = ‘1’)
(
*) unless masked)
Changes to the following bits or pins do not
(necessarily) cause a state-transition:
MODE, VSEL_SD/VSEL_DDR, enabling or
disabling of rails
Configuration dependent
(ON_Request) &
!(SD_fault) &
all rails discharged
(sequencing up)
TIMEOUT
(sequencing down
remaining active rails)
TIMEOUT
(sequencing down)
!STBY-request (polarity configurable)
(sequencing up select rails)
STBY
Selected
Outputs ON
TIMEOUT
(sequencing down)
ACTIVE
Outputs ON
All Monitors on
nRSTOUT
nINT =
Fault- & Mask-
dependent
All Monitors on,
nRSTOUT = ‘1’
nINT =
Fault- & Mask-
dependent
STBY-request (polarity configurable)
(sequencing down select rails)
1) in case of a RESET or a SD-fault, the device transi ons from INITIALIZE state to the ACTIVE state without a new
Push-bu on-ON_Request. In EN or VSENSE con gura on, the ON-request must s ll be valid to transi on to ACTIVE state.
2) If INITIALIZE state was entered due to a Thermal-Shut-Down, the temperature monitors remain ac ve un l the
temperature on all sensors fell below TWARM threshold. Thermal-Shut-Down causes immediate shut-shutdown,
no sequencing down
图7-11. State diagram
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7.4.1 Modes of Operation
7.4.1.1 OFF State
In OFF state, the PMIC is insufficiently supplied. Neither internal logic nor external rails are available. If VSYS
exceeds VSYS_POR voltage and the internal 1.8V-rail (VDD1P8) is in regulation, the device enters the
INITIALIZE state.
7.4.1.2 INITIALIZE State
In INITIALIZE state, the device is completely shut down with the exception of a few circuits to monitor the
EN/PB/VSENSE input. Whenever entering the INITIALIZE state, the PMIC reads the memory and loads the
registers to their EEPROM-default values. The I2C communication interface is turned off .
Entry to INITIALIZE state is gated if any one of the thermal sensors is above the TWARM_Rising threshold and
WARM-detection is not masked.
The EEPROM loading takes approximately 2.3 ms. The power-up sequence can only execute after the
EEPROM-load and if all rails are discharged below the VBUCKx_SCG_TH respectively VLDOx_SCG_TH threshold.
If INITIALIZE state was entered from OFF state, bit POWER_UP_FROM_OFF in POWER_UP_STATUS_REG
register is set and remains set until a write-1-clear is issued. Read-out of this bit allows to determine if INITIALZE
state was entered from OFF state or due to a Shut-down-fault or OFF-request.
In INITIALIZE state, the nINT pin status is dependent if faults are and masking thereof. If no faults are present or
nINT-reaction for those are masked, nINT-pin is pulled high, provided a VIO-voltage for the pull-up is available.
To transition from the INITIALIZE state to the ACTIVE state, one of the ON-requests must occur:
• The EN input is 'high' (if EN/PB/VSENSE is configured as 'EN' or 'VSENSE')
• The PB input is pulled low for at least tPB_ON_SLOW respectively tPB_ON_FAST (if EN/PB/VSENSE is configured
as 'PB')
备注
The DISCHARGE_CONFIG register is purposefully omitted from RESET when entering INITIALIZE
state from ACTIVE or STBY state. When entering INITIALIZE state from OFF state, the EEPROM
content is loaded. If the discharge configuration changed after power-up, a different start-up behavior
can occur, depending if the INITIALIZE state was entered from OFF state or from ACTIVE/STBY.
7.4.1.3 ACTIVE State
The ACTIVE state is the normal mode of operation when the system is up and running. All enabled bucks
converters and LDOs are operational and can be controlled through the I2C interface. After a wake-up event, the
PMIC discharges potential residual voltages on the outputs, regardless of the discharge-configuration. ACTIVE
state can also be directly entered from STBY state by de-asserting the STBY pin high or by an I2C command.
See STBY state description for details. To transition to STBY, the STBY pin must be forced or an I2C command
to STBY_I2C_CTRL in MFP_CTRL register must be issued.
To transition to INITIALIZE state, one of the following OFF_Requests must occur:
• The EN input is 'low' (if EN/PB/VSENSE is configured as 'EN' or 'VSENSE')
• The PB input is pulled low for at least tPB_OFF (if EN/PB/VSENSE is configured as 'PB')
• An I2C OFF-request is issued
If a shut-down-fault (SD_Fault) occurs while in the ACTIVE state, TPS65219-Q1 sequences down the active
outputs and transition to the INITIALIZE state. The device does transition to ACTIVE state without a new
Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to
ACTIVE state.
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7.4.1.4 STBY State
STBY state is a low-power mode of operation intended to support system standby. The mode can be entered by
the MODE/STBY pin, if configured as 'STBY' or by an I2C-command to STBY_I2C_CTRL in MFP_CTRL
register. Typically, the majority of power rails are turned off with the exception of rails required by the SoC during
this state. Which rails power down in STBY state can be configured in STBY_1_CONFIG and STBY_2_CONFIG
register.
The monitoring functions are all available: Under-voltage- (UV), Short-to-GND- (SCG) and Over-current- (OC)
detection, thermal warning (WARM) and thermal-shutdown (TSD/HOT) remain active.
The device enters ACTIVE state if STBY is de-asserted or an I2C command is received (provided VIO-supply
remained active). Before starting the STBY to ACTIVE sequence, disabled rails are discharged. In case this fails
to complete within 80 ms, the device also runs into a timeout-condition and transitions to INITIALIZE state. The
device sets bit TIMEOUT in the INT_TIMEOUT_RV_SD register and the fault flags for the rail that caused the
shut-down.
The sequence into and out of STBY state is the same as for power-down respectively for power-up. Rails that
remain on in STBY are skipped, but their respective slots are still executed.
CAUTION
The device cannot transition from INITIALIZE state to STBY state directly, it must first enter ACTIVE
state.
CAUTION
Only rails that were enabled in ACTIVE state can remain enabled in STBY. Previously disabled rails
cannot be turned on in STBY-state. Activity in STBY-state requires a AND-combination of
LDOx_EN / BUCKx_EN and LDOx_STBY_EN/BUCKx_STBY_EN.
CAUTION
Do not change the registers related to an ongoing sequence by I2C-command!
Non-NVM-bits are not accessible for ~80 us after starting a transition into INITIALIZE state.
7.4.1.5 Fault Handling
Detectable Faults
The TPS65219-Q1 offers various fault-detections. Per default, all of them lead to a sequenced shut-down. Some
of them are maskable and the reaction to masked faults is configurable.
The device provides the following fault-detections on the supply voltage (VSYS) and internal voltage supply
(VDD1P8):
• Undervoltage on VSYS, resulting in transition to OFF state or gating start-up
• Overvoltage-protection on VSYS, resulting in transition to OFF state
• Under- or Overvoltage on internal 1.8V-supply (VDD1P8), resulting in transition to OFF state or gating start-
up.
None of these faults are maskable.
The TPS65219-Q1 provides the following fault-detections on the buck- and LDO-outputs:
• Undervoltage detection (UV)
• Over Current detection (OC), triggering on positive as well as (for buck-converters) negative current-limit
• Short-to-GND detection (SCG)
• Temperature warning (WARM) and Thermal Shut Down (TSD / HOT)
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• Residual Voltage (RV) and Residual Voltage - Shutdown (RV_SD)
• Timeout (TO)
SCG, OC, HOT, RV_SD and TO are not maskable. If any one of those occurs, the device powers down. Positive
and negative current limit share the same mask-bit per regulator.
The reaction to UV, RV and WARM faults is configurable. If not masked, a fault triggers a sequenced shut-down.
UV, RV and WARM can be masked individually per regulator in INT_MASK_BUCKS, INT_MASK_LDOS and
INT_MASK_WARM registers. No state-transition occurs in case of a masked fault. Whether bits are set and if
nINT is pulled low can be configured globally by MASK_EFFECT bits in MASK_CONFIG register. Positive and
negative current limit share the same mask-bit per regulator.
• 00b = no state change, no nINT reaction, no bit set
• 01b = no state change, no nINT reaction, bit set
• 10b = no state change, nINT reaction, bit set (same as 11b)
• 11b = no state change, nINT reaction, bit set (same as 10b)
For any fault that corresponds to a shut-down condition, the fault-bit remains asserted until a W1C (write-one-
clear) operation is performed via I2C (assuming the fault is not present any more). In case of a shut-down fault,
no renewed on-request is required. The device automatically executes the power up sequence if the fault is no
longer present as long as EN/VSENSE is still high and no PB-press is required for a restart.
For any fault that is not a shut-down condition (for example because the fault is masked), the bit is cleared when
going to the INITIALIZE state.
Thermal Warning and Shutdown
There are two thermal thresholds: Thermal-warning (WARM) and Thermal Shutdown (TSD / HOT).
• Thermal Warning, WARM-threshold:
• if the temperature exceeds TWARM_Rising threshold, the SENSOR_x_WARM-bit is set and the PMIC
sequences down (unless masked).
• if the temperature fell below TWARM_Falling threshold, the device powers up again, without a new
Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to
ACTIVE state.
• if the temperature exceeds TWARM_Rising threshold, but SENSOR_x_WARM_MASK bit is /bits are set, the
PMIC remains in ACTIVE state. Fault-reporting occurs as configured by MASK_EFFECT bits. The processor
makes the decision to either sequence the power down or throttles back on the running applications to
reduce the power consumption and hopefully avoiding a Thermal Shutdown situation.
• Thermal Shutdown, HOT-threshold, applicable if WARM-threshold is masked:
• if the temperature exceeds THOT_Rising threshold, the SENSOR_x_HOT-bit is set and the PMIC powers off all
rails immediately. This power down is simultaneously and not sequenced.
• in case ALL sensors are masked for WARM-detection (all SENSOR_x_WARM_MASK bits are set), the PMIC
does power back up once the temperature drops below the THOT_Falling threshold, provided a valid ON-
request is present.
• in case any one of the sensors is unmasked for WARM-detection, the PMIC does power back up once the
temperature drops below the TWARM_Falling threshold, without a new
Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to
ACTIVE state.
Residual Voltage
Residual voltage checks are performed at various occasions: before starting the INITIALIZE- to ACTIVE-
transition and any time before a rail is enabled, regardless if during the sequence, by I2C-command or during the
STBY- to ACTIVE-transition. RV-checks are also performed during the sequences, to detect if a rail that is
supposed to be disabled is pulled up by another rail. The treatment of RV-faults depends on the situation when
the fault occurs:
• INITIALIZE to ACTIVE:
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– if residual voltage is detected for more than 4 ms to 5 ms prior to the execution of the sequence, the
respective INT_RV_IS_SET bit in INT_SOURCE register and LDOx_RV respectively BUCKx_RV bit in
INT_RV register is set and remains set, even if the discharge is successful at a later time and the ON-
request is executed.
– if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device
initiates the power-down-sequence at the end of the slot-duration. The device sets the respective
INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register, LDOx_RV_SD respectively
BUCKx_RV_SD bit and bit TIMEOUT in INT_TIMEOUT_RV_SD register.
• ACTIVE to STBY:
– if active discharge is enabled and residual voltage is detected after eight times the power-down slot-
duration, this constitutes a shutdown-fault: the device sequences down at the end of the slot. The device
sets INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register, the LDOx_RV_SD respectively
BUCKx_RV_SD bit and the bit TIMEOUT in INT_TIMEOUT_RV_SD register.
– if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device
sequences down at the end of the slot-duration and sets bit INT_TIMEOUT_RV_SD_IS_SET in
INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD
register.
• STBY to ACTIVE:
– if residual voltage is detected prior to the execution of the sequence for more than 4 ms to 5 ms, the
device sets INT_RV_IS_SET bit in INT_SOURCE register and LDOx_RV respectively BUCKx_RV bit in
INT_RV register. The bit remains set, even if the discharge is successful before timeout expires and the
STBY-to-ACTIVE-sequence is executed.
– if residual voltage is detected for more than 80 ms prior to the execution of the sequence, this constitutes
a shutdown-fault: the device sequences down and sets the bit INT_TIMEOUT_RV_SD_IS_SET in
INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD
register. In addition, the device sets the bit TIMEOUT in INT_TIMEOUT_RV_SD register.
– if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device
sequences down at the end of the slot-duration and sets the INT_TIMEOUT_RV_SD_IS_SET bit in
INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD
register. The TIMEOUT bit is not set in this case.
• ACTIVE to INITIALIZE or STBY to INITIALIZE
– if the residual voltage is detected at the end of the power-down slot-duration of the respective rail, this
gates the disabling of the subsequent rail for up to eight times the slot-duration, but then the power-
sequence continues regardless of the residual voltage. No bit is set in this case.
• MASKING of RV-bits
– the reaction of the nINT-pin reaction in case of residual voltage detection is maskable for LDOx_RV
respectively BUCKx_RV bits by MASK_INT_FOR_RV bit in MASK_CONFIG register.
– neither the bit nor the shutdown-fault-reaction in case of residual voltage detection is maskable for
LDOx_RV_SD respectively BUCKx_RV_SD bits.
• Timeout
– Timeout occurs if residual voltage cannot be discharged in time. The bit TIMEOUT in
INT_TIMEOUT_RV_SD register is set. See details above.
备注
In case active discharge on a rail is disabled, the unsuccessful discharge of that rail within the slot
duration does not gate the disable of the subsequent rail.
During power-down, the device sets neither RV-bits nor RV_SD-bits for rails with disabled discharge.
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CAUTION
For every detected Shut-Down fault, irrespective if prior to the sequence due to unsuccessful
discharge, during the power-up-sequence or in ACTIVE or STBY state, the retry counter
(RETRY_COUNT in POWER_UP_STATUS_REG register) is incremented. The device attempts two
retries to power-up. If both fail, a power-cycle on VSYS is required to reset the retry counter. Any
successful power-up also resets the retry counter.
If faults are masked and do not cause a shut-down, the retry counter does not increment.
To disable the retry-counter, set bit MASK_RETRY_COUNT in INT_MASK_UV register. When set,
the device attempts to retry infinitely.
Below table gives an overview of the fault-behavior in ACTIVE and STBY states if unmasked and whether a fault
is maskable.
CAUTION
Masking of faults can pose a risk to the device or the system, including but not limited to starting into
a pre-biased output.
It is strongly discouraged to mask OC- and UV-detection on the same rail.
表7-6. Fault Handling
Block
Fault
ACTIVE or STBY state (if fault ACTIVE or STBY state (if fault IS masked)
NOT masked)
BUCK & LDO
BUCK & LDO
BUCK & LDO
BUCK & LDO
BUCK & LDO
BUCK & LDO
BUCK & LDO
BUCK & LDO
Residual voltage - shutdown- Fault triggers a sequenced shut- Not maskable
Fault - RV_SD *)
down to INITIALIZE state
Residual voltage - RV
Fault does not trigger state-
change
Fault does not trigger state-change
Timeout - TO *)
Fault triggers a sequenced shut- Fault does not trigger state-change
down to INITIALIZE state
Undervoltage - UV
Overcurrent - OC
Short-to-GND - SCG
Fault triggers a sequenced shut- Fault does not trigger state-change
down to INITIALIZE state
Fault triggers a sequenced shut- Not maskable
down to INITIALIZE state
Fault triggers a sequenced shut- Not maskable
down to INITIALIZE state
Temperature warning - WARM Fault triggers a sequenced shut- Yes
down to INITIALIZE state
Temperature shut-down - HOT Fault triggers an immediate
shut-down to INITIALIZE state
Not maskable
(not sequenced)
VSYS
VSYS
Undervoltage - UV
Overvoltage - OV
Fault triggers an immediate
shut-down to OFF state (not
sequenced)
Not maskable
Not maskable
Fault triggers an immediate
shut-down to OFF state (not
sequenced)
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表7-6. Fault Handling (continued)
Block
Fault
ACTIVE or STBY state (if fault ACTIVE or STBY state (if fault IS masked)
NOT masked)
VDD1P8
Undervoltage or Overvoltage - Fault triggers an immediate
Not maskable
UV or OV
shut-down to OFF state (not
sequenced)
*) RV_SD and TIMEOUT faults can only occur during a sequence
7.5 User Registers
The registers up to register 27h, USER_GENERAL_NVM_STORAGE_REG are backed up by EEPROM. The
reset value corresponds to the configuration of the orderable part number and is signified by an 'X' herein.
Please refer to the Technical Reference Manual (TRM) of the respective orderable part-number.
The registers 28h through 37h are not EEPROM-backed and reset to the value shown in the register map.
Registers 00h, TI_DEV_ID, 01h, NVM_ID, 28h, MANUFACTURING_VER and 41h, FACTORY_CONFIG_2 are
hard-wired and cannot be changed by the user.
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7.6 Device Registers
表 7-7 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in 表
7-7 should be considered as reserved locations and the register contents should not be modified.
表7-7. DEVICE Registers
Offset Acronym
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
0h
1h
TI_DEV_ID
Device ID
NVM_ID
NVM configuration ID
2h
ENABLE_CTRL
Enable/Push-Button/Vsense Control
Generic Buck Configuration
LDO4 Configuration
3h
BUCKS_CONFIG
4h
LDO4_VOUT
5h
LDO3_VOUT
LDO3 Configuration
6h
LDO2_VOUT
LDO2 Configuration
7h
LDO1_VOUT
LDO1 Configuration
8h
BUCK3_VOUT
Buck3 Configuration
9h
BUCK2_VOUT
Buck2 Configuration
Ah
Bh
Ch
Dh
Eh
Fh
BUCK1_VOUT
Buck1 Configuration
LDO4_SEQUENCE_SLOT
LDO3_SEQUENCE_SLOT
LDO2_SEQUENCE_SLOT
LDO1_SEQUENCE_SLOT
BUCK3_SEQUENCE_SLOT
BUCK2_SEQUENCE_SLOT
BUCK1_SEQUENCE_SLOT
nRST_SEQUENCE_SLOT
GPIO_SEQUENCE_SLOT
GPO2_SEQUENCE_SLOT
GPO1_SEQUENCE_SLOT
Power-up and -down slot for LDO4
Power-up and -down slot for LDO3
Power-up and -down slot for LDO2
Power-up and -down slot for LDO10
Power-up and -down slot for Buck3
Power-up and -down slot for Buck2
Power-up and -down slot for Buck1
Power-up and -down slot for nRSTOUT
Power-up and -down slot for GPIO
Power-up and -down slot for GPO2
Power-up and -down slot for GPO1
10h
11h
12h
13h
14h
15h
16h
POWER_UP_SLOT_DURATION Slot-duration at power-up for slot0-3
_1
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
POWER_UP_SLOT_DURATION Slot-duration at power-up for slot4-7
_2
Go
Go
Go
Go
Go
Go
Go
POWER_UP_SLOT_DURATION Slot-duration at power-up for slot8-11
_3
POWER_UP_SLOT_DURATION Slot-duration at power-up for slot12-15
_4
POWER_DOWN_SLOT_DURATI Slot-duration at power-down for slot0-3
ON_1
POWER_DOWN_SLOT_DURATI Slot-duration at power-down for slot4-7
ON_2
POWER_DOWN_SLOT_DURATI Slot-duration at power-down for slot8-11
ON_3
POWER_DOWN_SLOT_DURATI Slot-duration at power-down for slot12-15
ON_4
1Eh
1Fh
20h
21h
22h
23h
GENERAL_CONFIG
MFP_1_CONFIG
MFP_2_CONFIG
STBY_1_CONFIG
STBY_2_CONFIG
OC_DEGL_CONFIG
LDO-undervoltage and GPO-enable
Multi-Function pin configuration1
Multi-Function pin configuration2
STBY configuration LDOs and Bucks
STBY configuration GPIO and GPO
Overcurrent deglitch time per rail
Go
Go
Go
Go
Go
Go
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表7-7. DEVICE Registers (continued)
Offset Acronym
Register Name
Section
Go
24h
25h
26h
27h
INT_MASK_UV
Undervoltage fault-masking
WARM-masking and mask-effect
I2C-address
MASK_CONFIG
Go
I2C_ADDRESS_REG
Go
USER_GENERAL_NVM_STORA User-configurable register (NVM-backed)
GE_REG
Go
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
MANUFACTURING_VER
MFP_CTRL
Silicon-revision (read-only)
I2C-control for RESET, STBY, OFF
Discharge configuration per rail
Interrupt source
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
DISCHARGE_CONFIG
INT_SOURCE
INT_LDO_3_4
OC, UV, SCG for LDO3 and LDO4
OC, UV, SCG for LDO1 and LDO2
OC, UV, SCG for Buck3
INT_LDO_1_2
INT_BUCK_3
INT_BUCK_1_2
INT_SYSTEM
OC, UV, SCG for Buck1 and Buck2
WARM and HOT fault flags
RV (residual voltage) per rail
INT_RV
INT_TIMEOUT_RV_SD
RV (residual voltage) per rail causing shut-
down
33h
34h
35h
36h
37h
41h
INT_PB
PushButton status and edge-detection
DIY - user programming commands
Power-up status and STATE
Go
Go
Go
Go
Go
Go
USER_NVM_CMD_REG
POWER_UP_STATUS_REG
SPARE_2
Spare register (not NVM-backed)
Spare register (not NVM-backed)
Revision of NVM-configuration (read only)
SPARE_3
FACTORY_CONFIG_2
Complex bit access types are encoded to fit into small table cells. 表 7-8 shows the codes that are used for
access types in this section.
表7-8. Device Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
W1C
W
Write
1C
1 to clear
WSelfClrF
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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7.6.1 TI_DEV_ID Register (Offset = 0h) [Reset = X]
TI_DEV_ID is shown in 图7-12 and described in 表7-9.
Return to the Summary Table.
图7-12. TI_DEV_ID Register
7
6
5
4
3
2
1
0
TI_DEVICE_ID
R/W-X
表7-9. TI_DEV_ID Register Field Descriptions
Bit
7-0
Field
TI_DEVICE_ID
Type
Reset
Description
R/W
X
TI_DEVICE_ID[7]: 0 - TA: -40oC to 105oC, TJ: -40oC to 125oC 1 -
TA: -40oC to 125oC, TJ: -40oC to 150oC TI_DEVICE_ID[6:0] =
Device GPN Note: This register can be programmed only by the
manufacturer! Refer to Technical Reference Manual / User's Guide
for specific numbering and associated configuration. (Default from
NVM memory)
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7.6.2 NVM_ID Register (Offset = 1h) [Reset = X]
NVM_ID is shown in 图7-13 and described in 表7-10.
Return to the Summary Table.
图7-13. NVM_ID Register
7
6
5
4
3
2
1
0
TI_NVM_ID
R/W-X
表7-10. NVM_ID Register Field Descriptions
Bit
7-0
Field
TI_NVM_ID
Type
Reset
Description
R/W
X
NVM ID of the IC Note: This register can be programmed only by the
manufacturer! Refer to Technical Reference Manual / User's Guide
for specific numbering and associated configuration. (Default from
NVM memory)
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7.6.3 ENABLE_CTRL Register (Offset = 2h) [Reset = X]
ENABLE_CTRL is shown in 图7-14 and described in 表7-11.
Return to the Summary Table.
图7-14. ENABLE_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R-X
LDO4_EN
R/W-X
LDO3_EN
R/W-X
LDO2_EN
R/W-X
LDO1_EN
R/W-X
BUCK3_EN
R/W-X
BUCK2_EN
R/W-X
BUCK1_EN
R/W-X
表7-11. ENABLE_CTRL Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
X
X
Reserved
6
LDO4_EN
LDO3_EN
LDO2_EN
LDO1_EN
BUCK3_EN
BUCK2_EN
BUCK1_EN
R/W
Enable LDO4 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
Enable LDO3 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
Enable LDO2 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
Enable LDO1 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
Enable BUCK3 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
Enable BUCK2 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
Enable BUCK1 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
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7.6.4 BUCKS_CONFIG Register (Offset = 3h) [Reset = X]
BUCKS_CONFIG is shown in 图7-15 and described in 表7-12.
Return to the Summary Table.
图7-15. BUCKS_CONFIG Register
7
6
5
4
3
2
1
0
USER_NVM_S USER_NVM_S BUCK_SS_EN BUCK_FF_ENA
BUCK3_PHASE_CONFIG
R/W-X
BUCK2_PHASE_CONFIG
PARE_2
PARE_1
ABLE
BLE
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
表7-12. BUCKS_CONFIG Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
Reset
Description
USER_NVM_SPARE_2
USER_NVM_SPARE_1
BUCK_SS_ENABLE
X
X
X
Spare bit in user NVM space (Default from NVM memory)
Spare bit in user NVM space (Default from NVM memory)
6
5
Spread spectrum enabled on Bucks (only applicable in FF-mode)
(Default from NVM memory)
0h = Spread spectrum disabled
1h = Spread spectrum enabled
4
BUCK_FF_ENABLE
R/W
X
X
All Bucks set into fixed frequency mode NOTE: MUST NOT
CHANGE AT ANY TIME! (Default from NVM memory)
0h = Quasi-fixed frequency mode
1h = Fixed frequency mode
3-2
BUCK3_PHASE_CONFIG R/W
BUCK2_PHASE_CONFIG R/W
Phase of BUCK3 clock. Applicable if Bucks are configured for fixed
frequency. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED!
(Default from NVM memory)
0h = 0 degrees
1h = 90 degrees
2h = 180 degrees
3h = 270 degrees
1-0
X
Phase of BUCK2 clock. Applicable if Bucks are configured for fixed
frequency. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED!
(Default from NVM memory)
0h = 0 degrees
1h = 90 degrees
2h = 180 degrees
3h = 270 degrees
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7.6.5 LDO4_VOUT Register (Offset = 4h) [Reset = X]
LDO4_VOUT is shown in 图7-16 and described in 表7-13.
Return to the Summary Table.
图7-16. LDO4_VOUT Register
7
6
5
4
3
2
1
0
LDO4_SLOW_ LDO4_LSW_C
LDO4_VSET
R/W-X
PU_RAMP
ONFIG
R/W-X
R/W-X
表7-13. LDO4_VOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LDO4_SLOW_PU_RAMP R/W
X
LDO4 Power-up ramp When set high, slows down the power-up
ramp to ~3ms. Cout max 30uF When set low, ramp time is ~660us.
Cout max 15uF (Default from NVM memory)
0h = Fast ramp for power-up (~660us)
1h = Slow ramp for power-up (~3ms)
6
LDO4_LSW_CONFIG
R/W
X
LDO4 LDO or LSW Mode. NOTE: ONLY CHANGE WHILE RAIL IS
DISABLED! (Default from NVM memory)
0h = LDO Mode
1h = LSW Mode
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表7-13. LDO4_VOUT Register Field Descriptions (continued)
Bit
Field
LDO4_VSET
Type
Reset
Description
5-0
R/W
X
Voltage selection for LDO4. The output voltage range is from 1.2V to
3.3V. (Default from NVM memory)
0h = 1.200V
1h = 1.200V
2h = 1.200V
3h = 1.200V
4h = 1.200V
5h = 1.200V
6h = 1.200V
7h = 1.200V
8h = 1.200V
9h = 1.200V
Ah = 1.200V
Bh = 1.200V
Ch = 1.200V
Dh = 1.250V
Eh = 1.300V
Fh = 1.350V
10h = 1.400V
11h = 1.450V
12h = 1.500V
13h = 1.550V
14h = 1.600V
15h = 1.650V
16h = 1.700V
17h = 1.750V
18h = 1.800V
19h = 1.850V
1Ah = 1.900V
1Bh = 1.950V
1Ch = 2.000V
1Dh = 2.050V
1Eh = 2.100V
1Fh = 2.150V
20h = 2.200V
21h = 2.250V
22h = 2.300V
23h = 2.350V
24h = 2.400V
25h = 2.450V
26h = 2.500V
27h = 2.550V
28h = 2.600V
29h = 2.650V
2Ah = 2.700V
2Bh = 2.750V
2Ch = 2.800V
2Dh = 2.850V
2Eh = 2.900V
2Fh = 2.950V
30h = 3.000V
31h = 3.050V
32h = 3.100V
33h = 3.150V
34h = 3.200V
35h = 3.250V
36h = 3.300V
37h = 3.300V
38h = 3.300V
39h = 3.300V
3Ah = 3.300V
3Bh = 3.300V
3Ch = 3.300V
3Dh = 3.300V
3Eh = 3.300V
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表7-13. LDO4_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3Fh = 3.300V
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7.6.6 LDO3_VOUT Register (Offset = 5h) [Reset = X]
LDO3_VOUT is shown in 图7-17 and described in 表7-14.
Return to the Summary Table.
图7-17. LDO3_VOUT Register
7
6
5
4
3
2
1
0
LDO3_SLOW_ LDO3_LSW_C
LDO3_VSET
R/W-X
PU_RAMP
ONFIG
R/W-X
R/W-X
表7-14. LDO3_VOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LDO3_SLOW_PU_RAMP R/W
X
LDO3 Power-up ramp When set high, slows down the power-up
ramp to ~3ms. Cout max 30uF When set low, ramp time is ~660us.
Cout max 15uF (Default from NVM memory)
0h = Fast ramp for power-up (~660us)
1h = Slow ramp for power-up (~3ms)
6
LDO3_LSW_CONFIG
R/W
X
LDO3 LDO or LSW Mode. NOTE: ONLY CHANGE WHILE RAIL IS
DISABLED! (Default from NVM memory)
0h = LDO Mode
1h = LSW Mode
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表7-14. LDO3_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
LDO3_VSET
R/W
X
Voltage selection for LDO3. The output voltage range is from 1.2V to
3.3V. (Default from NVM memory)
0h = 1.200V
1h = 1.200V
2h = 1.200V
3h = 1.200V
4h = 1.200V
5h = 1.200V
6h = 1.200V
7h = 1.200V
8h = 1.200V
9h = 1.200V
Ah = 1.200V
Bh = 1.200V
Ch = 1.200V
Dh = 1.250V
Eh = 1.300V
Fh = 1.350V
10h = 1.400V
11h = 1.450V
12h = 1.500V
13h = 1.550V
14h = 1.600V
15h = 1.650V
16h = 1.700V
17h = 1.750V
18h = 1.800V
19h = 1.850V
1Ah = 1.900V
1Bh = 1.950V
1Ch = 2.000V
1Dh = 2.050V
1Eh = 2.100V
1Fh = 2.150V
20h = 2.200V
21h = 2.250V
22h = 2.300V
23h = 2.350V
24h = 2.400V
25h = 2.450V
26h = 2.500V
27h = 2.550V
28h = 2.600V
29h = 2.650V
2Ah = 2.700V
2Bh = 2.750V
2Ch = 2.800V
2Dh = 2.850V
2Eh = 2.900V
2Fh = 2.950V
30h = 3.000V
31h = 3.050V
32h = 3.100V
33h = 3.150V
34h = 3.200V
35h = 3.250V
36h = 3.300V
37h = 3.300V
38h = 3.300V
39h = 3.300V
3Ah = 3.300V
3Bh = 3.300V
3Ch = 3.300V
3Dh = 3.300V
3Eh = 3.300V
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表7-14. LDO3_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3Fh = 3.300V
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7.6.7 LDO2_VOUT Register (Offset = 6h) [Reset = X]
LDO2_VOUT is shown in 图7-18 and described in 表7-15.
Return to the Summary Table.
图7-18. LDO2_VOUT Register
7
6
5
4
3
2
1
0
LDO2_LSW_C LDO2_BYP_CO
LDO2_VSET
R/W-X
ONFIG
NFIG
R/W-X
R/W-X
表7-15. LDO2_VOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LDO2_LSW_CONFIG
R/W
X
LDO2 LDO/Bypass or LSW Mode. NOTE: ONLY CHANGE WHILE
RAIL IS DISABLED! (Default from NVM memory)
0h = Not Applicable (LDO2 not configured as load-switch)
1h = LDO1 configured as Load-switch
6
LDO2_BYP_CONFIG
R/W
X
LDO2 LDO or Bypass Mode. (Default from NVM memory)
0h = LDO2 configured as LDO (only applicable if
LDO2_LSW_CONFIG 0x0)
1h = LDO2 configured as Bypass (only applicable if
LDO2_LSW_CONFIG 0x0)
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表7-15. LDO2_VOUT Register Field Descriptions (continued)
Bit
Field
LDO2_VSET
Type
Reset
Description
5-0
R/W
X
Voltage selection for LDO2. The output voltage range is from 0.6V to
3.4V in LDO mode and 1.5V to 3.4V in bypass-mode. (Default from
NVM memory)
0h = 0.600V
1h = 0.650V
2h = 0.700V
3h = 0.750V
4h = 0.800V
5h = 0.850V
6h = 0.900V
7h = 0.950V
8h = 1.000V
9h = 1.050V
Ah = 1.100V
Bh = 1.150V
Ch = 1.200V
Dh = 1.250V
Eh = 1.300V
Fh = 1.350V
10h = 1.400V
11h = 1.450V
12h = 1.500V
13h = 1.550V
14h = 1.600V
15h = 1.650V
16h = 1.700V
17h = 1.750V
18h = 1.800V
19h = 1.850V
1Ah = 1.900V
1Bh = 1.950V
1Ch = 2.000V
1Dh = 2.050V
1Eh = 2.100V
1Fh = 2.150V
20h = 2.200V
21h = 2.250V
22h = 2.300V
23h = 2.350V
24h = 2.400V
25h = 2.450V
26h = 2.500V
27h = 2.550V
28h = 2.600V
29h = 2.650V
2Ah = 2.700V
2Bh = 2.750V
2Ch = 2.800V
2Dh = 2.850V
2Eh = 2.900V
2Fh = 2.950V
30h = 3.000V
31h = 3.050V
32h = 3.100V
33h = 3.150V
34h = 3.200V
35h = 3.250V
36h = 3.300V
37h = 3.350V
38h = 3.400V
39h = 3.400V
3Ah = 3.400V
3Bh = 3.400V
3Ch = 3.400V
3Dh = 3.400V
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表7-15. LDO2_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3Eh = 3.400V
3Fh = 3.400V
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7.6.8 LDO1_VOUT Register (Offset = 7h) [Reset = X]
LDO1_VOUT is shown in 图7-19 and described in 表7-16.
Return to the Summary Table.
图7-19. LDO1_VOUT Register
7
6
5
4
3
2
1
0
LDO1_LSW_C LDO1_BYP_CO
LDO1_VSET
R/W-X
ONFIG
NFIG
R/W-X
R/W-X
表7-16. LDO1_VOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LDO1_LSW_CONFIG
R/W
X
LDO1 LDO/Bypass or LSW Mode. NOTE: ONLY CHANGE WHILE
RAIL IS DISABLED! (Default from NVM memory)
0h = Not Applicable (LDO1 not configured as load-switch)
1h = LDO1 configured as Load-switch
6
LDO1_BYP_CONFIG
R/W
X
LDO1 LDO or Bypass Mode. (Default from NVM memory)
0h = LDO1 configured as LDO (only applicable if
LDO1_LSW_CONFIG 0x0)
1h = LDO1 configured as Bypass (only applicable if
LDO1_LSW_CONFIG 0x0)
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表7-16. LDO1_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
LDO1_VSET
R/W
X
Voltage selection for LDO1. The output voltage range is from 0.6V to
3.4V in LDO-mode and 1.5V to 3.4V in bypass-mode. (Default from
NVM memory)
0h = 0.600V
1h = 0.650V
2h = 0.700V
3h = 0.750V
4h = 0.800V
5h = 0.850V
6h = 0.900V
7h = 0.950V
8h = 1.000V
9h = 1.050V
Ah = 1.100V
Bh = 1.150V
Ch = 1.200V
Dh = 1.250V
Eh = 1.300V
Fh = 1.350V
10h = 1.400V
11h = 1.450V
12h = 1.500V
13h = 1.550V
14h = 1.600V
15h = 1.650V
16h = 1.700V
17h = 1.750V
18h = 1.800V
19h = 1.850V
1Ah = 1.900V
1Bh = 1.950V
1Ch = 2.000V
1Dh = 2.050V
1Eh = 2.100V
1Fh = 2.150V
20h = 2.200V
21h = 2.250V
22h = 2.300V
23h = 2.350V
24h = 2.400V
25h = 2.450V
26h = 2.500V
27h = 2.550V
28h = 2.600V
29h = 2.650V
2Ah = 2.700V
2Bh = 2.750V
2Ch = 2.800V
2Dh = 2.850V
2Eh = 2.900V
2Fh = 2.950V
30h = 3.000V
31h = 3.050V
32h = 3.100V
33h = 3.150V
34h = 3.200V
35h = 3.250V
36h = 3.300V
37h = 3.350V
38h = 3.400V
39h = 3.400V
3Ah = 3.400V
3Bh = 3.400V
3Ch = 3.400V
3Dh = 3.400V
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表7-16. LDO1_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3Eh = 3.400V
3Fh = 3.400V
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7.6.9 BUCK3_VOUT Register (Offset = 8h) [Reset = X]
BUCK3_VOUT is shown in 图7-20 and described in 表7-17.
Return to the Summary Table.
图7-20. BUCK3_VOUT Register
7
6
5
4
3
2
1
0
BUCK3_BW_S BUCK3_UV_TH
BUCK3_VSET
R/W-X
EL
R_SEL
R/W-X
R/W-X
表7-17. BUCK3_VOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BUCK3_BW_SEL
R/W
X
BUCK3 Bandwidth selection. NOTE: ONLY CHANGE WHILE RAIL
IS DISABLED! (Default from NVM memory)
0h = low bandwidth
1h = high bandwidth
6
BUCK3_UV_THR_SEL
R/W
X
UV threshold selection for BUCK3. (Default from NVM memory)
0h = -5% UV detection
1h = -10% UV detection
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表7-17. BUCK3_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
BUCK3_VSET
R/W
X
Voltage selection for BUCK3. The output voltage range is from 0.6V
to 3.4V. (Default from NVM memory)
0h = 0.600V
1h = 0.625V
2h = 0.650V
3h = 0.675V
4h = 0.700V
5h = 0.725V
6h = 0.750V
7h = 0.775V
8h = 0.800V
9h = 0.825V
Ah = 0.850V
Bh = 0.875V
Ch = 0.900V
Dh = 0.925V
Eh = 0.950V
Fh = 0.975V
10h = 1.000V
11h = 1.025V
12h = 1.050V
13h = 1.075V
14h = 1.100V
15h = 1.125V
16h = 1.150V
17h = 1.175V
18h = 1.200V
19h = 1.225V
1Ah = 1.250V
1Bh = 1.275V
1Ch = 1.300V
1Dh = 1.325V
1Eh = 1.350V
1Fh = 1.375V
20h = 1.400V
21h = 1.500V
22h = 1.600V
23h = 1.700V
24h = 1.800V
25h = 1.900V
26h = 2.000V
27h = 2.100V
28h = 2.200V
29h = 2.300V
2Ah = 2.400V
2Bh = 2.500V
2Ch = 2.600V
2Dh = 2.700V
2Eh = 2.800V
2Fh = 2.900V
30h = 3.000V
31h = 3.100V
32h = 3.200V
33h = 3.300V
34h = 3.400V
35h = 3.400V
36h = 3.400V
37h = 3.400V
38h = 3.400V
39h = 3.400V
3Ah = 3.400V
3Bh = 3.400V
3Ch = 3.400V
3Dh = 3.400V
3Eh = 3.400V
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表7-17. BUCK3_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3Fh = 3.400V
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7.6.10 BUCK2_VOUT Register (Offset = 9h) [Reset = X]
BUCK2_VOUT is shown in 图7-21 and described in 表7-18.
Return to the Summary Table.
图7-21. BUCK2_VOUT Register
7
6
5
4
3
2
1
0
BUCK2_BW_S BUCK2_UV_TH
BUCK2_VSET
R/W-X
EL
R_SEL
R/W-X
R/W-X
表7-18. BUCK2_VOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BUCK2_BW_SEL
R/W
X
BUCK2 Bandwidth selection. NOTE: ONLY CHANGE WHILE RAIL
IS DISABLED! (Default from NVM memory)
0h = low bandwidth
1h = high bandwidth
6
BUCK2_UV_THR_SEL
R/W
X
UV threshold selection for BUCK2. (Default from NVM memory)
0h = -5% UV detection
1h = -10% UV detection
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表7-18. BUCK2_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
BUCK2_VSET
R/W
X
Voltage selection for BUCK2. The output voltage range is from 0.6V
to 3.4V. (Default from NVM memory)
0h = 0.600V
1h = 0.625V
2h = 0.650V
3h = 0.675V
4h = 0.700V
5h = 0.725V
6h = 0.750V
7h = 0.775V
8h = 0.800V
9h = 0.825V
Ah = 0.850V
Bh = 0.875V
Ch = 0.900V
Dh = 0.925V
Eh = 0.950V
Fh = 0.975V
10h = 1.000V
11h = 1.025V
12h = 1.050V
13h = 1.075V
14h = 1.100V
15h = 1.125V
16h = 1.150V
17h = 1.175V
18h = 1.200V
19h = 1.225V
1Ah = 1.250V
1Bh = 1.275V
1Ch = 1.300V
1Dh = 1.325V
1Eh = 1.350V
1Fh = 1.375V
20h = 1.400V
21h = 1.500V
22h = 1.600V
23h = 1.700V
24h = 1.800V
25h = 1.900V
26h = 2.000V
27h = 2.100V
28h = 2.200V
29h = 2.300V
2Ah = 2.400V
2Bh = 2.500V
2Ch = 2.600V
2Dh = 2.700V
2Eh = 2.800V
2Fh = 2.900V
30h = 3.000V
31h = 3.100V
32h = 3.200V
33h = 3.300V
34h = 3.400V
35h = 3.400V
36h = 3.400V
37h = 3.400V
38h = 3.400V
39h = 3.400V
3Ah = 3.400V
3Bh = 3.400V
3Ch = 3.400V
3Dh = 3.400V
3Eh = 3.400V
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表7-18. BUCK2_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3Fh = 3.400V
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7.6.11 BUCK1_VOUT Register (Offset = Ah) [Reset = X]
BUCK1_VOUT is shown in 图7-22 and described in 表7-19.
Return to the Summary Table.
图7-22. BUCK1_VOUT Register
7
6
5
4
3
2
1
0
BUCK1_BW_S BUCK1_UV_TH
BUCK1_VSET
R/W-X
EL
R_SEL
R/W-X
R/W-X
表7-19. BUCK1_VOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BUCK1_BW_SEL
R/W
X
BUCK1 Bandwidth selection. NOTE: ONLY CHANGE WHILE RAIL
IS DISABLED! (Default from NVM memory)
0h = low bandwidth
1h = high bandwidth
6
BUCK1_UV_THR_SEL
R/W
X
UV threshold selection for BUCK1. (Default from NVM memory)
0h = -5% UV detection
1h = -10% UV detection
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表7-19. BUCK1_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
BUCK1_VSET
R/W
X
Voltage selection for BUCK1. The output voltage range is from 0.6V
to 3.4V. (Default from NVM memory)
0h = 0.600V
1h = 0.625V
2h = 0.650V
3h = 0.675V
4h = 0.700V
5h = 0.725V
6h = 0.750V
7h = 0.775V
8h = 0.800V
9h = 0.825V
Ah = 0.850V
Bh = 0.875V
Ch = 0.900V
Dh = 0.925V
Eh = 0.950V
Fh = 0.975V
10h = 1.000V
11h = 1.025V
12h = 1.050V
13h = 1.075V
14h = 1.100V
15h = 1.125V
16h = 1.150V
17h = 1.175V
18h = 1.200V
19h = 1.225V
1Ah = 1.250V
1Bh = 1.275V
1Ch = 1.300V
1Dh = 1.325V
1Eh = 1.350V
1Fh = 1.375V
20h = 1.400V
21h = 1.500V
22h = 1.600V
23h = 1.700V
24h = 1.800V
25h = 1.900V
26h = 2.000V
27h = 2.100V
28h = 2.200V
29h = 2.300V
2Ah = 2.400V
2Bh = 2.500V
2Ch = 2.600V
2Dh = 2.700V
2Eh = 2.800V
2Fh = 2.900V
30h = 3.000V
31h = 3.100V
32h = 3.200V
33h = 3.300V
34h = 3.400V
35h = 3.400V
36h = 3.400V
37h = 3.400V
38h = 3.400V
39h = 3.400V
3Ah = 3.400V
3Bh = 3.400V
3Ch = 3.400V
3Dh = 3.400V
3Eh = 3.400V
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表7-19. BUCK1_VOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3Fh = 3.400V
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7.6.12 LDO4_SEQUENCE_SLOT Register (Offset = Bh) [Reset = X]
LDO4_SEQUENCE_SLOT is shown in 图7-23 and described in 表7-20.
Return to the Summary Table.
图7-23. LDO4_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
LDO4_SEQUENCE_ON_SLOT
R/W-X
LDO4_SEQUENCE_OFF_SLOT
R/W-X
表7-20. LDO4_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
LDO4_SEQUENCE_ON_ R/W
SLOT
X
LDO4 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
LDO4_SEQUENCE_OFF_ R/W
SLOT
X
LDO4 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.13 LDO3_SEQUENCE_SLOT Register (Offset = Ch) [Reset = X]
LDO3_SEQUENCE_SLOT is shown in 图7-24 and described in 表7-21.
Return to the Summary Table.
图7-24. LDO3_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
LDO3_SEQUENCE_ON_SLOT
R/W-X
LDO3_SEQUENCE_OFF_SLOT
R/W-X
表7-21. LDO3_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
LDO3_SEQUENCE_ON_ R/W
SLOT
X
LDO3 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
LDO3_SEQUENCE_OFF_ R/W
SLOT
X
LDO3 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.14 LDO2_SEQUENCE_SLOT Register (Offset = Dh) [Reset = X]
LDO2_SEQUENCE_SLOT is shown in 图7-25 and described in 表7-22.
Return to the Summary Table.
图7-25. LDO2_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
LDO2_SEQUENCE_ON_SLOT
R/W-X
LDO2_SEQUENCE_OFF_SLOT
R/W-X
表7-22. LDO2_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
LDO2_SEQUENCE_ON_ R/W
SLOT
X
LDO2 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
LDO2_SEQUENCE_OFF_ R/W
SLOT
X
LDO2 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.15 LDO1_SEQUENCE_SLOT Register (Offset = Eh) [Reset = X]
LDO1_SEQUENCE_SLOT is shown in 图7-26 and described in 表7-23.
Return to the Summary Table.
图7-26. LDO1_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
LDO1_SEQUENCE_ON_SLOT
R/W-X
LDO1_SEQUENCE_OFF_SLOT
R/W-X
表7-23. LDO1_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
LDO1_SEQUENCE_ON_ R/W
SLOT
X
LDO1 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
LDO1_SEQUENCE_OFF_ R/W
SLOT
X
LDO1 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.16 BUCK3_SEQUENCE_SLOT Register (Offset = Fh) [Reset = X]
BUCK3_SEQUENCE_SLOT is shown in 图7-27 and described in 表7-24.
Return to the Summary Table.
图7-27. BUCK3_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
BUCK3_SEQUENCE_ON_SLOT
R/W-X
BUCK3_SEQUENCE_OFF_SLOT
R/W-X
表7-24. BUCK3_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
BUCK3_SEQUENCE_ON R/W
_SLOT
X
BUCK3 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
BUCK3_SEQUENCE_OF R/W
F_SLOT
X
BUCK3 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.17 BUCK2_SEQUENCE_SLOT Register (Offset = 10h) [Reset = X]
BUCK2_SEQUENCE_SLOT is shown in 图7-28 and described in 表7-25.
Return to the Summary Table.
图7-28. BUCK2_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
BUCK2_SEQUENCE_ON_SLOT
R/W-X
BUCK2_SEQUENCE_OFF_SLOT
R/W-X
表7-25. BUCK2_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
BUCK2_SEQUENCE_ON R/W
_SLOT
X
BUCK2 Slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
BUCK2_SEQUENCE_OF R/W
F_SLOT
X
BUCK2 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.18 BUCK1_SEQUENCE_SLOT Register (Offset = 11h) [Reset = X]
BUCK1_SEQUENCE_SLOT is shown in 图7-29 and described in 表7-26.
Return to the Summary Table.
图7-29. BUCK1_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
BUCK1_SEQUENCE_ON_SLOT
R/W-X
BUCK1_SEQUENCE_OFF_SLOT
R/W-X
表7-26. BUCK1_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
BUCK1_SEQUENCE_ON R/W
_SLOT
X
BUCK1 Slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
BUCK1_SEQUENCE_OF R/W
F_SLOT
X
BUCK1 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.19 nRST_SEQUENCE_SLOT Register (Offset = 12h) [Reset = X]
nRST_SEQUENCE_SLOT is shown in 图7-30 and described in 表7-27.
Return to the Summary Table.
图7-30. nRST_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
nRST_SEQUENCE_ON_SLOT
R/W-X
nRST_SEQUENCE_OFF_SLOT
R/W-X
表7-27. nRST_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
nRST_SEQUENCE_ON_ R/W
SLOT
X
nRST slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
nRST_SEQUENCE_OFF_ R/W
SLOT
X
nRST slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.20 GPIO_SEQUENCE_SLOT Register (Offset = 13h) [Reset = X]
GPIO_SEQUENCE_SLOT is shown in 图7-31 and described in 表7-28.
Return to the Summary Table.
图7-31. GPIO_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
GPIO_SEQUENCE_ON_SLOT
R/W-X
GPIO_SEQUENCE_OFF_SLOT
R/W-X
表7-28. GPIO_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
GPIO_SEQUENCE_ON_ R/W
SLOT
X
GPIO slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
GPIO_SEQUENCE_OFF_ R/W
SLOT
X
GPIO slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.21 GPO2_SEQUENCE_SLOT Register (Offset = 14h) [Reset = X]
GPO2_SEQUENCE_SLOT is shown in 图7-32 and described in 表7-29.
Return to the Summary Table.
图7-32. GPO2_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
GPO2_SEQUENCE_ON_SLOT
R/W-X
GPO2_SEQUENCE_OFF_SLOT
R/W-X
表7-29. GPO2_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
GPO2_SEQUENCE_ON_ R/W
SLOT
X
GPO2 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
GPO2_SEQUENCE_OFF R/W
_SLOT
X
GPO2 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.22 GPO1_SEQUENCE_SLOT Register (Offset = 15h) [Reset = X]
GPO1_SEQUENCE_SLOT is shown in 图7-33 and described in 表7-30.
Return to the Summary Table.
图7-33. GPO1_SEQUENCE_SLOT Register
7
6
5
4
3
2
1
0
GPO1_SEQUENCE_ON_SLOT
R/W-X
GPO1_SEQUENCE_OFF_SLOT
R/W-X
表7-30. GPO1_SEQUENCE_SLOT Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
GPO1_SEQUENCE_ON_ R/W
SLOT
X
GPO1 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0
GPO1_SEQUENCE_OFF R/W
_SLOT
X
GPO1 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
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7.6.23 POWER_UP_SLOT_DURATION_1 Register (Offset = 16h) [Reset = X]
POWER_UP_SLOT_DURATION_1 is shown in 图7-34 and described in 表7-31.
Return to the Summary Table.
图7-34. POWER_UP_SLOT_DURATION_1 Register
7
6
5
4
3
2
1
0
POWER_UP_SLOT_0_DURATIO POWER_UP_SLOT_1_DURATIO POWER_UP_SLOT_2_DURATIO POWER_UP_SLOT_3_DURATIO
N
N
N
N
R/W-X
R/W-X
R/W-X
R/W-X
表7-31. POWER_UP_SLOT_DURATION_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
POWER_UP_SLOT_0_D R/W
URATION
X
Duration of slot 0 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4
3-2
1-0
POWER_UP_SLOT_1_D R/W
URATION
X
X
X
Duration of slot 1 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_UP_SLOT_2_D R/W
URATION
Duration of slot 2 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_UP_SLOT_3_D R/W
URATION
Duration of slot 3 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
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7.6.24 POWER_UP_SLOT_DURATION_2 Register (Offset = 17h) [Reset = X]
POWER_UP_SLOT_DURATION_2 is shown in 图7-35 and described in 表7-32.
Return to the Summary Table.
图7-35. POWER_UP_SLOT_DURATION_2 Register
7
6
5
4
3
2
1
0
POWER_UP_SLOT_4_DURATIO POWER_UP_SLOT_5_DURATIO POWER_UP_SLOT_6_DURATIO POWER_UP_SLOT_7_DURATIO
N
N
N
N
R/W-X
R/W-X
R/W-X
R/W-X
表7-32. POWER_UP_SLOT_DURATION_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
POWER_UP_SLOT_4_D R/W
URATION
X
Duration of slot 4 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4
3-2
1-0
POWER_UP_SLOT_5_D R/W
URATION
X
X
X
Duration of slot 5 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_UP_SLOT_6_D R/W
URATION
Duration of slot 6 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_UP_SLOT_7_D R/W
URATION
Duration of slot 7 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
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7.6.25 POWER_UP_SLOT_DURATION_3 Register (Offset = 18h) [Reset = X]
POWER_UP_SLOT_DURATION_3 is shown in 图7-36 and described in 表7-33.
Return to the Summary Table.
图7-36. POWER_UP_SLOT_DURATION_3 Register
7
6
5
4
3
2
1
0
POWER_UP_SLOT_8_DURATIO POWER_UP_SLOT_9_DURATIO POWER_UP_SLOT_10_DURATI POWER_UP_SLOT_11_DURATI
N
N
ON
ON
R/W-X
R/W-X
R/W-X
R/W-X
表7-33. POWER_UP_SLOT_DURATION_3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
POWER_UP_SLOT_8_D R/W
URATION
X
Duration of slot 8 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4
3-2
1-0
POWER_UP_SLOT_9_D R/W
URATION
X
X
X
Duration of slot 9 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_UP_SLOT_10_D R/W
URATION
Duration of slot 10 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_UP_SLOT_11_D R/W
URATION
Duration of slot 11 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
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7.6.26 POWER_UP_SLOT_DURATION_4 Register (Offset = 19h) [Reset = X]
POWER_UP_SLOT_DURATION_4 is shown in 图7-37 and described in 表7-34.
Return to the Summary Table.
图7-37. POWER_UP_SLOT_DURATION_4 Register
7
6
5
4
3
2
1
0
POWER_UP_SLOT_12_DURATI POWER_UP_SLOT_13_DURATI POWER_UP_SLOT_14_DURATI POWER_UP_SLOT_15_DURATI
ON
ON
ON
ON
R/W-X
R/W-X
R/W-X
R/W-X
表7-34. POWER_UP_SLOT_DURATION_4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
POWER_UP_SLOT_12_D R/W
URATION
X
Duration of slot 12 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4
3-2
1-0
POWER_UP_SLOT_13_D R/W
URATION
X
X
X
Duration of slot 13 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_UP_SLOT_14_D R/W
URATION
Duration of slot 14 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_UP_SLOT_15_D R/W
URATION
Duration of slot 15 during the power-up and standby-to-active
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
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7.6.27 POWER_DOWN_SLOT_DURATION_1 Register (Offset = 1Ah) [Reset = X]
POWER_DOWN_SLOT_DURATION_1 is shown in 图7-38 and described in 表7-35.
Return to the Summary Table.
图7-38. POWER_DOWN_SLOT_DURATION_1 Register
7
6
5
4
3
2
1
0
POWER_DOWN_SLOT_0_DUR POWER_DOWN_SLOT_1_DUR POWER_DOWN_SLOT_2_DUR POWER_DOWN_SLOT_3_DUR
ATION
ATION
ATION
ATION
R/W-X
R/W-X
R/W-X
R/W-X
表7-35. POWER_DOWN_SLOT_DURATION_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
POWER_DOWN_SLOT_0 R/W
_DURATION
X
Duration of slot 0 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4
3-2
1-0
POWER_DOWN_SLOT_1 R/W
_DURATION
X
X
X
Duration of slot 1 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_DOWN_SLOT_2 R/W
_DURATION
Duration of slot 2 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_DOWN_SLOT_3 R/W
_DURATION
Duration of slot 3 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
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7.6.28 POWER_DOWN_SLOT_DURATION_2 Register (Offset = 1Bh) [Reset = X]
POWER_DOWN_SLOT_DURATION_2 is shown in 图7-39 and described in 表7-36.
Return to the Summary Table.
图7-39. POWER_DOWN_SLOT_DURATION_2 Register
7
6
5
4
3
2
1
0
POWER_DOWN_SLOT_4_DUR POWER_DOWN_SLOT_5_DUR POWER_DOWN_SLOT_6_DUR POWER_DOWN_SLOT_7_DUR
ATION
ATION
ATION
ATION
R/W-X
R/W-X
R/W-X
R/W-X
表7-36. POWER_DOWN_SLOT_DURATION_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
POWER_DOWN_SLOT_4 R/W
_DURATION
X
Duration of slot 4 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4
3-2
1-0
POWER_DOWN_SLOT_5 R/W
_DURATION
X
X
X
Duration of slot 5 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_DOWN_SLOT_6 R/W
_DURATION
Duration of slot 6 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_DOWN_SLOT_7 R/W
_DURATION
Duration of slot 7 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
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7.6.29 POWER_DOWN_SLOT_DURATION_3 Register (Offset = 1Ch) [Reset = X]
POWER_DOWN_SLOT_DURATION_3 is shown in 图7-40 and described in 表7-37.
Return to the Summary Table.
图7-40. POWER_DOWN_SLOT_DURATION_3 Register
7
6
5
4
3
2
1
0
POWER_DOWN_SLOT_8_DUR POWER_DOWN_SLOT_9_DUR POWER_DOWN_SLOT_10_DU POWER_DOWN_SLOT_11_DUR
ATION
ATION
RATION
ATION
R/W-X
R/W-X
R/W-X
R/W-X
表7-37. POWER_DOWN_SLOT_DURATION_3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
POWER_DOWN_SLOT_8 R/W
_DURATION
X
Duration of slot 8 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4
3-2
1-0
POWER_DOWN_SLOT_9 R/W
_DURATION
X
X
X
Duration of slot 9 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_DOWN_SLOT_1 R/W
0_DURATION
Duration of slot 10 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_DOWN_SLOT_1 R/W
1_DURATION
Duration of slot 11 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
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7.6.30 POWER_DOWN_SLOT_DURATION_4 Register (Offset = 1Dh) [Reset = X]
POWER_DOWN_SLOT_DURATION_4 is shown in 图7-41 and described in 表7-38.
Return to the Summary Table.
图7-41. POWER_DOWN_SLOT_DURATION_4 Register
7
6
5
4
3
2
1
0
POWER_DOWN_SLOT_12_DU POWER_DOWN_SLOT_13_DU POWER_DOWN_SLOT_14_DU POWER_DOWN_SLOT_15_DU
RATION
RATION
RATION
RATION
R/W-X
R/W-X
R/W-X
R/W-X
表7-38. POWER_DOWN_SLOT_DURATION_4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
POWER_DOWN_SLOT_1 R/W
2_DURATION
X
Duration of slot 12 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4
3-2
1-0
POWER_DOWN_SLOT_1 R/W
3_DURATION
X
X
X
Duration of slot 13 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_DOWN_SLOT_1 R/W
4_DURATION
Duration of slot 14 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
POWER_DOWN_SLOT_1 R/W
5_DURATION
Duration of slot 15 during the power-down and active-to-standby
sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
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7.6.31 GENERAL_CONFIG Register (Offset = 1Eh) [Reset = X]
GENERAL_CONFIG is shown in 图7-42 and described in 表7-39.
Return to the Summary Table.
图7-42. GENERAL_CONFIG Register
7
6
5
4
3
2
1
0
BYPASS_RAIL LDO4_UV_THR LDO3_UV_THR LDO2_UV_THR LDO1_UV_THR
GPIO_EN
GPO2_EN
GPO1_EN
S_DISCHARGE
D_CHECK
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
表7-39. GENERAL_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BYPASS_RAILS_DISCHA R/W
RGED_CHECK
X
Bypass the all-rails discharged check to commence a transition to
ACTIVE state, and the rails-in-slot discharged check executed in
each slot during a power-down to INITIALIZE state. Does not bypass
the check for RV(Pre-biased) condition prior to enabling a regulator.
(Default from NVM memory)
0h = Discharged checks enforced
1h = Discharged checks bypassed
6
5
4
3
2
LDO4_UV_THR
LDO3_UV_THR
LDO2_UV_THR
LDO1_UV_THR
GPIO_EN
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
UV threshold selection bit for LDO4. Only applicable if configured as
LDO. (Default from NVM memory)
0h = -5% UV detection
1h = -10% UV detection
UV threshold selection bit for LDO3. Only applicable if configured as
LDO. (Default from NVM memory)
0h = -5% UV detection
1h = -10% UV detection
UV threshold selection bit for LDO2. Only applicable if configured as
LDO. (Default from NVM memory)
0h = -5% UV detection
1h = -10% UV detection
UV threshold selection bit for LDO1. Only applicable if configured as
LDO. (Default from NVM memory)
0h = -5% UV detection
1h = -10% UV detection
Both an enable and state control of GPIO. This bit enables the GPIO
function and also controls the state of the GPIO pin. (Default from
NVM memory)
0h = The GPIO function is disabled. The output state is 'low'.
1h = The GPIO function is enabled. The output state is 'high'.
1
0
GPO2_EN
GPO1_EN
R/W
R/W
X
X
Both an enable and state control of GPO2. This bit enables the
GPO2 function and also controls the state of the GPO2 pin. (Default
from NVM memory)
0h = GPO2 disabled. The output state is low.
1h = GPO2 enabled. The output state is Hi-Z.
Both an enable and state control of GPO1. This bit enables the
GPO1 function and also controls the state of the GPO1 pin. (Default
from NVM memory)
0h = GPO1 disabled. The output state is low.
1h = GPO1 enabled. The output state is Hi-Z.
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7.6.32 MFP_1_CONFIG Register (Offset = 1Fh) [Reset = X]
MFP_1_CONFIG is shown in 图7-43 and described in 表7-40.
Return to the Summary Table.
图7-43. MFP_1_CONFIG Register
7
6
5
4
3
2
1
0
MODE_I2C_CT VSEL_SD_I2C_ MODE_RESET MODE_STBY_ MULTI_DEVICE
VSEL_RAIL
VSEL_SD_POL VSEL_DDR_SD
ARITY
RL
CTRL
_POLARITY
POLARITY
_ENABLE
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
表7-40. MFP_1_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MODE_I2C_CTRL
R/W
X
MODE control using I2C. Consolidated with MODE control via
MODE/RESET and/or MODE/STBY pins. Refer to table in the data
sheet. (Default from NVM memory)
0h = Auto PFM
1h = Forced PWM
6
5
VSEL_SD_I2C_CTRL
R/W
X
X
VSEL_SD control using I2C. Applicable only if VSEL_SD/
VSEL_DDR pin is configured as "VSEL_DDR". (Default from NVM
memory)
0h = 1.8V
1h = LDOx_VOUT register setting
MODE_RESET_POLARIT R/W
Y
MODE_RESET Pin Polarity configuration. Note: Ok to change during
operation, but consider immediate reaction: MODE-change or
RESET-entry! (Default from NVM memory)
0h = [if configured as MODE] LOW - auto-PFM / HIGH - forced
PWM. [if configured as RESET] LOW - reset / HIGH - normal
operation.
1h = [if configured as MODE] HIGH - auto-PFM / LOW - forced
PWM. [if configured as RESET] HIGH - reset / LOW - normal
operation.
4
MODE_STBY_POLARITY R/W
X
MODE_STBY Pin Polarity configuration. Note: Ok to change during
operation, but consider immediate reaction: MODE-change or
STATE-change! (Default from NVM memory)
0h = [if configured as MODE] LOW - auto-PFM / HIGH - forced
PWM. [if configured as a STBY] LOW - STBY state / HIGH - ACTIVE
state.
1h = [if configured as MODE] HIGH - auto-PFM / LOW - forced
PWM. [if configured as a STBY] HIGH - STBY state / LOW - ACTIVE
state.
3
MULTI_DEVICE_ENABLE R/W
X
Configures the device as a single device where GPO is used as
GPO function, or as a multi-device configuration where GPO is used
for synchronization with other devices. NOTE: ONLY CHANGE IN
INITIALIZE STATE! (Default from NVM memory)
0h = Single-device configuration, GPIO pin configured as GPO
1h = Multi-device configuration, GPIO pin configured as GPIO
2
1
VSEL_RAIL
R/W
R/W
X
X
LDO controlled by VSEL_SD/VSEL_DDR. NOTE: ONLY CHANGE
IN INITIALIZE STATE! (Default from NVM memory)
0h = LDO1
1h = LDO2
VSEL_SD_POLARITY
SD Card Voltage Select Note: Ok to change during operation, but
consider immediate reaction: change of SD-card supply voltage!
(Default from NVM memory)
0h = LOW - 1.8V / HIGH - LDOx_VOUT register setting
1h = HIGH - 1.8V / LOW - LDOx_VOUT register setting
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表7-40. MFP_1_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
VSEL_DDR_SD
R/W
X
VSEL_SD/VSEL_DDR Configuration NOTE: ONLY CHANGE IN
INITIALIZE STATE! (Default from NVM memory)
0h = VSEL pin configured as DDR to set the voltage on Buck3
1h = VSEL pin configured as SD to set the voltage on the
VSEL_RAIL
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7.6.33 MFP_2_CONFIG Register (Offset = 20h) [Reset = X]
MFP_2_CONFIG is shown in 图7-44 and described in 表7-41.
Return to the Summary Table.
图7-44. MFP_2_CONFIG Register
7
6
5
4
3
2
1
0
PU_ON_FSD WARM_COLD_
EN_PB_VSENSE_CONFIG
EN_PB_VSENS MODE_RESET
MODE_STBY_CONFIG
RESET_CONFI
G
E_DEGL
_CONFIG
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
表7-41. MFP_2_CONFIG Register Field Descriptions
Bit
Field
PU_ON_FSD
Type
Reset
Description
7
R/W
X
Power up upon First Supply Detected (FSD). So when VSYS is
applied, device does power up to ACTIVE state even if EN/PB/
VSENSE pin is at OFF_REQ status. (Default from NVM memory)
0h = First Supply Detection (FSD) Disabled.
1h = First Supply Detection (FSD) Enabled.
6
WARM_COLD_RESET_C R/W
ONFIG
X
X
Selection between WARM or COLD Reset, when a RESET event is
triggered via MODE/RESET pin (does not apply to RESET via I2C)
(Default from NVM memory)
0h = COLD RESET
1h = WARM RESET
5-4
EN_PB_VSENSE_CONFI R/W
G
Enable / Push-Button / VSENSE Configuration. Do not change via
I2C after NVM load (except as a precursor before programming
NVM) (Default from NVM memory)
0h = Device Enable Configuration
1h = Push Button Configuration
2h = VSENSE Configuration
3h = Device Enable Configuration
3
EN_PB_VSENSE_DEGL R/W
MODE_RESET_CONFIG R/W
X
Enable / Push-Button / VSENSE Deglitch NOTE: ONLY CHANGE IN
INITIALIZE STATE! Consider immediate reaction when changing
from EN/VSENSE to PB or vice versa: power-up! (Default from NVM
memory)
0h = short (typ: 120us for EN/VSENSE and 200ms for PB)
1h = long (typ: 50ms for EN/VSENSE and 600ms for PB)
2
X
X
MODE/RESET Configuration (Default from NVM memory)
0h = MODE
1h = RESET
1-0
MODE_STBY_CONFIG
R/W
MODE_STDBY Configuration (Default from NVM memory)
0h = MODE
1h = STBY
2h = MODE and STBY
3h = MODE
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7.6.34 STBY_1_CONFIG Register (Offset = 21h) [Reset = X]
STBY_1_CONFIG is shown in 图7-45 and described in 表7-42.
Return to the Summary Table.
图7-45. STBY_1_CONFIG Register
7
6
5
4
3
2
1
0
RESERVED
LDO4_STBY_E LDO3_STBY_E LDO2_STBY_E LDO1_STBY_E BUCK3_STBY_ BUCK2_STBY_ BUCK1_STBY_
N
N
N
N
EN
EN
EN
R-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
表7-42. STBY_1_CONFIG Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
X
X
Reserved
6
LDO4_STBY_EN
LDO3_STBY_EN
LDO2_STBY_EN
LDO1_STBY_EN
BUCK3_STBY_EN
BUCK2_STBY_EN
BUCK1_STBY_EN
R/W
Enable LDO4 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
Enable LDO3 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
Enable LDO2 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
Enable LDO1 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
Enable BUCK3 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
Enable BUCK2 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
Enable BUCK1 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
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7.6.35 STBY_2_CONFIG Register (Offset = 22h) [Reset = X]
STBY_2_CONFIG is shown in 图7-46 and described in 表7-43.
Return to the Summary Table.
图7-46. STBY_2_CONFIG Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
R-X
RESERVED
R-X
RESERVED
R-X
GPIO_STBY_E GPO2_STBY_E GPO1_STBY_E
N
N
N
R-X
R-X
R/W-X
R/W-X
R/W-X
表7-43. STBY_2_CONFIG Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
Reserved
Reserved
Reserved
Reserved
Reserved
R
X
X
X
X
X
X
6
RESERVED
RESERVED
RESERVED
RESERVED
GPIO_STBY_EN
R
5
R
4
R
3
R
2
R/W
Enable GPIO in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
1
0
GPO2_STBY_EN
GPO1_STBY_EN
R/W
R/W
X
X
Enable GPO2 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
Enable GPO1 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
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7.6.36 OC_DEGL_CONFIG Register (Offset = 23h) [Reset = X]
OC_DEGL_CONFIG is shown in 图7-47 and described in 表7-44.
Return to the Summary Table.
图7-47. OC_DEGL_CONFIG Register
7
6
5
4
3
2
1
0
RESERVED
EN_LONG_DE EN_LONG_DE EN_LONG_DE EN_LONG_DE EN_LONG_DE EN_LONG_DE EN_LONG_DE
GL_FOR_OC_L GL_FOR_OC_L GL_FOR_OC_L GL_FOR_OC_L GL_FOR_OC_ GL_FOR_OC_ GL_FOR_OC_
DO4
DO3
DO2
DO1
BUCK3
BUCK2
BUCK1
R-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
表7-44. OC_DEGL_CONFIG Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
X
X
Reserved
6
EN_LONG_DEGL_FOR_ R/W
OC_LDO4
When set, enables the long-deglitch option for OverCurrent signal of
LDO4. When clear, enables the short-deglitch option for OverCurrent
signal of LDO4. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals of LDO4 is ~20us
1h = Deglitch duration for OverCurrent signals of LDO4 is ~2ms
5
4
3
2
EN_LONG_DEGL_FOR_ R/W
OC_LDO3
X
X
X
X
When set, enables the long-deglitch option for OverCurrent signal of
LDO3. When clear, enables the short-deglitch option for OverCurrent
signal of LDO3. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals of LDO3 is ~20us
1h = Deglitch duration for OverCurrent signals of LDO3 is ~2ms
EN_LONG_DEGL_FOR_ R/W
OC_LDO2
When set, enables the long-deglitch option for OverCurrent signal of
LDO2. When clear, enables the short-deglitch option for OverCurrent
signal of LDO2. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals of LDO2 is ~20us
1h = Deglitch duration for OverCurrent signals of LDO2 is ~2ms
EN_LONG_DEGL_FOR_ R/W
OC_LDO1
When set, enables the long-deglitch option for OverCurrent signal of
LDO1. When clear, enables the short-deglitch option for OverCurrent
signal of LDO1. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals of LDO1 is ~20us
1h = Deglitch duration for OverCurrent signals of LDO1 is ~2ms
EN_LONG_DEGL_FOR_ R/W
OC_BUCK3
When set, enables the long-deglitch option for OverCurrent signals
of BUCK3. When clear, enables the short-deglitch option for
OverCurrent signals of BUCK3. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals for BUCK3 (High-Side
Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative
OverCurrent) is ~20us
1h = Deglitch duration for OverCurrent signals for BUCK3 (High-Side
Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative
OverCurrent) is ~2ms
1
EN_LONG_DEGL_FOR_ R/W
OC_BUCK2
X
When set, enables the long-deglitch option for OverCurrent signals
of BUCK2. When clear, enables the short-deglitch option for
OverCurrent signals of BUCK2. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals for BUCK2 (High-Side
Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative
OverCurrent) is ~20us
1h = Deglitch duration for OverCurrent signals for BUCK2 (High-Side
Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative
OverCurrent) is ~2ms
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表7-44. OC_DEGL_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
EN_LONG_DEGL_FOR_ R/W
OC_BUCK1
X
When set, enables the long-deglitch option for OverCurrent signals
of BUCK1. When clear, enables the short-deglitch option for
OverCurrent signals of BUCK1. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals for BUCK1 (High-Side
Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative
OverCurrent) is ~20us
1h = Deglitch duration for OverCurrent signals for BUCK1 (High-Side
Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative
OverCurrent) is ~2ms
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7.6.37 INT_MASK_UV Register (Offset = 24h) [Reset = X]
INT_MASK_UV is shown in 图7-48 and described in 表7-45.
Return to the Summary Table.
图7-48. INT_MASK_UV Register
7
6
5
4
3
2
1
0
MASK_RETRY BUCK3_UV_M BUCK2_UV_M BUCK1_UV_M LDO4_UV_MA LDO3_UV_MA LDO2_UV_MA LDO1_UV_MA
_COUNT
ASK
ASK
ASK
SK
SK
SK
SK
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
表7-45. INT_MASK_UV Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MASK_RETRY_COUNT
R/W
X
When set, device can power up even after two retries. (Default from
NVM memory)
0h = Device does retry up to 2 times, then stay off
1h = Device does retry infinitely
6
5
4
3
BUCK3_UV_MASK
BUCK2_UV_MASK
BUCK1_UV_MASK
LDO4_UV_MASK
R/W
R/W
R/W
R/W
X
X
X
X
BUCK3 Undervoltage Mask. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
BUCK2 Undervoltage Mask. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
BUCK1 Undervoltage Mask. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
LDO4 Undervoltage Mask - Always masked in BYP or LSW modes.
(Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
2
1
0
LDO3_UV_MASK
LDO2_UV_MASK
LDO1_UV_MASK
R/W
R/W
R/W
X
X
X
LDO3 Undervoltage Mask - Always masked in BYP or LSW modes.
(Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
LDO2 Undervoltage Mask - Always masked in BYP or LSW modes.
(Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
LDO1 Undervoltage Mask - Always masked in BYP or LSW modes.
(Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
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7.6.38 MASK_CONFIG Register (Offset = 25h) [Reset = X]
MASK_CONFIG is shown in 图7-49 and described in 表7-46.
Return to the Summary Table.
图7-49. MASK_CONFIG Register
7
6
5
4
3
2
1
0
MASK_INT_FO
R_PB
MASK_EFFECT
MASK_INT_FO SENSOR_0_W SENSOR_1_W SENSOR_2_W SENSOR_3_W
R_RV
ARM_MASK
ARM_MASK
ARM_MASK
ARM_MASK
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
表7-46. MASK_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MASK_INT_FOR_PB
R/W
X
Masking bit to control whether nINT pin is sensitive to PushButton
(PB) press/release events or not. (Default from NVM memory)
0h = un-masked (nINT pulled low for any PB events)
1h = masked (nINT not sensitive to any PB events)
6-5
4
MASK_EFFECT
R/W
R/W
X
X
Effect of masking (global) (Default from NVM memory)
0h = no state change, no nINT reaction, no bit set for Faults
1h = no state change, no nINT reaction, bit set for Faults
2h = no state change, nINT reaction, bit set for Faults (same as 11b)
3h = no state change, nINT reaction, bit set for Faults (same as 10b)
MASK_INT_FOR_RV
Masking bit to control whether nINT pin is sensitive to RV (Residual
Voltage) events or not. (Default from NVM memory)
0h = un-masked (nINT pulled low for any RV events during transition
to ACTIVE state or during enabling of rails)
1h = masked (nINT not sensitive to any RV events)
3
2
1
0
SENSOR_0_WARM_MAS R/W
K
X
X
X
X
Die Temperature Warm Fault Mask, Sensor 0. (Default from NVM
memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
SENSOR_1_WARM_MAS R/W
K
Die Temperature Warm Fault Mask, Sensor 1. (Default from NVM
memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
SENSOR_2_WARM_MAS R/W
K
Die Temperature Warm Fault Mask, Sensor 2. (Default from NVM
memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
SENSOR_3_WARM_MAS R/W
K
Die Temperature Warm Fault Mask, Sensor 3. (Default from NVM
memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
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7.6.39 I2C_ADDRESS_REG Register (Offset = 26h) [Reset = X]
I2C_ADDRESS_REG is shown in 图7-50 and described in 表7-47.
Return to the Summary Table.
图7-50. I2C_ADDRESS_REG Register
7
6
5
4
3
2
1
0
DIY_NVM_PRO
GRAM_CMD_I
SSUED
I2C_ADDRESS
R/W-X
R/W-X
表7-47. I2C_ADDRESS_REG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DIY_NVM_PROGRAM_C R/W
MD_ISSUED
X
Bit that indicates whether a DIY program command was attempted.
Once set, remains always set. (Default from NVM memory)
0h = NVM data not changed
1h = NVM data attempted to be changed via DIY program command
6-0
I2C_ADDRESS
R/W
X
I2C secondary address. Note: Ok to change during operation, but
consider immediate reaction: new address for read/write! (Default
from NVM memory)
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7.6.40 USER_GENERAL_NVM_STORAGE_REG Register (Offset = 27h) [Reset = X]
USER_GENERAL_NVM_STORAGE_REG is shown in 图7-51 and described in 表7-48.
Return to the Summary Table.
图7-51. USER_GENERAL_NVM_STORAGE_REG Register
7
6
5
4
3
2
1
0
USER_GENERAL_NVM_STORAGE
R/W-X
表7-48. USER_GENERAL_NVM_STORAGE_REG Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
USER_GENERAL_NVM_ R/W
STORAGE
X
8-bit NVM-based register available to the user to use to store user-
data, for example NVM-ID of customer-modified NVM-version or
other purposes. (Default from NVM memory)
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7.6.41 MANUFACTURING_VER Register (Offset = 28h) [Reset = 00h]
MANUFACTURING_VER is shown in 图7-52 and described in 表7-49.
Return to the Summary Table.
图7-52. MANUFACTURING_VER Register
7
6
5
4
3
2
1
0
SILICON_REV
R-0h
表7-49. MANUFACTURING_VER Register Field Descriptions
Bit
7-0
Field
SILICON_REV
Type
Reset
Description
R
0h
SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR
SILICON_REV[2:0] - Metal Silicon Revision - Hard wired (not under
NVM control)
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7.6.42 MFP_CTRL Register (Offset = 29h) [Reset = X]
MFP_CTRL is shown in 图7-53 and described in 表7-50.
Return to the Summary Table.
图7-53. MFP_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
GPIO_STATUS WARM_RESET COLD_RESET_ STBY_I2C_CT I2C_OFF_REQ
_I2C_CTRL
I2C_CTRL
RL
R-X
R-X
R-X
R-0h
R/WSelfClrF-0h
R/W-0h
R/W-0h
R/WSelfClrF-0h
表7-50. MFP_CTRL Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
Reserved
Reserved
Reserved
R
X
6
RESERVED
RESERVED
GPIO_STATUS
R
X
5
R
X
4
R
0h
Indicates the real-time value of GPIO pin
0h = The GPIO pin is currently '0'
1h = The GPIO pin is currently '1'
3
2
1
0
WARM_RESET_I2C_CTR R/WSelfClrF 0h
L
Triggers a WARM RESET when written as '1'. Note: This bit self-
clears automatically, so cannot be read as '1' after the write.
0h = normal operation
1h = WARM_RESET
COLD_RESET_I2C_CTR R/W
L
0h
0h
Triggers a COLD RESET when set high. Cleared upon entry to
INITIALIZE.
0h = normal operation
1h = COLD_RESET
STBY_I2C_CTRL
I2C_OFF_REQ
R/W
STBY control using I2C. Consolidated with STBY control via MODE/
STBY pin. Refer to table in spec.
0h = normal operation
1h = STBY mode
R/WSelfClrF 0h
When '1' is written to this bit: Trigger OFF request. When '0': No
effect. Does self-clear.
0h = No effect
1h = Trigger OFF Request
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7.6.43 DISCHARGE_CONFIG Register (Offset = 2Ah) [Reset = X]
DISCHARGE_CONFIG is shown in 图7-54 and described in 表7-51.
Return to the Summary Table.
图7-54. DISCHARGE_CONFIG Register
7
6
5
4
3
2
1
0
RESERVED
LDO4_DISCHA LDO3_DISCHA LDO2_DISCHA LDO1_DISCHA BUCK3_DISCH BUCK2_DISCH BUCK1_DISCH
RGE_EN
RGE_EN
RGE_EN
RGE_EN
ARGE_EN
ARGE_EN
ARGE_EN
R-X
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
表7-51. DISCHARGE_CONFIG Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
X
Reserved
6
LDO4_DISCHARGE_EN R/W
LDO3_DISCHARGE_EN R/W
LDO2_DISCHARGE_EN R/W
LDO1_DISCHARGE_EN R/W
BUCK3_DISCHARGE_EN R/W
BUCK2_DISCHARGE_EN R/W
BUCK1_DISCHARGE_EN R/W
1h
Discharge setting for LDO4
0h = No Discharge
1h = 250 Ω
5
4
3
2
1
0
1h
1h
1h
1h
1h
1h
Discharge setting for LDO3
0h = No Discharge
1h = 250 Ω
Discharge setting for LDO2
0h = No Discharge
1h = 200 Ω
Discharge setting for LDO1
0h = No Discharge
1h = 200 Ω
Discharge setting for BUCK3
0h = No Discharge
1h = 125 Ω
Discharge setting for BUCK2
0h = No Discharge
1h = 125 Ω
Discharge setting for BUCK1
0h = No Discharge
1h = 125 Ω
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7.6.44 INT_SOURCE Register (Offset = 2Bh) [Reset = 00h]
INT_SOURCE is shown in 图7-55 and described in 表7-52.
Return to the Summary Table.
图7-55. INT_SOURCE Register
7
6
5
4
3
2
1
0
INT_PB_IS_SE INT_LDO_3_4_ INT_LDO_1_2_ INT_BUCK_3_I INT_BUCK_1_2 INT_SYSTEM_I INT_RV_IS_SE INT_TIMEOUT_
T
IS_SET
IS_SET
S_SET
_IS_SET
S_SET
T
RV_SD_IS_SE
T
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表7-52. INT_SOURCE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
3
2
1
0
INT_PB_IS_SET
R
0h
One or more sources of the INT present in register INT_PB
0h = No bits set in INT_PB
1h = One or more bits set in INT_PB
INT_LDO_3_4_IS_SET
INT_LDO_1_2_IS_SET
INT_BUCK_3_IS_SET
INT_BUCK_1_2_IS_SET
INT_SYSTEM_IS_SET
INT_RV_IS_SET
R
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
0h
One or more sources of the INT present in register INT_LDO_3_4
0h = No bits set in INT_LDO_3_4
1h = One or more bits set in INT_LDO_3_4
One or more sources of the INT present in register INT_LDO_1_2
0h = No bits set in INT_LDO_1_2
1h = One or more bits set in INT_LDO_1_2
One or more sources of the INT present in register INT_BUCK_3
0h = No bits set in INT_BUCK_3
1h = One or more bits set in INT_BUCK_3
One or more sources of the INT present in register INT_BUCK_1_2
0h = No bits set in INT_BUCK_1_2
1h = One or more bits set in INT_BUCK_1_2
One or more sources of the INT present in register INT_SYSTEM
0h = No bits set in INT_SYSTEM
1h = One or more bits set in INT_SYSTEM
One or more sources of the INT present in register INT_RV
0h = No bits set in INT_RV
1h = One or more bits set in INT_RV
INT_TIMEOUT_RV_SD_I
S_SET
One or more sources of the INT present in register
INT_TIMEOUT_RV_SD
0h = No bits set in INT_TIMEOUT_RV_SD
1h = One or more bits set in INT_TIMEOUT_RV_SD
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7.6.45 INT_LDO_3_4 Register (Offset = 2Ch) [Reset = X]
INT_LDO_3_4 is shown in 图7-56 and described in 表7-53.
Return to the Summary Table.
图7-56. INT_LDO_3_4 Register
7
6
5
4
3
2
1
0
RESERVED
R-X
RESERVED
R-X
LDO4_UV
R/W1C-0h
LDO4_OC
R/W1C-0h
LDO4_SCG
R/W1C-0h
LDO3_UV
R/W1C-0h
LDO3_OC
R/W1C-0h
LDO3_SCG
R/W1C-0h
表7-53. INT_LDO_3_4 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
Reserved
Reserved
R
X
6
RESERVED
LDO4_UV
R
X
5
R/W1C
0h
LDO4 Undervoltage Fault. Is automatically cleared upon a transition
to INITIALIZE state, if corresponding *_UV_MASK bit in register
INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
4
3
2
LDO4_OC
LDO4_SCG
LDO3_UV
R/W1C
R/W1C
R/W1C
0h
0h
0h
LDO4 Overcurrent Fault.
0h = No Fault detected
1h = Fault detected
LDO4 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected
LDO3 Undervoltage Fault. Is automatically cleared upon a transition
to INITIALIZE state, if corresponding *_UV_MASK bit in register
INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
1
0
LDO3_OC
R/W1C
R/W1C
0h
0h
LDO3 Overcurrent Fault
0h = No Fault detected
1h = Fault detected
LDO3_SCG
LDO3 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected
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7.6.46 INT_LDO_1_2 Register (Offset = 2Dh) [Reset = X]
INT_LDO_1_2 is shown in 图7-57 and described in 表7-54.
Return to the Summary Table.
图7-57. INT_LDO_1_2 Register
7
6
5
4
3
2
1
0
RESERVED
R-X
RESERVED
R-X
LDO2_UV
R/W1C-0h
LDO2_OC
R/W1C-0h
LDO2_SCG
R/W1C-0h
LDO1_UV
R/W1C-0h
LDO1_OC
R/W1C-0h
LDO1_SCG
R/W1C-0h
表7-54. INT_LDO_1_2 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
Reserved
Reserved
R
X
6
RESERVED
LDO2_UV
R
X
5
R/W1C
0h
LDO2 Undervoltage Fault. Is automatically cleared upon a transition
to INITIALIZE state, if corresponding *_UV_MASK bit in register
INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
4
3
2
LDO2_OC
LDO2_SCG
LDO1_UV
R/W1C
R/W1C
R/W1C
0h
0h
0h
LDO2 Overcurrent Fault
0h = No Fault detected
1h = Fault detected
LDO2 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected
LDO1 Undervoltage Fault. Is automatically cleared upon a transition
to INITIALIZE state, if corresponding *_UV_MASK bit in register
INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
1
0
LDO1_OC
R/W1C
R/W1C
0h
0h
LDO1 Overcurrent Fault
0h = No Fault detected
1h = Fault detected
LDO1_SCG
LDO1 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected
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7.6.47 INT_BUCK_3 Register (Offset = 2Eh) [Reset = X]
INT_BUCK_3 is shown in 图7-58 and described in 表7-55.
Return to the Summary Table.
图7-58. INT_BUCK_3 Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
BUCK3_UV
BUCK3_NEG_
OC
BUCK3_OC
BUCK3_SCG
R-X
R-X
R-X
R-X
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
表7-55. INT_BUCK_3 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
Reserved
Reserved
Reserved
Reserved
R
X
6
RESERVED
RESERVED
RESERVED
BUCK3_UV
R
X
5
R
X
4
R
X
3
R/W1C
0h
BUCK3 Undervoltage Fault. Is automatically cleared upon a
transition to INITIALIZE state, if corresponding *_UV_MASK bit in
register INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
2
1
0
BUCK3_NEG_OC
BUCK3_OC
R/W1C
R/W1C
R/W1C
0h
0h
0h
BUCK3 Negative Overcurrent Fault
0h = No Fault detected
1h = Fault detected
BUCK3 Positive Overcurrent Fault
0h = No Fault detected
1h = Fault detected
BUCK3_SCG
BUCK3 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected
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7.6.48 INT_BUCK_1_2 Register (Offset = 2Fh) [Reset = 00h]
INT_BUCK_1_2 is shown in 图7-59 and described in 表7-56.
Return to the Summary Table.
图7-59. INT_BUCK_1_2 Register
7
6
5
4
3
2
1
0
BUCK2_UV
BUCK2_NEG_
OC
BUCK2_OC
BUCK2_SCG
BUCK1_UV
BUCK1_NEG_
OC
BUCK1_OC
BUCK1_SCG
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
表7-56. INT_BUCK_1_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BUCK2_UV
R/W1C
0h
BUCK2 Undervoltage Fault. Is automatically cleared upon a
transition to INITIALIZE state, if corresponding *_UV_MASK bit in
register INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
6
5
4
3
BUCK2_NEG_OC
BUCK2_OC
R/W1C
R/W1C
R/W1C
R/W1C
0h
0h
0h
0h
BUCK2 Negative Overcurrent Fault
0h = No Fault detected
1h = Fault detected
BUCK2 Positive Overcurrent Fault
0h = No Fault detected
1h = Fault detected
BUCK2_SCG
BUCK1_UV
BUCK2 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected
BUCK1 Undervoltage Fault. Is automatically cleared upon a
transition to INITIALIZE state, if corresponding *_UV_MASK bit in
register INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
2
1
0
BUCK1_NEG_OC
BUCK1_OC
R/W1C
R/W1C
R/W1C
0h
0h
0h
BUCK1 Negative Overcurrent Fault
0h = No Fault detected
1h = Fault detected
BUCK1 Positive Overcurrent Fault
0h = No Fault detected
1h = Fault detected
BUCK1_SCG
BUCK1 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected
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7.6.49 INT_SYSTEM Register (Offset = 30h) [Reset = 00h]
INT_SYSTEM is shown in 图7-60 and described in 表7-57.
Return to the Summary Table.
图7-60. INT_SYSTEM Register
7
6
5
4
3
2
1
0
SENSOR_0_H SENSOR_1_H SENSOR_2_H SENSOR_3_H SENSOR_0_W SENSOR_1_W SENSOR_2_W SENSOR_3_W
OT
OT
OT
OT
ARM
ARM
ARM
ARM
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
R/W1C-0h
表7-57. INT_SYSTEM Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SENSOR_0_HOT
SENSOR_1_HOT
SENSOR_2_HOT
SENSOR_3_HOT
SENSOR_0_WARM
R/W1C
0h
TSD Hot detection for sensor 0
0h = No Fault detected
1h = Fault detected
6
5
4
3
R/W1C
R/W1C
R/W1C
R/W1C
0h
0h
0h
0h
TSD Hot detection for sensor 1
0h = No Fault detected
1h = Fault detected
TSD Hot detection for sensor 2
0h = No Fault detected
1h = Fault detected
TSD Hot detection for sensor 3
0h = No Fault detected
1h = Fault detected
TSD Warm detection for sensor 0. Is automatically cleared upon a
transition to INITIALIZE state, if corresponding *_WARM_MASK bit
in register MASK_CONFIG is '1'
0h = No Fault detected
1h = Fault detected
2
1
0
SENSOR_1_WARM
SENSOR_2_WARM
SENSOR_3_WARM
R/W1C
R/W1C
R/W1C
0h
0h
0h
TSD Warm detection for sensor 1. Is automatically cleared upon a
transition to INITIALIZE state, if corresponding *_WARM_MASK bit
in register MASK_CONFIG is '1'
0h = No Fault detected
1h = Fault detected
TSD Warm detection for sensor 2. Is automatically cleared upon a
transition to INITIALIZE state, if corresponding *_WARM_MASK bit
in register MASK_CONFIG is '1'
0h = No Fault detected
1h = Fault detected
TSD Warm detection for sensor 3. Is automatically cleared upon a
transition to INITIALIZE state, if corresponding *_WARM_MASK bit
in register MASK_CONFIG is '1'
0h = No Fault detected
1h = Fault detected
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7.6.50 INT_RV Register (Offset = 31h) [Reset = X]
INT_RV is shown in 图7-61 and described in 表7-58.
Return to the Summary Table.
图7-61. INT_RV Register
7
6
5
4
3
2
1
0
RESERVED
R-X
LDO4_RV
R/W1C-0h
LDO3_RV
R/W1C-0h
LDO2_RV
R/W1C-0h
LDO1_RV
R/W1C-0h
BUCK3_RV
R/W1C-0h
BUCK2_RV
R/W1C-0h
BUCK1_RV
R/W1C-0h
表7-58. INT_RV Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
X
Reserved
6
LDO4_RV
LDO3_RV
LDO2_RV
LDO1_RV
BUCK3_RV
BUCK2_RV
BUCK1_RV
R/W1C
0h
RV event detected on LDO4 rail during rail-turn-on, or after 4-5 ms
during discharge checks prior to entering power sequence to
ACTIVE state
0h = No RV detected
1h = RV detected
5
4
3
2
1
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
0h
0h
0h
0h
0h
0h
RV event detected on LDO3 rail during rail-turn-on, or after 4-5 ms
during discharge checks prior to entering power sequence to
ACTIVE state
0h = No RV detected
1h = RV detected
RV event detected on LDO2 rail during rail-turn-on, or after 4-5 ms
during discharge checks prior to entering power sequence to
ACTIVE state
0h = No RV detected
1h = RV detected
RV event detected on LDO1 rail during rail-turn-on, or after 4-5 ms
during discharge checks prior to entering power sequence to
ACTIVE state
0h = No RV detected
1h = RV detected
RV event detected on BUCK3 rail during rail-turn-on, or after 4-5 ms
during discharge checks prior to entering power sequence to
ACTIVE state
0h = No RV detected
1h = RV detected
RV event detected on BUCK2 rail during rail-turn-on, or after 4-5 ms
during discharge checks prior to entering power sequence to
ACTIVE state
0h = No RV detected
1h = RV detected
RV event detected on BUCK1 rail during rail-turn-on, or after 4-5 ms
during discharge checks prior to entering power sequence to
ACTIVE state
0h = No RV detected
1h = RV detected
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7.6.51 INT_TIMEOUT_RV_SD Register (Offset = 32h) [Reset = 00h]
INT_TIMEOUT_RV_SD is shown in 图7-62 and described in 表7-59.
Return to the Summary Table.
图7-62. INT_TIMEOUT_RV_SD Register
7
6
5
4
3
2
1
0
TIMEOUT
R/W1C-0h
LDO4_RV_SD LDO3_RV_SD LDO2_RV_SD LDO1_RV_SD BUCK3_RV_SD BUCK2_RV_SD BUCK1_RV_SD
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
表7-59. INT_TIMEOUT_RV_SD Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TIMEOUT
R/W1C
0h
Is set if ShutDown occurred due to a TimeOut while: 1. Transitioning
to ACTIVE state, and one or more rails did not rise past the UV level
at the end of the assigned slot (and UV on this rail is configured as a
SD fault). Which rail(s) is/are indicated by the *_UV bits in the INT_*
registers. 2. Transitioning to STANDBY state, and one or more rails
did not fall below the SCG level at the end of the assigned slot and
discharge is enabled for that rail (which rail(s) is/are indicated by the
corresponding RV_SD bit(s) in this register).
0h = No SD due to TimeOut occurred
1h = SD due to TimeOut occurred
6
5
4
LDO4_RV_SD
R/W1C
R/W1C
R/W1C
0h
0h
0h
RV on LDO4 rail caused a shutdown during: 1. A transition to
STANDBY state, this rail did not discharge at the end of the assigned
slot and discharge is enabled for this rail 2. A transition to STANDBY
state, RV was observed on this rail during the transition after this rail
was disabled and discharge was enabled 3. A transition to ACTIVE
state, RV was observed on this rail during the transition when this rail
was OFF (rails are expected to be discharged before commencing
the sequence to ACTIVE) 4. This rail did not discharge and therefore
caused a Timeout-SD while attempting to discharge all rails at the
start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets
also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO4 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on LDO4 occurred
LDO3_RV_SD
RV on LDO4 rail caused a shutdown during: 1. A transition to
STANDBY state, this rail did not discharge at the end of the assigned
slot and discharge is enabled for this rail 2. A transition to STANDBY
state, RV was observed on this rail during the transition after this rail
was disabled and discharge was enabled 3. A transition to ACTIVE
state, RV was observed on this rail during the transition when this rail
was OFF (rails are expected to be discharged before commencing
the sequence to ACTIVE) 4. This rail did not discharge and therefore
caused a Timeout-SD while attempting to discharge all rails at the
start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets
also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO3 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on LDO3 occurred
LDO2_RV_SD
RV on LDO4 rail caused a shutdown during: 1. A transition to
STANDBY state, this rail did not discharge at the end of the assigned
slot and discharge is enabled for this rail 2. A transition to STANDBY
state, RV was observed on this rail during the transition after this rail
was disabled and discharge was enabled 3. A transition to ACTIVE
state, RV was observed on this rail during the transition when this rail
was OFF (rails are expected to be discharged before commencing
the sequence to ACTIVE) 4. This rail did not discharge and therefore
caused a Timeout-SD while attempting to discharge all rails at the
start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets
also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO2 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on LDO2 occurred
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表7-59. INT_TIMEOUT_RV_SD Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
LDO1_RV_SD
BUCK3_RV_SD
BUCK2_RV_SD
BUCK1_RV_SD
R/W1C
0h
RV on LDO4 rail caused a shutdown during: 1. A transition to
STANDBY state, this rail did not discharge at the end of the assigned
slot and discharge is enabled for this rail 2. A transition to STANDBY
state, RV was observed on this rail during the transition after this rail
was disabled and discharge was enabled 3. A transition to ACTIVE
state, RV was observed on this rail during the transition when this rail
was OFF (rails are expected to be discharged before commencing
the sequence to ACTIVE) 4. This rail did not discharge and therefore
caused a Timeout-SD while attempting to discharge all rails at the
start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets
also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO1 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on LDO1 occurred
2
1
0
R/W1C
R/W1C
R/W1C
0h
0h
0h
RV on LDO4 rail caused a shutdown during: 1. A transition to
STANDBY state, this rail did not discharge at the end of the assigned
slot and discharge is enabled for this rail 2. A transition to STANDBY
state, RV was observed on this rail during the transition after this rail
was disabled and discharge was enabled 3. A transition to ACTIVE
state, RV was observed on this rail during the transition when this rail
was OFF (rails are expected to be discharged before commencing
the sequence to ACTIVE) 4. This rail did not discharge and therefore
caused a Timeout-SD while attempting to discharge all rails at the
start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets
also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on BUCK3 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on BUCK3 occurred
RV on LDO4 rail caused a shutdown during: 1. A transition to
STANDBY state, this rail did not discharge at the end of the assigned
slot and discharge is enabled for this rail 2. A transition to STANDBY
state, RV was observed on this rail during the transition after this rail
was disabled and discharge was enabled 3. A transition to ACTIVE
state, RV was observed on this rail during the transition when this rail
was OFF (rails are expected to be discharged before commencing
the sequence to ACTIVE) 4. This rail did not discharge and therefore
caused a Timeout-SD while attempting to discharge all rails at the
start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets
also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on BUCK2 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on BUCK2 occurred
RV on LDO4 rail caused a shutdown during: 1. A transition to
STANDBY state, this rail did not discharge at the end of the assigned
slot and discharge is enabled for this rail 2. A transition to STANDBY
state, RV was observed on this rail during the transition after this rail
was disabled and discharge was enabled 3. A transition to ACTIVE
state, RV was observed on this rail during the transition when this rail
was OFF (rails are expected to be discharged before commencing
the sequence to ACTIVE) 4. This rail did not discharge and therefore
caused a Timeout-SD while attempting to discharge all rails at the
start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets
also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on BUCK1 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on BUCK1 occurred
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7.6.52 INT_PB Register (Offset = 33h) [Reset = X]
INT_PB is shown in 图7-63 and described in 表7-60.
Return to the Summary Table.
图7-63. INT_PB Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PB_REAL_TIM PB_RISING_E PB_FALLING_E
E_STATUS
DGE_DETECT DGE_DETECT
ED
ED
R-X
R-X
R-X
R-X
R-X
R-1h
R/W1C-0h
R/W1C-0h
表7-60. INT_PB Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
Reserved
Reserved
Reserved
Reserved
Reserved
R
X
6
RESERVED
RESERVED
RESERVED
RESERVED
R
X
5
R
X
4
R
X
3
R
X
2
PB_REAL_TIME_STATUS R
1h
Deglitched (64-128ms) real-time status of PB pin. Valid only when
EN/PB/VSENSE pin is configured as PB.
0h = Current deglitched status of PB: PRESSED
1h = Current deglitched status of PB: RELEASED
1
0
PB_RISING_EDGE_DET R/W1C
ECTED
0h
0h
PB was released for > deglitch period (64-128ms) since the previous
time this bit was cleared. This bit when set, does assert nINT pin (if
config bit MASK_INT_FOR_PB='0').
0h = No PB-release detected
1h = PB-release detected
PB_FALLING_EDGE_DE R/W1C
TECTED
PB was pressed for > deglitch period (64-128ms) since the previous
time this bit was cleared. This bit when set, does assert nINT pin (if
config bit MASK_INT_FOR_PB='0').
0h = No PB-press detected
1h = PB-press detected
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7.6.53 USER_NVM_CMD_REG Register (Offset = 34h) [Reset = 00h]
USER_NVM_CMD_REG is shown in 图7-64 and described in 表7-61.
Return to the Summary Table.
图7-64. USER_NVM_CMD_REG Register
7
6
5
4
3
2
1
0
NVM_VERIFY_ CUST_NVM_V CUST_PROG_ I2C_OSC_ON
USER_NVM_CMD
R-0h
RESULT
ERIFY_DONE
DONE
R-0h
R/W1C-0h
R/W1C-0h
R-0h
表7-61. USER_NVM_CMD_REG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
NVM_VERIFY_RESULT
R
0h
After an CUST_NVM_VERIFY_CMD is executed, this bit gives the
result of the operation. (1 = fail, 0= pass). If '1', can only be cleared if
a subsequent CUST_NVM_VERIFY_CMD passes.
0h = PASS
1h = FAIL
6
5
CUST_NVM_VERIFY_DO R/W1C
NE
0h
0h
Is set to '1' after a CUST_NVM_VERIFY_CMD is executed. Remains
'1' until W1C by user.
0h = Not yet done / not in progress
1h = Done
CUST_PROG_DONE
R/W1C
Is set to '1' after a CUST_PROG_CMD is executed. Remains '1' until
W1C by user.
0h = Not yet done / not in progress
1h = Done
4
I2C_OSC_ON
R
R
0h
0h
This register field is set to '1' if an EN_OSC_DIY is received.
0h = OSC not controlled via I2C
1h = OSC unconditionally ON due to I2C command EN_OSC_DIY
3-0
USER_NVM_CMD
Commands to enter DIY programming mode and program user NVM
space. Always reads as 0.
6h = DIS_OSC_DIY
7h = CUST_NVM_VERIFY_CMD
9h = EN_OSC_DIY
Ah = CUST_PROG_CMD
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7.6.54 POWER_UP_STATUS_REG Register (Offset = 35h) [Reset = 00h]
POWER_UP_STATUS_REG is shown in 图7-65 and described in 表7-62.
Return to the Summary Table.
图7-65. POWER_UP_STATUS_REG Register
7
6
5
4
3
2
1
0
POWER_UP_F POWER_UP_F COLD_RESET_
STATE
R-0h
RETRY_COUNT
POWER_UP_F
ROM_OFF
ROM_FSD
ROM_EN_PB_
VSENSE
ISSUED
R/W1C-0h
R/W1C-0h
R/W1C-0h
R-0h
R/W1C-0h
表7-62. POWER_UP_STATUS_REG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
POWER_UP_FROM_FSD R/W1C
0h
Is set if ON_REQ was triggered due to FSD
0h = No power-up via FSD detected
1h = Power-up via FSD detected
6
5
POWER_UP_FROM_EN_ R/W1C
PB_VSENSE
0h
0h
0h
Is set if ON_REQ was triggered due to EN/PB/VSENSE pin
0h = No power-up via pin detected
1h = Power-up via pin detected
COLD_RESET_ISSUED
STATE
R/W1C
R
Is set if we received a COLD_RESET over pin or over I2C
0h = No COLD RESET received
1h = COLD RESET received either through pin or I2C
4-3
Indicates the current device state
0h = Transition state
1h = INITIALIZE
2h = STANDBY
3h = ACTIVE
2-1
0
RETRY_COUNT
R
0h
0h
Reads the current retry count in the state machine. If
RETRY_COUNT = 3 and is not masked, device does not power up.
POWER_UP_FROM_OFF R/W1C
Indicates if we powered up from OFF state (POR was asserted)
0h = OFF state not entered since the previous clearing of this bit
1h = OFF state was entered since the previous clearing of this bit
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7.6.55 SPARE_2 Register (Offset = 36h) [Reset = 00h]
SPARE_2 is shown in 图7-66 and described in 表7-63.
Return to the Summary Table.
图7-66. SPARE_2 Register
7
6
5
4
3
2
1
0
SPARE_2_1
R/W-0h
SPARE_2_2
R/W-0h
SPARE_2_3
R/W-0h
SPARE_2_4
R/W-0h
SPARE_2_5
R/W-0h
SPARE_2_6
R/W-0h
SPARE_2_7
R/W-0h
SPARE_2_8
R/W-0h
表7-63. SPARE_2 Register Field Descriptions
Bit
7
Field
SPARE_2_1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
0h
Spare bit in user non-NVM space
Spare bit in user non-NVM space
Spare bit in user non-NVM space
Spare bit in user non-NVM space
Spare bit in user non-NVM space
Spare bit in user non-NVM space
Spare bit in user non-NVM space
Spare bit in user non-NVM space
6
SPARE_2_2
SPARE_2_3
SPARE_2_4
SPARE_2_5
SPARE_2_6
SPARE_2_7
SPARE_2_8
0h
5
0h
4
0h
3
0h
2
0h
1
0h
0
0h
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7.6.56 SPARE_3 Register (Offset = 37h) [Reset = 00h]
SPARE_3 is shown in 图7-67 and described in 表7-64.
Return to the Summary Table.
图7-67. SPARE_3 Register
7
6
5
4
3
2
1
0
SPARE_3_1
R/W-0h
表7-64. SPARE_3 Register Field Descriptions
Bit
7-0
Field
SPARE_3_1
Type
Reset
Description
R/W
0h
Spare bit in user non-NVM space
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7.6.57 FACTORY_CONFIG_2 Register (Offset = 41h) [Reset = X]
FACTORY_CONFIG_2 is shown in 图7-68 and described in 表7-65.
Return to the Summary Table.
图7-68. FACTORY_CONFIG_2 Register
7
6
5
4
3
2
1
0
NVM_REVISION
R/W-X
表7-65. FACTORY_CONFIG_2 Register Field Descriptions
Bit
7-5
Field
Type
Reset
Description
NVM_REVISION
R/W
X
Specifies the version of the NVM configuration Note: This register
can be programmed only by the manufacturer.
0h = V0
1h = V1 ...
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The following sections provide more detail on the proper utilization of the PMIC. Each orderable part number has
unique default non-volatile memory (NVM) settings and the relevant Technical Reference Manual (TRM) for that
orderable is available in the product folder, under Technical Documentation. Refer to these TRMs for specific
application information. More generic topics and some examples are outlined here.
To help with new designs, a variety of tools and documents are available in the product folder. Some examples
are:
• Evaluation module and user guide.
• GUI to communicate with the PMIC
• Schematic and layout checklist
• User's guide describing how to power specific processors and SoCs with the PMIC.
• Technical Reference Manual (TRM) describing the default register settings on each orderable.
8.2 Typical Application
The TPS65219 PMIC contains seven regulators; 3 Buck converters and 4 Low Drop-out Regulators (LDOs). In
addition to the power resources, it also integrates 3 configurable multi-function pins, 1 GPIO, 2 GPOs and I2C
communication making this power management IC an ideal cost and size optimized solution to power multiple
processors and SoCs. There are several considerations to take into account when designing the TPS65219 to
power a processor and peripherals. The number of regulators needed, the required sequencing, the load current
requirements, and the voltage characteristics are all critical in determining the number of supply rails as well as
the external components used with it. The following section provides a generic case. For specific cases, refer to
the relevant user's guide and TRM based on the orderable part number.
8.2.1 Typical Application Example
In this example, a single TPS65219 PMIC is used to power a generic processor. This power distribution network
(PDN) shows a 3.3V input supply but 5V can be used as well to supply the Bucks and LDO (if not configured as
bypass). To reduce power dissipation, the output from one of the PMIC Buck regulators can be used to supply
the LDOs if it meets the required headroom and sequence needs. For example, Buck2 (1.8V) is used to supply
LDO2 (0.85V). LDO1 is configured as bypass and assigned to supply the SD card interface. The bypass mode
allows voltage change between VSET_LDO1 and 1.8V to meet the SD spec for UHS speed which requires 3.3V
to initialize the card before the voltage can be lowered to 1.8V for faster rise/fall time and lower electromagnetic
interference. The VSEL_SD multifunction pin can be configured to trigger the voltage change during operation.
Since Buck1 is the regulator with the highest current capabilities, it was assigned to supply the CORE rail of the
processor. Each of the Buck regulators have the option to be configured for high bandwidth to support higher
load transients and higher total capacitance (local + point of load). Since the PMIC is being supplied by a 3.3V
rail, an external load switch is used to supply the 3.3V IO domain on the processor. One of the PMIC GPOs
(GPO2) is configured to be part of the power-up/power-down sequence and enables the external power-switch.
备注
If an external discrete is used to supply the 3.3V IO, it must be chosen with active discharge so the
voltage can be discharge after the PMIC GPO2 disables it.
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VSYS (3.3V)
PMIC GPO2
PVIN
EN
3.3V
Power Switch
TPS65219
PMIC
Example Processor
3.3V IO
VSYS
0.75V
1.8V
BUCK1
(3.5A max)
PVIN_B1
PVIN_B2
VDD_CORE
BUCK2
(2A max)
1.8V IO
1.1V
BUCK3
(2A max)
PVIN_B3
VDDS_DDR
3.3V / 1.8V
0.85V
1.8V
LDO1 - Bypass
(400mA max)
PVIN_LDO1
PVIN_LDO2
SD card interface
VDDR_CORE
Buck2 (1.8V)
LDO2
(400mA max)
LDO3
(300mA max)
1.8V Analog
PVIN_LDO34
Digital / Analog Supplies
1.2V
LDO4
(300mA max)
Analog
PMIC Enable signal
EN/PB/VSENSE
SCL
SDA
I2C_SCL
I2C_SDA
nINT
PMIC interrupt
nRSTOUT
PMIC power good
VSEL_SD /
VSEL_DDR
GPIOx
High: forced-PWM
LOW: auto-PFM
MODE/STBY
RESET
MODE/RESET
GPIO
Free resource
Digital Signals
Free resource
PMIC GPO2
GPO1
GPO2
Digital
Example Peripherals
VDD_1V8
VDDQ
uSD
Processor GPIOx
HDMI Transmitter
图8-1. Example Power Map
8.2.2 Design Requirements
The design requirements for the typical application described on this section are outlined below:
• VDD CORE rail requires 0.75 V rail with high loadtransient response.
• VDDR CORE rail requires 0.85V.
• Low noise 1.8V required to supply the analog.
• 3.3V and 1.8V required to supply processor IO domains and peripherals.
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• uSD card interface requires a rail with 3.3V at startup with dynamic voltage capability to switch from 3.3V to
1.8V and support ultra-high speed (UHS)
• LPDDR4 requires a 1.1V rail.
• HDMI transmitter requires 1.2V rail.
8.2.3 Detailed Design Procedure
This section describes the design procedure for each of the power modules integrated in the TPS65219 PMIC.
Please note, most of the external component values that are mentioned in this section are based on the typical
spec. For minimum and maximum values, refer to the corresponding parameter in the Specifications section.
8.2.3.1 Buck1, Buck2, Buck3 Design Procedure
Input Capacitance - Buck1, Buck2, Buck3
Each of the Buck converters require an input capacitor on the corresponding PVIN_Bx pin. The capacitor value
must be selected taking into account the voltage and temperature de-rating. Due to the nature of the switching
converter, a low ESR ceramic capacitor is required for best input voltage filtering. The typical recommended
capacitance is 4.7 uF, 10V capacitor. Higher input capacitance can be used if the PCB size allows larger
footprint.
Output Capacitance - Buck1, Buck2, Buck3
Every Buck output requires a local output capacitor to form the capacitive part of the LC output filter. Ceramic
capacitor with X7 temperature coefficient are recommended. Non-automotive applications can use X6 or lower
based on the operating temperature. The Buck converters have multiple switching modes and bandwidth
configuration that impact the output capacitor selection. The switching mode configuration (BUCK_FF_ENABLE)
is a global register field that applies to the three Buck converters and must not be changed at any point. The
bandwidth selection is an independent register field for each Buck converter. Refer to the Technical Reference
Manual (TRM) for the specific orderable part number to identify the NVM configuration and the corresponding
output capacitance requirements. 表8-1 shows the required minimum and maximum capacitance (after derating)
for each switching mode and bandwidth configuration. DC bias voltage characteristics of ceramic capacitors,
tolerance, aging and temperature effects must be considered. ESR must be 10 mΩor lower.
表8-1. Buck output capacitance
Switching Mode Selection
Bandwidth Selection
Spec parameter
Capacitance
Max
Register Field:
Register fields:
BUCK1_BW_SEL,
BUCK2_BW_SEL,
BUCK3_BW_SEL
Min
BUCK_FF_ENABLE
(Includes local + point of
load)
Quasi-fixed frequency
Low Bandwidth
High Bandwidth
Low Bandwidth
High Bandwidth
COUT
10 uF
30 uF
12 uF
48 uF
75 uF
220 uF
36 uF
(auto-PFM or forced-PWM)
COUT_HIGH_BW
COUT_FF
Fixed Frequency
(supported on TPS65220
and TPS65219-Q1)
COUT_HIGH_BW_FF
144 uF
Inductor Selection - Buck1, Buck2, Buck3
Internal parameters for the buck converters are optimized for 0.47uF inductor. DCR must be 50 mΩ or lower.
Ensure that the selected inductor is rated to support saturation current of at least 7.4A for Buck1 and 5.4A for
Buck2/Buck3.
8.2.3.2 LDO1, LDO2 Design Procedure
Input Capacitance - LDO1, LDO2
LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a typical of 2.2-µF
capacitance for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3 V or higher rated
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capacitor can be used. The same input capacitance requirements applies when the LDO is configured as LDO,
bypass or "load-switch.
Output Capacitance - LDO1, LDO2
LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input
voltage. Using a 2.2-µF local capacitance for each LDO output with ESR of 10 mOhms or less is recommended.
Local capacitance must not exceed 4uF (after derating). This requirement excludes any capacitance seen at the
load and only refers to the capacitance seen close to the device. The total capacitance (local + point of load) that
each LDO can support depends on the NVM configuration. 表 8-2 shows the maximum total output capacitance
allowed based on the rail configuration. Refer to the Technical Reference Manual (TRM) for the specific
orderable part number to identify the LDO configuration based on the register settings and the applicable max
total capacitance.
表8-2. LDO1, LDO2 output capacitance
Register setting
LDO config
Max total capacitance (2.2uF local +
point of load)
LDOx_LSW_CONFIG
LDOx_BYP_CONFIG
0
0
1
0
1
X
LDO
20uF
50uF
50uF
Bypass
Load-switch
8.2.3.3 LDO3, LDO4 Design Procedure
Input Capacitance - LDO3, LDO4
The input supply pin for LDO3 and LDO4 require an input decoupling capacitor to minimize input ripple voltage.
These two LDOs share the same input supply pin. Using a minimum of 4.7-µF input capacitance is
recommended. Depending on the input voltage of the LDO, a 6.3 V or higher rated capacitor can be used. The
same input capacitance requirements applies when the LDO is configured as LDO or load-switch.
Output Capacitance - LDO3, LDO4
LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input
voltage. Using a 2.2-µF local capacitance for each LDO output with ESR of 10 mOhms or less is recommended.
Local capacitance must not exceed 4uF (after derating). This requirement excludes any capacitance seen at the
load and only refers to the capacitance seen close to the device. The total capacitance (local + point of load) that
each LDO can support depends on the NVM configuration. 表 8-3 shows the maximum total output capacitance
allowed. Refer to the Technical Reference Manual (TRM) for the specific orderable part number to identify the
LDO configuration based on the register settings and the applicable maximum total capacitance.
表8-3. LDO3, LDO4 output capacitance
Register setting
LDO ramp config
Max total capacitance
(2.2uF local + point of load)
LDOx_SLOW_PU_RAMP
0
1
fast ramp
slow ramp
15uF
30uF
8.2.3.4 VSYS, VDD1P8
The VSYS pin provides power to the internal VDD1P8 LDO and other internal functions. This pin requires a
typical of 2.2uF ceramic capacitor. The input capacitor can be increased without any limit for better input-voltage
filtering. On a typical application, this pin is connected to the same pre-regulator that supplies the PVIN_Bx pins.
VDD1P8 in an internal reference LDO and must not have any load. This pin requires a 2.2uF ceramic capacitor.
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8.2.3.5 Digital Signals Design Procedure
This section describes the external connections required for the digital pins. 3.3V or 1.8V supply is commonly
used as the voltage level for the digital signals that require an external pull-up. However, higher voltage can be
used (up to the maximum spec). The pull-up supply for the digital pins on the PMIC must be the same as the IO
domain for the digital signal that is connected to on the processor. 100 kΩ is the recommended pull-up resistor
for EN/PB/VSENSE. Pull-up resistor for I2C pins can be calculated based on system requirements. All other
digital pins can use 10 kΩ.
If GPIO, GPO1 or GPO2 is assigned to the first slot of the power-up sequence to enable an external discrete,
they can be pulled up to VSYS.
The EN/PB/VSENSE pin can be driven externally to enable or disable the PMIC. However, if the application
does not have an external signal dedicated to drive this pin, it can be pulled up to VSYS.
备注
Driving the EN/PB/VSENSE pin with an external signal is needed to wake-up the PMIC after an I2C
OFF request is sent by I2C (I2C_OFF_REQ). If an OFF request is sent by I2C and the EN/PB/
VSENSE is not driven by an external signal, a power cycle on VSYS must be performed to transfer
the PMIC from Initialize state to Active.
表8-4. Digital Signals requirements
Digital Pin
nINT
External Connection
Open-drain output. Requires external pull-up.
Open-drain output. Requires external pull-up.
nRSTOUT
EN/PB/VSENSE
When configured as EN, this signal can be driven by external logic to enable or disable the PMIC.
When configured as PB, this signal requires a pull-up resistor connected to the VSYS pin. Push-button
is optional.
When configured as VSENSE, this signal requires an external resistor divider to monitor the pre-
regulator.
SDA
SCL
I2C clock signal. Requires external pull-up.
I2C data signal. Requires external pull-up.
GPIO
When configured as GPIO (for multi-PMIC), this pin shares the external pull-up resistor with the
second TPS65219 PMIC.
When configured as GPO (for single PMIC), requires external pull-up.
GPO1
Open-drain general purpose output. Requires external pull-up.
Open-drain general purpose output. Requires external pull-up.
GPO2
VSEL_SD / VSEL_DDR
Input digital pin. The initial state (pull-up or pull-down) must be set before the assigned PMIC rail
ramps up. For example, if this pin is used to set the voltage on LDO1, the state must be set before
LDO1 powers up.
MODE / STBY
Input digital pin. The initial state (pull-up or pull-down) must be set before the power-up sequence is
complete.
MODE / RESET
Input digital pin. The initial state (pull-up or pull-down) must be set before the power-up sequence is
complete.
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8.3 Application Curves
V(BUCK1) (1V/div)
V(BUCK2) (1V/div)
(200µs/div)
(200µs/div)
VIN = 5.0 V
Forced-PWM / High
Bandwidth
VOUT = 3.3V
Iout = 1 A
TA = 25 °C
VIN = 5.0 V
Forced-PWM / High
Bandwidth
VOUT = 3.3V
Iout = 1 A
TA = 25 °C
COUT_total = 57 μF
COUT_total = 57 μF
图8-2. Buck1 ramp
图8-3. Buck2 ramp
V(LDO1, LDO2) (1V/div)
V(BUCK3) (1V/div)
(200µs/div)
(200µs/div)
VIN = 5.0 V
VOUT = 3.3V
TA = 25 °C
VIN = 5.0 V
LDO mode
VOUT = 3.3V
Iout = 400 mA
TA = 25 °C
Forced-PWM / High
Bandwidth
Iout = 1 A
COUT_total = 57 μF
COUT_total = 10 μF
图8-5. LDO1, LDO2 ramp
图8-4. Buck3 ramp
V(LDO3, LDO4) (1V/div)
V(LDO3, LDO4) (1V/div)
(200µs/div)
(400µs/div)
VIN = 5.0 V
LDO mode / Fast
ramp
VOUT = 3.3V
Iout = 400 mA
TA = 25 °C
VIN = 5.0 V
LDO mode / Slow
ramp
VOUT = 3.3V
Iout = 400 mA
TA = 25 °C
COUT_total = 10 μF
COUT_total = 10 μF
图8-6. LDO3, LDO4 Fast Ramp
图8-7. LDO3, LDO4 Slow Ramp
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V(LDO1) (2V/div)
V(LDO2) (2V/div)
V(LDO3) (2V/div)
V(LDO4) (2V/div)
V(BUCK1) (1V/div)
V(BUCK2) (1V/div)
V(BUCK3) (1V/div)
(1ms/div)
(10ms/div)
VIN = 5.0 V
Forced-PWM / High
Bandwidth
VOUT = 3.3V
no load
TA = 25 °C
COUT_total = 57 μF
VIN = 5.0 V
LDO mode
VOUT = 3.3V
no load
TA = 25 °C
COUT_total = 2.2 μF
图8-9. LDOs Discharge
图8-8. Bucks Discharge
nRSTOUT
EN/PB/VSENSE
BUCK1
BUCK1
BUCK2
BUCK3
BUCK2
BUCK3
LDO1
LDO2
LDO3
LDO1
LDO2
LDO3
LDO4
LDO4
GPO1
GPO1
nRSTOUT
(20ms/div)
(4ms/div)
Slot#
Duration
10 ms
0 ms
Assigned Rail
Slot#
Duration
1.5 ms
0 ms
Assigned Rail
0
1
nRSTOUT / BUCK3 / LDO2
BUCK1 / LDO1 / LDO3 / GPO1
BUCK2 / LDO4
0
BUCK2
1
2
10 ms
0 ms
2
3 ms
LDO1 / LDO3 / LDO4 / GPO1
3
3
1.5 ms
1.5 ms
1.5 ms
1.5 ms
10 ms
1.5 ms
10 ms
0ms
4
10 ms
0 ms
4
BUCK3
BUCK1
LDO2
5-15
5
6
图8-11. Configurable power-down sequence -
7
8
Example
9
nRSTOUT
10-15
图8-10. Configurable power-up sequence -
Example
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8.4 Power Supply Recommendations
The device is designed to operate with an input voltage supply range between 2.5 V and 5.5 V. This input supply
can be generated from a single cell Li-Ion battery, two primary cells or a regulated pre-regulator. The voltage
headroom required for each of the PMIC regulators must be taken into account when defining selecting the
supply voltage. For example, if the Bucks require 700 mV head room and the output voltage is configured as
3.3V, then the input supply must be at least 4 V to allow sufficient headroom. The resistance of the input supply
rail must be low enough that the input current transient does not cause too high drop in the device supply
voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the
device, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 47 μF is a typical choice. When using a pre-regulator to supply the PMIC, it is
recommended to select the pre-regulator without active discharge to hold the voltage at the input of the PMIC for
as long as possible during a uncontrolled power-down.
CAUTION
Sequencing and Voltage requirements: The voltage on PVIN_Bx, and PVIN_LDOx must not exceed
VSYS. The Pull-up supply for the digital signals must not exceed VSYS at any point.
8.5 Layout
8.5.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design. If the layout is not carefully done,
the regulators can have stability and EMI issues. Therefore, use wide and short traces for the main current path
and for the power ground tracks. The input capacitors, output capacitors, and inductors must be placed as close
as possible to the device. The output capacitors must have a low impedance to ground. Use multiple VIAS (at
least three) directly at the ground landing pad of the capacitor. Here are some layout guidelines:
• PVIN_Bx: Place the input capacitor as close to the IC as allowed by the layout DRC rules. Any extra parasitic
inductance between the input cap and the PVIN_Bx pin can create a voltage spike. It is recommended to
have wide a short traces or polygon to help minimize trace inductance. Do not route any sensitive signals
close to the input cap and the device pin as this node has high frequency switching currents. Add 3-4 vias per
amp of current on the GND pads for each DCDC. If the space is limited and does not allow to place the input
capacitors on the same layer as the PMIC, then place the input capacitors on the opposite layer with VIAS,
close to the IC, and add a small input capacitor (0.1uF) on the same layer as the PMIC. This small capacitor
must be placed close to the PVIN_Bx pin.
• LX_Bx: Place the inductor close to the PMIC without compromising the PVIN input caps and use short &
wide traces or polygons to connect the pin to the inductor. Do not route any sensitive signals close to this
node. The inductor must be placed in the same layer as the IC to prevent having to use VIAS in the SW
node. Since the SW-node voltage swings from the input voltage to ground with very fast rise and fall times, it
is the main generator of EMI. If needed, to reduce EMI, a RC snubber can be added to the SW node.
• FB_Bx: Route each of the FB_Bx pins as a trace to the output capacitor. Do not extend the output voltage
polygon to the FB_Bx pin as this pin requires to be routed as a trace. The trace resistance from the output
capacitor to the FB_Bx pin must be less than 1 Ω. The TPS65219 does not support remote sensing so the
FB_Bx pins must be connected to the local capacitor of the PMIC. Avoid routing the FB_Bx close to any noisy
signals such as the switch node or under the inductor to avoid coupling. If space is constraint, FB_Bx pin can
be routed through an inner layer. See example layout.
• Bucks Cout: The local output capacitors must be placed as close to the inductor as possible to minimize
electromagnetic emissions.
• PVIN_LDOx: Place the input capacitor as close as posible to the PVIN_LDOx pin.
• VLDOx: Place the output capacitor close to the VLDOx pin. For the LDO regulators, the feedback connection
is internal. Therefore, it is important to keep the PCB resistance between LDO output and target load in the
range of the acceptable voltage, IR, drop for LDOs.
• VSYS: Connect VSYS directly to a quiet system voltage node. Place the decoupling capacitor as close as
possible to the VSYS pin.
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• VDD1P8: Place the 2.2 uF cap as close as possible to the VDD1P8 pin. This capacitor needs to be placed in
the same layer as the IC. Two to Three VIAS can be used to connect the GND side of the capacitor to the
GND plane of the PCB.
• Power Pad: The thermal pad must be connected to the PCB ground plane with a minimum of nine VIAS.
• AGND: Do not connect AGND to the power pad (or thermal pad). The AGDN pin must be connected to the
PCB ground planes through a VIA . Keep the trace from the AGDN pin to the VIA short.
8.5.2 Layout Example
Buck2
Cout
Buck3
Cout
Buck2
Inductor Inductor
Buck3
Buck1
Inductor
Buck1
Cout
LDO4 Cout
LDO3/4 Cin
LDO3 Cout
LDO2 Cin
LDO1 Cin
LDO2 Cout
LDO1 Cout
VSYS Cin
VDD1P8 Cout
图8-12. Example PMIC Layout
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9 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Documentation Support
9.1.1 Related Documentation
9.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Cortex® is a registered trademark of Arm Ltd.
所有商标均为其各自所有者的财产。
9.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS6521920WRHBRQ1
TPS6521920WRHBRQ1
ACTIVE
ACTIVE
VQFN
VQFN
RHB
RHB
32
32
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
Samples
Samples
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
65219Q
NVM 20
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2023
OTHER QUALIFIED VERSIONS OF TPS65219-Q1 :
Catalog : TPS65219
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
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PACKAGE OUTLINE
RHB0032U
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
0.1 MIN
(0.13)
SECTION A-A
A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
3.7 0.1
2X 3.5
(0.2) TYP
9
16
EXPOSED
THERMAL PAD
28X 0.5
8
(0.16) TYP
17
2X
A
A
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
PIN 1 ID
(45 X 0.3)
32
25
SYMM
0.5
0.3
(0.25)
TYP
32X
4225709/C 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032U
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.7)
SYMM
25
32
32X (0.6)
1
24
32X (0.25)
(0.97)
28X (0.5)
(0.63)
TYP
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(0.63) TYP
(0.97)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225709/C 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032U
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9X ( 1.06)
(1.26)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(1.26)
SYMM
33
(4.8)
METAL
TYP
17
8
(R0.05) TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
74% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225709/C 01/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023,德州仪器 (TI) 公司
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TI
PTPS659106A1RSLR
1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48, 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48
TI
PTPS659107A1RSL
1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48, 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48
TI
PTPS659107A1RSLR
1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48, 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48
TI
PTPS659108A1RSLR
1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48, 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48
TI
PTPS659109A1RSLR
1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48, 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48
TI
PTPS65910A1RSL
1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48, 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48
TI
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