PTPS7B8601BQDDARQ1 [TI]

具有电源正常状态指示功能的汽车类 500mA、40V 超低 IQ 低压降 (LDO) 线性稳压器 | DDA | 8 | -40 to 150;


型号：	PTPS7B8601BQDDARQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有电源正常状态指示功能的汽车类 500mA、40V 超低 IQ 低压降 (LDO) 线性稳压器 \| DDA \| 8 \| -40 to 150 稳压器
文件：	总29页 (文件大小：1802K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS7B86-Q1

SBVS362 –JUNE 2020

TPS7B86-Q1 500-mA, 40-V, Low-Dropout Regulator

With Power-Good

1 Features

3 Description

The TPS7B86-Q1 is a low-dropout linear regulator

designed to connect to the battery in automotive

applications. The device has an input voltage range

extending to 40 V, which allows the device to

withstand transients (such as load dumps) that are

anticipated in automotive systems. With only a 20-µA

quiescent current at light loads, the device is an

optimal solution for powering always-on components

such as microcontrollers (MCUs) and controller area

network (CAN) transceivers in standby systems.

•

AEC-Q100 qualified for automotive applications:

–

Temperature grade 1: –40°C to +125°C, T_A

Junction temperature: –40°C to +150°C, T_J

•

Input voltage range: 3 V to 40 V (42 V max)

Output voltage range:

–

Adjustable output: 1.2 V to 18 V

Fixed output: 3.3 V and 5 V

•

Maximum output current: 500 mA

Output voltage accuracy: ±1% (max)

Low dropout voltage:

The device has a state-of-the-art transient response

that allows the output to quickly react to changes in

load or line (for example, during cold-crank

conditions). Additionally, the device has a novel

architecture that minimizes output overshoot when

recovering from dropout. During normal operation, the

device has a tight DC accuracy of ±1% over line,

load, and temperature.

–

500 mV (max) at 450 mA (V_OUT≥ 3.3 V)

•

Low quiescent current:

–

20 µA (typ) at light loads

5 µA (max) when disabled

Excellent line transient response:

The device is equipped with a power-good output to

indicate when the output voltage is close to its final

value. The power-good delay can be adjusted by

external components, thus allowing the delay time to

be configured for a specific system.

–

±2% V_OUTdeviation during cold-crank

±2% V_OUTdeviation (1-V/µs V_INslew rate)

•

Dropout voltage: 555 mV (max) at V_OUT≥ 3.3 V

Power-good with programmable delay period

Stable with a 2.2-µF or larger capacitor

Package options:

The device is available in thermally conductive

packaging to allow the device to efficiently transfer

heat to the circuit board.

–

3-pin TO-252 package: (R_θJA): 29.7°C/W

8-pin SO-8 package: (R_θJA): 41.8°C/W

Device Information⁽¹⁾

PART NUMBER

PACKAGE

HSOP (8)

TO-252 (5)

BODY SIZE (NOM)

4.89 mm × 3.90 mm

6.60 mm × 6.10 mm

2 Applications

TPS7B86-Q1

•

Reconfigurable instrument clusters

Body control modules (BCM)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Always-on battery-connected applications:

–

Automotive gateways

Remote keyless entries (RKE)

Output Equal to Reference Voltage

Line Transient Response (3-V/µs V_INSlew Rate)

TPS7B86-Q1

0.25

bat

reg

V_IN

V_OUT

10 …F

0.1 …F

0.2

0.15

0.1

0.05

-0.05

-0.1

-0.15

-0.2

GND

500

1000

1500

Time (ms)

2000

2500

3000

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to

change without notice.

TPS7B86-Q1

SBVS362 –JUNE 2020

www.ti.com

Table of Contents

7.4 Device Functional Modes........................................ 18

Application and Implementation ........................ 19

8.1 Application Information............................................ 19

8.2 Typical Application .................................................. 22

Power Supply Recommendations...................... 22

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Switching Characteristics.......................................... 6

6.7 Typical Characteristics.............................................. 8

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7.2 Functional Block Diagrams ..................................... 14

7.3 Feature Description................................................. 16

10 Layout................................................................... 23

10.1 Layout Guidelines ................................................. 23

10.2 Layout Examples................................................... 24

11 Device and Documentation Support ................. 25

11.1 Device Support...................................................... 25

11.2 Documentation Support ........................................ 25

11.3 Receiving Notification of Documentation Updates 25

11.4 Support Resources ............................................... 25

11.5 Trademarks........................................................... 25

11.6 Electrostatic Discharge Caution............................ 25

11.7 Glossary................................................................ 25

12 Mechanical, Packaging, and Orderable

Information ........................................................... 25

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

June 2020

Initial release.

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SBVS362 –JUNE 2020

5 Pin Configuration and Functions

KVU Package

5-Pin TO-252

Top View

DDA Package

8-Pin SOIC

Top View

FB/NC

GND

Thermal pad

Thermal

Pad

GND

Not to scale

DDA Package With PG (Preview)

8-Pin SOIC

Top View

Not to scale

OUT

FB/NC

DELAY

GND

Thermal

Pad

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SBVS362 –JUNE 2020

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Pin Functions

DDA

(Without

PG)

TYPE⁽¹⁾

DESCRIPTION

DDA

(With PG)

NAME

KVU

Reset-pulse delay adjustment. Connecting a capacitor from this pin to

GND changes the power-good (PG) reset delay.

DELAY

—

Enable pin. The device is disabled when the enable pin becomes

lower than the enable logic input low level (V_IL).

Feedback pin when using an external resistor divider or an NC pin

when using the device with a fixed output voltage.

FB/NC

GND

Ground pin. Connect this pin to the thermal pad with a low-impedance

connection.

—

No internal connection. This pin can be left floating or tied to GND for

the best thermal performance.

—

3, 4, 6

Input power-supply voltage pin. For best transient response and to

minimize input impedance, use the recommended value or larger

ceramic capacitor from IN to ground as listed in the Recommended

Operating Conditions table and the Input Capacitor section. Place the

input capacitor as close to the output of the device as possible.

Regulated output voltage pin. A capacitor is required from OUT to

ground for stability. For best transient response, use the nominal

recommended value or larger ceramic capacitor from OUT to ground;

see the Recommended Operating Conditions table and the Output

Capacitor section. Place the output capacitor as close to output of the

device as possible.

OUT

Power good. This pin has an internal pullup resistor. Do not connect

this pin to VO. V_PGis logic level high when V_OUTis above the power-

good threshold.

—

Thermal pad. Connect the pad to GND for the best possible thermal

performance. See the Layout section for more information.

Thermal pad

—

(1) I = input; O = output; P = power; G = ground.

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SBVS362 –JUNE 2020

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX UNIT

V_IN

V_OUT

Unregulated input

Enable input

Regulated output

Feedback

–0.3 V_IN+ 0.3 V⁽²⁾

–0.3

–40

–65

150

T_J

Operating junction temperature

Storage temperature

°C

T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Theseare stress ratings

only and functional operation of the device at these or any other conditionsbeyond those indicated under recommended operating

conditions isnot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.

(2) The absolute maximum rating is VIN + 0.3 V or 20 V, whichever is smaller

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

V_(ESD)

Electrostatic discharge

All pins

Charged-device model (CDM), per AEC Q100-

011

Corner pins

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

V_IN

Input voltage

V_OUT

I_OUT

F_EN

V_EN

C_OUT

ESR

C_IN

Output voltage

1.2

Output current

500

kHz

Enable pin frequency

High voltage (I/O)

2.2

Output capacitor⁽¹⁾

Output capacitor ESR requirements

Input capacitor

220

µF

0.001

µF

°C

T_J

Operating junction temperature

–40

150

(1) Effective output capacitance of 1 µF minimum required for stability.

6.4 Thermal Information

TPS7B86-Q1

THERMAL METRIC⁽¹⁾⁽²⁾

KVU (DPAK-5)

SO8-EP

8 PINS

41.8

UNIT

5 PINS

29.7

40.2

8.6

θ_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

θ_JCtop

θ_JB

17.3

4.5

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.9

ψ_JB

8.5

17.3

5.7

θ_JCbot

1.5

(1) The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.

The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated.

(2) For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application

report.

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SBVS362 –JUNE 2020

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6.5 Electrical Characteristics

Specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 0 mA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, V_EN= 2 V

(unless otherwise noted). Typical values are at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

–0.85

–1

TYP

MAX

0.85

UNIT

V_IN= V_OUT+ 1V to 40 V, I_OUT= 100 µA to 450 mA, T_J= 25ºC

V_IN= V_OUT+ 1V to 40 V, I_OUT= 100 µA to 500 mA, T_J= 25ºC

V_IN= V_OUT+ 1V to 40 V, I_OUT= 100 µA to 450 mA

V_IN= V_OUT+ 1V to 40 V, I_OUT= 100 µA to 500 mA

V_IN= V_OUT+ 1V, I_OUT= 100 µA to 450 mA , V_OUT≥ 3.3 V

V_IN= V_OUT+ 1V, I_OUT= 100 µA to 500 mA , V_OUT≥ 3.3 V

V_IN= V_OUT+ 1V, I_OUT= 100 µA to 450 mA , V_OUT< 3.3 V

V_IN= V_OUT+ 1V, I_OUT= 100 µA to 500 mA , V_OUT< 3.3 V

V_IN= V_OUT+ 1V to 40 V, I_OUT= 100 µA

V_OUT

Regulated output

–1

0.4

0.45

0.6

0.65

0.2

ΔV_OUT(ΔIOUT)

Load regulation

ΔV_OUT(ΔIOUT)

ΔV_OUT(ΔVIN)

Load regulation

Line regulation

V_IN= V_OUT+ 1V to 40V, I_OUT= 0 mA, T_J= 25ºC

V_IN= V_OUT+ 1V to 40 V, I_OUT= 0 mA

TBD

µA

I_Q

Quiescent current

I_OUT= 500 µA

I_OUT= 500 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)

I_OUT= 450 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)

I_OUT= 315 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)

555

500

370

V_DO

Dropout voltage fixed output voltages

I_OUT≤ 1 mA, V_OUT≥ 3.3 V, V_IN= V_OUT(NOM)x 0.95

I_OUT= 500 mA, V_FB= 0.61 V, V_IN= 3 V

I_OUT= 450 mA, V_FB= 0.61 V, V_IN= 3 V

I_OUT= 315 mA, V_FB= 0.61 V, V_IN= 3 V

793

714

500

V_DO

Dropout voltage adjustable output

µA

I_OUT≤ 1 mA, V_FB= 0.61 V, V_IN= 3 V

V_EN= 0 V, T_J= 25ºC

V_EN= 0V

I_SHUTDOWN

Shutdown supply current (I_GND)

I_EN

EN pin current

V_EN= V_IN= 13.5 V

Reference voltage for FB

Current into FB pin

V_INrising, I_OUT= 1 mA

V_INfalling, I_OUT= 1 mA

µA

V_FB

Feedback voltage

0.643

0.65

0.657

I_FB

Feedback current

V_UVLO(RISING)

V_{UVLO(FALLING)}

V_UVLO(HYST)

V_IL

Rising Input Supply UVLO

Falling Input Supply UVLO

V _UVLO(IN)Hysteresis

2.6

2.7

2.5

2.82

2.6

2.38

200

Enable Logic input low level

Enable Logic input high level

Output current limit

0.7

V_IH

I_CL

V_IN= V_OUT+ 1 V, V_OUTshort to 90% x V_OUT(NOM)

V_IN- V_OUT= 1V, Frequency = 1 kHz, I_OUT= 450 mA

540

780

kΩ

PSRR

Power supply ripple rejection

R_PG

Power Good internal pull up resistor

PG pin low level output voltage

Default power-good threshold

Power-good hysteresis

0.4

V_PG(OL)

V_{PG(TH,RISING)}

V_{PG(TH,FALLING)}

V_PG(HYST)

V_DLY(TH)

I_DLY(CHARGE)

T_J

V_OUT≤ 0.83 x V_OUT

V_OUTrising

V_OUTfalling

%V_OUT

1.21

1.5

Threshold to release Power good high Voltage at Delay pin rising

1.17

1.25

Delay capacitor charging current

Junction temperature

Voltage at Delay pin = 1V

µA

°C

–40

150

T_SD(SHUTDOWN)

T_SD(HYST)

Junction shutdown temperature

Hysteresis of thermal shutdown

175

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

100

MAX

UNIT

µs

t_{(DLY_FIX)}

t_(Deglitch)

Power-good propagation delay

Power-good deglitch time

No capacitor connect at DELAY pin

µs

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SBVS362 –JUNE 2020

Switching Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay capacitor value:

C_(DELAY)= 100 nF

t_(DLY)

Power-good propagation delay

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6.7 Typical Characteristics

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

= 2 V (unless otherwise noted)

5.015

5.01

5.005

0.1

0.05

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

150 mA

100 mA

-0.05

-0.1

-0.15

-0.2

-0.25

-0.3

4.995

4.99

4.985

4.98

4.975

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature èC

20 25

Input Voltage (V)

V_OUT= 5 V, I_OUT= 150 mA

Figure 2. Line Regulation vs V_IN

Figure 1. Accuracy vs Temperature

5.015

5.01

5.005

5.015

5.01

5.005

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

4.995

4.99

4.985

4.98

4.975

4.995

4.99

4.985

4.98

4.975

20 25

Input Voltage (V)

20 25

Input Voltage (V)

V_OUT= 5 V, I_OUT= 5 mA

Figure 3. Line Regulation vs V_IN

V_OUT= 5 V, I_OUT= 1 mA

Figure 4. Line Regulation vs V_IN

550

5.015

5.01

5.005

-55 èC

-40 èC

0 èC

25 èC

85 èC

125 èC

150 èC

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

500

450

400

350

300

250

200

150

100

4.995

4.99

4.985

4.98

4.975

50 100 150 200 250 300 350 400 450 500

Output Current (mA)

100

125

150

V_IN= 3 V

V_OUT= 5 V

Figure 6. Dropout Voltage (V_DO) vs I_OUT

Figure 5. Load Regulation vs I_OUT

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SBVS362 –JUNE 2020

Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

= 2 V (unless otherwise noted)

550

500

450

400

350

300

250

200

150

100

500

450

400

350

300

250

200

150

-55 èC

-40 èC

0 èC

25 èC

85 èC

125 èC

150 èC

-55èC

-40èC

0èC

85èC

150èC

25èC

125èC

50 100 150 200 250 300 350 400 450 500

Output Current (mA)

10 12

Input Voltage (V)

V_IN= 20 V

I_OUT= 450 mA

Figure 7. Dropout Voltage (V_DO) vs I_OUT

Figure 8. Dropout Voltage (V_DO) vs V_IN

100

I_OUT= 150 mA

I_OUT= 100 mA

I_OUT= 50 mA

I_OUT= 10 mA

I_OUT= 1mA

V_IN= 5.5 V

V_IN= 6 V

V_IN= 7 V

V_IN= 10 V

V_IN= 13.5 V

100

10k 100k

Frequency (Hz)

10M

100

10k 100k

Frequency (Hz)

10M

C_OUT= 10 µF (X7R 50 V), V_OUT= 5 V

C_OUT= 10 µF (X7R 50 V), I_OUT= 150 mA, V_OUT= 5 V

Figure 9. PSRR vs Frequency and I_OUT

Figure 10. PSRR vs Frequency and V_IN

0.25

0.2

200

150

100

640

560

480

400

320

240

160

V_IN

V_OUT

I_OUT

0.15

0.1

0.05

-50

-0.05

-0.1

-0.15

-0.2

-100

-150

-200

500

1000

1500

Time (ms)

2000

2500

3000

0.25

0.5

0.75

Time (ms)

1.25

1.5

1.75

V_OUT= 5 V, I_OUT= 1 mA, V_IN= 13.5 V to 45 V,

slew rate = 2.7 V/µs, V_EN= 3.3 V

V_OUT= 5 V, I_OUT= 0 mA to 100 mA, slew rate = 1 A/µs,

V_EN= 3.3 V

Figure 11. Line Transients

Figure 12. Load Transient, No Load to 100 mA

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Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

= 2 V (unless otherwise noted)

650

600

550

500

450

400

350

300

250

200

150

100

480

440

400

360

320

280

240

200

160

120

V_OUT

I_OUT

V_OUT

I_OUT

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-10

-20

-30

-40

-50

100

150

Time (ms)

200

250

300

350

50 100 150 200 250 300 350 400 450 500

Time (ms)

V_OUT= 5 V, I_OUT= 0 mA to 100 mA, slew rate = 1 A/µs,

V_EN= 3.3 V

V_OUT= 5 V, I_OUT= 100 mA to 0 mA, slew rate = 1 A/µs,

V_EN= 3.3 V

Figure 13. Load Transient, No Load to 100-mA Rising Edge

Figure 14. Load Transient, No Load to 100-mA Falling Edge

400

360

320

280

240

200

160

120

400

360

320

280

240

200

160

120

V_OUT

I_OUT

V_OUT

I_OUT

-5

-10

-15

-20

-25

-10

-15

-20

-25

0.25 0.5 0.75

1.25 1.5 1.75

Time (ms)

2.25 2.5

100

150

Time (ms)

200

250

300

350

V_OUT= 5 V, I_OUT= 50 mA to 100 mA, slew rate = 0.1 A/µs,

V_EN= 3.3 V

V_OUT= 5 V, I_OUT= 50 mA to 100 mA, slew rate = 0.1 A/µs,

V_EN= 3.3 V

Figure 15. Load Transient, 50 mA to 100 mA

Figure 16. Load Transient, 50-mA to 100-mA Rising Edge

400

360

320

280

240

200

160

120

800

750

700

650

600

550

500

450

400

350

300

250

200

150

100

V_OUT

I_OUT

V_OUT

I_OUT

-10

-20

-30

-40

-50

-60

-70

-80

-5

-10

-15

-20

-25

350

200 400 600 800 1000 1200 1400 1600 1800 2000

100

150

200

250

300

Time (ms)

V_OUT= 5 V, I_OUT= 100 mA to 50 mA, slew rate = 0.1 A/µs,

V_EN= 3.3 V

V_OUT= 5 V, I_OUT= 0 mA to 150 mA, slew rate = 1 A/µs,

V_EN= 3.3 V

Figure 17. Load Transient, 50-mA to 100-mA Falling Edge

Figure 18. Load Transient, 0 mA to 150 mA

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Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

= 2 V (unless otherwise noted)

150

100

2400

2000

1600

1200

800

400

600

550

500

450

400

350

300

250

200

150

100

V_OUT

I_OUT

V_OUT

I_OUT

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-50

-100

-150

0.5

1.5

2.5

Time (ms)

3.5

4.5

25 50 75 100 125 150 175 200 225 250 275 300

Time (ms)

V_OUT= 5 V, I_OUT= 0 mA to 450 mA, slew rate = 2 A/µs,

V_EN= 3.3 V, C_IN= 1 µF, C_OUT= 10 µF

V_OUT= 5 V, I_OUT= 0 mA to 150 mA, slew rate = 1 A/µs,

V_EN= 3.3 V

Figure 20. Load Transient, 0 mA to 450 mA

Figure 19. Load Transient, 0-mA to 150-mA Rising Edge

1400

V_OUT

I_OUT

V_OUT

I_OUT

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

-10

-20

-30

-40

-50

-60

-70

-80

-90

-10

-20

-30

-40

-50

-60

-70

-80

-90

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Time (ms)

0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2

Time (ms)

V_OUT= 5 V, I_OUT= 135 mA to 315 mA, slew rate = 2 A/µs,

V_EN= 3.3 V, C_IN= 1 µF, C_OUT= 10 µF

V_OUT= 5 V, I_OUT= 135 mA to 315 mA, slew rate = 2 A/µs,

V_EN= 3.3 V, C_IN= 1 µF, C_OUT= 10 µF

Figure 21. Load Transient, 135 mA to 315 mA

Figure 22. Load Transient, 135-mA to 315-mA Rising Edge

150

125

100

2400

2200

2000

1800

1600

1400

1200

1000

800

2400

2100

1800

1500

1200

900

V_OUT

I_OUT

V_OUT

I_OUT

-25

-50

-25

-50

-75

-100

-125

-150

-75

600

-100

-125

-150

600

400

300

200

0.25

0.5

0.75

Time (ms)

1.25

1.5

1.75

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Time (ms)

V_OUT= 5 V, I_OUT= 1 mA to 450 mA, slew rate = 2 A/µs,

V_EN= 3.3 V, C_IN= 1 µF, C_OUT= 10 µF

V_OUT= 5 V, I_OUT= 1 mA to 450 mA, slew rate = 2 A/µs,

V_EN= 3.3 V, C_IN= 1 µF, C_OUT= 10 µF

Figure 23. Load Transient, 1 mA to 450 mA

Figure 24. Load Transient, 1-mA to 450-mA Rising Edge

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Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

= 2 V (unless otherwise noted)

175

150

125

100

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

-55èC

-40èC

0èC

25èC

85èC

125èC

150èC

20 25

Input Voltage (V)

V_OUT= 5 V

Figure 25. Quiescent Current (I_Q) vs V_IN

Figure 26. Quiescent Current (I_Q) vs V_IN

1.38

1.36

1.34

1.32

1.3

Falling Threshold

Rising Threshold

Falling Threshold

Rising Threshold

1.28

1.26

1.24

1.22

1.2

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature (èC)

Figure 27. EN Threshold vs Temperature

Figure 28. PG Threshold vs Temperature

5.5

600

550

500

450

400

350

300

250

200

150

100

2.8

2.75

2.7

V_OUT

V_PG

I_Inrush

Falling Threshold

Rising Threshold

4.5

2.65

2.6

3.5

2.5

2.55

2.5

1.5

2.45

2.4

0.5

50 100 150 200 250 300 350 400 450 500

Time (ms)

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature (èC)

Figure 29. Startup Plot Inrush Current

Figure 30. Undervoltage Lockout (UVLO) Threshold vs

Temperature

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Typical Characteristics (continued)

specified at T_J= –40°C to +150°C, V_IN= 13.5 V, I_OUT= 100 µA, C_OUT= 2.2 µF, 1 mΩ < C_OUTESR < 2 Ω, C_IN= 1 µF, and V_EN

= 2 V (unless otherwise noted)

1.58

1.57

1.56

1.55

1.54

1.53

1.52

-60 -40 -20

20 40 60 80 100 120 140 160

Temperature èC

V_DELAY= 1 V

Figure 31. Delay Pin Current vs Temperature

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7 Detailed Description

7.1 Overview

The TPS7B86-Q1 is a low-dropout linear regulator (LDO) designed to connect to the battery in automotive

applications. The device has an input voltage range extending to 40 V, which allows the device to withstand

transients (such as load dumps) that are anticipated in automotive systems. With only a 20-µA quiescent current

at light loads, the device is an optimal solution for powering always-on components.

The device has a state-of-the-art transient response that allows the output to quickly react to changes in the load

or line (for example, during cold-crank conditions). Additionally, the device has a novel architecture that

minimizes output overshoot when recovering from dropout. During normal operation, the device has a tight DC

accuracy of ±1.5% over line, load, and temperature.

7.2 Functional Block Diagrams

OUT

Current

Limit

Thermal

Shutdown

UVLO

Bandgap

GND

Figure 32. Adjustable Output Block Diagram

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Functional Block Diagrams (continued)

OUT

Current

Limit

R₁

Thermal

Shutdown

UVLO

R₂

Bandgap

GND

Figure 33. Fixed Output Block Diagram

FPO

Figure 34. Adjustable With Power-Good Block Diagram

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7.3 Feature Description

7.3.1 Enable (EN)

The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable

pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than

the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the

enable pin to the input of the device.

7.3.2 Power-Good (PG)

The PG signal provides an easy solution to meet demanding sequencing requirements because PG alerts when

the output nears its nominal value. PG can be used to signal other devices in a system when the output voltage

is near, at, or above the set output voltage (V_OUT(nom)). Figure 35 shows a simplified schematic. The PG signal is

an internal pullup resistor to the nominal output voltage and is active high. The PG circuit sets the PG pin into a

high-impedance state to indicate that the power is good.

OUT

V_REF

Figure 35. Simplified Power-Good Schematic

7.3.3 Adjustable Power-Good Delay Timer (DELAY)

The power-good delay period is a function of the external capacitor on the DELAY pin. The adjustable delay

configures the amount of time required before the PG pin becomes high. This delay is configured by connecting

an external capacitor from this pin to GND. Figure 36 shows a typical timing diagram for the power-good delay

pin. If the DELAY pin is left floating, the power-good delay is t_{(DLY_FIX)}. For more information on how to program

the PG delay, see the Setting the Adjustable Power-Good Delay section.

V_IN

(UVLO)

t < t_(DEGLITCH)

V(PG_HYST)

V_{(PG_TH}) rising

V_{(PG_ADJ}) rising

V_{(PG_TH) falling}

V_{(PG_ADJ) falling}

V_OUT

(DLY_TH)

DELAY

t_(DEGLITCH)

(DLY)

Power Up

Input Voltage Drop

Undervoltage

Power Down

NOTE: V_{(PG_TH) falling}= V_{(PG_TH) rising}– V_{(PG_HYST).}

Figure 36. Typical Power-Good Timing Diagram

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Feature Description (continued)

7.3.4 Undervoltage Lockout

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a

controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input

drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

7.3.5 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature

(T_J) of the pass transistor rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device

resets (turns on) when the temperature falls to T_SD(reset)(typical).

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when

thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high

from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before startup

completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry of the device is designed to protect against thermal

overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device

into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

7.3.6 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a brickwall scheme. In a high-load current fault, the brickwall scheme limits

the output current to the current limit (I_CL). I_CLis listed in the Electrical Characteristics table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. If thermal shutdown is triggered, the device turns

off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output

current fault condition continues, the device cycles between current limit and thermal shutdown. For more

information on current limits, see the Know Your Limits application report.

Figure 37 shows a diagram of the current limit.

V_OUT

Brickwall

V_OUT(NOM)

0 V

I_OUT

I_RATED

0 mA

I_CL

Figure 37. Current Limit

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7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

The Device Functional Mode Comparison table shows the conditions that lead to the different modes of

operation. See the Electrical Characteristics table for parameter values.

Table 1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_EN> V_EN(HI)

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

V_EN< V_EN(LOW)

Not applicable

T_J> T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

The output current is less than the current limit (I_OUT< I_CL

The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to

less than the enable falling threshold

)

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN

pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned

off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal

discharge circuit from the output to ground.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Input and Output Capacitor Selection

The TPS7B86-Q1 requires an output capacitor of 2.2 µF or larger (1 µF or larger capacitance) for stability and an

equivalent series resistance (ESR) between 0.001 Ω and 2 Ω. For the best transient performance, use X5R- and

X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over

temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for

the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the

maximum recommended output capacitance is 220 µF.

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor

from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input

supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves

transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of

frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a

higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several

inches from the input power source.

8.1.2 Adjustable Device Feedback Resistor Selection

The adjustable-version device requires external feedback divider resistors to set the output voltage. V_OUTis set

using the feedback divider resistors, R₁and R₂, according to the following equation:

V_OUT= V_FB× (1 + R₁/ R₂)

(1)

To ignore the FB pin current error term in the V_OUTequation, set the feedback divider current to 100x the FB pin

current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series

resistance, as shown in the following equation:

R₁+ R₂≤ V_OUT/ (I_FB× 100)

(2)

8.1.3 Feed-Forward Capacitor (C_FF)

For the adjustable-voltage version device, a feed-forward capacitor (C_FF) can be connected from the OUT pin to

the FB pin. C_FFimproves transient, noise, and PSRR performance, but is not required for regulator stability.

Recommended C_FFvalues are listed in the Recommended Operating Conditions table. A higher capacitance C_FF

can be used; however, the startup time increases. For a detailed description of C_FFtradeoffs, see the Pros and

Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.

C_FFand R₁form a zero in the loop gain at frequency f_Z, while C_FF, R₁, and R₂form a pole in the loop gain at

frequency f_P. C_FFzero and pole frequencies can be calculated from the following equations:

f_Z= 1 / (2 × π × C_FF× R₁)

(3)

(4)

f_P= 1 / (2 × π × C_FF× (R₁|| R₂))

8.1.4 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch.

The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output

voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the

nominal output regulation, then the output voltage falls as well.

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Application Information (continued)

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. Use Equation 5 to calculate the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(5)

8.1.5 Reverse Current

Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the

pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the

long-term reliability of the device.

Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute

maximum rating of V_OUT≤ V_IN+ 0.3 V.

•

If the device has a large C_OUTand the input supply collapses with little or no load current

The output is biased when the input supply is not established

The output is biased above the input supply

If reverse current flow is expected in the application, external protection is recommended to protect the device.

Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation

is anticipated.

8.1.6 Power Dissipation (P_D)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit

board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no

other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

and load conditions. Equation 6 calculates power dissipation (P_D).

P_D= (V_IN– V_OUT) × I_OUT

(6)

NOTE

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by

correct selection of the system voltage rails. For the lowest power dissipation use the

minimum input voltage required for correct output regulation.

For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal

pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an

array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (T_A) for the device.

According to Equation 7, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the ambient

air (T_A).

T_J= T_A+ (R_θJA× P_D)

(7)

Thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the particular PCB

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC

standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

8.1.7 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal

resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi

metrics are determined to be significantly independent of the copper area available for heat-spreading. The

Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization

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Application Information (continued)

parameter (ψ_JT) and junction-to-board characterization parameter (ψ_JB). These parameters provide two methods

for calculating the junction temperature (T_J). As described in , use the junction-to-top characterization parameter

(ψ_JT) with the temperature at the center-top of device package (T_T) to calculate the junction temperature. As

described in , use the junction-to-board characterization parameter (ψ_JB) with the PCB surface temperature 1 mm

from the device package (T_B) to calculate the junction temperature.

T_J= T_T+ ψ_JT× P_D

where:

•

P_Dis the dissipated power

T_Tis the temperature at the center-top of the device package

(8)

T_J= T_B+ ψ_JB× P_D

where

•

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(9)

For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package

Thermal Metrics application report.

8.1.8 Pulling Up the PG Pin to a Different Voltage

Because the power-good (PG) pin is pulled up internally to the output rail, output signals on this pin cannot be

pulled up to any voltage or wire AND'd like a typical open-drain PG output can be. If these signals must be pulled

up to another logic level, then an external circuit can be implemented using a p-channel metal-oxide-

semiconductor field effect (PMOS) transistor and a pullup resistor. Implementing the circuit shown in Figure 38

allows the outputs to be pulled up to any logic rail. This implementation also allows the outputs to be AND'd

together like traditional power-good pins.

SENSE_OUT

Figure 38. Additional Components for the PG Pin to be Pulled Up to Another Rail

8.1.9 Power-Good

8.1.9.1 Setting the Adjustable Power-Good Delay

The power-good delay time can be set in two ways: either by floating the delay pin or by connecting a capacitor

from this pin to GND. When the DELAY pin is floating, the time defaults to t_{(DLY_FIX)}. The delay time is set by

Equation 10 if a capacitor is connected between the DELAY pin and GND.

≈

’

V_DLY(TH)

t = t_{(DLY _FIX)}+ C_DELAY

∆

◊

I_DLY(CHARGE)

(10)

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8.2 Typical Application

Figure 39 shows a typical application circuit for the TPS7B86-Q1. Use different values of external components,

depending on the end application. An application may require a larger output capacitor during fast load steps in

order to prevent a reset from occurring. TI recommends a low-ESR ceramic capacitor with a dielectric of type

X5R or X7R.

OUT

TPS7B86-Q1

GND

Figure 39. Typical Application Schematic for the TPS7B86-Q1

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters.

Table 2. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

6 V to 40 V

5 V

Output current

100 mA

10 µF

Output capacitor

Power-good delay capacitor

100 nF

8.2.2 Detailed Design Procedure

8.2.2.1 Input Capacitor

The device requires an input decoupling capacitor, the value of which depends on the application. The typical

recommended value for the decoupling capacitor is 1 µF. The voltage rating must be greater than the maximum

input voltage.

8.2.2.2 Output Capacitor

The device requires an output capacitor to stabilize the output voltage. The capacitor value must be between

2.2 µF and 200 µF and the ESR range must be between 1 mΩ and 2 Ω. For this design a low ESR, 10-µF

ceramic capacitor was used to improve transient performance.

9 Power Supply Recommendations

This device is designed for operation from an input voltage supply with a range between 3 V and 40 V. This input

supply must be well regulated. If the input supply is located more than a few inches from the TPS7B86-Q1, add

an electrolytic capacitor with a value of 22 µF and a ceramic bypass capacitor at the input.

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10 Layout

10.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,

copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and

negatively affects system performance. TI also recommends a ground reference plane either embedded in the

PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to

assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread (or sink)

heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is

necessary to meet thermal requirements.

10.1.1 Package Mounting

Solder pad footprint recommendations for the TPS7B86-Q1 are available at the end of this document and at

www.ti.com.

10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance

As depicted in Figure 40 and Figure 41, place the input and output capacitors close to the device for the layout of

the TPS7B86-Q1. To enhance the thermal performance, place as many vias as possible around the device.

These vias improve the heat transfer between the different GND planes in the PCB.

To improve AC performance such as PSRR, output noise, and transient response, TI recommends a board

design with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin

of the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of

the device.

Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.

Place each capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.

Do not place any capacitors on the opposite side of the PCB from where the regulator is installed. TI strongly

discourages the use of vias and long traces to connect capacitors because these traces may negatively impact

system performance and even cause instability.

If possible, and to ensure the maximum performance specified in this document, use the same layout pattern

used for the TPS7B86-Q1 evaluation board, available at www.ti.com.

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10.2 Layout Examples

FPO

Figure 40. SO-8 (DDA) Layout

FPO

Figure 41. TO-252 (KVU)

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TPS7B86-Q1

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SBVS362 –JUNE 2020

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

For the PSpice model, see the TPS7B4250 PSpice Transient Model.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, Various Applications for Voltage-Tracking LDO application report

Texas Instruments, TPS7B4250 Evaluation Module user guide

Texas Instruments, TPS7B5250-Q1 Pin FMEA application report

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: TPS7B86-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

4-Sep-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTPS7B8601QDDARQ1

PTPS7B8633QDDARQ1

PTPS7B8650QDDARQ1

ACTIVE SO PowerPAD

DDA

2500

TBD

Call TI

-40 to 150

Call TI

TPS7B8601QDDARQ1

TPS7B8633QDDARQ1

TPS7B8633QKVURQ1

TPS7B8650QDDARQ1

TPS7B8650QKVURQ1

PREVIEW SO PowerPAD

DDA

KVU

DDA

KVU

2500

TBD

Call TI

-40 to 150

PREVIEW

PREVIEW SO PowerPAD

PREVIEW TO-252

TO-252

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

4-Sep-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

GENERIC PACKAGE VIEW

DDA 8

PowerPAD^TMSOIC - 1.7 mm max height

PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4202561/G

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PTPS7B8601BQDDARQ1 [TI]

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