PUCC27624QDGNRQ1 [TI]
具有 4V UVLO、30V VDD 和低传播延迟的汽车类 5A/5A 双通道栅极驱动器
| DGN | 8 | -40 to 150;
| 型号： | PUCC27624QDGNRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 4V UVLO、30V VDD 和低传播延迟的汽车类 5A/5A 双通道栅极驱动器 | DGN | 8 | -40 to 150 栅极驱动 驱动器 |
| 文件： | 总35页 (文件大小：3038K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC27624-Q1
ZHCSPL5B –MARCH 2022 –REVISED NOVEMBER 2022
UCC27624-Q1 具有-10V 输入能力、适用于汽车应用的30V、5A、双通道、低
侧栅极驱动器
1 特性
3 说明
• 符合汽车应用要求
• 符合AEC-Q100
UCC27624-Q1 是一款双通道、高速、低侧栅极驱动
器，能够有效地驱动 MOSFET、IGBT、SiC 和 GaN
电源开关。UCC27624-Q1 的典型峰值驱动强度为
5A，这有助于缩短电源开关的上升和下降时间、降低
开关损耗并提高效率。此器件具有快速传播延迟（典型
值为 17ns），可改善系统的死区时间优化、控制环路
响应，提高脉宽利用率和瞬态性能，从而提高功率级效
率。
– 器件温度1 级
– 器件人体放电模式(HBM) 静电放电(ESD) 分类
等级H1C
– 器件组件充电模式(CDM) ESD 分类等级C6
• 每个通道具有5A 的典型峰值拉取和灌入驱动电流
• 输入和使能引脚能够处理–10V 的电压
• 输出端能够处理–2V 的瞬态电压
• 绝对最大VDD 电压：30V
UCC27624-Q1 可在输入端处理 –10V 的电压，通过
平缓的接地反弹提高系统稳健性。输入与电源电压无
关，可以连接大多数控制器输出端，从而最大限度地提
高控制灵活性。独立的使能信号支持在不依赖主控制逻
辑的情况下对功率级进行控制。发生系统故障时，栅极
驱动器可以通过拉低使能端来快速关闭。许多高频开关
电源在功率器件的栅极都存在噪音，这种噪音会进入栅
极驱动器的输出引脚，造成驱动器故障。该器件凭借其
瞬态反向电流和反向电压能力，能够承受功率器件或脉
冲变压器的栅极噪声，并避免驱动器故障。
• 宽VDD 工作电压范围：4.5V 至26V，具有UVLO
功能
• 可实现高抗噪性的迟滞逻辑阈值
• VDD 独立输入阈值（兼容TTL）
• 快速传播延迟（典型值为17ns）
• 快速上升和下降时间（典型值为6ns 和10ns）
• 两个通道之间的延迟匹配时间典型值为1 ns
• 可将两个通道并联以获得更高的驱动电流
• SOIC8 和VSSOP8 PowerPAD™ 封装选项
• 工作结温范围：–40°C 至150°C
UCC27624-Q1 还具有欠压锁定 (UVLO) 功能，可提高
系统稳健性。当没有足够的偏置电压来全面增强功率器
件时，强大的内部下拉 MOSFET 使栅极驱动器输出保
持在低电平。
2 应用
• 汽车直流/直流转换器
• 开关模式电源(SMPS)
• 功率因数校正(PFC) 电路
• 直流/直流转换器
• 电机驱动器
器件信息
器件型号(1)
UCC27624-Q1
UCC27624-Q1
封装尺寸（标称值）
4.90mm × 3.91mm
3.00mm × 3.00mm
封装
SOIC (8)
VSSOP (8)
• 太阳能电源
• 脉冲变压器驱动器
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VBias
+
CVDD
To Switch
–
Node
ENB
ENA
1
8
VDD
Rg
INA
6
2
4
3
To Switch
Node
OUTA
OUTB
INB
7
5
Rg
GND
简化版应用图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSES4
UCC27624-Q1
ZHCSPL5B –MARCH 2022 –REVISED NOVEMBER 2022
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Table of Contents
7.4 Device Functional Modes..........................................16
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 18
9 Power Supply Recommendations................................22
10 Layout...........................................................................23
10.1 Layout Guidelines................................................... 23
10.2 Layout Example...................................................... 24
10.3 Thermal Considerations..........................................24
11 Device and Documentation Support..........................25
11.1 第三方产品免责声明................................................25
11.2 接收文档更新通知................................................... 25
11.3 支持资源..................................................................25
11.4 Trademarks............................................................. 25
11.5 Electrostatic Discharge Caution..............................25
11.6 术语表..................................................................... 25
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Timing Diagrams ........................................................7
6.8 Typical Characteristics................................................8
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................13
Information.................................................................... 25
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (May 2022) to Revision B (November 2022)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
Changes from Revision * (March 2022) to Revision A (May 2022)
Page
• 添加了汽车认证...................................................................................................................................................1
• Updated ESD ratings..........................................................................................................................................4
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5 Pin Configuration and Functions
1
2
3
4
8
7
6
5
ENA
ENB
INA
GND
INB
OUTA
VDD
OUTB
图5-1. D Package 8-Pin SOIC Top View
ENA
INA
ENB
1
2
3
4
8
7
6
5
OUTA
VDD
GND
INB
OUTB
图5-2. DGN Package 8-Pin VSSOP Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
DGN
D
Enable input for Channel A. Biasing ENA, LOW will disable Channel A output
regardless of the state of INA. Pulling ENA, HIGH enables the Channel A output. If
ENA is left floating, Channel A is enabled by default due to an internal pullup
resistor. It is recommended to connect this pin to VDD if unused.
ENA
1
8
1
I
Enable input for Channel B. Biasing ENB, LOW disables Channel B output
regardless of the state of INB. Pulling ENB, HIGH enables the Channel B output. If
ENB is left floating, Channel B is enabled by default due to an internal pullup
resistor. It is recommended to connect this pin to VDD if unused.
ENB
8
I
GND
INA
3
2
3
2
Ground: All signals are referenced to this pin.
—
Input to Channel A. INA is the non-inverting input of the UCC27624-Q1 device.
OUTA is held LOW if INA is unbiased or floating by default due to an internal
pulldown resistor. Connect this pin to GND if unused.
I
Input to Channel B. INB is the non-inverting input of the UCC27624-Q1 device.
OUTB is held LOW if INB is unbiased or floating by default due to an internal
pulldown resistor. Connect this pin to GND if unused.
INB
4
4
I
OUTA
OUTB
7
5
7
5
O
O
Channel A Output
Channel B Output
Bias supply input. Bypass this pin with two ceramic capacitors, generally ≥1 μF
and 0.1 μF, which are referenced to GND pin of this device.
VDD
6
6
I
Thermal
Pad
Connect to GND through large copper plane. This pad is not a low-impedance path
to GND.
—
—
(1) I = Input; O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
–0.3
–0.3
–2
MAX
UNIT
Supply voltage, VDD
30
V
DC
Output Voltage, OUTA, OUTB
200ns Pulse
VDD +0.3
VDD +3
30
V
V
Input Voltage INA, INB, ENA, ENB
Operating junction temperature, TJ
V
–10
–40
150
°C
Soldering, 10 sec.
300
Lead temperature
Reflow
°C
°C
260
Storage temperature, Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See 节
6.4 of the datasheet for thermal limitations and considerations of packages.
(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range. All voltages are with reference to GND (unless otherwise noted)
MIN
NOM
MAX
26
UNIT
V
Supply voltage, VDD
4.5
12
Input voltage, INA, INB, ENA, ENB
Output Voltage, OUTA, OUTB
Operating junction temperature, TJ
26
V
–10
0
VDD
150
V
°C
–40
6.4 Thermal Information
UCC27624-Q1
THERMAL METRIC
DGN
D
UNIT
8 PINS
8 PINS
126.4
RθJA
Junction-to-ambient thermal resistance
48.9
RθJC(top)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
71.8
22.3
2.6
67.0
69.9
19.2
69.1
n/a
RθJB
ψJT
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
22.3
4.5
RθJC(bot)
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6.5 Electrical Characteristics
Unless otherwise noted, VDD = 12 V, TA = TJ = –40°C to 150°C, 1-µF capacitor from VDD to GND, no load on the output.
Typical condition specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BIAS CURRENTS
VDD quiescent supply
current
IVDDq
VINx = 3.3 V, VDD = 3.4 V, ENx = VDD
300
450
μA
IVDD
IVDD
IVDDO
IDIS
VDD static supply current
VDD static supply current
VDD operating current
VDD disable current
VINx = 3.3 V, ENx = VDD
0.6
0.7
3.2
0.8
1.0
1.0
3.8
1.1
mA
mA
mA
mA
VINx = 0 V, ENx = VDD
fSW = 1000 kHz, ENx = VDD, VINx = 0 V –3.3 V PWM
VINx = 3.3 V, ENx = 0 V
UNDERVOLTAGE LOCKOUT (UVLO)
VVDD_ON
VVDD_OFF
VVDD_HYS
VDD UVLO rising threshold
VDD UVLO falling threshold
VDD UVLO hysteresis
3.8
3.5
4.1
3.8
0.3
4.4
4.1
V
V
V
INPUT (INA, INB)
VINx_H
VINx_L
VINx_HYS
RINx
Input signal high threshold
Output High, ENx = HIGH
Output Low, ENx = HIGH
1.8
0.8
2
1
2.3
1.2
V
V
Input signal low threshold
Input signal hysteresis
INx pin pulldown resistor
1
V
INx = 3.3 V
120
kΩ
ENABLE (ENA, ENB)
VENx_H
VENx_L
VENx_HYS
RENx
Enable signal high threshold Output High, INx = HIGH
1.8
0.8
2
1
2.3
1.2
V
V
Enable signal low threshold
Enable signal hysteresis
EN pin pullup resistance
Output Low, INx = HIGH
1
V
ENx = 0 V
200
kΩ
OUTPUTS (OUTA, OUTB)
(1)
ISRC
Peak output source current
VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz
VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz
5
A
A
(1)
(2)
ISNK
Peak output sink current
–5
IOUT = –50 mA
See 节7.3.4.
ROH
ROL
Pullup resistance
5
8.5
1.1
Ω
Ω
Pulldown resistance
IOUT = 50 mA
0.6
(1) Parameter not tested in production.
(2) Output pullup resistance in this table is a DC measurement that measures resistance of PMOS structure only (not N-channel
structure).
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6.6 Switching Characteristics
Unless otherwise noted, VDD = VEN = 12 V, TA = TJ = –40°C to 150°C, 1-µF capacitor from VDD to GND, no load on the
output. Typical condition specifications are at 25°C (1)
.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
tRx
tFx
Rise time
Fall time
6
10
14
ns
ns
CLOAD = 1.8 nF, 20% to 80%, Vin = 0 V –3.3 V
CLOAD = 1.8 nF, 90% to 10%, Vin = 0 V –3.3 V
10
CLOAD = 1.8 nF, VINx_H of the input rise to 10% of output rise,
Vin = 0 V –3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C
tD1x
tD2x
Turn-on propagation delay
Turn-off propagation delay
17
17
27
27
ns
ns
CLOAD = 1.8 nF, VINx_L of the input fall to 90% of output fall, Vin
= 0 V –3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C
CLOAD = 1.8 nF, VENx_H of the enable rise to 10% of output
rise, Vin = 0 V –3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ =
125°C
tD3x
Enable propagation delay
Disable propagation delay
17
17
27
27
ns
ns
CLOAD = 1.8 nF, VENx_L of the enable fall to 90% of output fall,
Vin = 0 V –3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C
tD4x
Delay matching between
two channels
CLOAD = 1.8 nF, Vin = 0 V –3.3 V, Fsw = 500 kHz, 50% duty
tM
1
2
ns
ns
cycle, INA = INB, |tRA –tRB|, |tFA –tFB
|
tPWmin
Minimum input pulse width
10
15
CL = 1.8 nF, Vin = 0 V –3.3 V, Fsw = 500 kHz, Vo > 1.5 V
(1) Switching parameters are not tested in production.
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6.7 Timing Diagrams
High
Input
Low
VENx_H
Enable
VENx_L
90%
Output
10%
tD4
tD3
图6-1. Enable Function
VINx_H
Input
VINx_L
High
Enable
Low
90%
Output
10%
tD1
tD2
图6-2. Input-Output Operation
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6.8 Typical Characteristics
Unless otherwise specified, VDD=12 V, INx = 3.3 V, ENx = 3.3 V, TJ = 25°C, no load
5
4.5
4
3.5
3
2.5
2
1.5
1
4.5VDD
12VDD
26VDD
0.5
0
1
2
3 4 567 10
20 30 50 70100 200
Frequency (kHz)
500 1000
图6-4. Operating Supply Current (Both Outputs Switching)
图6-3. Start-Up and Quiescent Current
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
ON
OFF
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD Voltage (V)
图6-5. Static Supply Current (Outputs in DC On or Off
图6-6. Disable Current (EN = 0 V)
Condition)
4.11
4.08
2.2
Rise
Fall
Rise
Fall
2
4.05
4.02
3.99
3.96
3.93
3.9
1.8
1.6
1.4
1.2
1
3.87
3.84
3.81
3.78
0.8
-40 -20
0
20
40
60
80 100 120 140 160
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
Temperature (°C)
图6-7. VDD UVLO Threshold
图6-8. Input Thresholds
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6.8 Typical Characteristics (continued)
Unless otherwise specified, VDD=12 V, INx = 3.3 V, ENx = 3.3 V, TJ = 25°C, no load
2.2
Rise
Fall
2
1.8
1.6
1.4
1.2
1
0.8
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
图6-10. Enable Threshold
图6-9. Input Pulldown Resistance
图6-11. Enable Pullup Resistance
图6-13. Output Pulldown Resistance
图6-12. Output Pullup Resistance
CLOAD = 1.8 nF
图6-14. Output Rise Time vs VDD
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6.8 Typical Characteristics (continued)
Unless otherwise specified, VDD=12 V, INx = 3.3 V, ENx = 3.3 V, TJ = 25°C, no load
CLOAD = 1.8 nF
CLOAD = 1.8 nF
图6-15. Output Fall Time vs VDD
图6-16. Output Rise and Fall Time vs Temperature
21
20.5
20
24
23.5
23
22.5
22
19.5
19
21.5
21
18.5
18
20.5
20
17.5
17
19.5
19
16.5
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
CLOAD = 1.8 nF
CLOAD = 1.8 nF
图6-17. Input to Output Rising (Turn-On) Propagation Delay vs 图6-18. Input to Output Falling (Turn-Off) Propagation Delay vs
VDD
VDD
21
20.5
20
19.5
19
18.5
18
17.5
17
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
CLOAD = 1.8 nF
CLOAD = 1.8 nF
图6-20. Enable to Output Rising Propagation Delay
图6-19. Input Propagation Delay vs Temperature
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6.8 Typical Characteristics (continued)
Unless otherwise specified, VDD=12 V, INx = 3.3 V, ENx = 3.3 V, TJ = 25°C, no load
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
图6-22. Turn-on/Rising Delay Matching
CLOAD = 1.8 nF
图6-21. Enable to Output Falling Propagation Delay
0.5
0.45
0.4
9
8.5
8
7.5
7
0.35
0.3
6.5
6
0.25
0.2
5.5
5
4.5
4
0.15
0.1
3.5
3
0.05
0
2.5
2
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
图6-23. Turn-Off and Falling Delay Matching
图6-24. Peak Source Current vs VDD
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
图6-25. Peak Sink Current vs VDD
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7 Detailed Description
7.1 Overview
The UCC27624-Q1 device represents TI's latest generation of dual-channel, low-side, high-speed, gate driver
devices featuring 5-A source and sink current capability, fast switching characteristics, and a host of other
features. UCC27624-Q1 Features and Benefits details the advantages of the gate driver's features, which
combine to ensure efficient, robust, and reliable operation in high-frequency switching power circuits. The robust
inputs of UCC27624-Q1 can handle –10 V, ensuring reliable operation in noisy environments. The driver has
good transient handling capability on its output due to its reverse current handling, as well as rail-to-rail output
drive, and a small propagation delay (typically 17 ns). With this built-in robustness, the UCC27624-Q1 device
can also be directly connected to a gate drive transformer.
The input threshold of UCC27624-Q1 is compatible with TTL low-voltage logic, which is fixed and independent of
VDD supply voltage. The driver can also work with CMOS-based controllers as long as the threshold
requirement is met. The 1-V typical hysteresis offers excellent noise immunity.
Each channel has an enable pin, ENx, with a fixed TTL compatible threshold. The ENx pins are internally pulled
up. Pulling ENx low disables the corresponding channel, while leaving ENx open provides normal operation. The
ENx pins can be used as an additional input with the same performance as the INx pins.
表7-1. UCC27624-Q1 Features and Benefits
FEATURE
BENEFIT
Enhanced signal reliability and device robustness in noisy
environments that experience ground bounce on the gate driver
–10-V IN and EN capability
17-ns (typical) propagation delay
Extremely low-pulse transmission distortion
Ease of paralleling outputs for higher (two times) current capability.
This helps when driving parallel-power switches.
1-ns (typical) delay matching between channels
Expanded VDD operating range of 4.5 V to 26 V
Flexibility in system design. Covers a wide range of power switches
Flexibility in system design. System robustness improvement
Expanded operating temperature range of –40°C to +150°C
Outputs are held low in UVLO condition, which ensures predictable,
glitch-free operation at power-up and power-down.
VDD UVLO protection
Protection feature, especially useful in passing abnormal condition
tests during safety certification
Outputs are held low when input pins (INx) are in floating condition.
Outputs are enabled when enable pins (ENx) are in floating
condition.
Pin-to-pin compatibility with legacy devices from Texas Instruments
in designs where Pin 1 and Pin 8 are "No Connect" pins
Enhanced noise immunity while retaining compatibility with
microcontroller logic-level input signals (3.3 V, 5 V) optimized for
digital power
Input and enable threshold with wide hysteresis
Inputs independent of VDD
System simplification, especially related to auxiliary bias supply
architecture
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7.2 Functional Block Diagram
VDD
INB
4
8
5
ENB
VDD
VDD
DRIVER
STAGE
OUTB
ENA
INA
1
2
UVLO
VDD
6
7
VDD
DRIVER
STAGE
OUTA
GND
3
Typical ENx pullup resistance is 200 kΩand INx pulldown resistance is 120 kΩ.
7.3 Feature Description
7.3.1 Operating Supply Current
The UCC27624-Q1 device features low quiescent IDD currents. The typical operating supply current in UVLO
state and fully-on state (under static and switching conditions) are summarized in the Electrical Characteristics
table. The lowest quiescent current (IDD) is achieved when the device is fully on and the outputs are in a static
state (DC high or DC low). During this state, all of the internal logic circuits of the device are fully operational.
The total supply current is the sum of the quiescent IDD current, the average IOUT current because of switching,
and any current related to pullup resistors on the enable pins. Knowing the operating switching frequency (fSW
and the MOSFET gate charge (QG) at the drive voltage being used, the average IOUT current can be calculated
as product of QG and fSW
)
.
Typical Characteristics provides a complete characterization of the IDD current as a function of switching
frequency at different VDD bias voltages. The linear variation and close correlation with the theoretical value of
the average IOUT indicate a negligible shoot-through inside the gate driver device, displaying its high-speed
characteristics.
7.3.2 Input Stage
The input pins of the UCC27624-Q1 gate driver device are based on a TTL compatible input threshold logic that
is independent of the VDD supply voltage. With a high threshold of 2 V and a low threshold of 1 V, the logic level
thresholds are conveniently driven with PWM control signals derived from 3.3-V and 5-V digital power controller
devices. Wider hysteresis (1-V typical) offers enhanced noise immunity compared to traditional TTL logic
implementations, where the hysteresis is typically less than 0.5 V. UCC27624-Q1 devices also feature tight
control of the input pin threshold voltage levels, which eases system design considerations and ensures stable
operation across temperature (refer to Typical Characteristics). The very low input capacitance on these pins
reduces loading and increases switching speed.
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The UCC27624-Q1 device features an important protection feature that holds the output of a channel low when
the respective input pin is in a floating condition. This is achieved through the internal pulldown resistors to
ground on both of the input pins (INA, INB), as shown in .
The input pins can handle wide range of slew rate. In most power supply applications, the gate driver is either
driven by the output of a digital controller or logic gates. Therefore, in most applications the input signal slew rate
is fast and is no concern for the UCC27624 family of devices. The wide hysteresis offered in UCC27624-Q1
alleviates the concern of chattering compared to many other drivers that have very small hysteresis at the input.
If limiting the rise or fall times to the power device is the primary goal, then an external gate resistor is highly
recommended between the output of the driver and the gate of the switching power device. This external resistor
has the additional benefit of reducing part of the gate-charge related power dissipation in the gate driver device
package and transferring it into the external resistor itself. In short, some of the power gets dissipated in the gate
resistor rather than inside of the gate driver. Additionally, the input pins of UCC27624-Q1 are capable of handling
–10 V. This improves the system robustness in noisy (electrical) applications. This also enables the driver to
directly connect to the output of a gate drive transformer without the use of rectifying diodes, which saves board
space and BOM cost.
7.3.3 Enable Function
The enable function is an extremely beneficial feature in gate driver devices, especially for certain applications
such as synchronous rectification where the driver outputs are disabled in light-load conditions to prevent
negative current circulation and to improve light-load efficiency.
The UCC27624-Q1 device is equipped with independent enable pins (ENx) for exclusive control of each driver
channel operation. The enable pins are based on a non-inverting configuration (active-high operation). Thus,
when ENx pins are driven high, the drivers are enabled and when ENx pins are driven low, the driver outputs are
disabled. Similar to the input pins, the enable pins are also based on a TTL compatible threshold logic that is
independent of the supply voltage and are effectively controlled using logic signals from 3.3-V or 5-V controllers.
The UCC27624-Q1 device also features tight control of the enable-function threshold-voltage levels which eases
system design considerations and ensures stable operation across temperature. The ENx pins are internally
pulled up to VDD using pullup resistors, as a result of which the outputs of the device are enabled in the default
state. Hence even if the ENx pins are left floating the driver output is enabled. Essentially, this floating allows the
UCC27624-Q1 device to be pin-to-pin compatible with TI’s previous generation of drivers (UCC27324,
UCC27424, UCC27524), where Pin 1 and Pin 8 are either ENx or N/C pins. If the channel A and channel B
inputs and outputs are connected in parallel to increase the driver current capacity, ENA and ENB must be
connected and driven together. The ENx pins of the UCC27624-Q1 are capable of handling –10 V, which
improves system robustness in noisy (electrical) applications.
7.3.4 Output Stage
The UCC27624-Q1 device output stage features a unique architecture on the pullup structure, which delivers the
highest peak source current when it is most needed, during the Miller plateau region of the power switch turn-on
transition (when the power switch drain or collector voltage experiences dV/dt). The device output stage features
a hybrid pullup structure using a parallel arrangement of N-Channel and P-Channel MOSFET devices. By
turning on the N-Channel MOSFET during a narrow instant when the output changes state from low to high, the
gate driver device is able to deliver a brief boost in the peak sourcing current enabling fast turn-on. The on-
resistance of this N-channel MOSFET (RNMOS) is approximately 1.04 Ωwhen activated.
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VDD
ROH
RNMOS ,Pull Up
OUT
An Shoot-
Through
Input Signal
Circuitry
Narrow Pulse at
each Turn On
ROL
图7-1. UCC27624-Q1 Gate Driver Output Structure
The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-Channel device
only. This is because the N-Channel device is held in the off state in DC condition and is turned-on only for a
narrow instant when output changes state from low to high. Note that effective resistance of the UCC27624-Q1
pull-up stage during the turn-on instance is much lower than what is represented by ROH parameter.
The pull-down structure in the UCC27624-Q1 device is simply comprised of a N-Channel MOSFET. The ROL
parameter, which is also a DC measurement, is representative of the impedance of the pull-down stage in the
device.
Each output stage in the UCC27624-Q1 device is capable of supplying 5-A peak source and 5-A peak sink
current pulses. The output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the
MOS-output stage which delivers very low dropout. The presence of the MOSFET-body diodes also offers low
impedance to transient overshoots and undershoots. The outputs of these drivers are designed to withstand 5A
of peak reverse current transients without damage to the device.
The UCC27624-Q1 device is particularly suited for dual-polarity, symmetrical drive-gate transformer applications
where the primary winding of transformer driven by OUTA and OUTB, with inputs INA and INB being driven
complementary to each other. This is possible because of the extremely low dropout offered by the MOS output
stage of these devices, both during high (VOH) and low (VOL) states along with the low impedance of the driver
output stage. All of these allow alleviate concerns regarding transformer demagnetization and flux imbalance.
The low propagation delays also ensure proper reset for high-frequency applications.
For applications that have zero voltage switching during power MOSFET turn-on or turn-off interval, the driver
supplies high-peak current for fast switching even though the miller plateau is not present. This situation often
occurs in synchronous rectifier applications because the body diode is generally conducting before power
MOSFET is switched on.
7.3.5 Low Propagation Delays and Tightly Matched Outputs
The UCC27624-Q1 driver device features a very small, 17-ns (typical) propagation delay between input and
output, which offers the lowest level of pulse width distortion for high-frequency switching applications. For
example, in synchronous rectifier applications, the SR MOSFETs are driven with very low distortion when a
single driver device is used to drive the SR MOSFETs. Additionally, the driver devices also feature extremely
accurate, 1-ns (typical) matched internal propagation delays between the two channels, which is beneficial for
applications that require dual gate drives with critical timing. For example, in a PFC application, a pair of
paralleled MOSFETs can be driven independently using each output channel, with the inputs of both channels
driven by a common control signal from the PFC controller. In this case, the 1-ns delay matching ensures that
the paralleled MOSFETs are driven in a simultaneous fashion, minimizing turn-on and turn-off delay differences.
Another benefit of the tight matching between the two channels is that the two channels can be connected
together to effectively double the drive current capability. That is, A and B channels may be combined into a
single driver by connecting the INA and INB inputs together and the OUTA and OUTB outputs together; then, a
single signal controls the paralleled power devices.
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7.4 Device Functional Modes
表7-2. Device Logic Table
UCC27624-Q1
ENA
ENB
INA
INB
OUTA
OUTB
L
H
L
L
L
H
L
L
H
H
L
H
H
L
H
H
H
L
L
L
Any
Any
Float
L
Any
Any
Float
L
L
L
L
L
H
L
H
L
Float
Float
L
H
H
H
H
H
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
High-current gate driver devices are required in switching power applications for a variety of reasons. In order to
achieve fast switching of power devices and reduce associated switching-power losses, a powerful gate driver
device is employed between the PWM output of control devices and the gates of the power semiconductor
devices. Further, gate driver devices are indispensable when it is not feasible for the PWM controller device to
directly drive the gates of the switching devices. With the advent of digital power, this situation is often
encountered because the PWM signal from the digital controller is often a 3.3-V logic signal which is not capable
of effectively turning ON a power switch. A level-shifting circuitry is required to boost the 3.3-V signal to the gate-
drive voltage (such as 12 V) in order to fully turn ON the power device and minimize conduction losses.
Traditional buffer-drive circuits based on NPN/PNP bipolar transistors in a totem-pole arrangement, as emitter-
follower configurations, prove inadequate with digital power because the traditional buffer-drive circuits lack
level-shifting capability. Gate driver devices effectively combine both the level-shifting and buffer-drive functions.
Gate driver devices also find other needs ,such as minimizing the effect of high frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power device gates, reducing power dissipation and thermal stress in controller devices by
moving gate-charge power losses into the controller.
Finally, emerging wide band-gap power device technologies, such as SiC MOSFETs and GaN switches, which
are capable of supporting very high switching frequency operation, are driving special requirements in terms of
gate-drive capability. These requirements include a wide operating voltage range (5 V to 26 V), low propagation
delays, good delay matching, and availability in compact, low inductance packages with good thermal capability.
In summary, gate driver devices are an extremely important component in switching power combining benefits of
high performance, low cost, low component count, board space reduction, and simplified system design.
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8.2 Typical Application
400V
LBoost
+
DC or
Rectified AC
Vin
–
LBoost
To Load
VBias
ENB
ENA
VDD
OUTA
OUTB
RGS
INA
RGS
CVDD
From
GND
Controller
INB
图8-1. UCC27624-Q1 Typical Application Diagram
8.2.1 Design Requirements
When selecting and designing-in the gate driver device for an end application, some functional aspects must be
considered and evaluated first, in order to make the most appropriate selection. Among these considerations are
bias voltage, UVLO, drive current, and power dissipation.
8.2.2 Detailed Design Procedure
8.2.2.1 VDD and Undervoltage Lockout
The UCC27624-Q1 device has an internal undervoltage-lockout (UVLO) protection feature on the VDD pin
supply circuit blocks. When VDD is rising and the level is still below UVLO threshold, this circuit holds the output
low, regardless of the status of the inputs. The UVLO is typically 4 V with 300-mV typical hysteresis. This
hysteresis prevents chatter when VDD supply voltages have noise, specifically at the lower end of the VDD
operating range. UVLO hysteresis is also important to avoid any false tripping due to the bias noise generated
because of fast switching transitions, where large peak currents are drawn from the bias supply bypass
capacitors. The driver capability to operate at wide bias voltage range, along with good switching characteristics,
is especially important in driving emerging power semiconductor devices, such as advanced low gate charge fast
MOSFETs, GaN FETs, and SiC MOSFETs.
At power-up, the UCC27624-Q1 driver device output remains low until the VDD voltage reaches the UVLO rising
threshold, irrespective of the state of any other input pins such as INx and ENx. After the UVLO rising threshold,
the magnitude of the OUT signal rises with VDD until steady-state VDD is reached.
For the best high-speed circuit performance and to prevent noise problems because the device draws current
from the VDD pin to bias all internal circuits, use two VDD bypass capacitors. Also, use surface mount, low ESR
capacitors. A 0.1-μF ceramic capacitor should be located less than 1 mm from the VDD to GND pins of the
gate-driver device. In addition, a larger capacitor (≥1 μF) must be connected in parallel (also as close to the
driver IC as possible) to help deliver the high-current peaks required by the load. The parallel combination of
capacitors presents a low impedance characteristic for the expected current levels and switching frequencies in
the application.
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VDD Threshold
VDD
EN
IN
OUT
UDG-11228
图8-2. Power-Up Sequence
8.2.2.2 Drive Current and Power Dissipation
The UCC27624-Q1 driver is capable of delivering 5 A of peak current to a switching power device gate
(MOSFET, IGBT, SiC MOSFET, GaN FET) for a period of several-hundred nanoseconds at VDD = 12 V. High
peak current is required to turn ON the device quickly. Then, to turn the device OFF, the driver is required to sink
a similar amount of current to ground, which repeats at the operating switching frequency of the power device.
The power dissipated in the gate driver device package depends on the following factors:
• Gate charge of the power MOSFET (usually a function of the drive voltage VGS, which is very close to input
bias supply voltage VDD due to low VOH drop-out).
• Switching frequency
• External gate resistors
Because UCC27624-Q1 features low-quiescent currents and internal logic to eliminate any shoot-through in the
output driver stage, their effect on the power dissipation within the gate driver is very small compared to the
losses due to switching of the power device.
When a driver device is tested with a discrete capacitive load, calculating the power that is required from the bias
supply is fairly simple. The following equation provides an example of the energy that must transfer from the bias
supply to charge the capacitor.
1
2
EG
=
CLOADVDD
2
(1)
where
• CLOAD is the load capacitor.
• VDD is the bias voltage of the driver.
There is an equal amount of energy dissipated when the capacitor is discharged. This leads to a total power
loss, as shown in the following equation example.
2
LOAD DD SW
P
= C
V
f
G
(2)
where
• fSW is the switching frequency.
With VDD = 12 V, CLOAD = 10 nF and fSW = 300 kHz, the switching power loss is calculated as follows:
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2
= 10nF´12V ´300kHz = 0.432W
P
G
(3)
The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the
gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the
added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to
switch the device under specified conditions. Using the gate charge Qg, the power that must dissipate when
charging a capacitor is determined, which by using the equivalence Qg = CLOADVDD is shown in the following
equation.
2
LOAD DD SW
P
= C
V
f
= Q V f
g DD SW
G
(4)
Assuming that the UCC27624-Q1 device is driving power MOSFET with 60 nC of gate charge (Qg = 60 nC at
VDD = 12 V) on each output, the gate charge related power loss is calculated using the equation below.
P
= 2x60nC´12V ´300kHz = 0.432W
G
(5)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET turns on or turns off. Half
of the total power is dissipated when the load capacitor is charged during turn-on, and the other half is dissipated
when the load capacitor is discharged during turn-off. When no external gate resistor is employed between the
driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external
gate resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor
in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based
on this simplified analysis, the driver power dissipation during switching is calculated as follows:
æ
ç
è
ö
÷
ø
R
R
ON
OFF
P
= 0.5´Q ´ VDD´ f ´
SW
+
SW
G
R
+ R
R
+ R
ON GATE
OFF
GATE
(6)
where
• ROFF = ROL
• RON (effective resistance of pull-up structure)
The above equation is necessary when the external gate resistor is large enough to reduce the peak current of
the driver. In addition to the above gate-charge related power dissipation, dissipation in the driver is related to
the power associated with the quiescent bias current consumed by the device to bias all internal circuits such as
input stage (with pullup and pulldown resistors), enable, and UVLO sections. As shown in the electrical
characteristics table, the quiescent current is less than 1 mA. The power loss due to DC current consumption of
the driver internal circuit can be calculated as below.
P
= I
V
Q
DD DD
(7)
Assuming total internal current consumption to be 0.6 mA (typical) at bias voltage of 12 V, the DC power loss in
the driver is:
P
= 0.6 mA ´12V = 7.2mW
Q
(8)
This power loss is insignificant compared to gate charge related power dissipation calculated earlier.
With a 12-V supply, the bias current is estimated as follows, with an additional 0.6-mA overhead for the
quiescent consumption:
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P
0.432 W
12 V
G
I
~
=
= 0.036 A
DD
V
DD
(9)
If the gate driver is used with inductive load, then special attention should be paid to the ringing on each pin of
the gate driver device. The ringing should not exceed the recommended operating rating of the pin.
8.2.3 Application Curves
The figures below show the typical switching characteristics of the UCC27624-Q1 device used in high-voltage
boost converter application. In this application, the UCC27624-Q1 is driving the IGBT switch that has a gate
charge of
110 nC.
Vout
LBoost
+
To Load
Vin
–
VBias
ENB
VDD
ENA
OUTA
OUTB
INA
From
CVDD
Controller
GND
INB
图8-3. UCC27624-Q1 Used to Drive IGBT in the Boost Converter
Vin = 210 V, Vout = 235 V, Iout = 1.14 A, Fsw = 100 kHz,
Vin = 210 V, Vout = 235 V, Iout = 1.14 A, Fsw = 125 kHz,
driver supply voltage = 15 V, gate resistor = 0 Ω
driver supply voltage = 15 V, gate resistor = 0 Ω
图8-5. Turn-Off Propagation Delay Waveform
图8-4. Turn-On Propagation Delay Waveform
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9 Power Supply Recommendations
The bias supply voltage range for the UCC27624-Q1 device is rated to operate is from 4.5 V to 26 V. The lower
end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD pin
supply circuit blocks. If the driver is in a UVLO condition when the VDD pin voltage is below the VDD UVLO turn-
on (rising) threshold, the UVLO protection feature holds the output low, regardless of the status of the inputs.
The upper end of this range is driven by the 30-V absolute maximum voltage rating of the VDD pin of the device
(which is a stress rating). It is necessary to have sufficient margin from the absolute maximum rating of the
device to realize full operating life of the device. Therefore, the upper limit of recommended voltage of the VDD
pin is 26 V.
The UVLO protection feature also has a hysteresis function. This means, when the VDD pin bias voltage
exceeds the rising threshold voltage, the device begins to operate normally. If the VDD bias voltage drops below
the rising threshold while on, the device continues to deliver normal functionality unless the voltage drop
exceeds the hysteresis specification of the falling threshold. Therefore, while operating at or near the 4.5-V,
design engineer should ensure that the voltage ripple on the auxiliary power supply output is smaller than the
hysteresis specification of the device. Otherwise, the device output may turn-off. During system shutdown, the
device operation continues until the VDD pin voltage has dropped below the VDD turn-off (falling) threshold,
which must be accounted for while evaluating system shutdown timing or sequencing requirements. At system
startup, the device does not begin operation until the VDD pin voltage has exceeded VDD turn-on (rising)
threshold.
The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin.
Although this fact is well known, recognizing that the charge for source current pulses delivered by the OUTA/B
pin is also supplied through the same VDD pin capacitor, is important. As a result, every time a current is
sourced out of the output pins, a corresponding current pulse is delivered into the device through the VDD pin.
Thus, ensure that the local bypass capacitors are provided between the VDD and GND pins and locate them as
close to the device pins as possible for the purpose of decoupling. A low ESR, ceramic surface mount capacitor
is required. TI recommends having two capacitors: a 0.1-μF ceramic surface-mount capacitor placed less than
1 mm from the VDD pin of the device and another larger ceramic capacitor (≥1 μF) must be connected in
parallel.
UCC27624-Q1 is a high-current gate driver. If the gate driver is placed far from the switching power device, such
as a MOSFET, then that could create a large inductive loop. A large inductive loop may cause excessive ringing
on any and all pins of the gate driver. This may result in stress that exceeds device recommended ratings.
Therefore, place the gate driver as close to the switching power device as possible. Also, use an external gate
resistor to damp any ringing due to the high switching currents and board parasitic elements.
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10 Layout
10.1 Layout Guidelines
Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device
operation and design robustness. The UCC27624-Q1 gate driver incorporates small propagation delays and
powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of
power MOSFET to facilitate very quick voltage transitions. Very high di/dt causes unacceptable ringing if the
trace lengths and impedances are not well controlled. The following circuit layout guidelines are recommended
when designing with these high-speed drivers.
• Place the driver IC as close as possible to the power device in order to minimize the length of high-current
traces between the driver IC output pins and the gate of the switching power device.
• Place the VDD bypass capacitors between VDD and GND as close as possible to the driver IC with minimal
trace length to improve the noise filtering. These capacitors support high peak current being drawn from VDD
pin, during turn-on of power MOSFET. The use of low inductance surface-mounted-device (SMD)
components such as 50V rated X7R chip capacitors are highly recommended.
• The turn-on and turn-off current loop paths (driver device, power MOSFET and VDD bypass capacitor) must
be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is
established in these loops at two instances, namely during turn-on and turn-off transients, which induces
significant voltage transients on the output pin of the driver device and Gate of the power MOSFET.
• Wherever possible, parallel the source and return traces to take advantage of flux cancellation.
• Separate power traces and signal traces, such as output and input signals.
• To minimize switch node transients and ringing, adding some gate resistance and/or snubbers on the power
devices may be necessary. These measures may also reduce EMI.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM
controller at one, single point. The connected paths must be as short as possible to reduce inductance and
be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT pin of the driver IC may corrupt
the input signals of the driver IC. The ground plane must not be a conduction path for any high current (power
stage) loop. Instead the ground plane must be connected to the star-point with one single trace to establish
the ground potential. In addition to noise shielding, the ground plane can help in power dissipation as well
• External gate resistor and parallel diode-resistor combination may come in handy when replacing any gate
driver IC with UCC27624-Q1 device in existing or new designs, specifically if they do not have the same drive
strength.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: UCC27624-Q1
UCC27624-Q1
ZHCSPL5B –MARCH 2022 –REVISED NOVEMBER 2022
www.ti.com.cn
10.2 Layout Example
Power stage
current
Output loop of driver
bias
loop
(bypass capacitor)
图10-1. UCC27624-Q1 Layout Example
10.3 Thermal Considerations
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the device package. In order for a gate driver device to be useful over a particular temperature
range, the package must allow for the efficient removal of the heat produced, while keeping the junction
temperature within the specified limit. For detailed information regarding the thermal information table, please
refer to the Semiconductor and IC Package Thermal Metrics Application Note (SPRA953).
Among the different package options available for the UCC27624-Q1 device, power dissipation capability of the
DGN package is of particular mention. The VSSOP-8 (DGN) package offers thermal pad for removing the heat
from the semiconductor junction through the bottom of the package. This pad is soldered to the copper on the
printed circuit board directly underneath the device package, reducing the thermal resistance to a very low value.
This allows a significant improvement in heat-sinking over the D package. The printed circuit board must be
designed with thermal lands and thermal vias to complete the heat removal subsystem. Note that the exposed
pads in the VSSOP-8 package are not directly connected to any leads of the package, however, PowerPAD is
thermally connected to the substrate of the device. TI recommends to externally connect the exposed pads to
GND pin of the driver IC in PCB layout.
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: UCC27624-Q1
UCC27624-Q1
ZHCSPL5B –MARCH 2022 –REVISED NOVEMBER 2022
www.ti.com.cn
11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: UCC27624-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PUCC27624QDGNRQ1
PUCC27624QDRQ1
UCC27624QDGNRQ1
UCC27624QDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HVSSOP
SOIC
DGN
D
8
8
8
8
2500
3000
TBD
TBD
Call TI
Call TI
-40 to 150
-40 to 150
-40 to 150
-40 to 150
Samples
Samples
Samples
Samples
Call TI
NIPDAU
NIPDAU
Call TI
HVSSOP
SOIC
DGN
D
2500 RoHS & Green
3000 RoHS & Green
Level-1-260C-UNLIM
Level-1-260C-UNLIM
624Q
27624Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jan-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC27624-Q1 :
Catalog : UCC27624
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008H
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
(0.48) MAX
NOTE 6
EXPOSED THERMAL PAD
(0.205) MAX
NOTE 6
4
5
0.25
GAGE PLANE
1.8
1.1
9
1.1 MAX
8
1
0.15
0.05
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.71
1.01
4229130/A 10/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
6. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008H
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.71)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.8)
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4229130/A 10/2022
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008H
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.71)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.8)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.91 X 2.01
1.71 X 1.80 (SHOWN)
1.56 X 1.64
0.125
0.15
0.175
1.45 X 1.52
4229130/A 10/2022
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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