REF1933AIDDCT [TI]
3.3V Vref、双输出 Vref 和 Vref/2 电压基准 | DDC | 5 | -40 to 125;
| 型号： | REF1933AIDDCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V Vref、双输出 Vref 和 Vref/2 电压基准 | DDC | 5 | -40 to 125 |
| 文件： | 总33页 (文件大小：2811K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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REF1925, REF1930, REF1933, REF1941
ZHCSCT4A –SEPTEMBER 2014–REVISED JANUARY 2017
REF19xx 低漂移、低功率、双路输出、VREF 和 VREF/2 电压基准
1 特性
3 说明
1
•
两个输出，VREF 和 VREF/2，便于在单电源系统中
使用
仅具有 正向电源电压的应用通常需要一个在模数转换
器 (ADC) 输入范围中间位置的附加稳定电压来偏置输
入双极信号。REF19xx 提供了一个可供 ADC 使用的
基准电压 (VREF) 和一个可用于偏置输入双极信号的高
精度电压 (VBIAS)。
•
出色的温度漂移性能：
–
-40℃ 至 125℃ 时为 25 ppm/°C（最大值）
•
•
高初始精度：±0.1%（最大值）
温度范围内的 VREF 和 VBIAS 跟踪：
REF19xx 在 VREF 和 VBIAS 输出端具有优异的温度漂移
（最大 25 ppm/°C）特性和初始精度 (0.1%)，同时可
保持静态电流低于 430µA。此外，VREF 和 VBIAS 输出
端可在 –40°C 至 85°C 的温度范围内彼此跟踪，精度
达 6 ppm/°C（最大值）。所有这些 特性 都可提高信
号链的精度并节省电路板空间，相比分立式解决方案而
言还能降低系统成本。仅 10mV 的超低压降允许器件
在极低输入电压条件下工作，这一特性在电池供电系统
中非常适用。
–
–
-40℃ 至 85℃ 时为 6 ppm/°C（最大值）
-40℃ 至 125℃ 时为 7 ppm/°C（最大值）
•
•
•
•
•
•
微型封装：SOT23-5
低压降电压：10mV
高输出电流：±20mA
低静态电流：360μA
线路调节：3 ppm/V
负载调节：8 ppm/mA
2 应用
VREF 和 VBIAS 电压具有同样出色的技术规范，而且灌
电流和拉电流能力同样强大。这些器件具有优异的长期
稳定性和低噪声级别，是高精度工业 应用的理想选
择。
•
数字信号处理:
–
–
电源逆变器
电机控制
•
•
•
•
•
电流感测
器件信息(1)
工业过程控制
医疗设备
部件名称
REF19xx
封装
封装尺寸（标称值）
小外形尺寸晶体管
(SOT) (5)
2.90mm x 1.60mm
数据采集系统
单电源系统
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
空白
空白
应用示例
VREF 和 VBIAS 与温度间的关系
Power
Supply
0.05
0.04
0.03
VBIAS
0.02
0.01
0
VIN+
VOUT
ADC
INA213
RSHUNT
ISENSE
-0.01
-0.02
VREF
-0.03
REF
VIN-
-0.04
-0.05
VBIAS
1.5 V
VREF
3.0 V
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
C001
REF1930
VIN
EN
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS697
REF1925, REF1930, REF1933, REF1941
ZHCSCT4A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 15
9.4 Device Functional Modes........................................ 16
10 Applications and Implementation...................... 17
10.1 Application Information.......................................... 17
10.2 Typical Application ................................................ 17
11 Power-Supply Recommendations ..................... 22
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................. 23
12.2 Layout Example .................................................... 23
13 器件和文档支持 ..................................................... 24
13.1 文档支持................................................................ 24
13.2 相关链接................................................................ 24
13.3 接收文档更新通知 ................................................. 24
13.4 社区资源................................................................ 24
13.5 商标....................................................................... 24
13.6 静电放电警告......................................................... 24
13.7 Glossary................................................................ 24
14 机械、封装和可订购信息....................................... 25
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics.......................................... 5
7.6 Typical Characteristics.............................................. 6
Parameter Measurement Information ................ 12
8.1 Solder Heat Shift..................................................... 12
8.2 Thermal Hysteresis ................................................. 13
8.3 Noise Performance ................................................. 14
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (September 2014) to Revision A
Page
•
•
•
Changed Input to Output in I/O column of pin 1 row in Pin Functions table ......................................................................... 3
Added Storage temperature parameter to Absolute Maximum Ratings table (moved from ESD Ratings table)................... 4
Changed ESD Ratings table: changed title and updated table format .................................................................................. 4
2
Copyright © 2014–2017, Texas Instruments Incorporated
REF1925, REF1930, REF1933, REF1941
www.ti.com.cn
ZHCSCT4A –SEPTEMBER 2014–REVISED JANUARY 2017
5 Device Comparison Table
PRODUCT
REF1925
REF1930
REF1933
REF1941
VREF
2.5 V
VBIAS
1.25 V
1.5 V
3.0 V
3.3 V
1.65 V
2.048 V
4.096 V
6 Pin Configuration and Functions
DDC Package
SOT23-5
(Top View)
5
VREF
VBIAS
GND
EN
1
2
3
4
VIN
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
VBIAS
GND
EN
Output
—
Bias voltage output (VREF / 2)
Ground
2
3
Input
Input
Output
Enable (EN ≥ VIN – 0.7 V, device enabled)
4
VIN
Input supply voltage
5
VREF
Reference voltage output (VREF)
Copyright © 2014–2017, Texas Instruments Incorporated
3
REF1925, REF1930, REF1933, REF1941
ZHCSCT4A –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–55
MAX
6
UNIT
VIN
Input voltage
EN
V
VIN + 0.3
150
Operating
Temperature
Junction, TJ
Storage, Tstg
150
°C
–65
170
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Supply input voltage range (IL = 0 mA, TA = 25°C)
VREF + 0.02(1)
5.5
V
(1) See Figure 24 in the Typical Characteristics section for the minimum input voltage at different load currents and temperature.
7.4 Thermal Information
REF19xx
THERMAL METRIC(1)
DDC (SOT23)
5 PINS
193.6
40.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
34.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
34.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2014–2017, Texas Instruments Incorporated
REF1925, REF1930, REF1933, REF1941
www.ti.com.cn
ZHCSCT4A –SEPTEMBER 2014–REVISED JANUARY 2017
7.5 Electrical Characteristics
At TA = 25°C, IL = 0 mA, and VIN = 5 V, unless otherwise noted. Both VREF and VBIAS have the same specifications.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy
–0.1%
0.1%
Output voltage temperature coefficient(1)
–40°C ≤ TA ≤ 125°C
±10
±1.5
±2
±25 ppm/°C
–40°C ≤ TA ≤ 85°C
–40°C ≤ TA ≤ 125°C
±6
VREF and VBIAS tracking over temperature(2)
ppm/°C
±7
LINE AND LOAD REGULATION
ΔVO(ΔVI)
Line regulation
VREF + 0.02 V ≤ VIN ≤ 5.5 V
3
8
35
20
ppm/V
0 mA ≤ IL ≤ 20 mA ,
VREF + 0.6 V ≤ VIN ≤ 5.5 V
Sourcing
Sinking
ΔVO(ΔIL)
Load regulation
ppm/mA
0 mA ≤ IL ≤ –20 mA,
VREF + 0.02 V ≤ VIN ≤ 5.5 V
8
20
POWER SUPPLY
360
3.3
430
460
5
Active mode
–40°C ≤ TA ≤ 125°C
ICC
Supply current
µA
Shutdown mode
–40°C ≤ TA ≤ 125°C
9
Device in shutdown mode (EN = 0)
Device in active mode (EN = 1)
0
0.7
VIN
20
Enable voltage
Dropout voltage
V
VIN – 0.7
10
mV
IL = 20 mA
600
ISC
Short-circuit current
Turn-on time
50
mA
µs
ton
0.1% settling, CL = 1 µF
500
NOISE
Low-frequency noise(3)
0.1 Hz ≤ f ≤ 10 Hz
12
ppmPP
Output voltage noise density
f = 100 Hz
0.25
ppm/√Hz
CAPACITIVE LOAD
Stable output capacitor range
0
10
µF
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability
0 to 1000 hours
60
60
35
ppm
ppm
Cycle 1
Cycle 2
Output voltage hysteresis(4)
25°C, –40°C, 125°C, 25°C
(1) Temperature drift is specified according to the box method. See the Feature Description section for more details.
(2) The VREF and VBIAS tracking over temperature specification is explained in more detail in the Feature Description section.
(3) The peak-to-peak noise measurement procedure is explained in more detail in the Noise Performance section.
(4) The thermal hysteresis measurement procedure is explained in more detail in the Thermal Hysteresis section.
Copyright © 2014–2017, Texas Instruments Incorporated
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www.ti.com.cn
7.6 Typical Characteristics
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
60
50
40
30
20
10
0
40
30
20
10
0
0
1
2
3
4
5
6
VREF and VBIAS Tracking Over Temperature (ppm/°C)
VREF and VBIAS Matching (ppm)
C016
C004
–40°C ≤ TA ≤ 85°C
Figure 2. Distribution of VREF – 2 × VBIAS Drift Tracking
Over Temperature
Figure 1. VREF – 2 × VBIAS Distribution
50
40
30
20
10
0
60
50
40
30
20
10
0
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
0
1
2
3
4
5
6
7
VREF and VBIAS Tracking Over Temperature (ppm/°C)
Solder Heat Shift Histogram - VREF (%)
C017
C041
–40°C ≤ TA ≤ 125°C
Refer to the Solder Heat Shift section for more information.
Figure 3. Distribution of VREF – 2 × VBIAS Drift Tracking
Over Temperature
Figure 4. Solder Heat Shift Distribution (VREF)
60
50
40
30
20
10
0
0.05
0.04
0.03
0.02
0.01
0
VBIAS
-0.01
-0.02
-0.03
-0.04
-0.05
VREF
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
œ75 œ50 œ25
0
25
50
75
100 125 150
Solder Heat Shift Histogram - VBIAS (%)
Temperature (°C)
C001
C040
Refer to the Solder Heat Shift section for more information.
Figure 5. Solder Heat Shift Distribution (VBIAS
)
Figure 6. Output Voltage Accuracy (VREF) vs Temperature
6
Copyright © 2014–2017, Texas Instruments Incorporated
REF1925, REF1930, REF1933, REF1941
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ZHCSCT4A –SEPTEMBER 2014–REVISED JANUARY 2017
Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
1000
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
750
-40°C
500
250
25°C
0
œ250
œ500
œ750
œ1000
125°C
œ75 œ50 œ25
0
25
50
75
100 125 150
œ20
œ15
œ10
œ5
0
5
10
15
20
Load Current (mA)
Temperature (°C)
C003
C038
VREF output
Figure 7. VREF – 2 × VBIAS Tracking vs Temperature
Figure 8. Output Voltage Change vs Load Current (VREF
)
12
1.2503
-40°C
11
10
9
1.2501
1.2499
1.2497
1.2495
1.2493
8
7
25°C
10
6
125°C
15
5
4
œ75 œ50 œ25
0
25
50
75
100 125 150
œ20
œ15
œ10
œ5
0
5
20
Temperature (°C)
Load Current (mA)
C025
C039
VREF output
IL = 20 mA
VBIAS output
Figure 10. Load Regulation Sourcing vs Temperature (VREF
)
Figure 9. Output Voltage Change vs Load Current (VBIAS
)
12
12
11
10
9
11
10
9
8
8
7
7
6
6
5
5
4
4
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C020
C021
VBIAS output
IL = 20 mA
VREF output
IL = –20 mA
Figure 11. Load Regulation Sourcing vs Temperature (VBIAS
)
Figure 12. Load Regulation Sinking vs Temperature (VREF)
Copyright © 2014–2017, Texas Instruments Incorporated
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REF1925, REF1930, REF1933, REF1941
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Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
5
4.5
4
12
11
10
9
3.5
3
8
7
6
2.5
2
5
4
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C022
C019
VBIAS output
IL = –20 mA
VREF output
Figure 14. Line Regulation vs Temperature (VREF
Figure 13. Load Regulation Sinking vs Temperature (VBIAS
)
)
5
100
4.5
4
VBIAS
80
60
40
20
VREF
3.5
3
2.5
2
œ75 œ50 œ25
0
25
50
75
100 125 150
1
10
100
1k
10k
100k
Temperature (°C)
Frequency (Hz)
C018
C026
VBIAS output
Figure 15. Line Regulation vs Temperature (VBIAS
CL = 0 µF
)
Figure 16. Power-Supply Rejection Ratio vs Frequency
100
VIN + 0.25 V
VIN + 0.25 V
VBIAS
500 mV/div
40 mV/div
VIN - 0.25 V
80
60
40
20
VREF
VREF
Time (500 µs/div)
1
10
100
1k
10k
100k
Frequency (Hz)
C027
C006
CL = 10 µF
Figure 17. Power-Supply Rejection Ratio vs Frequency
CL = 1 µF
Figure 18. Line Transient Response
8
Copyright © 2014–2017, Texas Instruments Incorporated
REF1925, REF1930, REF1933, REF1941
www.ti.com.cn
ZHCSCT4A –SEPTEMBER 2014–REVISED JANUARY 2017
Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
VIN + 0.25 V
VIN + 0.25V
500 mV/div
40 mV/div
+1 mA
+1 mA
VIN - 0.25V
2 mA/div
- 1 mA
VREF
VREF
20 mV/div
Time (500 µs/div)
Time (500 µs/div)
C006
C032
CL = 10 µF
Figure 19. Line Transient Response
CL = 1 µF
IL = ±1-mA step
Figure 20. Load Transient Response
+20 mA
+20 mA
+1 mA
+1 mA
40 mA/div
40 mV/div
2 mA/div
-20 mA
VREF
- 1 mA
VREF
20 mV/div
Time (500 µs/div)
Time (500 µs/div)
C037
C031
CL = 10 µF
IL = ±1-mA step
CL = 1 µF
IL = ±20-mA step
Figure 21. Load Transient Response
Figure 22. Load Transient Response
400
300
200
100
0
125°C
+20 mA
+20 mA
40 mA/div
40 mV/div
25°C
-20 mA
VREF
œ40°C
Time (500 µs/div)
œ30
œ20
œ10
0
10
20
30
Load Current (mA)
C036
C005
CL = 10 µF
IL = ±20-mA step
Figure 23. Load Transient Response
Figure 24. Minimum Dropout Voltage vs Load Current
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Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
VIN
VIN
2 V/div
2 V/div
VREF
VREF
Time (100 µs/div)
Time (100 µs/div)
C033
C034
CL = 1 µF
CL = 10 µF
Figure 26. Turn-On Settling Time
Figure 25. Turn-On Settling Time
500
450
400
350
300
250
200
500
450
400
350
300
250
200
œ75 œ50 œ25
0
25
50
75
100 125 150
2
3
4
5
6
Temperature (°C)
Input Voltage (V)
C006
C007
Figure 27. Quiescent Current vs Temperature
Figure 28. Quiescent Current vs Input Voltage
Time (1 s/div)
Time (1 s/div)
C028
C029
VREF output
VBIAS output
Figure 29. 0.1-Hz to 10-Hz Noise (VREF
)
Figure 30. 0.1-Hz to 10-Hz Noise (VBIAS)
10
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Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
1
100
CL = 0 ꢁF
10
CL = 0 µF
CL = 1µF
0.1
1
CL = 4.7 ꢀF
CL = 10 ꢁF
0.1
CL = 10 µF
0.01
0.01
1
10
100
Frequency (Hz)
1k
10k
0.01
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
C024
C030
VREF output
Figure 32. Output Impedance vs Frequency (VREF
Figure 31. Output Voltage Noise Spectrum
)
100
10
40
CL = 0 ꢁF
35
30
25
20
15
10
5
CL = 1µF
1
CL = 10 ꢁF
0.1
0.01
0
0.01
0.1
1
10
100
1k
10k
100k
Thermal Hysterisis - VREF (ppm)
Frequency (Hz)
C023
C013
VBIAS output
Figure 33. Output Impedance vs Frequency (VBIAS
)
Figure 34. Thermal Hysteresis Distribution (VREF
)
40
35
30
25
20
15
10
5
0
Thermal Hysteresis - VBIAS (ppm)
C014
Figure 35. Thermal Hysteresis Distribution (VBIAS
)
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8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF19xx have differing coefficients of thermal expansion, resulting
in stress on the device die when the device is heated. Mechanical and thermal stress on the device die can
cause the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is
a common cause of this error.
In order to illustrate this effect, a total of 92 devices were soldered on four printed circuit boards [23 devices on
each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow
profile. The reflow profile is as shown in Figure 36. The PCB is comprised of FR4 material. The board thickness
is 1.57 mm and the area is 171.54 mm × 165.1 mm.
300
250
200
150
100
50
0
0
50
100
150
200
250
300
350
400
Time (seconds)
C01
Figure 36. Reflow Profile
The reference and bias output voltages are measured before and after the reflow process; the typical shift is
displayed in Figure 37 and Figure 38. Although all tested units exhibit very low shifts (< 0.01%), higher shifts are
also possible depending on the size, thickness, and material of the PCB. An important note is that the histograms
display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on
PCBs with surface-mount components on both sides, causes additional shifts in the output bias voltage. If the
PCB is exposed to multiple reflows, solder the device in the second pass to minimize device exposure to thermal
stress.
60
50
40
30
20
10
0
50
40
30
20
10
0
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
Solder Heat Shift Histogram - VREF (%)
Solder Heat Shift Histogram - VBIAS (%)
C040
C041
Figure 38. Solder Heat Shift Distribution, VBIAS (%)
Figure 37. Solder Heat Shift Distribution, VREF (%)
12
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8.2 Thermal Hysteresis
Thermal hysteresis is measured with the REF19xx soldered to a PCB, similar to a real-world application. Thermal
hysteresis for the device is defined as the change in output voltage after operating the device at 25°C, cycling the
device through the specified temperature range, and returning to 25°C. Hysteresis can be expressed by
Equation 1:
≈
’
VPRE - VPOST
VHYST
=
ñ 106 (ppm)
∆
∆
÷
÷
VNOM
«
◊
where
•
•
•
•
VHYST = thermal hysteresis (in units of ppm),
VNOM = the specified output voltage,
VPRE = output voltage measured at 25°C pre-temperature cycling, and
VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature
range of –40°C to 125°C and returns to 25°C.
(1)
Typical thermal hysteresis distribution is as shown in Figure 39 and Figure 40.
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
Thermal Hysteresis - VBIAS (ppm)
Thermal Hysterisis - VREF (ppm)
C013
C014
Figure 39. Thermal Hysteresis Distribution (VREF
)
Figure 40. Thermal Hysteresis Distribution (VBIAS)
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8.3 Noise Performance
Typical 0.1-Hz to 10-Hz voltage noise is shown in Figure 41 and Figure 42. Device noise increases with output
voltage and operating temperature. Additional filtering can be used to improve output noise levels, although care
must be taken to ensure the output impedance does not degrade ac performance. Peak-to-peak noise
measurement setup is shown in Figure 43.
Time (1 s/div)
Time (1 s/div)
Figure 42. 0.1-Hz to 10-Hz Noise (VBIAS
10 kꢁ
C028
C029
Figure 41. 0.1-Hz to 10-Hz Noise (VREF
)
)
100 ꢁ
40 mF
VIN
To scope
VREF
+
10 ꢀF
EN
1 kꢁ
2-Pole High-pass
4-Pole Low-pass
REF19xx
0.1 ꢀF
0.1 Hz to 10 Hz Filter
GND
VBIAS
Figure 43. 0.1-Hz to 10-Hz Noise Measurement Setup
14
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9 Detailed Description
9.1 Overview
The REF19xx is a family of dual-output, VREF and VBIAS (VREF / 2) band-gap voltage references. The Functional
Block Diagram section provides a block diagram of the basic band-gap topology and the two buffers used to
derive the VREF and VBIAS outputs. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater
than that of Q2. The difference of the two base emitter voltages (VBE1 – VBE2) has a positive temperature
coefficient and is forced across resistor R5. The voltage is amplified and added to the base emitter voltage of Q2,
which has a negative temperature coefficient. The resulting band-gap output voltage is almost independent of
temperature. Two independent buffers are used to generate VREF and VBIAS from the band-gap voltage. The
resistors R1, R2 and R3, R4 are sized such that VBIAS = VREF / 2.
e-Trim™ is a method of package-level trim for the initial accuracy and temperature coefficient of VREF and VBIAS
,
implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the
influence of inherent transistor mismatch, as well as errors induced during package molding. e-Trim is
implemented in the REF19xx to minimize the temperature drift and maximize the initial accuracy of both the VREF
and VBIAS outputs.
9.2 Functional Block Diagram
R2
R1
R6
R7
R5
VREF
+
+
e-Trim
+
+
R4
VBE1 VBE2
-
-
R3
Q2
VBIAS
Q1
+
e-Trim
9.3 Feature Description
9.3.1 VREF and VBIAS Tracking
Most single-supply systems require an additional stable voltage in the middle of the analog-to-digital converter
(ADC) input range to bias input bipolar signals. The VREF and VBIAS outputs of the REF19xx are generated from
the same band-gap voltage as shown in the Functional Block Diagram section. Hence, both outputs track each
other over the full temperature range of –40°C to 125°C with an accuracy of 7 ppm/°C (max). The tracking
accuracy increases to 6 ppm/°C (max) when the temperature range is limited to –40°C to 85°C. The tracking
error is calculated using the box method, as described by Equation 2:
VDIFF(MAX) - VDIFF (MIN)
≈
∆
«
’
÷
◊
Tracking Error =
ñ106 (ppm)
VREF ñTemperature Range
where
VDIFF = VREF - 2• VBIAS
•
(2)
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Feature Description (continued)
The tracking accuracy is as shown in Figure 44.
0.05
0.04
0.03
0.02
0.01
0
VBIAS
-0.01
-0.02
-0.03
-0.04
VREF
-0.05
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
C001
Figure 44. VREF and VBIAS Tracking vs Temperature
9.3.2 Low Temperature Drift
The REF19xx is designed for minimal drift error, which is defined as the change in output voltage over
temperature. The drift is calculated using the box method, as described by Equation 3:
VREF(MAX)-VREF(MIN)
≈
∆
«
’
÷
◊
Drift =
ñ106 (ppm)
VREFñTemperature Range
(3)
9.3.3 Load Current
The REF19xx family is specified to deliver a current load of ±20 mA per output. Both the VREF and VBIAS outputs
of the device are protected from short circuits by limiting the output short-circuit current to 50 mA. The device
temperature increases according to Equation 4:
TJ = TA +P •RꢀJA
D
where
•
•
•
•
TJ = junction temperature (°C),
TA = ambient temperature (°C),
PD = power dissipated (W), and
RθJA = junction-to-ambient thermal resistance (°C/W).
(4)
The REF19xx maximum junction temperature must not exceed the absolute maximum rating of 150°C.
9.4 Device Functional Modes
When the EN pin of the REF19xx is pulled high, the device is in active mode. The device must be in active mode
for normal operation. The REF19xx can be placed in a low-power mode by pulling the ENABLE pin low. When in
shutdown mode, the output of the device becomes high impedance and the quiescent current of the device
reduces to 5 µA in shutdown mode. See the Electrical Characteristics for logic high and logic low voltage levels.
16
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The low-drift, bidirectional, single-supply, low-side, current-sensing solution described in this section can
accurately detect load currents from –2.5 A to 2.5 A. The linear range of the output is from 250 mV to 2.75 V.
Positive current is represented by output voltages from 1.5 V to 2.75 V, whereas negative current is represented
by output voltages from 250 mV to 1.5 V. The difference amplifier is the INA213 current-shunt monitor, whose
supply and reference voltages are supplied by the low-drift REF1930.
10.2 Typical Application
REF19xx
VREF
+
VIN
.andgap
EN
+
VBIAS
+
VCC
œ
GND
REF
V+
±ILOAD
VREF
ADC
+
IN+
+
OUT
VBUS
œ
w{IÜbÇ
VOUT
IN-
GND
INA213B
Figure 45. Low-Side, Current-Sensing Application
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Typical Application (continued)
10.2.1 Design Requirements
The design requirements are as follows:
1. Supply voltage: 5.0 V
2. Load current: ±2.5 A
3. Output: 250 mV to 2.75 V
4. Maximum shunt voltage: ±25 mV
10.2.2 Detailed Design Procedure
Low-side current sensing is desirable because the common-mode voltage is near ground. Therefore, the current-
sensing solution is independent of the bus voltage, VBUS. When sensing bidirectional currents, use a differential
amplifier with a reference pin. This procedure allows for the differentiation between positive and negative
currents by biasing the output stage such that it can respond to negative input voltages. There are a variety of
methods for supplying power (V+) and the reference voltage (VREF, or VBIAS) to the differential amplifier. For a
low-drift solution, use a monolithic reference that supplies both power and the reference voltage. Figure 46
shows the general circuit topology for a low-drift, low-side, bidirectional, current-sensing solution. This topology is
particularly useful when interfacing with an ADC; see Figure 45. Not only do VREF and VBIAS track over
temperature, but their matching is much better than alternate topologies. For a more detailed version of the
design procedure, refer to TIDU357.
REF19xx
VREF
+
VIN
.andgap
EN
+
VBIAS
+
VCC
œ
GND
REF
V+
±ILOAD
+
IN+
+
OUT
VBUS
œ
w{IÜbÇ
± VSHUNT
VOUT
IN-
GND
INA213B
Figure 46. Low-Drift, Low-side, Bidirectional, Current-Sensing Circuit Topology
The transfer function for the circuit given in Figure 46 is as shown in Equation 5:
VOUT = G • (êVSHUNT ) + VBIAS
= G • (êILOAD • RSHUNT) + VBIAS
(5)
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Typical Application (continued)
10.2.2.1 Shunt Resistor
As illustrated in Figure 46, the value of VSHUNT is the ground potential for the system load. If the value of VSHUNT
is too large, issues may arise when interfacing with systems whose ground potential is actually 0 V. Also, a value
of VSHUNT that is too negative may violate the input common-mode voltage of the differential amplifier in addition
to potential interfacing issues. Therefore, limiting the voltage across the shunt resistor is important. Equation 6
can be used to calculate the maximum value of RSHUNT
.
VSHUNT(max)
RSHUNT(max)
=
ILOAD(max)
(6)
Given that the maximum shunt voltage is ±25 mV and the load current range is ±2.5 A, the maximum shunt
resistance is calculated as shown in Equation 7.
VSHUNT (max)
25mV
2.5A
RSHUNT (max)
=
=
=10mW
ILOAD(max)
(7)
To minimize errors over temperature, select a low-drift shunt resistor. To minimize offset error, select a shunt
resistor with the lowest tolerance. For this design, the Y14870R01000B9W resistor is used.
10.2.2.2 Differential Amplifier
The differential amplifier used for this design must have the following features:
1. Single supply (3 V),
2. Reference voltage input,
3. Low initial input offset voltage (VOS),
4. Low-drift,
5. Fixed gain, and
6. Low-side sensing (input common-mode range below ground).
For this design, a current-shunt monitor (INA213) is used. The INA21x family topology is shown in Figure 47. The
INA213B specifications can be found in the INA213 product data sheet.
V+
IN-
-
OUT
IN+
+
REF
GND
Figure 47. INA21x Current-Shunt Monitor Topology
The INA213B is an excellent choice for this application because all the required features are included. In general,
instrumentation amplifiers (INAs) do not have the input common-mode swing to ground that is essential for this
application. In addition, INAs require external resistors to set their gain, which is not desirable for low-drift
applications. Difference amplifiers typically have larger input bias currents, which reduce solution accuracy at
small load currents. Difference amplifiers typically have a gain of 1 V/V. When the gain is adjustable, these
amplifiers use external resistors that are not conducive to low-drift applications.
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Typical Application (continued)
10.2.2.3 Voltage Reference
The voltage reference for this application must have the following features:
1. Dual output (3.0 V and 1.5 V),
2. Low drift, and
3. Low tracking errors between the two outputs.
For this design, the REF1930 is used. The REF19xx topology is as shown in the Functional Block Diagram
section.
The REF1930 is an excellent choice for this application because of its dual output. The temperature drift of
25 ppm/°C and initial accuracy of 0.1% make the errors resulting from the voltage reference minimal in this
application. In addition, there is minimal mismatch between the two outputs and both outputs track very well
across temperature, as shown in Figure 48 and Figure 49.
60
50
40
30
20
10
0
40
30
20
10
0
0
1
2
3
4
5
6
VREF and VBIAS Tracking Over Temperature (ppm/°C)
VREF and VBIAS Matching (ppm)
C016
C004
Figure 49. Distribution of VREF – 2 × VBIAS Drift Tracking
Over Temperature
Figure 48. VREF – 2 × VBIAS Distribution (At TA = 25°C)
10.2.2.4 Results
Table 1 summarizes the measured results.
Table 1. Measured Results
ERROR
UNCALIBRATED (%)
CALIBRATED (%)
±0.004
Error across the full load current range (25°C)
Error across the full load current range (–40°C to 125°C)
±0.0355
±0.0522
±0.0606
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10.2.3 Application Curves
Performing a two-point calibration at 25°C removes the errors associated with offset voltage, gain error, and so
forth. Figure 50 to Figure 52 show the measured error at different conditions. For a more detailed description on
measurement procedure, calibration, and calculations, please refer to TIDU357.
3
2.5
2
800
600
-40°C
0°C
400
200
1.5
1
0
25°C
85°C
œ200
œ400
œ600
œ800
0.5
0
125°C
-3
-2
-1
0
1
2
3
œ3
œ2
œ1
0
1
2
3
Load current (mA)
Load current (mA)
C00
C00
Figure 50. Measured Transfer Function
Figure 51. Uncalibrated Error vs Load Current
800
600
-40°C
0°C
400
200
0
25°C
85°C
œ200
œ400
œ600
œ800
125°C
œ3
œ2
œ1
0
1
2
3
Load current (mA)
C00
Figure 52. Calibrated Error vs Load Current
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11 Power-Supply Recommendations
The REF19xx family of references feature an extremely low-dropout voltage. These references can be operated
with a supply of only 20 mV above the output voltage. For loaded reference conditions, a typical dropout voltage
versus load is shown in Figure 53. A supply bypass capacitor ranging between 0.1 µF to 10 µF is recommended.
400
125°C
300
25°C
œ40°C
200
100
0
œ30
œ20
œ10
0
10
20
30
Load Current (mA)
C005
Figure 53. Dropout Voltage vs Load Current
22
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12 Layout
12.1 Layout Guidelines
Figure 54 shows an example of a PCB layout for a data acquisition system using the REF1930. Some key
considerations are:
•
•
•
•
Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF1930.
Decouple other active devices in the system per the device specifications.
Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
•
•
Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise
pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
V+
IN+
IN-
Via to
Input Power
C
GND
REF
C
OUT
REF
VREF
VBIAS
Via
to GND
Plane
Analog Input
C
C
Microcontroller
A/D Input
GND
EN
C
VIN
DIG1
AIN
Figure 54. Layout Example
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13 器件和文档支持
13.1 文档支持
13.1.1 相关文档ꢀ
相关文档请参见以下部分：
•
•
《INA21x 电压输出、低侧或高侧测量、双向、零漂移系列分流监控器》（文献编号：SBOS437）
《低漂移双向单电源低侧电流感测参考设计》（文献编号：TIDU357）
13.2 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，以及样片或购买的快速访
问。
表 2. 相关链接
部件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
请单击此处
REF1925
REF1930
REF1933
REF1941
13.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
13.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 商标
E2E is a trademark of Texas Instruments.
e-Trim is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
24
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14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014–2017, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
REF1925AIDDCR
REF1925AIDDCT
REF1930AIDDCR
REF1930AIDDCT
REF1933AIDDCR
REF1933AIDDCT
REF1941AIDDCR
REF1941AIDDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
5
5
5
5
5
5
5
5
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
GAGM
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
GAGM
GAHM
GAHM
GAIM
GAIM
GAJM
GAJM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
REF1925AIDDCR
REF1925AIDDCT
REF1930AIDDCR
REF1930AIDDCT
REF1933AIDDCR
REF1933AIDDCT
REF1941AIDDCR
REF1941AIDDCT
SOT-
23-THIN
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
5
5
5
5
5
5
5
5
3000
250
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
SOT-
23-THIN
SOT-
23-THIN
3000
250
SOT-
23-THIN
SOT-
23-THIN
3000
250
SOT-
23-THIN
SOT-
23-THIN
3000
250
SOT-
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
REF1925AIDDCR
REF1925AIDDCT
REF1930AIDDCR
REF1930AIDDCT
REF1933AIDDCR
REF1933AIDDCT
REF1941AIDDCR
REF1941AIDDCT
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
5
5
5
5
5
5
5
5
3000
250
213.0
213.0
213.0
213.0
213.0
213.0
213.0
213.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0005A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
5
1
NOTE 4
(0.15)
0.95
3.05
2.75
1.9
2
3
(0.2)
4
0.1
TYP
0.0
0.5
0.3
5X
0.2
C A B
0.25
GAGE PLANE
0.20
0.12
TYP
0 -8 TYP
C
SEATING PLANE
0.6
0.3
TYP
4220752/A 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0005A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
5X (1.1)
5X (0.6)
1
5
SYMM
2
3
4X (0.95)
4
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4220752/A 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0005A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
5X (1.1)
5X (0.6)
1
5
SYMM
2
3
4X(0.95)
4
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4220752/A 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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