REF200AU/2K5 [TI]
双路、100µA 拉/灌电流 | D | 8 | -25 to 85;
| 型号： | REF200AU/2K5 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、100µA 拉/灌电流 | D | 8 | -25 to 85 光电二极管 |
| 文件： | 总34页 (文件大小：1212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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REF200
SBVS020C –SEPTEMBER 2000–REVISED FEBRUARY 2020
REF200 Dual Current Source and Current Sink
1 Features
3 Description
The REF200 combines three circuit building-blocks
1
•
Completely floating: no power supply or ground
connections
on a single monolithic chip: two 100-µA current
sources and a current mirror. The sections are
dielectrically isolated, making them completely
independent. Also, because the current sources are
two-terminal devices, they can be used equally well
as current sinks. The performance of each section is
individually measured and laser-trimmed to achieve
high accuracy at low cost.
•
•
•
•
High accuracy: 100 µA ±0.5%
Low temperature coefficient: ±25 ppm/°C
Wide voltage compliance: 2.5 V to 40 V
Includes current mirror
2 Applications
The sections can be pin-strapped for currents of 50
µA, 100 µA, 200 µA, 300 µA, or 400 µA. External
circuitry can obtain virtually any current. These and
many other circuit techniques are shown in the
Application Information section of this data sheet.
•
•
•
•
•
•
Sensor excitation
Biasing circuitry
Offsetting current loops
Low voltage references
Charge-pump circuitry
Hybrid microcircuits
The REF200 is available in an SOIC package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
REF200
SOIC (8)
3.91 mm × 4.90 mm
(1) For all available packages, see the package addendum at the
end of the data sheet.
Functional Block Diagram
I1
I2
Mirror
In
High
High
Substrate
6
8
7
5
100µA
100µA
1
2
3
4
I1
Low
I2
Mirror
Mirror
Out
Low
Common
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
REF200
SBVS020C –SEPTEMBER 2000–REVISED FEBRUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Electrical Characteristics........................................... 4
6.5 Typical Characteristics.............................................. 5
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
7.4 Device Functional Modes.......................................... 8
8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
8.3 System Examples ................................................... 12
Power Supply Recommendations...................... 25
9
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1 Documentation Support ....................................... 26
11.2 Receiving Notification of Documentation Updates 26
11.3 Support Resources ............................................... 26
11.4 Trademarks........................................................... 26
11.5 Electrostatic Discharge Caution............................ 26
11.6 Glossary................................................................ 26
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2015) to Revision C
Page
•
Changed storage temperature................................................................................................................................................ 4
Changes from Revision A (August 2013) to Revision B
Page
•
Changed multiple instances of "mA" in data sheet back to "µA" (typo) ................................................................................. 1
Changes from Original (September 2000) to Revision A
Page
•
Added ESD Ratings and Recommended Operating Conditions tables, and Feature Description, Device Functional
Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation
Support, and Mechanical, Packaging, and Orderable Information sections........................................................................... 1
2
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SBVS020C –SEPTEMBER 2000–REVISED FEBRUARY 2020
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
I1 Low
1
2
3
4
8
7
6
5
I1 High
I2 Low
Mirror Common
Mirror Output
I2 High
Substrate
Mirror Input
Pin Functions
PIN
DESCRIPTION
NAME
NO.
1
I1 Low
Current source 1 low terminal
Current source 2 low terminal
Current mirror common terminal
Current mirror output terminal
Current mirror input terminal
I2 Low
2
Mirror Common
Mirror Output
Mirror Input
Substrate
I2 High
3
4
5
6
Substrate (Usually connected to most negative potential in the system)
Current source 2 high terminal
7
I1 High
8
Current source 1 high terminal
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Applied voltage
–6
Reverse current
–350
±80
85
µA
V
Voltage between any two sections
Operating temperature
–40
–55
°C
°C
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101(1)
±750
V
(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
NOM
MAX
40
UNIT
V
VCOMP
TA
Compliance voltage
Specified temperature range
–25
85
°C
6.4 Electrical Characteristics
at TA = 25°C, VS = 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SOURCES
Current accuracy
±0.25%
±0.25%
25
±1%
±1%
Current match
Temperature drift
Specified temperature range
2.5 V to 40 V
ppm/°C
20
100
Output impedance
MΩ
3.5 V to 30 V
200
500
BW = 0.1 Hz to 10 Hz
f = 10 kHz
1
nAp-p
Noise
20
pA/√Hz
Voltage compliance (1%)
Capacitance
TMIN to TMAX
See Typical Characteristics
10
pF
CURRENT MIRROR – I = 100 µA unless otherwise noted
Gain
0.995
40
1
25
1.005
Temperature drift
ppm/°C
Impedance (output)
Nonlinearity
2 V to 40 V
100
MΩ
I = 0 µA to 250 µA
0.05%
1.4
Input voltage
V
Output compliance voltage
Frequency response (–3 dB)
See Typical Characteristics
Transfer
5
MHz
4
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6.5 Typical Characteristics
at TA = 25°C, VS = 15 V (unless otherwise noted)
100.1
100
600
500
400
300
200
501
454
Distribution of three
99.9
99.8
production lots —
1284 Current Sources.
Drift specified by
85°C
“box method”
(See text)
99.7
117
86
99.6
99.5
100
0
66
30
15
6
5
2
0
1
1
–50
–25
0
25
50
75
100
125
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Temperature Drift (ppm/°C)
Temperature (°C)
Figure 1. Current Source Typical Drift vs Temperature
Figure 2. Current Source Temperature Drift Distribution
100.5
100.4
100.3
100.2
101
100.8
100.6
100.4
100.2
100
100.1
25°C
100
99.9
99.8
99.8
99.6
–55°C
99.7
99.4
99.6
99.2
99
125°C
99.5
0
1
2
3
4
5
0
5
10
15
20
25
30
35
40
Voltage (V)
Voltage (V)
Figure 4. Current Source Output Current vs Voltage
Figure 3. Current Source Output Current vs Voltage
1000
900
800
700
600
500
400
300
200
12kW
7V
Reverse Voltage
Circuit Model
5kW
Safe Reverse Current
Safe Reverse Voltage
100
0
–10
0
–2
–4
–6
–8
–12
Reverse Voltage (V)
Figure 6. Current Source Reverse Current vs Reverse
Voltage
Figure 5. Current Source Current Noise (0.1 Hz to 10 Hz)
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Typical Characteristics (continued)
at TA = 25°C, VS = 15 V (unless otherwise noted)
5
0.1
0.08
0.06
0.04
0.02
0
Data from Three
Representative Units
(Least-square fit)
4
VO
=
1.25V
3
2
VO = 1V
1
0
–1
–2
–3
–0.02
–0.04
–0.06
–0.08
–0.01
VO = 1.5V
–4
–5
0
50
100
150
200
250
10µA
100µA
Mirror Current (A)
1mA
Current (µA)
Figure 8. Mirror Transfer Nonlinearity
Figure 7. Mirror Gain Error vs Current
4
3
2
1
Input Voltage
Output
Compliance
Voltage
0
1mA
1µA
10µA
100µA
10mA
Current
Figure 9. Mirror Input Voltage and Output Compliance Voltage vs Current
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SBVS020C –SEPTEMBER 2000–REVISED FEBRUARY 2020
7 Detailed Description
7.1 Overview
The REF200 device combines three circuit building-blocks on a single monolithic chip—two 100-µA current
sources and a current mirror. The sections are dielectrically isolated, making them completely independent. Also,
because the current sources are two terminal devices, they can be used equally well as current sinks. The
performance of each section is individually measured and laser-trimmed to achieve high accuracy at low cost.
7.2 Functional Block Diagram
I1
I2
Mirror
In
High
High
Substrate
6
8
7
5
100µA
100µA
1
2
3
4
I1
Low
I2
Mirror
Mirror
Out
Low
Common
7.3 Feature Description
7.3.1 Temperature Drift
Drift performance is specified by the box method, as illustrated in Figure 1. The upper and lower current
extremes measured over temperature define the top and bottom of the box. The sides are determined by the
specified temperature range of the device. The drift of the unit is the slope of the diagonal, typically 25 ppm/°C
from –25°C to +85°C.
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7.4 Device Functional Modes
The three circuit sections of the REF200 are electrically isolated from one another, using a dielectrically-isolated
fabrication process. A substrate connection is provided (pin 6), which is isolated from all circuitry. This pin should
be connected to a defined circuit potential to assure rated DC performance. The preferred connection is to the
most negative constant potential in the system. In most analog systems, this would be –VS. For best ac
performance, leave pin 6 open and leave unused sections unconnected. Figure 10 shows the simplified circuit
diagram of the REF200.
8,7
5
4
5kΩ
1kΩ
1kΩ
3
Current
Mirror
(Substrate)
Current
8X
Source
(1 of 2)
4kΩ
12kΩ
6
1,2
Figure 10. Simplified Circuit Diagram
8
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SBVS020C –SEPTEMBER 2000–REVISED FEBRUARY 2020
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Applications for the REF200 are limitless. Application Bulletin AB-165 (SBOA046) shows additional REF200
circuits as well as other related current source techniques. In this section, a collection of circuits are shown to
illustrate some techniques.
If the current sources are subjected to reverse voltage, a protection diode may be required. A reverse voltage
circuit model of the REF200 is shown in Figure 6. If reverse voltage is limited to less than 6 V or reverse current
is limited to less than 350 µA, then no protection circuitry is required. A parallel diode (see (a) in Figure 17)
protects the device by limiting the reverse voltage across the current source to approximately 0.7 V. In some
applications, a series diode may be preferable (see (b) in Figure 17), because it allows no reverse current. This
configuration, however, reduces the compliance voltage range by one diode drop.
8.2 Typical Application
Figure 11 shows the schematic of a circuit that translates RTD resistance to a voltage level convenient for an
ADC input. The REF200 precision current reference provides excitation and an instrumentation amplifier scales
the signal. The design also uses a 3-wire RTD configuration to minimize errors due to wiring resistance.
+5V
REF200
100µA
100µA
+5V
3 Wire
RTD
INA326
+
R1
Vout
R2
œ
R3 78.7
Figure 11. RTD Resistance to Voltage Converter Schematic
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Typical Application (continued)
8.2.1 Design Requirements
The design requirements are as follows:
•
•
•
•
Supply Voltage: 5 V
RTD temperature range: –50°C to +125°C
RTD resistance range 80.3 Ω to 147.9 Ω
Output: 0.1 V to 4.9 V
The design goals and performance are summarized in Table 1. Figure 15 depicts the measured transfer function
of the design.
Table 1. Comparison of Design Goals, Calculations, Simulation, and Measured Performance
VOUT
RTD
GOAL
0.1 V
4.9 V
CALCULATED
0.112 V
SIMULATED
0.117 V
MEASURED
0.11 3 V
VOUT maximum scale
VOUT minimum scale
80.3 Ω
142.9 Ω
4.83 V
4.82 V
4.862 V
8.2.2 Detailed Design Procedure
Figure 12 and Figure 13 shows the schematic of the RTD amplifier for minimum and maximum output conditions.
This circuit was designed for a –50°C to 150°C RTD temperature range. At –50°C the RTD resistance is 80.3 Ω
and the voltage across it is 8.03 mV (VRTD = (100 μA) (80.3 Ω), see Figure 2). Notice that R3 develops a voltage
drop that opposes the RTD drop. The drop across R3 is used to shift amplifiers input differential voltage to a
minimum level. The output is the differential input multiplied by the gain (Vout = 698 ∙ 160 μV = 0.111 V). At
150°C, the RTD resistance is 148 Ω and the voltage across it is 14. 8 mV (VRTD = (100 μA × 148 Ω ). This
produces a differential input of 6.93 mV and an output voltage of 4.84 V (VOUT = 698 ∙ 6.93 mV = 4.84 V , see
Figure 13). For more detailed design procedures and results, refer to the reference guide, RTD to Voltage
Reference Design Using Instrumentation Amplifier and Current Reference (TIDU969).
+5V
REF200
100µA
100µA
+5V
3 Wire
RTD
INA326
+
R1
VOUT
0.111V
+
8.03mV
+
160µ V
80.3Ω @
-50C
R1
-
-
-
R3 78.7
- 7.87mV +
G = 2(R2/R1)
200µA
Figure 12. RTD Amplifier with Minimum Output Condition
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+5V
REF200
100µA
100µA
+5V
3 Wire
RTD
INA326
+
R1
VOUT
4.84V
+
6.93mV
+
148Ω @
150C
14.8mV
-
R1
-
-
R3 78.7
- 7.87mV +
G = 2(R2/R1)
200µA
Figure 13. RTD Amplifier with Maximum Output Condition
8.2.2.1 Lead Resistance Cancelation (3-Wire RTD)
Figure 14 shows the 3-wire RTD configuration can be used to cancel lead resistance. The resistance in each
lead must be equal to cancel the error. Also, the two current sources in the REF200 must be equal. Notice that
the voltage developed on the two top leads of the RTD are equal and opposite polarity so that the amplifiers
input is only from the RTD voltage. In this example, the RTD drop is 14.8 mV and the leads each have 1 mV.
Notice that the 1 mV drops cancel. Finally, notice that the voltage on the 3rd lead (2 mV) creates a small shift in
the common mode voltage. In some applications, a larger resistor is intentionally added to shift the common-
mode voltage. However, the INA326 has a rail-to-rail common mode range, so it can accept common-mode
voltages near ground.
+5V
REF200
100µA
100µA
Large Lead R
300m
+5V
INA326
10Ω
+
R1
VOUT
-1mV+
+
14.8mV
+
148Ω @
150C
14.8mV
-
4.84V
R1
-
-
R3 78.7
10Ω
3 Wire
RTD
- 1mV+
10Ω
+2mV-
PCB
Figure 14. 3-Wire RTD Configuration Cancels Lead Resistance
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8.2.3 Application Curves
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Error (0 Ω)
Error (10 Ω)
140
80
100
120
160
80
90
100
110
120
130
140
150
RTD Resistance (Ω)
RTD Resistance
C002
C001
Figure 16. Measured Error vs RTD Resistance
Figure 15. RTD to Vout Transfer Function
8.3 System Examples
NOTE: All diodes = 1N4148.
D1
D3
100µA
D1
Bidirectional
Bidirectional
Current Source
Current Source
100µA
D2
100µA
D
D2
4
(a)
(b)
(c)
(d)
Figure 17. Reverse Voltage Protection
+VS
100µA
IOUT
5
4
50µA
In
Out
Mirror
Com
3
100µA
–VS
Figure 18. 50-µA Current Source
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System Examples (continued)
300µA
400µA
200µA
100µA
100µA
100µA
100µA
5
4
100µA
100µA
In
Out
5
4
In
Out
Mirror
Mirror
Com
3
Com
3
Compliance = 4V
Compliance = 4V
(a)
(b)
(c)
Figure 19. 200-µA, 300-µA, and 400-µA Floating Current Sources
Compliance to
+VS
Ground
+VS
Compliance to
–VS + 5 V
Compliance to
–VS + 5.1 V
50 µA
100 µA
27 kΩ
50 µA
50 µA
5
4
In
Out
5
4
Mirror
In
Out
5
4
Com
3
Mirror
In
Out
Mirror
Com
3
0.01 µF
Com
3
100 µA
5.1 V
100 kΩ
100 µA
1N4689
100 µA
–VS
(a)
–VS
–VS
(b)
(c)
Figure 20. 50-µA Current Sinks
SERIES-CONNECTED CURRENT SOURCES
CURRENT vs APPLIED VOLTAGE
+VS
101
High
100µA
100µA
100µA
100µA
Low
100µA/200µA
100
5
4
In
Out
Mirror
Com
3
99
0
10
20
30
40
50
60
70
80
Applied Voltage (V)
–VS
Compliance to –VS + 1.5V
Provides 2X Higher Compliance Voltage
Figure 21. Improved Low-Voltage Compliance
Figure 22. 100-µA Current Source—80-V Compliance
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System Examples (continued)
+VS
+VS
100µA
100µA
0.01µF
33kΩ
L
o
a
d
L
o
a
d
100µA
+VS
5.1V
1N4689
100µA
–VS
(b) Compliance to +VS – 5V.
–VS
(a) Compliance approximate
to Gnd. HV compliance
limited by FET breakdown.
L
o
a
d
1N4148
1N4148
27kΩ
High
–VS
40kΩ
40kΩ
100µA
(c)
100µA
0.01µF
0.01µF
0.01µF
0.01µF
100µA
100µA
40kΩ
40kΩ
Low
1N4148
1N4148
(d) Floating 200µA cascoded
current source.
(e) Bidirectional 200µA
cascoded current source.
NOTES: (1) FET cascoded current sources offer improved output impedance and high frequency operation. Circuit in (b)
also provides improved PSRR. (2) For current sinks (Circuits (a) and (b) only), invert circuits and use “N” channel JFETS.
Figure 23. FET Cascode Circuits
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System Examples (continued)
Using Bourns Op Amp Trimpot®
Using Standard Potentiometer
+V
+VS
S
V
V
IN
IN
RA
RB
RA
RB
100µA
100µA
VOUT
VOUT
Op Amp
Op Amp
51Ω
51Ω
To (1)
To
Other
Amps
Other
Amps
(1)
2kΩ Linear
100Ω
®
Bourns Trimpot
100µA
100µA
V
= VIN (–RB /RA )
V
= –VIN(RB /RA)
OUT
OUT
Offset Adjustment Range = 5mV
Offset Adjustment Range = 5mV
–VS
–VS
NOTE: (1) For N Op Amps, use Potentiometer Resistance = N • 100Ω.
Figure 24. Operational Amplifier Offset Adjustment Circuits
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System Examples (continued)
R2
+VS
100 µA
NOTE: (1) OPA602 or OPA128
0.01 µF
EXAMPLES
(1)
R
R
I
OUT
1
2
IOUT = N • 100 µA
R1
Use OPA128
100 Ω 10 MΩ
1 nA
1 μA
1 mA
(N • R2 )
10 kΩ
10 kΩ
1 MΩ
1 kΩ
R1
(N • R2)
IOUT = N • 100 µA
(1)
R2
0.01 µF
100 µA
–VS
(a)
(b)
FEATURES:
(1) Zero volts shunt compliance.
(2) Adjustable only to values above
reference value.
NOTE:
IO = (N +1) 100 µA
Current source/sink swing to the
Load Return rail is limited only
by the op amp's input common
mode range and output swing
capability. Voltage drop across R
can be tailored for any amplifier to
allow swing to zero volts from rail.
+VS
100 µA
NR
R
0.01 µF
OPA602
EXAMPLES
R
NR
I
OUT
OPA602
1 kΩ
1 kΩ
4 kΩ 500 μA
9 kΩ 1 mA
100 kΩ 9.9 kΩ 10 mA
NR
R
0.01 µF
100 µA
IO = (N +1) 100 µA
Reference
–VS
(c)
(d)
IO = (N +1) 100 µA
100 µA
OPA602
10 pF
IO = 100 μA (N + 1). Compliance » 3.5 V
with 0.1 V across R. Max I limited by FET.
O
For IO = 1 A, R = 0.1 Ω, NR = 1 kΩ.
NR
R
0.01 µF
(e)
Figure 25. Adjustable Current Sources
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SBVS020C –SEPTEMBER 2000–REVISED FEBRUARY 2020
System Examples (continued)
INA110
Instrumentation Amplifier
ROFFSET
Cable Shield
RTD
VOUT = Gain • 200 µA • Δ RTD
200-µA
Reference
Current
200-µA
Compensation
Current
+VS
8
6
5
7
I
O
A
B
C
REF200
1
2
3
4
–VS
Figure 26. RTD Excitation With Three-Wire Lead Resistance Compensation
2 Vp-p
2 Vp-p
Triangle Output
C
OPA602
Square Output
R
10 kΩ
Frequency = 1/4RC (Hz)
Frequency = 25/C (Hz)
(C is in µF and R = 10 kΩ)
1N4148
1N4148
Bidirectional
Current Source
1/2
REF200
1N4148
1N4148
Figure 27. Precision Triangle Waveform Generator
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System Examples (continued)
100 kΩ
VIN
¦10 V ≤ VIN ≤ 10 V
100 µA + Bridge(1)
C
1/4
OPA404
1/4
OPA404
1/4
OPA404
12 Vp-p
(1)
100 µA + Bridge
Duty Cycle Out
VIN
VIN
=
=
10 V: 100% Duty Cycle
0 V: 50% Duty Cycle
60 kꢀ
VIN = œ10 V: 0% Duty Cycle
(1) See Figure 27.
Figure 28. Precision Duty-Cycle Modulator
For current source,
IOUT
invert circuitry and
use P-Channel FET.
Siliconix
J109
0.1 µF
50kΩ
100 µA
–15 V
Figure 29. Low Noise Current Sink
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SBVS020C –SEPTEMBER 2000–REVISED FEBRUARY 2020
System Examples (continued)
IOUT
For current source,
50 kΩ
invert circuitry and
0.1 µF
use P-Channel FET.
Siliconix
J109
0.1 µF
50 kΩ
100 µA
100 µA
–15 V
Figure 30. Low Noise Current Sink With Compliance Below Ground
High
High
300 µA
400 µA
0.01 µF
0.01 µF
20 kΩ
20 kΩ
100 µA
100 µA
100 µA
2N5116
2N5116
2N4340
2N4340
0.01 µF
27 kΩ
5
4
5
4
100 µA
In
Out
In
Out
Mirror
Com
3
Mirror
Com
3
300 µA
Low
400 µA
Low
(a) Regulation (15 V to 30 V = 0.00003%/V (10 GW)
(a) Regulation (15 V to 30 V = 0.000025%/V (10 GW)
Figure 31. Floating 300-µA and 400-µA Cascoded Current Sources
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System Examples (continued)
+V
S
100 µA
10 kΩ
C
10 kΩ
V
I
VO = –VI
OPA602
Diodes: 1N4148
or PWS740-3
VO Rate Limit = 100 µA/C
Diode Bridge for
reduced VOS
.
100 µA
–V
S
Figure 32. Rate Limiter
High
Compliance
4 V to 30 V
25 mA
100 Ω
100 μA
100 Ω
+VS
–VS
100 Ω
100 Ω
10 kΩ
40.2 Ω
NOTE: Each amplifier 1/4 LM324
Op amp power supplies are derived
within the circuitry, and this quiescent
current is included in the 25 mA.
Low
Figure 33. 25-mA Floating Current Source
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System Examples (continued)
+15 V
VO
100 µA
+10
R
R
(50 kΩ)
(50 kΩ)
VI
+5
1N4148
–10
–5
+5
+10
VI
10 pF
–5
1N4148
For VI > –5 V: VO = 0
For VI < –5 V: VO= –V – 5 V
VO
OPA602
I
–10
(Dead to 100 µA • R)
R
R
VO
(50 kΩ)
(50 kΩ)
+10
+5
VI
1N4148
–10
–5
+5
+10
VI
100 µA
10 pF
1N4148
–15 V
VO
OPA602
–5
For VI < 5 V: VO = 0
For VI > 5 V: VO = 5 V – V
I
(Dead to –100 µA • R)
–10
Figure 34. Dead-Band Circuit
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System Examples (continued)
+15 V
VO
+10
+5
100 µA
R
R
(50 kΩ)
(50 kΩ)
–10
–5
+5
+10
1N4148
VI
–5
10 pF
For VI > 5 V: VO = V – 5 V
For VI < –5 V: VO= V + 5 V
I
10 kΩ
10 kΩ
1N4148
I
OPA602
–10
(Dead to 100 µA • R)
10 kΩ
VI
VO
OPA602
R
R
(50 kΩ)
(50 kΩ)
1N4148
100 µA
10 pF
1N4148
–15 V
OPA602
Figure 35. Double Dead-Band Circuit
+VS
100 µA
VO = 100 µV
1 Ω
Figure 36. Low-Voltage Reference
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SBVS020C –SEPTEMBER 2000–REVISED FEBRUARY 2020
System Examples (continued)
+VS
100 µA
OPA602
VO = 1 V
0.01 µF
10 kΩ
Figure 37. Voltage Reference
VO
+10
+5
+7.5 V (R = 75 kΩ)
+5 V (R = 50 kΩ)
+2.5 V (R = 25 kΩ)
1 kΩ
100 µF
VO
OPA121
–10
–5
+5
+10
VI
OPA121
VI
100 µA
with bridge(1)
–2.5 V (R = 25 kΩ)
+5 V (R = 50 kΩ)
+7.5 V (R = 75 kΩ)
R
–5
(50 kΩ)
VO = VI (–5 V < VI < 5 V)
VO = 5 V (VI > 5 V)
VO = –5 V (V < –5 V)
I
–10
(Bound = 100 µA • R)
(1) See Figure 17.
Figure 38. Bipolar Limiting Circuit
VO
1 kΩ
+10
+5
+7.5 V (R = 75 kΩ)
+5 V (R = 50 kΩ)
+2.5 V (R = 25 kΩ)
100 µF
VO
OPA121
1N4148
–10
–5
+5
+10
VI
OPA121
VI
–5
R
100 µA
VO = VI (VI < 5 V)
VO = 5 V (VI > 5 V)
(VLIMIT = 100 µA • R)
(50 kΩ)
–10
Figure 39. Limiting Circuit
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System Examples (continued)
+VS
+5V
100µA
VO
1kΩ
The
Window
5V
1/2
LM393
0
V
I
–VW
+VW
(2)
VCENTER
R(3)
0.01µF(1)
0.01µF(1)
–VW , +VW = 100µA • R
(2)
VCENTER
VO
R(3)
1/2
LM393
VI
100µA
NOTES: (1) Capacitors optional to reduce noise and switching time.
(2) Programs center of threshold voltage. (3) Programs window voltage.
–VS
Figure 40. Window Comparator
+VS
100µA
100µA
1/2
OPA1013
1/2
OPA1013
PMI
+In
–In
MAT03
–VS
INA105
VO = +In – (–In)
Figure 41. Instrumentation Amplifier With Compliance to –VS
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SBVS020C –SEPTEMBER 2000–REVISED FEBRUARY 2020
9 Power Supply Recommendations
The REF200 device has completely floating current sources and current mirror. The REF200 device has a wide
compliance voltage range from 2.5 V to 40 V.
10 Layout
10.1 Layout Guidelines
Figure 42 illustrates an example of a printed-circuit-board (PCB) layout for a data acquisition system using the
REF2030. Some key considerations are:
•
•
•
Minimize trace lengths in the current source and current mirror paths to reduce impedance.
Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
•
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
10.2 Layout Example
VSUPPLY
GND
C
REF200
To RTD
R
R
To INA
R
Figure 42. Example Layout of REF200 in a RTD Measurement System
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
•
•
RTD to Voltage Reference Design Using Instrumentation Amplifier and Current Reference, TIDU969
Implementation and Applications of Current Sources and Current Receivers, SBOA046
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
REF200AU
REF200AU/2K5
REF200AU/2K5E4
REF200AUE4
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
75
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-25 to 85
-25 to 85
-25 to 85
-25 to 85
REF
200U
ACTIVE
ACTIVE
ACTIVE
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
REF
200U
REF
200U
75
RoHS & Green
REF
200U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
REF200AU/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
REF200AU/2K5
D
8
2500
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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