REF3433SQDBVRQ1 [TI]

REF34-Q1 Low-Drift, Low-Power, Small-Footprint Series Voltage References;


型号：	REF3433SQDBVRQ1
厂家：	TEXAS INSTRUMENTS
描述：	REF34-Q1 Low-Drift, Low-Power, Small-Footprint Series Voltage References
文件：	总38页 (文件大小：4818K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

REF34-Q1

_{SBAS901C – JULY 2018 – REVISED OC}R_TOE_BF_E3_R4₂-Q₀₂1₀

SBAS901C – JULY 2018 – REVISED OCTOBER 2020

www.ti.com

REF34-Q1 Low-Drift, Low-Power, Small-Footprint Series

Voltage References

1 Features

3 Description

•

AEC-Q100 qualified with the following results:

– Device temperature grade 1: –40°C to +125°C

ambient operating temperature

– Device HBM ESD classification level 2

– Device CDM ESD classification level C6

Initial accuracy: ±0.05% (maximum)

Temperature coefficient : 6 ppm/°C (maximum)

Operating temperature range: −40°C to +125°C

Output voltage options: 2.5V, 3.0V, 3.3V, 4.096V,

5.0V

The REF34-Q1 devices are low-temperature-drift

(6 ppm/°C), low-power, high-precision CMOS voltage

references. The devices have ±0.05% initial accuracy

and low operating current with power consumption

less than 95 μA. These devices also offer very low

output noise of 3.8 µV_PP/V, which enable the devices

to maintain high signal integrity with high-resolution

data converters and noise critical systems.

•

Stability and system reliability are further improved by

the low output-voltage hysteresis of these devices and

low long-term output voltage drift. Furthermore, the

small size and low operating current of the devices

(95 μA) make them an excellent choise for battery-

powered applications. The REF34-Q1 features an

enable pin that can set the device into shutdown

where it consumes a low stand by current (3 μA) to

help with overall system power during standby.

•

Output current: ±10 mA

Low quiescent current: 95 μA (maximum)

Low shutdown mode current: 3 μA (maximum)

Wide input voltage: 12 V

Output 1/f noise (0.1 Hz to 10 Hz): 3.8 µV_PP/V

Excellent long-term stability 25 ppm/1000 hrs

Available in 6-pin and 5-Pin SOT-23 package and

8-pin MSOP package

The REF34-Q1 family is specified for the wide

temperature range of −40°C to +125°C. Contact the

TI sales representative for additional voltage options.

2 Applications

Device Information ⁽¹⁾

•

Body control modules

On board chargers

Traction inverters

Battery management systems

Advanced driver assistance systems

PART NUMBER

PACKAGE

BODY SIZE (NOM)

2.90 mm × 1.60 mm

4.00 mm × 4.00 mm

REF34xx-Q1

SOT-23 (6)

REF34xxS-Q1

REF34xx-Q1

SOT-23 (5)

VSSOP (8)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

3V VDD

0.4

0.36

+125°C

VDD

2.5V VREF

AIN0

0.32

VREF+

OUT

GND

AIN1

AIN2

AIN3

0.28

VREF-

+25°C

0.24

REF3425-Q1

ADS7828-Q1

0.2

-40°C

0.16

3.3V VDD

0.12

0.08

0.04

I2C

VDD

GPIO0

GPIOx

I2C

TDA2 (MCU)

-10

-5

Load Current (mA)

drop

Dropout vs Current Load Over Temperature

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

6.1 Pin Functions ............................................................. 3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings ....................................... 4

7.2 ESD Ratings .............................................................. 4

7.3 Recommended Operating Conditions ........................4

7.4 Thermal Information ...................................................4

7.5 Electrical Characteristics ............................................5

8 Typical Characteristics................................................... 7

9 Parameter Measurement Information..........................12

9.1 Solder Heat Shift.......................................................12

9.2 Long-Term Stability................................................... 13

9.3 Thermal Hysteresis...................................................13

9.4 Power Dissipation..................................................... 14

9.5 Noise Performance................................................... 15

10 Detailed Description....................................................16

10.1 Overview.................................................................16

10.2 Functional Block Diagram.......................................16

10.3 Feature Description.................................................16

10.4 Device Functional Modes........................................17

11 Application and Implementation................................ 18

11.1 Application Information............................................18

11.2 Typical Applications.................................................18

12 Power Supply Recommendations..............................23

13 Layout...........................................................................23

13.1 Layout Guidelines................................................... 23

13.2 Layout Example...................................................... 23

14 Device and Documentation Support..........................25

14.1 Documentation Support.......................................... 25

14.2 Receiving Notification of Documentation Updates..25

14.3 Support Resources................................................. 25

14.4 Trademarks.............................................................25

14.5 Electrostatic Discharge Caution..............................25

14.6 Glossary..................................................................25

15 Mechanical, Packaging, and Orderable

Information.................................................................... 25

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (August 2020) to Revision C (October 2020)

Page

•

Added information for REF34-Q1 DGK Package............................................................................................... 3

Added information for REF34xx-Q1 DGK package pin functions.......................................................................3

Changes from Revision A (September 2018) to Revision B (August 2020)

Page

Added information for REF34xxS-Q1................................................................................................................. 3

•

Changes from Revision * (July 2018) to Revision A (September 2018)

Page

•

Changed Advance Information to Production Data............................................................................................ 1

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5 Device Comparison Table

PRODUCT⁽¹⁾

V_OUT

2.5 V

REF3425-Q1

REF3430-Q1

REF3433-Q1

REF3440-Q1

REF3450-Q1

REF3425S-Q1

REF3430S-Q1

REF3433S-Q1

REF3440S-Q1

REF3450S-Q1

3.0 V

3.3 V

4.096 V

5.0 V

(1) For full orderable part number please refer to Section 15.

6 Pin Configuration and Functions

OUT_F

OUT_S

NIC

GND_F

GND_S

GND

OUT

Not to scale

Figure 6-1. DBV Package 6-Pin SOT-23 (Top View) Figure 6-2. DBV Package 5-Pin SOT-23 (Top View)

ENABLE

GND_S

GND_F

OUT_S

OUT_F

NIC

Not to scale

Figure 6-3. DGK Package 8-Pin VSSOP (Top View)

6.1 Pin Functions

REF34xxS-Q1

(DBV)

TYPE

DESCRIPTION

REF34xx-Q1

REF34xx-

Q1 (DGK)

NAME

(DBV)

GND_F

GND_S

GND

Ground Ground force connection

Ground Ground sense connection

Ground Ground connection

ENABLE

Input

Power

Output

Enable connection. Enables or disables the device.

Input supply voltage connection

OUT_S

OUT_F

OUT

Reference voltage output sense connection

Reference voltage output force connection

Reference voltage output connection

Test pin, connect from 0V to 18V

No internal connection

NIC

4,5

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

Input voltage

V_OUT

IN + 0.3

5.5

Output voltage

Output short circuit current

Operating temperature range, T_A

Storage temperature range, T_stg

°C

–55

–65

150

170

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied. These are stress ratings only and functional operation of the device at these or any other conditions

beyond those specified in the Electrical Characteristics Table is not implied.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

±2500

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per AEC

Q100-011

±1500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_OUT+ V

Input Voltage

(1)

I_L

Enable Voltage

–10

–40

Output Current

°C

T_A

Operating Temperature

125

(1) V_DO= Dropout voltage

7.4 Thermal Information

REF34-Q1

THERMAL METRIC⁽¹⁾

DBV

5 PINS

122.6

80.2

DBV

6 PINS

122.6

80.2

DGK

UNIT

8 PINS

174.1

61.3

95.5

8.5

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

23.2

41.9

N/A

23.2

41.9

N/A

Ψ_JB

93.9

N/A

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics

At V_IN= V_OUT+ V_DO, C_OUT= 10 µF, C_IN= 0.1 µF, I_L= 0 mA, minimum and maximum specifications at T_A= –40℃ to 125℃;

Typical specifications at T_A= 25℃ unless otherwise noted

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

ACCURACY AND DRIFT

Output voltage accuracy T_A= 25℃

–0.05

0.05

Output voltage

temperature coefficient

2.5

ppm/℃

(1)

LINE & LOAD REGULATION

ΔV_O/ΔV_INLine Regulation

V_IN= V_OUT+ V_DO⁽²⁾to 12 V

ppm/V

Sourcing

I_L= 0 mA to 10mA, V_IN

(3)

= V_OUT+ V_DO

Sourcing

Sinking, REF3425-Q1

Sinking, REF3430-Q1

Sinking, REF3433-Q1

Sinking, REF3440-Q1

Sinking, REF3450-Q1

Sinking, REF3425-Q1

Sinking, REF3430-Q1

Sinking, REF3433-Q1

Sinking, REF3440-Q1

Sinking, REF3450-Q1

ΔV_O/ΔI_L

Load Regulation

ppm/mA

I_L= 0 mA to –10mA, V_IN

= V_OUT+ V_DO

(3)

140

NOISE

0.1Hz ≤ f ≤ 10Hz

e_np-p

Low frequency noise ⁽⁴⁾

µV p–p/V

0.1Hz ≤ f ≤ 10Hz (REF3440–Q1 and REF3450–

Q1)

3.8

Integrated wide band

noise

e_n

10Hz ≤ f ≤ 10kHz

µVrms

f = 1kHz

0.25

0.2

Output voltage noise

density

ppm/√Hz

f = 1kHz (REF3440–Q1 and REF3450–Q1)

LONG TERM STABILITY AND HYSTERESIS

0 to 1000h at 35℃

1000h to 2000h at 35℃

0 to 1000h at 35℃

Long-term stability ⁽⁵⁾

DBV Package

ppm

DGK Package

DBV Package

25°C, –40°C,125°C,

25°C Cycle 1

25°C, –40°C,125°C,

25°C Cycle 2

Output voltage thermal

hysteresis ⁽⁶⁾

25°C, –40°C,125°C,

25°C Cycle 1

DGK Package

25°C, –40°C,125°C,

25°C Cycle 2

TURN-ON TIME

t_ONTurn-on time

0.1% of output voltage settling, C_L= 10 µF,

REF3425–Q1

2.5

µF

CAPACITIVE LOAD

Stable output capacitor

range

C_L

0.1

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At V_IN= V_OUT+ V_DO, C_OUT= 10 µF, C_IN= 0.1 µF, I_L= 0 mA, minimum and maximum specifications at T_A= –40℃ to 125℃;

Typical specifications at T_A= 25℃ unless otherwise noted

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

OUTPUT VOLTAGE

REF3425Q1

REF3430Q1

REF3433Q1

REF3440Q1

REF3450Q1

2.5

3.0

V_OUT

Output voltage

3.3

4.096

5.0

POWER SUPPLY

V_OUT+ V

V_IN

I_L

Input voltage

Output current capacity V_IN= V_OUT+ V_DOto 12 V

–10

Active mode

Quiescent current

2.5

I_Q

µA

Shutdown mode ⁽⁷⁾

I_L= 0 mA

V_DO

Dropout voltage

I_L= 0 mA

100

500

I_L= 10 mA

Voltage reference in active mode (EN = 1)

Voltage reference in shutdown mode (EN = 0)

1.6

V_EN

ENABLE pin voltage ⁽⁷⁾

0.5

ENABLE pin leakage

current ⁽⁷⁾

I_EN

I_SC

V_EN= V_IN= 12V

µA

Short circuit current

V_OUT= 0 V at T_A= 25°C

(1) Temperature drift is specified according to the box method. See Low Temperature Drift section for more details.

(2) V_DOfor line regulation test is 50 mV.

(3) V_DOfor load regulation test is 500 mV.

(4) The peak-to-peak noise measurement is explained in more detail in section Noise Performance.

(5) Long-term stability measurement procedure is explained in more detail in section Long–Term Stability.

(6) Thermal hysteresis measurement procedure is explained in more detail in section Thermal Hysteresis.

(7) Not applicable for REF34S device (DBV - 5 pin package)

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8 Typical Characteristics

at T_A= 25°C, V_IN= V_EN= 12 V, I_L= 0 mA, C_L= 10 µF, C_IN= 0.1 µF (unless otherwise noted)

12V

3.3V

-40

-15

35 60

Temperature (°C)

110 125

Vinv

D001

Drift (ppm/°C)

Figure 8-2. V_INvs I_QOver Temperature

(-40°C to 125°C)

Figure 8-1. Temperature Drift

0.02

0.015

0.01

74.5

73.5

0.005

-0.005

-0.01

-0.015

-0.02

72.5

71.5

-50

-25

25 50

Temperature (°C)

100

125

-50

-25

25 50

Temperature (°C)

100

125

D002

D004

Figure 8-3. Output Voltage Accuracy vs Temperature

Figure 8-4. Quiescent Current vs Temperature

-20

0.24

0.23

0.22

0.21

0.2

C_L= 1uF

C_L= 10uF

-40

-60

0.19

0.18

0.17

0.16

0.15

0.14

0.13

-80

-100

-120

100

Frequency (Hz)

10k

100k

-40

-20

40 60

Temperature (°C)

100 120 140

D005

D019

Figure 8-5. Power-Supply Rejection Ratio vs Frequency

Figure 8-6. Line Regulation

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8 Typical Characteristics (continued)

at T_A= 25°C, V_IN= V_EN= 12 V, I_L= 0 mA, C_L= 10 µF, C_IN= 0.1 µF (unless otherwise noted)

8.7

8.4

8.1

7.8

7.5

7.2

6.9

6.6

6.3

52.5

47.5

42.5

37.5

32.5

5.7

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

D021

D020

Figure 8-8. Load Regulation Sinking

Figure 8-7. Load Regulation Sourcing

800

720

640

560

480

400

320

240

160

I_LOAD

+1mA

-1mA

1mA/div

4mV/div

V_OUT

250µs/div

100

Frequency(Hz)

10k

100k

(C_L= 1µF, I_OUT= 1mA)

D010

D009

Figure 8-10. Load Transient

Figure 8-9. Noise Performance 10 Hz to 10 kHz

I_LOAD

+1mA

+10mA

+1mA

10mA/div

-10mA

-1mA

1mA/div

4mV/div

V_OUT

100mV/div

250µs/div

(C_L= 1µF, I_OUT= 10mA)

D010

(C_L= 10µF, I_OUT= 1mA)

D010

Figure 8-12. Load Transient

Figure 8-11. Load Transient

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8 Typical Characteristics (continued)

at T_A= 25°C, V_IN= V_EN= 12 V, I_L= 0 mA, C_L= 10 µF, C_IN= 0.1 µF (unless otherwise noted)

I_LOAD

-10mA

+10mA

10mA/div

20mV/div

V_IN

4V/div

+10mA

V_OUT

15mV/div

250µs/div

(C_L= 10µF, I_OUT= 10mA)

250µs/div

(C_L= 1µF)

D010

D011

Figure 8-13. Load Transient

Figure 8-14. Line Transient

2.6

2.5

2.4

2.3

2.2

2.1

V_IN

4V/div

V_OUT

5mV/div

250µs/div

-40

-15

35 60

Temperature (°C)

110 125

D011

(C_L= 10µF)

D013

Figure 8-15. Line Transient

Figure 8-16. Quiescent Current Shutdown Mode

30%

25%

20%

15%

10%

30%

25%

20%

15%

10%

D016

Thermal Hysteresis - Cycle 1 (ppm)

Thermal Hysteresis - Cycle 2 (ppm)

Figure 8-17. Thermal Hysteresis Distribution (Cycle 1) - DBV

Package

Figure 8-18. Thermal Hysteresis Distribution (Cycle 2) - DBV

Package

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8 Typical Characteristics (continued)

at T_A= 25°C, V_IN= V_EN= 12 V, I_L= 0 mA, C_L= 10 µF, C_IN= 0.1 µF (unless otherwise noted)

30%

25%

20%

15%

10%

30%

25%

20%

15%

10%

DGKt

Thermal Hysteresis - Cycle 2 (ppm)

Thermal Hysteresis - Cycle 1 (ppm)

Figure 8-20. Thermal Hysteresis Distribution (Cycle 2) - DGK

Package

Figure 8-19. Thermal Hysteresis Distribution (Cycle 1) - DGK

Package

50%

40%

30%

20%

10%

50%

40%

30%

20%

10%

D017

DGKs

Solder Heat Shift (%)

Refer to Section 9.1 for more information

Figure 8-21. Solder Heat Shift Distribution - DBV Package

Figure 8-22. Solder Heat Shift Distribution - DGK Package

1V/div

V_OUT

Time 1s/div

0.5ms/div

D08_

D018

Figure 8-24. 0.1-Hz to 10-Hz Noise (V_REF

)

Figure 8-23. Turnon Time (Enable)

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8 Typical Characteristics (continued)

at T_A= 25°C, V_IN= V_EN= 12 V, I_L= 0 mA, C_L= 10 µF, C_IN= 0.1 µF (unless otherwise noted)

-5

-10

-15

-20

-25

-30

-35

-40

-10

-15

-20

-25

-30

-35

-40

100 200 300 400 500 600 700 800 900 1000

Hours

DGKl

D022

Figure 8-26. Long Term Stability - 1000 hours (V_REF) - DGK

Package

Figure 8-25. Long Term Stability - 1000 hours (V_REF) - DBV

Package

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9 Parameter Measurement Information

9.1 Solder Heat Shift

The materials used in the manufacture of the REF34-Q1 have differing coefficients of thermal expansion,

resulting in stress on the device die when the part is heated. Mechanical and thermal stress on the device die

can cause the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow

soldering is a common cause of this error.

In order to illustrate this effect, a total of 32 devices were soldered on four printed circuit boards [16 devices on

each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow

profile. The reflow profile is as shown in Figure 9-1. The printed circuit board is comprised of FR4 material. The

board thickness is 1.65 mm and the area is 114 mm × 152 mm. All measurements were taken after baking at

150°C.

300

250

200

150

100

150

200

250

300

350

400

Time (seconds)

C01

Figure 9-1. Reflow Profile

The reference output voltage is measured before and after the reflow process; the typical shift is displayed in

Figure 9-2. Although all tested units exhibit very low shifts (< 0.01%), higher shifts are also possible depending

on the size, thickness, and material of the printed circuit board. An important note is that the histograms display

the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is common on PCBs with

surface-mount components on both sides, causes additional shifts in the output bias voltage. If the PCB is

exposed to multiple reflows, the device must be soldered in the second pass to minimize its exposure to thermal

stress.

50%

40%

30%

20%

10%

50%

40%

30%

20%

10%

D017

DGKs

Solder Heat Shift (%)

Figure 9-2. Solder Heat Shift Distribution, V_REF(%)

- DBV Package

Figure 9-3. Solder Heat Shift Distribution, V_REF(%)

- DGK Package

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9.2 Long-Term Stability

One of the key parameters of the REF34-Q1 references is long-term stability. Typical characteristic expressed

as: curves shows the typical drift value for the REF34-Q1 is 25 ppm from 0 to 1000 hours. This parameter is

characterized by measuring 32 units at regular intervals for a period of 1000 hours. It is important to understand

that long-term stability is not ensured by design and that the output from the device may shift beyond the typical

25 ppm specification at any time. For systems that require highly stable output voltages over long periods of

time, the designer should consider burning in the devices prior to use to minimize the amount of output drift

exhibited by the reference over time

-5

-10

-15

-20

-25

-30

-35

-40

-10

-15

-20

-25

-30

-35

-40

100 200 300 400 500 600 700 800 900 1000

Hours

DGKl

D022

Figure 9-5. Long Term Stability - 1000 hours (V_REF

- DGK Package

)

Figure 9-4. Long Term Stability - 1000 hours (V_REF

- DBV Package

)

9.3 Thermal Hysteresis

Thermal hysteresis is measured with the REF34-Q1 soldered to a PCB, similar to a real-world application.

Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C,

cycling the device through the specified temperature range, and returning to 25°C. Hysteresis can be expressed

by Equation 1:

≈

∆

’

◊

| V_PRE- V_POST

V_NOM

V_HYST

ì10⁶ppm

(

)

(1)

where

•

V_HYST= thermal hysteresis (in units of ppm)

V_NOM= the specified output voltage

V_PRE= output voltage measured at 25°C pre-temperature cycling

V_POST= output voltage measured after the device has cycled from 25°C through the specified temperature

range of –40°C to +125°C and returns to 25°C.

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Typical thermal hysteresis distribution is as shown in Figure 9-6.

30%

25%

20%

15%

10%

30%

25%

20%

15%

10%

D016

Thermal Hysteresis - Cycle 1 (ppm)

Thermal Hysteresis - Cycle 2 (ppm)

Figure 9-6. Thermal Hysteresis Distribution (V_REF) - Figure 9-7. Thermal Hysteresis Distribution (V_REF) -

DBV Package (Cycle 1)

DBV Package (Cycle 2)

30%

25%

20%

15%

10%

30%

25%

20%

15%

10%

DGKt

Thermal Hysteresis - Cycle 2 (ppm)

Thermal Hysteresis - Cycle 1 (ppm)

Figure 9-9. Thermal Hysteresis Distribution (V_REF) -

DGK Package (Cycle 2)

Figure 9-8. Thermal Hysteresis Distribution (V_REF) -

DGK Package (Cycle 1)

9.4 Power Dissipation

The REF34-Q1 voltage references are capable of source and sink up to 10 mA of load current across the rated

input voltage range. However, when used in applications subject to high ambient temperatures, the input voltage

and load current must be carefully monitored to ensure that the device does not exceeded its maximum power

dissipation rating. The maximum power dissipation of the device can be calculated with Equation 2:

T_J= T_A+P ì R_qJA

(2)

where

•

P_Dis the device power dissipation

T_Jis the device junction temperature

T_Ais the ambient temperature

R_θJAis the package (junction-to-air) thermal resistance

Because of this relationship, acceptable load current in high temperature conditions may be less than the

maximum current-sourcing capability of the device. In no case should the device be operated outside of its

maximum power rating because doing so can result in premature failure or permanent damage to the device.

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9.5 Noise Performance

Typical 0.1-Hz to 10-Hz voltage noise can be seen in Figure 9-10 . Device noise increases with output voltage

and operating temperature. Additional filtering can be used to improve output noise levels, although care must

be taken to ensure the output impedance does not degrade ac performance. Peak-to-peak noise measurement

setup is shown in Figure 9-10.

Time 1s/div

D08_

Figure 9-10. 0.1-Hz to 10-Hz Noise (V_REF

)

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10 Detailed Description

10.1 Overview

The REF34-Q1 devices are a family of low-noise, precision bandgap voltage references that are specifically

designed for excellent initial voltage accuracy and drift. The Section 10.2 is a simplified block diagram of the

REF34-Q1 showing basic band-gap topology.

10.2 Functional Block Diagram

Enable

Blocks

GNDF

GNDS

OUTF

OUTS

Vdd

Digital

Inrush

Current

Limit

Bandgap

core

Buffer

10.3 Feature Description

10.3.1 Supply Voltage

The REF34-Q1 family of references features an extremely low dropout voltage. For loaded conditions, a typical

dropout voltage versus load is shown on the front page. The REF34-Q1 family features a low quiescent current

that is extremely stable over changes in both temperature and supply. The typical room temperature quiescent

current is 72 μA, and the maximum quiescent current over temperature is just 95 μA. Supply voltages below the

specified levels can cause the REF34-Q1 to momentarily draw currents greater than the typical quiescent

current. Use a power supply with a fast rising edge and low output impedance to easily prevent this issue.

10.3.2 Low Temperature Drift

The REF34-Q1 devices are designed for minimal drift error, which is defined as the change in output voltage

over temperature. The drift is calculated using the box method, as described by Equation 3:

V_REF(MAX)- V_REF(MIN)

≈

∆

’

◊

Drift =

ì 10⁶

V_REFì Temperature Range

(3)

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10.3.3 Load Current

The REF34-Q1 family is specified to deliver a current load of ±10 mA per output. The V_REFoutput of the device

are protected from short circuits by limiting the output short-circuit current to 18 mA. The device temperature

increases according to Equation 4:

T_J= T_A+P ì R_qJA

(4)

where

•

T_J= junction temperature (°C),

T_A= ambient temperature (°C),

P_D= power dissipated (W), and

R_θJA= junction-to-ambient thermal resistance (°C/W)

The REF34-Q1 maximum junction temperature must not exceed the absolute maximum rating of 150°C.

10.4 Device Functional Modes

10.4.1 EN Pin

When the EN pin of the REF34-Q1 is pulled high, the device is in active mode. The device must be in active

mode for normal operation. The REF34-Q1 can be placed in a low-power mode by pulling the ENABLE pin low.

When in shutdown mode, the output of the device becomes high impedance and the quiescent current of the

device reduces to 2 µA in shutdown mode. The EN pin must not be pulled higher than VIN supply voltage. See

Thermal Information for logic high and logic low voltage levels.

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11 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

11.1 Application Information

As the REF34-Q1 devices have many applications and setups, there are many situations that this data sheet can

not characterize in detail. Basic applications includes positive/negative voltage reference and data acquisition

systems.

Table 11-1. Typical Applications and Companion ADC/DAC

APPLICATIONS

ADC/DAC/CONTROLLER

ADAS

ADS7828-Q1

HEV/EV

ADS7951-Q1, ADS1120-Q1, ADS1258,

BQ76PL455A-Q1

11.2 Typical Applications

11.2.1 Basic Voltage Reference Connection

The circuit shown in Figure 11-1 shows the basic configuration for the REF34-Q1 references. Connect bypass

capacitors according to the guidelines in Section 11.2.1.2.1.

10 ꢀ

124 ꢀ

Input Signal

ADS7828-Q1

REF

1 nF

VIN

CIN

1µF

COUT

10 µF

REF34-Q1

Figure 11-1. Basic Reference Connection

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11.2.1.1 Design Requirements

A detailed design procedure is based on a design example. For this design example, use the parameters listed

in Table 11-2 as the input parameters.

Table 11-2. Design Example Parameters

DESIGN PARAMETER

VALUE

Input voltage V_IN

12 V

Output voltage V_OUT

5 V

REF3450-Q1 input capacitor

REF3450-Q1 output capacitor

1 µF

10 µF

11.2.1.2 Detailed Design Procedure

11.2.1.2.1 Input and Output Capacitors

A 1-μF to 10-μF electrolytic or ceramic capacitor can be connected to the input to improve transient response in

applications where the supply voltage may fluctuate. Connect an additional 0.1-μF ceramic capacitor in parallel

to reduce high frequency supply noise.

A ceramic capacitor of at least a 0.1 μF must be connected to the output to improve stability and help filter out

high frequency noise. An additional 1-μF to 10-μF electrolytic or ceramic capacitor can be added in parallel to

improve transient performance in response to sudden changes in load current; however, keep in mind that doing

so increases the turnon time of the device.

Best performance and stability is attained with low-ESR, low-inductance ceramic chip-type output capacitors

(X5R, X7R, or similar). If using an electrolytic capacitor on the output, place a 0.1-μF ceramic capacitor in

parallel to reduce overall ESR on the output.

11.2.1.2.2 4-Wire Kelvin Connections

Current flowing through a PCB trace produces an IR voltage drop, and with longer traces, this drop can reach

several millivolts or more, introducing a considerable error into the output voltage of the reference. A 1-inch long,

5-millimeter wide trace of 1-ounce copper has a resistance of approximately 100 mΩ at room temperature; at a

load current of 10 mA, this can introduce a full millivolt of error. In an ideal board layout, the reference must be

mounted as close as possible to the load to minimize the length of the output traces, and, therefore, the error

introduced by voltage drop. However, in applications where this is not possible or convenient, force and sense

connections (sometimes referred to as Kelvin sensing connections) are provided as a means of minimizing the

IR drop and improving accuracy.

Kelvin connections work by providing a set of high impedance voltage-sensing lines to the output and ground

nodes. Because very little current flows through these connections, the IR drop across their traces is negligible,

and the output and ground.

It is always advantageous to use Kelvin connections whenever possible. However, in applications where the IR

drop is negligible or an extra set of traces cannot be routed to the load, the force and sense pins for both V_OUT

and GND can simply be tied together, and the device can be used in the same fashion as a normal 3-terminal

reference (as shown in Figure 9-6).

11.2.1.2.3 V_INSlew Rate Considerations

In applications with slow-rising input voltage signals, the reference exhibits overshoot or other transient

anomalies that appear on the output. These phenomena also appear during shutdown as the internal circuitry

loses power.

To avoid such conditions, ensure that the input voltage wave-form has both a rising and falling slew rate close to

6 V/ms.

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11.2.1.2.4 Shutdown/Enable Feature

The REF34-Q1 references can be switched to a low power shut-down mode when a voltage of 0.5 V or lower is

input to the ENABLE pin. Likewise, the reference becomes operational for ENABLE voltages of 1.6 V or higher.

During shutdown, the supply current drops to less than 2 μA, useful in applications that are sensitive to power

consumption.

If using the shutdown feature, ensure that the ENABLE pin voltage does not fall between 0.5 V and 1.6 V

because this causes a large increase in the supply current of the device and may keep the reference from

starting up correctly. If not using the shutdown feature, however, the ENABLE pin can simply be tied to the IN

pin, and the reference remains operational continuously.

11.2.1.3 Application Curves

74.5

2.6

2.5

2.4

2.3

2.2

2.1

73.5

72.5

71.5

-50

-25

25 50

Temperature (°C)

100

125

-40

-15

35 60

Temperature (°C)

110 125

D004

D013

Figure 11-2. Quiescent Current vs Temperature

Figure 11-3. Quiescent Current Shutdown Mode

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11.2.2 Advanced Driver Assistance Systems (ADAS) Microcontroller Connection

11.2.2.1 Basic Voltage Reference Connection

The circuit shown in Figure 11-4 shows the basic configuration for the REF34-Q1 references.

3V VDD

VDD

2.5V VREF

AIN0

VREF+

OUT

GND

AIN1

AIN2

AIN3

VREF-

REF3425-Q1

ADS7828-Q1

3.3V VDD

I2C

VDD

GPIO0

GPIOx

I2C

TDA2 (MCU)

Figure 11-4. ADAS Microcontroller Application

11.2.2.2 Design Requirements

In ADAS applications it is common to use an ADC with a MCU to monitor the voltage rails to the MCU/DSP/

FPGAs. In figure Figure 11-4 the automotive TI Jacinto^™TDA2 MCU is using a ADS7828-Q1 to monitor several

analog input signals and in ADAS these signals will be the system power rails. It is important to monitor these

power rails because tighter rail requirements allow for further system monitoring and optimization. The

REF3425-Q1 is used in this application to provide the precise voltage reference signal. In these systems it is not

typical to have calibration and such the most precise low power voltage reference is necessary to be able to

measure down to 1% accuracy on key power rails.

For this design example, use the parameters listed in Table 11-3 as the input parameters and desired output

parameters.

Table 11-3. Typical Core Voltage Rail Monitoring

SPECIFICATION

REQUIREMENT

Input Voltage V_IN

Output Voltage

2.5V

Voltage Power Rail

Max Error on Voltage Power Rail

Temperature Range

-40°C to 125°C

11.2.2.3 Detailed Design Procedure

It is important to keep track of the error margin in this system to make sure that the total error of the voltage

reference and ADC are less than the maximum 1% error allowed. To calculate the total RSS error of a voltage

reference use Equation 5.

Error_{VREF Total}

Accuracy ²+ TempCo ²+ TempHyst ²+ LongTerm Drift ²+ 1/ f Noise

(

)

(

)

(

)

(

)

(

)

(5)

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With the RSS error of the voltage reference, the ADC error needs also needs to be calculated using the RSS

method as seen in Equation 6. Equation 7 can then be used to sum both errors. It is important to make sure that

only the applicable voltage reference error in relation to the measured signal is used.

Total Unadjusted Error = Error_{ADC Total}

Gain Error ²+ Offset Error ²+ INL Error ²+ DNL Error

(

)

(

)

(

)

(

)

(6)

(7)

²+ Error

Error_{VREF+ ADC Total}

Error

(

)

(

)

VREF@AIN Total

ADC Total

11.2.2.4 Enable Feature in ADAS

In ADAS applications it is important to have a low quiescent current when the automotive application does not

require the ADAS system to be in use. This creates a need for a low standby power so the battery life is

preserved but there is also need for the system to still be readily available to start-up with minimal delays. In

such situations the MCU and other systems will go into a standby mode to ensure that the power consumption is

lowered to the absolute minimum. The REF3425-Q1 offers an enable pin that can be controlled by the MCU to

activate shutdown mode with causes the REF3425-Q1 to go into stand by and consume 3 μA (maximum) and

allow for a longer battery life.

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12 Power Supply Recommendations

The REF34-Q1 family of references feature an extremely low-dropout voltage. These references can be

operated with a supply of only 50 mV above the output voltage. TI recommends a supply bypass capacitor

ranging between 0.1 µF to 10 µF.

13 Layout

13.1 Layout Guidelines

Figure 13-1 illustrates an example of a PCB layout for a data acquisition system using the REF34-Q1. Some key

considerations are:

•

Connect low-ESR, 0.1-μF ceramic bypass capacitors at V_IN, V_REFof the REF34-Q1.

Decouple other active devices in the system per the device specifications.

Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise

pickup.

•

Place the external components as close to the device as possible. This configuration prevents parasitic errors

(such as the Seebeck effect) from occurring.

Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when absolutely necessary.

13.2 Layout Example

6 OUT_F

5 OUT_S

GND_F

GND_S

REF34XX

Figure 13-1. Layout Example (REF34xx-Q1 DBV Package)

GND

NIC

REF34S-Q1

C_IN

OUT

C_OUT

Figure 13-2. Layout Example (REF34xxS-Q1 DBV Package)

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C_IN

8 IN

ENABLE

GND_S

GND_F

NIC

OUT_S

REF34-Q1

(DGK)

OUT_F

NIC

C_OUT

Figure 13-3. Layout Example (REF34xx-Q1 DGK Package)

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14 Device and Documentation Support

14.1 Documentation Support

14.1.1 Related Documentation

For related documentation see the following:

•

INA21x Voltage Output, Low- or High-Side Measurement, Bidirectional, Zero-Drift Series, Current-Shunt

Monitors

•

Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design

14.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

14.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

14.4 Trademarks

Jacinto^™is a trademark of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

14.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

14.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

2-Apr-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

REF3425QDBVRQ1

REF3425QDGKRQ1

REF3425SQDBVRQ1

REF3430QDBVRQ1

REF3430QDGKRQ1

REF3430SQDBVRQ1

REF3433QDBVRQ1

REF3433QDGKRQ1

REF3433SQDBVRQ1

REF3440QDBVRQ1

REF3440QDGKRQ1

REF3440SQDBVRQ1

REF3450QDBVRQ1

REF3450QDGKRQ1

REF3450SQDBVRQ1

ACTIVE

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

DBV

DGK

DBV

DGK

DBV

DGK

DBV

DGK

DBV

DGK

DBV

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

2500 RoHS & Green

3000 RoHS & Green

NIPDAUAG

Level-2-260C-1 YEAR

-40 to 125

1OLC

2E93

2D6C

NIPDAUAG

NIPDAU

NIPDAUAG

NIPDAU

1OMC

2FW3

2D7C

1ONC

2FV3

2D8C

1OOC

2FQ3

2D9C

1OPC

2FX3

2DAC

NIPDAUAG

NIPDAU

NIPDAUAG

NIPDAU

NIPDAUAG

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

2-Apr-2021

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Apr-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

REF3425QDBVRQ1

REF3425QDGKRQ1

REF3425SQDBVRQ1

REF3430QDBVRQ1

REF3430QDGKRQ1

REF3430SQDBVRQ1

REF3433QDBVRQ1

REF3433QDGKRQ1

REF3433SQDBVRQ1

REF3440QDBVRQ1

REF3440QDGKRQ1

REF3440SQDBVRQ1

REF3450QDBVRQ1

REF3450QDGKRQ1

REF3450SQDBVRQ1

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

DBV

DGK

DBV

DGK

DBV

DGK

DBV

DGK

DBV

DGK

DBV

3000

2500

3000

2500

3000

2500

3000

2500

3000

2500

3000

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

8.4

12.4

8.4

3.23

5.3

3.17

3.4

1.37

1.4

4.0

8.0

4.0

8.0

4.0

8.0

4.0

8.0

4.0

8.0

4.0

8.0

12.0

8.0

3.23

5.3

3.17

3.4

1.37

1.4

8.4

8.0

12.4

8.4

12.0

8.0

3.23

5.3

3.17

3.4

1.37

1.4

8.4

8.0

12.4

8.4

12.0

8.0

3.23

5.3

3.17

3.4

1.37

1.4

8.4

8.0

12.4

8.4

12.0

8.0

3.23

5.3

3.17

3.4

1.37

1.4

8.4

8.0

12.4

8.4

12.0

8.0

3.23

3.17

1.37

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Apr-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

REF3425QDBVRQ1

REF3425QDGKRQ1

REF3425SQDBVRQ1

REF3430QDBVRQ1

REF3430QDGKRQ1

REF3430SQDBVRQ1

REF3433QDBVRQ1

REF3433QDGKRQ1

REF3433SQDBVRQ1

REF3440QDBVRQ1

REF3440QDGKRQ1

REF3440SQDBVRQ1

REF3450QDBVRQ1

REF3450QDGKRQ1

REF3450SQDBVRQ1

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

VSSOP

SOT-23

DBV

DGK

DBV

DGK

DBV

DGK

DBV

DGK

DBV

DGK

DBV

3000

2500

3000

2500

3000

2500

3000

2500

3000

2500

3000

213.0

366.0

213.0

366.0

213.0

366.0

213.0

366.0

213.0

366.0

213.0

191.0

364.0

191.0

364.0

191.0

364.0

191.0

364.0

191.0

364.0

191.0

35.0

50.0

35.0

50.0

35.0

50.0

35.0

50.0

35.0

50.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

0.90

PIN 1

INDEX AREA

2X 0.95

1.9

3.05

2.75

1.9

0.5

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/E 09/2019

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

1.45 MAX

PIN 1

INDEX AREA

2X 0.95

1.9

3.05

2.75

0.50

0.25

C A B

0.15

0.00

0.2

(1.1)

TYP

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214840/B 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.

4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.

5. Refernce JEDEC MO-178.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

6X (0.6)

SYMM

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214840/B 03/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

6X (0.6)

SYMM

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214840/B 03/2018

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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REF3433SQDBVRQ1 [TI]

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