REF4132B40DBVR [TI]
12ppm/°C 低噪声低功耗精密电压基准 | DBV | 5 | -40 to 125;
| 型号： | REF4132B40DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12ppm/°C 低噪声低功耗精密电压基准 | DBV | 5 | -40 to 125 |
| 文件： | 总26页 (文件大小：1839K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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REF4132
SNAS794A –JUNE 2020–REVISED JUNE 2020
REF4132 Low-Drift, Low-Power, Small-Footprint Series Voltage Reference
1 Features
3 Description
The REF4132 device is a low temperature drift
(12 ppm/°C), low-power, high-precision CMOS
voltage reference, featuring ±0.05% initial accuracy,
low operating current with power consumption less
than 100μA. This device also offers very low output
noise of 15 μVp-p/V, which enables its ability to
maintain high signal integrity with high-resolution data
converters in noise critical systems. Packaged in the
same SOT-23-5 package, REF4132 offers enhanced
specifications and pin-to-pin replacement for LM4128
and LM4132.
1
•
Voltage options: 2.5V, 3V, 3.3V, 4.096V, 5V
Initial accuracy: ±0.05% (maximum)
Low temperature coefficient :
•
•
–
–
A grade: 12 ppm/°C (maximum)
B grade: 30 ppm/°C (maximum)
•
•
•
•
•
•
Operating temperature range: −40°C to +125°C
Output current: ±10 mA
Low quiescent current: 100 μA (maximum)
Output 1/f noise (0.1 Hz to 10 Hz): 15 µVPP/V
Excellent long-term stability 30 ppm/1000 hrs
Small footprint 5-pin SOT-23 package
Stability and system reliability are further improved by
the low output-voltage hysteresis of the device and
low long-term output voltage drift. Furthermore, the
small size and low operating current of the devices
(100 μA) can benefit portable and battery-powered
applications.
2 Applications
•
•
•
•
•
•
Data acquisition (DAQ)
PLC analog I/O modules
Field transmitters
REF4132 is specified for the wide temperature range
of −40°C to +125°C.
Motor drive control module
Battery test equipment
LCR meters
Device Information(1)
PART NAME
REF4132
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Dropout vs. Current Load Over Temperature
+5 V
0.4
0.36
+125°C
0.32
EN
VIN
0.28
VREF
+25°C
-40°C
REF4132
GND
+2.5 V
0.24
R1
0.2
0.16
0.12
0.08
0.04
0
10 kΩ
R2
10 kΩ
+5 V
œ
0
5
Load Current (mA)
10
OPA735
+
-2.5 V
-5 V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
REF4132
SNAS794A –JUNE 2020–REVISED JUNE 2020
www.ti.com
Table of Contents
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
Parameter Measurement Information .................. 9
8.1 Solder Heat Shift....................................................... 9
8.2 Long-Term Stability................................................. 10
8.3 Thermal Hysteresis ................................................. 10
8.4 Power Dissipation ................................................... 10
8.5 Noise Performance ................................................. 11
Detailed Description ............................................ 12
10.2 Typical Application: Basic Voltage Reference
Connection............................................................... 14
11 Power Supply Recommendations ..................... 16
12 Layout................................................................... 17
12.1 Layout Guidelines ................................................. 17
12.2 Layout Example .................................................... 17
13 Device and Documentation Support ................. 18
13.1 Documentation Support ........................................ 18
13.2 Receiving Notification of Documentation Updates 18
13.3 Community Resources.......................................... 18
13.4 Trademarks........................................................... 18
13.5 Electrostatic Discharge Caution............................ 18
13.6 Glossary................................................................ 18
8
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2020) to Revision A
Page
•
Added 3V, 3.3V, 4.096V, 5V output voltage variants. ............................................................................................................ 1
2
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5 Device Comparison Table
PRODUCT
VOUT
2.5 V
3.0 V
3.3 V
4.096 V
5 V
REF4132 - 2.5
REF4132 - 3.0
REF4132 - 3.3
REF4132 - 4.0
REF4132 - 5.0
6 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
VREF
1
2
3
5
N/C
GND
EN
4
VIN
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
N/C
–
No connect pin, leave floating
Ground
2
GND
EN
Ground
Input
3
Enable pin. Enables or disables the device.
Reference voltage input
4
VIN
Power
Output
5
VREF
Reference voltage output
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
6
UNIT
V
Input voltage
VIN
Enable voltage
VEN
VREF
ISC
VIN + 0.3
5.5
V
Output voltage
V
Output short circuit current
Operating temperature range
Storage temperature range
20
mA
°C
°C
TA
–55
–65
150
Tstg
170
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. These are stress ratings only and functional operation of the device at these or any other conditions
beyond those specified in the Electrical Characteristics Table is not implied.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VREF
VDO
+
VIN
Input Voltage
5.5
V
(1)
VEN
IL
Enable Voltage
0
VIN
10
V
Output Current
–10
–40
mA
℃
TA
Operating Temperature
25
125
(1) Dropout voltage
7.4 Thermal Information
DEVICE
THERMAL METRIC(1)
DBV
5 PINS
185
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
156
29.6
33.8
29.1
N/A
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At VIN = 5.5 V, VEN = VIN, CREF = 10 µF, CIN = 0.1 µF, IL = 0 mA, minimum and maximum specifications at TA = –40℃ to
125℃; typical specifications at TA = 25℃ unless otherwise noted
PARAMETER
ACCURACY AND DRIFT
Output voltage
TEST CONDITION
MIN
TYP
MAX
UNIT
TA = 25°C
–0.05
0.05
%
accuracy
Output voltage
temperature
coefficient
–40°C ≤ TA ≤ 125°C
–40°C ≤ TA ≤ 125°C
REF4132 A grade
REF4132 B grade
12 ppm/℃
30 ppm/℃
LINE & LOAD REGULATION
VREF + VDO ≤ VIN ≤ 5.5 V
2
ppm/V
15 ppm/V
55 ppm/V
ppm/mA
ΔVREF/ΔVIN
Line Regulation
Load Regulation
VREF + VDO ≤ VIN ≤ 5.5 V
VREF = 5 V, VREF + VDO ≤ VIN ≤ 5.5 V
IL = 0 mA to 10mA, VIN = VREF + VDO
IL = 0 mA to 10mA, VIN = VREF + VDO
20
ΔVREF/ΔIL
120 ppm/mA
POWER SUPPLY
VREF
VDO
+
VIN
Input voltage
5.5
V
Active mode
80
100
5
µA
µA
V
IQ
Quiescent current
Shutdown mode, VEN = 0 V
2.5
Voltage reference in active mode (EN=1)
Voltage reference in shutdown mode (EN=0)
1.6
Enable pin
Voltage
VEN
IEN
0.5
2
V
Enable pin
current
VEN = 5.5 V
1
µA
IL = 0 mA
IL = 0 mA
IL = 10 mA
50
mV
mV
mV
VDO
Dropout voltage
100
500
Short circuit current
ISC
VREF = 0 V
18
11.5
mA
(1)
TURNON
tON
Turn-on time
0.1% settling, CL = 1 µF, 10% to 90%
2.5
ms
NOISE
Low frequency
noise
en(p-p)
en
ƒ = 0.1 Hz to 10 Hz
ƒ = 10 Hz to 10 kHz
15
24
ppmp-p
µVrms
Wide band
noise
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability
0 to 1000h at 35℃
30
35
ppm
ppm
Output voltage
hysteresis
VHYST
TA= 25℃ to −40℃ to 125℃ to 25℃
CAPACITIVE LOAD
Stable output
capacitor range
CL
0.1
10
µF
(1) At higher ambient temperature the short circuit current capacity is limited due to junction temeprature max limit
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7.6 Typical Characteristics
at TA = 25°C, VIN = VEN = 5 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
0.02
0.015
0.01
85
84
83
82
81
80
79
78
0.005
0
-0.005
-0.01
-0.015
-0.02
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
Figure 1. Output Voltage Accuracy vs Temperature
Figure 2. VIN vs IQ over Temperature
25
20
15
10
5
-20
-40
CL = 1uF
CL = 10uF
-60
-80
-100
0
-120
-40
-15
10
35 60
Temperature (°C)
85
110 125
10
100
1k
Frequency (Hz)
10k
100k
D005
Figure 3. Short Circuit Current
Figure 4. Power-Supply Rejection Ratio vs Frequency
0.26
0.24
0.22
0.2
12
11.5
11
10.5
10
0.18
0.16
0.14
0.12
9.5
9
8.5
8
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
Figure 5. Line Regulation
Figure 6. Load Regulation Sourcing
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Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = 5 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
800
ILOAD
720
+1mA
+1mA
640
560
480
-1mA
1mA/div
400
VOUT
320
240
160
80
4mV/div
0
10
250µs/div
100
1k
Frequency(Hz)
10k
100k
(CL = 1µF, IOUT = 1mA)
Figure 8. Load Transient
Figure 7. Noise Performance 10 Hz to 10 kHz
ILOAD
+10mA
ILOAD
+1mA
+1mA
+10mA
10mA/div
-1mA
-10mA
1mA/div
4mV/div
VOUT
VOUT
100mV/div
250µs/div
250µs/div
(CL = 10µF, IOUT = 1mA)
(CL = 1µF, IOUT = 10mA)
Figure 9. Load Transient
Figure 10. Load Transient
3
2.5
2
ILOAD
+10mA
+10mA
10mA/div
20mV/div
-10mA
1.5
1
VOUT
0.5
0
-40
250µs/div
-15
10
35 60
Temperature (°C)
85
110 125
(CL = 10µF, IOUT = 10mA)
Figure 11. Load Transient
Figure 12. Quiescent Current Shutdown Mode
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Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = 5 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
10
5
0
-5
En
-10
-15
-20
-25
-30
-35
-40
1V/div
VOUT
0.5ms/div
0
100 200 300 400 500 600 700 800 900 1000
Time (hours)
Figure 13. Turnon Time (Enable)
Figure 14. Long Term Stability - 1000 hours (VREF
)
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8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF4132 have differing coefficients of thermal expansion, resulting
in stress on the device die when the part is heated. Mechanical and thermal stress on the device die can cause
the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is a
common cause of this error.
In order to illustrate this effect, a total of 32 devices were soldered on two printed circuit boards [16 devices on
each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow
profile. The reflow profile is as shown in Figure 15. The printed circuit board is comprised of FR4 material. The
board thickness is 1.65 mm and the area is 114 mm × 152 mm.
300
250
200
150
100
50
0
0
50
100
150
200
250
300
350
400
Time (seconds)
C01
Figure 15. Reflow Profile
The reference output voltage is measured before and after the reflow process; the typical shift is displayed in
Figure 16. Although all tested units exhibit very low shifts (< 0.01%), higher shifts are also possible depending on
the size, thickness, and material of the printed circuit board. An important note is that the histograms display the
typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is common on PCBs with
surface-mount components on both sides, causes additional shifts in the output bias voltage. If the PCB is
exposed to multiple reflows, the device must be soldered in the last pass to minimize its exposure to thermal
stress.
50%
40%
30%
20%
10%
0
Solder Heat Shift (%)
Figure 16. Solder Heat Shift Distribution, VREF (%)
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8.2 Long-Term Stability
One of the key parameters of the REF4132 references is long-term stability. Typical characteristic expressed as:
curves shows the typical drift value for the REF4132 is 30 ppm from 0 to 1000 hours. This parameter is
characterized by measuring 32 units at regular intervals for a period of 1000 hours. It is important to understand
that long-term stability is not ensured by design and that the output from the device may shift beyond the typical
30 ppm specification at any time. For systems that require highly stable output voltages over long periods of
time, the designer should consider burning in the devices prior to use to minimize the amount of output drift
exhibited by the reference over time.
10
5
0
-5
-10
-15
-20
-25
-30
-35
-40
0
100 200 300 400 500 600 700 800 900 1000
Time (hours)
Figure 17. Long Term Stability - 1000 hours (VREF
)
8.3 Thermal Hysteresis
Thermal hysteresis is measured with the REF4132 soldered to a PCB, similar to a real-world application.
Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C,
cycling the device through the specified temperature range, and returning to 25°C. The PCB was baked at 150°C
for 30 minutes before thermal hysteresis was measured. Hysteresis can be expressed by Equation 1:
≈
∆
«
’
÷
◊
| VPRE - VPOST
VNOM
|
VHYST
=
ì106 ppm
(
)
where
•
•
•
•
VHYST = thermal hysteresis (in units of ppm)
VNOM = the specified output voltage
VPRE = output voltage measured at 25°C pre-temperature cycling
VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature
range of –40°C to +125°C and returns to 25°C.
(1)
8.4 Power Dissipation
The REF4132 voltage references are capable of source and sink up to 10 mA of load current across the rated
input voltage range. However, when used in applications subject to high ambient temperatures, the input voltage
and load current must be carefully monitored to ensure that the device does not exceeded its maximum power
dissipation rating. The maximum power dissipation of the device can be calculated with Equation 2:
TJ = TA +P ì RqJA
D
where
•
•
•
•
PD is the device power dissipation
TJ is the device junction temperature
TA is the ambient temperature
RθJA is the package (junction-to-air) thermal resistance
(2)
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Power Dissipation (continued)
Because of this relationship, acceptable load current in high temperature conditions may be less than the
maximum current-sourcing capability of the device. In no case should the device be operated outside of its
maximum power rating because doing so can result in premature failure or permanent damage to the device.
8.5 Noise Performance
Typical 0.1-Hz to 10-Hz voltage noise can be seen in Figure 18 . Device noise increases with output voltage and
operating temperature. Additional filtering can be used to improve output noise levels, although care must be
taken to ensure the output impedance does not degrade ac performance. Peak-to-peak noise measurement
setup is shown in Figure 18.
1s/div
Figure 18. 0.1-Hz to 10-Hz Noise (VREF
)
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9 Detailed Description
9.1 Overview
The REF4132 is family of low-noise, precision bandgap voltage references that are specifically designed for
excellent initial voltage accuracy and drift. The Functional Block Diagram is a simplified block diagram of the
REF4132 showing basic band-gap topology.
9.2 Functional Block Diagram
Bandgap
Core
Digital
N/C
GND
EN
VREF
Buffer
Enable
Blocks
VIN
9.3 Feature Description
9.3.1 Supply Voltage
The REF4132 family of references features an extremely low dropout voltage. For loaded conditions, a typical
dropout voltage versus load is shown on Dropout vs. Current Load Over Temperature. The REF4132 features a
low quiescent current that is extremely stable over changes in both temperature and supply. The typical room
temperature quiescent current is 80 μA, and the maximum quiescent current over temperature is 100 μA. Supply
voltages below the specified levels can cause the REF4132 to momentarily draw currents greater than the typical
quiescent current. Use a power supply with a low output impedance.
9.3.2 Low Temperature Drift
The REF4132 is designed for minimal drift error, which is defined as the change in output voltage over
temperature. The drift is calculated using the box method, as described by Equation 3:
VREF(MAX) - VREF(MIN)
≈
∆
«
’
÷
◊
Drift =
ì 106
VREF ì Temperature Range
(3)
9.3.3 Load Current
The REF4132 family is specified to deliver a current load of ±10 mA per output. The VREF output of the device
are protected from short circuits by limiting the output short-circuit current to 18 mA. The device temperature
increases according to Equation 4:
TJ = TA +P ì RqJA
D
where
•
•
•
•
TJ = junction temperature (°C),
TA = ambient temperature (°C),
PD = power dissipated (W), and
RθJA = junction-to-ambient thermal resistance (°C/W)
(4)
The REF4132 maximum junction temperature must not exceed 150°C.
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9.4 Device Functional Modes
9.4.1 EN Pin
When the EN pin (ENABLE PIN) of the REF4132 is pulled high, the device is in active mode. The device must be
in active mode for normal operation. The REF4132 can be placed in shutdown mode by pulling the ENABLE pin
low. When in shutdown mode, the output of the device becomes high impedance and the quiescent current of
the device reduces to 2.5 µA in shutdown mode. The EN pin must not be pulled higher than VIN supply voltage.
See the Specifications for logic high and logic low voltage levels.
9.4.2 Negative Reference Voltage
For applications requiring a negative and positive reference voltage, the REF4132 and OPA735 can be used to
provide a dual-supply reference from a 5-V supply. Figure 19 shows the REF4132 used to provide a 2.5-V supply
reference voltage. The low drift performance of the REF4132 complements the low offset voltage and zero drift of
the OPA735 to provide an accurate solution for split-supply applications. Take care to match the temperature
coefficients of R1 and R2.
+5 V
EN
VIN
VREF
REF4132
+2.5 V
R1
10 kΩ
GND
R2
10 kΩ
+5 V
œ
OPA735
+
-2.5 V
-5 V
Figure 19. REF4132 and OPA735 Create Positive and Negative Reference Voltages
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The REF4132 is a versatile device which can cater to multiple applications and use cases. Basic applications
includes positive/negative voltage reference and data acquisition systems. The table below shows the typical
application of REF4132 and its companion ADC/DAC.
Table 1. Typical Applications and Companion ADC/DAC
Applications
ADC/DAC
PLC - DCS
DAC8881, ADS8332, ADS8568, ADS8317,
ADS8588S, ADS1287
Display Test Equipment
ADS8332, ADS8168
ADS1120
Field Transmitters - Pressure
Video Surveillance - Thermal Cameras
Medical Blood Glucose Meter
ADS7279
ADS1112
10.2 Typical Application: Basic Voltage Reference Connection
The circuit shown in Figure 20 shows the basic configuration for the REF4132 references. Connect bypass
capacitors according to the guidelines in Layout Guidelines.
10 ꢀ
10 ꢀ
124 ꢀ
-
ADS1287
REF
Input Signal
1 nF
+
VIN
VREF
CIN
REF4132
COUT
GND
EN
VIN
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Figure 20. Basic Reference Connection
10.2.1 Design Requirements
A detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 2 as the input parameters.
Table 2. Design Example Parameters
DESIGN PARAMETER
Input voltage VIN
VALUE
5 V
Output voltage VOUT
2.5 V
1 µF
REF4132 input capacitor
REF4132 output capacitor
10 µF
14
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REF4132
www.ti.com
SNAS794A –JUNE 2020–REVISED JUNE 2020
10.2.2 Detailed Design Procedure
10.2.2.1 Input and Output Capacitors
A 1-μF to 10-μF electrolytic or ceramic capacitor can be connected to the input to improve transient response in
applications where the supply voltage may fluctuate. Connect an additional 0.1-μF ceramic capacitor in parallel to
reduce high frequency supply noise.
A ceramic capacitor of at least a 0.1 μF must be connected to the output to improve stability and help filter out
high frequency noise. An additional 1-μF to 10-μF electrolytic or ceramic capacitor can be added in parallel to
improve transient performance in response to sudden changes in load current; however, keep in mind that doing
so increases the turnon time of the device.
Best performance and stability is attained with low-ESR, low-inductance ceramic chip-type output capacitors
(X5R, X7R, or similar). If using an electrolytic capacitor on the output, place a 0.1-μF ceramic capacitor in parallel
to reduce overall ESR on the output.
10.2.2.2 VIN Slew Rate Considerations
In applications with slow-rising input voltage signals, the reference exhibits overshoot or other transient
anomalies that appear on the output. These phenomena also appear during shutdown as the internal circuitry
loses power.
To avoid such conditions, ensure that the input voltage wave-form has both a rising and falling slew rate faster
than 6 V/ms.
10.2.2.3 Shutdown/Enable Feature
The REF4132 references can be switched to a low power shut-down mode when a voltage of 0.5 V or lower is
input to the ENABLE pin. Likewise, the reference becomes operational for ENABLE voltages of 1.6 V or higher.
During shutdown, the supply current drops to less than 2.5 μA, useful in applications that are sensitive to power
consumption.
If using the shutdown feature, ensure that the ENABLE pin voltage does not fall between 0.5 V and 1.6 V
because this causes a large increase in the supply current of the device and may keep the reference from
starting up correctly. If not using the shutdown feature, however, the ENABLE pin can simply be tied to the IN
pin, and the reference remains operational continuously.
10.2.3 Application Curves
85
84
83
82
81
80
79
78
3
2.5
2
1.5
1
0.5
0
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
Figure 21. Quiescent Current vs Temperature
Figure 22. Quiescent Current Shutdown Mode
Copyright © 2020, Texas Instruments Incorporated
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SNAS794A –JUNE 2020–REVISED JUNE 2020
www.ti.com
11 Power Supply Recommendations
The REF4132 family of references feature an extremely low-dropout voltage. These references can be operated
with a supply of only 50 mV above the output voltage. TI recommends a supply bypass capacitor ranging
between 0.1 µF to 10 µF.
16
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REF4132
www.ti.com
SNAS794A –JUNE 2020–REVISED JUNE 2020
12 Layout
12.1 Layout Guidelines
Figure 23 illustrates an example of a PCB layout for a data acquisition system using the REF4132. Some key
considerations are:
•
•
•
•
Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF of the REF4132.
Decouple other active devices in the system per the device specifications.
Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
•
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
COUT
1
2
5 VREF
N/C
GND
EN
REF4132
VIN
4
3
CIN
Figure 23. Layout Example
Copyright © 2020, Texas Instruments Incorporated
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REF4132
SNAS794A –JUNE 2020–REVISED JUNE 2020
www.ti.com
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
Voltage Reference Design Tips For Data Converters
Voltage Reference Selection Basics
Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design
OPA375, OPA2375, OPA4375 500-μV (Maximum), 10-MHz,Low Broadband Noise, RRO, Operational
Amplifier
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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Product Folder Links: REF4132
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
REF4132A25DBVR
REF4132A30DBVR
REF4132A33DBVR
REF4132A40DBVR
REF4132A50DBVR
REF4132B25DBVR
REF4132B30DBVR
REF4132B33DBVR
REF4132B40DBVR
REF4132B50DBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
24MD
24ND
24OD
24PD
24QD
24SD
24TD
24UD
24VD
24WD
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF REF4132 :
Automotive: REF4132-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
REF4132A25DBVR
REF4132A30DBVR
REF4132A33DBVR
REF4132A40DBVR
REF4132A50DBVR
REF4132B25DBVR
REF4132B30DBVR
REF4132B33DBVR
REF4132B40DBVR
REF4132B50DBVR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
REF4132A25DBVR
REF4132A30DBVR
REF4132A33DBVR
REF4132A40DBVR
REF4132A50DBVR
REF4132B25DBVR
REF4132B30DBVR
REF4132B33DBVR
REF4132B40DBVR
REF4132B50DBVR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
445.0
445.0
445.0
445.0
445.0
445.0
445.0
445.0
445.0
445.0
220.0
220.0
220.0
220.0
220.0
220.0
220.0
220.0
220.0
220.0
345.0
345.0
345.0
345.0
345.0
345.0
345.0
345.0
345.0
345.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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