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REF6133IDGKT [TI]

具有集成缓冲器和使能引脚的 3.3V、8ppm/°C 高精度电压基准 | DGK | 8 | -40 to 125;
REF6133IDGKT
型号： REF6133IDGKT
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有集成缓冲器和使能引脚的 3.3V、8ppm/°C 高精度电压基准 | DGK | 8 | -40 to 125
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REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
REF61xx 集成 ADC 驱动器缓冲器的高精度电压基准  
1 特性  
3 说明  
1
•
出色的温度漂移性能  
-40℃ 至 +125°C 时为 8ppm/°C（最大值）  
极低噪声  
REF6000 系列电压基准集成低输出阻抗缓冲器，这使  
得用户能够直接驱动精密数据转换器的 REF 引脚，同  
时维持线性度、失真和噪声性能。多数精密 SAR 和 Δ-  
Σ ADC 在转换过程中会将二进制加权电容切换到 REF  
引脚。为了支持这一动态负载，必须通过一个低输出阻  
抗（高带宽）缓冲器缓冲电压基准的输出。REF6000  
系列器件非常适合（但不限于）驱动 ADS88xx 系列  
SAR ADC 和 ADS127xx 系列 Δ-Σ ADC 以及其他数模  
转换器 (DAC) 的 REF 引脚。  
–
•
–
–
总噪声：5 µVRMS（使用 47µF 电容时）  
1/f 噪声（0.1Hz 至 10Hz）：3 µVPP/V  
•
集成 ADC 驱动器缓冲器  
–
–
–
低输出阻抗：< 50mΩ (0kHz-200kHz)  
首次使用 ADS8881 实现 18 位精确采样  
支持突发模式 DAQ 系统  
•
•
•
•
低电源电流：820µA  
低关断电流：1μA  
高初始精度：±0.05%  
超低噪声和失真  
在驱动 ADS8881 的 REF 引脚时，即使在首次转换过  
程中，REF6000 系列电压基准的输出电压也不会降至  
1 LSB（18 位）以下。该特性对于突发模式、事件触  
发的等时采样和可变采样率数据采集系统极为有用。  
REF6000 系列的 REF61xx 型号指定了最大温度漂移  
（仅为 8ppm/°C），可为电压基准与低输出阻抗缓冲  
器组合提供 0.05% 初始精度。关于 REF6000 系列中  
的多种温度漂移选项，请参见 器件比较表。  
–
信噪比 (SNR)：100.5dB，总谐波失真  
(THD)：-125dB (ADS8881)  
–
信噪比 (SNR)：106dB，总谐波失真 (THD)：-  
120dB (ADS127L01)  
•
•
•
输出电流驱动能力：±4mA  
器件信息(1)  
可通过编程设定的短路电流  
产品型号  
REF61xx  
封装  
VSSOP (8)  
封装尺寸（标称值）  
经验证用于驱动 ADS88xx 系列逐次逼近寄存器  
(SAR) ADC 和 ADS127xx 系列宽频带 Δ-Σ ADC 的  
REF 引脚  
3.00mm x 3.00mm  
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。  
2 应用  
•
•
•
•
•
自动测试设备 (ATE) 测试器和示波器  
测试和测量设备  
可编程逻辑控制器 (PLC) 的模拟输入模块  
医疗设备  
精密数据采集系统  
典型应用  
基准压降比较  
（1 LSB = 19.07µV，ADS8881 的速率为 1MSPS）  
Power Supply  
RLIM  
VIN  
SS  
OUT_S  
OUT_F  
REF61xx  
4
VIN  
3
Buffer  
Regular Voltage Reference Droop  
RFILT  
Bandgap  
Voltage  
EN  
+
Reference  
RESR  
2
1
0
GND_S  
FILT  
GND_F  
CL  
CFILT  
R
œ1  
REF61xx Droop  
Power Supply  
RF  
R
œ2  
GND  
ADS8881  
REF  
+
AINP  
AINN  
VIN  
CF  
THS4521  
œ3  
œ4  
R
RF  
R
Copyright © 2016, Texas Instruments Incorporated  
0
200  
400  
600  
800  
1000  
Time (µs)  
C04  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
English Data Sheet: SBOS747  
 
 
 
 
 
REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
www.ti.com.cn  
目录  
9.1 Overview ................................................................. 19  
9.2 Functional Block Diagram ....................................... 19  
9.3 Feature Description................................................. 20  
9.4 Device Functional Modes........................................ 23  
10 Applications and Implementation...................... 24  
10.1 Application Information.......................................... 24  
10.2 Typical Application ................................................ 24  
11 Power Supply Recommendations ..................... 27  
12 Layout................................................................... 28  
12.1 Layout Guidelines ................................................. 28  
12.2 Layout Example .................................................... 28  
13 器件和文档支持 ..................................................... 29  
13.1 文档支持................................................................ 29  
13.2 相关链接................................................................ 29  
13.3 接收文档更新通知 ................................................. 29  
13.4 社区资源................................................................ 29  
13.5 商标....................................................................... 29  
13.6 静电放电警告......................................................... 29  
13.7 Glossary................................................................ 29  
14 机械、封装和可订购信息....................................... 30  
1
2
3
4
5
6
7
特性.......................................................................... 1  
应用.......................................................................... 1  
说明.......................................................................... 1  
修订历史记录 ........................................................... 2  
Device Comparison Table..................................... 3  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
7.1 Absolute Maximum Ratings ...................................... 4  
7.2 ESD Ratings.............................................................. 4  
7.3 Recommended Operating Conditions....................... 4  
7.4 Thermal Information.................................................. 4  
7.5 Electrical Characteristics.......................................... 5  
7.6 Typical Characteristics.............................................. 7  
Parameter Measurement Information ................ 14  
8.1 Solder Heat Shift..................................................... 14  
8.2 Thermal Hysteresis ................................................. 15  
8.3 Reference Droop Measurements............................ 16  
8.4 1/f Noise Performance ............................................ 18  
Detailed Description ............................................ 19  
8
9
4 修订历史记录  
Changes from Revision A (June 2016) to Revision B  
Page  
•
•
•
•
•
•
•
•
•
已更改 说明 ............................................................................................................................................................................ 1  
Changed the Device Comparison Table ............................................................................................................................... 3  
Changed list of devices for output current in Recommended Operating Conditions ............................................................ 4  
Changed load regulation max value for REF6150 at TA = –40°C to +125°C from 30 to 50 ................................................. 5  
Changed Figure 1................................................................................................................................................................... 7  
Changed Figure 2................................................................................................................................................................... 7  
Changed Figure 5................................................................................................................................................................... 7  
Changed "second pass" to "final pass" in last paragraph of Solder Heat Shift section ...................................................... 14  
Added link to SLYY097 in Overview section ........................................................................................................................ 19  
Changes from Original (May 2016) to Revision A  
Page  
•
已由“产品预览”更改为“量产数据” ............................................................................................................................................ 1  
2
版权 © 2016, Texas Instruments Incorporated  
 
REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
www.ti.com.cn  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
5 Device Comparison Table  
DEVICE FAMILY  
TEMPERATURE DRIFT  
5 ppm/°C from –40 to 125°C  
8 ppm/°C from –40 to 125°C  
3 ppm/°C from 0 to 70°C  
REF60xx  
REF61xx  
REF62xx  
6 Pin Configuration and Functions  
DGK Package  
8-Pin VSSOP  
Top View  
VIN  
EN  
1
2
3
4
8
7
6
5
GND_S  
GND_F  
OUT_F  
OUT_S  
SS  
FILT  
Not to scale  
Pin Functions  
PIN  
TYPE  
DESCRIPTION  
NAME  
NO.  
EN  
2
Input  
—
Enable pin  
Filter capacitor pin. A capacitor (CFILT) ≥ 1 µF must be connected between the FILT pin and  
ground for stability.  
FILT  
4
GND_F  
GND_S  
OUT_F  
OUT_S  
7
8
6
5
Ground  
Ground  
Output  
Input  
Ground force pin  
Ground sense pin  
Output voltage force pin  
Output voltage sense pin  
Short circuit current limit pin. Connect a resistor to this pin to set the output short-circuit current  
limit. Connect to VIN pin for highest current limit  
SS  
3
1
—
VIN  
Power  
Input supply voltage pin  
Copyright © 2016, Texas Instruments Incorporated  
3
REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
www.ti.com.cn  
7 Specifications  
7.1 Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.3  
–0.3  
–55  
MAX  
6
UNIT  
V
VIN  
Input voltage  
VEN  
VIN + 0.3  
150  
V
Operating temperature, TA  
Junction temperature, Tj  
Storage temperature, Tstg  
°C  
°C  
°C  
150  
–65  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
7.2 ESD Ratings  
VALUE  
±1000  
±250  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)  
V(ESD)  
Electrostatic discharge  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Recommended Operating Conditions  
MIN  
NOM  
MAX  
5.5  
5.5  
5.5  
VIN  
4
UNIT  
V
REF6125  
3
Supply input voltage  
(IOUT = 0 mA)  
VIN  
VEN  
IL  
REF6130, REF6133, REF6141, REF6145  
REF6150  
VOUT + 0.25  
5.3  
0
Enable voltage  
V
REF6125, REF6130, REF6133, REF6141  
–4  
Output current  
REF6145  
REF6150  
–3.5  
–3  
3.5  
3
mA  
°C  
TA  
Operating temperature  
–40  
25  
125  
7.4 Thermal Information  
REF61xx  
THERMAL METRIC(1)  
DGK (VSSOP)  
8 PINS  
158.5  
51.2  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
Junction-to-board thermal resistance  
79.5  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
5.2  
ψJB  
78.0  
RθJC(bot)  
N/A  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
4
Copyright © 2016, Texas Instruments Incorporated  
REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
www.ti.com.cn  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
7.5 Electrical Characteristics  
at TA = 25°C, VIN = 5 V for all devices except REF6150, VIN = 5.4 V for REF6150, IL = 0 mA, CL = 22 µF, CFILT = 1 µF, and  
VEN = 5 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
ACCURACY AND DRIFT  
Output voltage accuracy  
-0.05%  
0.05%  
8
Output voltage temperature  
coefficient(1)  
ppm/°C  
LINE AND LOAD REGULATION  
TA = 25°C  
4
4
20  
30  
20  
REF6125 VOUT + 0.5 V ≤ VIN ≤ 5.5 V  
TA = –40°C to +125°C  
TA = 25°C  
REF6130,  
REF6133,  
ΔVO(ΔVI)  
Line regulation  
VOUT + 0.25 V ≤ VIN ≤ 5.5 V  
REF6141,  
ppm/V  
TA = –40°C to +125°C  
30  
REF6145  
TA = 25°C  
7
2
60  
120  
20  
REF6150 VOUT + 0.3 V ≤ VIN ≤ 5.5 V  
TA = –40°C to +125°C  
TA = 25°C  
REF6125,  
REF6130, IL = 0 mA to 4 mA,  
REF6133, VIN = VOUT + 600 mV  
REF6141  
TA = –40°C to +125°C  
30  
TA = 25°C  
2
2
20  
30  
20  
50  
ΔVO(ΔIL)  
Load regulation, sourcing and sinking  
ppm/mA  
IL = 0 mA to 3.5 mA,  
REF6145  
VIN = VOUT + 600 mV  
TA = –40°C to +125°C  
TA = 25°C  
IL = 0 mA to 3 mA,  
REF6150  
VIN = VOUT + 400 mV  
TA = –40°C to +125°C  
ISC  
Short-circuit current  
SS = open  
10.5  
mA  
NOISE  
CL = 22 µF  
5
5
3
Total integrated noise  
Low frequency noise  
µVRMS  
CL = 47 µF  
0.1 Hz ≤ f ≤ 10 Hz  
µVPP/V  
OUTPUT IMPEDANCE  
Output impedance  
TURN-ON TIME  
f = DC to 200 kHz, CL= 47 μF  
50  
mΩ  
ton  
Turn-on time  
0.1% settling, CL = 47 µF, SS = open, REF6125  
100  
ms  
HYSTERESIS AND LONG TERM DRIFT  
0 to 1000h at 25°C  
80  
20  
33  
8
Long term stability  
ppm  
ppm  
1000h to 2000h at 25°C  
25°C, –40°C,125°C, 25°C (cycle 1)  
25°C, –40°C,125°C, 25°C (cycle 2)  
Output voltage hysteresis(2)  
CAPACITIVE LOAD  
CL  
Stable output capacitor value  
10  
47  
µF  
(1) Temperature drift is specified according to the box method. See the Feature Description section for more details.  
(2) See the Thermal Hysteresis section.  
Copyright © 2016, Texas Instruments Incorporated  
5
 
REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
www.ti.com.cn  
Electrical Characteristics (continued)  
at TA = 25°C, VIN = 5 V for all devices except REF6150, VIN = 5.4 V for REF6150, IL = 0 mA, CL = 22 µF, CFILT = 1 µF, and  
VEN = 5 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OUTPUT VOLTAGE  
REF6125  
REF6130  
REF6133  
REF6141  
REF6145  
REF6150  
2.5  
3
3.3  
4.096  
4.5  
5
VOUT  
Output voltage  
V
POWER SUPPLY  
REF6125,  
REF6130,  
REF6133,  
REF6141  
TA = 25°C  
0.82  
0.90  
1.1  
Active mode, VEN = 5 V  
TA = –40°C to +125°C  
mA  
µA  
TA = 25°C  
0.83  
1
0.95  
1.15  
3
ICC  
Supply current  
REF6145,  
REF6150  
Active mode, VEN = 5 V  
TA = –40°C to +125°C  
TA = 25°C  
Shutdown mode, VEN = 0 V  
TA = –40°C to +125°C  
15  
Voltage reference in active mode (EN = 1)  
1.6  
Enable pin voltage  
Enable pin current  
V
Voltage reference in shutdown mode (EN = 0)  
VEN = 5 V  
0.6  
150  
500  
600  
250  
600  
250  
600  
300  
400  
100  
500  
nA  
IL = 0 mA  
REF6125  
IL = 4 mA  
IL = 0 mA  
IL = 4 mA  
IL = 0 mA  
IL = 3.5 mA  
IL = 0 mA  
IL = 3 mA  
50  
50  
REF6130, REF6133, REF6141  
REF6145  
Dropout voltage  
mV  
100  
REF6150  
6
Copyright © 2016, Texas Instruments Incorporated  
REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
www.ti.com.cn  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
7.6 Typical Characteristics  
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6125 (unless otherwise noted)  
80  
70  
60  
50  
40  
30  
20  
10  
0
80  
70  
60  
50  
40  
30  
20  
10  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Drift Distribution (ppm/ºC)  
Initial Accuracy (%)  
C002  
C003  
TA = –40°C to +125°C  
TA = –40°C to +85°C  
Figure 1. Drift Distribution  
Figure 2. Drift Distribution  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
40  
30  
20  
10  
0
C005  
C004  
Initial Accuracy (%)  
Solder Heat Shift (%)  
Figure 3. Initial Accuracy Distribution  
Figure 4. Solder-Heat Shift Distribution  
250  
200  
150  
100  
50  
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0
90°C  
125°C  
-0.01  
-0.02  
-0.03  
-0.04  
-0.05  
-0.06  
25°C  
-40°C  
0
0
1
2
3
4
œ4  
œ3  
œ2  
œ1  
0
25  
50  
75  
100  
125  
œ50  
œ25  
Load Current (mA)  
C001  
Temperature (°/)  
C017  
Figure 6. Dropout Voltage vs Load Current  
Figure 5. Output Voltage Accuracy vs Temperature  
Copyright © 2016, Texas Instruments Incorporated  
7
REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
www.ti.com.cn  
Typical Characteristics (continued)  
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6125 (unless otherwise noted)  
14  
12  
10  
8
14  
12  
10  
8
6
6
4
4
2
2
0
0
0
25  
50  
75  
100  
125  
œ50  
œ25  
0
25  
50  
75  
100  
125  
œ50  
œ25  
C006  
Temperature (ºC)  
Temperature (ºC)  
C007  
VIN = VOUT + 600 mV,  
IL = 0 mA to 4 mA  
VIN = VOUT + 600 mV,  
IL = 0 mA to 4 mA  
Figure 7. Load Regulation Sourcing vs Temperature  
Figure 8. Load Regulation Sinking vs Temperature  
8
1000  
950  
900  
850  
800  
750  
700  
650  
6
4
2
0
0
25  
50  
75  
100  
125  
0
25  
50  
75  
100  
125  
œ50  
œ25  
œ50  
œ25  
C01  
Temperature (°C)  
Temperature (ºC)  
C019  
VOUT + 0.25 V ≤ VIN ≤ 5.5 V  
Figure 9. Line Regulation vs Temperature  
Figure 10. Supply Current vs Temperature  
870  
850  
830  
810  
790  
770  
750  
EN  
2 V/div  
VREF  
Time (100 ms/div)  
2
3
4
5
6
C020  
C018  
Input Voltage (V)  
Figure 11. Supply Current vs Input Voltage  
Figure 12. Turn-On Settling Time  
8
Copyright © 2016, Texas Instruments Incorporated  
REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
www.ti.com.cn  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
Typical Characteristics (continued)  
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6125 (unless otherwise noted)  
25  
20  
15  
10  
5
10 µF  
22 µF  
47 µF  
0
Time (2 s/div)  
1k  
10k  
100k  
1000k  
C022  
C021  
Frequency (Hz)  
Figure 13. 0.1-Hz to 10-Hz Noise  
Figure 14. Output-Voltage Noise Spectrum  
30  
25  
20  
15  
10  
5
œ50  
œ60  
œ70  
CL = 47 µF  
CL = 22 µF  
10 µF  
œ80  
22 µF  
47 µF  
œ90  
œ100  
œ110  
0
100  
1k  
10k  
100k  
1M  
10  
100  
1k  
10k  
100k  
C011  
Frequency (Hz)  
Frequency (Hz)  
C025  
Graph obtained by design simulation  
Figure 15. PSRR vs Frequency  
Figure 16. Output Impedance vs Frequency  
VOUT  
VOUT  
50 mV/div  
6 mA/div  
2 mV/div  
2 mA/div  
+1 mA  
+3 mA  
-1 mA  
-3 mA  
-1 mA  
-3 mA  
Time (0.5 ms/div)  
0
5
10  
15  
C015  
C014  
Time (5 ms/div)  
Load current = ±1 mA  
Load current = ±3 mA  
Figure 18. Load Transient Response  
Figure 17. Load Transient Response  
Copyright © 2016, Texas Instruments Incorporated  
9
REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
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Typical Characteristics (continued)  
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6125 (unless otherwise noted)  
50  
VIN - 0.25 V  
VIN - 0.25 V  
40  
30  
20  
10  
0
500 mV/div  
200 µV/div  
VIN + 0.25 V  
VREF  
-80  
-60  
-40  
-20  
0
20  
40  
60  
Time (500 µs/div)  
Thermal hysteresis - Cycle 1 (ppm)  
C013  
C030  
Figure 19. Line Transient Response  
Figure 20. Thermal Hysteresis Distribution (Cycle 1)  
50  
40  
30  
20  
10  
0
100  
10  
1
REF20xx (CL = 10 µF)  
REF61xx (CL = 10 µF)  
0.1  
0.01  
0.001  
-20  
-15  
-10  
-5  
0
5
15  
20  
100  
1k  
10k  
100k  
1M  
Thermal hysteresis - Cycle 2 (ppm)  
Frequency (Hz)  
C063  
C031  
Figure 21. Thermal Hysteresis Distribution (Cycle 2)  
Figure 22. Output Impedance Comparison  
0
0
œ20  
œ20  
œ40  
œ60  
œ40  
œ60  
œ80  
œ80  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
0
100  
200  
300  
400  
500  
0
100  
200  
300  
400  
500  
C024  
Frequency (kHz)  
Frequency (kHz)  
C037  
REF6150 driving REF pin of ADS8881,  
REF6150 driving REF pin of ADS8881,  
fIN = 1 kHz, SNR = 100.5 dB, THD = –125.9 dB  
fIN = 2 kHz, SNR = 100.4 dB, THD = –123.9 dB  
Figure 23. Typical FFT Plot  
Figure 24. Typical FFT Plot  
10  
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Typical Characteristics (continued)  
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6125 (unless otherwise noted)  
0
0
œ20  
œ20  
œ40  
œ40  
œ60  
œ60  
œ80  
œ80  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
0
100  
200  
300  
400  
500  
0
100  
200  
300  
400  
500  
Frequency (kHz)  
Frequency (kHz)  
C038  
C030  
REF6150 driving REF pin of ADS8881,  
REF6141 driving REF pin of ADS8881,  
fIN = 10 kHz, SNR = 99.2 dB, THD = –119.4 dB  
fIN = 1 kHz, SNR = 99 dB, THD = –124.4 dB  
Figure 25. Typical FFT Plot  
Figure 26. Typical FFT Plot  
0
0
œ20  
œ20  
œ40  
œ40  
œ60  
œ60  
œ80  
œ80  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
0
100  
200  
300  
400  
500  
0
100  
200  
300  
400  
500  
Frequency (kHz)  
Frequency (kHz)  
C031  
C032  
REF6141 driving REF pin of ADS8881,  
REF6141 driving REF pin of ADS8881,  
fIN = 2 kHz, SNR = 99 dB, THD = –123.6 dB  
fIN = 10 kHz, SNR = 97.2 dB, THD = –119.7 dB  
Figure 27. Typical FFT Plot  
Figure 28. Typical FFT Plot  
0
œ20  
0
œ20  
œ40  
œ40  
œ60  
œ60  
œ80  
œ80  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
0
100  
200  
300  
400  
500  
0
100  
200  
300  
400  
500  
Frequency (kHz)  
Frequency (kHz)  
C033  
C034  
REF6125 driving REF pin of ADS8881,  
REF6125 driving REF pin of ADS8881,  
fIN = 1 kHz, SNR = 95.4 dB, THD = –124 dB  
fIN = 2 kHz, SNR = 95.4 dB, THD = –123.5 dB  
Figure 29. Typical FFT Plot  
Figure 30. Typical FFT Plot  
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Typical Characteristics (continued)  
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6125 (unless otherwise noted)  
0
121410  
121409  
121408  
121407  
121406  
121405  
œ20  
œ40  
œ60  
œ80  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
0
100  
200  
300  
400  
500  
0
20  
40  
60  
80  
100  
Frequency (kHz)  
Time (µs)  
C035  
C047  
REF6125 driving REF pin of ADS8881,  
REF6150 driving REF pin of ADS8881 operating at 1 MSPS,  
positive full-scale input to ADS8881  
fIN = 10 kHz, SNR = 94.0 dB, THD = –119.3 dB  
Figure 31. Typical FFT Plot  
Figure 32. Reference Droop  
œ131  
œ121334  
œ121335  
œ121336  
œ121337  
œ121338  
œ121339  
œ132  
œ133  
œ134  
œ135  
œ136  
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
Time (µs)  
Time (µs)  
C048  
C049  
REF6150 driving REF pin of ADS8881 operating at 1 MSPS,  
negative full-scale input to ADS8881  
REF6150 driving REF pin of ADS8881 operating at 1 MSPS,  
AINP = AINN = VREF / 2 for ADS8881  
Figure 33. Reference Droop  
Figure 34. Reference Droop  
40  
40  
30  
20  
10  
30  
20  
10  
0
0
ADC Output Code  
ADC Output Code  
C050  
C051  
AINP = AINN = VREF / 2 for ADS8881,  
sampling rate = 1 MSPS  
AINP = AINN = VREF / 2 for ADS8881,  
sampling rate = 500 kSPS  
Figure 35. DC Input Histogram  
Figure 36. DC Input Histogram  
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Typical Characteristics (continued)  
at TA = 25°C, IL = 0 mA, and VIN = 5 V, using REF6125 (unless otherwise noted)  
40  
30  
20  
10  
0
40  
30  
20  
10  
0
ADC Output Code  
ADC Output Code  
C052  
C053  
AINP = AINN = VREF / 2 for ADS8881,  
sampling rate = 100 kSPS  
AINP = AINN = VREF / 2 for ADS8881,  
sampling rate = 20 kSPS  
Figure 37. DC Input Histogram  
Figure 38. DC Input Histogram  
4
3
2
Regular Voltage Reference Droop  
1
0
œ1  
œ2  
œ3  
REF61xx Droop  
œ4  
0
200  
400  
600  
800  
1000  
Time (µs)  
C04  
1 LSB = 19.07 µV, with ADS8881 at 1 MSPS  
Figure 39. Reference Droop Comparison  
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8 Parameter Measurement Information  
8.1 Solder Heat Shift  
The materials used in the manufacture of the REF61xx have differing coefficients of thermal expansion, and  
result in stress on the device die when the part is heated. Mechanical and thermal stress on the device die  
sometimes causes the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow  
soldering is a common cause of this error.  
In order to illustrate this effect, a total of 128 devices were soldered on eight printed circuit boards (PCBs), with  
16 devices on each PCB, using lead-free solder paste, and the manufacturer-suggested reflow profile. The reflow  
profile is as shown in Figure 40. The printed circuit board is comprised of FR4 material. The board thickness is  
1.65 mm and the area is 101.6 mm × 127 mm.  
The reference output voltage is measured before and after the reflow process; the typical shift is displayed in  
Figure 41. Although all tested units exhibit very low shifts (< 0.03%), higher shifts are also possible depending on  
the size, thickness, and material of the PCB.  
The histogram displays the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is  
common on PCBs with surface-mount components on both sides, causes additional shifts in the output bias  
voltage. If the PCB is exposed to multiple reflows, solder the device in the final pass to minimize exposure to  
thermal stress.  
40  
30  
20  
10  
0
300  
250  
200  
150  
100  
50  
0
0
50  
100  
150  
200  
250  
300  
350  
400  
Time (seconds)  
C01  
C004  
Solder Heat Shift (%)  
Figure 40. Reflow Profile  
Figure 41. Solder Heat Shift Distribution  
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8.2 Thermal Hysteresis  
Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C,  
cycling the device through the specified temperature range, and returning to 25°C. Thermal hysteresis was  
measured with the REF61xx soldered to a PCB, similar to a real-world application. The PCB was baked at 150°C  
for 30 minutes before thermal hysteresis was measured. Thermal hysteresis is expressed as:  
≈
’
VPRE - VPOST  
VHYST  
=
ñ 106 (ppm)  
∆
∆
÷
÷
VNOM  
«
◊
where  
•
•
•
•
VHYST = thermal hysteresis (in units of ppm).  
VNOM = the specified output voltage.  
VPRE = output voltage measured at 25°C pretemperature cycling.  
VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature  
range of –40°C to 125°C and returns to 25°C.  
(1)  
Typical thermal hysteresis distribution is shown in Figure 42 and Figure 43.  
50  
40  
30  
20  
10  
0
50  
40  
30  
20  
10  
0
-80  
-60  
-40  
-20  
0
20  
40  
60  
-20  
-15  
-10  
-5  
0
5
15  
20  
Thermal hysteresis - Cycle 1 (ppm)  
Thermal hysteresis - Cycle 2 (ppm)  
C030  
C031  
Figure 42. Thermal Hysteresis Distribution (Cycle 1)  
Figure 43. Thermal Hysteresis Distribution (Cycle 2)  
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8.3 Reference Droop Measurements  
Many applications, such as event-triggered and multiplexed data-acquisition systems, require the very first  
conversion of the ADC to have 18-bit or greater precision. These types of data-acquisition systems capture data  
in bursts, and are also called burst-mode, data-acquisition systems. Achieving 18-bit precision for the first sample  
is a very difficult using a conventional voltage reference because the voltage reference droop limits the accuracy  
of the first few conversions. The REF61xx have an integrated ADC drive buffer that makes sure the reference  
droop is less than 1 LSB at 18-bit precision when used with the ADS8881, even at full throughput. Figure 44 and  
Figure 45 show the REF61xx output voltage droop when driving the REF pin of the ADS8881 at positive and  
negative full-scale inputs, respectively.  
121410  
121409  
121408  
121407  
121406  
121405  
œ121334  
œ121335  
œ121336  
œ121337  
œ121338  
œ121339  
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
Time (µs)  
Time (µs)  
C047  
C048  
REF6150 driving REF pin of ADS8881 operating at 1 MSPS,  
positive full-scale input to ADS8881  
REF6150 driving REF pin of ADS8881 operating at 1 MSPS,  
negative full-scale input to ADS8881  
Figure 44. Output Voltage Droop  
Figure 45. Output Voltage Droop  
Direct measurement of the reference droop to 18-bit accuracy can be a challenging process. Therefore, the plots  
in Figure 44 and Figure 45 were obtained by processing the output code of the ADC. The ADC output code is  
given by:  
C = (Input Voltage / VREF) × 2N  
(2)  
If the input voltage is kept constant, VREF is computed by monitoring the ADC output code C. The ADC code  
usually has six to seven LSBs of code spread due to the inherent noise of the ADC. In order to measure  
reference droop, this noise must be reduced drastically. Noise reduction is done by averaging the output code  
multiple times, as described in the next paragraph.  
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Reference Droop Measurements (continued)  
Figure 46 shows the setup that was used to measure the reference droop. The output ADC code was captured  
using a field-programmable gate array (FPGA), and post-processing was done on a personal computer. The  
input to the THS4521, and hence in turn to the ADS8881, is a constant dc voltage (close to positive or negative  
full-scale because this condition is the worst-case for charge drawn from the REF pin). The dc source must have  
extremely low noise. After the REF61xx device is powered up and stable, the FPGA sends commands to the  
ADS8881 to capture data in bursts. The ADS8881 is initially in idle mode for 100 ms. The FPGA then sends a  
command to the ADS8881 to perform 100 conversions at 1 MSPS. The ADC code corresponding to these 100  
conversions (one burst of data) is stored as the first row in a 1000 × 100 dimensional array. This operation is  
repeated 1000 times, and the data corresponding to each burst is stored in a new row of the 1000 × 100  
dimensional array. Finally, each column in this array is averaged to get a final data-set of 100 elements. This  
final data-set now has code spread that is much less than 1 LSB because most of the noise has now been  
removed through averaging. This data-set was plotted on a graph with X axis = column number (each column  
number corresponds to 1 µs of time because the sampling rate is 1 MSPS), and Y axis = ADC output code to  
obtain reference-droop measurements.  
Power Supply  
RLIM = 120 kΩ  
VIN  
SS  
OUT_S  
OUT_F  
REF61xx  
VIN  
Buffer  
RFILT  
Bandgap  
Voltage  
Reference  
EN  
+
RESR = 5 mΩ  
GND_S  
FILT  
GND_F  
CL = 47 µF  
CFILT = 1 µF  
R = 1 kΩ  
Power Supply  
R = 1 kΩ  
RF = 5 Ω  
REF  
GND  
+
AINP  
VIN  
CF = 10 nF  
THS4521  
ADS8881  
AINN  
R = 1 kΩ  
RF = 5 Ω  
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R = 1 kΩ  
Figure 46. Burst-Mode Measurement Setup  
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8.4 1/f Noise Performance  
Typical 0.1-Hz to 10-Hz voltage noise for the REF6125 is shown in Figure 47. The 1/f noise scales with output  
voltage, but remains 3 µVPP/V for all the variants. Peak-to-peak noise measurement setup is shown in Figure 48.  
Time (2 s/div)  
C021  
Figure 47. 0.1-Hz to 10-Hz Noise  
10 kꢁ  
100 ꢁ  
40 mF  
To Scope  
VIN  
EN  
OUT_F  
OUT_S  
+
Power  
Supply  
1 kꢁ  
2-Pole High-Pass  
4-Pole Low-Pass  
REF61xx  
22 ꢀF  
0.1 ꢀF  
0.1-Hz to 10-Hz Filter  
GND  
GND_F  
GND_S  
Copyright © 2016, Texas Instruments Incorporated  
Figure 48. 0.1-Hz to 10-Hz Noise Measurement Setup  
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9 Detailed Description  
9.1 Overview  
Most SAR ADCs, and a few delta-sigma ADCs, switch binary-weighted capacitors onto the REF pin during the  
conversion process. The magnitude of the capacitance switched onto the REF pin during each conversion  
depends on the input signal to the ADC. If a voltage reference is directly connected to the REF pin of these  
ADCs, the reference voltage droops because of the dynamic input signal dependent load of the binary-weighted  
capacitors. Because the reference voltage droop now has input signal dependance, significant degradation in  
THD and linearity for the system occurs.  
In order to support this dynamic load and preserve the ADC linearity, distortion and noise performance, the  
output of the voltage reference must be buffered with a low-output impedance (high-bandwidth) buffer. The  
REF61xx family of voltage references have an integrated low output impedance buffer that enables the user to  
directly drive the REF pin of a SAR ADC, while preserving ADC linearity and distortion. In addition, the total noise  
in the full bandwidth of the REF61xx is extremely low, thus preserving the noise performance of the ADC.  
Voltage-Reference Impact on Total Harmonic Distortion (SLYY097) correlates the effect of reference settling to  
ADC distortion, and how the REF61xx achieves lowest distortion with minimal components and lowest power  
consumption.  
The output voltage of the REF61xx does not droop below 1 LSB (18-bit), even during the first conversion while  
driving the REF pin of the ADS8881. This feature is useful in burst-mode, event-triggered, equivalent-time  
sampling, and variable-sampling-rate data-acquisition systems. Functional Block Diagram shows a simplified  
schematic of the REF61xx.  
9.2 Functional Block Diagram  
VIN  
SS  
OUT_S  
OUT_F  
VIN  
Buffer  
RFILT  
Bandgap  
Voltage  
Reference  
EN  
+
GND_F  
GND_S  
FILT  
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9.3 Feature Description  
9.3.1 Integrated ADC Drive Buffer  
Many ADC data sheets specify a few microamps of average current draw from the REF pin. Almost all voltage  
references provide these few microamps of average current; but not all voltage references are practical for  
driving a high-resolution, high-throughput SAR ADC because the peak current drawn can be very high when the  
capacitors are switched on the REF pin. The worst-case demand for the voltage reference is during a burst-mode  
conversion, when the ADC is idle for a very long time, before a conversion is initiated, and the first sample  
converted is expected to be precise. Usually, a large capacitor is connected between the REF pin and ground pin  
(or sometimes between the REFP and REFM pins) of the ADC to smoothen the current load and reduce the  
burden on the voltage reference. The voltage reference must then be capable of providing the average current  
required to completely charge the reference capacitor, but without causing the reference voltage to droop  
significantly. Most voltage references lack the ability to completely charge the reference capacitor, and settle  
when the binary-weighted capacitors are being switched onto the REF pin because of the large output  
impedance. Usually, voltage references have output impedances in the range of 10's of ohms at frequencies  
higher than 100 Hz. The output voltage of the voltage reference must be buffered with a low output impedance  
(usually high bandwidth) amplifier to achieve excellent linearity and distortion performance.  
The key amplifier specifications to be considered when designing a reference buffer for a high-precision ADC  
are: low offset, low drift, wide bandwidth, and low output impedance. While it is possible to select an amplifier  
that sufficiently meets all these requirements, the amplifier comes at a cost of excessive power consumption. For  
example, the OPA350 is a 38-MHz bandwidth amplifier with a maximum offset of 0.5 mV, and low offset drift of 4  
µV/ºC, but consumes a quiescent current of 5.2mA. This is because (from an amplifier design perspective) offset  
and drift are dc specifications, whereas bandwidth, low output impedance, and high capacitive drive capability  
are high-frequency specifications. Therefore, achieving all the performance in one amplifier requires power.  
However, a more efficient design to meet the low power budget is to use a composite reference buffer, which  
uses an amplifier with superior high-frequency specifications in the feedback loop of a dc precision amplifier to  
get the overall performance at much lower power consumption. Figure 49 shows such a composite amplifier  
design with the OPA333 (dc precision amplifier) and THS4281 (high-bandwidth amplifier). This reference buffer  
design requires three devices, and a large number of external components. This solution still consumes close to  
2 mA of quiescent current.  
VDD  
5-V Power Supply  
VDD  
1 kΩ  
VIN  
VOUT  
REF5045  
Temp  
+
1 kΩ  
Temp  
OPA333  
+
200 mΩ  
THS4281  
1 µF  
GND  
Trim  
1 µF  
10 µF  
1 µF  
1 µF  
To REF pin  
of ADC  
20 kΩ  
200 mΩ  
10 µF  
Copyright © 2016, Texas Instruments Incorporated  
Figure 49. Composite Amplifier Reference Buffer  
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Feature Description (continued)  
The REF61xx family of voltage references have an integrated low output impedance buffer (ADC drive buffer);  
therefore, there is no need for an external buffer while driving the REF pin of high-precision, high-throughput  
SAR ADCs, as shown in Figure 50. The ADC drive buffer of the REF61xx is capable of replenishing a charge of  
70 pC on a 47-µF capacitor in 1 µs, without allowing the voltage on the capacitor to droop more than 1 LSB at  
18-bit precision. The REF61xx are trimmed at multiple temperatures in production, achieving a max drift of just 8  
ppm/°C for both the voltage reference and the buffer combined, while operating at a typical quiescent current of  
820 µA. Figure 51 compares the output impedance of a regular voltage reference (REF20xx) and a voltage  
reference with integrated ADC drive buffer (REF61xx). Figure 52 compares the burst-mode, reference-settling  
performance of a regular voltage reference and the REF61xx.  
Power Supply  
RLIM = 120 kΩ  
VIN  
SS  
OUT_S  
OUT_F  
REF61xx  
VIN  
Buffer  
RFILT  
Bandgap  
Voltage  
Reference  
EN  
+
RESR = 5 mΩ  
GND_S  
FILT  
GND_F  
CL = 47 µF  
CFILT = 1 µF  
R = 1 kΩ  
Power Supply  
R = 1 kΩ  
RF = 5 Ω  
REF  
GND  
+
AINP  
VIN  
CF = 10 nF  
THS4521  
ADS8881  
AINN  
R = 1 kΩ  
RF = 5 Ω  
Copyright © 2016, Texas Instruments Incorporated  
R = 1 kΩ  
Figure 50. REF61xx Driving REF Pin of ADS8881 SAR ADC  
100  
10  
4
3
2
Regular Voltage Reference Droop  
REF20xx (CL = 10 µF)  
1
1
0
REF61xx (CL = 10 µF)  
0.1  
œ1  
œ2  
œ3  
œ4  
REF61xx Droop  
0.01  
0.001  
100  
1k  
10k  
100k  
1M  
0
200  
400  
600  
800  
1000  
Frequency (Hz)  
C063  
Time (µs)  
C04  
1 LSB = 19.07 µV, with ADS8881 at 1 MSPS  
Figure 51. Output Impedance Comparison  
Figure 52. Reference Droop Comparison  
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Feature Description (continued)  
9.3.2 Temperature Drift  
The REF61xx family is designed for minimal drift error, defined as the change in output voltage over temperature.  
The drift is calculated using the box method, as described by the following equation:  
VREF(MAX)-VREF(MIN)  
≈
∆
«
’
÷
◊
Drift =  
ñ106 (ppm)  
VREFñTemperature Range  
(3)  
9.3.3 Load Current  
The REF6125, REF6130, REF6133 and REF6141 are specified to deliver current load of ±4 mA. The REF6145  
is specified to deliver ±3.5 mA, and the REF6150 is specified to deliver ±3 mA. The REF61xx are protected from  
short circuits at the output by limiting the output short-circuit current.  
The short-circuit current limit (ISC) of the REF61xx family of devices is adjusted by connecting a resistor (RSS) on  
the SS pin. The short-circuit current limit when the REF61xx device is sourcing current can be calculated as  
shown in Equation 4:  
ISC = (80 *10-9 ) *RSS + (3 *10-3  
The short circuit current limit when the REF61xx device is sinking is calculated as shown in Equation 5:  
ISC = (115 *10-9 ) *RSS + (4.6 *10-3  
)
(4)  
)
(5)  
The recommended output current of the REF61xx also depends on the resistor connected to the SS pin. The  
recommended output current (sourcing and sinking) for the REF6125, REF6130, REF6133 and REF6141 is  
given by Equation 6:  
IL = (31.25 *10-9 ) *RSS + (0.25 *10-3  
The recommended output current (sourcing and sinking) for the REF6145 is given by Equation 7:  
IL = (27.08 *10-9 ) *RSS + (0.25 *10-3  
The recommended output current (sourcing and sinking) for the REF6150 is given by Equation 8:  
IL = (23.75 *10-9 ) *RSS + (0.15 *10-3  
)
(6)  
(7)  
(8)  
)
)
The temperature of the device increases according to Equation 9:  
TJ = TA +P •RꢀJA  
D
where:  
•
•
•
•
TJ = junction temperature (°C).  
TA = ambient temperature (°C).  
PD = power dissipated (W).  
RθJA = junction-to-ambient thermal resistance (°C/W).  
(9)  
The REF61xx maximum junction temperature must not exceed the absolute maximum rating of 150°C.  
22  
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Feature Description (continued)  
9.3.4 Stability  
The REF61xx family of voltage references are stable with output capacitor values ranging from 10 µF to 47 µF.  
At a low output-capacitor value of 10 µF, an effective series resistance (ESR) of 20 mΩ to 100 mΩ is required for  
stability; whereas, at a higher value of 47 µF, an ESR of 5 mΩ to 100 mΩ is required. The shaded region in  
Figure 53 shows the stable region of operation for the REF61xx devices.  
120  
100  
80  
60  
40  
20  
10  
20  
30  
40  
50  
Output Capacitor (µF)  
Figure 53. Stable Output Capacitor Range  
A capacitor of value 1 µF is required at the FILT pin for stability and noise performance. A low ESR (5 mΩ to 20  
mΩ) is easily achieved by increasing the PCB trace length, thus eliminating the need for a discrete resistor.  
Higher values of ESR (greater than 20 mΩ, but lesser than 100 mΩ) can be intentionally added to increase the  
output bandwidth of the REF61xx. This higher ESR improves the transient performance of the REF61xx, but  
worsens noise performance because of increased bandwidth.  
9.4 Device Functional Modes  
When the EN pin of the REF61xx is pulled high, the device is in active mode. The device must be in active mode  
for normal operation.  
To place the REF61xx into a shutdown mode, pull the ENABLE pin low. When in shutdown mode, the output of  
the device becomes high impedance and the quiescent current of the device reduces to 1 µA (typ). See the  
enable pin voltage parameter in the Electrical Characteristics table for logic high and logic low voltage levels.  
Copyright © 2016, Texas Instruments Incorporated  
23  
 
 
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www.ti.com.cn  
10 Applications and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
10.1 Application Information  
Many applications, such as event-triggered and multiplexed data-acquisition systems, require the very first  
conversion of the ADC to have 18-bit or greater precision. These types of data acquisition systems capture data  
in bursts, and are also called burst-mode, data-acquisition systems. Achieving 18-bit precision for the first sample  
is very difficult using a conventional voltage reference because the voltage reference droop limits the accuracy of  
the first few conversions. Furthermore, variable-sampling-rate systems require that the gain error of the system  
does not vary with sampling rate. The primary objective of this design example is to demonstrate the lowest  
distortion and noise, burst-mode data-acquisition block with low power consumption, using an 18-bit SAR ADC  
operating at a throughput of 1 MSPS, for a 1-kHz, full-scale, pure sine-wave input.  
10.2 Typical Application  
Power Supply  
RLIM = 120 kΩ  
VIN  
SS  
OUT_S  
OUT_F  
REF61xx  
VIN  
Buffer  
RFILT  
Bandgap  
Voltage  
Reference  
EN  
+
RESR = 5 mΩ  
GND_S  
FILT  
GND_F  
CL = 47 µF  
CFILT = 1 µF  
R = 1 kΩ  
Power Supply  
R = 1 kΩ  
RF = 5 Ω  
REF  
GND  
+
AINP  
VIN  
CF = 10 nF  
THS4521  
ADS8881  
AINN  
R = 1 kΩ  
RF = 5 Ω  
Copyright © 2016, Texas Instruments Incorporated  
R = 1 kΩ  
Figure 54. 18-bit, 1-MSPS, Burst-Mode Data Acquisition system  
10.2.1 Design Requirements  
1. Burst-mode support (see Reference Droop Measurements section for more details)  
2. ENOB > 16 bits  
3. THD < –120 dB  
4. Power consumption < 50 mW  
5. Throughput = 1 MSPS  
24  
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ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
Typical Application (continued)  
10.2.2 Detailed Design Procedure  
The data acquisition system shown in Figure 54 has three major contributors to the noise and accuracy in the  
system: the input driver, the reference with driver, and the data converter. Each analog block is carefully  
designed so that the data converter specifications limit the system specifications. The THS4551, a fully  
differential operational amplifier is used to drive the 18-bit ADC (ADS8881). The charge-kickback RC filter at the  
output of the THS4551 is used to reduce the charge kickback created by the opening and closing of the sampling  
switch inside the ADC. Design the RC filter so that the voltage at the sampling capacitor settles to 18-bit  
accuracy within the acquisition time of the ADC.  
Data-acquisition systems require stable and accurate voltage references in order to perform the most accurate  
data conversion. The REF61xx family of voltage references have integrated an ADC drive buffer, and can  
therefore drive the REF pin of the ADS8881 directly, without the need for an external reference buffer. See the  
Integrated ADC Drive Buffer section for more details about reference-buffer requirements. Correct output  
capacitor selection for the REF61xx is very important in this design. The Stability section describes the ESR  
requirements of the output capacitor for stability and burst-mode requirements. A capacitance of 1 μF is  
connected to the FILT pin to reduce broadband noise of the REF61xx.  
10.2.2.1 Results  
Table 1 summarizes the measured results.  
Table 1. Measured Results  
SPECIFICATION  
MEASURED RESULT  
100.5 dB  
SNR  
ENOB  
THD  
16.4  
–125.9 dB  
Throughput  
1 MSPS  
Burst mode  
First sample > 18-bit precision  
40 mW  
Power consumption  
Copyright © 2016, Texas Instruments Incorporated  
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www.ti.com.cn  
10.2.3 Application Curves  
0
œ20  
0
œ20  
œ40  
œ40  
œ60  
œ60  
œ80  
œ80  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
0
100  
200  
300  
400  
500  
0
100  
200  
300  
400  
500  
C024  
Frequency (kHz)  
Frequency (kHz)  
C037  
REF6150 driving REF pin of ADS8881,  
REF6150 driving REF pin of ADS8881,  
fIN = 1 kHz, SNR = 100.5 dB, THD = –125.9 dB  
fIN = 2 kHz, SNR = 100.4 dB, THD = –123.9 dB  
Figure 55. Typical FFT Plot  
Figure 56. Typical FFT Plot  
0
œ131  
œ20  
œ40  
œ132  
œ133  
œ134  
œ135  
œ136  
œ60  
œ80  
œ100  
œ120  
œ140  
œ160  
œ180  
œ200  
0
100  
200  
300  
400  
500  
0
20  
40  
60  
80  
100  
Frequency (kHz)  
Time (µs)  
C038  
C049  
REF6150 driving REF pin of ADS8881,  
REF6150 driving REF pin of ADS8881 operating at 1 MSPS,  
AINP = AINN = VREF / 2 for ADS8881  
fIN = 10 kHz, SNR = 99.2 dB, THD = –119.4 dB  
Figure 57. Typical FFT Plot  
Figure 58. Reference Droop  
121410  
œ121334  
121409  
121408  
121407  
121406  
121405  
œ121335  
œ121336  
œ121337  
œ121338  
œ121339  
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
Time (µs)  
Time (µs)  
C047  
C048  
REF6150 driving REF pin of ADS8881 operating at 1 MSPS,  
positive full-scale input to ADS8881  
REF6150 driving REF pin of ADS8881 operating at 1 MSPS,  
negative full-scale input to ADS8881  
Figure 59. Reference Droop  
Figure 60. Reference Droop  
26  
Copyright © 2016, Texas Instruments Incorporated  
REF6125, REF6130, REF6133, REF6141, REF6145, REF6150  
www.ti.com.cn  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
11 Power Supply Recommendations  
The REF61xx family of references have extremely low dropout voltage. The dropout specifications can be found  
in the Electrical Characteristics section. A minimum 0.1 µF decoupling capacitor must be connected between the  
VIN and GND_F pins of the REF61xx. A typical dropout voltage versus load is shown in Figure 61.  
250  
90°C  
200  
125°C  
150  
100  
25°C  
50  
-40°C  
0
0
1
2
3
4
œ4  
œ3  
œ2  
œ1  
Load Current (mA)  
C017  
Figure 61. Dropout Voltage vs Load Current  
Copyright © 2016, Texas Instruments Incorporated  
27  
 
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12 Layout  
12.1 Layout Guidelines  
Figure 62 illustrates an example of a PCB layout for a data-acquisition system using the REF61xx. Some key  
considerations are:  
•
•
•
•
Connect low-ESR, 0.1-μF ceramic bypass capacitors between the VIN pin and ground.  
Place the REF61xx output capacitor (CL) and the ADC as close to each other as possible.  
Run two separate traces between VOUT_F, VOUT_S and the output capacitor, as shown in Figure 62.  
Short the GND_F and GND_S pins with a solid plane, and extend this plane to connect to the output  
capacitor CL, as shown in Figure 62.  
•
•
Use a solid ground plane to help distribute heat and reduces electromagnetic interference (EMI) noise pickup.  
Place the external components as close to the device as possible. This configuration prevents parasitic errors  
(such as the Seebeck effect) from occurring.  
•
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if  
possible, and only make perpendicular crossings when absolutely necessary.  
12.2 Layout Example  
CIN  
RESR  
AGND  
ADC  
VIN  
EN  
REFM  
REFP  
REF61xx  
VOUT  
RSS  
CL  
Copyright © 2016, Texas Instruments Incorporated  
AGND  
CFILT  
Figure 62. Layout Example  
28  
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www.ti.com.cn  
ZHCSF42B –MAY 2016–REVISED AUGUST 2016  
13 器件和文档支持  
13.1 文档支持  
13.1.1 相关文档ꢀ  
相关文档如下：  
•
《ADS8881x 18 位、1MSPS、串行接口、微功耗、微型、真正的差分输入、SAR 模数转换器数据表》（文献  
编号：SBAS547）  
•
•
•
《ADS127L01 24 位、高速、高带宽模数转换器数据表》（文献编号：SBAS607）  
《REF6025EVM-PDK 用户指南》（文献编号：SBAU258）  
《电压基准对总谐波失真的影响》（文献编号：SLYY097)  
13.2 相关链接  
下面的表格中列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或  
购买链接。  
表 2. 相关链接  
器件  
产品文件夹  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
样片与购买  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
技术文档  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
工具与软件  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
支持与社区  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
请单击此处  
REF6125  
REF6130  
REF6133  
REF6141  
REF6145  
REF6150  
13.3 接收文档更新通知  
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册  
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。  
13.4 社区资源  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
13.5 商标  
E2E is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
13.6 静电放电警告  
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可  
能会损坏集成电路。  
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可  
能会导致器件与其发布的规格不相符。  
13.7 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
版权 © 2016, Texas Instruments Incorporated  
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14 机械、封装和可订购信息  
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对  
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。  
30  
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只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面  
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有  
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TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要  
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IMPORTANT NOTICE  
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122  
Copyright © 2016, 德州仪器半导体技术（上海）有限公司  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
REF6125IDGKR  
REF6125IDGKT  
REF6130IDGKR  
REF6130IDGKT  
REF6133IDGKR  
REF6133IDGKT  
REF6141IDGKR  
REF6141IDGKT  
REF6145IDGKR  
REF6145IDGKT  
REF6150IDGKR  
REF6150IDGKT  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
8
8
8
8
8
8
8
8
8
8
8
8
2500 RoHS & Green  
250 RoHS & Green  
2500 RoHS & Green  
250 RoHS & Green  
2500 RoHS & Green  
250 RoHS & Green  
2500 RoHS & Green  
250 RoHS & Green  
2500 RoHS & Green  
250 RoHS & Green  
2500 RoHS & Green  
250 RoHS & Green  
NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
14AV  
14AV  
14BV  
14BV  
14CV  
14CV  
14DV  
14DV  
14EV  
14EV  
14FV  
14FV  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2018  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
REF6125IDGKR  
REF6125IDGKT  
REF6130IDGKR  
REF6130IDGKT  
REF6133IDGKR  
REF6133IDGKT  
REF6141IDGKR  
REF6141IDGKT  
REF6145IDGKR  
REF6145IDGKT  
REF6150IDGKR  
REF6150IDGKT  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
8
8
8
8
8
8
8
8
8
8
8
8
2500  
250  
330.0  
177.8  
330.0  
177.8  
330.0  
177.8  
330.0  
177.8  
330.0  
177.8  
330.0  
177.8  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
5.3  
5.3  
5.3  
5.3  
5.3  
5.3  
5.3  
5.3  
5.3  
5.3  
5.3  
5.3  
3.4  
3.4  
3.4  
3.4  
3.4  
3.4  
3.4  
3.4  
3.4  
3.4  
3.4  
3.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
2500  
250  
2500  
250  
2500  
250  
2500  
250  
2500  
250  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2018  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
REF6125IDGKR  
REF6125IDGKT  
REF6130IDGKR  
REF6130IDGKT  
REF6133IDGKR  
REF6133IDGKT  
REF6141IDGKR  
REF6141IDGKT  
REF6145IDGKR  
REF6145IDGKT  
REF6150IDGKR  
REF6150IDGKT  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
DGK  
8
8
8
8
8
8
8
8
8
8
8
8
2500  
250  
346.0  
223.0  
346.0  
223.0  
346.0  
223.0  
346.0  
223.0  
346.0  
223.0  
346.0  
223.0  
346.0  
270.0  
346.0  
270.0  
346.0  
270.0  
346.0  
270.0  
346.0  
270.0  
346.0  
270.0  
29.0  
35.0  
29.0  
35.0  
29.0  
35.0  
29.0  
35.0  
29.0  
35.0  
29.0  
35.0  
2500  
250  
2500  
250  
2500  
250  
2500  
250  
2500  
250  
Pack Materials-Page 2  
重要声明和免责声明  
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资  
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示  
担保。  
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、  
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用  
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权  
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。  
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约  
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE  
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122  
Copyright © 2020 德州仪器半导体技术（上海）有限公司  

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