RM42L432PZT_技术文档

RM42L432

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SPNS180A –SEPTEMBER 2012–REVISED SEPTEMBER 2013

RM42L432 16- and 32-Bit RISC Flash Microcontroller

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1 RM42L432 16- and 32-Bit RISC Flash Microcontroller

1.1 Features

1

• High-Performance Microcontroller for Safety-

Critical Applications

• Multiple Communication Interfaces

– Two CAN Controllers (DCANs)

– Dual CPUs Running in Lockstep

– ECC on Flash and RAM Interfaces

– Built-In Self-Test for CPU and On-Chip RAMs

– Error Signaling Module with Error Pin

– Voltage and Clock Monitoring

•

DCAN1 - 32 Mailboxes with Parity

Protection

DCAN2 - 16 Mailboxes with Parity

Protection

Compliant to CAN Protocol Version 2.0B

– Multibuffered Serial Peripheral Interface

(MibSPI) Module

• ARM® Cortex™ – R4 32-Bit RISC CPU

– Efficient 1.66 DMIPS/MHz with 8-Stage

Pipeline

•

128 Words with Parity Protection

– Two Standard Serial Peripheral Interface

(SPI) Modules

– UART (SCI) Interface with Local Interconnect

Network (LIN 2.1) Interface Support

– 8-Region Memory Protection Unit

– Open Architecture with Third-Party Support

• Operating Conditions

– 100-MHz System Clock

• High-End Timer (N2HET) Module

– Up to 19 Programmable Pins

– Core Supply Voltage (V_CC): 1.2-V Nominal

– I/O Supply Voltage (V_CCIO): 3.3-V Nominal

– ADC Supply Voltage (V_CCAD): 3.3-V Nominal

• Integrated Memory

– 128-Word Instruction RAM with Parity

Protection

– Each Includes Hardware Angle Generator

– Dedicated High-End Timer Transfer Unit

(HTU)

– 384KB of Program Flash with ECC

– 32KB of RAM with ECC

– 16KB of Flash for Emulated EEPROM with

ECC

• Enhanced Quadrature Encoder Pulse (eQEP)

Module

– Motor Position Encoder Interface

• 12-Bit Multibuffered Analog-to-Digital Converter

(ADC) Module

• Common Platform Architecture

– Consistent Memory Map Across Family

– Real-Time Interrupt (RTI) Timer (OS Timer)

– 96-Channel Vectored Interrupt Module (VIM)

– 16 Channels

– 2-Channel Cyclic Redundancy Checker

(CRC)

• Frequency-Modulated Phase-Locked Loop

(FMPLL) with Built-In Slip Detector

• IEEE 1149.1 JTAG, Boundary Scan and ARM

CoreSight™ Components

• Advanced JTAG Security Module (AJSM)

– 64 Result Buffers with Parity Protection

• Up to 45 General-Purpose I/O (GPIO) Capable

Pins

– 8 Dedicated GPIO Pins with up to 8 External

Interrupts

• Package

– 100-Pin Quad Flatpack (PZ) [Green]

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

RM42L432

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1.2 Applications

•

Industrial Safety Applications

–

Industrial Automation

Safe Programmable Logic Controllers (PLCs)

Power Generation and Distribution

Turbines and Windmills

Elevators and Escalators

•

Medical Applications

–

Ventilators

Defibrillators

Infusion and Insulin Pumps

Radiation Therapy

Robotic Surgery

2

RM42L432 16- and 32-Bit RISC Flash Microcontroller

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1.3 Description

The RM42L432 device is a high-performance microcontroller for safety systems. The safety architecture

includes dual CPUs in lockstep, CPU and Memory Built-In Self Test (BIST) logic, ECC on both the flash

and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.

The RM42L432 device integrates the ARM Cortex-R4 CPU which offers an efficient 1.66 DMIPS/MHz, and

can run up to 100 MHz providing up to 166 DMIPS. The device supports little-endian [LE] format.

The RM42L432 device has 384KB integrated flash and 32-KB data RAM with single-bit error correction

and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and

programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V

supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline

mode, the flash operates with a system clock frequency of up to 100 MHz. The SRAM supports single-

cycle read and write accesses in byte, halfword, and word modes throughout the supported frequency

range.

The RM42L432 device features peripherals for real-time control-based applications, including a Next

Generation High-End Timer (N2HET) timing coprocessor with up to 19 total I/O terminals and a 12-bit

Analog-to-Digital Converter (ADC) supporting 16 inputs in the 100-pin package.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,

capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring

multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer

Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory.

A Memory Protection Unit (MPU) is built into the HTU.

The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with a linear or rotary

incremental encoder to get position, direction, and speed information from a rotating machine as used in

high-performance motion and position-control systems.

The device has a 12-bit-resolution MibADC with 16 channels and 64 words of parity-protected buffer RAM.

The MibADC channels can be converted individually or can be grouped by software for sequential

conversion sequences. There are three separate groups. Each group can be converted once when

triggered or configured for continuous conversion mode.

The device has multiple communication interfaces: one MibSPI, two SPIs, one UART/LIN, and two

DCANs. The SPI provides a convenient method of serial interaction for high-speed communications

between similar shift-register type devices. The UART/LIN supports the Local Interconnect standard 2.1

and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format.

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication

protocol that efficiently supports distributed real-time control with robust communication rates of up to 1

Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example,

automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

The frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the external

frequency reference to a higher frequency for internal use. The FMPLL provides one of the five possible

clock source inputs to the global clock module (GCM). The GCM manages the mapping between the

available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) module. When the ECP is enabled, it outputs a

continuous external clock on the ECLK pin. The ECLK frequency is a user-programmable ratio of the

peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an

indicator of the operating frequency of the device.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or

external Error pin is triggered when a fault is detected. The nERROR can be monitored externally as an

indicator of a fault condition in the microcontroller.

RM42L432 16- and 32-Bit RISC Flash Microcontroller

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With integrated safety features and a wide choice of communication and control peripherals, the

RM42L432 device is an ideal solution for real-time control applications with safety-critical requirements.

4

RM42L432 16- and 32-Bit RISC Flash Microcontroller

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1.4 Functional Block Diagram

nTRST

TMS

DAP

with

ICEPick

TCK

AJSM

RTCK

TDI

CCM-R4

Debug

Gasket

TDO

N2HET

128 Words

with Parity

V_CCP1

FLTP1

FLTP2

N2HET[31:28, 26, 24:22, 20:16,

14, 12, 10, 8, 6, 4, 2, 0]

Flash

384kB

with ECC

Cortex-R4

Corte^wx-^itR^{h M}4^PU

with MPU

8 regions

nRST

nPORRST

TEST

ECLK

8 regions

SYS

RAM

32kB

with ECC

GIOA[7:0]/INT[7:0]

GIO

LIN

STC

LBIST

LINRX

LINTX

HTU

2 Regions

8 DCP

with MPU

MiBSPI1

8 Transfer

Groups

MIBSPI1SIMO

MIBSPI1SOMI

MIBSPI1CLK

MIBSPI1nCS[3:0]

MIBSPI1nENA

128 Buffers

with Parity

BRIDGE

SPI2SIMO

SPI2SOMI

SPI2CLK

SPI2

SPI2nCS[0]

SCR

SPI3SIMO

SPI3SOMI

SPI3CLK

SPI3nCS[3:0]

SPI3nENA

SPI3

Peripheral

Bridge

16kB

Flash for

EEPROM

w/ECC

CRC

R4

2 Channel Slave I/F

DCAN1

32 Messages

with Parity

PCR

CAN1RX

CAN1TX

OSCIN

OSC

PLL

Clock

Monitor

DCAN2

16 Messages

with Parity

OSCOUT

Kelvin_GND

V_CCPLL

CAN2RX

CAN2TX

RTI

V_SSPLL

ADIN[21, 20, 17, 16, 11:0]

ADEVT

V_CCAD/A_DREFH

V_SSAD/A_DREFLO

VIM

96 Channel

with Parity

MiBADC

64 Words

with Parity

nERROR

ESM

eQEP

IOMM

DCC

Figure 1-1. Functional Block Diagram

RM42L432 16- and 32-Bit RISC Flash Microcontroller

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1

RM42L432 16- and 32-Bit RISC Flash

Microcontroller .......................................... 1

1.1 Features ............................................. 1

1.2 Applications .......................................... 2

1.3 Description ........................................... 3

1.4 Functional Block Diagram ........................... 5

4.8 Device Memory Map ................................ 41

4.9 Flash Memory ...................................... 46

4.10 Flash Program and Erase Timings for Program

Flash ................................................ 48

4.11 Flash Program and Erase Timings for Data Flash . 48

4.12 Tightly-Coupled RAM Interface Module ............ 49

4.13 Parity Protection for Accesses to peripheral RAMs 49

4.14 On-Chip SRAM Initialization and Testing ........... 51

4.15 Vectored Interrupt Manager ........................ 53

4.16 Real Time Interrupt Module ........................ 55

4.17 Error Signaling Module ............................. 57

4.18 Reset / Abort / Error Sources ...................... 61

4.19 Digital Windowed Watchdog ....................... 62

4.20 Debug Subsystem .................................. 63

Revision History .............................................. 7

2

Device Package and Terminal Functions .......... 8

2.1 PZ QFP Package Pinout (100-Pin) .................. 8

2.2 Terminal Functions ................................... 9

2.3 Output Multiplexing and Control .................... 16

2.4 Special Multiplexed Options ........................ 17

Device Operating Conditions ....................... 18

3

3.1

Absolute Maximum Ratings Over Operating Free-

Air Temperature Range, ............................ 18

5

Peripheral Information and Electrical

3.2

3.3

Device Recommended Operating Conditions ...... 18

Specifications .......................................... 67

Switching Characteristics over Recommended

5.1 Peripheral Legend .................................. 67

Operating Conditions for Clock Domains .......... 19

5.2

Multi-Buffered 12-bit Analog-to-Digital Converter .. 67

3.4 Wait States Required ............................... 19

5.3 General-Purpose Input/Output ..................... 75

5.4 Enhanced High-End Timer (N2HET) ............... 76

5.5 Controller Area Network (DCAN) ................... 79

3.5

Power Consumption Over Recommended

Operating Conditions ............................... 20

Input/Output Electrical Characteristics Over

3.6

5.6

Local Interconnect Network Interface (LIN) ........ 80

Multi-Buffered / Standard Serial Peripheral Interface

...................................................... 81

Recommended Operating Conditions .............. 21

5.7

3.7 Output Buffer Drive Strengths ...................... 21

3.8 Input Timings ....................................... 22

3.9 Output Timings ..................................... 22

5.8 Enhanced Quadrature Encoder (eQEP) ............ 91

6

7

Device and Documentation Support ............... 93

4

System Information and Electrical Specifications

6.1

Device and Development-Support Tool

............................................................. 24

Nomenclature ....................................... 93

4.1 Voltage Monitor Characteristics .................... 24

6.2 Device Identification ................................ 93

6.3 Community Resources ............................. 95

6.4 Module Certifications ............................... 95

Mechanical Data ...................................... 100

7.1 Thermal Data ...................................... 100

7.2 Packaging Information ............................ 100

4.2

Power Sequencing and Power On Reset .......... 25

4.3 Warm Reset (nRST) ................................ 27

4.4 ARM^©Cortex-R4™ CPU Information .............. 28

4.5 Clocks .............................................. 31

4.6 Clock Monitoring .................................... 38

4.7 Glitch Filters ........................................ 40

6

Contents

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Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the initial revision of the

device-specific data manual to make it an A revision.

Document Revision History

Section

Change

From

To

Section 3.1

Section 3.2

Increased absolute max voltage V_CCIOand Input Voltage

Added maximum 3.3V supply voltage slew rate

4.1 V

4.6 V

1 V/µs

Added table of control bits for programmable 8 mA / 2 mA

buffers

Table 3-3

Section 3.4

Section 3.3

Revised wait state requirements

Added that after reset, flash bank 7 reads have two data wait-

states

15 mA, 34 mA, 15

mA,

Section 3.5

Combined I_CCIO, I_CCPand I_CCAD

45 mA

Section 3.5

Section 3.6

Added derating factors for Icc current

V_OH, I_OH= 50 µA, standard output mode

Input clamp current

V_CCIO-0.2

-2 mA

V_CCIO-0.3

-3.5 mA

3.5 mA

Input clamp current

2 mA

Added table note warning not to do byte or halfword writes to

SPI2PC9[32.16]

Table 3-3

Table 4-21

Table 4-1

Table 4-6

Table 5-5

Corrected size of bank 7 and programming times

Vmon Vcc high

64KB

1.0 V

16KB

1.13 V

Corrected nRST timings

8 t_c(VCLK)

32 t_c(VCLK)

Updated ADC leakage table

Section 5.7.4

Section 5.7.5

Updated SPI timings

Table 6-2

Updated Die-ID register

Section 6.4

Added section for module certifications

Contents

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2 Device Package and Terminal Functions

2.1 PZ QFP Package Pinout (100-Pin)

50

49

ADIN[10]

ADIN[1]

ADIN[9]

76

nTRST

77

TDI

48

47

78

TDO

VSSAD/ADREFLO

VCCAD/ADREFHI

ADIN[21]

79

TCK

RTCK

46

45

80

81

nRST

44

ADIN[20]

ADIN[7]

82

nERROR

N2HET[10]

43

42

83

ADIN[0]

84

ECLK

VCCIO

VSS

41

40

39

ADIN[17]

85

86

87

ADIN[16]

MIBSPI1nCS[3]

SPI3nCS[0]

VSS

38

37

36

35

34

33

32

31

30

29

28

27

26

VCC

88

89

90

91

92

93

94

95

96

97

98

99

100

SPI3nENA

SPI3CLK

N2HET[12]

N2HET[14]

CAN2TX

SPI3SIMO

SPI3SOMI

CAN2RX

MIBSPI1nCS[1]

VSS

VCC

LINRX

LINTX

nPORRST

VCC

VCCP

VSS

N2HET[16]

N2HET[18]

VCC

VCCIO

MIBSPI1nCS[2]

N2HET[6]

VSS

Figure 2-1. PZ QFP Package Pinout (100-Pin)

Note: Pins can have multiplexed functions. Only the default function is depicted in above diagram.

8

Device Package and Terminal Functions

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2.2 Terminal Functions

The following table identifies the external signal names, the associated pin numbers along with the

mechanical package designator, the pin type (Input, Output, IO, Power or Ground), whether the pin has

any internal pullup/pulldown, whether the pin can be configured as a GIO, and a functional pin description.

NOTE

All I/O signals except nRST are configured as inputs while nPORRST is low and immediately

after nPORRST goes High.

All output-only signals are configured as inputs while nPORRST is low, and are configured

as outputs immediately after nPORRST goes High.

While nPORRST is low, the input buffers are disabled, and the output buffers are tri-stated.

NOTE

In the Terminal Functions table below, the "Default Pull State" is the state of the pullup or

pulldown while nPORRST is low and immediately after nPORRST goes High. The default

pull direction may change when software configures the pin for an alternate function. The

"Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given

terminal.

Device Package and Terminal Functions

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2.2.1 High-End Timer (N2HET)

Table 2-1. High-End Timer (N2HET)

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

N2HET[0]

N2HET[2]

N2HET[4]

N2HET[6]

N2HET[8]

N2HET[10]

N2HET[12]

N2HET[14]

N2HET[16]

19

22

25

26

74

83

89

90

97

93

I/O

Pull Down

Programmable,

20uA

Timer input capture or output compare. The

N2HET applicable terminals can be programmed

as general-purpose input/output (GIO).

Each N2HET terminal is equipped with a

suppression filter. If the terminal is configured as

an input it enables to filter out pulses which are

smaller than a programmable duration.

MIBSPI1nCS[1]/EQEPS/

N2HET[17]

N2HET[18]

98

27

MIBSPI1nCS[2]/N2HET[20]/

N2HET[19]

MIBSPI1nCS[2]/N2HET[20]/

27

N2HET[19]

N2HET[22]

11

64

39

58

18

68

N2HET[24]

MIBSPI1nCS[3]/N2HET[26]

ADEVT/N2HET[28]

GIOA[7]/N2HET[29]

MIBSPI1nENA/N2HET[23]/

N2HET[30]

GIOA[6]/SPI2nCS[1]/N2HET[31]

12

2.2.2 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 2-2. PGE Enhanced Quadrature Encoder Pulse Modules (eQEP)

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

SPI3CLK/EQEPA

SPI3nENA/EQEPB

SPI3nCS[0]/EQEPI

36

37

38

93

Input

I/O

Pullup

Fixed, 20uA

Enhanced QEP Input A

Enhanced QEP Input B

Enhanced QEP Index

Enhanced QEP Strobe

MIBSPI1nCS[1]/EQEPS/N2HET

I/O

[17]

10

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2.2.3 General-Purpose Input/Output (GIO)

Table 2-3. General-Purpose Input/Output (GIO)

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

GIOA[0]/SPI3nCS[3]

GIOA[1]/SPI3nCS[2]

GIOA[2]/SPI3nCS[1]

GIOA[3]/SPI2nCS[3]

GIOA[4]/SPI2nCS[2]

GIOA[5]/EXTCLKIN

1

2

I/O

Pull Down

Programmable,

20uA

General-purpose input/output

All GPIO terminals are capable of generating

interrupts to the CPU on rising/falling/both edges.

5

8

9

10

12

18

GIOA[6]/SPI2nCS[1]/N2HET[31]

GIOA[7]/N2HET[29]

2.2.4 Controller Area Network Interface Modules (DCAN1, DCAN2)

Table 2-4. Controller Area Network Interface Modules (DCAN1, DCAN2)

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

CAN1RX

CAN1TX

CAN2RX

CAN2TX

63

62

92

91

I/O

Pull Up

Programmable,

20uA

CAN1 Receive, or general-purpose I/O (GPIO)

CAN1 Transmit, or GPIO

CAN2 Receive, or GPIO

CAN2 Transmit, or GPIO

2.2.5 Multi-Buffered Serial Peripheral Interface (MibSPI1)

Table 2-5. Multi-Buffered Serial Peripheral Interface (MibSPI1)

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

MIBSPI1CLK

67

73

93

I/O

Pull Up

Programmable,

20uA

MibSPI1 Serial Clock, or GPIO

MibSPI1 Chip Select, or GPIO

MIBSPI1nCS[0]

MIBSPI1nCS[1]/EQEPS/N2HET

[17]

MIBSPI1nCS[2]/N2HET[20]/N2

27

HET[19]

MIBSPI1nCS[3]/N2HET[26]

39

68

MIBSPI1nENA/N2HET[23]/N2H

MibSPI1 Enable, or GPIO

ET[30]

MIBSPI1SIMO

MIBSPI1SOMI

65

66

MibSPI1 Slave-In-Master-Out, or GPIO

MibSPI1 Slave-Out-Master-In, or GPIO

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2.2.6 Standard Serial Peripheral Interface (SPI2)

Table 2-6. Standard Serial Peripheral Interface (SPI2)

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

SPI2CLK

71

23

12

9

I/O

Pull Up

Programmable,

20uA

SPI2 Serial Clock, or GPIO

SPI2 Chip Select, or GPIO

SPI2nCS[0]

GIOA[6]/SPI2nCS[1]/N2HET[31]

GIOA[4]/SPI2nCS[2]

GIOA[3]/SPI2nCS[3]

SPI2SIMO

8

70

69

SPI2 Slave-In-Master-Out, or GPIO

SPI2 Slave-Out-Master-In, or GPIO

SPI2SOMI

The drive strengths for the SPI2CLK, SPI2SIMO and SPI2SOMI signals are selected individually by configuring the respective SRS bits of

the SPIPC9 register fo SPI2.

SRS = 0 for 8mA drive (fast). This is the default mode as the SRS bits in the SPIPC9 register default to 0.

SRS = 1 for 2mA drive (slow)

SPI3CLK/EQEPA

SPI3nCS[0]/EQEPI

GIOA[2]/SPI3nCS[1]

GIOA[1]/SPI3nCS[2]

GIOA[0]/SPI3nCS[3]

SPI3nENA/EQEPB

SPI3SIMO

36

38

5

I/O

Pull Up

Programmable,

20uA

SPI3 Serial Clock, or GPIO

SPI3 Chip Select, or GPIO

2

1

37

35

34

SPI3 Enable, or GPIO

SPI3 Slave-In-Master-Out, or GPIO

SPI3 Slave-Out-Master-In, or GPIO

SPI3SOMI

2.2.7 Local Interconnect Network Controller (LIN)

Table 2-7. Local Interconnect Network Controller (LIN)

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

LINRX

LINTX

94

95

I/O

Pull Up

Programmable,

20uA

LIN Receive, or GPIO

LIN Transmit, or GPIO

2.2.8 Multi-Buffered Analog-to-Digital Converter (MibADC)

Table 2-8. Multi-Buffered Analog-to-Digital Converter (MibADC)

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

ADEVT/N2HET[28]

58

I/O

Pull Up

Programmable,

20uA

ADC Event Trigger or GPIO

12

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Table 2-8. Multi-Buffered Analog-to-Digital Converter (MibADC) (continued)

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

ADIN[0]

42

49

51

52

54

55

56

43

57

48

50

53

40

41

44

45

46

Input

-

Analog Inputs

ADIN[1]

ADIN[2]

ADIN[3]

ADIN[4]

ADIN[5]

ADIN[6]

ADIN[7]

ADIN[8]

ADIN[9]

ADIN[10]

ADIN[11]

ADIN[16]

ADIN[17]

ADIN[20]

ADIN[21]

ADREFHI/VCCAD

Input/Pow

er

-

ADC High Reference Level/ADC Operating

Supply

ADREFLO/VSSAD

47

Input/Grou

nd

ADC Low Reference Level/ADC Supply Ground

2.2.9 System Module

Table 2-9. System Module

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

ECLK

84

I/O

Pull Down

Programmable,

20uA

External prescaled clock output, or GIO.

External Clock In

GIOA[5]/EXTCLKIN

10

31

Input

Pull Down

20uA

nPORRST

100uA

Power-on reset, cold reset External power supply

monitor circuitry must drive nPORRST low when

any of the supplies to the microcontroller fall out

of the specified range. This terminal has a glitch

filter.

nRST

81

I/O

Pull Up

100uA

The external circuitry can assert a system reset

by driving nRST low. To ensure that an external

reset is not arbitrarily generated, TI recommends

that an external pull-up resistor is connected to

this terminal. This terminal has a glitch filter.

2.2.10 Error Signaling Module (ESM)

Table 2-10. Error Signaling Module (ESM)

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

nERROR

82

I/O

Pull Down

20uA

ESM Error Signal. Indicates error of high severity.

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2.2.11 Main Oscillator

Table 2-11. Main Oscillator

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

OSCIN

14

Input

-

From external crystal/resonator, or external clock

input

OSCOUT

16

15

Output

Input

-

To external crystal/resonator

Dedicated ground for oscillator

KELVIN_GND

2.2.12 Test/Debug Interface

Table 2-12. Test/Debug Interface

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

nTRST

RTCK

TCK

76

80

79

77

78

75

24

Input

Output

Input

I/O

Pull Down

-

Fixed, 100uA

-

JTAG test hardware reset

JTAG return test clock

JTAG test clock

Pull Down

Pull Up

Pull Down

Pull Up

Pull Down

Fixed, 100uA

TDI

JTAG test data in

TDO

I/O

JTAG test data out

JTAG test select

TMS

I/O

TEST

I/O

Test enable. Reserved for internal use only. This

terminal has a glitch filter.

For proper operation, this terminal must be

connected to ground using an external resistor.

2.2.13 Flash

Table 2-13. Flash

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

FLTP1

FLTP2

3

4

Input

-

Flash Test Pins. For proper operation this

terminal must connect only to a test pad or not be

connected at all [no connect (NC)].

The test pad must not be exposed in the final

product where it might be subjected to an ESD

event.

VCCP

96

3.3V

Power

-

Flash external pump voltage (3.3 V). This

terminal is required for both Flash read and Flash

program and erase operations.

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2.2.14 Core Supply

Table 2-14. Core Supply

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

VCC

13

21

30

32

61

88

99

1.2V

Power

-

Digital logic and RAM supply

2.2.15 I/O Supply

Table 2-15. I/O Supply

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

VCCIO

6

3.3V

Power

-

I/O Supply

28

60

85

2.2.16 Core and I/O Supply Ground Reference

Table 2-16. Core and I/O Supply Ground Reference

Terminal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

100

PZ

VSS

7

17

20

29

33

59

72

86

87

100

Ground

-

Device Ground Reference. This is a single

ground reference for all supplies except for the

ADC Supply.

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2.3 Output Multiplexing and Control

Output multiplexing will be utilized in the device. The multiplexing is utilized to allow development of

additional package/feature combinations as well as to maintain pinout compatibility with the marketing

device family.

In all cases indicated as multiplexed, the output buffers are multiplexed.

Table 2-17. Output Mux Options

100PZ Pin

Default Function

GIOA[0]

Control 1

Option2

SPI3nCS[3]

SPI3nCS[2]

SPI3nCS[1]

SPI2nCS[3]

SPI2nCS[2]

EXTCLKIN

SPI2nCS[1]

N2HET[29]

EQEPS

Control 2

Option 3

Control 3

1

PINMMR0[8]

PINMMR1[0]

PINMMR1[8]

PINMMR1[16]

PINMMR1[24]

PINMMR2[0]

PINMMR2[8]

PINMMR2[16]

PINMMR6[8]

PINMMR3[0]

PINMMR4[8]

PINMMR5[8]

PINMMR3[16]

PINMMR4[0]

PINMMR3[24]

PINMMR4[16]

PINMMR0[9]

PINMMR1[1]

PINMMR1[9]

PINMMR1[17]

PINMMR1[25]

PINMMR2[1]

PINMMR2[9]

PINMMR2[17]

PINMMR6[9]

PINMMR3[1]

PINMMR4[9]

PINMMR5[9]

PINMMR3[17]

PINMMR4[1]

PINMMR3[25]

PINMMR4[17]

-

2

GIOA[1]

-

5

GIOA[2]

-

8

GIOA[3]

-

9

GIOA[4]

-

10

12

18

93

27

39

68

36

38

37

58

GIOA[5]

-

GIOA[6]

N2HET[31]

PINMMR2[10]

GIOA[7]

-

MIBSPI1nCS[1]

MIBSPI1nCS[2]

MIBSPI1nCS[3]

MIBSPI1nENA

SPI3CLK

N2HET[17]

PINMMR6[10]

N2HET[20]

N2HET[26]

N2HET[23]

EQEPA

N2HET[19]

PINMMR3[2]

-

N2HET[30]

PINMMR5[10]

-

SPI3nCS[0]

SPI3nENA

ADEVT

EQEPI

EQEPB

N2HET[28]

2.3.1 Notes on Output Multiplexing

Table 2-17 shows the output signal multiplexing and control signals for selecting the desired functionality

for each pin.

•

The pins default to the signal defined by the "Default Function" column in Table 2-17

The "CTRL x" columns indicate the multiplexing control register and the bit that must be set in order to

select the corresponding functionality to be output on any particular pin.

For example, consider the multiplexing on pin 18, shown below.

Table 2-18. Muxing Example

100PZ Pin

Default Function

Control 1

Option2

Control 2

Option 3

Control 3

18

GIOA[7]

PINMMR2[16]

N2HET[29]

PINMMR2[17]

-

•

When GIOA[7] is configured as an output pin in the GIO module control register, then the programmed

output level appears on pin 18 by default. The PINMMR2[16] bit is set by default to indicate that the

GIOA[7] signal is selected to be output.

•

If the application needs to output the N2HET[29] signal on pin 18, it must clear PINMMR2[16] and set

PINMMR2[17].

Note that the pin is connected as input to both the GIO and N2HET modules. That is, there is no input

multiplexing on this pin.

2.3.2 General Rules for Multiplexing Control Registers

•

The PINMMR control registers can only be written in privileged mode. A write in a non–privileged mode

will generate an error response.

•

If the application writes all 0’s to any PINMMR control register, then the default functions are selected

for the affected pins.

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•

Each byte in a PINMMR control register is used to select the functionality for a given pin. If the

application sets more than one bit within a byte for any pin, then the default function is selected for this

pin.

•

Some bits within the PINMMR registers could be associated with internal pads that are not brought out

in the 100 pin package. As a result, bits marked reserved should not be written as a 1.

2.4 Special Multiplexed Options

Special controls are implemented to affect particular functions on this microcontroller. These controls are

described in this section.

2.4.1 Filtering for eQEP Inputs

2.4.1.1 eQEPA Input

•

When PINMMR8[0] = 1, the eQEPA input is double-synchronized using VCLK.

When PINMMR8[0] = 0 and PINMMR8[1] = 1, the eQEPA input is double-synchronized and then

qualified through a fixed 6-bit counter using VCLK.

•

PINMMR8[0] = 0 and PINMMR8[1] = 0 is an illegal combination and behavior defaults to PINMMR8[0]

= 1.

2.4.1.2 eQEPB Input

•

When PINMMR8[8] = 1, the eQEPB input is double-synchronized using VCLK.

When PINMMR8[8] = 0 and PINMMR8[9] = 1, the eQEPB input is double-synchronized and then

qualified through a fixed 6-bit counter using VCLK.

•

PINMMR8[8] = 0 and PINMMR8[9] = 0 is an illegal combination and behavior defaults to PINMMR8[8]

= 1.

2.4.1.3 eQEPI Input

•

When PINMMR8[16] = 1, the eQEPI input is double-synchronized using VCLK.

When PINMMR8[16] = 0 and PINMMR8[17] = 1, the eQEPI input is double-synchronized and then

qualified through a fixed 6-bit counter using VCLK.

•

PINMMR8[16] = 0 and PINMMR8[17] = 0 is an illegal combination and behavior defaults to

PINMMR8[16] = 1.

2.4.1.4 eQEPS Input

•

When PINMMR8[24] = 1, the eQEPS input is double-synchronized using VCLK.

When PINMMR8[24] = 0 and PINMMR8[25] = 1, the eQEPS input is double-synchronized and then

qualified through a fixed 6-bit counter using VCLK.

•

PINMMR8[24] = 0 and PINMMR8[25] = 0 is an illegal combination and behavior defaults to

PINMMR8[24] = 1.

2.4.2 N2HET PIN_nDISABLE Input Port

•

When PINMMR9[0] = 1, GIOA[5] is connected directly to N2HET PIN_nDISABLE input of the N2HET

module.

When PINMMR9[0] = 0 and PINMMR9[1] = 1, EQEPERR is inverted and double-synchronized using

VCLK before connecting directly to the N2HET PIN_nDISABLE input of the N2HET module.

PINMMR9[0] = 0 and PINMMR9[1] = 0 is an illegal combination and behavior defaults to PINMMR9[0]

= 1.

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3 Device Operating Conditions

(1)

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range,

(2)

V_CC

-0.3 V to 1.43 V

-0.3 V to 4.6 V

-0.3 V to 3.6 V

-0.3 V to 4.6 V

±20 mA

(2)

Supply voltage range:

Input voltage range:

V_CCIO, V_CCP

V_CCAD

All input pins

ADC input pins

I_IK(V_I< 0 or V_I> V_CCIO

)

All pins, except ADIN

Input clamp current:

I_IK(V_I< 0 or V_I> V_CCAD

)

±10 mA

ADIN

Total

±40 mA

-40°C to 105°C

-40°C to 130°C

-65°C to 150°C

Operating free-air temperature range, T_A:

Operating junction temperature range, T_J:

Storage temperature range, T_stg

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated

grounds.

3.2 Device Recommended Operating Conditions⁽¹⁾

MIN

1.14

3

NOM

1.2

3.3

0

MAX UNIT

V_CC

Digital logic supply voltage (Core)

1.32

3.6

V

V_CCIO

Digital logic supply voltage (I/O)

V_{CCAD /}V_ADREFHI

MibADC supply voltage / A-to-D high-voltage reference source

Flash pump supply voltage

3

3.6

V

V_CCP

3

3.6

V

V_SS

Digital logic supply ground

V

V_{SSAD /}V_ADREFLO

MibADC supply ground / A-to-D low-voltage reference source

Maximum positive slew rate for V_CCIO, V_CCADand V_CCPsupplies

Operating free-air temperature

-0.1

0.1

1

V

V_SLEW

T_A

V/µs

°C

-40

105

130

T_J

Operating junction temperature⁽²⁾

(1) All voltages are with respect to V_SS, except V_CCAD, which is with respect to V_SSAD

(2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.

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3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains

Table 3-1. Clock Domain Timing Specifications

Parameter

f_HCLK

Description

Conditions

MIN

MAX

100

Unit

MHz

HCLK - System clock frequency

f_GCLK

GCLK - CPU clock frequency (ratio f_GCLK

f_HCLK= 1:1)

:

f_HCLK

f_VCLK

VCLK - Primary peripheral clock frequency

100

MHz

f_VCLK2

VCLK2 - Secondary peripheral clock

frequency

f_VCLKA1

f_RTICLK

VCLKA1 - Primary asynchronous

peripheral clock frequency

100

MHz

RTICLK - clock frequency

f_VCLK

3.4 Wait States Required

The TCM RAM can support program and data fetches at full CPU speed without any address or data wait states

required. There are no registers which need to be programmed for RAM wait states.

The TCM flash can support zero address and data wait states up to a CPU speed of 50MHz in non-pipelined

mode.The flash supports a maximum CPU clock speed of 100MHz in pipelined mode with no address wait states

and one data wait state.

The proper wait states should be set in the register fields Address Setup Wait State Enable (ASWSTEN

0xFFF87000[4]), Random Wait states (RWAIT 0xFFF87000[11:8]), and Emulation Wait states (EWAIT

0xFFF872B8[19:16]) as shown in Figure 3-1 below.

Flash Address Waitstates

ASWSTEN

0

0MHz

100MHz

Main Memory Data Waitstates (Bank 0)

RWAIT

0

1

0MHz

50MHz

EEPROM Emulation Memory Waitstates (Bank 7)

EWAIT

1

2

3

4

67MHz

84MHz

100MHz

0MHz

Figure 3-1. Wait States Scheme

The flash wrapper defaults to non-pipelined mode with address wait states disabled, ASWSTEN=0; the main

memory random-read data wait state, RWAIT=1; and the emulation memory random-read wait states, EWAIT=1.

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3.5 Power Consumption Over Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_HCLK= 100MHz

V_CCdigital supply current (operating mode)

150⁽¹⁾

mA

f_VCLK

=

100MHz,

Flash in pipelined

mode, V_CCmax

I_CC

LBIST clock rate =

50MHz

V_CCDigital supply current (LBIST mode)

VCC Digital supply current (PBIST mode)

165⁽²⁾⁽³⁾

mA

(2)(3)

PBIST ROM clock

frequency = 100MHz

150

mA

I_CCREFHI

I_CCAD

I_CCIO

AD_REFHIsupply current (operating mode)

V_CCADsupply current (operating mode)

V_CCIODigital supply current (operating mode.

V_CCPpump supply current

AD_REFHImax

3

45⁽⁴⁾

V_CCADmax

No DC load, V_CCmax

Read mode

mA

I_CCP

read from one bank

and program or

erase another,

V_CCPmax

65⁽⁴⁾

I_CCP,

3.3V supply current

I_{CCIO, CCAD}

I

(1) The maximum I_CC,value can be derated

•

linearly with voltage

by 0.76 mA/MHz for lower operating frequency when f_HCLK= f_VCLK

for lower junction temperature by the equation below where T_JKis the junction temperature in Kelvin and the result is in milliamperes.

36 - 0.001 ^0.026T

JK

(2) The maximum I_CC,value can be derated

•

linearly with voltage

for lower junction temperature by the equation below where T_JKis the junction temperature in Kelvin and the result is in milliamperes.

36 - 0.001 ^0.026T

JK

(3) LBIST and PBIST currents are for a short duration, typically less than 10ms. They are usually ignored for thermal calculations for the

device and the voltage regulator

(4) Maximum current requirement of the three combined supplies

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3.6 Input/Output Electrical Characteristics Over Recommended Operating Conditions⁽¹⁾

PARAMETER

Input hysteresis

TEST CONDITIONS

MIN

180

-0.3

2

TYP

MAX

UNIT

mV

V

V_hys

V_IL

All inputs

Low-level input voltage

High-level input voltage

All inputs⁽²⁾

0.8

V_CCIO+ 0.3

0.2 V_CCIO

0.2

V_IH

V

I_OL= I_OLmax

I_OL= 50 µA,

standard output

mode

V_OL

Low-level output voltage

V

I_OH= I_OHmax

0.8 V_CCIO

V_CCIO-0.3

I_OH= 50 µA,

standard output

mode

V_OH

High-level output voltage

V

V_I< V_SSIO- 0.3 or V_I

> V_CCIO+ 0.3

-3.5

3.5

I_IC

Input clamp current (I/O pins)

mA

I_IHPull-down 20µA

V_I= V_CCIO

5

40

195

-5

I_IHPull-down 100µA V_I= V_CCIO

I_ILPull-up 20µA

I_ILPull-up 100µA

V_I= V_SS

-40

-195

-1

I_I

Input current (I/O pins)

µA

-40

1

No Pull up or Pull-

down

All other pins

C_I

Input capacitance

Output capacitance

2

3

pF

C_O

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

(2) This does not apply to the nPORRST pin.

3.7 Output Buffer Drive Strengths

Table 3-2. Output Buffer Drive Strengths

Low-level Output Current,

I_OLfor V_I=V_OLmax

or

Signals

High-level Output Current,

I_OHfor V_I=V_OHmin

EQEPI, EQEPS,

TMS, TDI, TDO, RTCK,

nERROR

8mA

4mA

TEST,

MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, SPI3CLK, SPI3SIMO, SPI3SOMI,

nRST

AD1EVT,

CAN1RX, CAN1TX, CAN2RX, CAN2TX,

GIOA[0-7],

LINRX, LINTX,

2mA zero-dominant

MIBSPI1NCS[0-3], MIBSPI1NENA

N2HET[0], N2HET[2], N2HET[4], N2HET[6], N2HET[8], N2HET[10], N2HET[12], N2HET[14],

N2HET[16], N2HET[18], N2HET[22], N2HET[24],

SPI2NCS[0-3], SPI3NENA

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Table 3-2. Output Buffer Drive Strengths (continued)

Low-level Output Current,

I_OLfor V_I=V_OLmax

or

Signals

High-level Output Current,

I_OHfor V_I=V_OHmin

ECLK,

selectable 8mA / 2mA

SPI2CLK, SPI2SIMO, SPI2SOMI

The default output buffer drive strength is 8mA for these signals.

Table 3-3. Selectable 8ma/2ma Control

Signal

Control Bit

SYSPC10[0]

SPI2PC9[9]⁽¹⁾

SPI2PC9[10]⁽¹⁾

SPI2PC9[11]⁽¹⁾

Address

8mA

2mA

ECLK

0xFFFF FF78

0xFFF7 F668

0

1

SPI2CLK

SPI2SIMO

SPI2SOMI

(1) Do not do byte or half-word writes to SPI2PC9[31.16] as it may inadvertently change the drive strength of the SPI2 pins

3.8 Input Timings

t_pw

V_CCIO

Input

V_IH

V_IL

0

Figure 3-2. TTL-Level Inputs

Table 3-4. Timing Requirements for Inputs⁽¹⁾

Parameter

MIN

t_c(VCLK)+ 10⁽²⁾

MAX

Unit

t_pw

Input minimum pulse width

ns

(1) t_c(VCLK)= peripheral VBUS clock cycle time = 1 / f_(VCLK)

(2) The timing shown above is only valid for pin used in GIO mode.

3.9 Output Timings

Table 3-5. Switching Characteristics for Output Timings versus Load Capacitance ©_L)

Parameter

MIN

MAX

2.5

4

Unit

Rise time, t_r

Fall time, t_f

8mA pins

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

ns

7.2

12.5

2.5

4

ns

7.2

12.5

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Table 3-5. Switching Characteristics for Output Timings versus Load Capacitance ©_L) (continued)

Parameter

MIN

MAX

5.6

10.4

16.8

23.2

5.6

10.4

16.8

23.2

8

Unit

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

4mA pins

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL= 50 pF

ns

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

2mA-z pins

15

23

33

8

15

23

33

Selectable 8mA / 2mA-z

pins

8mA mode

2.5

4

7.2

12.5

2.5

4

7.2

12.5

8

2mA-z mode

15

23

33

8

15

23

33

t_r

t

f

V_CCIO

Output

V_OH

V_OL

0

Figure 3-3. CMOS-Level Outputs

Table 3-6. Timing Requirements for Outputs⁽¹⁾

Parameter

MIN

MAX

UNIT

t_{d(parallel_out)}

Delay between low to high, or high to low transition of general-purpose output signals

that can be configured by an application in parallel, e.g. all signals in a GIOA port, or

all N2HET signals.

5

ns

(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check

Table 3-2for output buffer drive strength information on each signal.

Device Operating Conditions

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4 System Information and Electrical Specifications

4.1 Voltage Monitor Characteristics

A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the

requirement for a specific sequence when powering up the core and I/O voltage supplies.

4.1.1 Important Considerations

•

The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the

device is held in reset when the voltage supplies are out of range.

•

The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other

supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a

source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and

VCCP supplies.

4.1.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO

signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when

the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and

PGMCU being low isolates the core logic as well as the I/O controls during the power-up or power-down

of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When

the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output

pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device

enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 4.2.3.1 for the timing

information on this glitch filter.

Table 4-1. Voltage Monitoring Specifications

PARAMETER

VCC low - VCC level below this

MIN

TYP

MAX

UNIT

0.75

0.9

1.13

V

threshold is detected as too low.

Voltage monitoring

thresholds

VCC high - VCC level above this

threshold is detected as too high.

1.40

1.85

1.7

2.4

2.1

2.9

V_MON

VCCIO low - VCCIO level below this

threshold is detected as too low.

4.1.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the

maximum specification cannot be filtered.

Table 4-2. VMON Supply Glitch Filtering Capability

Parameter

MIN

MAX

1us

Width of glitch on VCC that can be filtered

Width of glitch on VCCIO that can be filtered

250ns

1us

24

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4.2 Power Sequencing and Power On Reset

4.2.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-

up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 4-4 for

more details), core voltage rising above the minimum core supply threshold and the release of power-on

reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The

oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The

different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

Table 4-3. Power-Up Phases

Oscillator start-up and validity check

eFuse autoload

1032 oscillator cycles

1160 oscillator cycles

688 oscillator cycles

617 oscillator cycles

3497 oscillator cycles

Flash pump power-up

Flash bank power-up

Total

The CPU reset is released at the end of the above sequence and fetches the first instruction from address

0x00000000.

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4.2.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

4.2.3 Power-On Reset: nPORRST

This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the

recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

4.2.3.1 nPORRST Electrical and Timing Requirements

Table 4-4. Electrical Requirements for nPORRST

NO Parameter

MIN

MAX

Unit

V_CCPORL

V_CClow supply level when nPORRST must be active during power-

up

0.5

V

V_CCPORH

V_CChigh supply level when nPORRST must remain active during

power-up and become active during power down

1.14

V

V_CCIOPORL

V_CCIOPORH

V_IL(PORRST)

V_CCIO/ V_CCPlow supply level when nPORRST must be active during

power-up

1.1

V_CCIO/ V_CCPhigh supply level when nPORRST must remain active

during power-up and become active during power down

3.0

Low-level input voltage of nPORRST V_CCIO> 2.5V

Low-level input voltage of nPORRST V_CCIO< 2.5V

0.2 * V_CCIO

0.5

V

3

t_su(PORRST)

Setup time, nPORRST active before V_CCIOand V_CCP> V_CCIOPORL

during power-up

0

ms

6

7

t_h(PORRST)

t_su(PORRST)

Hold time, nPORRST active after V_CC> V_CCPORH

1

2

ms

µs

Setup time, nPORRST active before V_CC< V_CCPORHduring power

down

8

9

t_h(PORRST)

t_f(nPORRST)

Hold time, nPORRST active after V_CCIOand V_CCP> V_CCIOPORH

Hold time, nPORRST active after V_CC< V_CCPORL

1

0

ms

ns

Filter time nPORRST pin;

475

2000

Pulses less than MIN will be filtered out, pulses greater than MAX

will generate a reset.

3.3 V

1.2 V

V_CCIOPORH

V_CCIO/ V_CCP

8

6

V_CCPORH

V_CC

V_CCPORH

7

6

V_CCIOPORL

7

V_CCIOPORL

V_CCPORL

V_CC(1.2 V)

V_CCIO/ V_CCP(3.3 V)

3

9

V_IL

V_IL(PORRST)

nPORRST

NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.

Figure 4-1. nPORRST Timing Diagram

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4.3 Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset

condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the

output buffer is implemented as an open drain (drives low only). To ensure an external reset is not

arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup

4.3.1 Causes of Warm Reset

Table 4-5. Causes of Warm Reset

DEVICE EVENT

SYSTEM STATUS FLAG

Exception Status Register, bit 15

Global Status Register, bit 0

Power-Up Reset

Oscillator fail

PLL slip

Global Status Register, bits 8 and 9

Exception Status Register, bit 13

Exception Status Register, bit 5

Exception Status Register, bit 4

Exception Status Register, bit 3

Watchdog exception / Debugger reset

CPU Reset (driven by the CPU STC)

Software Reset

External Reset

4.3.2 nRST Timing Requirements

Table 4-6. nRST Timing Requirements

PARAMETER

MIN

MAX

UNIT

(1)

t_v(RST)

Valid time, nRST active after

nPORRST inactive

2256t_c(OSC)

ns

Valid time, nRST active (all other

System reset conditions)

32t_c(VCLK)

475

t_f(nRST)

Filter time nRST pin;

2000

ns

Pulses less than MIN will be

filtered out, pulses greater than

MAX will generate a reset

(1) Assumes the oscillator has started up and stabilized before nPORRST is released .

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4.4 ARM^©Cortex-R4™ CPU Information

4.4.1 Summary of ARM Cortex-R4 CPU Features

The features of the ARM Cortex-R4™ CPU include:

•

An integer unit with integral Embedded ICE-RT logic.

High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)

for Level two (L2) master and slave interfaces.

•

Dynamic branch prediction with a global history buffer, and a 4-entry return stack

Low interrupt latency.

Non-maskable interrupt.

A Harvard Level one (L1) memory system with:

–

Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking

memories

–

ARMv7-R architecture Memory Protection Unit (MPU) with 8 regions

•

Dual core logic for fault detection in safety-critical applications.

An L2 memory interface:

–

Single 64-bit master AXI interface

64-bit slave AXI interface to TCM RAM blocks

•

A debug interface to a CoreSight Debug Access Port (DAP).

A Perfomance Monitoring Unit (PMU)

A Vectored Interrupt Controller (VIC) port.

For more information on the ARM Cortex-R4 CPU please see www.arm.com.

4.4.2 ARM Cortex-R4 CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

•

ECC On Tightly-Coupled Memory (TCM) Accesses

Hardware Vectored Interrupt (VIC) Port

Memory Protection Unit (MPU)

4.4.3 Dual Core Implementation

The device has two Cortex-R4 cores, where the output signals of both CPUs are compared in the CCM-

R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock

cycles as shown in Figure 4-3.

The CPUs have a diverse CPU placement given by following requirements:

•

different orientation; e.g. CPU1 = "north" orientation, CPU2 = "flip west" orientation

dedicated guard ring for each CPU

Flip West

North

F

Figure 4-2. Dual - CPU Orientation

4.4.4 Duplicate clock tree after GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU

running at the same frequency and in phase to the clock of CPU1. See Figure 4-3.

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4.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety

This device has two ARM Cortex-R4 CPU cores, where the output signals of both CPUs are compared in

the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in

a different way as shown in the figure below.

Output + Control

CCM-R4

2 cycle delay

CCM-R4

compare

error

CPU1CLK

CPU 1

CPU 2

2 cycle delay

CPU2CLK

Input + Control

Figure 4-3. Dual Core Implementation

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of

both CPUs before the registers are used, including function calls where the register values are pushed

onto the stack.

4.4.6 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4 CPU Cores using the Deterministic

Logic BIST Controller as the test engine.

The main features of the self-test controller are:

•

Ability to divide the complete test run into independent test intervals

Capable of running the complete test or running a few intervals at a time

Ability to continue from the last executed interval (test set) or to restart from the beginning (First test

set)

•

Complete isolation of the self-tested CPU core from the rest of the system during the self-test run

Ability to capture the failure interval number

Timeout counter for the CPU self-test run as a fail-safe feature

4.4.6.1 Application Sequence for CPU Self-Test

1. Configure clock domain frequencies.

2. Select the number of test intervals to be run.

3. Configure the timeout period for the self-test run.

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4. Save the CPU state if required

5. Enable self-test.

6. Wait for CPU reset.

7. In the reset handler, read CPU self-test status to identify any failures.

8. Retrieve CPU state if required.

For more information refer to the device technical reference manual.

4.4.6.2 CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is 50MHz. The STCCLK is divided down from the CPU clock,

when necessary. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.

For more information see the device Technical Reference Manual..

4.4.6.3 CPU Self-Test Coverage

Table 4-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test

cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.

Table 4-7. CPU Self-Test Coverage

INTERVALS

TEST COVERAGE, %

0

TEST CYCLES

0

1

60.06

68.71

73.35

76.57

78.7

1365

2

2730

3

4095

4

5460

5

6825

6

80.4

8190

7

81.76

82.94

83.84

84.58

85.31

85.9

9555

8

10920

12285

13650

15015

16380

17745

19110

20475

21840

23205

24570

25935

27300

28665

30030

31395

32760

34125

35490

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

86.59

87.17

87.67

88.11

88.53

88.93

89.26

89.56

89.86

90.1

90.36

90.62

90.86

91.06

30

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4.5 Clocks

4.5.1 Clock Sources

The table below lists the available clock sources on the device. Each of the clock sources can be enabled

or disabled using the CSDISx registers in the system module. The clock source number in the table

corresponds to the control bit in the CSDISx register for that clock source.

The table also shows the default state of each clock source.

Table 4-8. Available Clock Sources

Clock

Source #

Name

Description

Default State

0

1

2

3

4

OSCIN

PLL1

Main Oscillator

Output From PLL1

Enabled

Disabled

Enabled

Reserved

EXTCLKIN1

CLK80K

Reserved

External Clock Input #1

Low Frequency Output of Internal Reference Oscillator

High Frequency Output of Internal Reference

Oscillator

5

CLK10M

Enabled

6

7

Reserved

Disabled

4.5.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors

across the external OSCIN and OSCOUT pins as shown in Figure 4-4. The oscillator is a single stage

inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test

measurement and low power modes.

TI strongly encourages each customer to submit samples of the device to the resonator/crystal

vendors for validation. The vendors are equipped to determine what load capacitors will best tune

their resonator/crystal to the microcontroller device for optimum start-up and operation over

temperature/voltage extremes.

An external oscillator source can be used by connecting a 3.3V clock signal to the OSCIN pin and leaving

the OSCOUT pin unconnected (open) as shown in the figure below.

(see Note B)

OSCIN

Kelvin_GND

OSCOUT

OSCIN

OSCOUT

C1

C2

External

Clock Signal

(toggling 0-3.3V)

(see Note A)

Crystal

(a)

(b)

Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.

Note B: Kelvin_GND should not be connected to any other GND.

Figure 4-4. Recommended Crystal/Clock Connection

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4.5.1.1.1 Timing Requirements for Main Oscillator

Table 4-9. Timing Requirements for Main Oscillator

Parameter

MIN

50

Type

MAX

200

Unit

ns

tc(OSC)

Cycle time, OSCIN (when using a sine-wave input)

tc(OSC_SQR)

Cycle time, OSCIN, (when input to the OSCIN is a

square wave )

50

200

ns

tw(OSCIL)

tw(OSCIH)

Pulse duration, OSCIN low (when input to the OSCIN

is a square wave)

15

ns

Pulse duration, OSCIN high (when input to the OSCIN

is a square wave)

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4.5.1.2 Low Power Oscillator

The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single

macro.

4.5.1.2.1 Features

The main features of the LPO are:

•

Supplies a clock at extremely low power for power-saving modes. This is connected as clock source #

4 of the Global Clock Module.

Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source # 5

of the Global Clock Module.

Provides a comparison clock for the crystal oscillator failure detection circuit.

BIAS_EN

LFEN

CLK80K

LF_TRIM

Low

Power

Oscillator

HFEN

CLK10M

HF_TRIM

CLK10M_VALID

nPORRST

Figure 4-5. LPO Block Diagram

Figure 4-5 shows a block diagram of the internal reference oscillator. This is a low power oscillator (LPO)

and provides two clock sources: one nominally 80KHz and one nominally 10MHz.

4.5.1.2.2 LPO Electrical and Timing Specifications

Table 4-10. LPO Specifications

Parameter

MIN

Typical

MAX

Unit

Clock Detection

oscillator fail frequency - lower threshold, using

untrimmed LPO output

1.375

2.4

4.875

MHz

oscillator fail frequency - higher threshold, using

untrimmed LPO output

22

38.4

78

MHz

LPO - HF oscillator

untrimmed frequency

trimmed frequency

5.5

8

9

19.5

11

MHz

µs

(f_HFLPO

)

9.6

startup time from STANDBY (LPO BIAS_EN High for

at least 900µs)

10

cold startup time

900

180

100

µs

kHz

µs

LPO - LF oscillator

untrimmed frequency

36

85

startup time from STANDBY (LPO BIAS_EN High for

at least 900µs)

cold startup time

2000

µs

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4.5.1.3 Phase Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

•

Frequency modulation can be optionally superimposed on the synthesized frequency of PLL.

Configurable frequency multipliers and dividers.

Built-in PLL Slip monitoring circuit.

Option to reset the device on a PLL slip detection.

4.5.1.3.1 Block Diagram

Figure below shows a high-level block diagram of the PLL macro on this microcontroller.

PLLCLK

OSCIN

INTCLK

/NR

/OD

/R

VCOCLK

post_ODCLK

PLL

/1 to /64

/1 to /8

/1 to /32

/NF

f_PLLCLK= (f_OSCIN/ NR) * NF / (OD * R)

/1 to /256

Figure 4-6. PLL Block Diagram

4.5.1.3.2 PLL Timing Specifications

Table 4-11. PLL Timing Specifications

PARAMETER

MIN

MAX

20

UNIT

f_INTCLK

PLL1 Reference Clock frequency

1

MHz

f_{post_ODCLK}

Post-ODCLK – PLL1 Post-divider input

clock frequency

400

f_VCOCLK

VCOCLK – PLL1 Output Divider (OD) input

clock frequency

150

550

MHz

4.5.2 Clock Domains

4.5.2.1 Clock Domain Descriptions

The table below lists the device clock domains and their default clock sources. The table also shows the

system module control register that is used to select an available clock source for each clock domain.

Table 4-12. Clock Domain Descriptions

Clock Domain Name

Default Clock

Source

Clock Source

Selection Register

Description

HCLK

GCLK

OSCIN

GHVSRC

•

Is disabled via the CDDISx registers bit 1

•

Always the same frequency as HCLK

In phase with HCLK

Is disabled separately from HCLK via the CDDISx registers bit 0

Can be divided by 1 up to 8 when running CPU self-test

(LBIST) using the CLKDIV field of the STCCLKDIV register at

address 0xFFFFE108

GCLK2

OSCIN

GHVSRC

•

Always the same frequency as GCLK

2 cycles delayed from GCLK

Is disabled along with GCLK

Gets divided by the same divider setting as that for GCLK when

running CPU self-test (LBIST)

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Table 4-12. Clock Domain Descriptions (continued)

Clock Domain Name

Default Clock

Source

Clock Source

Selection Register

Description

VCLK

OSCIN

GHVSRC

•

Divided down from HCLK

Can be HCLK/1, HCLK/2, ... or HCLK/16

Is disabled separately from HCLK via the CDDISx registers bit 2

Can be disabled separately for eQEP using CDDISx registers

bit 9

VCLK2

OSCIN

GHVSRC

•

Divided down from HCLK

Can be HCLK/1, HCLK/2, ... or HCLK/16

Frequency must be an integer multiple of VCLK frequency

Is disabled separately from HCLK via the CDDISx registers bit 3

VCLKA1

RTICLK

VCLK

VCLKASRC

RCLKSRC

•

Defaults to VCLK as the source

Frequency can be as fast as HCLK frequency

Is disabled via the CDDISx registers bit 4

•

Defaults to VCLK as the source

If a clock source other than VCLK is selected for RTICLK, then

the RTICLK frequency must be less than or equal to VCLK/3

–

Application can ensure this by programming the RTI1DIV

field of the RCLKSRC register, if necessary

•

Is disabled via the CDDISx registers bit 6

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4.5.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in the figure below.

GCM

0

OSCIN

FMzPLL

1

GCLK, GCLK2 (to CPU)

X1..256

/1..8

/1..32

*

/1..64

HCLK (to SYSTEM)

4

80kHz

Low Power

Oscillator

/1..16

10MHz

5

3

VCLK (to System and

Peripheral Modules)

VCLK2 (to N2HET)

EXTCLKIN

* The frequency at this node must not

exceed the maximum HCLK frequency.

0

1

3

4

AVCLK1 (to DCAN1, 2)

5

VCLK

0

1

3

/1, 2, 4, or 8

4

RTICLK (to RTI+DWWD)

5

VCLK

CDDISx.9

AVCLK1

VCLK

VCLK2

HRP

/1..64

/1,2,..256

/2,3..2²⁴

/1,2..32

/1,2..65536

/1,2,..1024

eQEP

HET TU

LRP

/2⁰..2⁷

Prop_seg Phase_seg2

Phase_seg1

ECLK

SPI

Baud Rate

ADCLK

LIN

Baud Rate

LIN

External Clock

High Loop

Resolution Clock

SPIx,MibSPIx

MibADC

CAN Baud Rate

DCAN1, 2

N2HET

Figure 4-7. Device Clock Domains

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4.5.3 Clock Test Mode

The RM4x platform architecture defines a special mode that allows various clock signals to be brought out

on to the ECLK pin and N2HET[2] device outputs. This mode is called the Clock Test mode. It is very

useful for debugging purposes and can be configured via the CLKTEST register in the system module.

Table 4-13. Clock Test Mode Options

CLKTEST[3-0]

SIGNAL ON ECLK

CLKTEST[11-8]

SIGNAL ON N2HET[2]

0000

Oscillator

0000

Oscillator Valid Status

Main PLL free-running clock output

(PLLCLK)

0001

Main PLL Valid status

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Reserved

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Reserved

CLK80K

Reserved

CLK10M

CLK10M Valid status

Reserved

GCLK

CLK80K

RTI Base

Oscillator Valid status

Reserved

VCLKA1

Reserved

Flash HD Pump Oscillator

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4.6 Clock Monitoring

The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low

power oscillator (LPO).

The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).

The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN

frequency falls out of a frequency window, the CLKDET flags this condition in the global status register

(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp

mode clock).

The valid OSCIN frequency range is defined as: f_HFLPO/ 4 < f_OSCIN< f_HFLPO* 4.

4.6.1 Clock Monitor Timings

For more information on LPO and Clock detection, refer to Table 4-10.

upper

threshold

lower

threshold

guaranteed fail

guaranteed pass

guaranteed fail

f[MHz]

1.375

4.875

22

78

Figure 4-8. LPO and Clock Detection, Untrimmed HFLPO

4.6.2 External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a pre-scaled clock signal indicative of an internal device clock.

This output can be externally monitored as a safety diagnostic.

4.6.3 Dual Clock Comparator

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by

counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of

spec, an error signal is generated. For example, the DCC can be configured to use CLK10M as the

reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration

allows the DCC to monitor the PLL output clock when VCLK is using the PLL output as its source.

An additional use of this module is to measure the frequency of a selectable clock source, using the input

clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a

fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width

pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1

does not reach 0 within the counting window generated by counter 0.

4.6.3.1 Features

•

Takes two different clock sources as input to two independent counter blocks.

One of the clock sources is the known-good, or reference clock; the second clock source is the "clock

under test."

•

Each counter block is programmable with initial, or seed values.

The counter blocks start counting down from their seed values at the same time; a mismatch from the

expected frequency for the clock under test generates an error signal which is used to interrupt the

CPU.

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4.6.3.2 Mapping of DCC Clock Source Inputs

Table 4-14. DCC Counter 0 Clock Sources

TEST MODE

CLOCK SOURCE [3:0]

CLOCK NAME

oscillator (OSCIN)

high frequency LPO

test clock (TCK)

VCLK

others

0x5

0xA

X

0

1

Table 4-15. DCC Counter 1 Clock Sources

TEST MODE

KEY [3:0]

CLOCK SOURCE [3:0]

CLOCK NAME

others

-

N2HET[31]

Main PLL free-running clock

output

0x0

0x1

0x2

n/a

low frequency LPO

high frequency LPO

flash HD pump oscillator

EXTCLKIN

0xA

0x3

0

1

0x4

0x5

0x6

n/a

0x7

ring oscillator

VCLK

0x8 - 0xF

X

HCLK

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4.7 Glitch Filters

A glitch filter is present on the following signals.

Table 4-16. Glitch Filter Timing Specifications

Parameter

MIN

MAX

Unit

nPORRST

t_f(nPORRST)

475

2000

ns

Filter time nPORRST pin;

pulses less than MIN will be filtered out, pulses greater than

MAX will generate a reset⁽¹⁾

nRST

TEST

t_f(nRST)

475

2000

ns

Filter time nRST pin;

pulses less than MIN will be filtered out, pulses greater than

MAX will generate a reset

t_f(TEST)

Filter time TEST pin;

pulses less than MIN will be filtered out, pulses greater than

MAX will pass through

(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,

I/O pins, etc.) without also generating a valid reset signal to the CPU.

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4.8 Device Memory Map

4.8.1 Memory Map Diagram

The figure below shows the device memory map.

0xFFFFFFFF

SYSTEM Modules

Peripherals - Frame 1

0xFFF80000

0xFFF7FFFF

0xFF000000

0xFE000000

CRC

RESERVED

0xFCFFFFFF

0xFC000000

Peripherals - Frame 2

RESERVED

0xF07FFFFF

Flash Module Bus2 Interface

(Flash ECC, OTP andEEPROM accesses)

0xF0000000

RESERVED

0x2005FFFF

0x20000000

Flash (384KB) (Mirrored Image)

RESERVED

0x08407FFF

0x08400000

RAM - ECC

RESERVED

0x08007FFF

0x08000000

RAM (32KB)

RESERVED

0x0005FFFF

0x00000000

Flash (384KB)

Figure 4-9. RM42LS432 Memory Map

The Flash memory in all configurations is mirrored to support ECC logic testing. The base address of the

mirrored Flash image is 0x2000 0000.

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4.8.2 Memory Map Table

Please refer to Figure 1-1 for a block diagram showing the device interconnects.

Table 4-17. Device Memory Map

ADDRESS RANGE

START END

Memories tightly coupled to the ARM Cortex-R4 CPU

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME ACTUA

SIZE L SIZE

MODULE NAME

TCM Flash

CS0

0x0000_0000

0x00FF_FFFF

16MB

384KB

TCM RAM + RAM

ECC

CSRAM0

0x0800_0000

0x0BFF_3FFF

64MB

32KB

Abort

Flash mirror

frame

Mirrored Flash

0x2000_0000

0x20FF_FFFF

16MB

384KB

Flash Module Bus2 Interface

Customer OTP,

TCM Flash Banks

0xF000_0000

0xF000_07FF

0xF000_E3FF

2KB

1KB

64KB

8KB

Customer OTP,

EEPROM Bank

0xF000_E000

0xF004_0000

Customer

OTP–ECC, TCM

Flash Banks

0xF004_00FF

0xF004_1C7F

256B

128B

Customer

OTP–ECC,

0xF004_1C00

EEPROM Bank

TI OTP, TCM

Flash Banks

0xF008_0000

0xF008_E000

0xF00C_0000

0xF00C_1C00

0xF008_07FF

0xF008_E3FF

0xF00C_00FF

0xF00C_1C7F

2KB

1KB

Abort

64KB

8KB

TI OTP, EEPROM

Bank

TI OTP–ECC,

TCM Flash Banks

256B

128B

TI OTP–ECC,

EEPROM Bank

EEPROM

Bank–ECC

0xF010_0000

0xF020_0000

0xF040_0000

0xF010_07FF

0xF020_3FFF

0xF040_DFFF

256KB

2MB

2KB

16KB

48KB

EEPROM Bank

Flash Data Space

ECC

1MB

Cyclic Redundancy Checker (CRC) Module Registers

CRC

CRC frame

PCS[7]

0xFE00_0000

0xFF0E_0000

0xFF1C_0000

0xFEFF_FFFF

Peripheral Memories

0xFF0F_FFFF

16MB

128KB

512B

2KB

Accesses above 0x200 generate abort.

Abort for accesses above 2KB

MIBSPI1 RAM

DCAN2 RAM

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

PCS[14]

0xFF1D_FFFF

0xFF1F_FFFF

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

DCAN1 RAM

MIBADC RAM

PCS[15]

PCS[31]

0xFF1E_0000

0xFF3E_0000

128KB

2KB

8KB

Wrap around for accesses to

unimplemented address offsets lower

than 0x1FFF.

Look-up table for ADC wrapper. Starts

at offset 0x2000 ans ends at 0x217F.

Wrap around for accesses between

offsets 0x180 and 0x3FFF. Aborts

generated for accesses beyond 0x4000

0xFF3F_FFFF

MIBADC Look-Up

Table

384

bytes

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Table 4-17. Device Memory Map (continued)

ADDRESS RANGE

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME ACTUA

MODULE NAME

SIZE

L SIZE

START

END

Wrap around for accesses to

unimplemented address offsets lower

than 0x3FFF. Abort generated for

accesses beyond 0x3FFF.

N2HET RAM

HTU RAM

PCS[35]

PCS[39]

0xFF46_0000

0xFF4E_0000

0xFF47_FFFF

128KB

16KB

1KB

0xFF4F_FFFF

Abort

Debug Components

CoreSight Debug

ROM

Reads return zeros, writes have no

effect

CSCS0

CSCS1

0xFFA0_0000

0xFFA0_1000

0xFFA0_0FFF

0xFFA0_1FFF

4KB

Reads return zeros, writes have no

effect

Cortex-R4 Debug

Peripheral Control Registers

0xFFF7_A400 256B

Reads return zeros, writes have no

effect

HTU

N2HET

GIO

PS[22]

PS[17]

PS[16]

PS[15]

PS[8]

0xFFF7_A4FF

0xFFF7_B8FF

0xFFF7_BCFF

0xFFF7_C1FF

0xFFF7_DDFF

0xFFF7_DFFF

0xFFF7_E4FF

0xFFF7_F5FF

0xFFF7_F7FF

0xFFF7_F9FF

0xFFF7_99FF

0xFCF7_99FF

256B

512B

256B

512B

256B

Reads return zeros, writes have no

effect

0xFFF7_B800

0xFFF7_BC00

0xFFF7_C000

0xFFF7_DC00

0xFFF7_DE00

0xFFF7_E400

0xFFF7_F400

0xFFF7_F600

0xFFF7_F800

0xFFF7_9900

0xFCF7_9900

256B

512B

256B

512B

256B

Reads return zeros, writes have no

effect

Reads return zeros, writes have no

effect

MIBADC

DCAN1

DCAN2

LIN

Reads return zeros, writes have no

effect

Reads return zeros, writes have no

effect

PS[8]

Reads return zeros, writes have no

effect

PS[6]

Reads return zeros, writes have no

effect

MibSPI1

SPI2

PS[2]

Reads return zeros, writes have no

effect

PS[2]

Reads return zeros, writes have no

effect

SPI3

PS[1]

Reads return zeros, writes have no

effect

EQEP

PS[25]

PS2[25]

Reads return zeros, writes have no

effect

EQEP (Mirrored)

System Modules Control Registers and Memories

Wrap around for accesses to

unimplemented address offsets lower

than 0x3FF. Accesses beyond 0x3FF

will be ignored.

VIM RAM

PPCS2

0xFFF8_2000

0xFFF8_2FFF

4KB

1KB

Flash Wrapper

PPCS7

0xFFF8_7000

0xFFF8_C000

0xFFF8_7FFF

0xFFF8_CFFF

4KB

Abort

eFuse Farm

Controller

PPCS12

Abort

Reads return zeros, writes have no

effect

PCR registers

PPS0

0xFFFF_E000

0xFFFF_E100

0xFFFF_E0FF

0xFFFF_E1FF

256B

System Module -

Frame 2 (see

device TRM)

Reads return zeros, writes have no

effect

Reads return zeros, writes have no

effect

PBIST

STC

PPS1

0xFFFF_E400

0xFFFF_E600

0xFFFF_E5FF

0xFFFF_E6FF

512B

256B

512B

256B

Reads return zeros, writes have no

effect

IOMM

Multiplexing

control module

Generates address error interrupt if

enabled.

PPS2

0xFFFF_EA00

0xFFFF_EBFF

512B

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Table 4-17. Device Memory Map (continued)

ADDRESS RANGE

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME ACTUA

MODULE NAME

SIZE

256B

L SIZE

256B

START

END

Reads return zeros, writes have no

effect

DCC

ESM

PPS3

PPS5

PPS6

PPS7

0xFFFF_EC00

0xFFFF_F500

0xFFFF_F600

0xFFFF_F800

0xFFFF_F900

0xFFFF_FC00

0xFFFF_FD00

0xFFFF_FE00

0xFFFF_ECFF

Reads return zeros, writes have no

effect

0xFFFF_F5FF

0xFFFF_F6FF

0xFFFF_F8FF

0xFFFF_F9FF

0xFFFF_FCFF

0xFFFF_FDFF

0xFFFF_FEFF

Reads return zeros, writes have no

effect

CCMR4

Reads return zeros, writes have no

effect

RAM ECC even

RAM ECC odd

RTI + DWWD

VIM Parity

VIM

Reads return zeros, writes have no

effect

Reads return zeros, writes have no

effect

Reads return zeros, writes have no

effect

Reads return zeros, writes have no

effect

System Module -

Frame 1 (see

device TRM)

Reads return zeros, writes have no

effect

PPS7

0xFFFF_FF00

0xFFFF_FFFF

256B

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4.8.3 Master/Slave Access Privileges

The table below lists the access permissions for each bus master on the device. A bus master is a module

that can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed

in the "MASTERS" column can access that slave module.

Table 4-18. Master / Slave Access Matrix

MASTERS

ACCESS MODE

SLAVES ON MAIN SCR

Flash Module Bus2 Non-CPU Accesses

Interface: to Program Flash

CRC

Peripheral Control

Registers, All

OTP, ECC, EEPROM and CPU Data RAM

Bank

Peripheral

Memories, And All

System Module

Control Registers

And Memories

CPU READ

CPU WRITE

HTU

User/Privilege

Privilege

Yes

No

Yes

No

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4.9 Flash Memory

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4.9.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a

customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense

amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical

construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or

erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

Table 4-19. Flash Memory Banks and Sectors

Memory Arrays (or Banks)⁽¹⁾

Block

No.

Sector

No.

Segment

Low Address

High Address

BANK0 (384kBytes)

0

1

8K Bytes

32K Bytes

128K Bytes

4K Bytes

0x0000_0000

0x0000_2000

0x0000_4000

0x0000_6000

0x0000_8000

0x0000_A000

0x0000_C000

0x0000_E000

0x0001_0000

0x0001_2000

0x0001_4000

0x0001_6000

0x0001_8000

0x0002_0000

0x0004_0000

0xF020_0000

0xF020_1000

0xF020_2000

0xF020_3000

0x0000_1FFF

0x0000_3FFF

0x0000_5FFF

0x0000_7FFF

0x0000_9FFF

0x0000_BFFF

0x0000_DFFF

0x0000_FFFF

0x0001_1FFF

0x0001_3FFF

0x0001_5FFF

0x0001_7FFF

0x0001_FFFF

0x0003_FFFF

0x0005_FFFF

0xF020_0FFF

0xF020_1FFF

0xF020_2FFF

0xF020_3FFF

2

3

4

5

6

7

8

9

10

11

12

13

14

0

1

2

0

1

2

3

BANK7 (16kBytes) for EEPROM

emulation⁽²⁾⁽³⁾

1

2

3

(1) The Flash banks are 144-bit wide bank with ECC support.

(2) Flash bank7 is an FLEE bank and can be programmed while executing code from flash bank0.

(3) Code execution is not allowed from flash bank7.

4.9.2 Main Features of Flash Module

•

Support for multiple flash banks for program and/or data storage

Simultaneous read access on a bank while performing program or erase operation on any other bank

Integrated state machines to automate flash erase and program operations

Software interface for flash program and erase operations

Pipelined mode operation to improve instruction access interface bandwidth

Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4 CPU

–

Error address is captured for host system debugging

•

Support for a rich set of diagnostic features

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4.9.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection

(SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of

instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on

the 64 bits received and compares it with the ECC code returned by the flash module. A signle-bit error is

corrected and flagged by the CPU, while a multi-bit error is only flagged. The CPU signals an ECC error

via its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the

"X" bit of the Performance Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0

ORR r1, r1, #0x00000010

MCR p15,#0,r1,c9,c12,#0

MRC p15,#0,r1,c9,c12,#0

;Enabling Event monitor states

;Set 4th bit (‘X’) of PMNC register

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM

and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC

checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN

bits of the System Control coprocessor's Auxiliary Control Register, c1.

MRC p15, #0, r1, c1, c0, #1

ORR r1, r1, #0x0e000000

DMB

;Enable ECC checking for ATCM and BTCMs

MCR p15, #0, r1, c1, c0, #1

4.9.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, refer to Section 3.4.

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4.10 Flash Program and Erase Timings for Program Flash

Table 4-20. Timing Specifications for Program Flash

Parameter

Wide Word (144bit) programming time

384KByte programming time⁽¹⁾

MIN

NOM

MAX

300

4

Unit

µs

s

t_prog(144bit)

t_prog(Total)

40

-40°C to 105°C

0°C to 60°C, for first

25 cycles

1

2

s

t_erase

Sector/Bank erase time⁽²⁾

-40°C to 105°C

0.30

16

4

s

0°C to 60°C, for first

25 cycles

100

ms

t_wec

Write/erase cycles with 15 year Data Retention -40°C to 105°C

requirement

1000

cycles

(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes

programming 144 bits at a time at the maximum specified operating frequency.

(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase

a sector.

4.11 Flash Program and Erase Timings for Data Flash

Table 4-21. Timing Specifications for Data Flash

Parameter

Wide Word (72bit) programming time

16KByte programming time⁽¹⁾

MIN

NOM

MAX

300

330

165

Unit

µs

t_prog(72 bit)

t_prog(Total)

40

-40°C to 105°C

ms

0°C to 60°C, for first

25 cycles

85

t_erase

Sector/Bank erase time⁽²⁾

-40°C to 105°C

0.200

14

8

s

0°C to 60°C, for first

25 cycles

100

ms

t_wec

Write/erase cycles with 15 year Data Retention -40°C to 105°C

requirement

100000

cycles

(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes

programming 144 bits at a time at the maximum specified operating frequency.

(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase

a sector.

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4.12 Tightly-Coupled RAM Interface Module

Figure 4-10 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4™ CPU.

VBUSP I/F PMT I/F

36 Bit

Upper 32 bits data &

4 ECC bits

wide

RAM

Cortex R4™

EVEN Address

TCM BUS

TCRAM

B0

TCM

36 Bit

Interface 1

wide

RAM

64 Bit data bus

RAM

Lower32 bits data &

4 ECC bits

A

TCM

36 Bit

36 Bwitide

wideRAM

RAM

Upper 32 bits data &

4 ECC bits

wide

B1

TCM

ODD Address

TCM BUS

TCRAM

Interface 2

36 Bit

64 Bit data bus

36 Bit

wide

RAM

Lower32 bits data &

4 ECC bits

VBUSP I/F PMT I/F

Figure 4-10. TCRAM Block Diagram

4.12.1 Features

The features of the Tightly Coupled RAM (TCRAM) Module are:

•

Acts as slave to the Cortex-R4 CPU's BTCM interface

Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code

Monitors CPU Event Bus and generates single or multi-bit error interrupts

Stores addresses for single and multi-bit errors

Provides CPU address bus integrity checking by supporting parity checking on the address bus

Performs redundant address decoding for the RAM bank chip select and ECC select generation logic

Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved

RAM banks and generating independent RAM access control signals to the two banks

•

Supports auto-initialization of the RAM banks along with the ECC bits

No support for bit-wise RAM accesses

4.12.2 TCRAMW ECC Support

The TCRAMW passes on the ECC code for each data read by the Cortex-R4 CPU from the RAM. It also

stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The

TCRAMW monitors the CPU's event bus and provides registers for indicating single/multi-bit errors and

also for identifying the address that caused the single or multi-bit error. The event signaling and the ECC

checking for the RAM accesses must be enabled inside the CPU.

For more information see the device Technical Reference Manual.

4.13 Parity Protection for Accesses to peripheral RAMs

Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the

parity is calculated based on the data read from the peripheral RAM and compared with the good parity

value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates

a parity error signal that is mapped to the Error Signaling Module. The module also captures the

peripheral RAM address that caused the parity error.

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The parity protection for peripheral RAMs is not enabled by default and must be enabled by the

application. Each individual peripheral contains control registers to enable the parity protection for

accesses to its RAM.

NOTE

The CPU read access gets the actual data from the peripheral. The application can choose

to generate an interrupt whenever a peripheral RAM parity error is detected.

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4.14 On-Chip SRAM Initialization and Testing

4.14.1 On-Chip SRAM Self-Test Using PBIST

4.14.1.1 Features

•

Extensive instruction set to support various memory test algorithms

ROM-based algorithms allow application to run TI production-level memory tests

Independent testing of all on-chip SRAM

4.14.1.2 PBIST RAM Groups

Table 4-22. PBIST RAM Grouping

Test Pattern (Algorithm)

March 13N⁽¹⁾

two port

(cycles)

March 13N⁽¹⁾

single port

(cycles)

triple read

slow read

triple read

fast read

Memory

RAM Group

Test Clock

MEM Type

ALGO MASK

0x1

ALGO MASK

0x2

ALGO MASK

0x4

ALGO MASK

0x8

PBIST_ROM

STC_ROM

DCAN1

1

2

ROM CLK

VCLK

ROM

X

ROM

3

Dual Port

Single Port

Dual Port

12720

6480

DCAN2

4

VCLK

ESRAM1

MIBSPI1

VIM

6

HCLK

133160

7

VCLK

33440

12560

4200

10

11

13

14

VCLK

MIBADC

N2HET1

HTU1

VCLK

25440

6480

VCLK

(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for

application testing.

The PBIST ROM clock can be divided down from HCLK. The divider is selected by programming the

ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.

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4.14.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized via the Memory Hardware

Initialization mechanism in the System module. This hardware mechanism allows an application to

program the memory arrays with error detection capability to a known state based on their error detection

scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects

the memories that are to be initialized.

For more information on these registers refer to the device Technical Reference Manual.

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in

Table 4-23.

Table 4-23. Memory Initialization

ADDRESS RANGE

CONNECTING MODULE

MSINENA REGISTER BIT #⁽¹⁾

BASE ADDRESS

0x08000000

0xFF0E0000

0xFF1C0000

0xFF1E0000

0xFF3E0000

0xFF460000

0xFF4E0000

0xFFF82000

ENDING ADDRESS

0x08007FFF

0xFF0FFFFF

0xFF1DFFFF

0xFF1FFFFF

0xFF3FFFFF

0xFF47FFFF

0xFF4FFFFF

0xFFF82FFF

RAM

0

7⁽²⁾

6

MIBSPI1 RAM

DCAN2 RAM

DCAN1 RAM

MIBADC RAM

N2HET RAM

HTU RAM

5

8

3

4

VIM RAM

2

(1) Unassigned register bits are reserved.

(2) The MibSPI1 module performs an initialization of the transmit and receive RAMs as soon as the module is brought out of reset using the

SPI Global Control Register 0 (SPIGCR0). This is independent of whether the application chooses to initialize the MibSPI1 RAMs using

the system module auto-initialization method.

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4.15 Vectored Interrupt Manager

The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the

many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow

of program execution. Normally, these events require a timely response from the central processing unit

(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to

an interrupt service routine (ISR).

4.15.1 VIM Features

The VIM module has the following features:

•

Supports 96 interrupt channels.

Provides programmable priority and enable for interrupt request lines.

–

•

Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.

Provides two software dispatch mechanisms when the CPU VIC port is not used.

–

Index interrupt

Register vectored interrupt

•

Parity protected vector interrupt table against soft errors.

4.15.2 Interrupt Request Assignments

Table 4-24. Interrupt Request Assignments

Modules

Interrupt Sources

Default VIM Interrupt

Channel

ESM

Reserved

RTI

ESM High level interrupt (NMI)

Reserved

0

1

RTI compare interrupt 0

RTI compare interrupt 1

RTI compare interrupt 2

RTI compare interrupt 3

RTI overflow interrupt 0

RTI overflow interrupt 1

Reserved

2

RTI

3

RTI

4

RTI

5

RTI

6

RTI

7

Reserved

GIO

8

GIO interrupt A

9

N2HET

HTU

N2HET level 0 interrupt

HTU level 0 interrupt

MIBSPI1 level 0 interrupt

LIN level 0 interrupt

MIBADC event group interrupt

MIBADC sw group 1 interrupt

DCAN1 level 0 interrupt

SPI2 level 0 interrupt

Reserved

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

MIBSPI1

LIN

MIBADC

DCAN1

SPI2

Reserved

ESM

Reserved

ESM Low level interrupt

Software interrupt (SSI)

PMU interrupt

SYSTEM

CPU

GIO

GIO interrupt B

N2HET

HTU

N2HET level 1 interrupt

HTU level 1 interrupt

MIBSPI1 level 1 interrupt

MIBSPI1

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Table 4-24. Interrupt Request Assignments (continued)

Modules

Interrupt Sources

Default VIM Interrupt

Channel

LIN

LIN level 1 interrupt

MIBADC sw group 2 interrupt

DCAN1 level 1 interrupt

SPI2 level 1 interrupt

MIBADC magnitude compare interrupt

Reserved

27

MIBADC

DCAN1

SPI2

28

29

30

MIBADC

Reserved

DCAN2

Reserved

SPI3

31

32-34

35

DCAN2 level 0 interrupt

Reserved

36

SPI3 level 0 interrupt

SPI3 level 1 interrupt

Reserved

37

SPI3

38

Reserved

DCAN2

Reserved

FMC

39-41

42

DCAN2 level 1 interrupt

Reserved

43-60

61

FSM_DONE interrupt

Reserved

HWAG

62-79

80

HWA_INT_REQ_H

Reserved

DCC

81

DCC done interrupt

Reserved

82

Reserved

eQEPINTn

PBIST

83

eQEP Interrupt

84

PBIST Done Interrupt

Reserved

85

Reserved

HWAG

86-87

88

HWA_INT_REQ_L

Reserved

89-95

NOTE

Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR

entry; therefore only request channels 0..94 can be used and are offset by 1 address in the

VIM RAM.

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4.16 Real Time Interrupt Module

The real-time interrupt (RTI) module provides timer functionality for operating systems and for

benchmarking code. The RTI module can incorporate several counters that define the timebases needed

for scheduling an operating system.

The timers also allow you to benchmark certain areas of code by reading the values of the counters at the

beginning and the end of the desired code range and calculating the difference between the values.

4.16.1 Features

The RTI module has the following features:

•

Two independent 64 bit counter blocks

Four configurable compares for generating operating system ticks. Each event can be driven by either

counter block 0 or counter block 1.

•

Fast enabling/disabling of events

Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block

4.16.2 Block Diagrams

Figure 4-11 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI

module. Both the counter blocks are identical.

31

0

Compare

up counter

RTICPUCx

OVLINTx

31

0

31

0

To Compare

Unit

=

Up counter

RTIUCx

Free running counter

RTIFRCx

RTICLK

31

0

31

0

Capture

up counter

RTICAUCx

Capture

free running counter

RTICAFRCx

CAP event source 0

CAP event source 1

External

control

Figure 4-11. Counter Block Diagram

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31

Update

compare

0

RTIUDCPy

+

31

0

Compare

RTICOMPy

From counter

block 0

=

INTy

From counter

block 1

Compare

control

Figure 4-12. Compare Block Diagram

4.16.3 Clock Source Options

The RTI module uses the RTICLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTICLK by configuring the RCLKSRC register in the

System module at address 0xFFFFFF50. The default source for RTICLK is VCLK.

For more information on clock sources refer to Table 4-8 and Table 4-12.

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4.17 Error Signaling Module

The Error Signaling Module (ESM) manages the various error conditions on the RM4x microcontroller. The

error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be

configured to drive a low level on a dedicated device terminal called nERROR. This can be used as an

indicator to an external monitor circuit to put the system into a safe state.

4.17.1 Features

The features of the Error Signaling Module are:

•

128 interrupt/error channels are supported, divided into 3 different groups

–

64 channels with maskable interrupt and configurable error pin behavior

32 error channels with non-maskable interrupt and predefined error pin behavior

32 channels with predefined error pin behavior only

•

Error pin to signal severe device failure

Configurable timebase for error signal

Error forcing capability

4.17.2 ESM Channel Assignments

The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order

of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest

severity. The device response to each error is determined by the severity group it is connected to.

Table 4-26 shows the channel assignment for each group.

Table 4-25. ESM Groups

ERROR GROUP

Group1

INTERRUPT CHARACTERISTICS

maskable, low or high priority

non-maskable, high priority

no interrupt generated

INFLUENCE ON ERROR PIN

configurable

fixed

Group2

Group3

fixed

Table 4-26. ESM Channel Assignments

ERROR SOURCES

GROUP

Group1

CHANNELS

Reserved

0

1

2

3

4

5

6

FMC - correctable error: bus1 and bus2 interfaces (does not include accesses to

EEPROM bank)

N2HET - parity

HTU - parity

Group1

7

8

HTU - MPU

9

PLL - Slip

10

11

12

13

14

15

16

17

Clock Monitor - interrupt

Reserved

VIM RAM - parity

Reserved

MibSPI1 - parity

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Table 4-26. ESM Channel Assignments (continued)

ERROR SOURCES

GROUP

Group1

CHANNELS

Reserved

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

MibADC - parity

Reserved

DCAN1 - parity

Reserved

DCAN2 - parity

Reserved

RAM even bank (B0TCM) - correctable error

CPU - selftest

RAM odd bank (B1TCM) - correctable error

Reserved

DCC - error

CCM-R4 - selftest

Reserved

FMC - correctable error (EEPROM bank access)

FMC - uncorrectable error (EEPROM bank access)

IOMM - Mux configuration error

Reserved

eFuse farm – this error signal is generated whenever any bit in the eFuse farm

error status register is set. The application can choose to generate and interrupt

whenever this bit is set in order to service any eFuse farm error condition.

eFuse farm - self test error. It is not necessary to generate a separate interrupt

when this bit gets set.

Group1

41

Reserved

Group1

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

58

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Table 4-26. ESM Channel Assignments (continued)

ERROR SOURCES

GROUP

Group1

Group2

Group3

CHANNELS

Reserved

63

0

Reserved

1

CCMR4 - compare

2

Reserved

3

FMC - uncorrectable error (address parity on bus1 accesses)

4

Reserved

5

RAM even bank (B0TCM) - uncorrectable error

6

Reserved

7

RAM odd bank (B1TCM) - uncorrectable error

8

Reserved

9

RAM even bank (B0TCM) - address bus parity error

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0

Reserved

RAM odd bank (B1TCM) - address bus parity error

Reserved

TCM - ECC live lock detect

Reserved

RTI_WWD_NMI

Reserved

eFuse Farm - autoload error

Reserved

1

2

RAM even bank (B0TCM) - ECC uncorrectable error

Reserved

3

4

RAM odd bank (B1TCM) - ECC uncorrectable error

Reserved

5

6

FMC - uncorrectable error: bus1 and bus2 interfaces (does not include address

parity error and errors on accesses to EEPROM bank)

7

Reserved

Group3

8

9

10

11

12

13

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Table 4-26. ESM Channel Assignments (continued)

ERROR SOURCES

Reserved

GROUP

Group3

CHANNELS

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

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4.18 Reset / Abort / Error Sources

Table 4-27. Reset/Abort/Error Sources

ESM HOOKUP

group.channel

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

CPU TRANSACTIONS

User/Privilege

Precise write error (NCNB/Strongly Ordered)

Precise read error (NCB/Device or Normal)

Imprecise write error (NCB/Device or Normal)

Precise Abort (CPU)

Imprecise Abort (CPU)

n/a

User/Privilege

Undefined Instruction Trap

(CPU)⁽¹⁾

Illegal instruction

User/Privilege

n/a

MPU access violation

User/Privilege

SRAM

Abort (CPU)

B0 TCM (even) ECC single error (correctable)

User/Privilege

ESM

1.26

3.3

Abort (CPU), ESM =>

nERROR

B0 TCM (even) ECC double error (non-correctable)

User/Privilege

B0 TCM (even) uncorrectable error (i.e. redundant address

decode)

ESM => NMI => nERROR

2.6

B0 TCM (even) address bus parity error

User/Privilege

ESM => NMI => nERROR

ESM

2.10

1.28

B1 TCM (odd) ECC single error (correctable)

Abort (CPU), ESM =>

nERROR

B1 TCM (odd) ECC double error (non-correctable)

User/Privilege

3.5

B1 TCM (odd) uncorrectable error (i.e. redundant address

decode)

User/Privilege

ESM => NMI => nERROR

2.8

B1 TCM (odd) address bus parity error

2.12

FLASH WITH CPU BASED ECC

FMC correctable error - Bus1 and Bus2 interfaces (does not

include accesses to EEPROM bank)

User/Privilege

ESM

1.6

3.7

FMC uncorrectable error - Bus1 accesses

(does not include address parity error)

Abort (CPU), ESM =>

nERROR

FMC uncorrectable error - Bus2 accesses

(does not include address parity error and EEPROM bank

accesses)

User/Privilege

ESM => nERROR

3.7

FMC uncorrectable error - address parity error on Bus1

accesses

User/Privilege

ESM => NMI => nERROR

2.4

FMC correctable error - Accesses to EEPROM bank

FMC uncorrectable error - Accesses to EEPROM bank

User/Privilege

ESM

1.35

1.36

High-End Timer Transfer Unit (HTU)

NCNB (Strongly Ordered) transaction with slave error response

User/Privilege

Interrupt => VIM

ESM

n/a

1.9

1.8

External imprecise error (Illegal transaction with ok response)

Memory access permission violation

Memory parity error

ESM

N2HET

User/Privilege

MIBSPI

User/Privilege

MIBADC

User/Privilege

DCAN

Memory parity error

ESM

1.7

MibSPI1 memory parity error

MibADC Memory parity error

1.17

1.19

DCAN1 memory parity error

DCAN2 memory parity error

User/Privilege

ESM

1.21

1.23

(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage

of the CPU.

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Table 4-27. Reset/Abort/Error Sources (continued)

ESM HOOKUP

group.channel

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

PLL

PLL slip error

User/Privilege

ESM

1.10

1.11

1.30

CLOCK MONITOR

Clock monitor interrupt

DCC error

User/Privilege

DCC

User/Privilege

CCM-R4

Self test failure

Compare failure

User/Privilege

ESM

1.31

2.2

User/Privilege

ESM => NMI => nERROR

VIM

Memory parity error

User/Privilege

ESM

Reset

ESM

1.15

n/a

VOLTAGE MONITOR

n/a

VMON out of voltage range

CPU Selftest (LBIST) error

Mux configuration error

CPU SELFTEST (LBIST)

User/Privilege

1.27

1.37

PIN MULTIPLEXING CONTROL

User/Privilege

eFuse Controller

User/Privilege

eFuse Controller Autoload error

ESM => nERROR

3.1

eFuse Controller - Any bit set in the error status register

eFuse Controller self-test error

User/Privilege

ESM

1.40

1.41

WINDOWED WATCHDOG

n/a

WWD Non-Maskable Interrupt exception

ESM => NMI => nERROR

2.24

ERRORS REFLECTED IN THE SYSESR REGISTER

Power-Up Reset

n/a

Reset

n/a

Oscillator fail / PLL slip⁽²⁾

Watchdog exception

CPU Reset (driven by the CPU STC)

Software Reset

External Reset

(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

4.19 Digital Windowed Watchdog

This device includes a digital windowed watchdog (DWWD) module that protects against runaway code

execution.

The DWWD module allows the application to configure the time window within which the DWWD module

expects the application to service the watchdog. A watchdog violation occurs if the application services the

watchdog outside of this window, or fails to service the watchdog at all. The application can choose to

generate a system reset or a non-maskable interrupt to the CPU in case of a watchdog violation.

The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog

can only be disabled upon a system reset.

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4.20 Debug Subsystem

4.20.1 Block Diagram

The device contains an ICEPICK module to allow JTAG access to the scan chains.

Boundary Scan I/F

Boundary Scan

BSR/BSDL

Debug

ROM1

TRST

TMS

TCK

RTCK

TDI

TDO

Debug APB

Secondary Tap 0

DAP

APB slave

Cortex

R4

Secondary Tap 2

Test Tap 0

AJSM

eFuse Farm

Figure 4-13. ZWT Debug Subsystem Block Diagram

4.20.2 Debug Components Memory Map

Table 4-28. Debug Components Memory Map

FRAME ADDRESS RANGE

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME ACTUA

MODULE NAME

SIZE

4KB

L SIZE

START

END

CoreSight Debug

ROM

Reads return zeros, writes have no

effect

CSCS0

CSCS1

0xFFA0_0000

0xFFA0_0FFF

4KB

Reads return zeros, writes have no

effect

Cortex-R4 Debug

0xFFA0_1000

0xFFA0_1FFF

4KB

4.20.3 JTAG Identification Code

The JTAG ID code for this device is 0x0B97102F. This is the same as the device ICEPick Identification

Code.

4.20.4 Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus:

Table 4-29. Debug ROM table

ADDRESS

0x000

DESCRIPTION

pointer to Cortex-R4

Reserved

VALUE

0x0000 1003

0x0000 2002

0x0000 3002

0x0000 4002

0x0000 0000

0x001

0x002

Reserved

0x003

Reserved

0x004

end of table

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4.20.5 JTAG Scan Interface Timings

Table 4-30. JTAG Scan Interface Timing⁽¹⁾

No.

Parameter

Min

MAX

Unit

MHz

ns

fTCK

TCK frequency (at HCLKmax)

12

fRTCK

RTCK frequency (at TCKmax and HCLKmax)

Delay time, TCK to RTCK

10

1

2

3

4

5

td(TCK -RTCK)

tsu(TDI/TMS - RTCKr)

th(RTCKr -TDI/TMS)

th(RTCKr -TDO)

td(TCKf -TDO)

24

12

Setup time, TDI, TMS before RTCK rise (RTCKr)

Hold time, TDI, TMS after RTCKr

26

0

ns

Hold time, TDO after RTCKf

0

ns

Delay time, TDO valid after RTCK fall (RTCKf)

ns

(1) Timings for TDO are specified for a maximum of 50pF load on TDO

TCK

RTCK

1

TMS

TDI

2

3

TDO

4

5

Figure 4-14. JTAG Timing

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4.20.6 Advanced JTAG Security Module

This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to

the device’s memory content by allowing users to secure the device after programming.

Flash Module Output

OTP Contents

(example)

. . .

H

L

H

L

H

L

H

Unlock By Scan

Register

H

L

Internal Tie-Offs

(example only)

L

H

UNLOCK

128-bit comparator

Internal Tie-Offs

(example only)

H

L

H

L

H

Figure 4-15. AJSM Unlock

The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP

address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The

outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this

combinational logic is compared against a secret hard-wired 128-bit value. A match results in the

UNLOCK signal being asserted, so that the device is now unsecure.

A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing

a 0 to 1 is not possible since the visible unlock code is stored in the One Time Programmable (OTP) flash

region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the

device.

Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By

Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents

and the Unlock-By-Scan register contents results in the original visible unlock code.

The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).

A secure device only permits JTAG accesses to the AJSM scan chain via the Secondary Tap # 2 of the

ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in

this state.

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4.20.7 Boundary Scan Chain

The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary

scan chain is connected to the Boundary Scan Interface of the ICEPICK module.

Device Pins (conceptual)

TRST

TMS

TCK

TDI

Boundary

Scan

Boundary Scan Interface

TDO

RTCK

TDI

TDO

BSDL

Figure 4-16. Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers via TDI, and out via TDO.

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5 Peripheral Information and Electrical Specifications

5.1 Peripheral Legend

Table 5-1. Peripheral Legend

Abbreviation

Full Name

MibADC

CCM-R4

CRC

Multi-Buffered Analog to Digital Converter

CPU Compare Module – CortexR4

Cyclic Redundancy Check

DCAN

DCC

Controller Area Network

Dual Clock Comparator

ESM

Error Signaling Module

GIO

General-Purpose Input/Output

High End Timer Transfer Unit

Local Interconnect Network

Multi-Buffered Serial Peripheral Interface

Platform High End Timer

HTU

LIN

MibSPI

N2HET

RTI

Real-Time Interrupt Module

Serial Communications Interface

Serial Peripheral Interface

SCI

SPI

VIM

Vectored Interrupt Manager

Enhanced Quadrature Encoder Pulse

eQEP

5.2 Multi-Buffered 12-bit Analog-to-Digital Converter

The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that

enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could

be present on V_SSand V_CCfrom coupling into the A-to-D analog stage. All A-to-D specifications are given

with respect to AD_REFLOunless otherwise noted.

Table 5-2. MibADC Overview

Description

Resolution

Value

12 bits

Assured

Monotonic

Output conversion code

00h to FFFh [00 for V_AI≤ AD_REFLO; FFF for V_AI≥ AD_REFHI]

5.2.1 Features

•

12-bit resolution

AD_REFHIand AD_REFLOpins (high and low reference voltages)

Total Sample/Hold/Convert time: 600ns Typical Minimum at 30MHz ADCLK

One memory region per conversion group is available (event, group 1, group 2)

Allocation of channels to conversion groups is completely programmable

Memory regions are serviced by interrupt

Programmable interrupt threshold counter is available for each group

Programmable magnitude threshold interrupt for each group for any one channel

Option to read either 8-bit, 10-bit or 12-bit values from memory regions

Single or continuous conversion modes

Embedded self-test

Embedded calibration logic

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•

Enhanced power-down mode

Optional feature to automatically power down ADC core when no conversion is in progress

External event pin (ADEVT) programmable as general-purpose I/O

–

5.2.2 Event Trigger Options

The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3

groups can be configured to be hardware event-triggered. In that case, the application can select from

among 8 event sources to be the trigger for a group's conversions.

5.2.2.1 MIBADC Event Trigger Hookup

Table 5-3. MIBADC Event Trigger Hookup

Event #

Source Select Bits For G1, G2 Or Event

(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])

Trigger

1

2

3

4

5

6

7

8

000

001

010

011

100

101

110

111

ADEVT

N2HET[8]

N2HET[10]

RTI compare 0 interrupt

N2HET[12]

N2HET[14]

N2HET[17]

N2HET[19]

NOTE

For ADEVT, N2HET trigger sources, the connection to the MibADC module trigger input is

made from the output side of the input buffer. This way, a trigger condition can be generated

either by configuring the function as output onto the pad, or by driving the function from an

external trigger source as input. If the mux controller module is used to select different

functionality instead of ADEVT or N2HET[x], care must be taken to disable these signals

from triggering conversions; there is no multiplexing on input connections.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

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5.2.3 ADC Electrical and Timing Specifications

Table 5-4. MibADC Recommended Operating Conditions

Parameter

MIN

AD_REFLO

V_SSAD

AD_REFLO

- 2

MAX

V_CCAD

AD_REFHI

2

Unit

V

AD_REFHI

AD_REFLO

V_AI

A-to-D high-voltage reference source

A-to-D low-voltage reference source

Analog input voltage

V

I_AIC

Analog input clamp current

mA

(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)

Table 5-5. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions⁽¹⁾

Parameter

Description/Conditions

MIN

Type MAX

Unit

R_mux

Analog input mux on-

resistance

See Figure 5-1

95

250

Ω

R_samp

ADC sample switch on-

resistance

See Figure 5-1

60

250

Ω

C_mux

C_samp

I_AIL

Input mux capacitance

See Figure 5-1

7

8

16

13

pF

nA

ADC sample capacitance

See Figure 5-1

Analog off-state input

leakage current

V_CCAD= 3.6V maximum

V_SSAD< V_IN< V_SSAD

100mV

+

-300

-200

-8

-1

200

V_SSAD+ 100mV < V_IN

V_CCAD- 200mV

<

-0.3

1

200

500

2

nA

µA

V_CCAD- 200mV < V_IN

V_CCAD

<

I_AOSB

Analog on-state input bias

V_CCAD= 3.6V maximum

V_SSAD< V_IN< V_SSAD

100mV

+

V_SSAD+ 100mV < V_IN

V_CCAD- 200mV

<

-4

2

V_CCAD- 200mV < V_IN

V_CCAD

<

-4

12

I_ADREFHI

I_CCAD

AD_REFHIinput current

Static supply current

AD_REFHI= V_CCAD, AD_REFLO= V_SSAD

Normal operating mode

3

mA

See

Sectio

n 3.5

ADC core in power down mode

5

µA

(1) 1 LSB = (AD_REFHI– AD_REFLO)/ 2ⁿwhere n = 10 in 10-bit mode and 12 in 12-bit mode

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R_ext

P_in

R_mux

S_mux

V_S1

23*I_AIL

C_ext

On-State

Leakage

S_mux

R_ext

P_in

R_mux

V_S2

I_AIL

C_ext

I_AIL

Off-State

Leakages

S_mux

R_ext

P_in

R_mux

S_samp

R_samp

V_S24

I_AIL

C_samp

C_mux

C_ext

I_AIL

Figure 5-1. MibADC Input Equivalent Circuit

Table 5-6. MibADC Timing Specifications

Parameter

Cycle time, MibADC clock

MIN

33

NOM

MAX

Unit

ns

(1)

t_c(ADCLK)

(2)

t_d(SH)

Delay time, sample and hold

time

200

ns

t_d(PU-ADV)

Delay time from ADC power on

until first input can be sampled

1

µs

12-bit mode

t_d(C)

Delay time, conversion time

400

600

ns

(3)

t_d(SHC)

Delay time, total sample/hold

and conversion time

10-bit mode

t_d(C)

Delay time, conversion time

330

530

ns

(4)

t_d(SHC)

Delay time, total sample/hold

and conversion time

(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits

4:0.

(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each

conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as

well as the ADC’s internal impedance.

(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the

prescale settings.

(4) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the

prescale settings.

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Table 5-7. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions

Parameter

Description/Conditions

MIN

Type

MAX

Unit

CR

Conversion range AD_REFHI- AD_REFLO

3

3.6

V

over which

specified

accuracy is

maintained

Z_SET

Offset Error

Difference between the first ideal

transition (from code 000h to 001h)

and the actual transition

10-bit

mode

With ADC

Calibration

1

2

4

LSB

Without ADC

Calibration

12-bit

mode

With ADC

Calibration

Without ADC

Calibration

F_SET

E_DNL

E_INL

Gain Error

Differential

Difference between the last ideal

transition (from code FFEh to FFFh)

and the actual transition minus offset.

10-bit mode

12-bit mode

2

3

LSB

Difference between the actual step

10-bit mode

12-bit mode

± 1.5

± 2

LSB

nonlinearity error width and the ideal value. (See

Figure 5-2)

Integral

Maximum deviation from the best

10-bit mode

12-bit mode

± 2

LSB

nonlinearity error straight line through the MibADC.

MibADC transfer characteristics,

excluding the quantization error. (See

Figure 5-3)

E_TOT

Total unadjusted

error

Maximum value of the difference

between an analog value and the

ideal midstep value. (See Figure 5-4)

10-bit

mode

With ADC

Calibration

± 2

± 4

± 7

LSB

Without ADC

Calibration

12-bit

mode

With ADC

Calibration

Without ADC

Calibration

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5.2.4 Performance (Accuracy) Specifications

5.2.4.1 MibADC Nonlinearity Errors

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The differential nonlinearity error shown in Figure Figure 5-2 (sometimes referred to as differential

linearity) is the difference between an actual step width and the ideal value of 1 LSB.

0 ... 110

0 ... 101

0 ... 100

0 ... 011

Differential Linearity

Error (–½ LSB)

1 LSB

0 ... 010

Differential Linearity

Error (–½ LSB)

0 ... 001

0 ... 000

1 LSB

0

1

2

3

4

5

Analog Input Value (LSB)

n

NOTE A: 1 LSB = (AD_REFHI– AD_REFLO)/2 where n=10 in 10-bit mode and 12 in 12-bit mode

Figure 5-2. Differential Nonlinearity (DNL) Error

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The integral nonlinearity error shown in Figure Figure 5-3 (sometimes referred to as linearity error) is the

deviation of the values on the actual transfer function from a straight line.

0 ... 111

0 ... 110

Ideal

Transition

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

Actual

Transition

At Transition

011/100

(–½ LSB)

End-Point Lin. Error

At Transition

001/010 (–1/4 LSB)

0

1

2

3

4

5

6

7

Analog Input Value (LSB)

n

NOTE A: 1 LSB = (AD_REFHI– AD_REFLO)/2 where n=10 in 10-bit mode and 12 in 12-bit mode

Figure 5-3. Integral Nonlinearity (INL) Error

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5.2.4.2 MibADC Total Error

The absolute accuracy or total error of an MibADC as shown in Figure Figure 5-4 is the maximum value of

the difference between an analog value and the ideal midstep value.

0 ... 111

0 ... 110

0 ... 101

0 ... 100

Total Error

At Step 0 ... 101

(–1 1/4 LSB)

0 ... 011

0 ... 010

Total Error

At Step

0 ... 001 (1/2 LSB)

0 ... 001

0 ... 000

0

1

2

3

4

5

6

7

Analog Input Value (LSB)

n

NOTE A: 1 LSB = (AD_REFHI– AD_REFLO)/2 where n=10 in 10-bit mode and 12 in 12-bit mode

Figure 5-4. Absolute Accuracy (Total) Error

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5.3 General-Purpose Input/Output

The GPIO module on this device supports one port GIOA. The I/O pins are bidirectional and bit-

programmable. GIOA supports external interrupt capability.

5.3.1 Features

The GPIO module has the following features:

•

Each IO pin can be configured as:

–

Input

Output

Open Drain

•

The interrupts have the following characteristics:

–

Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)

Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)

Individual interrupt flags (set in GIOFLG register)

Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers

respectively

–

Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers

•

Internal pullup/pulldown allows unused I/O pins to be left unconnected

For information on input and output timings see Section 3.8 and Section 3.9

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5.4 Enhanced High-End Timer (N2HET)

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,

capture or compare inputs, or general-purpose I/O.. It is especially well suited for applications requiring

multiple sensor information and drive actuators with complex and accurate time pulses.

5.4.1 Features

The N2HET module has the following features:

•

Programmable timer for input and output timing functions

Reduced instruction set (30 instructions) for dedicated time and angle functions

128 words of instruction RAM protected by parity

User defined number of 25-bit virtual counters for timer, event counters and angle counters

7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual

counters

•

Up to 19 pins usable for input signal measurements or output signal generation

Programmable suppression filter for each input pin with adjustable limiting frequency

Low CPU overhead and interrupt load

Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)

Diagnostic capabilities with different loopback mechanisms and pin status readback functionality

5.4.2 N2HET RAM Organization

The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one

RAM address may be written while another address is read. The RAM words are 96-bits wide, which are

split into three 32-bit fields (program, control, and data).

5.4.3 Input Timing Specifications

The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.

1

N2HETx

3

4

2

Figure 5-5. N2HET Input Capture Timings

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Table 5-8. Dynamic Characteristics for the N2HET Input Capture Functionality

PARAMETER

MIN^{(1) (2)}

MAX^{(1) (2)}

UNIT

1

2

3

4

Input signal period, PCNT or WCAP for rising edge (hr)(lr) t_c(VCLK2)+ 2

to rising edge

2²⁵(hr)(lr)t_c(VCLK2)- 2

ns

Input signal period, PCNT or WCAP for falling edge (hr) (lr) t_c(VCLK2)+ 2

to falling edge

2²⁵(hr)(lr) t_c(VCLK2)- 2

ns

Input signal high phase, PCNT or WCAP for rising

edge to falling edge

2(hr) t_c(VCLK2)+ 2

Input signal low phase, PCNT or WCAP for falling

edge to rising edge

2(hr) t_c(VCLK2)+ 2

(1) hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).

(2) lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR)

5.4.4 N2HET Checking

5.4.4.1 Output Monitoring using Dual Clock Comparator (DCC)

N2HET[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure

the frequency of the pulse-width modulated (PWM) signal on N2HET[31].

N2HET[31] can be configured to be an internal-only channel. That is, the connection to the DCC module is

made directly from the output of the N2HET module (from the input of the output buffer).

For more information on DCC see Section 4.6.3.

5.4.5 Disabling N2HET Outputs

Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET

module provides this capability via the "Pin Disable" input signal. This signal, when driven low, causes the

N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. Please refer to the

device Technical Reference Manual for more details on the "N2HET Pin Disable" feature.

GIOA[5] and EQEPERR are connected to the "Pin Disable" input for N2HET. In the case of GIOA[5]

connection, this connection is made from the output of the input buffer. In the case of EQEPERR, the

EQEPERR output signal is asserted in the event of a phase error. This signal is inverted and double-

synchronized to VCLK2 for input into the N2HET PIN_nDISABLE port.

The PIN_nDISABLE port input source is selectable between the GIOA[5] and EQEPERR sources. This is

achieved via the PINMMR9[1:0] bits.

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5.4.6 High-End Timer Transfer Unit (N2HET)

A High End Timer Transfer Unit (N2HET) can perform DMA type transactions to transfer N2HET data to or

from main memory. A Memory Protection Unit (MPU) is built into the N2HET.

5.4.6.1 Features

CPU independent

•

Master Port to access system memory

8 control packets supporting dual buffer configuration

Control packet information is stored in RAM protected by parity

Event synchronization (N2HET transfer requests)

Supports 32 or 64 bit transactions

Addressing modes for N2HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or

64bit)

•

One shot, circular and auto switch buffer transfer modes

Request lost detection

5.4.6.2 Trigger Connections

Table 5-9. N2HET Request Line Connection

Modules

N2HET

Request Source

HTUREQ[0]

HTUREQ[1]

HTUREQ[2]

HTUREQ[3]

HTUREQ[4]

HTUREQ[5]

HTUREQ[6]

HTUREQ[7]

HTU Request

HTU DCP[0]

HTU DCP[1]

HTU DCP[2]

HTU DCP[3]

HTU DCP[4]

HTU DCP[5]

HTU DCP[6]

HTU DCP[7]

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5.5 Controller Area Network (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication

protocol that efficiently supports distributed real-time control with robust communication rates of up to 1

megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh

environments (e.g., automotive and industrial fields) that require reliable serial communication or

multiplexed wiring.

5.5.1 Features

Features of the DCAN module include:

•

Supports CAN protocol version 2.0 part A, B

Bit rates up to 1 MBit/s

The CAN kernel can be clocked by the oscillator for baud-rate generation.

32 and 16 mailboxes on DCAN1 and DCAN2, respectively

Individual identifier mask for each message object

Programmable FIFO mode for message objects

Programmable loop-back modes for self-test operation

Automatic bus on after Bus-Off state by a programmable 32-bit timer

Message RAM protected by parity

Direct access to Message RAM during test mode

CAN Rx / Tx pins configurable as general purpose IO pins

Message RAM Auto Initialization

For more information on the DCAN see the device Technical Reference Manual.

5.5.2 Electrical and Timing Specifications

Table 5-10. Dynamic Characteristics for the DCANx TX and RX pins

Parameter

MIN

MAX

15

Unit

ns

t_d(CANnTX)

t_d(CANnRX)

Delay time, transmit shift register to CANnTX pin⁽¹⁾

Delay time, CANnRX pin to receive shift register

5

ns

(1) These values do not include rise/fall times of the output buffer.

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5.6 Local Interconnect Network Interface (LIN)

The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is

an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility.

The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn

to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-

line.

The LIN standard is based on the SCI (UART) serial data link format. The communication concept is

single-master/multiple-slave with a message identification for multi-cast transmission between any network

nodes.

5.6.1 LIN Features

The following are features of the LIN module:

•

Compatible to LIN 1.3, 2.0 and 2.1 protocols

Multi-buffered receive and transmit units

Identification masks for message filtering

Automatic Master Header Generation

–

Programmable Synch Break Field

Synch Field

Identifier Field

•

Slave Automatic Synchronization

–

Synch break detection

Optional baudrate update

Synchronization Validation

2³¹programmable transmission rates with 7 fractional bits

•

Error detection

2 Interrupt lines with priority encoding

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5.7 Multi-Buffered / Standard Serial Peripheral Interface

The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of

programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.

Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display

drivers, and analog-to-digital converters.

5.7.1 Features

Both Standard and MibSPI modules have the following features:

•

16-bit shift register

Receive buffer register

8-bit baud clock generator, supports max up to 20Mhz baud rate

SPICLK can be internally-generated (master mode) or received from an external clock source (slave

mode)

•

Each word transferred can have a unique format

SPI I/Os not used in the communication can be used as digital input/output signals

Table 5-11. MibSPI/SPI Default Configurations

MibSPIx/SPIx

MibSPI1

I/Os

MIBSPI1SIMO[0], MIBSPI1SOMI[0], MIBSPI1CLK, MIBSPI1nCS[3:0], MIBSPI1nENA

SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[0]

SPI2

SPI3

SPI3SIMO, SPI3SOMI, SPI3CLK, SPI3nENA, SPI3nCS[0]

5.7.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a

16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer

RAM can be partitioned into multiple transfer group with variable number of buffers each.

5.7.3 MibSPI Transmit Trigger Events

Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event

and a trigger source can be chosen. A trigger event can be, for example, a rising edge or a permanent low

level at a selectable trigger source. Up to 15 trigger sources are available which can be utilized by each

transfer group. These trigger options are listed in Table 5-12 and .

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5.7.3.1 MIBSPI1 Event Trigger Hookup

Table 5-12. MIBSPI1 Event Trigger Hookup

Event #

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

EVENT9

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

TGxCTRL TRIGSRC[3:0]

Trigger

No trigger source

GIOA[0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

N2HET[8]

N2HET[10]

N2HET[12]

N2HET[14]

N2HET[16]

N2HET[18]

Intern Tick counter

NOTE

For N2HET trigger sources, the connection to the MibSPI1 module trigger input is made from

the input side of the output buffer (at the N2HET module boundary). This way, a trigger

condition can be generated even if the N2HET signal is not selected to be output on the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin, or by driving the GIOx pin from an external trigger

source.

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5.7.4 MibSPI/SPI Master Mode I/O Timing Specifications

Table 5-13. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO

= output, and SPISOMI = input)^(1)(2)(3)

NO. Parameter

t_c(SPC)M

2⁽⁵⁾t_w(SPCH)M

MIN

MAX

Unit

ns

1

Cycle time, SPICLK⁽⁴⁾

40

256t_c(VCLK)

0.5t_c(SPC)M+ 3

Pulse duration, SPICLK high (clock

polarity = 0)

0.5t_c(SPC)M– t_r(SPC)M– 3

ns

t_w(SPCL)M

3⁽⁵⁾t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK low (clock

polarity = 1)

0.5t_c(SPC)M– t_f(SPC)M– 3

0.5t_c(SPC)M– t_r(SPC)M– 3

0.5t_c(SPC)M– 6

0.5t_c(SPC)M+ 3

Pulse duration, SPICLK low (clock

polarity = 0)

ns

Pulse duration, SPICLK high (clock

polarity = 1)

4⁽⁵⁾t_{d(SPCH-SIMO)M}Delay time, SPISIMO valid before

SPICLK low (clock polarity = 0)

t_{d(SPCL-SIMO)M}Delay time, SPISIMO valid before

SPICLK high (clock polarity = 1)

5⁽⁵⁾t_{v(SPCL-SIMO)M}

0.5t_c(SPC)M– 6

Valid time, SPISIMO data valid after

SPICLK low (clock polarity = 0)

0.5t_c(SPC)M– t_f(SPC)– 4

0.5t_c(SPC)M– t_r(SPC)– 4

t_f(SPC)+ 2.2

t_{v(SPCH-SIMO)M}Valid time, SPISIMO data valid after

SPICLK high (clock polarity = 1)

6⁽⁵⁾t_{su(SOMI-SPCL)M}Setup time, SPISOMI before SPICLK

low (clock polarity = 0)

t_{su(SOMI-SPCH)M}Setup time, SPISOMI before SPICLK

high (clock polarity = 1)

7⁽⁵⁾t_{h(SPCL-SOMI)M}Hold time, SPISOMI data valid after

SPICLK low (clock polarity = 0)

t_r(SPC)+ 2.2

10

t_{h(SPCH-SOMI)M}Hold time, SPISOMI data valid after

SPICLK high (clock polarity = 1)

8⁽⁶⁾t_C2TDELAY

10

Setup time CS active

until SPICLK high

(clock polarity = 0)

CSHOLD = 0 C2TDELAY*t_c(VCLK)+ 2*t_c(VCLK)

- t_f(SPICS)+ t_r(SPC)– 7

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)+ 5.5

-

CSHOLD = 1 C2TDELAY*t_c(VCLK)+ 3*t_c(VCLK)

- t_f(SPICS)+ t_r(SPC)– 7

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)+ 5.5

Setup time CS active

until SPICLK low

CSHOLD = 0 C2TDELAY*t_c(VCLK)+ 2*t_c(VCLK)

- t_f(SPICS)+ t_f(SPC)– 7

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)+ 5.5

(clock polarity = 1)

CSHOLD = 1 C2TDELAY*t_c(VCLK)+ 3*t_c(VCLK)

- t_f(SPICS)+ t_f(SPC)– 7

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)+ 5.5

9⁽⁶⁾t_T2CDELAY

Hold time SPICLK low until CS inactive

(clock polarity = 0)

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_f(SPC)+ t_r(SPICS)- 7

+

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_f(SPC)+ t_r(SPICS)+ 11

+

ns

-

Hold time SPICLK high until CS

inactive (clock polarity = 1)

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_r(SPC)+ tr(SPICS) - 7

+

0.5*t_c(SPC)M+

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_r(SPC)+ t_r(SPICS)+ 11

10

11

t_SPIENA

SPIENAn Sample point

(C2TDELAY+1) * t_c(VCLK)

t_f(SPICS)– 29

-

(C2TDELAY+1)*t_c(VCLK)

ns

t_SPIENAW

SPIENAn Sample point from write to

buffer

(C2TDELAY+2)*t_c(VCLK)

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.

(2) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

(3) For rise and fall timings, see Table 3-5.

(4) When the SPI is in Master mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_c(VCLK)≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(VCLK)≥ 40 ns.

The external load on the SPICLK pin must be less than 60pF.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISIMO

Master Out Data Is Valid

6

7

Master In Data

Must Be Valid

SPISOMI

Figure 5-6. SPI Master Mode External Timing (CLOCK PHASE = 0)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

8

9

10

11

SPIENAn

Figure 5-7. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)

84

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Table 5-14. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO

= output, and SPISOMI = input)^(1)(2)(3)

NO.

Parameter

MIN

MAX

Unit

ns

(4)

1

t_c(SPC)M

Cycle time, SPICLK

40

256t_c(VCLK)

0.5t_c(SPC)M+ 3

2⁽⁵⁾t_w(SPCH)M

t_w(SPCL)M

3⁽⁵⁾t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high (clock

polarity = 0)

0.5t_c(SPC)M– t_r(SPC)M– 3

ns

Pulse duration, SPICLK low (clock

polarity = 1)

0.5t_c(SPC)M– t_f(SPC)M– 3

0.5t_c(SPC)M– t_r(SPC)M– 3

0.5t_c(SPC)M– 6

0.5t_c(SPC)M+ 3

Pulse duration, SPICLK low (clock

polarity = 0)

ns

Pulse duration, SPICLK high (clock

polarity = 1)

4⁽⁵⁾t_{v(SIMO-SPCH)M}

Valid time, SPICLK high after

SPISIMO data valid (clock polarity =

0)

t_{v(SIMO-SPCL)M}

Valid time, SPICLK low after

0.5t_c(SPC)M– 6

SPISIMO data valid (clock polarity =

1)

5⁽⁵⁾t_{v(SPCH-SIMO)M}

t_{v(SPCL-SIMO)M}

6⁽⁵⁾t_{su(SOMI-SPCH)M}

t_{su(SOMI-SPCL)M}

7⁽⁵⁾t_{v(SPCH-SOMI)M}

t_{v(SPCL-SOMI)M}

Valid time, SPISIMO data valid after

SPICLK high (clock polarity = 0)

0.5t_c(SPC)M– t_r(SPC)– 4

ns

Valid time, SPISIMO data valid after

SPICLK low (clock polarity = 1)

0.5t_c(SPC)M– t_f(SPC)– 4

Setup time, SPISOMI before

SPICLK high (clock polarity = 0)

t_r(SPC)+ 2.2

t_f(SPC)+ 2.2

10

Setup time, SPISOMI before

SPICLK low (clock polarity = 1)

Valid time, SPISOMI data valid after

SPICLK high (clock polarity = 0)

Valid time, SPISOMI data valid after

SPICLK low (clock polarity = 1)

10

8⁽⁶⁾t_C2TDELAY

Setup time CS

active until SPICLK

high (clock polarity =

0)

CSHOLD = 0

CSHOLD = 1

CSHOLD = 0

CSHOLD = 1

0.5*t_c(SPC)M

+

0.5*t_c(SPC)M+

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)+ 5.5

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)– 7

-

0.5*t_c(SPC)M

+

0.5*t_c(SPC)M+

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)+ 5.5

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)– 7

Setup time CS

active until SPICLK

low (clock polarity =

1)

0.5*t_c(SPC)M

+

0.5*t_c(SPC)M

+

ns

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)– 7

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)+ 5.5

-

0.5*t_c(SPC)M

+

0.5*t_c(SPC)M+

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)+ 5.5

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)– 7

-

9⁽⁶⁾t_T2CDELAY

Hold time SPICLK low until CS

inactive (clock polarity = 0)

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPC)+ t_r(SPICS)

7

+

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPC)+ t_r(SPICS)

11

+

ns

+

Hold time SPICLK high until CS

inactive (clock polarity = 1)

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPC)+ t_r(SPICS)

7

+

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPC)+ t_r(SPICS)

11

+

10 t_SPIENA

SPIENAn Sample Point

(C2TDELAY+1)* t_c(VCLK)

t_f(SPICS)– 29

-

(C2TDELAY+1)*t_c(VCLK)

ns

11 t_SPIENAW

SPIENAn Sample point from write to

buffer

(C2TDELAY+2)*t_c(VCLK)

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

(3) For rise and fall timings, see the Table 3-5.

(4) When the SPI is in Master mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_c(VCLK)≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(VCLK)≥ 40 ns.

The external load on the SPICLK pin must be less than 60pF.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

Master Out Data Is Valid

Data Valid

SPISIMO

SPISOMI

6

7

Master In Data

Must Be Valid

Figure 5-8. SPI Master Mode External Timing (CLOCK PHASE = 1)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

8

9

10

11

SPIENAn

Figure 5-9. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)

86

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5.7.5 SPI Slave Mode I/O Timings

Table 5-15. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =

input, and SPISOMI = output)^(1)(2)(3)(4)

NO.

1

Parameter

t_c(SPC)S

MIN

40

MAX

Unit

ns

Cycle time, SPICLK⁽⁵⁾

2⁽⁶⁾

t_w(SPCH)S

t_w(SPCL)S

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

14

ns

14

3⁽⁶⁾

4⁽⁶⁾

t_w(SPCL)S

14

ns

t_w(SPCH)S

t_{d(SPCH-SOMI)S}

14

Delay time, SPISOMI valid after SPICLK high (clock

polarity = 0)

t_rf(SOMI)+ 20

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

t_{su(SIMO-SPCL)S}

t_{su(SIMO-SPCH)S}

t_{h(SPCL-SIMO)S}

t_{h(SPCH-SIMO)S}

t_{d(SPCL-SENAH)S}

t_{d(SPCH-SENAH)S}

t_{d(SCSL-SENAL)S}

Delay time, SPISOMI valid after SPICLK low (clock polarity

= 1)

5⁽⁶⁾

6⁽⁶⁾

7⁽⁶⁾

8

Hold time, SPISOMI data valid after SPICLK high (clock

polarity =0)

2

ns

Hold time, SPISOMI data valid after SPICLK low (clock

polarity =1)

2

Setup time, SPISIMO before SPICLK low (clock polarity =

0)

4

Setup time, SPISIMO before SPICLK high (clock polarity =

1)

4

2

Hold time, SPISIMO data valid after SPICLK low (clock

polarity = 0)

Hold time, SPISIMO data valid after S PICLK high (clock

polarity = 1)

2

Delay time, SPIENAn high after last SPICLK low (clock

polarity = 0)

1.5t_c(VCLK)

t_f(ENAn)

2.5t_c(VCLK)+t_r(ENAn)

+

22

Delay time, SPIENAn high after last SPICLK high (clock

polarity = 1)

2.5t_c(VCLK)+ t_r(ENAn)

22

+

9

Delay time, SPIENAn low after SPICSn low (if new data

has been written to the SPI buffer)

t_c(VCLK)+t_f(ENAn)+27

(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.

(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S≥ (PS + 1) t_c(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3) For rise and fall timings, see Table 3-5.

(4) t_c(VCLK)= interface clock cycle time = 1 /f_(VCLK)

(5) When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_c(VCLK)≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)S= 2t_c(VCLK)≥ 40ns.

(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI Data Is Valid

SPISOMI

6

7

SPISIMO Data

Must Be Valid

SPISIMO

Figure 5-10. SPI Slave Mode External Timing (CLOCK PHASE = 0)

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

8

SPIENAn

SPICSn

9

Figure 5-11. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

88

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Table 5-16. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =

input, and SPISOMI = output)^(1)(2)(3)(4)

NO. Parameter

t_c(SPC)S

2⁽⁶⁾t_w(SPCH)S

t_w(SPCL)S

3⁽⁶⁾t_w(SPCL)S

t_w(SPCH)S

MIN

40

MAX

Unit

ns

1

Cycle time, SPICLK⁽⁵⁾

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

14

ns

14

ns

14

4⁽⁶⁾t_{d(SOMI-SPCL)S}

Dealy time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

t_rf(SOMI)+ 20

t_{d(SOMI-SPCH)S}

5⁽⁶⁾t_{h(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

Delay time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity =0)

2

ns

Hold time, SPISOMI data valid after SPICLK low (clock

polarity =1)

2

6⁽⁶⁾t_{su(SIMO-SPCH)S}Setup time, SPISIMO before SPICLK high (clock

polarity = 0)

4

t_{su(SIMO-SPCL)S}Setup time, SPISIMO before SPICLK low (clock polarity

= 1)

7⁽⁶⁾t_{v(SPCH-SIMO)S}

4

2

High time, SPISIMO data valid after SPICLK high

(clock polarity = 0)

t_{v(SPCL-SIMO)S}

High time, SPISIMO data valid after SPICLK low (clock

polarity = 1)

2

8

t_{d(SPCH-SENAH)S}Delay time, SPIENAn high after last SPICLK high

(clock polarity = 0)

1.5t_c(VCLK)

t_f(ENAn)

t_c(VCLK)

2.5t_c(VCLK)+t_r(ENAn)+ 22

t_c(VCLK)+t_f(ENAn)+ 27

t_{d(SPCL-SENAH)S}Delay time, SPIENAn high after last SPICLK low (clock

polarity = 1)

9

t_{d(SCSL-SENAL)S}Delay time, SPIENAn low after SPICSn low (if new data

has been written to the SPI buffer)

ns

10

t_{d(SCSL-SOMI)S}

Delay time, SOMI valid after SPICSn low (if new data

has been written to the SPI buffer)

2t_c(VCLK)+t_rf(SOMI)+ 28

(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3) For rise and fall timings, see Table 3-5.

(4) t_c(VCLK)= interface clock cycle time = 1 /f_(VCLK)

(5) When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_c(VCLK)≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)S= 2t_c(VCLK)≥ 40ns.

(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

Figure 5-12. SPI Slave Mode External Timing (CLOCK PHASE = 1)

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

8

SPIENAn

SPICSn

9

10

SPISOMI

Slave Out Data Is Valid

Figure 5-13. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)

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5.8 Enhanced Quadrature Encoder (eQEP)

Figure 5-14 shows the eQEP module interconnections on the device.

VBUSP Interface

EQEPA

EQEPB

EQEPI

EQEPIO

EQEPIOE

EQEPENCLK

EQEP

Module

CDDISx.9

EQEP

CLK

GATE

VCLK

ACK

CLKSTOP_REQ

I/O

MUX

CTRL

SYS_nRST

EQEPS

EQEPSO

EQEPSOE

EQEPINTn

VIM

nEQEPERR

_SYNC

EQEPERR

NHET

nDIS

GIOA[5]

VCLK2

NHETnDIS_SEL

Figure 5-14. eQEP Module Interconnections

5.8.1 Clock Enable Control for eQEPx Modules

The device level control of the eQEP clock is accomplished through the enable/disable of the VCLK clock

domain for eQEP only. This is realized using bit 9 of the CLKDDIS register. The eQEP clock source is

enabled by default.

5.8.2 Using eQEPx Phase Error

The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs

EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection

multiplexor. As shown in Figure 5-14, the output of this selection multiplexor is inverted and connected to

the N2HET module. This connection allows the application to define the response to a phase error

indicated by the eQEP modules.

5.8.3 Input Connections to eQEPx Modules

The input connections to each of the eQEP modules can be selected between a double-VCLK-

synchronized input or a double-VCLK-synchronized and filtered input, as shown in Table 5-17.

Table 5-17. Device-Level Input Synchronization

Input Signal

Control for Double-Synchronized Connection to

eQEPx

Control for Double-Synchronized and Filtered

Connection to eQEPx

eQEPA

eQEPB

eQEPI

eQEPS

PINMMR8[0] = 1

PINMMR8[8] = 1

PINMMR8[16] = 1

PINMMR8[24] = 1

PINMMR8[0] = 0 and PINMMR8[1] = 1

PINMMR8[8] = 0 and PINMMR8[9] = 1

PINMMR8[16] = 0 and PINMMR8[17] = 1

PINMMR8[24] = 0 and PINMMR8[25] = 1

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5.8.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing

Table 5-18. eQEPx Timing Requirements

PARAMETER

QEP input period

TEST CONDITIONS

MIN

MAX

UNIT

cycles

t_w(QEPP)

Synchronous

2 t_c(VCLK)

Synchronous, with input 2 t_c(VCLK)+ filter width

filter

t_w(INDEXH)

QEP Index Input High Time

QEP Index Input Low Time

Synchronous

2 t_c(VCLK)

cycles

Synchronous, with input 2 t_c(VCLK)+ filter width

filter

t_w(INDEXL)

Synchronous

2 t_c(VCLK)

cycles

Synchronous, with input 2 t_c(VCLK)+ filter width

filter

t_w(STROBH)QEP Strobe Input High Time

t_w(STROBL)QEP Strobe Input Low Time

Synchronous

2 t_c(VCLK)

cycles

Synchronous, with input 2 t_c(VCLK)+ filter width

filter

Synchronous

2 t_c(VCLK)

cycles

Synchronous, with input 2 t_c(VCLK)+ filter width

filter

Table 5-19. eQEPx Switching Characteristics

PARAMETER

MIN

MAX

UNIT

cycles

t_d(CNTR)xin

Delay time, external clock to counter increment

4 t_c(VCLK)

6 t_c(VCLK)

t_{d(PCS-OUT)QEP}

Delay time, QEP input edge to position compare sync output

92

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6 Device and Documentation Support

6.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of

all devices.Each device has one of three prefixes: X, P, or null (no prefix) (for example, xRM46L852).

These prefixes represent evolutionary stages of product development from engineering prototypes

through fully qualified production devices/tools.

Device development evolutionary flow:

x

Experimental device that is not necessarily representative of the final device's electrical

specifications and may not use production assembly flow.

P

Prototype device that is not necessarily the final silicon die and may not necessarily meet

final electrical specifications.

null

Fully-qualified production device.

x and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices have been characterized fully, and the quality and reliability of the device have

been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to

be used.

6.2 Device Identification

The figure below illustrates the numbering and symbol nomenclature for the RM42L432 .

RM 4 2 L 4 3 2 PZ T R

Prefix:

x = Not Qualified

Removed when qualified

Shipping Options:

R = Tape and Reel

RM = Real Time Microcontroller

Temperature Range:

T = -40...+105^oC

CPU:

4 = ARM Cortex-R4

Package Type:

PZ = 100 Pin Package

Series Number

Architecture:

L = Lockstep

Reserved

Flash / RAM Size:

4 = 384kB flash, 32kB RAM

Figure 6-1. Device Numbering Conventions

6.2.1 Device Identification Code Register

The device identification code register identifies several aspects of the device including the silicon version.

The details of the device identification code register are shown in Table 6-1. The device identification code

register value for this device is:

•

Rev 0 = 0x8048AD05

Rev A = 0x8048AD0D

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Figure 6-2. Device ID Bit Allocation Register

31

CP-15

R-1

30

29

13

28

27

11

26

25

24

23

22

21

20

19

3

18

17

16

TECH

R-0

UNIQUE ID

R-00000000100100

15

14

12

10

9

8

7

6

5

4

2

1

0

1

TECH

I/O

PERIPH FLASH ECC

RAM

ECC

VERSION

VOLT PARITY

AGE

R-101

R-0

R-1

R-10

R-1

R-00001

R-1

R-0

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 6-1. Device ID Bit Allocation Register Field Descriptions

Bit

Field

Value

Description

31

CP15

Indicates the presence of coprocessor 15

CP15 present

1

30-17

UNIQUE ID

100100

Silicon version (revision) bits.

This bitfield holds a unique number for a dedicated device configuration (die).

16-13

12

TECH

Process technology on which the device is manufactured.

0101

0

F021

I/O VOLTAGE

I/O voltage of the device.

I/O are 3.3v

11

PERIPHERAL

PARITY

Peripheral Parity

1

Parity on peripheral memories

Flash ECC

10-9

8

FLASH ECC

RAM ECC

10

Program memory with ECC

Indicates if RAM memory ECC is present.

ECC implemented

1

0

7-3

2-0

REVISION

FAMILY ID

Revision of the Device.

101

The platform family ID is always 0b101

6.2.2 Die Identification Registers

The four die ID registers at addresses 0xFFFFE1F0, 0xFFFFE1F4, 0xFFFFE1F8 and FFFFE1FC form a

128-bit dieid with the information as shown in Table Table 6-2.

Table 6-2. Die-ID Registers

Item

X Coord. on Wafer

Y Coord. on Wafer

Wafer #

# of Bits

Bit Location

12

8

0xFFFFE1F0[11:0]

0xFFFFE1F0[23:12]

0xFFFFE1F0[31:24]

0xFFFFE1F4[23:0]

Lot #

24

72

Reserved

0xFFFFE1F4[31:24], 0xFFFFE1F8[31:0],

0xFFFFE1FC[31:0]

6.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

Hercules™ ARM® Cortex™ Safety Microcontroller Section of the TI E2E Support Community. TI's

Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers.

At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve

problems with fellow engineers.

6.4 Module Certifications

The following communications modules have received certification of adherence to a standard.

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6.4.1 DCAN Certification

Figure 6-3. DCAN Certification

96

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6.4.2 LIN Certification

6.4.2.1 LIN Master Mode

Figure 6-4. LIN Certification - Master Mode

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6.4.2.2 LIN Slave Mode - Fixed Baud Rate

Figure 6-5. LIN Certification - Slave Mode - Fixed Baud Rate

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6.4.2.3 LIN Slave Mode - Adaptive Baud Rate

Figure 6-6. LIN Certification - Slave Mode - Adaptive Baud Rate

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7 Mechanical Data

7.1 Thermal Data

Table 7-1 shows the thermal resistance characteristics for the PQFP - PZ mechanical packages.

Table 7-1. Thermal Resistance Characteristics

(S-PQFP Package) [PZ]

PARAMETER

R_θJA

°C/W

48

R_θJC

5

7.2 Packaging Information

The following packaging information reflects the most current released data available for the designated

device(s). This data is subject to change without notice and without revision of this document.

100

Mechanical Data

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MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

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型号：	RM42L432PZT
厂家：	TEXAS INSTRUMENTS
描述：	16- and 32-Bit RISC Flash Microcontroller 100-LQFP -40 to 105 时钟微控制器外围集成电路
文件：	总104页 (文件大小：8348K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RM42L432PZT [TI]

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