RM48L540ZWT [TI]
RM48Lx40 16- and 32-Bit RISC Flash Microcontroller;
| 型号： | RM48L540ZWT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | RM48Lx40 16- and 32-Bit RISC Flash Microcontroller 微控制器 外围集成电路 |
| 文件： | 总174页 (文件大小：8881K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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RM48L940, RM48L740, RM48L540
SPNS175C –APRIL 2012–REVISED JUNE 2015
RM48Lx40 16- and 32-Bit RISC Flash Microcontroller
1 Device Overview
1.1 Features
1
• High-Performance Microcontroller for Safety-
Critical Applications
• Multiple Communication Interfaces
– 10/100 Mbps Ethernet MAC (EMAC)
– Dual CPUs Running in Lockstep
– ECC on Flash and RAM Interfaces
•
•
IEEE 802.3 Compliant (3.3-V I/O Only)
Supports MII, RMII, and MDIO
– Built-In Self-Test (BIST) for CPU and On-chip
RAMs
– Error Signaling Module With Error Pin
– Voltage and Clock Monitoring
– Three CAN Controllers (DCANs)
•
•
64 Mailboxes, Each With Parity Protection
Compliant to CAN Protocol Version 2.0B
– Standard Serial Communication Interface (SCI)
– Local Interconnect Network (LIN) Interface
Controller
• ARM® Cortex®-R4F 32-Bit RISC CPU
– Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline
– FPU With Single- and Double-Precision
– 12-Region Memory Protection Unit (MPU)
– Open Architecture With Third-Party Support
• Operating Conditions
•
•
Compliant to LIN Protocol Version 2.1
Can be Configured as a Second SCI
– Inter-Integrated Circuit (I2C)
– Three Multibuffered Serial Peripheral Interfaces
(MibSPIs)
– System Clock up to 200 MHz
– Core Supply Voltage (VCC): 1.2 V Nominal
– I/O Supply Voltage (VCCIO): 3.3 V Nominal
– ADC Supply Voltage (VCCAD): 3.0 to 5.25 V
• Integrated Memory
•
128 Words With Parity Protection Each
– Two Standard Serial Peripheral Interfaces
(SPIs)
• Two Next Generation High-End Timer (N2HET)
Modules
– 3MB of Program Flash With ECC (RM48L940)
– N2HET1: 32 Programmable Channels
– N2HET2: 18 Programmable Channels
– 2MB of Program Flash With ECC
(RM48L740/540)
– 160-Word Instruction RAM Each With Parity
Protection
– Each N2HET Includes Hardware Angle
Generator
– Dedicated High-End Transfer Unit (HTU) With
MPU for Each N2HET
– 256KB of RAM With ECC (RM48L940/740)
– 192KB of RAM With ECC (RM48L540)
– 64KB of Flash With ECC for Emulated
EEPROM
• 16-Bit External Memory Interface
• Common Platform Architecture
• Two 12-Bit Multibuffered ADC Modules
– ADC1: 24 Channels
– ADC2: 16 Channels Shared With ADC1
– 64 Result Buffers With Parity Protection Each
• General-Purpose Input/Output (GPIO) Pins
Capable of Generating Interrupts
– 16 Pins on the ZWT Package
– 10 Pins on the PGE Package
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight™ Components
• JTAG Security Module
• Packages
– Consistent Memory Map Across Family
– Real-Time Interrupt (RTI) Timer OS Timer
– 96-Channel Vectored Interrupt Module (VIM)
– 2-Channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Peripheral Requests
– Parity Protection for Control Packet RAM
– DMA Accesses Protected by Dedicated MPU
• Frequency-Modulated Phase-Locked Loop
(FMPLL) With Built-In Slip Detector
• Separate Nonmodulating PLL
• Trace and Calibration Capabilities
– Embedded Trace Macrocell (ETM-R4)
– Data Modification Module (DMM)
– RAM Trace Port (RTP)
– 144-Pin Quad Flatpack (PGE) [Green]
– 337-Ball Grid Array (ZWT) [Green]
– Parameter Overlay Module (POM)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
RM48L940, RM48L740, RM48L540
SPNS175C –APRIL 2012–REVISED JUNE 2015
www.ti.com
1.2 Applications
•
Industrial Safety Applications
•
Medical Applications
–
–
–
–
–
Industrial Automation
–
–
–
–
–
Ventilators
Safe Programmable Logic Controllers (PLCs)
Power Generation and Distribution
Turbines and Windmills
Defibrillators
Infusion and Insulin Pumps
Radiation Therapy
Robotic Surgery
Elevators and Escalators
2
Device Overview
Copyright © 2012–2015, Texas Instruments Incorporated
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SPNS175C –APRIL 2012–REVISED JUNE 2015
1.3 Description
The RM48Lx40 device is a high-performance microcontroller family for safety systems. The safety
architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the
data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.
The RM48Lx40 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient
1.66 DMIPS/MHz, and has configurations that can run up to 200 MHz, providing up to 332 DMIPS. The
device supports the little-endian [LE] format.
The RM48L940 device has 3MB of integrated flash and 256KB of data RAM. The RM48L740 device has
2MB of integrated flash and 256KB of data RAM. The RM48L540 device has 2MB of integrated flash and
192KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error
detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable
memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input
(same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash
operates with a system clock frequency of up to 200 MHz. The SRAM supports single-cycle read and write
accesses in byte, halfword, word, and double-word modes.
The RM48Lx40 device features peripherals for real-time control-based applications, including two Next
Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital Converters
(ADCs) supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,
capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer
Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory.
A Memory Protection Unit (MPU) is built into the HTU.
The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer
RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are
three separate groupings. Each sequence can be converted once when triggered or configured for
continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older
devices or faster conversion time is desired.
The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three
DCANs, one I2C module, and one Ethernet. The SPIs provide a convenient method of serial high-speed
communication between similar shift-register type devices. The LIN supports the Local Interconnect
standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero
(NRZ) format.
The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster
communication protocol that efficiently supports distributed real-time control with robust communication
rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for
example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication
or multiplexed wiring.
The Ethernet module supports MII, RMII, and MDIO interfaces.
The I2C module is a multimaster communication module providing an interface between the
microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100
and 400 Kbps.
Copyright © 2012–2015, Texas Instruments Incorporated
Device Overview
3
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The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device.
These modules, when enabled, provide two of the seven possible clock source inputs to the Global Clock
Module (GCM). The GCM manages the mapping between the available clock sources and the device
clock domains.
The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous
external clock on the ECLK pin (or ball). The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an
indicator of the device operating frequency.
The DMA controller has 16 channels, 32 peripheral requests, and parity protection on its memory. An
MPU is built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the
memory system from any malfunction of the DMA.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is
generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be
monitored externally as an indicator of a fault condition in the microcontroller.
The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to
synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals, or FPGA devices.
Several interfaces are implemented to enhance the debugging capabilities of application code. In addition
to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides
instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP)
module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any
other master. A Data Modification Module (DMM) gives the ability to write external data into the device
memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the
application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to
the EMIF. This rerouting allows the dynamic calibration against production code of parameters and tables
without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.
With integrated safety features and a wide choice of communication and control peripherals, the
RM48Lx40 device is an ideal solution for high-performance real-time control applications with safety-
critical requirements.
Device Information(1)
PART NUMBER
RM48L940ZWT
PACKAGE
NFBGA (337)
LQFP (144)
NFBGA (337)
LQFP (144)
NFBGA (337)
LQFP (144)
BODY SIZE
16.0 mm × 16.0 mm
20.0 mm × 20.0 mm
16.0 mm × 16.0 mm
20.0 mm × 20.0 mm
16.0 mm × 16.0 mm
20.0 mm × 20.0 mm
RM48L940PGE
RM48L740ZWT
RM48L740PGE
RM48L540ZWT
RM48L540PGE
(1) For more information, see Section 9, Mechanical Packaging and Orderable Information.
4
Device Overview
Copyright © 2012–2015, Texas Instruments Incorporated
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SPNS175C –APRIL 2012–REVISED JUNE 2015
1.4 Functional Block Diagram
Color Legend for Power Domains
RAM
Core/RAM
Core
always on
# 1
# 2
# 3
# 4
# 5
# 1
# 2
3MB(B)
Flash
with
64K(A)
256KB
64K RAM
with
# 3
64K
ECC
64K
ECC
ETM-R4
RTP
DMA
POM
DMM
HTU1 HTU2
EMAC
Dual Cortex-R4F
CPUs in Lockstep
Switched Central Resource Switched Central Resource Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
64KB Flash
Peripheral Central Resource Bridge
SYS
CRC Switched Central Resource
for EEPROM
Emulation
with ECC
nPORRST
nRST
ECLK
IOMM
nERROR
EMAC Slaves
ESM
MDCLK
MDIO
PMM
VIM
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
EMIF_nWAIT
EMIF_CLK
MDIO
DCAN1
MII_RXD[3:0]
MII_RXER
MII_TXD[3:0]
MII_TXEN
MII_TXCLK
MII_RXCLK
EMIF_CKE
DCAN2
DCAN3
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[21:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
MII
MIBSPI1_CLK
EMIF
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MII_CRS
MII_RXDV
MII_COL
MibSPI1
SPI2
RTI
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
EMIF_nWE
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
EMIF_nRAS
EMIF_nCAS
DCC1
SPI2_nCS[1:0]
SPI2_nENA
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
MibSPI3
SPI4
DCC2
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
MibADC1
MibADC2
N2HET1 N2HET2 GIO
I2C
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
MibSPI5
LIN_RX
LIN_TX
LIN
SCI
SCI_RX
SCI_TX
A. For devices with 192KB RAM with ECC, the RAM #3 power domain is not supported.
B. The RM48L740 and RM48L540 devices only support 2MB of Flash with ECC.
Figure 1-1. Functional Block Diagram
Copyright © 2012–2015, Texas Instruments Incorporated
Device Overview
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SPNS175C –APRIL 2012–REVISED JUNE 2015
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Table of Contents
1
Device Overview ......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 2
1.3 Description............................................ 3
1.4 Functional Block Diagram ............................ 5
Revision History ......................................... 7
Device Comparison ..................................... 8
Terminal Configuration and Functions ............. 9
4.1 PGE QFP Package Pinout (144-Pin)................. 9
6.12 Parity Protection for Peripheral RAMs .............. 82
6.13 On-Chip SRAM Initialization and Testing ........... 84
6.14 External Memory Interface (EMIF) .................. 86
6.15 Vectored Interrupt Manager ......................... 93
6.16 DMA Controller ...................................... 96
6.17 Real Time Interrupt Module ......................... 98
6.18 Error Signaling Module............................. 100
6.19 Reset / Abort / Error Sources...................... 104
6.20 Digital Windowed Watchdog....................... 106
6.21 Debug Subsystem ................................. 107
2
3
4
4.2
ZWT BGA Package Ball-Map (337-Ball Grid Array) 10
4.3 Terminal Functions ................................. 11
Specifications .......................................... 40
5.1 Absolute Maximum Ratings ........................ 40
5.2 ESD Ratings ........................................ 40
5.3 Power-On Hours (POH)............................. 40
5.4 Recommended Operating Conditions............... 41
7
Peripheral Information and Electrical
Specifications ......................................... 118
7.1 Peripheral Legend ................................. 118
5
7.2
Multibuffered 12-Bit Analog-to-Digital Converter .. 118
7.3 General-Purpose Input/Output..................... 129
7.4
Enhanced Next Generation High-End Timer
(N2HET)............................................ 130
7.5 Controller Area Network (DCAN) .................. 135
5.5
Switching Characteristics for Clock Domains ....... 42
5.6 Wait States Required ............................... 42
5.7 Power Consumption................................. 43
7.6
Local Interconnect Network Interface (LIN)........ 136
Serial Communication Interface (SCI) ............. 137
7.7
5.8
Input/Output Electrical Characteristics .............. 44
7.8 Inter-Integrated Circuit (I2C) ....................... 138
7.9
5.9 Thermal Resistance Characteristics ................ 45
5.10 Output Buffer Drive Strengths ...................... 46
5.11 Input Timings........................................ 47
5.12 Output Timings...................................... 47
5.13 Low-EMI Output Buffers ............................ 49
Multibuffered / Standard Serial Peripheral
Interface............................................ 141
7.10 Ethernet Media Access Controller ................. 153
Device and Documentation Support.............. 157
8.1 Device Support..................................... 157
8.2 Documentation Support............................ 159
8.3 Related Links ...................................... 159
8.4 Community Resources............................. 159
8.5 Trademarks ........................................ 159
8.6 Electrostatic Discharge Caution ................... 159
8.7 Glossary............................................ 160
8.8 Device Identification Code Register ............... 160
8.9 Die Identification Registers ....................... 161
8.10 Module Certifications............................... 162
8
6
System Information and Electrical
Specifications ........................................... 51
6.1 Device Power Domains ............................. 51
6.2 Voltage Monitor Characteristics ..................... 52
6.3
Power Sequencing and Power On Reset ........... 53
6.4 Warm Reset (nRST)................................. 55
6.5 ARM Cortex-R4F CPU Information ................. 56
6.6 Clocks ............................................... 60
6.7 Clock Monitoring .................................... 68
6.8 Glitch Filters......................................... 70
6.9 Device Memory Map ................................ 71
6.10 Flash Memory ....................................... 79
6.11 Tightly Coupled RAM (TCRAM) Interface Module .. 82
9
Mechanical Packaging and Orderable
Information............................................. 167
9.1 Packaging Information ............................. 167
6
Table of Contents
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RM48L940, RM48L740, RM48L540
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SPNS175C –APRIL 2012–REVISED JUNE 2015
2 Revision History
This data manual revision history highlights the technical changes made to the SPNS175B device-specific
data manual to make it an SPNS175C revision.
Scope: Applicable updates to the Hercules™ RM MCU device family, specifically relating to the
RM48Lx40 devices, which are now in the production data (PD) stage of development have been
incorporated.
Changes from May 15, 2015 to June 30, 2015 (from B Revision (May 2015) to C Revision)
Page
•
Figure 8-1 (RM48x Device Numbering Conventions): Updated/Changed figure to show the die revision letter...... 158
Copyright © 2012–2015, Texas Instruments Incorporated
Revision History
7
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SPNS175C –APRIL 2012–REVISED JUNE 2015
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3 Device Comparison
Table 3-1 lists the features of the RM48Lx40 devices.
Table 3-1. RM48Lx40 Device Comparison(1)(2)
FEATURES
Generic Part Number
Package
DEVICES
RM48L740ZWT
337 BGA
RM57L843ZWT(3) RM48L952ZWT(3)
337 BGA 337 BGA
RM48L940ZWT
337 BGA
RM48L940PGE
144 QFP
RM48L740PGE
144 QFP
RM48L540ZWT
337 BGA
RM48L540PGE
144 QFP
RM46L852ZWT(3)
337 BGA
CPU
ARM Cortex-R5F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F
Frequency (MHz)
333
220
–
200
–
200
–
200
–
200
–
200
–
200
–
220
–
32 I
32 D
Cache (KB)
Flash (KB)
4096
3072
3072
3072
2048
2048
2048
2048
1280
RAM (KB)
512
256
256
256
256
256
192
192
192
Data Flash [EEPROM] (KB)
USB OHCI + Device
EMAC
128
64
64
64
64
64
64
64
64
–
2+0 or 1+1
–
–
–
–
–
–
2+0 or 1+1
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100
CAN
4
3
3
3
3
3
3
3
3
MibADC 12-bit (Ch)
N2HET (Ch)
ePWM Channels
eCAP Channels
eQEP Channels
MibSPI (CS)
SPI (CS)
2 (41ch)
2 (24ch)
2 (24ch)
2 (24ch)
2 (24ch)
2 (24ch)
2 (24ch)
2 (24ch)
2 (24ch)
2 (64)
2 (44)
2 (44)
2 (40)
2 (44)
2 (40)
2 (44)
2 (40)
2 (44)
14
–
–
–
–
–
–
–
14
6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6
2
2
5 (4 x 6 + 2)
–
3 (6 + 6 + 4)
2 (2 + 1)
2 (1 with LIN)
1
3 (6 + 6 + 4)
2 (2 + 1)
2 (1 with LIN)
1
3 (5 + 6 + 1)
1 (1)
3 (6 + 6 + 4)
2 (2 + 1)
2 (1 with LIN)
1
3 (5 + 6 + 1)
1 (1)
3 (6 + 6 + 4)
2 (2 + 1)
2 (1 with LIN)
1
3 (5 + 6 + 1)
1 (1)
3 (6 + 6 + 4)
2 (2 + 1)
2 (1 with LIN)
1
SCI (LIN)
4 (2 with LIN)
2
2 (1 with LIN)
1
2 (1 with LIN)
1
2 (1 with LIN)
1
I2C
168 (with 16
144 (with 16
144 (with 16
64 (with 4
144 (with 16
64 (with 4
144 (with 16
64 (with 4
101 (with 16
GPIO (INT)(4)
interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable)
EMIF
16-bit data
(32)
16-bit data
(32)
16-bit data
32-bit
–
16-bit data
32-bit
–
16-bit data
32-bit
–
16-bit data
–
ETM [Trace] (Data)
RTP/DMM (Data)
Operating Temperature
Core Supply (V)
I/O Supply (V)
–
–
–
(16/16)
(16/16)
16/16
–
16/16
–
16/16
–
–
–40ºC to 105ºC
1.14 V – 1.32 V
3.0 V – 3.6 V
–40ºC to 105ºC
1.14 V – 1.32 V
3.0 V – 3.6 V
–40ºC to 105ºC
1.14 V – 1.32 V
3.0 V – 3.6 V
–40ºC to 105ºC
1.14 V – 1.32 V
3.0 V – 3.6 V
–40ºC to 105ºC
1.14 V – 1.32 V
3.0 V – 3.6 V
–40ºC to 105ºC
1.14 V – 1.32 V
3.0 V – 3.6 V
–40ºC to 105ºC
1.14 V – 1.32 V
3.0 V – 3.6 V
–40ºC to 105ºC
1.14 V – 1.32 V
3.0 V – 3.6 V
–40ºC to 105ºC
1.14 V – 1.32 V
3.0 V – 3.6 V
(1) For additional device variants, see www.ti.com/rm
(2) This table reflects the maximum configuration for each peripheral. Some functions are multiplexed and not all pins are available at the same time.
(3) Superset device
(4) Total number of pins that can be used as general-purpose input or output when not used as part of a peripheral
8
Device Comparison
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4 Terminal Configuration and Functions
4.1 PGE QFP Package Pinout (144-Pin)
AD1IN[10] / AD2IN[10]
AD1IN[01]
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
nTRST
TDI
TDO
TCK
RTCK
VCC
VSS
nRST
AD1IN[09] / AD2IN[09]
VCCAD
VSSAD
ADREFLO
ADREFHI
AD1IN[21] / AD2IN[05]
AD1IN[20] / AD2IN[04]
AD1IN[19] / AD2IN[03]
AD1IN[18] / AD2IN[02]
nERROR
N2HET1[10]
ECLK
VCCIO
VSS
VSS
AD1IN[07]
AD1IN[0]
AD1IN[17] / AD2IN[01]
AD1IN[16] / AD2IN[0]
VCC
VCC
N2HET1[12]
N2HET1[14]
GIOB[0]
N2HET1[30]
CAN2TX
VSS
MIBSPI3NCS[0]
MIBSPI3NENA
MIBSPI3CLK
MIBSPI3SIMO
MIBSPI3SOMI
VSS
CAN2RX
MIBSPI1NCS[1]
LINRX
LINTX
GIOB[1]
VCCP
VSS
VCCIO
VCC
VCC
VSS
nPORRST
VCC
VSS
VCC
VSS
VSS
VCCIO
N2HET1[16]
N2HET1[18]
N2HET1[20]
GIOB[2]
VCC
N2HET1[15]
MIBSPI1NCS[2]
N2HET1[13]
N2HET1[06]
MIBSPI3NCS[1]
VSS
A. Pins can have multiplexed functions. Only the default function is depicted in the figure.
Figure 4-1. PGE QFP Package Pinout (144-Pin)(A)
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4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
AD1IN[15] AD1IN[22]
AD1IN[11]
/
AD2IN[11]
N2HET1 MIBSPI5 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 N2HET1
SIMO[0]
DMM_
DATA[0]
AD1IN
[06]
19
18
17
16
15
14
13
12
11
VSS
VSS
TMS
CAN3RX AD1EVT
/
/
AD2IN[15] AD2IN[06]
VSSAD
VSSAD 19
[10]
NCS[0]
SIMO
NENA
CLK
[28]
AD1IN[08] AD1IN[14] AD1IN[13]
N2HET1 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 N2HET1
SOMI[0]
DMM_
DATA[1]
AD1IN
[04]
AD1IN
[02]
VSS
TDI
TCK
RST
TDO
nTRST
CAN3TX
NC
/
AD2IN[08] AD2IN[14] AD2IN[13]
/
/
VSSAD 18
AD1IN[09]
[08]
CLK
SOMI
NENA
[0]
AD1IN[10]
/
AD2IN[10]
EMIF_
ADDR[21]
EMIF_
nWE
MIBSPI5
SOMI[1]
DMM_
CLK
MIBSPI5 MIBSPI5 N2HET1
[31]
EMIF_
nCS[3]
EMIF_
nCS[2]
EMIF_
nCS[4]
EMIF_
nCS[0]
AD1IN
[05]
AD1IN
[03]
AD1IN
[01]
NC
NC
/
AD2IN[09]
17
SIMO[3] SIMO[2]
AD1IN[23] AD1IN[12] AD1IN[19]
/
AD2IN[07] AD2IN[12] AD2IN[03]
EMIF_
ADDR[20]
EMIF_
BA[1]
MIBSPI5
SIMO[1]
DMM_
NENA
MIBSPI5 MIBSPI5
SOMI[3] SOMI[2]
DMM_
SYNC
RTCK
NC
NC
NC
NC
NC
NC
/
/
ADREFLO VSSAD 16
ADREFHI VCCAD 15
AD1IN[21] AD1IN[20]
EMIF_ ETM
ADDR[19] ADDR[18] DATA[06] DATA[05] DATA[04] DATA[03] DATA[02] DATA[16] DATA[17] DATA[18] DATA[19]
EMIF_
ETM
ETM
ETM
ETM
ETM
ETM
ETM
ETM
NC
NC
NC
NC
/
AD2IN[05] AD2IN[04]
/
AD1IN[18]
/
AD2IN[02]
N2HET1
[26]
EMIF_ ETM
ADDR[17] ADDR[16] DATA[07]
EMIF_
AD1IN
[07]
AD1IN
[0]
nERROR
VCCIO
VCCIO
VCCIO
VCCIO
VCC
VCCIO
VCCIO
VCC
VCC
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCPLL
VCC
NC
NC
14
13
12
11
AD1IN[17] AD1IN[16]
/
AD2IN[01] AD2IN[0]
N2HET1 N2HET1
[17]
EMIF_
ADDR[15]
ETM
DATA[12]
ETM
DATA[01]
NC
NC
NC
NC
NC
NC
NC
/
NC
NC
NC
[19]
N2HET1
[04]
EMIF_
ADDR[14]
ETM
DATA[13]
ETM
DATA[0]
MIBSPI5
NCS[3]
ECLK
VSS
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
NC
NC
NC
NC
ETME
TRACE
CTL
N2HET1 N2HET1
[14] [30]
EMIF_
ADDR[13]
ETM
DATA[14]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ETM
TRACE
CLKOUT
EMIF_
ADDR[12]
ETM
DATA[15]
MIBSPI3
NCS[0]
10 CAN1TX CAN1RX
NC
GIOB[3] 10
ETM
TRACE
CLKIN
N2HET1
[27]
EMIF_
ADDR[11]
ETM
DATA[08]
MIBSPI3 MIBSPI3
CLK
9
8
7
6
5
4
3
2
1
NC
NC
VCC
VCCIO
VCCIO
VCCIO
NC
9
8
7
6
5
4
3
2
1
NENA
EMIF_
ADDR[10]
ETM
DATA[09]
ETM
DATA[31]
MIBSPI3 MIBSPI3
SOMI
NC
VCCP
VCCIO
NC
SIMO
EMIF_
ADDR[9]
ETM
DATA[10]
ETM
DATA[30]
N2HET1
[09]
nPORRST
LINRX
LINTX
NC
MIBSPI5
NCS[1]
EMIF_
ADDR[8]
ETM
DATA[11]
ETM
DATA[29]
N2HET1 MIBSPI5
[05] NCS[2]
GIOA[4]
NC
VCCIO
ETM
VCCIO
ETM
VCCIO
FLTP2
VCCIO
FLTP1
VCC
ETM
VCC
ETM
VCCIO
ETM
VCCIO
ETM
VCCIO
ETM
NC
EMIF_
EMIF_
ETM
ETM
MIBSPI3 N2HET1
NCS[1]
GIOA[0] GIOA[5]
N2HET1 N2HET1
NC
ADDR[7] ADDR[1] DATA[20] DATA[21] DATA[22]
DATA[23] DATA[24] DATA[25] DATA[26] DATA[27] DATA[28]
[02]
EMIF_ EMIF_
ADDR[6] ADDR[0]
N2HET1 N2HET1
[21]
EMIF_
nCAS
NC
NC
NC
NC]
NC
NC
NC
NC
NC
NC
NC
[16]
[12]
[23]
N2HET1 N2HET1 MIBSPI3
NCS[3]
SPI2
NENA
N2HET1 MIBSPI1 MIBSPI1
[11] NCS[1] NCS[2]
MIBSPI1
NCS[3]
EMIF_
CLK
EMIF_
CKE
NH2ET1
[25]
SPI2
NCS[0]
EMIF_
nWAIT
EMIF_
nRAS
N2HET1
[06]
GIOA[6]
NC
NC
[29]
[22]
MIBSPI3
NCS[2]
SPI2
SOMI
KELVIN_
GND
N2HET1 N2HET1 MIBSPI1
[20]
N2HET1
[01]
VSS
GIOA[1]
SPI2 CLK GIOB[2] GIOB[5] CAN2TX GIOB[6] GIOB[1]
GIOB[0]
TEST
VSS
[13]
NCS[0]
SPI2
SIMO
N2HET1
[18]
N2HET1 N2HET1
[24]
N2HET1 N2HET1
[07]
VSS
A
VSS
B
GIOA[2]
C
GIOA[3] GIOB[7] GIOB[4] CAN2RX
OSCIN
K
OSCOUT GIOA[7]
NC
R
VSS
V
VSS
W
[15]
[03]
D
E
F
G
H
J
L
M
N
P
T
U
A. Balls can have multiplexed functions. Only the default function, except for the EMIF signals that are multiplexed with
ETM signals, is depicted in the figure.
Figure 4-2. ZWT Package Pinout. Top View(A)
Note: Balls can have multiplexed functions. Only the default function is depicted in Figure 4-2, except for
the EMIF signals that are multiplexed with ETM signals.
10
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4.3 Terminal Functions
Section 4.3.1 and Section 4.3.2 identify the external signal names, the associated pin or ball numbers
along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground),
whether the pin or ball has any internal pullup or pulldown, whether the pin or ball can be configured as a
GPIO, and a functional pin or ball description. The first signal name listed is the primary function for that
terminal. The signal name in bold is the function being described. For information on how to select
between different multiplexed functions, see the RM48x 16/32-Bit RISC Flash Microcontroller Technical
Reference Manual (SPNU503) .
NOTE
In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to
the terminal while nPORRST is low and immediately after nPORRST goes High. The default
pull direction may change when software configures the pin for an alternate function. The
"Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given
terminal by the IOMM control registers.
All I/O signals except nRST are configured as inputs while nPORRST is low and
immediately after nPORRST goes High. While nPORRST is low, the input buffers
are disabled, and the output buffers are disabled with the default pulls enabled.
All output-only signals have the output buffer disabled and the default pull enabled
while nPORRST is low, and are configured as outputs with the pulls disabled
immediately after nPORRST goes High.
4.3.1 PGE Package
4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADCs)
Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
ADREFHI(1)
ADREFLO(1)
VCCAD(1)
66
67
69
68
86
55
60
71
73
74
76
78
80
61
Input
Input
Power
Ground
I/O
ADC high reference supply
ADC low reference supply
Operating supply for ADC
N/A
None
VSSAD(1)
AD1EVT/MII_RX_ER/RMII_RX_ER
Pulldown
Pullup
Programmable, 20 µA ADC1 event trigger input, or GPIO
Programmable, 20 µA ADC2 event trigger input, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS
I/O
AD1IN[0]
AD1IN[1]
AD1IN[2]
AD1IN[3]
AD1IN[4]
AD1IN[5]
AD1IN[6]
AD1IN[7]
Input
N/A
None
ADC1 analog input
(1) The ADREFHI, ADREFLO, VCCAD, and VSSAD connections are common for both ADC cores.
Terminal Configuration and Functions
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Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) (continued)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
AD1IN[8] / AD2IN[8]
AD1IN[9] / AD2IN[9]
AD1IN[10] / AD2IN[10]
AD1IN[11] / AD2IN[11]
AD1IN[12] / AD2IN[12]
AD1IN[13] / AD2IN[13]
AD1IN[14] / AD2IN[14]
AD1IN[15] / AD2IN[15]
AD1IN[16] / AD2IN[0]
AD1IN[17] / AD2IN[1]
AD1IN[18] / AD2IN[2]
AD1IN[19] / AD2IN[3]
AD1IN[20] / AD2IN[4]
AD1IN[21] / AD2IN[5]
AD1IN[22] / AD2IN[6]
AD1IN[23] / AD2IN[7]
83
70
72
75
77
79
82
85
58
59
62
63
64
65
81
84
Input
N/A
None
ADC1/ADC2 shared analog inputs
12
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4.3.1.2 Enhanced Next Generation High-End Timer (N2HET) Modules
Table 4-2. PGE Enhanced Next Generation High-End Timer Modules (N2HET1, N2HET2)
TERMINAL
SIGNAL RESET PULL
PULL TYPE
DESCRIPTION
144
PGE
TYPE
STATE
SIGNAL NAME
N2HET1[0]/SPI4CLK
25
23
N2HET1[1]/SPI4NENA/N2HET2[8]
N2HET1[2]/SPI4SIMO[0]
30
N2HET1[3]/SPI4NCS[0]/N2HET2[10]
N2HET1[4]
24
36
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]
N2HET1[6]/SCIRX
31
38
N2HET1[7]/N2HET2[14]
33
Programmable,
20 µA
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]
N2HET1[9]/N2HET2[16]
106
35
I/O
Pulldown
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
N2HET1[12]/MII_CRS/RMII_CRS_DV
N2HET1[13]/SCITX
118
6
124
39
N2HET1[14]
125
41
N2HET1[15]/MIBSPI1NCS[4]
N2HET1[16]
139
Programmable,
20 µA
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
N2HET1[18]
130
140
40
141
15
96
91
37
92
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pullup
Pulldown
Pullup
N2HET1 timer input capture
or output compare, or GIO.
Programmable,
20 µA
Each terminal has a
suppression filter with a
programmable duration.
Programmable,
20 µA
MIBSPI1NCS[2]/N2HET1[19]/MDIO
N2HET1[20]
Programmable,
20 µA
Pulldown
Pulldown
Pullup
Programmable,
20 µA
N2HET1[22]
Programmable,
20 µA
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
N2HET1[26]/MII_RXD[1]/RMII_RXD[1]
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
N2HET1[30]/MII_RX_DV
Programmable,
20 µA
Pulldown
Pullup
Programmable,
20 µA
Programmable,
20 µA
Pulldown
Pullup
Programmable,
20 µA
Programmable,
20 µA
107
3
Pulldown
Pullup
Programmable,
20 µA
Programmable,
20 µA
127
54
14
Pulldown
Pullup
Programmable,
20 µA
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS
Programmable,
20 µA
Disable selected PWM
outputs
Pulldown
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Table 4-2. PGE Enhanced Next Generation High-End Timer Modules (N2HET1, N2HET2) (continued)
TERMINAL
SIGNAL RESET PULL
PULL TYPE
DESCRIPTION
144
PGE
TYPE
STATE
SIGNAL NAME
GIOA[2]/N2HET2[0]
GIOA[6]/N2HET2[4]
GIOA[7]/N2HET2[6]
9
16
22
23
24
31
33
35
6
N2HET2 time input capture
or output compare, or GPIO
N2HET1[1]/SPI4NENA/N2HET2[8]
N2HET1[3]/SPI4NCS[0]/N2HET2[10]
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]
N2HET1[7]/N2HET2[14]
Programmable,
20 µA
I/O
I/O
Pulldown
Each terminal has a
suppression filter with a
programmable duration.
N2HET1[9]/N2HET2[16]
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
Programmable,
20 µA
Disable selected PWM
outputs
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS
55
Pullup
4.3.1.3 General-Purpose Input/Output (GPIO)
Table 4-3. PGE General-Purpose Input/Output (GPIO)
TERMINAL
SIGNAL NAME
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
144
PGE
GIOA[0]
2
5
GIOA[1]
GIOA[2]/N2HET2[0]
9
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS
14
16
22
126
133
142
55(1)
1
General-purpose I/O.
GIOA[6]/N2HET2[4]
Pulldown
All GPIO terminals are
capable of generating
interrupts to the CPU on rising
/ falling / both edges.
Programmable,
20 µA
GIOA[7]/N2HET2[6]
I/O
GIOB[0]
GIOB[1]
GIOB[2]/N2HET1_PIN_nDIS
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS
GIOB[3]
Pullup
Pulldown
(1) The application cannot output a level onto this terminal when it is configured as GIOB[2]. A pullup is enabled on this input. This pull
cannot be disabled, and is not programmable using the GIO module pull control registers.
4.3.1.4 Controller Area Network Controllers (DCANs)
Table 4-4. PGE Controller Area Network Controllers (DCAN)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
CAN1RX
CAN1TX
CAN2RX
CAN2TX
CAN3RX
CAN3TX
90
89
CAN1 receive, or GPIO
CAN1 transmit, or GPIO
CAN2 receive, or GPIO
CAN2 transmit, or GPIO
CAN3 receive, or GPIO
CAN3 transmit, or GPIO
129
128
12
Programmable,
20 µA
I/O
Pullup
13
14
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4.3.1.5 Local Interconnect Network Interface Module (LIN)
Table 4-5. PGE Local Interconnect Network Interface Module (LIN)
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
LINRX
LINTX
131
132
LIN receive, or GPIO
LIN transmit, or GPIO
Programmable,
20 µA
I/O
Pullup
4.3.1.6 Standard Serial Communication Interface (SCI)
Table 4-6. PGE Standard Serial Communication Interface (SCI)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
N2HET1[6]/SCIRX
N2HET1[13]/SCITX
38
39
SCI receive, or GPIO
SCI transmit, or GPIO
Programmable,
20 µA
I/O
Pulldown
4.3.1.7 Inter-Integrated Circuit Interface Module (I2C)
Table 4-7. PGE Inter-Integrated Circuit Interface Module (I2C)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
4
3
I2C serial data, or GPIO
I2C serial clock, or GPIO
Programmable,
20 µA
I/O
Pullup
4.3.1.8 Standard Serial Peripheral Interface (SPI)
Table 4-8. PGE Standard Serial Peripheral Interface (SPI)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
N2HET1[0]/SPI4CLK
25
24
23
SPI4 clock, or GPIO
N2HET1[3]/SPI4NCS[0]/N2HET2[10]
N2HET1[1]/SPI4NENA/N2HET2[8]
SPI4 chip select, or GPIO
SPI4 enable, or GPIO
Programmable,
20 µA
I/O
Pulldown
SPI4 slave-input master-
output, or GPIO
N2HET1[2]/SPI4SIMO[0]
30
31
SPI4 slave-output master-
input, or GPIO
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]
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4.3.1.9 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-9. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
MIBSPI1CLK
95
105
130
40
MibSPI1 clock, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
MIBSPI1NCS[2]/N2HET1[19]/MDIO
N2HET1[15]/MIBSPI1NCS[4]
Programmable,
20 µA
Pullup
MibSPI1 chip select, or GPIO
41
Programmable,
20 µA
Pulldown
MibSPI1 chip select, or GPIO
MibSPI1 enable, or GPIO
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
MIBSPI1SIMO[0]
91
I/O
96
Programmable,
20 µA
Pullup
Pulldown
Pullup
93
MibSPI1 slave-in master-out, or GPIO
MibSPI1 slave-in master-out, or GPIO
Programmable,
20 µA
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]
106
MIBSPI1SOMI[0]
94
105
53
55
37
4
Programmable,
20 µA
MibSPI1 slave-out master-in, or GPIO
MibSPI3 clock, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
MIBSPI3CLK
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
Programmable,
20 µA
Pullup
MibSPI3 chip select, or GPIO
3
I/O
Programmable,
20 µA
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
6
Pulldown
Pullup
MibSPI3 chip select, or GPIO
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
MIBSPI3SIMO[0]
54
54
52
51
100
32
97
99
98
MibSPI3 chip select, or GPIO
MibSPI3 enable, or GPIO
Programmable,
20 µA
MibSPI3 slave-in master-out, or GPIO
MibSPI3 slave-out master-in, or GPIO
MibSPI5 clock, or GPIO
MIBSPI3SOMI[0]
MIBSPI5CLK/MII_TXEN/RMII_TXEN
MIBSPI5NCS[0]
MibSPI5 chip select, or GPIO
MibSPI5 enable, or GPIO
Programmable,
20 µA
MIBSPI5NENA/MII_RXD[3]
I/O
Pullup
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0]
MibSPI5 slave-in master-out, or GPIO
MibSPI5 slave-out master-in, or GPIO
4.3.1.10 Ethernet Controller
Table 4-10. PGE Ethernet Controller: MDIO Interface
TERMINAL
SIGNAL NAME
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
MIBSPI1NCS[2]/N2HET1[19]/MDIO
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
144
PGE
Programmable,
20 µA
37
40
Output
I/O
Pullup
Pullup
Serial clock output
Serial data input/output
Fixed 20-µA
Pullup
16
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Table 4-11. PGE Ethernet Controller: Reduced Media Independent Interface (RMII)
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
RMII carrier sense and data
valid
N2HET1[12]/MII_CRS/RMII_CRS_DV
124
107
RMII synchronous reference
clock for receive, transmit and
control interface
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4
Fixed 20-µA
Pulldown
Input
Pulldown
AD1EVT/MII_RX_ER/RMII_RX_ER
86
91
RMII receive error
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]
N2HET1[26]/MII_RXD[1]/RMII_RXD[1]
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0]
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]
MIBSPI5CLK/MII_TXEN/RMII_TXEN
RMII receive data
92
98
RMII transmit data
99
Output
Pullup
None
100
RMII transmit enable
Table 4-12. PGE Ethernet Controller: Media Independent Interface (MII)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
130
124
Pullup
None
Collision detect
Input
Fixed 20-µA
Pulldown
Carrier sense and receive
valid
N2HET1[12]/MII_CRS/RMII_CRS_DV
Pulldown
Pulldown
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4
N2HET1[30]/MII_RX_DV
107
127
86
I/O
Input
I/O
None
MII output receive clock
Received data valid
Receive error
AD1EVT/MII_RX_ER/RMII_RX_ER
Fixed 20-µA
Pulldown
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]
N2HET1[26]/MII_RXD[1]/RMII_RXD[1]
107
91
Pulldown
Receive clock
92
Input
I/O
Receive data
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
MIBSPI5NENA/MII_RXD[3]
96
Fixed 20-µA
Pulldown
Pullup
97
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0]
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]
MIBSPI5CLK/MII_TXEN/RMII_TXEN
118
118
98
MII output transmit clock
Transmit clock
Pulldown
None
None
99
Pullup
Transmit data
105
106
100
Output
Pulldown
Pullup
None
None
Transmit enable
4.3.1.11 System Module Interface
Table 4-13. PGE System Module Interface
TERMINAL
RESET
SIGNAL
PULL
PULL TYPE
DESCRIPTION
144
PGE
TYPE
SIGNAL NAME
STATE
Power-on reset, cold reset
External power supply monitor
circuitry must drive nPORRST
low when any of the supplies
to the microcontroller fall out
of the specified range. This
terminal has a glitch filter.
See Section 6.8.
Fixed 100-µA
Pulldown
nPORRST
46
Input
Pulldown
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Table 4-13. PGE System Module Interface (continued)
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
System reset, warm reset,
bidirectional.
The internal circuitry indicates
any reset condition by driving
nRST low.
The external circuitry can
assert a system reset by
driving nRST low. To ensure
that an external reset is not
arbitrarily generated, TI
recommends that an external
pullup resistor is connected to
this terminal.
Fixed 100-µA
Pullup
nRST
116
I/O
Pullup
This terminal has a glitch
filter. See Section 6.8.
ESM Error Signal
Indicates error of high
severity. See Section 6.18.
Fixed 20-µA
Pulldown
nERROR
117
I/O
Pulldown
4.3.1.12 Clock Inputs and Outputs
Table 4-14. PGE Clock Inputs and Outputs
TERMINAL
RESET
SIGNAL
PULL
PULL TYPE
DESCRIPTION
144
PGE
TYPE
SIGNAL NAME
STATE
From external
OSCIN
18
Input
crystal/resonator, or external
clock input
N/A
None
KELVIN_GND
OSCOUT
19
20
Input
Kelvin ground for oscillator
To external crystal/resonator
Output
Programmable, 20 External prescaled clock
ECLK
119
14
I/O
Pulldown
Pulldown
µA
output, or GIO.
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS
Input
20 µA
External clock input #1
4.3.1.13 Test and Debug Modules Interface
Table 4-15. PGE Test and Debug Modules Interface
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
SIGNAL NAME
144
PGE
Test enable. This terminal
must be connected to ground
directly or through a pulldown
resistor.
TEST
34
I/O
Fixed 100-µA
Pulldown
Pulldown
nTRST
RTCK
109
113
Input
JTAG test hardware reset
JTAG return test clock
Output
N/A
None
Fixed 100-µA
Pulldown
TCK
TDI
112
110
111
108
Input
I/O
Pulldown
JTAG test clock
JTAG test data in
JTAG test data out
JTAG test select
Fixed 100-µA
Pullup
Pullup
100 µA
Pulldown
TDO
TMS
Output
I/O
None
Fixed 100-µA
Pullup
Pullup
18
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4.3.1.14 Flash Supply and Test Pads
Table 4-16. PGE Flash Supply and Test Pads
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
3.3-V
Power
VCCP
FLTP1
134
7
N/A
None
Flash pump supply
Flash test pads. These
terminals are reserved for TI
use only. For proper operation
these terminals must connect
only to a test pad or not be
connected at all [no connect
(NC)].
N/A
None
FLTP2
8
4.3.1.15 Supply for Core Logic: 1.2-V Nominal
Table 4-17. PGE Supply for Core Logic: 1.2-V Nominal
TERMINAL
SIGNAL NAME
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
144
PGE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
17
29
45
48
49
57
1.2-V
Power
N/A
None
1.2-V Core supply
87
101
114
123
137
143
4.3.1.16 Supply for I/O Cells: 3.3-V Nominal
Table 4-18. PGE Supply for I/O Cells: 3.3-V Nominal
TERMINAL
SIGNAL NAME
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
144
PGE
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
10
26
42
3.3-V
Power
3.3-V Operating supply for
I/Os
N/A
None
104
120
136
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4.3.1.17 Ground Reference for All Supplies Except VCCAD
Table 4-19. PGE Ground Reference for All Supplies Except VCCAD
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
144
PGE
SIGNAL NAME
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
11
21
27
28
43
44
47
50
56
Ground
N/A
None
Ground reference
88
102
103
115
121
122
135
138
144
20
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4.3.2 ZWT Package
4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADCs)
Table 4-20. ZWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
ADREFHI(1)
ADREFLO(1)
VCCAD(1)
VSSAD
V15
V16
W15
V19
W16
W18
W19
Input
Input
ADC high reference supply
ADC low reference supply
Operating supply for ADC
N/A
N/A
None
Power
VSSAD
Ground
None
ADC supply power
VSSAD
VSSAD
Programmable,
20 µA
ADC1 event trigger input, or
GPIO
AD1EVT/MII_RX_ER/RMII_RX_ER
N19
V10
I/O
I/O
Pulldown
Pullup
Programmable,
20 µA
ADC2 event trigger input, or
GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS
AD1IN[0]
W14
V17
V18
T17
U18
R17
T19
V14
P18
W17
U17
U19
T16
T18
R18
P19
V13
U13
U14
U16
U15
T15
R19
R16
AD1IN[1]
AD1IN[2]
AD1IN[3]
Input
N/A
None
ADC1 analog input
AD1IN[4]
AD1IN[5]
AD1IN[6]
AD1IN[7]
AD1IN[8] / AD2IN[8]
AD1IN[9] / AD2IN[9]
AD1IN[10] / AD2IN[10]
AD1IN[11] / AD2IN[11]
AD1IN[12] / AD2IN[12]
AD1IN[13] / AD2IN[13]
AD1IN[14] / AD2IN[14]
AD1IN[15] / AD2IN[15]
AD1IN[16] / AD2IN[0]
AD1IN[17] / AD2IN[1]
AD1IN[18] / AD2IN[2]
AD1IN[19] / AD2IN[3]
AD1IN[20] / AD2IN[4]
AD1IN[21] / AD2IN[5]
AD1IN[22] / AD2IN[6]
AD1IN[23] / AD2IN[7]
ADC1/ADC2 shared analog
inputs
Input
N/A
None
(1) The ADREFHI, ADREFLO, VCCAD, and VSSAD connections are common for both ADC cores.
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4.3.2.2 Enhanced Next Generation High-End Timer (N2HET) Modules
Table 4-21. ZWT Enhanced Next Generation High-End Timer (N2HET) Modules
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
N2HET1[0]/SPI4CLK
K18
V2
N2HET1[1]/SPI4NENA/N2HET2[8]
N2HET1[2]/SPI4SIMO[0]
W5
U1
N2HET1[3]/SPI4NCS[0]/N2HET2[10]
N2HET1[4]
B12
V6
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]
N2HET1[6]/SCIRX
W3
T1
N2HET1[7]/N2HET2[14]
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]
N2HET1[9]/N2HET2[16]
E18
V7
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
N2HET1[12]/MII_CRS/RMII_CRS_DV
N2HET1[13]/SCITX
D19
E3
B4
N2
N2HET1[14]
A11
N1
N2HET1[15]/MIBSPI1NCS[4]
N2HET1[16]
A4
N2HET1[17]
A13
F3
N2HET1 time input capture or
output compare, or GIO.
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
N2HET1[18]
J1
Programmable,
20 µA
I/O
Pulldown
Each terminal has a
suppression filter with a
programmable duration.
N2HET1[19]
B13
G3
P2
MIBSPI1NCS[2]/N2HET1[19]/MDIO
N2HET1[20]
N2HET1[21]
H4
MIBSPI1NCS[3]/N2HET1[21]
N2HET1[22]
J3
B3
N2HET1[23]
J4
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]
N2HET1[25]
G19
P1
M3
V5
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
N2HET1[26]/MII_RXD[1]/RMII_RXD[1]
N2HET1[27]
A14
A9
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4
N2HET1[29]
B2
K19
A3
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
N2HET1[30]/MII_RX_DV
C3
B11
J17
W9
N2HET1[31]
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
Programmable,
20 µA
Disable selected PWM
outputs
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS
B5
I/O
Pulldown
22
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Table 4-21. ZWT Enhanced Next Generation High-End Timer (N2HET) Modules (continued)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
GIOA[2]/N2HET2[0]
C1
D4
E1
EMIF_ADDR[0]/N2HET2[1]
GIOA[3]/N2HET2[2]
EMIF_ADDR[1]/N2HET2[3]
GIOA[6]/N2HET2[4]
D5
H3
D16
M1
N17
V2
EMIF_BA[1]/N2HET2[5]
GIOA[7]/N2HET2[6]
N2HET2 time input capture or
output compare, or GIO.
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]
N2HET1[1]/SPI4NENA/N2HET2[8]
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]
N2HET1[3]/SPI4NCS[0]/N2HET2[10]
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11]
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13]
N2HET1[7]/N2HET2[14]
Programmable,
20 µA
I/O
Pulldown
Each terminal has a
suppression filter with a
programmable duration.
K17
U1
C4
V6
C5
T1
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15]
N2HET1[9]/N2HET2[16]
C6
V7
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
E3
Programmable,
20 µA
Disable selected PWM
outputs
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS
V10
I/O
Pullup
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4.3.2.3 General-Purpose Input/Output (GPIO)
Table 4-22. ZWT General-Purpose Input/Output (GPIO)
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
GIOA[0]
A5
C2
C1
E1
A6
B5
H3
M1
M2
K2
F2
GIOA[1]
GIOA[2]/N2HET2[0]
GIOA[3]/N2HET2[2]
GIOA[4]
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS
GIOA[6]/N2HET2[4]
GIOA[7]/N2HET2[6]
GIOB[0]
General-purpose I/O.
All GPIO terminals are
capable of generating
interrupts to the CPU on rising
/ falling / both edges.
Programmable,
20 µA
Pulldown
GIOB[1]
GIOB[2]
I/O
GIOB[3]
W10
G1
G2
J2
GIOB[4]
GIOB[5]
GIOB[6]
GIOB[7]
F1
The application cannot output
a level onto this terminal
when it is configured as
Fixed 20 µA
Pulldown
GIOB[2]. A pullup is enabled
on this input. This pull cannot
be disabled, and is not
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS
V10
Pullup
programmable using the GIO
module pull control registers
24
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4.3.2.4 Controller Area Network Controllers (DCANs)
Table 4-23. ZWT Controller Area Network Controllers (DCANs)
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
CAN1RX
CAN1TX
CAN2RX
CAN2TX
CAN3RX
CAN3TX
B10
A10
H1
CAN1 receive, or GPIO
CAN1 transmit, or GPIO
CAN2 receive, or GPIO
CAN2 transmit, or GPIO
CAN3 receive, or GPIO
CAN3 transmit, or GPIO
Programmable,
20 µA
I/O
Pullup
H2
M19
M18
4.3.2.5 Local Interconnect Network Interface Module (LIN)
Table 4-24. ZWT Local Interconnect Network Interface Module (LIN)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
LINRX
LINTX
A7
B7
LIN receive, or GPIO
LIN transmit, or GPIO
Programmable,
20 µA
I/O
Pullup
4.3.2.6 Standard Serial Communication Interface (SCI)
Table 4-25. ZWT Standard Serial Communication Interface (SCI)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
N2HET1[6]/SCIRX
N2HET1[13]/SCITX
W3
N2
SCI receive, or GPIO
SCI transmit, or GPIO
Programmable,
20 µA
I/O
Pulldown
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4.3.2.7 Inter-Integrated Circuit Interface Module (I2C)
Table 4-26. ZWT Inter-Integrated Circuit Interface Module (I2C)
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
B2
C3
I2C serial data, or GPIO
I2C serial clock, or GPIO
Programmable,
20 µA
I/O
Pullup
4.3.2.8 Standard Serial Peripheral Interface (SPI)
Table 4-27. ZWT Standard Serial Peripheral Interface (SPI)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
SPI2CLK
E2
N3
D3
D3
SPI2 clock, or GPIO
SPI2NCS[0]
SPI2 chip select, or GPIO
SPI2 chip select, or GPIO
SPI2 enable, or GPIO
SPI2NENA/SPI2NCS[1]
SPI2NENA/SPI2NCS[1]
Programmable,
20 µA
I/O
Pullup
SPI2 slave-input master-
output, or GPIO
SPI2SIMO[0]
D1
D2
SPI2 slave-output master-
input, or GPIO
SPI2SOMI[0]
N2HET1[0]/SPI4CLK
K18
U1
SPI4 clock, or GPIO
N2HET1[3]/SPI4NCS[0]/N2HET2[10]
N2HET1[1]/SPI4NENA/N2HET2[8]
SPI4 chip select, or GPIO
SPI4 enable, or GPIO
V2
Programmable,
20 µA
I/O
Pulldown
SPI4 slave-input master-
output, or GPIO
N2HET1[2]/SPI4SIMO[0]
W5
V6
SPI4 slave-output master-
input, or GPIO
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]
26
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4.3.2.9 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-28. ZWT Multibuffered Serial Peripheral Interface Modules (MibSPI)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
MIBSPI1CLK
F18
R2
F3
MibSPI1 clock, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
MIBSPI1NCS[2]/N2HET1[19]/MDIO
MIBSPI1NCS[3]/N2HET1[21]
Programmable,
20 µA
Pullup
MibSPI1 chip select, or GPIO
G3
J3
N2HET1[15]/MIBSPI1NCS[4]
N1
P1
Programmable,
20 µA
Pulldown
Pullup
MibSPI1 chip select, or GPIO
MibSPI1 enable, or GPIO
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
I/O
G19
Programmable,
20 µA
MibSPI1 slave-in master-out,
or GPIO
MIBSPI1SIMO[0]
F19
E18
Programmable,
20 µA
MibSPI1 slave-in master-out,
or GPIO
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]
Pulldown
Pullup
MIBSPI1SOMI[0]
G18
R2
Programmable,
20 µA
MibSPI1 slave-out master-in,
or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
MIBSPI3CLK
V9
MibSPI3 clock, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
V10
V5
Programmable,
20 µA
Pullup
MibSPI3 chip select, or GPIO
B2
C3
Programmable,
20 µA
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
E3
Pulldown
MibSPI3 chip select, or GPIO
I/O
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
W9
W9
MibSPI3 chip select, or GPIO
MibSPI3 enable, or GPIO
Programmable,
20 µA
MibSPI3 slave-in master-out,
or GPIO
Pullup
MIBSPI3SIMO[0]
MIBSPI3SOMI[0]
W8
V8
MibSPI3 slave-out master-in,
or GPIO
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN
MIBSPI5NCS[0]/DMM_DATA[5]
H19
E19
B6
MibSPI5 clock, or GPIO
MIBSPI5NCS[1]/DMM_DATA[6]
MibSPI5 chip select, or GPIO
MibSPI5 enable, or GPIO
MIBSPI5NCS[2]/DMM_DATA[2]
W6
MIBSPI5NCS[3]/DMM_DATA[3]
T12
H18
J19
E16
H17
G17
J18
E17
H16
G16
MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1]
MIBSPI5SIMO[1]/DMM_DATA[9]
Programmable,
20 µA
I/O
Pullup
MIBSPI5SIMO[2]/DMM_DATA[10]
MIBSPI5SIMO[3]/DMM_DATA[11]
MibSPI5 slave-in master-out,
or GPIO
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0]
MIBSPI5SOMI[1]/DMM_DATA[13]
MIBSPI5SOMI[2]/DMM_DATA[14]
MIBSPI5SOMI[3]/DMM_DATA[15]
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4.3.2.10 Ethernet Controller
Table 4-29. ZWT Ethernet Controller: MDIO Interface
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
MIBSPI1NCS[2]/N2HET1[19]/MDIO
V5
G3
Output
I/O
Pullup
Pullup
None
Serial clock output
Serial data input/output
Fixed, 20 µA
Table 4-30. ZWT Ethernet Controller: Reduced Media Independent Interface (RMII)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
N2HET1[12]/MII_CRS/RMII_CRS_DV
RMII carrier sense and
receive data valid
B4
RMII synchronous reference
clock for receive, transmit and
control interface
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4
K19
Fixed 12-µA
Pulldown
Input
Pulldown
AD1EVT/MII_RX_ER/RMII_RX_ER
N19
P1
RMII receive error
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]
N2HET1[26]/MII_RXD[1]/RMII_RXD[1]
RMII receive data
A14
J18
J19
H19
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0]
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1]
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN
RMII transmit data
Output
Pullup
None
RMII transmit enable
Table 4-31. ZWT Ethernet Controller: Media Independent Interface (MII)
TERMINAL
RESET
SIGNAL
TYPE
PULL
STATE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
F3
B4
Pullup
None
Collision detect
Input
Fixed 20-µA
Pulldown
Carrier sense and receive
data valid
N2HET1[12]/MII_CRS/RMII_CRS_DV
Pulldown
Pulldown
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4
N2HET1[30]/MII_RX_DV
K19
B11
N19
K19
P1
I/O
Input
I/O
None
MII output receive clock
Received data valid
Receive error
AD1EVT/MII_RX_ER/RMII_RX_ER
Fixed 20-µA
Pulldown
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]
N2HET1[26]/MII_RXD[1]/RMII_RXD[1]
Pulldown
Receive clock
A14
G19
H18
D19
D19
J18
J19
R2
Input
I/O
Receive data
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
Fixed 20-µA
Pulldown
Pullup
MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0]
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1]
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]
MII output transmit clock
Transmit clock
Pulldown
None
None
Pullup
Transmit data
Output
E18
H19
Pulldown
Pullup
None
None
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN
Transmit enable
28
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4.3.2.11 External Memory Interface (EMIF)
Table 4-32. External Memory Interface (EMIF)
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
EMIF_CKE
EMIF_CLK
L3
Output
None
EMIF Clock Enable
EMIF clock. This is an output
signal in functional mode. It is
gated off by default, so that
the signal is tri-stated.
Pulldown
K3
I/O
None
PINMUX29[8] must be
cleared to enable this output.
ETMDATA[13]/EMIF_nOE
E12
P3
Pulldown
Pullup
None
EMIF Output Enable
Fixed 20-µA
Pullup
EMIF_nWAIT
I/O
EMIF Extended Wait Signal
EMIF_nWE
EMIF_nCAS
EMIF_nRAS
D17
R4
Output
Output
Output
Output
Output
Output
Output
Output
EMIF Write Enable.
Pullup
EMIF column address strobe
EMIF row address strobe
EMIF chip select, SDRAM
R3
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]
EMIF_nCS[2]
N17
L17
K17
M17
E10
Pulldown
Pullup
EMIF chip selects,
asynchronous
This applies to chip selects 2,
3, and 4
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]
EMIF_nCS[4]/RTP_DATA[7]
ETMDATA[15]/EMIF_nDQM[0]
Pulldown
Pullup
EMIF Data Mask or Write
Strobe.
Data mask for SDRAM
devices, write strobe for
connected asynchronous
devices.
ETMDATA[14]/EMIF_nDQM[1]
E11
Output
EMIF bank address or
address line
ETMDATA[12]/EMIF_BA[0]
EMIF_BA[1]/N2HET2[5]
E13
D16
Output
Output
EMIF bank address or
address line
EMIF_ADDR[0]/N2HET2[1]
D4
D5
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
EMIF_ADDR[1]/N2HET2[3]
ETMDATA[11]/EMIF_ADDR[2]
ETMDATA[10]/EMIF_ADDR[3]
ETMDATA[9]/EMIF_ADDR[4]
E6
E7
None
E8
Pulldown
ETMDATA[8]/EMIF_ADDR[5]
E9
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11]
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13]
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15]
EMIF_ADDR[9]/RTP_DATA[10]
EMIF_ADDR[10]/RTP_DATA[9]
EMIF_ADDR[11]/RTP_DATA[8]
EMIF_ADDR[12]/RTP_DATA[6]
EMIF_ADDR[13]/RTP_DATA[5]
EMIF_ADDR[14]/RTP_DATA[4]
EMIF_ADDR[15]/RTP_DATA[3]
EMIF_ADDR[16]/RTP_DATA[2]
EMIF_ADDR[17]/RTP_DATA[1]
EMIF_ADDR[18]/RTP_DATA[0]
EMIF_ADDR[19]/RTP_nENA
C4
C5
C6
C7
C8
EMIF address
C9
C10
C11
C12
C13
D14
C14
D15
C15
C16
C17
Pulldown
EMIF_ADDR[20]/RTP_nSYNC
EMIF_ADDR[21]/RTP_CLK
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Table 4-32. External Memory Interface (EMIF) (continued)
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
ETMDATA[16]/EMIF_DATA[0]
K15
L15
M15
N15
E5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ETMDATA[17]/EMIF_DATA[1]
ETMDATA[18]/EMIF_DATA[2]
ETMDATA[19]/EMIF_DATA[3]
ETMDATA[20]/EMIF_DATA[4]
ETMDATA[21]/EMIF_DATA[5]
ETMDATA[22]/EMIF_DATA[6]
ETMDATA[23]/EMIF_DATA[7]
ETMDATA[24]/EMIF_DATA[8]
ETMDATA[25]/EMIF_DATA[9]
ETMDATA[26]/EMIF_DATA[10]
ETMDATA[27]/EMIF_DATA[11]
ETMDATA[28]/EMIF_DATA[12]
ETMDATA[29]/EMIF_DATA[13]
ETMDATA[30]/EMIF_DATA[14]
ETMDATA[31]/EMIF_DATA[15]
F5
G5
K5
Fixed 20-µA
Pullup
Pulldown
EMIF Data
L5
M5
N5
P5
R5
R6
R7
R8
30
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4.3.2.12 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
Table 4-33. Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
Fixed 20-µA
Pullup
ETMTRACECLKIN/EXTCLKIN2
R9
Input
Pulldown
ETM Trace Clock Input
ETMTRACECLKOUT
R10
R11
R12
R13
J15
H15
G15
F15
E15
E14
E9
ETM Trace Clock Output
ETM trace control
ETMTRACECTL
ETMDATA[0]
ETMDATA[1]
ETMDATA[2]
ETMDATA[3]
ETMDATA[4]
ETMDATA[5]
ETMDATA[6]
ETMDATA[7]
ETMDATA[8]/EMIF_ADDR[5]
ETMDATA[9]/EMIF_ADDR[4]
ETMDATA[10]/EMIF_ADDR[3]
ETMDATA[11]/EMIF_ADDR[2]
ETMDATA[12]/EMIF_BA[0]
ETMDATA[13]/EMIF_nOE
ETMDATA[14]/EMIF_nDQM[1]
ETMDATA[15]/EMIF_nDQM[0]
ETMDATA[16]/EMIF_DATA[0]
ETMDATA[17]/EMIF_DATA[1]
ETMDATA[18]/EMIF_DATA[2]
ETMDATA[19]/EMIF_DATA[3]
ETMDATA[20]/EMIF_DATA[4]
ETMDATA[21]/EMIF_DATA[5]
ETMDATA[22]/EMIF_DATA[6]
ETMDATA[23]/EMIF_DATA[7]
ETMDATA[24]/EMIF_DATA[8]
ETMDATA[25]/EMIF_DATA[9]
ETMDATA[26]/EMIF_DATA[10]
ETMDATA[27]/EMIF_DATA[11]
ETMDATA[28]/EMIF_DATA[12]
ETMDATA[29]/EMIF_DATA[13]
ETMDATA[30]/EMIF_DATA[14]
ETMDATA[31]/EMIF_DATA[15]
E8
E7
E6
E13
E12
E11
E10
K15
L15
M15
N15
E5
Output
Pulldown
None
ETM data
F5
G5
K5
L5
M5
N5
P5
R5
R6
R7
R8
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4.3.2.13 RAM Trace Port (RTP)
Table 4-34. RAM Trace Port (RTP)
TERMINAL
SIGNAL NAME
RESET
SIGNAL
PULL
PULL TYPE
DESCRIPTION
337
ZWT
TYPE
STATE
EMIF_ADDR[21]/RTP_CLK
EMIF_ADDR[19]/RTP_nENA
C17
C15
I/O
I/O
I/O
RTP packet clock, or GPIO
RTP packet handshake, or
GPIO
EMIF_ADDR[20]/RTP_nSYNC
EMIF_ADDR[18]/RTP_DATA[0]
EMIF_ADDR[17]/RTP_DATA[1]
EMIF_ADDR[16]/RTP_DATA[2]
EMIF_ADDR[15]/RTP_DATA[3]
EMIF_ADDR[14]/RTP_DATA[4]
EMIF_ADDR[13]/RTP_DATA[5]
EMIF_ADDR[12]/RTP_DATA[6]
C16
D15
C14
D14
C13
C12
C11
C10
RTP synchronization, or GPIO
Programmable,
20 µA
Pulldown
Programmable,
20 µA
EMIF_nCS[4]/RTP_DATA[7]
M17
Pullup
I/O
RTP packet data, or GPIO
EMIF_ADDR[11]/RTP_DATA[8]
C9
C8
EMIF_ADDR[10]/RTP_DATA[9]
EMIF_ADDR[9]/RTP_DATA[10]
C7
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15]
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13]
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11]
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]
C6
Programmable,
20 µA
Pulldown
C5
C4
N17
K17
32
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4.3.2.14 Data Modification Module (DMM)
Table 4-35. Data Modification Module (DMM)
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
DMM_CLK
F17
F16
DMM clock, or GPIO
DMM_nENA
DMM handshake, or GPIO
DMM synchronization, or
GPIO
DMM_SYNC
J16
DMM_DATA[0]
DMM_DATA[1]
L19
L18
W6
MIBSPI5NCS[2]/DMM_DATA[2]
MIBSPI5NCS[3]/DMM_DATA[3]
T12
H19
E19
B6
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN
MIBSPI5NCS[0]/DMM_DATA[5]
Programmable,
20 µA
I/O
Pullup
MIBSPI5NCS[1]/DMM_DATA[6]
MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1]
MIBSPI5SIMO[1]/DMM_DATA[9]
H18
J19
E16
H17
G17
J18
E17
H16
G16
DMM data, or GPIO
MIBSPI5SIMO[2]/DMM_DATA[10]
MIBSPI5SIMO[3]/DMM_DATA[11]
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0]
MIBSPI5SOMI[1]/DMM_DATA[13]
MIBSPI5SOMI[2]/DMM_DATA[14]
MIBSPI5SOMI[3]/DMM_DATA[15]
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4.3.2.15 System Module Interface
Table 4-36. ZWT System Module Interface
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
Power-on reset, cold reset
External power supply monitor
circuitry must drive nPORRST
low when any of the supplies
to the microcontroller fall out
of the specified range. This
terminal has a glitch filter.
See Section 6.8.
Fixed 100-µA
Pulldown
nPORRST
W7
Input
Pulldown
System reset, warm reset,
bidirectional.
The internal circuitry indicates
any reset condition by driving
nRST low.
The external circuitry can
assert a system reset by
driving nRST low. To ensure
that an external reset is not
arbitrarily generated, TI
recommends that an external
pullup resistor is connected to
this terminal.
Fixed 100-µA
Pullup
nRST
B17
I/O
Pullup
This terminal has a glitch
filter. See Section 6.8.
ESM Error Signal
Indicates error of high
severity. See Section 6.18.
Fixed 20-µA
Pulldown
nERROR
B14
I/O
Pulldown
4.3.2.16 Clock Inputs and Outputs
Table 4-37. ZWT Clock Inputs and Outputs
TERMINAL
RESET
SIGNAL
PULL
PULL TYPE
DESCRIPTION
337
ZWT
TYPE
SIGNAL NAME
STATE
From external
OSCIN
K1
Input
crystal/resonator, or external
clock input
N/A
None
KELVIN_GND
OSCOUT
L2
L1
Input
Kelvin ground for oscillator
To external crystal/resonator
Output
Programmable,
20 µA
External prescaled clock
output, or GIO.
ECLK
A12
I/O
Pulldown
Pulldown
N/A
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS
ETMTRACECLKIN/EXTCLKIN2
B5
R9
Input
Input
External clock input #1
External clock input #2
Fixed 20-µA
Pulldown
1.2-V
Power
Dedicated core supply for
PLLs
VCCPLL
P11
None
34
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4.3.2.17 Test and Debug Modules Interface
Table 4-38. ZWT Test and Debug Modules Interface
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
Test enable. This terminal
must be connected to ground
directly or through a pulldown
resistor.
TEST
U2
I/O
Fixed 100-µA
Pulldown
Pulldown
nTRST
RTCK
D18
A16
Input
JTAG test hardware reset
JTAG return test clock
Output
N/A
None
Fixed 100-µA
Pulldown
TCK
TDI
B18
A17
C18
C19
Input
I/O
Pulldown
JTAG test clock
JTAG test data in
JTAG test data out
JTAG test select
Fixed 100-µA
Pullup
Pullup
100 µA
Pulldown
TDO
TMS
Output
I/O
None
Fixed 100-µA
Pullup
Pullup
4.3.2.18 Flash Supply and Test Pads
Table 4-39. ZWT Flash Supply and Test Pads
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
3.3-V
Power
VCCP
FLTP1
F8
J5
N/A
N/A
None
None
Flash pump supply
Flash test pads. These
terminals are reserved for TI
use only. For proper operation
these terminals must connect
only to a test pad or not be
connected at all [no connect
(NC)].
–
FLTP2
H5
4.3.2.19 Reserved
Table 4-40. Reserved
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A15
B15
B16
A8
–
–
–
–
–
–
N/A
N/A
N/A
N/A
N/A
N/A
None
None
None
None
None
None
Reserved. These balls are
connected to internal logic but
are not outputs nor do they
have internal pulls. They are
subject to ±1 µA leakage
current.
B8
B9
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4.3.2.20 No Connects
Table 4-41. No Connects
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D6
D7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
D8
D9
D10
D11
D12
D13
E4
F4
G4
K4
K16
L4
L16
M4
M16
N4
N16
N18
P4
No Connects. These balls are
not connected to any internal
logic and can be connected to
the PCB ground without
affecting the functionality of
the device.
P15
P16
P17
R1
R14
R15
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T13
T14
U3
U4
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Table 4-41. No Connects (continued)
TERMINAL
RESET
SIGNAL
PULL
PULL TYPE
DESCRIPTION
337
ZWT
TYPE
SIGNAL NAME
STATE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
U5
U6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
U7
U8
U9
U10
U11
U12
V3
No Connects. These balls are
not connected to any internal
logic and can be connected to
the PCB ground without
affecting the functionality of
the device.
V4
V11
V12
W4
W11
W12
W13
4.3.2.21 Supply for Core Logic: 1.2-V Nominal
Table 4-42. ZWT Supply for Core Logic: 1.2-V Nominal
TERMINAL
SIGNAL NAME
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F9
F10
H10
J14
K6
1.2-V
Power
K8
N/A
None
Core supply
K12
K14
L6
M10
P10
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4.3.2.22 Supply for I/O Cells: 3.3-V Nominal
Table 4-43. ZWT Supply for I/O Cells: 3.3-V Nominal
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
F6
F7
F11
F12
F13
F14
G6
G14
H6
H14
J6
3.3-V
Power
L14
M6
N/A
None
Operating supply for I/Os
M14
N6
N14
P6
P7
P8
P9
P12
P13
P14
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4.3.2.23 Ground Reference for All Supplies Except VCCAD
Table 4-44. ZWT Ground Reference for All Supplies Except VCCAD
TERMINAL
RESET
PULL
STATE
SIGNAL
TYPE
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
A2
A18
A19
B1
B19
H8
H9
H11
H12
J8
J9
J10
J11
J12
K9
Ground
N/A
None
Ground reference
K10
K11
L8
L9
L10
L11
L12
M8
M9
M11
M12
V1
W1
W2
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5 Specifications
(1)
5.1 Absolute Maximum Ratings
Over Operating Free-Air Temperature Range
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
1.43
4.6
UNIT
(2)
VCC
(2)
Supply voltage
Input voltage
VCCIO, VCCP
VCCAD
V
6.25
4.6
All input pins
V
ADC input pins
6.25
IIK (VI < 0 or VI > VCCIO
All pins, except AD1IN[23:0] and AD2IN[15:0]
)
–20
–10
20
10
mA
Input clamp current
IIK (VI < 0 or VI > VCCAD
AD1IN[23:0] and AD2IN[15:0]
)
Total
–40
–40
–40
–65
40
105
130
150
mA
°C
°C
°C
Operating free-air temperature, TA:
Operating junction temperature, TJ:
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated
grounds.
5.2 ESD Ratings
VALUE
±2
UNIT
kV
Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1)
Charged device model (CDM), per JESD22-C101(2) All pins
VESD
Electrostatic discharge (ESD) performance:
±250
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Power-On Hours (POH)(1)(2)
JUNCTION
TEMPERATURE (Tj)
NOMINAL CORE VOLTAGE (VCC
)
LIFETIME POH
1.2
105ºC
100K
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms
and conditions for TI semiconductor products.
(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to
equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application
Report (SPNA207).
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5.4 Recommended Operating Conditions(1)
MIN
1.14
1.14
3
NOM
1.2
MAX UNIT
VCC
Digital logic supply voltage (Core)
PLL Supply Voltage
1.32
1.32
3.6
V
V
VCCPLL
VCCIO
VCCAD
VCCP
1.2
Digital logic supply voltage (I/O)
MibADC supply voltage
3.3
V
3
3.3/5.0
3.3
5.25
3.6
V
Flash pump supply voltage
3
V
VSS
Digital logic supply ground
0
V
VSSAD
VADREFHI
VADREFLO
VSLEW
TA
MibADC supply ground
–0.1
VSSAD
VSSAD
0.1
VCCAD
VCCAD
1
V
A-to-D high-voltage reference source
A-to-D low-voltage reference source
Maximum positive slew rate for VCCIO, VCCAD and VCCP supplies
Operating free-air temperature
Operating junction temperature(2)
V
V
V/µs
°C
°C
105
TJ
130
(1) All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD
(2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.
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5.5 Switching Characteristics for Clock Domains
Over Recommended Operating Conditions
Table 5-1. Clock Domain Timing Specifications
PARAMET
ER
DESCRIPTION
CONDITIONS
MIN
MAX UNIT
Pipeline mode enabled
Pipeline mode disabled
200
MHz
50
fHCLK
HCLK - System clock frequency
fGCLK
fVCLK
GCLK - CPU clock frequency
fHCLK MHz
100 MHz
VCLK - Primary peripheral clock frequency
VCLK2 - Secondary peripheral clock
frequency
fVCLK2
fVCLK3
fVCLKA1
fVCLKA3
100 MHz
100 MHz
100 MHz
48 MHz
VCLK3 - Secondary peripheral clock
frequency
VCLKA1 - Primary asynchronous peripheral
clock frequency
VCLKA3 - Primary asynchronous peripheral
clock frequency
VCLKA4 - Secondary asynchronous
peripheral clock frequency
fVCLKA4
fRTICLK
50 MHz
RTICLK - clock frequency
fVCLK MHz
5.6 Wait States Required
RAM
0
0
Address Wait States
0MHz
fHCLK(max)
Data Wait States
0MHz
fHCLK(max)
Flash
1
Address Wait States
0
150MHz
150MHz
0MHz
fHCLK(max)
Data Wait States
0
1
2
3
0MHz
50MHz
100MHz
fHCLK(max)
Figure 5-1. Wait States Scheme
As shown in Figure 5-1, the TCM RAM can support program and data fetches at full CPU speed without any
address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined
mode. The flash supports a maximum CPU clock speed of 200 MHz in pipelined mode with one address wait
state and three data wait states.
The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data wait
state.
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5.7 Power Consumption
Over Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
fHCLK = 200 MHz
MIN
TYP
MAX UNIT
VCC Digital supply current (operating
mode)
240(1)
400(2)
fVCLK = 100 MHz,
Flash in pipelined mode, VCCmax
ICC, ICCPLL
mA
VCC Digital supply current (LBIST mode)
LBIST clock rate = 100 MHz
655(3)(4)
655(3)(4)
PBIST ROM clock frequency =
100 MHz
VCC Digital supply current (PBIST mode)
ICCIO
VCCIO supply current (operating mode)
VCCAD supply current (operating mode)
No DC load, VCCmax
10 mA
Single ADC operational, VCCADmax
Both ADCs operational, VCCADmax
Single ADC operational, ADREFHImax
Both ADCs operational, ADREFHImax
15
30
3
ICCAD
mA
mA
IADREFHI
ICCP
ADREFHI supply current (operating mode)
VCCP pump supply current
6
Read from 1 bank and program or
erase another bank, VCCPmax
60 mA
(1) The typical value is the average current for the nominal process corner and junction temperature of 25ºC.
(2) The maximum ICC, value can be derated
•
•
•
linearly with voltage
by 1 mA/MHz for lower operating frequency when fHCLK= 2 * fVCLK
for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.
166 - 0.15 e0.0174 T
JK
(3) The maximum ICC, value can be derated
•
•
•
linearly with voltage
by 1.7 mA/MHz for lower operating frequency when fHCLK= 2 * fVCLK
for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.
166 - 0.15 e0.0174 T
JK
(4) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the
device and the voltage regulator
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5.8 Input/Output Electrical Characteristics(1)
Over Recommended Operating Conditions
PARAMETER
Input hysteresis
Low-level input voltage
TEST CONDITIONS
MIN
180
–0.3
2
TYP
MAX UNIT
Vhys
VIL
All inputs
All inputs(2)
mV
0.8
VCCIO + 0.3
0.2 VCCIO
V
V
VIH
High-level input voltage All inputs(2)
IOL = IOLmax
IOL = 50 µA, standard
output mode
0.2
VOL
Low-level output voltage
V
V
IOL = 50 µA, low-EMI
output mode (see
Section 5.13)
0.2 VCCIO
IOH = IOHmax
0.8 VCCIO
IOH = 50 µA, standard
output mode
VCCIO – 0.3
VOH
IIC
II
High-level output voltage
IOH = 50 µA, low-EMI
output mode (see
Section 5.13)
0.8 VCCIO
VI < VSSIO – 0.3 or VI >
VCCIO + 0.3
Input clamp current (I/O pins)
–3.5
3.5 mA
IIH Pulldown 20 µA
VI = VCCIO
5
40
40
IIH Pulldown 100 µA VI = VCCIO
195
Input current (I/O pins)
IIL Pullup 20 µA
IIL Pullup 100 µA
All other pins
VI = VSS
–40
–195
–1
–5 µA
–40
VI = VSS
No pullup or pulldown
1
CI
Input capacitance
Output capacitance
2
3
pF
pF
CO
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) This does not apply to the nPORRST pin.
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5.9 Thermal Resistance Characteristics
Table 5-2 shows the thermal resistance characteristics for the QFP - PGE mechanical package.
Table 5-3 shows the thermal resistance characteristics for the BGA - ZWT mechanical package.
Table 5-2. Thermal Resistance Characteristics (PGE Package)
°C / W
Junction-to-free air thermal resistance, Still air using JEDEC 2S2P test
board
RΘJA
39
RΘJB
RΘJC
ΨJT
Junction-to-board thermal resistance
Junction-to-case thermal resistance
Junction-to-package top, Still air
26.3
6.7
0.10
Table 5-3. Thermal Resistance Characteristics (ZWT Package)
°C / W
Junction-to-free air thermal resistance, Still air (includes 5 × 5 thermal via
cluster in 2s2p PCB connected to first ground plane)
RΘJA
18.8
RΘJB
RΘJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
14.1
7.1
Junction-to-package top, Still air (includes 5 × 5 thermal via cluster in
2s2p PCB connected to first ground plane)
ΨJT
0.33
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5.10 Output Buffer Drive Strengths
Table 5-4. Output Buffer Drive Strengths
LOW-LEVEL OUTPUT CURRENT,
IOL for VI=VOLmax
or
SIGNALS
HIGH-LEVEL OUTPUT CURRENT,
IOH for VI=VOHmin
MIBSPI5CLK,
MIBSPI5SOMI[0],
MIBSPI5SOMI[1],
MIBSPI5SOMI[2],
MIBSPI5SOMI[3],
MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],
TMS, TDI, TDO, RTCK,
8 mA
4 mA
SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR,
N2HET2[1], N2HET2[3],
All EMIF Outputs and I/Os, All ETM Outputs
MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK,
nRST
AD1EVT,
CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,
DMM_CLK, DMM_DATA[0], DMM_DATA[1], DMM_nENA, DMM_SYNC,
GIOA[0-7], GIOB[0-7],
LINRX, LINTX,
2 mA zero-dominant
MIBSPI1NCS[0],
MIBSPI1NCS[1-3],
MIBSPI1NENA,
MIBSPI3NCS[0-3],
MIBSPI3NENA,
MIBSPI5NCS[0-3], MIBSPI5NENA,
N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7],
N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14],
N2HET2[15], N2HET2[16], N2HET2[18],
SPI2NCS[0], SPI2NENA, SPI4NCS[0], SPI4NENA
ECLK,
selectable 8 mA/2 mA
SPI2CLK, SPI2SIMO, SPI2SOMI
The default output buffer drive strength is 8 mA for these signals.
Table 5-5. Selectable 8 mA/2 mA Control
SIGNAL
ECLK
CONTROL BIT
ADDRESS
0xFFFFFF78
0xFFF7F668
0xFFF7F668
0xFFF7F668
8 mA
2 mA
SYSPC10[0]
SPI2PC9[9](1)
SPI2PC9[10](1)
SPI2PC9[11](1)
0
0
0
0
1
1
1
1
SPI2CLK
SPI2SIMO
SPI2SOMI
(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these 2 bits
differ, SPI2PC9[11] determines the drive strength.
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5.11 Input Timings
tpw
VCCIO
Input
VIH
VIH
VIL
VIL
0
Figure 5-2. TTL-Level Inputs
Table 5-6. Timing Requirements for Inputs(1)
MIN
MAX
UNIT
tpw
Input minimum pulse width
tc(VCLK) + 10(2)
ns
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(2) The timing shown in Figure 5-2 is only valid for pins used in GPIO mode.
5.12 Output Timings
Table 5-7. Switching Characteristics for Output Timings Versus Load Capacitance (CL)
PARAMETER
MIN
MAX
2.5
4
UNIT
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL= 50 pF
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
7.2
12.5
2.5
4
8 mA low EMI pins
(see Table 5-4)
ns
7.2
12.5
5.6
10.4
16.8
23.2
5.6
10.4
16.8
23.2
8
4 mA low EMI pins
(see Table 5-4)
ns
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
15
23
33
2 mA-z low EMI pins
(see Table 5-4)
ns
8
15
23
33
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Table 5-7. Switching Characteristics for Output Timings Versus Load Capacitance (CL) (continued)
PARAMETER
MIN
MAX
2.5
4
UNIT
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
7.2
12.5
2.5
4
8 mA mode
ns
7.2
12.5
8
Selectable 8 mA/2 mA-z pins
(see Table 5-4)
15
23
33
8
2 mA-z mode
ns
15
23
33
tr
t
f
VCCIO
Output
VOH
VOH
VOL
VOL
0
Figure 5-3. CMOS-Level Outputs
Table 5-8. Timing Requirements for Outputs(1)
MIN
MAX
UNIT
ns
Delay between low-to-high, or high-to-low transition of general-purpose output
signals that can be configured by an application in parallel, for example, all signals in
a GIOA port, or all N2HET1 signals, and so forth.
td(parallel_out)
5
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check
Table 5-4 for output buffer drive strength information on each signal.
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5.13 Low-EMI Output Buffers
The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of
emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of
the output buffer, and is particularly effective with capacitive loads.
This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the
system module GPCR1 register for the desired module or signal, as shown in Table 5-9. The adaptive
impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates
two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of
VCCIO, respectively.
Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then
the impedance of the output buffer will increase to Hi-Z. A high degree of decoupling between the internal
ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing,
for example, the buffer is driving low on a resistive path to ground. Current loads on the buffer which try to
pull the output voltage above VREFLOW will be opposed by the impedance of the output buffer so as to
maintain the output voltage at or below VREFLOW.
Conversely, once the output buffer has driven the output to a high level, if the output voltage is above
VREFHIGH then the impedance of the output buffer will again increase to Hi-Z. A high degree of
decoupling between internal power bus ad output pin will occur with capacitive loads or any loads in which
no current is flowing, for example, buffer is driving high on a resistive path to VCCIO. Current loads on the
buffer which try to pull the output voltage below VREFHIGH will be opposed by the impedance of the
buffer output so as to maintain the output voltage at or above VREFHIGH.
The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance
control mode cannot respond to high-frequency noise coupling into the power buses of the buffer. In this
manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.
Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will
allow a positive current load to pull the output voltage up to VCCIO + 0.6 V without opposition. Also, a
negative current load will pull the output voltage down to VSSIO – 0.6 V without opposition. This is not an
issue because the actual clamp current capability is always greater than the IOH / IOL specifications.
The low-EMI output buffers are automatically configured to be in the standard buffer mode when the
device enters a low-power mode.
Table 5-9. Low-EMI Output Buffer Hookup
CONTROL REGISTER TO
MODULE OR SIGNAL NAME
ENABLE LOW-EMI MODE
Module: MibSPI1
Module: SPI2
Module: MibSPI3
Reserved
GPREG1.0
GPREG1.1
GPREG1.2
GPREG1.3
GPREG1.4
GPREG1.5
GPREG1.6
GPREG1.7
GPREG1.8
GPREG1.9
GPREG1.10
GPREG1.11
GPREG1.12
GPREG1.13
Reserved
Reserved
Reserved
Reserved
Signal: TMS
Signal: TDI
Signal: TDO
Signal: RTCK
Signal: TEST
Signal: nERROR
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Table 5-9. Low-EMI Output Buffer Hookup (continued)
CONTROL REGISTER TO
ENABLE LOW-EMI MODE
MODULE OR SIGNAL NAME
Reserved
Reserved
GPREG1.14
GPREG1.15
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6 System Information and Electrical Specifications
6.1 Device Power Domains
The device core logic is split up into multiple power domains in order to optimize the power for a given
application use case. There are eight core power domains in total: PD1, PD2, PD3, PD4, PD5, RAM_PD1,
RAM_PD2, and RAM_PD3.
The actual contents of these power domains are indicated in Section 1.4.
PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains
can be turned ON/OFF one time during device initialization as per the application requirement. Refer to
the Power Management Module (PMM) chapter of RM48x Technical Reference Manual (SPNU503) for
more details.
NOTE
The clocks to a module must be turned off before powering down the core domain that
contains the module.
NOTE
The logic in the modules that are powered down lose power completely. Any access to
modules that are powered down results in an abort being generated. When power is
restored, the modules power up to their default states (after normal power up). No register or
memory contents are preserved in the core domains that are turned off.
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6.2 Voltage Monitor Characteristics
A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the
requirement for a specific sequence when powering up the core and I/O voltage supplies.
6.2.1 Important Considerations
•
The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the
device is held in reset when the voltage supplies are out of range.
•
The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other
supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a
source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and
VCCP supplies.
6.2.2 Voltage Monitor Operation
The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO
signal (PGIO) on the device. During power-up or power-down processes, the PGMCU and PGIO are
driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The
PGIO and PGMCU being low isolates the core logic as well as the I/O controls during power up or power
down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.
When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When
the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output
pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device
enters a low-power mode.
The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing
information on this glitch filter.
Table 6-1. Voltage Monitoring Specifications
PARAMETER
MIN
TYP
MAX UNIT
VCC low - VCC level below this threshold is detected as too
low.
0.75
0.9
1.13
Voltage monitoring VCC high - VCC level above this threshold is detected as
VMON
1.40
1.85
1.7
2.4
2.1
2.9
V
thresholds
too high.
VCCIO low - VCCIO level below this threshold is detected
as too low.
6.2.3 Supply Filtering
The VMON has the capability to filter glitches on the VCC and VCCIO supplies.
Table 6-2 shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum
specification cannot be filtered.
Table 6-2. VMON Supply Glitch Filtering Capability
PARAMETER
Width of glitch on VCC that can be filtered
Width of glitch on VCCIO that can be filtered
MIN
250
250
MAX
1000
1000
UNIT
ns
ns
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6.3 Power Sequencing and Power On Reset
6.3.1 Power-Up Sequence
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-
up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for
more details), core voltage rising above the minimum core supply threshold and the release of power-on
reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The
oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The
different supplies to the device can be powered up in any order.
The device goes through the following sequential phases during power up.
Table 6-3. Power-Up Phases
Oscillator start-up and validity check
eFuse autoload
1032 oscillator cycles
1180 oscillator cycles
688 oscillator cycles
617 oscillator cycles
3517 oscillator cycles
Flash pump power up
Flash bank power up
Total
The CPU reset is released at the end of the sequence in Table 6-3 and fetches the first instruction from
address 0x00000000.
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6.3.2 Power-Down Sequence
The different supplies to the device can be powered down in any order.
6.3.3 Power-On Reset: nPORRST
This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core
supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an
internal pulldown.
6.3.3.1 nPORRST Electrical and Timing Requirements
Table 6-4. Electrical Requirements for nPORRST
NO.
PARAMETER
MIN
MAX UNIT
VCCPORL
VCCPORH
VCC low supply level when nPORRST must be active during power up
0.5
V
VCC high supply level when nPORRST must remain active during power
up and become active during power down
1.14
V
VCCIO / VCCP low supply level when nPORRST must be active during
power up
VCCIOPORL
1.1
V
V
VCCIO / VCCP high supply level when nPORRST must remain active
during power up and become active during power down
VCCIOPORH
VIL(PORRST)
3.0
Low-level input voltage of nPORRST VCCIO > 2.5V
Low-level input voltage of nPORRST VCCIO < 2.5V
0.2 * VCCIO
0.5
V
V
Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during
power up
3
tsu(PORRST)
0
ms
6
7
8
9
th(PORRST)
tsu(PORRST)
th(PORRST)
th(PORRST)
Hold time, nPORRST active after VCC > VCCPORH
1
2
1
0
ms
µs
Setup time, nPORRST active before VCC < VCCPORH during power down
Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH
Hold time, nPORRST active after VCC < VCCPORL
ms
ms
Filter time nPORRST pin;
tf(nPORRST)
500
2000
ns
pulses less than MIN will be filtered out, pulses greater than MAX will
generate a reset.
3.3 V
VCCIOPORH
VCCIOPORH
VCCIO / VCCP
8
6
1.2 V
VCCPORH
VCC
VCCPORH
7
6
VCCIOPORL
7
VCCIOPORL
VCCPORL
VCCPORL
VCC (1.2 V)
VCCIO / VCCP(3.3 V)
3
9
VIL
VIL
VIL
VIL(PORRST)
VIL(PORRST)
nPORRST
NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.
Figure 6-1. nPORRST Timing Diagram
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6.4 Warm Reset (nRST)
This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset
condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the
output buffer is implemented as an open drain (drives low only). To ensure an external reset is not
arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup
6.4.1 Causes of Warm Reset
Table 6-5. Causes of Warm Reset
DEVICE EVENT
SYSTEM STATUS FLAG
Exception Status Register, bit 15
Global Status Register, bit 0
Power-Up Reset
Oscillator fail
PLL slip
Global Status Register, bits 8 and 9
Exception Status Register, bit 13
Exception Status Register, bit 5
Exception Status Register, bit 4
Exception Status Register, bit 3
Watchdog exception / Debugger reset
CPU Reset (driven by the CPU STC)
Software Reset
External Reset
6.4.2 nRST Timing Requirements
Table 6-6. nRST Timing Requirements
MIN
MAX
UNIT
(1)
tv(RST)
Valid time, nRST active after nPORRST inactive
Valid time, nRST active (all other System reset conditions)
2256tc(OSC)
ns
32tc(VCLK)
tf(nRST) Filter time nRST pin; pulses less than MIN will be filtered out; pulses greater
than MAX will generate a reset. See Section 6.8.
475
2000
ns
(1) Assumes the oscillator has started up and stabilized before nPORRST is released .
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6.5 ARM Cortex-R4F CPU Information
6.5.1 Summary of ARM Cortex-R4F CPU Features
The features of the ARM Cortex-R4F CPU include:
•
•
An integer unit with integral EmbeddedICE-RT logic.
High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
•
•
•
•
•
Floating Point Coprocessor
Dynamic branch prediction with a global history buffer, and a 4-entry return stack
Low interrupt latency.
Nonmaskable interrupt.
A Harvard Level one (L1) memory system with:
–
Tightly Coupled Memory (TCM) interfaces with support for error correction or parity checking
memories
–
ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
•
•
Dual core logic for fault detection in safety-critical applications.
An L2 memory interface:
–
–
Single 64-bit master AXI interface
64-bit slave AXI interface to TCM RAM blocks
•
•
•
•
•
•
A debug interface to a CoreSight Debug Access Port (DAP).
Six Hardware Breakpoints
Two Watchpoints
A trace interface to a CoreSight ETM-R4.
A Performance Monitoring Unit (PMU).
A Vectored Interrupt Controller (VIC) port.
For more information on the ARM Cortex-R4F CPU see www.arm.com.
6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
The following CPU features are disabled on reset and must be enabled by the application if required.
•
•
•
•
ECC On TCM Accesses
Hardware VIC Port
Floating Point Coprocessor
MPU
6.5.3 Dual Core Implementation
The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-
R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two
clock cycles as shown in Figure 6-3.
The CPUs have a diverse CPU placement given by following requirements:
•
•
different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation
dedicated guard ring for each CPU
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Flip West
North
Figure 6-2. Dual-CPU Orientation
6.5.4 Duplicate Clock Tree After GCLK
The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU
running at the same frequency and in phase to the clock of CPU1. See Figure 6-3.
6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in
the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in
a different way as shown in Figure 6-3.
Output + Control
CCM-R4
2 cycle delay
CCM-R4
compare
compare
error
CPU1CLK
CPU 1
CPU 2
2 cycle delay
CPU2CLK
Input + Control
Figure 6-3. Dual Core Implementation
To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of
both CPUs before the registers are used, including function calls where the register values are pushed
onto the stack.
6.5.6 CPU Self-Test
The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the
Deterministic Logic BIST Controller as the test engine.
The main features of the self-test controller are:
•
Ability to divide the complete test run into independent test intervals
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•
•
Capable of running the complete test as well as running few intervals at a time
Ability to continue from the last executed interval (test set) as well as ability to restart from the
beginning (First test set)
•
•
•
Complete isolation of the self-tested CPU core from rest of the system during the self-test run
Ability to capture the Failure interval number
Time-out counter for the CPU self-test run as a fail-safe feature
6.5.6.1 Application Sequence for CPU Self-Test
1. Configure clock domain frequencies.
2. Select number of test intervals to be run.
3. Configure the time-out period for the self-test run.
4. Enable self-test.
5. Wait for CPU reset.
6. In the reset handler, read CPU self-test status to identify any failures.
7. Retrieve CPU state if required.
For more information see the device specific technical reference manual.
6.5.6.2 CPU Self-Test Clock Configuration
The maximum clock rate for the self-test is 100 MHz. The STCCLK is divided down from the CPU clock.
This divider is configured by the STCCLKDIV register at address 0xFFFFE108.
For more information see the device specific technical reference manual.
6.5.6.3 CPU Self-Test Coverage
Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test
cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.
Table 6-7. CPU Self-Test Coverage
INTERVALS
TEST COVERAGE, %
0
TEST CYCLES
0
0
1
62.13
1365
2
70.09
2730
3
74.49
4095
4
77.28
5460
5
79.28
6825
6
80.90
8190
7
82.02
9555
8
83.10
10920
12285
13650
15015
16380
17745
19110
20475
21840
23205
24570
25935
9
84.08
10
11
12
13
14
15
16
17
18
19
84.87
85.59
86.11
86.67
87.16
87.61
87.98
88.38
88.69
88.98
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Table 6-7. CPU Self-Test Coverage (continued)
INTERVALS
TEST COVERAGE, %
TEST CYCLES
27300
20
21
22
23
24
89.28
89.50
89.76
90.01
90.21
28665
30030
31395
32760
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6.6 Clocks
6.6.1 Clock Sources
Table 6-8 lists the available clock sources on the device. Each of the clock sources can be enabled or
disabled using the CSDISx registers in the system module. The clock source number in the table
corresponds to the control bit in the CSDISx register for that clock source.
Table 6-8 also shows the default state of each clock source.
Table 6-8. Available Clock Sources
CLOCK
SOURCE
NO.
DEFAULT
STATE
NAME
DESCRIPTION
0
1
2
3
4
5
6
7
OSCIN
PLL1
Main Oscillator
Output From PLL1
Reserved
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
Reserved
EXTCLKIN1
CLK80K
CLK10M
PLL2
External Clock Input #1
Low-Frequency Output of Internal Reference Oscillator
High-Frequency Output of Internal Reference Oscillator
Output From PLL2
EXTCLKIN2
External Clock Input #2
6.6.1.1 Main Oscillator
The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors
across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage
inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test
measurement and low power modes.
TI strongly encourages each customer to submit samples of the device to the resonator/crystal
vendors for validation. The vendors are equipped to determine what load capacitors will best tune
their resonator/crystal to the microcontroller device for optimum start-up and operation over
temperature/voltage extremes.
An external oscillator source can be used by connecting a 3.3-V clock signal to the OSCIN pin and leaving
the OSCOUT pin unconnected (open) as shown in Figure 6-4.
(see Note B)
OSCIN
Kelvin_GND
OSCOUT
OSCIN
OSCOUT
C1
C2
External
Clock Signal
(toggling 0 V to 3.3 V)
(see Note A)
Crystal
(a)
(b)
Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Note B: Kelvin_GND should not be connected to any other GND.
Figure 6-4. Recommended Crystal/Clock Connection
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6.6.1.1.1 Timing Requirements for Main Oscillator
Table 6-9. Timing Requirements for Main Oscillator
MIN
50
50
6
MAX
200
UNIT
ns
tc(OSC)
Cycle time, OSCIN (when using a sine-wave input)
tc(OSC_SQR)
tw(OSCIL)
tw(OSCIH)
Cycle time, OSCIN, (when input to the OSCIN is a square wave )
Pulse duration, OSCIN low (when input to the OSCIN is a square wave)
Pulse duration, OSCIN high (when input to the OSCIN is a square wave)
200
ns
ns
6
ns
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6.6.1.2 Low-Power Oscillator (LPO)
The LPO is comprised of two oscillators — HF LPO and LF LPO, in a single macro.
6.6.1.2.1 Features
The main features of the LPO are:
•
•
•
Supplies a clock at extremely low power for power-saving modes. This is connected as clock source
# 4 of the GCM.
Supplies a high-frequency clock for nontiming-critical systems. This is connected as clock source # 5
of the GCM.
Provides a comparison clock for the crystal oscillator failure detection circuit.
BIAS_EN
LFEN
CLK80K
LF_TRIM
Low-Power
Oscillator
HFEN
CLK10M
HF_TRIM
CLK10M_VALID
nPORRST
Figure 6-5. LPO Block Diagram
Figure 6-5 shows a block diagram of the internal reference oscillator. This is an LPO and provides two
clock sources: one nominally 80 kHz and one nominally 10 MHz.
6.6.1.2.2 LPO Electrical and Timing Specifications
Table 6-10. LPO Specifications
PARAMETER
MIN
TYP
MAX
UNIT
Oscillator fail frequency - lower threshold, using
untrimmed LPO output
1.375
2.4
4.875
Clock Detection
Oscillator fail frequency - higher threshold, using
untrimmed LPO output
MHz
22
38.4
78
Untrimmed frequency
Trimmed frequency
5.5
8
9
19.5
11
9.6
MHz
µs
LPO - HF oscillator
Start-up time from STANDBY (LPO BIAS_EN High for
at least 900 µs)
(fHFLPO
)
10
Cold start-up time
900
180
µs
Untrimmed frequency
36
85
kHz
LPO - LF oscillator
(fLFLPO
Start-up time from STANDBY (LPO BIAS_EN High for
at least 900 µs)
100
µs
µs
)
Cold start-up time
2000
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6.6.1.3 Phase Locked Loop (PLL) Clock Modules
The PLL is used to multiply the input frequency to some higher frequency.
The main features of the PLL are:
•
Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The
frequency modulation capability of PLL2 is permanently disabled.
•
•
•
Configurable frequency multipliers and dividers.
Built-in PLL Slip monitoring circuit.
Option to reset the device on a PLL slip detection.
6.6.1.3.1 Block Diagram
Figure 6-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and
PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the
multiplier and dividers for PLL2.
/NR
/OD
/R
PLLCLK
OSCIN
INTCLK
VCOCLK
post_ODCLK
PLL
/1 to /64
/1 to /8
/1 to /32
fPLLCLK = (fOSCIN / NR) * NF / (OD * R)
/NF
/1 to /256
/NR2
/OD2
/R2
PLL2CLK
OSCIN
VCOCLK2
INTCLK2
post_ODCLK2
/1 to /64
PLL#2
/1 to /8
/1 to /32
fPLL2CLK = (fOSCIN / NR2) * NF2 / (OD2 * R2)
/NF2
/1 to /256
Figure 6-6. ZWT PLLx Block Diagram
6.6.1.3.2 PLL Timing Specifications
Table 6-11. PLL Timing Specifications
PARAMETER
MIN
MAX
20
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
fINTCLK
PLL1 Reference Clock frequency
1
fpost_ODCLK
fVCOCLK
Post-ODCLK – PLL1 Post-divider input clock frequency
VCOCLK – PLL1 Output Divider (OD) input clock frequency
PLL2 Reference Clock frequency
400
550
20
150
1
fINTCLK2
fpost_ODCLK2
fVCOCLK2
Post-ODCLK – PLL2 Post-divider input clock frequency
VCOCLK – PLL2 Output Divider (OD) input clock frequency
400
550
150
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6.6.1.4 External Clock Inputs
The device supports up to two external clock inputs. This clock input must be a square wave input. The
electrical and timing requirements for these clock inputs are specified in Table 6-12. The external clock
sources are not checked for validity. They are assumed valid when enabled.
Table 6-12. External Clock Timing and Electrical Specifications
PARAMETER
fEXTCLKx
DESCRIPTION
External clock input frequency
EXTCLK high-pulse duration
EXTCLK low-pulse duration
Low-level input voltage
MIN
MAX
UNIT
MHz
ns
80
tw(EXTCLKIN)H
tw(EXTCLKIN)L
viL(EXTCLKIN)
viH(EXTCLKIN)
6
6
ns
-0.3
2
0.8
V
High-level input voltage
VCCIO + 0.3
V
6.6.2 Clock Domains
6.6.2.1 Clock Domain Descriptions
Table 6-13 lists the device clock domains and their default clock sources. The table also shows the
system module control register that is used to select an available clock source for each clock domain.
Table 6-13. Clock Domain Descriptions
CLOCK SOURCE
SELECTION
REGISTER
CLOCK DOMAIN
DEFAULT CLOCK
SOURCE
DESCRIPTION
NAME
HCLK
OSCIN
GHVSRC
•
•
Is disabled via the CDDISx registers bit 1
Used for all system modules including DMA, ESM
GCLK
OSCIN
GHVSRC
•
•
•
Always the same frequency as HCLK
In phase with HCLK
Is disabled separately from HCLK through the CDDISx registers
bit 0
•
Can be divided by 1 up to 8 when running CPU self-test
(LBIST) using the CLKDIV field of the STCCLKDIV register at
address 0xFFFFE108
GCLK2
OSCIN
GHVSRC
•
•
•
•
Always the same frequency as GCLK
2 cycles delayed from GCLK
Is disabled along with GCLK
Gets divided by the same divider setting as that for GCLK when
running CPU self-test (LBIST)
VCLK
OSCIN
OSCIN
GHVSRC
GHVSRC
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK through the CDDISx registers
bit 2
VCLK2
•
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Frequency must be an integer multiple of VCLK frequency
Is disabled separately from HCLK through the CDDISx registers
bit 3
VCLK3
OSCIN
VCLK
GHVSRC
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK through the CDDISx registers
bit 8
VCLKA1
VCLKASRC
•
•
Defaults to VCLK as the source
Is disabled via the CDDISx registers bit 4
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Table 6-13. Clock Domain Descriptions (continued)
CLOCK SOURCE
SELECTION
CLOCK DOMAIN
DEFAULT CLOCK
SOURCE
DESCRIPTION
NAME
REGISTER
VCLKA3
VCLK
VCLKACON1
•
•
•
Defaults to VCLK as the source
Frequency can be as fast as HCLK frequency.
Is disabled through the CDDISx registers bit 10
VCLKA3_DIVR
VCLK
VCLKACON1
•
Divided down from the VCLKA3 using the VCLKA3R field of the
VCLKACON1 register at address 0xFFFFE140
•
•
•
Frequency can be VCLKA3/1, VCLKA3/2, ..., or VCLKA3/8
Default frequency is VCLKA3/2
Is disabled separately through the VCLKACON1 register
VCLKA3_DIV_CDDIS bit only if the VCLKA3 clock is not
disabled
VCLKA4
RTICLK
VCLK
VCLK
VCLKACON1
RCLKSRC
•
•
Defaults to VCLK as the source
Is disabled through the CDDISx registers bit 11
•
•
Defaults to VCLK as the source
If a clock source other than VCLK is selected for RTICLK, then
the RTICLK frequency must be less than or equal to VCLK/3
–
Application can ensure this by programming the RTI1DIV
field of the RCLKSRC register, if necessary
•
Is disabled through the CDDISx registers bit 6
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6.6.2.2 Mapping of Clock Domains to Device Modules
Each clock domain has a dedicated functionality as shown in Figure 6-7.
GCM
0
GCLK, GCLK2 (to CPU)
HCLK (to SYSTEM)
OSCIN
PLL #1 (FMzPLL)
1
X1..256
/1..32
/1..64
/1..8
*
/1..16
VCLK_peri (VCLK to peripherals on PCR1)
VCLK_sys (VCLK to system modules)
VCLK2 (to N2HETx and HTUx)
VCLK3 (to EMIF)
4
5
80kHz
10MHz
/1..16
/1..16
Low Power
Oscillator
PLL # 2 (FMzPLL)
6
/1..32
*
/1..64 X1..256
/1..8
0
1
3
4
5
6
3
7
EXTCLKIN1
EXTCLKIN2
VCLKA1 (to DCANx)
* the frequency at this node must not
exceed the maximum HCLK specifiation.
7
VCLK
0
1
VCLK3
3
4
VCLKA4
VCLKA4 (to Ethernet, as alternate
for MIITXCLK and/or MIIRXCLK)
5
6
7
VCLK
0
1
3
4
/1, 2, 4, or 8
5
6
7
Ethernet
EMIF
RTICLK (to RTI, DWWD)
VCLK
VCLKA1
VCLK
VCLK2
VCLK2
HRP
/1..64
/1,2,..256
/2,3..224
/1,2..32
/1,2..65536
/1,2..256
/1,2,..1024
N2HETx
TU
LRP
/20..25
Prop_seg
Phase_seg2
I2C baud
rate
ECLK
SPI
Baud Rate
ADCLK
LIN / SCI
Baud Rate
Phase_seg1
I2C
Loop
High
Resolution Clock
SPIx,MibSPIx
LIN, SCI
External Clock
MibADCx
EXTCLKIN1
NTU[3]
CAN Baud Rate
DCANx
PLL#2 output
Reserved
NTU[2]
NTU[1]
NTU[0]
N2HETx
RTI
Reserved
Figure 6-7. Device Clock Domains
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6.6.3 Clock Test Mode
The RM4x platform architecture defines a special mode that allows various clock signals to be brought out
on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very
useful for debugging purposes and can be configured through the CLKTEST register in the system
module.
Table 6-14. Clock Test Mode Options
SEL_ECP_PIN
SEL_GIO_PIN
=
=
SIGNAL ON ECLK
SIGNAL ON N2HET1[12]
CLKTEST[3-0]
CLKTEST[11-8]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Oscillator
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Oscillator Valid Status
Main PLL Valid status
Reserved
Main PLL free-running clock output
Reserved
EXTCLKIN1
Reserved
CLK80K
Reserved
CLK10M
CLK10M Valid status
Secondary PLL Valid Status
Reserved
Secondary PLL free-running clock output
EXTCLKIN2
GCLK
CLK80K
RTI Base
Reserved
VCLKA1
Reserved
VCLKA3
VCLKA4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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6.7 Clock Monitoring
The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal LPO.
The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).
The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN
frequency falls out of a frequency window, the CLKDET flags this condition in the global status register
(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp
mode clock).
The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4.
6.7.1 Clock Monitor Timings
For more information on LPO and Clock detection, refer to Table 6-10.
upper
threshold
lower
threshold
fail
pass
fail
f[MHz]
1.375
4.875
22
78
Figure 6-8. LPO and Clock Detection, Untrimmed HFLPO
6.7.2 External Clock (ECLK) Output Functionality
The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock.
This output can be externally monitored as a safety diagnostic.
6.7.3 Dual Clock Comparators
The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by
counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of
spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the
reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration
allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.
An additional use of this module is to measure the frequency of a selectable clock source, using the input
clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a
fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width
pulse (1 cycle) after a preprogrammed number of pulses. This pulse sets as an error signal if counter 1
does not reach 0 within the counting window generated by counter 0.
6.7.3.1 Features
•
•
Takes two different clock sources as input to two independent counter blocks.
One of the clock sources is the known-good, or reference clock; the second clock source is the "clock
under test."
•
•
Each counter block is programmable with initial, or seed values.
The counter blocks start counting down from their seed values at the same time; a mismatch from the
expected frequency for the clock under test generates an error signal which is used to interrupt the
CPU.
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6.7.3.2 Mapping of DCC Clock Source Inputs
Table 6-15. DCC1 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
Oscillator (OSCIN)
High-frequency LPO
Test clock (TCK)
Others
0x5
0xA
Table 6-16. DCC1 Counter 1 Clock Sources
KEY [3:0]
CLOCK SOURCE [3:0]
CLOCK NAME
Others
-
0x0
N2HET1[31]
Main PLL free-running clock output
reserved
0x1
0x2
Low-frequency LPO
High-frequency LPO
Flash HD pump oscillator
EXTCLKIN1
0xA
0x3
0x4
0x5
0x6
EXTCLKIN2
0x7
Ring oscillator
0x8 - 0xF
VCLK
Table 6-17. DCC2 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
Others
0xA
Oscillator (OSCIN)
Test clock (TCK)
Table 6-18. DCC2 Counter 1 Clock Sources
KEY [3:0]
Others
0xA
CLOCK SOURCE [3:0]
CLOCK NAME
N2HET2[0]
Reserved
VCLK
-
00x0 - 0x7
0x8 - 0xF
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6.8 Glitch Filters
A glitch filter is present on the following signals.
Table 6-19. Glitch Filter Timing Specifications
PIN
PARAMETER
MIN
MAX
UNIT
Filter time nPORRST pin;
nPORRST
tf(nPORRST)
475
2000
ns
pulses less than MIN will be filtered out, pulses greater than
MAX will generate a reset(1)
Filter time nRST pin;
nRST
TEST
tf(nRST)
475
475
2000
2000
ns
ns
pulses less than MIN will be filtered out, pulses greater than
MAX will generate a reset
Filter time TEST pin;
tf(TEST)
pulses less than MIN will be filtered out, pulses greater than
MAX will pass through
(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,
I/O pins, and so forth) without also generating a valid reset signal to the CPU.
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6.9 Device Memory Map
6.9.1 Memory Map Diagram
The figures below show the device memory maps.
0xFFFFFFFF
SYSTEM Modules
0xFFF80000
Peripherals - Frame 1
0xFF000000
0xFE000000
CRC
RESERVED
0xFCFFFFFF
0xFC000000
Peripherals - Frame 2
RESERVED
0xF07FFFFF
Flash Module Bus2 Interface
(Flash ECC, OTP and EEPROM accesses)
0xF0000000
RESERVED
0x87FFFFFF
0x80000000
EMIF (128MB)
SDRAM
CS0
RESERVED
reserved
CS4
0x6FFFFFFF
0x60000000
0x6C000000
0x68000000
0x64000000
EMIF (16MB * 3)
Async RAM
CS3
CS2
RESERVED
0x202FFFFF
0x20000000
Flash (3MB) (Mirrored Image)
RESERVED
0x0843FFFF
0x08400000
RAM - ECC
RESERVED
0x0803FFFF
0x08000000
RAM (256KB)
RESERVED
Flash (3MB)
0x002FFFFF
0x00000000
Figure 6-9. RM48L940 Memory Map
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0xFFFFFFFF
SYSTEM Modules
0xFFF80000
Peripherals - Frame 1
0xFF000000
0xFE000000
CRC
RESERVED
0xFCFFFFFF
0xFC000000
Peripherals - Frame 2
RESERVED
0xF07FFFFF
Flash Module Bus2 Interface
(Flash ECC, OTP and EEPROM accesses)
0xF0000000
0x87FFFFFF
RESERVED
EMIF (128MB)
SDRAM
CS0
0x80000000
0x6FFFFFFF
RESERVED
reserved
CS4
0x6C000000
0x68000000
0x64000000
EMIF (16MB * 3)
Async RAM
CS3
CS2
0x60000000
RESERVED
0x201FFFFF
0x20000000
Flash (2MB) (Mirrored Image)
RESERVED
0x0843FFFF
0x08400000
RAM - ECC
RESERVED
0x0803FFFF
0x08000000
RAM (256KB)
RESERVED
Flash (2MB)
0x001FFFFF
0x00000000
Figure 6-10. RM48L740 Memory Map
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0xFFFFFFFF
SYSTEM Modules
0xFFF80000
Peripherals - Frame 1
0xFF000000
0xFE000000
CRC
RESERVED
0xFCFFFFFF
0xFC000000
Peripherals - Frame 2
RESERVED
0xF07FFFFF
Flash Module Bus2 Interface
(Flash ECC, OTP and EEPROM accesses)
0xF0000000
RESERVED
0x87FFFFFF
0x80000000
EMIF (128MB)
SDRAM
CS0
RESERVED
reserved
CS4
0x6FFFFFFF
0x60000000
0x6C000000
0x68000000
0x64000000
EMIF (16MB * 3)
Async RAM
CS3
CS2
RESERVED
0x201FFFFF
0x20000000
Flash (2MB) (Mirrored Image)
RESERVED
0x0842FFFF
0x08400000
RAM - ECC
RESERVED
0x0802FFFF
0x08000000
RAM (192KB)
RESERVED
Flash (2MB)
0x001FFFFF
0x00000000
Figure 6-11. RM48L540 Memory Map
The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash
image is 0x20000000.
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6.9.2 Memory Map Table
Table 6-20. Device Memory Map
FRAME ADDRESS RANGE
FRAME
RESPONSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
MODULE NAME
ACTUAL
SIZE
SELECT
SIZE
START
END
MEMORIES TIGHTLY COUPLED TO THE ARM CORTEX-R4F CPU
TCM Flash
CS0
0x00000000
0x08000000
0x20000000
0x00FFFFFF
0x0BFFFFFF
0x20FFFFFF
16MB
64MB
16MB
3MB(1)
256KB(2)
3MB(1)
TCM RAM + RAM
ECC
CSRAM0
Abort
Mirrored Flash
Flash mirror frame
EXTERNAL MEMORY ACCESSES
EMIF Chip Select 2
(asynchronous)
EMIF select 2
EMIF select 3
EMIF select 4
EMIF select 0
0x60000000
0x64000000
0x68000000
0x80000000
0x63FFFFFF
0x67FFFFFF
0x6BFFFFFF
0x87FFFFFF
64MB
64MB
64MB
128MB
16MB
16MB
16MB
128MB
EMIF Chip Select 3
(asynchronous)
Access to "Reserved" space will generate
Abort
EMIF Chip Select 4
(asynchronous)
EMIF Chip Select 0
(synchronous)
FLASH MODULE BUS2 INTERFACE
Customer OTP,
TCM Flash Bank 0
0xF0000000
0xF0002000
0xF000E000
0xF0001FFF
0xF0003FFF
0xF000FFFF
8KB
8KB
8KB
4KB
4KB
2KB
Customer OTP,
TCM Flash Bank 1
Customer OTP,
EEPROM Bank 7
Customer
OTP–ECC, TCM
Flash Bank 0
0xF0040000
0xF0040400
0xF0041C00
0xF00403FF
0xF00407FF
0xF0041FFF
1KB
1KB
1KB
512B
512B
256B
Customer
OTP–ECC, TCM
Flash Bank 1
Customer
OTP–ECC,
EEPROM Bank 7
TI OTP, TCM Flash
Bank 0
0xF0080000
0xF0082000
0xF008E000
0xF00C0000
0xF00C0400
0xF00C1C00
0xF0081FFF
0xF0083FFF
0xF008FFFF
0xF00C03FF
0xF00C07FF
0xF00C1FFF
8KB
8KB
8KB
1KB
1KB
1KB
4KB
4KB
Abort
TI OTP, TCM Flash
Bank 1
TI OTP, EEPROM
Bank 7
2KB
TI OTP–ECC, TCM
Flash Bank 0
512B
512B
256B
TI OTP–ECC, TCM
Flash Bank 1
TI OTP–ECC,
EEPROM Bank 7
EEPROM
Bank–ECC
0xF0100000
0xF0200000
0xF0400000
0xF013FFFF
0xF03FFFFF
0xF04FFFFF
256KB
2MB
8KB
64KB
384KB
EEPROM Bank
Flash Data Space
ECC
1MB
ETHERNET AND EMIF SLAVE INTERFACES
CPPI Memory Slave
(Ethernet RAM)
0xFC520000
0xFCF78000
0xFCF78800
0xFC521FFF
0xFCF787FF
0xFCF788FF
8KB
2KB
8KB
2KB
Abort
EMAC Slave
(Ethernet Slave)
No error
No error
EMACSS Wrapper
(Ethernet Wrapper)
256B
256B
(1) The RM48L740 and RM48L540 devices only have 2MB of Flash
(2) The RM48L540 device has only 192KB of RAM.
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Table 6-20. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPONSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME
SIZE
ACTUAL
SIZE
MODULE NAME
START
END
Ethernet MDIO
Interface
0xFCF78900
0xFCFFE800
0xFCF789FF
0xFCFFE8FF
256B
256B
256B
256B
No error
Abort
EMIF Registers
CYCLIC REDUNDANCY CHECKER (CRC) MODULE REGISTERS
CRC
CRC frame
0xFE000000
0xFEFFFFFF
16MB
512B
Accesses above 0x200 generate abort.
PERIPHERAL MEMORIES
MIBSPI5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
PCS[5]
PCS[6]
PCS[7]
0xFF0A0000
0xFF0C0000
0xFF0E0000
0xFF0BFFFF
0xFF0DFFFF
0xFF0FFFFF
128KB
2KB
2KB
2KB
Abort for accesses above 2KB
Abort for accesses above 2KB
Abort for accesses above 2KB
128KB
128KB
Wrap around for accesses to
unimplemented address offsets lower than
0x7FF. Abort generated for accesses
beyond offset 0x800.
DCAN3 RAM
DCAN2 RAM
DCAN1 RAM
MIBADC2 RAM
MIBADC1 RAM
N2HET2 RAM
N2HET1 RAM
PCS[13]
PCS[14]
PCS[15]
PCS[29]
PCS[31]
PCS[34]
PCS[35]
0xFF1A0000
0xFF1C0000
0xFF1E0000
0xFF3A0000
0xFF3E0000
0xFF440000
0xFF460000
0xFF1BFFFF
0xFF1DFFFF
0xFF1FFFFF
0xFF3BFFFF
0xFF3FFFFF
0xFF45FFFF
0xFF47FFFF
128KB
128KB
128KB
128KB
128KB
128KB
128KB
2KB
2KB
Wrap around for accesses to
unimplemented address offsets lower than
0x7FF. Abort generated for accesses
beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower than
0x7FF. Abort generated for accesses
beyond offset 0x800.
2KB
Wrap around for accesses to
unimplemented address offsets lower than
0x1FFF. Abort generated for accesses
beyond 0x1FFF.
8KB
Wrap around for accesses to
unimplemented address offsets lower than
0x1FFF. Abort generated for accesses
beyond 0x1FFF.
8KB
Wrap around for accesses to
unimplemented address offsets lower than
0x3FFF. Abort generated for accesses
beyond 0x3FFF.
16KB
16KB
Wrap around for accesses to
unimplemented address offsets lower than
0x3FFF. Abort generated for accesses
beyond 0x3FFF.
HTU2 RAM
HTU1 RAM
PCS[38]
PCS[39]
0xFF4C0000
0xFF4E0000
0xFF4DFFFF
0xFF4FFFFF
128KB
128KB
1KB
1KB
Abort
Abort
DEBUG COMPONENTS
CoreSight Debug
ROM
CSCS0
0xFFA00000
0xFFA00FFF
4KB
4KB
Reads: 0, writes: no effect
Cortex-R4F Debug
ETM-R4
CSCS1
CSCS2
CSCS3
CSCS4
0xFFA01000
0xFFA02000
0xFFA03000
0xFFA04000
0xFFA01FFF
0xFFA02FFF
0xFFA03FFF
0xFFA04FFF
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Abort
CoreSight TPIU
POM
PERIPHERAL CONTROL REGISTERS
HTU1
HTU2
PS[22]
PS[22]
PS[17]
PS[17]
PS[16]
PS[15]
PS[15]
PS[10]
PS[8]
0xFFF7A400
0xFFF7A500
0xFFF7B800
0xFFF7B900
0xFFF7BC00
0xFFF7C000
0xFFF7C200
0xFFF7D400
0xFFF7DC00
0xFFF7DE00
0xFFF7E000
0xFFF7A4FF
0xFFF7A5FF
0xFFF7B8FF
0xFFF7B9FF
0xFFF7BCFF
0xFFF7C1FF
0xFFF7C3FF
0xFFF7D4FF
0xFFF7DDFF
0xFFF7DFFF
0xFFF7E1FF
256B
256B
256B
256B
256B
512B
512B
256B
512B
512B
512B
256B
256B
256B
256B
256B
512B
512B
256B
512B
512B
512B
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
N2HET1
N2HET2
GPIO
MIBADC1
MIBADC2
I2C
DCAN1
DCAN2
DCAN3
PS[8]
PS[7]
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Table 6-20. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPONSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME
SIZE
ACTUAL
SIZE
MODULE NAME
START
END
LIN
SCI
PS[6]
PS[6]
PS[2]
PS[2]
PS[1]
PS[1]
PS[0]
0xFFF7E400
0xFFF7E500
0xFFF7F400
0xFFF7F600
0xFFF7F800
0xFFF7FA00
0xFFF7FC00
0xFFF7E4FF
0xFFF7E5FF
0xFFF7F5FF
0xFFF7F7FF
0xFFF7F9FF
0xFFF7FBFF
0xFFF7FDFF
256B
256B
512B
512B
512B
512B
512B
256B
256B
512B
512B
512B
512B
512B
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
MibSPI1
SPI2
MibSPI3
SPI4
MibSPI5
SYSTEM MODULES CONTROL REGISTERS AND MEMORIES
DMA RAM
VIM RAM
PPCS0
PPCS2
0xFFF80000
0xFFF80FFF
4KB
4KB
Abort
Wrap around for accesses to
unimplemented address offsets between
1kB and 4kB.
0xFFF82000
0xFFF82FFF
4KB
1KB
RTP RAM
Flash Module
eFuse Controller
PPCS3
PPCS7
PPCS12
0xFFF83000
0xFFF87000
0xFFF8C000
0xFFF83FFF
0xFFF87FFF
0xFFF8CFFF
4KB
4KB
4KB
4KB
4KB
4KB
Abort
Abort
Abort
Power Management
Module (PMM)
PPSE0
0xFFFF0000
0xFFFF01FF
512B
512B
Abort
Test Controller
(FMTM)
PPSE1
PPS0
0xFFFF0400
0xFFFFE000
0xFFFF07FF
0xFFFFE0FF
1KB
1KB
Reads: 0, writes: no effect
Reads: 0, writes: no effect
PCR registers
256B
256B
System Module -
Frame 2 (see device
TRM)
PPS0
0xFFFFE100
0xFFFFE1FF
256B
256B
Reads: 0, writes: no effect
PBIST
STC
PPS1
PPS1
0xFFFFE400
0xFFFFE600
0xFFFFE5FF
0xFFFFE6FF
512B
256B
512B
256B
Reads: 0, writes: no effect
Generates address error interrupt, if
enabled
IOMM Multiplexing
Control Module
PPS2
0xFFFFEA00
0xFFFFEBFF
512B
512B
Reads: 0, writes: no effect
DCC1
DMA
PPS3
PPS4
PPS5
PPS5
PPS5
PPS5
PPS6
PPS6
PPS6
PPS7
PPS7
PPS7
0xFFFFEC00
0xFFFFF000
0xFFFFF400
0xFFFFF500
0xFFFFF600
0xFFFFF700
0xFFFFF800
0xFFFFF900
0xFFFFFA00
0xFFFFFC00
0xFFFFFD00
0xFFFFFE00
0xFFFFECFF
0xFFFFF3FF
0xFFFFF4FF
0xFFFFF5FF
0xFFFFF6FF
0xFFFFF7FF
0xFFFFF8FF
0xFFFFF9FF
0xFFFFFAFF
0xFFFFFCFF
0xFFFFFDFF
0xFFFFFEFF
256B
1KB
256B
1KB
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Reads: 0, writes: no effect
DCC2
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
ESM
CCMR4
DMM
RAM ECC even
RAM ECC odd
RTP
RTI + DWWD
VIM Parity
VIM
System Module -
Frame 1 (see device
TRM)
PPS7
0xFFFFFF00
0xFFFFFFFF
256B
256B
Reads: 0, writes: no effect
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6.9.3 Master/Slave Access Privileges
Table 6-21 lists the access permissions for each bus master on the device. A bus master is a module that
can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
Table 6-21. Master / Slave Access Matrix
MASTERS
ACCESS MODE
SLAVES ON MAIN SCR
CRC
Flash Module
Bus2 Interface:
OTP, ECC,
Non-CPU
Accesses to
Program Flash
and CPU Data
RAM
EMIF, Ethernet
Slave Interfaces
Peripheral
Control
Registers, All
Peripheral
Memories, And
All System
Module Control
Registers And
Memories
EEPROM Bank
CPU READ
CPU WRITE
DMA
User/Privilege
User/Privilege
User
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
POM
User
DMM
User
DAP
Privilege
Privilege
Privilege
User
HTU1
HTU2
No
EMAC DMA
No
6.9.3.1 Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned OFF.
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6.9.4 POM Overlay Considerations
•
The POM overlay can map onto up to 8MB of the internal or external memory space. The starting
address and the size of the memory overlay are configurable via the POM module control registers.
Care must be taken to ensure that the overlay is mapped on to available memory.
•
•
•
ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors
will be generated.
POM overlay must not be enabled when the flash and internal RAM memories are swapped via the
MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
When POM is used to overlay the flash onto internal or external RAM, there is a bus contention
possibility when another master accesses the TCM flash. This results in a system hang.
–
–
–
The POM module implements a time-out feature to detect this exact scenario. The time-out needs
to be enabled whenever POM overlay is enabled.
The time-out can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global
Control register (POMGLBCTRL, address = 0xFFA04000).
In case a read request by the POM cannot be completed within 32 HCLK cycles, the time-out (TO)
flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is
generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a
data fetch.
–
The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM module
is set. If so, then the application can assume that the time-out is caused by a bus contention
between the POM transaction and another master accessing the same memory region. The abort
handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been
caused due to a time-out from the POM.
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6.10 Flash Memory
6.10.1 Flash Memory Configuration
Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a
customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense
amplifiers, and control logic.
Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical
construction constraints.
Flash Pump: A charge pump which generates all the voltages required for reading, programming, or
erasing the flash banks.
Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.
Table 6-22. Flash Memory Banks and Sectors
SECTOR
NO.
SEGMENT
(BYTES)
MEMORY ARRAYS (OR BANKS)(1)
LOW ADDRESS
HIGH ADDRESS
BANK0 (1.5MB)
0
1
32KB
32KB
0x00000000
0x00008000
0x00010000
0x00018000
0x00020000
0x00040000
0x00060000
0x00080000
0x000A0000
0x000C0000
0x000E0000
0x00100000
0x00120000
0x00140000
0x00160000
0x00180000
0x001A0000
0x001C0000
0x001E0000
0x00200000
0x00220000
0x00240000
0x00260000
0x00280000
0x002A0000
0x002C0000
0x002E0000
0xF0200000
0xF0204000
0xF0208000
0xF020C000
0x00007FFF
0x0000FFFF
0x00017FFF
0x0001FFFF
0x0003FFFF
0x0005FFFF
0x0007FFFF
0x0009FFFF
0x000BFFFF
0x000DFFFF
0x000FFFFF
0x0011FFFF
0x0013FFFF
0x0015FFFF
0x0017FFFF
0x0019FFFF
0x001BFFFF
0x001DFFFF
0x001FFFFF
0x0021FFFF
0x0023FFFF
0x0025FFFF
0x0027FFFF
0x0029FFFF
0x002BFFFF
0x002DFFFF
0x002FFFFF
0xF0203FFF
0xF0207FFF
0xF020BFFF
0xF020FFFF
2
32KB
3
32KB
4
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
16KB
5
6
7
8
9
10
11
12
13
14
0
BANK1 (1.5MB)
1
2
3
(3MB devices only)
4
5
6
7
8
9
10
11
0
BANK7 (64KB) for EEPROM emulation(2)(3)
1
16KB
2
16KB
3
16KB
(1) The flash banks are 144-bit-wide bank with ECC support.
(2) The flash bank7 can be programmed while executing code from flash bank0 or bank1.
(3) Code execution is not allowed from flash bank7.
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6.10.2 Main Features of Flash Module
•
•
•
•
•
•
Support for multiple flash banks for program and/or data storage
Simultaneous read access on a bank while performing program or erase operation on any other bank
Integrated state machines to automate flash erase and program operations
Software interface for flash program and erase operations
Pipelined mode operation to improve instruction access interface bandwidth
Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU
–
Error address is captured for host system debugging
•
Support for a rich set of diagnostic features
6.10.3 ECC Protection for Flash Accesses
All accesses to the program flash memory are protected by Single Error Correction Double Error Detection
(SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of
instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on
the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is
corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error
via its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the
'X' bit of the Performance Monitor Control Register, c9.
MRC p15,#0,r1,c9,c12,#0
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0
MRC p15,#0,r1,c9,c12,#0
;Enabling Event monitor states
;Set 4th bit (‘X’) of PMNC register
The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM
and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC
checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN
bits of the System Control coprocessor's Auxiliary Control Register, c1.
MRC p15, #0, r1, c1, c0, #1
ORR r1, r1, #0x0e000000
DMB
;Enable ECC checking for ATCM and BTCMs
MCR p15, #0, r1, c1, c0, #1
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6.10.4 Flash Access Speeds
For information on flash memory access speeds and the relevant wait states required, refer to Section 5.6.
6.10.5 Flash Program and Erase Timings for Program Flash
Table 6-23. Timing Specifications for Program Flash
PARAMETER
MIN
NOM
MAX
300
32
UNIT
µs
s
tprog (144bit)
tprog (Total)
Wide Word (144bit) programming time
40
–40°C to 105°C
3-MB programming time(1)
Sector/Bank erase time(2)
0°C to 60°C, for first 25 cycles
–40°C to 105°C
8
0.03
16
16
s
4
s
terase
0°C to 60°C, for first 25 cycles
100
ms
Write/erase cycles with 15-year Data
Retention requirement
twec
–40°C to 105°C
1000
cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.
6.10.6 Flash Program and Erase Timings for Data Flash
Table 6-24. Timing Specifications for Data Flash
PARAMETER
MIN
NOM
MAX UNIT
tprog (144bit)
tprog (Total)
Wide Word (144bit) programming time
40
300
660
330
8
µs
ms
ms
s
–40°C to 105°C
64-KB programming time(1)
Sector/Bank erase time(2)
0°C to 60°C, for first 25 cycles
–40°C to 105°C
165
0.2
14
terase
0°C to 60°C, for first 25 cycles
100
ms
Write/erase cycles with 15-year Data
Retention requirement
twec
–40°C to 105°C
100000 cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.
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6.11 Tightly Coupled RAM (TCRAM) Interface Module
Figure 6-12 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F CPU.
36 Bit
Upper 32 bitsdata &
4 ECC bits
wide
RAM
Cortex-R4F
TCM BUS
TCRAM
B0
TCM
36 Bit
Interface 1
wide
RAM
72 Bit data + ECC
Lower32 bits data &
4 ECC bits
36 Bit
wide
RAM
Upper 32 bitsdata &
4 ECC bits
B1
TCM
TCM BUS
TCRAM
Interface 2
72 Bit data + ECC
36 Bit
wide
RAM
Lower32 bits data &
4 ECC bits
Figure 6-12. TCRAM Block Diagram
6.11.1 Features
The features of the TCRAM Module are:
•
•
•
•
•
•
•
•
Acts as slave to the BTCM interface of the Cortex-R4F CPU
Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code
Monitors CPU Event Bus and generates single or multibit error interrupts
Stores addresses for single and multibit errors
Supports RAM trace module
Provides CPU address bus integrity checking by supporting parity checking on the address bus
Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved
RAM banks and generating independent RAM access control signals to the two banks
•
Supports auto-initialization of the RAM banks along with the ECC bits
6.11.2 TCRAM Interface ECC Support
The TCRAM interface passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM.
It also stores the ECC port contents of the CPU in the ECC RAM when the CPU does a write to the RAM.
The TCRAM interface monitors the event bus of the CPU and provides registers for indicating singlebit or
multibit errors and also for identifying the address that caused the single or multibit error. The event
signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.
For more information see the device specific technical reference manual.
6.12 Parity Protection for Peripheral RAMs
Most peripheral RAMs are protected by odd/even parity checking. During a read access the parity is
calculated based on the data read from the peripheral RAM and compared with the good parity value
stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a
parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral
RAM address that caused the parity error.
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The parity protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity protection for
accesses to its RAM.
NOTE
The CPU read access gets the actual data from the peripheral. The application can choose
to generate an interrupt whenever a peripheral RAM parity error is detected.
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6.13 On-Chip SRAM Initialization and Testing
6.13.1 On-Chip SRAM Self-Test Using PBIST
6.13.1.1 Features
•
•
•
Extensive instruction set to support various memory test algorithms
ROM-based algorithms allow application to run TI production-level memory tests
Independent testing of all on-chip SRAM
6.13.1.2 PBIST RAM Groups
Table 6-25. PBIST RAM Grouping
TEST PATTERN (ALGORITHM)
MARCH 13N(1) MARCH 13N(1)
TRIPLE READ TRIPLE READ
TWO PORT
(CYCLES)
SINGLE PORT
(CYCLES)
MEMORY
RAM GROUP
TEST CLOCK
MEM TYPE
SLOW READ
FAST READ
ALGO MASK
0x1
ALGO MASK
0x2
ALGO MASK
0x4
ALGO MASK
0x8
PBIST_ROM
STC_ROM
DCAN1
1
ROM CLK
ROM CLK
VCLK
VCLK
VCLK
HCLK
VCLK
VCLK
VCLK
VCLK
VCLK
HCLK
VCLK
VCLK
HCLK
VCLK
VCLK
VCLK
HCLK
HCLK
ROM
24578
19586
8194
6530
2
ROM
3
Dual Port
Dual Port
Dual Port
Single Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Single Port
Single Port
25200
25200
25200
DCAN2
4
DCAN3
5
ESRAM1(2)
MIBSPI1
MIBSPI3
MIBSPI5
VIM
6
266280
7
33440
33440
33440
12560
4200
8
9
10
11
12
13
14
15
18
19
20
21
22
23
24
25
28
MIBADC1
DMA
18960
31680
6480
N2HET1
HTU1
RTP
37800
4200
MIBADC2
N2HET2
HTU2
ESRAM5(3)
ESRAM6(4)
31680
6480
266280
266280
8700
6360
Dual Port
ETHERNET
ESRAM8(5)
VCLK3
HCLK
Single Port
Single Port
133160
266280
(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for
application testing.
(2) ESRAM1: Address 0x08000000 - 0x0800FFFF (Always on power domain)
(3) ESRAM5: Address 0x08010000 - 0x0801FFFF (RAM power domain 1)
(4) ESRAM6: Address 0x08020000 - 0x0802FFFF (RAM power domain 2)
(5) ESRAM8: Address 0x08030000 - 0x0803FFFF (RAM power domain 3) Not available on theRM48L540 device.
The PBIST ROM clock frequency is limited to 100 MHz, if 100 MHz < HCLK <= HCLKmax, or HCLK, if
HCLK <= 100 MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV
field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
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6.13.2 On-Chip SRAM Auto Initialization
This microcontroller allows some of the on-chip memories to be initialized to zero through the Memory
Hardware Initialization mechanism in the System module. This hardware mechanism allows an application
to program the memory arrays with error detection capability to a known state based on their error
detection scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects
the memories that are to be initialized.
For more information on these registers see the device specific technical reference manual.
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in
Table 6-26.
Table 6-26. Memory Initialization
ADDRESS RANGE
BASE ADDRESS
MSINENA REGISTER
BIT NO.
CONNECTING MODULE
ENDING ADDRESS
0x0800FFFF
0x0801FFFF
0x0802FFFF
0x0803FFFF
0xFF0BFFFF
0xFF0DFFFF
0xFF0FFFFF
0xFF1BFFFF
0xFF1DFFFF
0xFF1FFFFF
0xFF3BFFFF
0xFF3FFFFF
0xFF45FFFF
0xFF47FFFF
0xFF4DFFFF
0xFF4FFFFF
0xFFF80FFF
0xFFF82FFF
RAM (PD#1)
RAM (RAM_PD#1)
RAM (RAM_PD#2)
RAM (RAM_PD#3)(2)
MIBSPI5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
DCAN3 RAM
0x08000000
0x08010000
0x08020000
0x08030000
0xFF0A0000
0xFF0C0000
0xFF0E0000
0xFF1A0000
0xFF1C0000
0xFF1E0000
0xFF3A0000
0xFF3E0000
0xFF440000
0xFF460000
0xFF4C0000
0xFF4E0000
0xFFF80000
0xFFF82000
0(1)
0(1)
0(1)
0(1)
12(3)
11(3)
7(3)
10
6
DCAN2 RAM
DCAN1 RAM
5
MIBADC2 RAM
MIBADC1 RAM
N2HET2 RAM
N2HET1 RAM
HTU2 RAM
14
8
15
3
16
4
HTU1 RAM
DMA RAM
1
VIM RAM
2
Ethernet RAM (CPPI Memory
Slave)
0xFC520000
0xFC521FFF
n/a
(1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.
(2) Not available on theRM48L540 device.
(3) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset
via the SPIGCR0 register. This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system
module auto-initialization method. Before the MibSPI RAM can be initialized using the system module auto-initialization method: (I) The
module must be released from its local reset, AND (ii) The application must poll for the "BUF INIT ACTIVE" status flag in the SPIFLG
register to become cleared (zero)
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6.14 External Memory Interface (EMIF)
6.14.1 Features
The EMIF includes many features to enhance the ease and flexibility of connecting to external
asynchronous memories or SDRAM devices. The EMIF features includes support for:
•
•
•
•
•
•
•
3 addressable chip select for asynchronous memories of up to 16MB each
1 addressable chip select space for SDRAMs up to 128MB
8- or 16-bit data bus width
Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
Select strobe mode
Extended Wait mode
Data bus parking
6.14.2 Electrical and Timing Specifications
6.14.2.1 Asynchronous RAM
3
1
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_nDQM[1:0]
4
8
5
9
6
7
29
30
10
EMIF_nOE
13
12
EMIF_DATA[15:0]
EMIF_nWE
Figure 6-13. Asynchronous Memory Read Timing
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Extended Due to EMIF_WAIT
SETUP
STROBE
STROBE HOLD
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
14
11
EMIF_nOE
EMIF_WAIT
2
2
Asserted
Deasserted
Figure 6-14. EMIFnWAIT Read Timing Requirements
15
1
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_nDQM[1:0]
16
18
17
19
21
23
20
24
22
EMIF_nWE
27
26
EMIF_DATA[15:0]
EMIF_nOE
Figure 6-15. Asynchronous Memory Write Timing
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Extended Due to EMIF_WAIT
SETUP
STROBE
STROBE HOLD
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
28
25
EMIF_nWE
EMIF_WAIT
2
2
Asserted
Deasserted
Figure 6-16. EMIFnWAIT Write Timing Requirements
Table 6-27. EMIF Asynchronous Memory Timing Requirements
NO.
MIN
NOM
MAX
UNIT
READS AND WRITES
E
EMIF clock period
10
2E
ns
ns
Pulse duration, EMIFnWAIT
assertion and deassertion
2
tw(EM_WAIT)
READS
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
Setup time, EMIFDATA[15:0]
valid before EMIFnOE high
12
13
30
ns
ns
Hold time, EMIFDATA[15:0] valid
after EMIFnOE high
0.5
Setup Time, EMIFnWAIT
asserted before end of Strobe
Phase(1)
14
tsu(EMOEL-EMWAIT)
4E+30
ns
WRITES
Setup Time, EMIFnWAIT
asserted before end of Strobe
Phase(1)
28
tsu(EMWEL-EMWAIT)
4E+30
ns
(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure 6-14 and Figure 6-16 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Table 6-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)
NO.
PARAMETER
MIN
READS AND WRITES
(TA)*E-4
NOM
MAX UNIT
1
3
td(TURNAROUND)
Turn around time
(TA)*E
(TA)*E+3
ns
ns
READS
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
(RS+RST+RH)*E-3
(RS+RST+RH)*E
(RS+RST+RH)*E+3
tc(EMRCYCLE)
(RS+RST+RH+(EWC*16))*
E-3
(RS+RST+RH+(EWC*16))*
E
(RS+RST+RH+(EWC*16))*
E+3
Output setup time, EMIFnCS[4:2]
low to EMIFnOE low (SS = 0)
(RS)*E-4
-3
(RS)*E
0
(RS)*E+3
+3
4
5
tsu(EMCEL-EMOEL)
ns
ns
Output setup time, EMIFnCS[4:2]
low to EMIFnOE low (SS = 1)
Output hold time, EMIFnOE high
to EMIFnCS[4:2] high (SS = 0)
(RH)*E-4
-3
(RH)*E
0
(RH)*E+3
+3
th(EMOEH-EMCEH)
Output hold time, EMIFnOE high
to EMIFnCS[4:2] high (SS = 1)
Output setup time, EMIFBA[1:0]
valid to EMIFnOE low
6
7
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
(RS)*E-4
(RH)*E-4
(RS)*E
(RH)*E
(RS)*E+3
(RH)*E+3
ns
ns
Output hold time, EMIFnOE high
to EMIFBA[1:0] invalid
Output setup time,
EMIFADDR[21:0] valid to
EMIFnOE low
8
9
tsu(EMAV-EMOEL)
(RS)*E-4
(RS)*E
(RS)*E+3
ns
ns
Output hold time, EMIFnOE high
to EMIFADDR[21:0] invalid
th(EMOEH-EMAIV)
(RH)*E-4
(RST)*E-3
(RH)*E
(RST)*E
(RH)*E+3
(RST)*E+3
EMIFnOE active low width
(EW = 0)
10 tw(EMOEL)
ns
EMIFnOE active low width
(EW = 1)
(RST+(EWC*16))*E-3
3E-3
(RST+(EWC*16))*E
4E
(RST+(EWC*16))*E+3
4E+30
Delay time from EMIFnWAIT
deasserted to EMIFnOE high
11 td(EMWAITH-EMOEH)
ns
ns
ns
Output setup time,
29 tsu(EMDQMV-EMOEL) EMIFnDQM[1:0] valid to
EMIFnOE low
(RS)*E-4
(RH)*E-4
(RS)*E
(RH)*E
(RS)*E+3
(RH)*E+3
Output hold time, EMIFnOE high
to EMIFnDQM[1:0] invalid
30 th(EMOEH-EMDQMIV)
WRITES
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)* E-3
(WS+WST+WH)*E
(WS+WST+WH)* E+3
15 tc(EMWCYCLE)
ns
ns
(WS+WST+WH+(EWC*16))* (WS+WST+WH+(EWC*16))* (WS+WST+WH+(EWC*16))*
E-3
E
E+3
Output setup time, EMIFnCS[4:2]
low to EMIFnWE low (SS = 0)
(WS)*E -4
(WS)*E
(WS)*E + 3
16 tsu(EMCEL-EMWEL)
Output setup time, EMIFnCS[4:2]
low to EMIFnWE low (SS = 1)
-4
(WH)*E-4
-4
0
(WH)*E
0
+3
(WH)*E+3
+3
Output hold time, EMIFnWE high
to EMIFnCS[4:2] high (SS = 0)
17 th(EMWEH-EMCEH)
ns
Output hold time, EMIFnWE high
to EMIFCS[4:2] high (SS = 1)
Output setup time, EMIFBA[1:0]
valid to EMIFnWE low
18 tsu(EMDQMV-EMWEL)
19 th(EMWEH-EMDQMIV)
20 tsu(EMBAV-EMWEL)
21 th(EMWEH-EMBAIV)
(WS)*E-4
(WH)*E-4
(WS)*E-4
(WH)*E-4
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
ns
ns
ns
ns
Output hold time, EMIFnWE high
to EMIFBA[1:0] invalid
Output setup time, EMIFBA[1:0]
valid to EMIFnWE low
Output hold time, EMIFnWE high
to EMIFBA[1:0] invalid
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1],
WH[8–1], and MEWC[1–256]. See the RM48x Technical Reference Manual (SPNU503) for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note
that the maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See
the RM48x Technical Reference Manual (SPNU503) for more information.
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MAX UNIT
Table 6-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)
NO.
PARAMETER
MIN
NOM
Output setup time,
EMIFADDR[21:0] valid to
EMIFnWE low
22 tsu(EMAV-EMWEL)
(WS)*E-4
(WS)*E
(WS)*E+3
ns
ns
Output hold time, EMIFnWE high
to EMIFADDR[21:0] invalid
23 th(EMWEH-EMAIV)
(WH)*E-4
(WST)*E-3
(WH)*E
(WST)*E
(WH)*E+3
(WST)*E+3
EMIFnWE active low width (EW
= 0)
24 tw(EMWEL)
ns
EMIFnWE active low width (EW
= 1)
(WST+(EWC*16))*E-3
3E-4
(WST+(EWC*16))*E
4E
(WST+(EWC*16))* E+3
4E+30
Delay time from EMIFnWAIT
deasserted to EMIFnWE high
25 td(EMWAITH-EMWEH)
26 tsu(EMDV-EMWEL)
27 th(EMWEH-EMDIV)
ns
ns
ns
ns
ns
Output setup time,
EMIFDATA[15:0] valid to
EMIFnWE low
(WS)*E-4
(WH)*E-4
(WH)*E-4
(WH)*E-4
(WS)*E
(WH)*E
(WH)*E
(WH)*E
(WS)*E+3
(WH)*E+3
(WH)*E+3
(WH)*E+3
Output hold time, EMIFnWE high
to EMIFDATA[15:0] invalid
Output setup time,
31 tsu(EMDQMV-EMWEL) EMIFnDQM[1:0] valid to
EMIFnWE low
Output hold time, EMIFnWE high
to EMIFnDQM[1:0] invalid
32 th(EMWEH-EMDQMIV)
6.14.2.2 Synchronous Timing
BASIC SDRAM
1
READ OPERATION
2
2
EMIF_CLK
4
3
5
7
7
EMIF_nCS[0]
6
EMIF_nDQM[1:0]
EMIF_BA[1:0]
8
8
EMIF_ADDR[21:0]
19
2 EM_CLK Delay
18
17
20
EMIF_DATA[15:0]
EMIF_nRAS
11
12
13
14
EMIF_nCAS
EMIF_nWE
Figure 6-17. Basic SDRAM Read Operation
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMIF_CLK
3
5
7
7
9
4
EMIF_CS[0]
EMIF_DQM[1:0]
EMIF_BA[1:0]
6
8
8
EMIF_ADDR[21:0]
10
EMIF_DATA[15:0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
11
12
13
15
16
Figure 6-18. Basic SDRAM Write Operation
Table 6-29. EMIF Synchronous Memory Timing Requirements
NO.
MIN
MAX
UNIT
Input setup time, read data valid on
EMIFDATA[15:0] before EMIF_CLK rising
19
20
tsu(EMIFDV-EM_CLKH)
2
ns
Input hold time, read data valid on
1.5
th(CLKH-DIV)
ns
EMIFDATA[15:0] after EMIF_CLK rising
Table 6-30. EMIF Synchronous Memory Switching Characteristics
NO.
1
PARAMETER
MIN
20
5
MAX
13
UNIT
ns
tc(CLK)
Cycle time, EMIF clock EMIF_CLK
Pulse width, EMIF clock EMIF_CLK high or low
Delay time, EMIF_CLK rising to EMIFnCS[0] valid
2
tw(CLK)
ns
3
td(CLKH-CSV)
ns
Output hold time, EMIF_CLK rising to EMIFnCS[0]
invalid
4
5
6
7
8
9
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
1
1
1
ns
ns
ns
ns
ns
ns
Delay time, EMIF_CLK rising to EMIFnDQM[1:0]
valid
13
Output hold time, EMIF_CLK rising to
EMIFnDQM[1:0] invalid
Delay time, EMIF_CLK rising to EMIFADDR[21:0]
and EMIFBA[1:0] valid
13
13
Output hold time, EMIF_CLK rising to
EMIFADDR[21:0] and EMIFBA[1:0] invalid
toh(CLKH-AIV)
td(CLKH-DV)
Delay time, EMIF_CLK rising to EMIFDATA[15:0]
valid
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Table 6-30. EMIF Synchronous Memory Switching Characteristics (continued)
NO.
10
11
12
13
14
15
16
PARAMETER
MIN
MAX
UNIT
ns
Output hold time, EMIF_CLK rising to
EMIFDATA[15:0] invalid
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
1
Delay time, EMIF_CLK rising to EMIFnRAS valid
13
ns
Output hold time, EMIF_CLK rising to EMIFnRAS
invalid
1
1
1
ns
Delay time, EMIF_CLK rising to EMIFnCAS valid
13
ns
Output hold time, EMIF_CLK rising to EMIFnCAS
invalid
ns
Delay time, EMIF_CLK rising to EMIFnWE valid
13
ns
Output hold time, EMIF_CLK rising to EMIFnWE
invalid
ns
Delay time, EMIF_CLK rising to EMIFDATA[15:0]
tri-stated
17
18
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
7
ns
ns
Output hold time, EMIF_CLK rising to
EMIFDATA[15:0] driving
1
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6.15 Vectored Interrupt Manager
The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the
many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow
of program execution. Normally, these events require a timely response from the central processing unit
(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to
an interrupt service routine (ISR).
6.15.1 VIM Features
The VIM module has the following features:
•
Supports 96 interrupt channels.
Provides programmable priority and enable for interrupt request lines.
–
•
•
Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
Provides two software dispatch mechanisms when the CPU VIC port is not used.
–
–
Index interrupt
Register vectored interrupt
•
Parity protected vector interrupt table
6.15.2 Interrupt Request Assignments
Table 6-31. Interrupt Request Assignments
DEFAULT VIM
INTERRUPT CHANNEL
MODULES
INTERRUPT SOURCES
ESM
Reserved
RTI
ESM High level interrupt (NMI)
Reserved
0
1
RTI compare interrupt 0
RTI compare interrupt 1
RTI compare interrupt 2
RTI compare interrupt 3
RTI overflow interrupt 0
RTI overflow interrupt 1
RTI time base interrupt
GPIO interrupt A
2
RTI
3
RTI
4
RTI
5
RTI
6
RTI
7
RTI
8
GPIO
9
N2HET1
HTU1
MIBSPI1
LIN
N2HET1 level 0 interrupt
HTU1 level 0 interrupt
MIBSPI1 level 0 interrupt
LIN level 0 interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MIBADC1
MIBADC1
DCAN1
SPI2
MIBADC1 event group interrupt
MIBADC1 sw group 1 interrupt
DCAN1 level 0 interrupt
SPI2 level 0 interrupt
Reserved
Reserved
CRC
CRC Interrupt
ESM
ESM Low level interrupt
Software interrupt (SSI)
PMU Interrupt
SYSTEM
CPU
GPIO
GPIO interrupt B
N2HET1
HTU1
N2HET1 level 1 interrupt
HTU1 level 1 interrupt
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Table 6-31. Interrupt Request Assignments (continued)
DEFAULT VIM
INTERRUPT CHANNEL
MODULES
INTERRUPT SOURCES
MIBSPI1
LIN
MIBSPI1 level 1 interrupt
LIN level 1 interrupt
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67-72
73
74
75
76
77
MIBADC1
DCAN1
SPI2
MIBADC1 sw group 2 interrupt
DCAN1 level 1 interrupt
SPI2 level 1 interrupt
MIBADC1 magnitude compare interrupt
Reserved
MIBADC1
Reserved
DMA
FTCA interrupt
DMA
LFSA interrupt
DCAN2
DMM
DCAN2 level 0 interrupt
DMM level 0 interrupt
MIBSPI3 level 0 interrupt
MIBSPI3 level 1 interrupt
HBCA interrupt
MIBSPI3
MIBSPI3
DMA
DMA
BTCA interrupt
EMIF
AEMIFINT3
DCAN2
DMM
DCAN2 level 1 interrupt
DMM level 1 interrupt
DCAN1 IF3 interrupt
DCAN3 level 0 interrupt
DCAN2 IF3 interrupt
"OR" of the six Cortex R4F FPU Exceptions
Reserved
DCAN1
DCAN3
DCAN2
FPU
Reserved
SPI4
SPI4 level 0 interrupt
MibADC2 event group interrupt
MibADC2 sw group1 interrupt
Reserved
MIBADC2
MIBADC2
Reserved
MIBSPI5
SPI4
MIBSPI5 level 0 interrupt
SPI4 level 1 interrupt
DCAN3 level 1 interrupt
MIBSPI5 level 1 interrupt
MibADC2 sw group2 interrupt
Reserved
DCAN3
MIBSPI5
MIBADC2
Reserved
MIBADC2
DCAN3
FMC
MibADC2 magnitude compare interrupt
DCAN3 IF3 interrupt
FSM_DONE interrupt
Reserved
Reserved
N2HET2
SCI
N2HET2 level 0 interrupt
SCI level 0 interrupt
HTU2 level 0 interrupt
I2C level 0 interrupt
HTU2
I2C
Reserved
N2HET2
SCI
Reserved
N2HET2 level 1 interrupt
SCI level 1 interrupt
HTU2 level 1 interrupt
C0_MISC_PULSE
HTU2
Ethernet
Ethernet
C0_TX_PULSE
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Table 6-31. Interrupt Request Assignments (continued)
DEFAULT VIM
INTERRUPT CHANNEL
MODULES
INTERRUPT SOURCES
Ethernet
Ethernet
HWAG1
HWAG2
DCC1
C0_THRESH_PULSE
C0_RX_PULSE
HWA_INT_REQ_H
HWA_INT_REQ_H
DCC1 done interrupt
DCC2 done interrupt
Reserved
78
79
80
81
82
DCC2
83
Reserved
PBIST
84
PBIST_DONE
85
Reserved
Reserved
HWAG1
HWAG2
Reserved
Reserved
86
Reserved
87
HWA_INT_REQ_L
HWA_INT_REQ_L
Reserved
88
89
90-95
NOTE
Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR
entry; therefore only request channels 0 to 94 can be used and are offset by 1 address in the
VIM RAM.
NOTE
The lower-order interrupt channels are higher priority channels than the higher-order interrupt
channels.
NOTE
The application can change the mapping of interrupt sources to the interrupt channels via the
interrupt channel control registers (CHANCTRLx) inside the VIM module.
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6.16 DMA Controller
The DMA controller is used to transfer data between two locations in the memory map in the background
of CPU operations. Typically, the DMA is used to:
•
•
•
Transfer blocks of data between external and internal data memories
Restructure portions of internal data memory
Continually service a peripheral
6.16.1 DMA Features
•
•
•
•
•
•
•
•
•
•
•
•
•
CPU independent data transfer
One master port - PortB (64 bits wide) that interfaces to the RM4x Memory System.
FIFO buffer (4 entries deep and each 64 bits wide)
Channel control information is stored in RAM protected by parity
16 channels with individual enable
Channel chaining capability
32 peripheral DMA requests
Hardware and Software DMA requests
8-, 16-, 32-, or 64-bit transactions supported
Multiple addressing modes for source/destination (fixed, increment, offset)
Auto-initiation
Power-management mode
Memory Protection with four configurable memory regions
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6.16.2 Default DMA Request Map
The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The
module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By
default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.
Some DMA requests have multiple sources, as shown in Table 6-32. The application must ensure that
only one of these DMA request sources is enabled at any time.
Table 6-32. DMA Request Line Connection
Modules
MIBSPI1
DMA Request Sources
MIBSPI1[1](1)
DMA Request
DMAREQ[0]
DMAREQ[1]
DMAREQ[2]
DMAREQ[3]
DMAREQ[4]
DMAREQ[5]
DMAREQ[6]
DMAREQ[7]
DMAREQ[8]
DMAREQ[9]
DMAREQ[10]
DMAREQ[11]
DMAREQ[12]
DMAREQ[13]
DMAREQ[14]
DMAREQ[15]
DMAREQ[16]
DMAREQ[17]
DMAREQ[18]
DMAREQ[19]
DMAREQ[20]
MIBSPI1
MIBSPI1[0](2)
SPI2
SPI2 receive
SPI2
SPI2 transmit
MIBSPI1 / MIBSPI3 / DCAN2
MIBSPI1 / MIBSPI3 / DCAN2
DCAN1 / MIBSPI5
MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3
MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2
DCAN1 IF2 / MIBSPI5[2]
MIBADC1 / MIBSPI5
MIBSPI1 / MIBSPI3 / DCAN1
MIBSPI1 / MIBSPI3 / DCAN2
MIBADC1 / I2C / MIBSPI5
MIBADC1 / I2C / MIBSPI5
RTI / MIBSPI1 / MIBSPI3
RTI / MIBSPI1 / MIBSPI3
MIBSPI3 / MibADC2 / MIBSPI5
MIBSPI3 / MIBSPI5
MIBADC1 event / MIBSPI5[3]
MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1
MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1
MIBADC1 G1 / I2C receive / MIBSPI5[4]
MIBADC1 G2 / I2C transmit / MIBSPI5[5]
RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6]
RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7]
MIBSPI3[1](1) / MibADC2 event / MIBSPI5[6]
MIBSPI3[0](2) / MIBSPI5[7]
MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2
MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2
RTI / MIBSPI5
MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1
MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2
RTI DMAREQ2 / MIBSPI5[8]
RTI / MIBSPI5
RTI DMAREQ3 / MIBSPI5[9]
N2HET1 / N2HET2 / DCAN3
N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3
IF2
N2HET1 / N2HET2 / DCAN3
N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3
IF3
DMAREQ[21]
MIBSPI1 / MIBSPI3 / MIBSPI5
MIBSPI1 / MIBSPI3 / MIBSPI5
MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10]
MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11]
DMAREQ[22]
DMAREQ[23]
DMAREQ[24]
N2HET1 / N2HET2 / SPI4 / MIBSPI5
N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4
receive / MIBSPI5[12]
N2HET1 / N2HET2 / SPI4 / MIBSPI5
N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4
transmit / MIBSPI5[13]
DMAREQ[25]
CRC / MIBSPI1 / MIBSPI3
CRC / MIBSPI1 / MIBSPI3
LIN / MIBSPI5
CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12]
CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13]
LIN receive / MIBSPI5[14]
DMAREQ[26]
DMAREQ[27]
DMAREQ[28]
DMAREQ[29]
DMAREQ[30]
LIN / MIBSPI5
LIN transmit / MIBSPI5[15]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5
MIBSPI1[14] / MIBSPI3[14] / SCI receive /
MIBSPI5[1](1)
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5
MIBSPI1[15] / MIBSPI3[15] / SCI transmit /
MIBSPI5[0](2)
DMAREQ[31]
(1) SPI1, SPI3, SPI5 receive in standard SPI mode
(2) SPI1, SPI3, SPI5 transmit in standard SPI mode
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6.17 Real Time Interrupt Module
The real-time interrupt (RTI) module provides timer functionality for operating systems and for
benchmarking code. The RTI module can incorporate several counters that define the time bases needed
for scheduling an operating system.
The timers also allow you to benchmark certain areas of code by reading the values of the counters at the
beginning and the end of the desired code range and calculating the difference between the values.
6.17.1 Features
The RTI module has the following features:
•
•
Two independent 64 bit counter blocks
Four configurable compares for generating operating system ticks or DMA requests. Each event can
be driven by either counter block 0 or counter block 1.
•
•
Fast enabling/disabling of events
Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block
6.17.2 Block Diagrams
Figure 6-19 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI
module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only
available as time base inputs for the counter block 0.
31
0
Compare
up counter
RTICPUCx
OVLINTx
31
0
=
Up counter
RTIUCx
31
0
RTICLK
To Compare
Unit
Free running counter
RTIFRCx
NTU0
NTU1
NTU2
NTU3
31
0
31
0
Capture
up counter
RTICAUCx
Capture
free running counter
RTICAFRCx
CAP event source 0
CAP event source 1
External
control
Figure 6-19. Counter Block Diagram
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Update
compare
0
RTIUDCPy
+
31
0
DMAREQy
INTy
Compare
RTICOMPy
From counter
block 0
=
From counter
block 1
Compare
control
Figure 6-20. Compare Block Diagram
6.17.3 Clock Source Options
The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.
The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the
System module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.
For more information on clock sources refer to Table 6-8 and Table 6-13.
6.17.4 Network Time Synchronization Inputs
The RTI module supports four NTU inputs that signal internal system events, and which can be used to
synchronize the time base used by the RTI module. On this device, these NTU inputs are connected as
shown in Table 6-33.
Table 6-33. Network Time Synchronization Inputs
NTU Input
Source
Reserved
0
1
2
3
Reserved
PLL2 Clock output
EXTCLKIN1 clock input
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6.18 Error Signaling Module
The Error Signaling Module (ESM) manages the various error conditions on the RM4x microcontroller. The
error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be
configured to drive a low level on a dedicated device terminal called nERROR. This can be used as an
indicator to an external monitor circuit to put the system into a safe state.
6.18.1 Features
The features of the ESM are:
•
128 interrupt/error channels are supported, divided into 3 different groups
–
–
–
64 channels with maskable interrupt and configurable error pin behavior
32 error channels with nonmaskable interrupt and predefined error pin behavior
32 channels with predefined error pin behavior only
•
•
•
Error pin to signal severe device failure
Configurable time base for error signal
Error forcing capability
6.18.2 ESM Channel Assignments
The ESM integrates all the device error conditions and groups them in the order of severity. Group1 is
used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device
response to each error is determined by the severity group it is connected to. Table 6-35 shows the
channel assignment for each group.
Table 6-34. ESM Groups
ERROR GROUP
Group1
INTERRUPT CHARACTERISTICS
Maskable, low or high priority
Nonmaskable, high priority
No interrupt generated
INFLUENCE ON ERROR PIN
Configurable
Fixed
Group2
Group3
Fixed
Table 6-35. ESM Channel Assignments
ERROR SOURCES
GROUP
Group1
Group1
Group1
Group1
Group1
Group1
CHANNELS
Reserved
MibADC2 - parity
DMA - MPU
0
1
2
3
4
5
DMA - parity
Reserved
DMA/DMM - imprecise read error
FMC - correctable error: bus1 and bus2 interfaces
(does not include accesses to EEPROM bank)
Group1
6
N2HET1/N2HET2 - parity
HTU1/HTU2 - parity
HTU1/HTU2 - MPU
PLL - Slip
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
7
8
9
10
11
12
13
14
15
16
17
Clock Monitor - interrupt
Reserved
DMA/DMM - imprecise write error
Reserved
VIM RAM - parity
Reserved
MibSPI1 - parity
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Table 6-35. ESM Channel Assignments (continued)
ERROR SOURCES
MibSPI3 - parity
GROUP
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
CHANNELS
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
MibADC1 - parity
Reserved
DCAN1 - parity
DCAN3 - parity
DCAN2 - parity
MibSPI5 - parity
Reserved
RAM even bank (B0TCM) - correctable error
CPU - self-test
RAM odd bank (B1TCM) - correctable error
Reserved
DCC1 - error
CCM-R4 - self-test
Reserved
Reserved
Reserved
FMC - correctable error (EEPROM bank access)
FMC - uncorrectable error (EEPROM bank access)
IOMM - Mux configuration error
Power domain controller compare error
Power domain controller self-test error
eFuse Controller Error – this error signal is generated when any bit in the eFuse
controller error status register is set. The application can choose to generate an
interrupt whenever this bit is set to service any eFuse controller error conditions.
Group1
Group1
40
41
eFuse Controller - Self Test Error. This error signal is generated only when a self
test on the eFuse controller generates an error condition. When an ECC self test
error is detected, group 1 channel 40 error signal will also be set.
PLL2 - Slip
Ethernet Controller master interface
Reserved
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Table 6-35. ESM Channel Assignments (continued)
ERROR SOURCES
GROUP
Group1
Group1
CHANNELS
DCC2 - error
Reserved
62
63
GROUP 2
Reserved
Reserved
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
0
1
CCMR4 - compare
Reserved
2
3
FMC - uncorrectable error (address parity on bus1 accesses)
4
Reserved
5
RAM even bank (B0TCM) - uncorrectable error
6
Reserved
7
RAM odd bank (B1TCM) - uncorrectable error
8
Reserved
9
RAM even bank (B0TCM) - address bus parity error
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
RAM odd bank (B1TCM) - address bus parity error
Reserved
Reserved
Reserved
TCM - ECC live lock detect
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RTI_WWD_NMI
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GROUP 3
Reserved
eFuse Controller - autoload error
Reserved
Group3
Group3
Group3
Group3
Group3
Group3
Group3
0
1
2
3
4
5
6
RAM even bank (B0TCM) - ECC uncorrectable error
Reserved
RAM odd bank (B1TCM) - ECC uncorrectable error
Reserved
FMC - uncorrectable error: bus1 and bus2 interfaces
(does not include address parity error and errors on accesses to EEPROM bank)
Group3
7
Reserved
Reserved
Reserved
Group3
Group3
Group3
8
9
10
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Table 6-35. ESM Channel Assignments (continued)
ERROR SOURCES
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GROUP
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
CHANNELS
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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6.19 Reset / Abort / Error Sources
Table 6-36. Reset/Abort/Error Sources
ESM HOOKUP
group.channel
ERROR SOURCE
SYSTEM MODE
ERROR RESPONSE
CPU TRANSACTIONS
User/Privilege
Precise write error (NCNB/Strongly Ordered)
Precise read error (NCB/Device or Normal)
Imprecise write error (NCB/Device or Normal)
Precise Abort (CPU)
Precise Abort (CPU)
Imprecise Abort (CPU)
n/a
n/a
n/a
User/Privilege
User/Privilege
Undefined Instruction Trap
(CPU)(1)
Illegal instruction
User/Privilege
n/a
n/a
MPU access violation
User/Privilege
SRAM
Abort (CPU)
B0 TCM (even) ECC single error (correctable)
User/Privilege
ESM
1.26
3.3
Abort (CPU), ESM =>
nERROR
B0 TCM (even) ECC double error (noncorrectable)
User/Privilege
B0 TCM (even) uncorrectable error (for example, redundant
address decode)
User/Privilege
ESM => NMI => nERROR
2.6
B0 TCM (even) address bus parity error
User/Privilege
User/Privilege
ESM => NMI => nERROR
ESM
2.10
1.28
B1 TCM (odd) ECC single error (correctable)
Abort (CPU), ESM =>
nERROR
B1 TCM (odd) ECC double error (noncorrectable)
User/Privilege
3.5
B1 TCM (odd) uncorrectable error (for example, redundant
address decode)
User/Privilege
User/Privilege
ESM => NMI => nERROR
ESM => NMI => nERROR
2.8
B1 TCM (odd) address bus parity error
2.12
FLASH
FMC correctable error - Bus1 and Bus2 interfaces
User/Privilege
ESM
1.6
3.7
FMC uncorrectable error - Bus1 accesses
(does not include address parity error)
Abort (CPU), ESM =>
nERROR
User/Privilege
FMC uncorrectable error - Bus2 accesses
(does not include address parity error and EEPROM bank
accesses)
User/Privilege
User/Privilege
ESM => nERROR
3.7
FMC uncorrectable error - address parity error on Bus1
accesses
ESM => NMI => nERROR
2.4
FMC correctable error - Accesses to EEPROM bank
FMC uncorrectable error - Accesses to EEPROM bank
User/Privilege
User/Privilege
ESM
ESM
1.35
1.36
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
response)
User/Privilege
ESM
ESM
1.5
External imprecise error on write (Illegal transaction with ok
response)
User/Privilege
1.13
Memory access permission violation
Memory parity error
User/Privilege
User/Privilege
ESM
ESM
1.2
1.3
DMM TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
response)
User/Privilege
ESM
ESM
1.5
External imprecise error on write (Illegal transaction with ok
response)
User/Privilege
1.13
HTU1
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
User/Privilege
User/Privilege
User/Privilege
Interrupt => VIM
Interrupt => VIM
ESM
n/a
n/a
1.9
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage
of the CPU.
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Table 6-36. Reset/Abort/Error Sources (continued)
ESM HOOKUP
group.channel
ERROR SOURCE
SYSTEM MODE
ERROR RESPONSE
Memory parity error
User/Privilege
HTU2
ESM
1.8
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
User/Privilege
User/Privilege
User/Privilege
User/Privilege
N2HET1
Interrupt => VIM
Interrupt => VIM
ESM
n/a
n/a
1.9
1.8
Memory parity error
ESM
Memory parity error
Memory parity error
User/Privilege
N2HET2
ESM
ESM
ESM
1.7
1.7
User/Privilege
ETHERNET MASTER INTERFACE
User/Privilege
MIBSPI
Any error reported by slave being accessed
1.43
MibSPI1 memory parity error
MibSPI3 memory parity error
MibSPI5 memory parity error
User/Privilege
User/Privilege
User/Privilege
MIBADC
ESM
ESM
ESM
1.17
1.18
1.24
MibADC1 Memory parity error
MibADC2 Memory parity error
User/Privilege
User/Privilege
DCAN
ESM
ESM
1.19
1.1
DCAN1 memory parity error
DCAN2 memory parity error
DCAN3 memory parity error
User/Privilege
User/Privilege
User/Privilege
PLL
ESM
ESM
ESM
1.21
1.23
1.22
PLL slip error
User/Privilege
User/Privilege
CLOCK MONITOR
User/Privilege
DCC
ESM
ESM
1.10
1.42
PLL #2 slip error
Clock monitor interrupt
ESM
1.11
DCC1 error
DCC2 error
User/Privilege
User/Privilege
CCM-R4
ESM
ESM
1.30
1.62
Self-test failure
Compare failure
User/Privilege
User/Privilege
VIM
ESM
1.31
2.2
ESM => NMI => nERROR
Memory parity error
User/Privilege
VOLTAGE MONITOR
n/a
ESM
Reset
ESM
1.15
n/a
VMON out of voltage range
CPU self-test (LBIST) error
CPU SELF-TEST (LBIST)
User/Privilege
1.27
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Table 6-36. Reset/Abort/Error Sources (continued)
ESM HOOKUP
group.channel
ERROR SOURCE
SYSTEM MODE
ERROR RESPONSE
PIN MULTIPLEXING CONTROL
User/Privilege
Mux configuration error
ESM
1.37
POWER DOMAIN CONTROL
User/Privilege
PSCON compare error
PSCON self-test error
ESM
ESM
1.38
1.39
User/Privilege
eFuse CONTROLLER
User/Privilege
eFuse Controller Autoload error
ESM => nERROR
3.1
eFuse Controller - Any bit set in the error status register
eFuse Controller self-test error
User/Privilege
User/Privilege
ESM
ESM
1.40
1.41
WINDOWED WATCHDOG
n/a
WWD Nonmaskable Interrupt exception
ESM => NMI => nERROR
2.24
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset
n/a
n/a
n/a
n/a
n/a
n/a
Reset
Reset
Reset
Reset
Reset
Reset
n/a
n/a
n/a
n/a
n/a
n/a
Oscillator fail / PLL slip(2)
Watchdog exception
CPU Reset (driven by the CPU STC)
Software Reset
External Reset
(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.
6.20 Digital Windowed Watchdog
This device includes a digital windowed watchdog (DWWD) module that protects against runaway code
execution.
The DWWD module allows the application to configure the time window within which the DWWD module
expects the application to service the watchdog. A watchdog violation occurs if the application services the
watchdog outside of this window, or fails to service the watchdog at all. The application can choose to
generate a system reset or a nonmaskable interrupt to the CPU in case of a watchdog violation.
The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog
can only be disabled upon a system reset.
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6.21 Debug Subsystem
6.21.1 Block Diagram
The device contains an ICEPICK module to allow JTAG access to the scan chains (see Figure 6-21).
Boundary Scan
Boundary Scan I/F
BSR/BSDL
Debug
ROM1
TRST
TMS
TCK
RTCK
TDI
TDO
Debug APB
DAP
Secondary Tap 0
APB Mux
AHB-AP
APB slave
Cortex
R4F
POM
ETM
TPIU
from
to SCR1 via A2A
PCR1/Bridge
RTP
DMM
TAP 0
Secondary Tap 1
TAP 1
Secondary Tap 2
AJSM
Figure 6-21. Debug Subsystem Block Diagram
NOTE
The ETM, RTP and DMM exist in silicon, but are not supported in the PGE package.
6.21.2 Debug Components Memory Map
Table 6-37. Debug Components Memory Map
FRAME ADDRESS RANGE
RESPONSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUAL
MODULE NAME
SIZE
4KB
4KB
SIZE
4KB
4KB
START
END
CoreSight Debug
ROM
CSCS0
CSCS1
0xFFA00000
0xFFA00FFF
Reads: 0, writes: no effect
Reads: 0, writes: no effect
Cortex-R4F
Debug
0xFFA01000
0xFFA01FFF
ETM-R4
CSCS2
CSCS3
0xFFA02000
0xFFA03000
0xFFA02FFF
0xFFA03FFF
4KB
4KB
4KB
4KB
Reads: 0, writes: no effect
Reads: 0, writes: no effect
CoreSight TPIU
6.21.3 JTAG Identification Code
The JTAG ID code for this device is the same as the device ICEPick Identification Code (see Table 6-38).
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Table 6-38. JTAG ID Code
SILICON REVISION
ID
Rev A
Rev B
Rev C
Rev D
0x0B8A002F
0x2B8A002F
0x3B8A002F
0x4B8A002F
6.21.4 Debug ROM
The Debug ROM stores the location of the components on the Debug APB bus (see Table 6-39).
Table 6-39. Debug ROM table
ADDRESS
0x000
DESCRIPTION
pointer to Cortex-R4F
ETM-R4
VALUE
0x00001003
0x00002003
0x00003003
0x00004003
0x00000000
0x001
0x002
TPIU
0x003
POM
0x004
end of table
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6.21.5 JTAG Scan Interface Timings
Table 6-40. JTAG Scan Interface Timing(1)
NO.
PARAMETER
MIN
MAX
UNIT
MHz
MHz
ns
fTCK
TCK frequency (at HCLKmax)
12
fRTCK
RTCK frequency (at TCKmax and HCLKmax)
Delay time, TCK to RTCK
10
1
2
3
4
5
td(TCK -RTCK)
tsu(TDI/TMS - RTCKr)
th(RTCKr -TDI/TMS)
th(RTCKr -TDO)
td(TCKf -TDO)
24
12
Setup time, TDI, TMS before RTCK rise (RTCKr)
Hold time, TDI, TMS after RTCKr
Hold time, TDO after RTCKf
26
0
ns
ns
0
ns
Delay time, TDO valid after RTCK fall (RTCKf)
ns
(1) Timings for TDO are specified for a maximum of 50-pF load on TDO
TCK
RTCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 6-22. JTAG Timing
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6.21.6 Advanced JTAG Security Module
This device includes an Advanced JTAG Security Module (AJSM) which provides maximum security to the
memory content of the device by letting users secure the device after programming.
Flash Module Output
OTP Contents
(example)
. . .
. . .
H
L
H
L
H
L
L
H
Unlock By Scan
Register
H
H
L
L
Internal Tie-Offs
(example only)
L
L
H
H
UNLOCK
128-bit comparator
Internal Tie-Offs
(example only)
H
L
L
H
H
L
L
H
Figure 6-23. AJSM Unlock
The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP
address 0xF0000000. The OTP contents are XOR-ed with the "Unlock By Scan" register contents (see
Figure 6-23). The outputs of these XOR gates are again combined with a set of secret internal tie-offs.
The output of this combinational logic is compared against a secret hard-wired 128-bit value. A match
results in the UNLOCK signal being asserted, so that the device is now unsecure.
A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing
a 0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP)
flash region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure
the device.
Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By
Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents
and the Unlock-By-Scan register contents results in the original visible unlock code.
The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).
A secure device only permits JTAG accesses to the AJSM scan chain via the Secondary Tap # 2 of the
ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in
this state.
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6.21.7 Embedded Trace Macrocell (ETM-R4)
The device contains a ETM-R4 module with a 32-bit internal data port. The ETM-R4 module is connected
to a TPIU with a 32-bit data bus; the TPIU provides a 35-bit (32-bit data, 3-bit control) external interface
for trace. The ETM-R4 is CoreSight compliant and follows the ETM v3 specification; for more details see
ARM CoreSight ETM-R4 TRM specification.
6.21.7.1 ETM TRACECLKIN Selection
The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The
selection is done by the EXTCTLOUT[1:0] control bits of the TPIU; the default is '00' (see Table 6-41). The
address of this register is TPIU base address + 0x404.
Before you begin accessing TPIU registers, TPIU should be unlocked via coresight key and 1 or 2 should
be written to this register.
Table 6-41. TPIU / TRACECLKIN Selection
EXTCTLOUT[1:0]
TPIU/TRACECLKIN
tied-zero
00 [default]
01
10
11
VCLK
ETMTRACECLKIN
tied-zero
6.21.7.2 Timing Specifications
tl(ETM)
th(ETM)
tr(ETM)
tf(ETM)
tcyc(ETM)
Figure 6-24. ETMTRACECLKOUT Timing
Table 6-42. ETMTRACECLK Timing
PARAMETER
Clock period
MIN
t(HCLK) * 4
20
MAX
UNIT
ns
tcyc(ETM)
tl(ETM)
Low pulse width
ns
th(ETM)
tr(ETM)
tf(ETM)
High pulse width
20
ns
Clock and data rise time
Clock and data fall time
3
3
ns
ns
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Figure 6-25. ETMDATA Timing
Table 6-43. ETMDATA Timing
PARAMETER
MIN
MAX
UNIT
Delay time, ETM trace clock high to ETM
data valid
td(ETMTRACECLKH-ETMDATAV)
td(ETMTRACECLKl-ETMDATAV)
1.5
7
ns
Delay time, ETM trace clock low to ETM
data valid
1.5
7
ns
NOTE
The ETMTRACECLK and ETMDATA timing is based on a 15-pF load and for ambient
temperature lower than 85°C.
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6.21.8 RAM Trace Port (RTP)
The RTP provides the ability to datalog the RAM contents of the RM4x devices or accesses to peripherals
without program intrusion. It can trace all data write or read accesses to internal RAM. In addition, it
provides the capability to directly transfer data to a FIFO to support a CPU-controlled transmission of the
data. The trace data is transmitted over a dedicated external interface.
6.21.8.1 Features
The RTP offers the following features:
•
Two modes of operation - Trace Mode and Direct Data Mode
–
Trace Mode
•
•
•
•
•
•
Nonintrusive data trace on write or read operation
Visibility of RAM content at any time on external capture hardware
Trace of peripheral accesses
2 configurable trace regions for each RAM module to limit amount of data to be traced
FIFO to store data and address of data of multiple read/write operations
Trace of CPU and/or DMA accesses with indication of the master in the transmitted data packet
–
Direct Data Mode
•
Directly write data with the CPU or trace read operations to a FIFO, without transmitting header
and address information
•
•
•
•
Dedicated synchronous interface to transmit data to external devices
Free-running clock generation or clock stop mode between transmissions
Up to 100 Mbps/pin transfer rate for transmitting data
Pins not used in functional mode can be used as GIOs
6.21.8.2 Timing Specifications
tl(RTP)
th(RTP)
tf
tr
tcyc(RTP)
Figure 6-26. RTPCLK Timing
Table 6-44. RTPCLK Timing
PARAMETER
MIN
MAX
UNIT
Clock period, prescaled from HCLK; must not be
faster than HCLK / 2
tcyc(RTP)
11 (= 90 MHz)
ns
th(RTP)
tl(RTP)
High pulse width
Low pulse width
((tcyc(RTP))/2) - ((tr+tf)/2)
((tcyc(RTP))/2) - ((tr+tf)/2)
ns
ns
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Figure 6-27. RTPDATA Timing
Table 6-45. RTPDATA Timing
PARAMETER
Delay time, RTPCLK high to RTPSYNC valid
MIN
–5
MAX
UNIT
ns
td(RTPCLKH-RTPSYNCV)
td(RTPCLKH-RTPDATAV)
4
4
Delay time, RTPCLK high to RTPDATA valid
–5
ns
tena(RTP)
tdis(RTP)
1
2
3
4
5
6
7
8
9
10 11
12 13
14
15 16
HCLK
RTPCLK
RTPnENA
RTPSYNC
RTPDATA
d1
d2
d3
d4
Divide by 1
d5
d6
d7
d8
Figure 6-28. RTPnENA Timing
Table 6-46. RTPnENA Timing
PARAMETER
MIN
MAX UNIT
time RTPnENA must go high before what would
be the next RTPSYNC, to ensure delaying the
next packet
tdis(RTP)
3tc(HCLK) + tr(RTPSYNC) + 12
ns
time after RTPnENA goes low before a packet that
has been halted, resumes
tena(RTP)
4tc(HCLK) + tr(RTPSYNC)
5tc(HCLK) + tr(RTPSYNC) + 12
ns
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6.21.9 Data Modification Module (DMM)
The Data Modification Module (DMM) provides the capability to modify data in the entire 4-GB address
space of the RM4x devices from an external peripheral, with minimal interruption of the application.
6.21.9.1 Features
The DMM has the following features:
•
•
Acts as a bus master, thus enabling direct writes to the 4-GB address space without CPU intervention
Writes to memory locations specified in the received packet (leverages packets defined by trace mode
of the RAM trace port (RTP) module
•
Writes received data to consecutive addresses, which are specified by the DMM (leverages packets
defined by direct data mode of RTP module)
•
•
•
Configurable port width (1, 2, 4, 8, 16 pins)
Up to 100 Mbps/pin data rate
Unused pins configurable as GPIO pins
6.21.9.2 Timing Specifications
tl(DMM)
th(DMM)
tf
tr
tcyc(DMM)
Figure 6-29. DMMCLK Timing
Table 6-47. Timing Requirements for DMMCLK
MIN
MAX UNIT
tcyc(DMM)
th(DMM)
tl(DMM)
Cycle time, DMMCLK period
tc(HCLK) * 2
((tcyc(DMM))/2) - ((tr+tf)/2)
((tcyc(DMM))/2) - ((tr+tf)/2)
ns
ns
ns
Pulse duration, DMMCLK high
Pulse duration, DMMCLK low
tssu(DMM)
tsh(DMM)
DMMSYNC
DMMCLK
DMMDATA
tdsu(DMM)
tdh(DMM)
Figure 6-30. DMMDATA Timing
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Table 6-48. Timing Requirements for DMMDATA
MIN
2
MAX
UNIT
ns
tssu(DMM)
tsh(DMM)
tdsu(DMM)
tdh(DMM)
SYNC active to clk falling edge setup time
clk falling edge to SYNC inactive hold time
DATA to clk falling edge setup time
clk falling edge to DATA hold time
3
ns
2
ns
3
ns
HCLK
DMMCLK
DMMSYNC
D00
D01
D10
D11
D20
D21
D30
D31
D40
D41
D50
DMMDATA
DMMnENA
Figure 6-31. DMMnENA Timing
Figure 6-31 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data
width = 8, port width = 4) where none of the packets received by the DMM are sent out, leading to filling
up of the internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been
received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets D4x,
D5x, D6x, D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to
stop receiving packets after 4 HCLK cycles; once DMMnENA is deasserted, the DMM can handle packets
immediately (after 0 HCLK cycles).
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6.21.10 Boundary Scan Chain
The device supports IEEE1149.1-compliant boundary scan for testing pin-to-pin compatibility. The
boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module (see Figure 6-
32).
Device Pins (conceptual)
TRST
TMS
TCK
TDI
Boundary
Scan
Boundary Scan Interface
TDO
RTCK
TDI
TDO
BSDL
Figure 6-32. Boundary Scan Implementation (Conceptual Diagram)
Data is serially shifted into all boundary-scan buffers through TDI and out through TDO.
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7 Peripheral Information and Electrical Specifications
7.1 Peripheral Legend
Table 7-1. Peripheral Legend
ABBREVIATION
FULL NAME
MibADC
Analog-to-Digital Converter
CCM-R4F
CRC
CPU Compare Module - Cortex-R4F
Cyclic Redundancy Checker
Controller Area Network
DCAN
DCC
Dual Clock Comparator
DMA
DMM
EMIF
ESM
Direct Memory Access
Data Modification Module
External Memory Interface
Error Signaling Module
ETM-R4F
GPIO
HTU
Embedded Trace Macrocell - Cortex-R4F
General-Purpose Input/Output
High-End Timer Transfer Unit
Inter-Integrated Circuit
I2C
LIN
Local Interconnect Network
Multibuffered Serial Peripheral Interface
Platform Next Generation High-End Timer
Parameter Overlay Module
Real-Time Interrupt Module
RAM Trace Port
MibSPI
N2HET
POM
RTI
RTP
SPI
Serial Peripheral Interface
Vectored Interrupt Manager
VIM
7.2 Multibuffered 12-Bit Analog-to-Digital Converter
The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could
be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given
with respect to ADREFLO unless otherwise noted.
Table 7-2. MibADC Overview
DESCRIPTION
Resolution
VALUE
12 bits
Assured
Monotonic
Output conversion code
00h to FFFh [00 for VAI ≤ ADREFLO; FFF for VAI ≥ ADREFHI]
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7.2.1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
10-/12-bit resolution
ADREFHI and ADREFLO pins (high and low reference voltages)
Total Sample/Hold/Convert time: 600 ns Typical Minimum at 30 MHz ADCLK
One memory region per conversion group is available (event, group 1, group 2)
Allocation of channels to conversion groups is completely programmable
Memory regions are serviced either by interrupt or by DMA
Programmable interrupt threshold counter is available for each group
Programmable magnitude threshold interrupt for each group for any one channel
Option to read either 8-, 10-, or 12-bit values from memory regions
Single or continuous conversion modes
Embedded self-test
Embedded calibration logic
Enhanced power-down mode
–
Optional feature to automatically power down ADC core when no conversion is in progress
•
External event pin (ADEVT) programmable as general-purpose I/O
7.2.2 Event Trigger Options
The ADC module supports three conversion groups: Event Group, Group1, and Group2. Each of these
three groups can be configured to be hardware event-triggered. In that case, the application can select
from among eight event sources to be the trigger for a group's conversions.
7.2.2.1 Default MIBADC1 Event Trigger Hookup
Table 7-3. MIBADC1 Event Trigger Hookup
Event #
Source Select Bits For G1, G2 Or Event
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
Trigger
1
2
3
4
5
6
7
8
000
001
010
011
100
101
110
111
ADEVT
N2HET1[8]
N2HET1[10]
RTI compare 0 interrupt
N2HET1[12]
N2HET1[14]
GIOB[0]
GIOB[1]
NOTE
For ADEVT, N2HET1, and GIOB trigger sources, the connection to the MibADC1 module
trigger input is made from the output side of the input buffer. This way, a trigger condition
can be generated either by configuring the function as output onto the pad (via the mux
control), or by driving the function from an external trigger source as input. If the mux control
module is used to select different functionality instead of the ADEVT, N2HET1[x], or GIOB[x]
signals, then care must be taken to disable these signals from triggering conversions; there
is no multiplexing on the input connections.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
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7.2.2.2 Alternate MIBADC1 Event Trigger Hookup
Table 7-4. Alternate MIBADC1 Event Trigger Hookup
SOURCE SELECT BITS FOR G1, G2 OR EVENT
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
EVENT #
TRIGGER
1
2
3
4
5
6
7
8
000
001
010
011
100
101
110
111
ADEVT
N2HET2[5]
N2HET1[27]
RTI compare 0 interrupt
N2HET1[17]
N2HET1[19]
N2HET1[11]
N2HET2[13]
The selection between the default MIBADC1 event trigger hook-up versus the alternate event trigger hook-
up is done by multiplexing control module register 30 bits 0 and 1.
If 30[0] = 1, then the default MibADC1 event trigger hook-up is used.
If 30[0] = 0 and 30[1] = 1, then the alternate MibADC1 event trigger hook-up is used.
NOTE
For ADEVT trigger source, the connection to the MibADC1 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
configuring ADEVT as an output function on to the pad (via the mux control), or by driving
the ADEVT signal from an external trigger source as input. If the mux control module is used
to select different functionality instead of the ADEVT signal, then care must be taken to
disable ADEVT from triggering conversions; there is no multiplexing on the input connection.
NOTE
For N2HETx trigger sources, the connection to the MibADC1 module trigger input is made
from the input side of the output buffer (at the N2HETx module boundary). This way, a
trigger condition can be generated even if the N2HETx signal is not selected to be output on
the pad.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
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7.2.2.3 Default MIBADC2 Event Trigger Hookup
Table 7-5. MIBADC2 Event Trigger Hookup
SOURCE SELECT BITS FOR G1, G2 OR EVENT
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
EVENT #
TRIGGER
1
2
3
4
5
6
7
8
000
001
010
011
100
101
110
111
AD2EVT
N2HET1[8]
N2HET1[10]
RTI compare 0
N2HET1[12]
N2HET1[14]
GIOB[0]
GIOB[1]
NOTE
For AD2EVT, N2HET1 and GIOB trigger sources, the connection to the MibADC2 module
trigger input is made from the output side of the input buffer. This way, a trigger condition
can be generated either by configuring the function as output onto the pad (via the mux
control), or by driving the function from an external trigger source as input. If the mux control
module is used to select different functionality instead of the AD2EVT, N2HET1[x] or GIOB[x]
signals, then care must be taken to disable these signals from triggering conversions; there
is no multiplexing on the input connections.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
7.2.2.4 Alternate MIBADC2 Event Trigger Hookup
Table 7-6. Alternate MIBADC2 Event Trigger Hookup
SOURCE SELECT BITS FOR G1, G2 OR EVENT
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
EVENT #
TRIGGER
1
2
3
4
5
6
7
8
000
001
010
011
100
101
110
111
AD2EVT
N2HET2[5]
N2HET1[27]
RTI compare 0
N2HET1[17]
N2HET1[19]
N2HET1[11]
N2HET2[13]
The selection between the default MIBADC2 event trigger hook-up versus the alternate event trigger hook-
up is done by multiplexing control module register 30 bits 0 and 1.
If 30[0] = 1, then the default MibADC2 event trigger hook-up is used.
If 30[0] = 0 and 30[1] = 1, then the alternate MibADC2 event trigger hook-up is used.
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NOTE
For AD2EVT trigger source, the connection to the MibADC2 module trigger input is made
from the output side of the input buffer. This way, a trigger condition can be generated either
by configuring AD2EVT as an output function on to the pad (via the mux control), or by
driving the AD2EVT signal from an external trigger source as input. If the mux control module
is used to select different functionality instead of the AD2EVT signal, then care must be
taken to disable AD2EVT from triggering conversions; there is no multiplexing on the input
connections.
NOTE
For N2HETx trigger sources, the connection to the MibADC2 module trigger input is made
from the input side of the output buffer (at the N2HETx module boundary). This way, a
trigger condition can be generated even if the N2HETx signal is not selected to be output on
the pad.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
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7.2.3 ADC Electrical and Timing Specifications
Table 7-7. MibADC Recommended Operating Conditions
PARAMETER
A-to-D high-voltage reference source
A-to-D low-voltage reference source
Analog input voltage
MIN
MAX
UNIT
(1)
ADREFHI
ADREFLO
VAI
ADREFLO
VCCAD
V
V
V
(1)
VSSAD
ADREFHI
ADREFHI
ADREFLO
Analog input clamp current(2)
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
IAIK
–2
2
mA
(1) For VCCAD and VSSAD recommended operating conditions, see Section 5.4.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Table 7-8. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions
PARAMETER
DESCRIPTION/CONDITIONS
MIN
MAX UNIT
Analog input mux on-
resistance
Rmux
See Figure 7-1
See Figure 7-1
250
250
Ω
Ω
ADC sample switch on-
resistance
Rsamp
Cmux
Input mux capacitance
See Figure 7-1
See Figure 7-1
16
13
200
200
500
250
250
1000
2
pF
pF
Csamp
ADC sample capacitance
V
SSAD ≤ VIN < VSSAD + 100 mV
–300
–200
–200
–1000
–250
–250
–8
Analog off-state input leakage VCCAD = 3.6 V
current maximum
IAIL
VSSAD + 100 mV ≤ VIN ≤ VCCAD - 200 mV
VCCAD - 200 mV < VIN ≤ VCCAD
nA
nA
µA
µA
µA
µA
VSSAD ≤ VIN < VSSAD + 300 mV
Analog off-state input leakage VCCAD = 5.5 V
current
IAIL
VSSAD + 300 mV ≤ VIN ≤ VCCAD - 300 mV
VCCAD - 300 mV < VIN ≤ VCCAD
maximum
VSSAD ≤ VIN < VSSAD + 100 mV
ADC1 Analog on-state input
bias current
VCCAD = 3.6 V
maximum
(1)
(1)
(1)
(1)
IAOSB1
IAOSB2
IAOSB1
IAOSB2
VSSAD + 100 mV < VIN < VCCAD - 200 mV
VCCAD - 200 mV < VIN < VCCAD
–4
2
–4
12
2
VSSAD ≤ VIN < VSSAD + 100 mV
–7
ADC2 Analog on-state input
bias current
VCCAD = 3.6 V
maximum
VSSAD + 100 mV ≤ VIN ≤ VCCAD - 200 mV
VCCAD - 200 mV < VIN ≤ VCCAD
–4
2
–4
10
3
VSSAD ≤ VIN < VSSAD + 300 mV
–10
–5
ADC1 Analog on-state input
bias current
VCCAD = 5.5 V
maximum
VSSAD + 300 mV ≤ VIN ≤ VCCAD - 300 mV
VCCAD - 300 mV < VIN ≤ VCCAD
3
–5
14
3
VSSAD ≤ VIN < VSSAD + 300 mV
–8
ADC2 Analog on-state input
bias current
VCCAD = 5.5 V
maximum
VSSAD + 300 mV ≤ VIN ≤ VCCAD - 300 mV
VCCAD - 300 mV < VIN ≤ VCCAD
–5
3
–5
12
3
IADREFHI
ICCAD
ADREFHI input current
Static supply current
ADREFHI = VCCAD, ADREFLO = VSSAD
Normal operating mode
mA
mA
µA
15
5
ADC core in power down mode
(1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to IAOSL1 + IAOSL2
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Rext
Pin
Rmux
Smux
VS1
IAOSB
Cext
On-State
Bias Current
Smux
Rext
Pin
Rmux
VS2
IAIL
Cext
IAIL
IAIL
Off-State
Leakages
Smux
Rext
Pin
Rmux
Ssamp
Rsamp
VS24
IAIL
Csamp
Cmux
Cext
IAIL
IAIL
Figure 7-1. MibADC Input Equivalent Circuit
Table 7-9. MibADC Timing Specifications
PARAMETER
MIN
0.033
0.2
NOM
MAX
UNIT
µs
(1)
tc(ADCLK)
Cycle time, MibADC clock
(2)
td(SH)
Delay time, sample and hold time
Delay time from ADC power on until first input can be sampled
12-BIT MODE
µs
td(PU-ADV)
1
µs
td(c)
Delay time, conversion time
0.4
0.6
µs
µs
(3)
td(SHC)
Delay time, total sample/hold and conversion time
10-BIT MODE
td(c)
Delay time, conversion time
0.33
0.53
µs
µs
(3)
td(SHC)
Delay time, total sample/hold and conversion time
(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits
4:0.
(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each
conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as
well as the internal impedance of the ADC.
(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, for
example, the prescale settings.
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Table 7-10. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions
PARAMETER
DESCRIPTION/CONDITIONS
ADREFHI - ADREFLO
MIN
NOM
MAX UNIT
CR
Conversion range over
which specified accuracy is
maintained
3
5.5
V
ZSET
Zero Scale Offset
Difference between the first ideal transition
(from code 000h to 001h) and the actual
transition
10-bit mode
12-bit mode
10-bit mode
12-bit mode
1
2
2
3
LSB(1)
LSB(2)
LSB
FSET
Full Scale Offset
Difference between the range of the
measured code transitions (from first to last)
and the range of the ideal code transitions
LSB
EDNL
Differential nonlinearity
error
Difference between the actual step width and 10-bit mode
± 1.5
± 2
LSB
LSB
LSB
the ideal value. (see Figure 7-2)
12-bit mode
EINL
Integral nonlinearity error
Maximum deviation from the best straight line 10-bit mode
through the MibADC. MibADC transfer
± 2
characteristics, excluding the quantization
error.
12-bit mode
± 2
LSB
ETOT
Total unadjusted error
Maximum value of the difference between an
analog value and the ideal midstep value.
10-bit mode
12-bit mode
± 2
± 4
LSB
LSB
(1) 1 LSB = (ADREFHI – ADREFLO)/ 210 for 10-bit mode
(2) 1 LSB = (ADREFHI – ADREFLO)/ 212 for 12-bit mode
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7.2.4 Performance (Accuracy) Specifications
7.2.4.1 MibADC Nonlinearity Errors
The differential nonlinearity error shown in Figure 7-2 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
0 ... 101
0 ... 100
0 ... 011
Differential Linearity
Error (–½ LSB)
1 LSB
0 ... 010
Differential Linearity
Error (–½ LSB)
0 ... 001
0 ... 000
1 LSB
0
1
2
3
4
5
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-2. Differential Nonlinearity (DNL) Error
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The integral nonlinearity error shown in Figure 7-3 (sometimes referred to as linearity error) is the
deviation of the values on the actual transfer function from a straight line.
0 ... 111
0 ... 110
Ideal
Transition
0 ... 101
0 ... 100
0 ... 011
0 ... 010
0 ... 001
0 ... 000
Actual
Transition
At Transition
011/100
(–½ LSB)
End-Point Lin. Error
At Transition
001/010 (–1/4 LSB)
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-3. Integral Nonlinearity (INL) Error
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7.2.4.2 MibADC Total Error
The absolute accuracy or total error of an MibADC as shown in Figure 7-4 is the maximum value of the
difference between an analog value and the ideal midstep value.
0 ... 111
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-4. Absolute Accuracy (Total) Error
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7.3 General-Purpose Input/Output
The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and
bit-programmable. Both GIOA and GIOB support external interrupt capability.
7.3.1 Features
The GPIO module has the following features:
•
Each I/O pin can be configured as:
–
–
–
Input
Output
Open Drain
•
The interrupts have the following characteristics:
–
–
–
–
Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)
Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)
Individual interrupt flags (set in GIOFLG register)
Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers,
respectively
–
Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers
•
Internal pullup or pulldown allows unused I/O pins to be left unconnected
For information on input and output timings see Section 5.11 and Section 5.12
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7.4 Enhanced Next Generation High-End Timer (N2HET)
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses.
7.4.1 Features
The N2HET module has the following features:
•
•
•
•
•
Programmable timer for input and output timing functions
Reduced instruction set (30 instructions) for dedicated time and angle functions
160 words of instruction RAM protected by parity
User-defined number of 25-bit virtual counters for timer, event counters and angle counters
7-bit hardware counters for some pins allow up to 32-bit resolution in conjunction with the 25-bit virtual
counters
•
•
•
•
Up to 32 pins usable for input signal measurements or output signal generation
Programmable suppression filter for each input pin with adjustable limiting frequency
Low CPU overhead and interrupt load
Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)
or DMA
•
Diagnostic capabilities with different loopback mechanisms and pin status readback functionality
7.4.2 N2HET RAM Organization
The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one
RAM address may be written while another address is read. The RAM words are 96 bits wide, which are
split into three 32-bit fields (program, control, and data).
7.4.3 Input Timing Specifications
The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.
1
N2HETx
3
4
2
Figure 7-5. N2HET Input Capture Timings
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Table 7-11. Input Timing Requirements for the N2HET Input Capture Functionality
NO.
MIN(1) (2)
MAX(1) (2) UNIT
Input signal period, PCNT or WCAP for rising edge to rising
edge
1
2
3
4
2 (hr) (lr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
ns
ns
ns
ns
Input signal period, PCNT or WCAP for falling edge to falling
edge
2 (hr) (lr) tc(VCLK2) + 2
(hr) (lr) tc(VCLK2) + 2
(hr) (lr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
225 (hr) (lr) tc(VCLK2) - 2
225 (hr) (lr) tc(VCLK2) - 2
Input signal high phase, PCNT or WCAP for rising edge to
falling edge
Input signal low phase, PCNT or WCAP for falling edge to
rising edge
(1) hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).
(2) lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR).
Both N2HET1 and N2HET2 have channels that are enhanced to be able to capture inputs with smaller
pulse widths than that specified in Table 7-11. See Table 7-13 for a list of which pins support small pulse
capture.
The input capture capability for these channels is specified in Table 7-12.
Table 7-12. Input Timing Requirements for N2HET Channels with Enhanced Pulse Capture
NO.
MIN
MAX UNIT
Input signal period, PCNT or WCAP for rising edge to rising
edge
1
(hr) (lr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
ns
ns
ns
ns
Input signal period, PCNT or WCAP for falling edge to falling
edge
2
3
4
(hr) (lr) tc(VCLK2) + 2
2 (hr) tc(VCLK2) + 2
2 (hr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
225 (hr) (lr) tc(VCLK2) - 2
225 (hr) (lr) tc(VCLK2) - 2
Input signal high phase, PCNT or WCAP for rising edge to
falling edge
Input signal low phase, PCNT or WCAP for falling edge to
rising edge
Table 7-13. Input Capture Pin Capability
CHANNEL
N2HET1[00]
N2HET1[01]
N2HET1[02]
N2HET1[03]
N2HET1[04]
N2HET1[05]
N2HET1[06]
N2HET1[07]
N2HET1[08]
N2HET1[09]
N2HET1[10]
N2HET1[11]
N2HET1[12]
N2HET1[13]
N2HET1[14]
N2HET1[15]
N2HET1[16]
N2HET1[17]
N2HET1[18]
N2HET1[19]
N2HET1[20]
SUPPORTS 32-BIT CAPTURE
ENHANCED PULSE CAPTURE
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
No
No
No
No
Yes
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Table 7-13. Input Capture Pin Capability (continued)
CHANNEL
N2HET1[21]
N2HET1[22]
N2HET1[23]
N2HET1[24]
N2HET1[25]
N2HET1[26]
N2HET1[27]
N2HET1[28]
N2HET1[29]
N2HET1[30]
N2HET1[31]
N2HET2[00]
N2HET2[01]
N2HET2[02]
N2HET2[03]
N2HET2[04]
N2HET2[05]
N2HET2[06]
N2HET2[07]
N2HET2[08]
N2HET2[09]
N2HET2[10]
N2HET2[11]
N2HET2[12]
N2HET2[13]
N2HET2[14]
N2HET2[15]
N2HET2[16]
N2HET2[18]
SUPPORTS 32-BIT CAPTURE
ENHANCED PULSE CAPTURE
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
Yes
No
No
No
No
No
No
No
No
No
No
No
No
Yes
No
Yes
No
Yes
No
No
No
Yes
No
Yes
No
No
No
No
No
Yes
No
Yes
No
Yes
No
7.4.4 N2HET1-N2HET2 Interconnections
In some applications the N2HET resolutions must be synchronized. Some other applications require a
single time base to be used for all PWM outputs and input timing captures.
The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures
the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal
to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to
the loop resolution signal sent by the master. The slave does not require this signal after it receives the
first synchronization signal. However, anytime the slave receives the resynchronization signal from the
master, the slave must synchronize itself again..
N2HET1
N2HET2
NHET_LOOP_SYNC
EXT_LOOP_SYNC
NHET_LOOP_SYNC
EXT_LOOP_SYNC
Figure 7-6. N2HET1 – N2HET2 Synchronization Hookup
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7.4.5 N2HET Checking
7.4.5.1 Internal Monitoring
To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be
used to monitor each other’s signals as shown in Figure 7-7. The direction of the monitoring is controlled
by the I/O multiplexing control module.
IOMM mux control signal x
N2HET1[1,3,5,7,9,11]
N2HET1[1,3,5,7,9,11] / N2HET2[8,10,12,14,16,18]
N2HET1
N2HET2[8,10,12,14,16,18]
N2HET2
Figure 7-7. N2HET Monitoring
7.4.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure
the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].
Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to
measure the frequency of the pulse-width modulated (PWM) signal on N2HET2[0].
Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection
to the DCC module is made directly from the output of the N2HETx module (from the input of the output
buffer).
For more information on DCC see Section 6.7.3.
7.4.6 Disabling N2HET Outputs
Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET
module provides this capability via the "Pin Disable" input signal. This signal, when driven low, causes the
N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. See the device
specific technical reference manual for more details on the "N2HET Pin Disable" feature.
GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin
Disable" input for N2HET2.
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7.4.7 High-End Timer Transfer Unit (HTU)
A High-End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or
from main memory. An MPU is built into the HTU.
7.4.7.1 Features
CPU and DMA independent
•
•
•
•
•
•
•
Master Port to access system memory
8 control packets supporting dual buffer configuration
Control packet information is stored in RAM protected by parity
Event synchronization (HET transfer requests)
Supports 32- or 64-bit transactions
Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or
64 bit)
•
•
One shot, circular and auto switch buffer transfer modes
Request lost detection
7.4.7.2 Trigger Connections
Table 7-14. HTU1 Request Line Connection
MODULES
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
REQUEST SOURCE
HTUREQ[0]
HTUREQ[1]
HTUREQ[2]
HTUREQ[3]
HTUREQ[4]
HTUREQ[5]
HTUREQ[6]
HTUREQ[7]
HTU1 REQUEST
HTU1 DCP[0]
HTU1 DCP[1]
HTU1 DCP[2]
HTU1 DCP[3]
HTU1 DCP[4]
HTU1 DCP[5]
HTU1 DCP[6]
HTU1 DCP[7]
Table 7-15. HTU2 Request Line Connection
MODULES
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
REQUEST SOURCE
HTUREQ[0]
HTUREQ[1]
HTUREQ[2]
HTUREQ[3]
HTUREQ[4]
HTUREQ[5]
HTUREQ[6]
HTUREQ[7]
HTU2 REQUEST
HTU2 DCP[0]
HTU2 DCP[1]
HTU2 DCP[2]
HTU2 DCP[3]
HTU2 DCP[4]
HTU2 DCP[5]
HTU2 DCP[6]
HTU2 DCP[7]
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7.5 Controller Area Network (DCAN)
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to 1
Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example,
automotive and industrial fields) that require reliable serial communication or multiplexed wiring.
7.5.1 Features
Features of the DCAN module include:
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 Mbps
The CAN kernel can be clocked by the oscillator for baud-rate generation.
64 mailboxes on each DCAN
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Message RAM protected by parity
Direct access to Message RAM during test mode
CAN Rx / Tx pins configurable as general purpose IO pins
Message RAM Auto Initialization
DMA support
For more information on the DCAN, see the RM48x 16/32-Bit RISC Flash Microcontroller Technical
Reference Manual (SPNU503).
7.5.2 Electrical and Timing Specifications
Table 7-16. Dynamic Characteristics for the DCANx TX and RX Pins
PARAMETER
Delay time, transmit shift register to CANnTX pin(1)
MIN
MAX
15
UNIT
ns
td(CANnTX)
td(CANnRX)
Delay time, CANnRX pin to receive shift register
5
ns
(1) These values do not include rise/fall times of the output buffer.
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7.6 Local Interconnect Network Interface (LIN)
The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is
an SCI. The hardware features of the SCI are augmented to achieve LIN compatibility.
The SCI module is a Universal Asynchronous Receiver-Transmitter (UART) that implements the standard
nonreturn to zero format. The SCI can be used to communicate, for example, through an RS-232 port or
over a K-line.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is
single-master/multiple-slave with a message identification for multicast transmission between any network
nodes.
7.6.1 LIN Features
The following are features of the LIN module:
•
•
•
•
Compatible to LIN 1.3, 2.0, and 2.1 protocols
Multibuffered receive and transmit units DMA capability for minimal CPU intervention
Identification masks for message filtering
Automatic Master Header Generation
–
–
–
Programmable Synch Break Field
Synch Field
Identifier Field
•
Slave Automatic Synchronization
–
–
–
Synch break detection
Optional baudrate update
Synchronization Validation
231 programmable transmission rates with 7 fractional bits
•
•
•
Error detection
2 Interrupt lines with priority encoding
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7.7 Serial Communication Interface (SCI)
7.7.1 Features
•
•
•
•
•
Standard UART communication
Supports full- or half-duplex operation
Standard nonreturn to zero (NRZ) format
Double-buffered receive and transmit functions
Configurable frame format of 3 to 13 bits per character based on the following:
–
–
–
–
Data word length programmable from 1 to 8 bits
Additional address bit in address-bit mode
Parity programmable for zero or 1 parity bit, odd or even parity
Stop programmable for 1 or 2 stop bits
•
•
•
•
Asynchronous or isosynchronous communication modes
Two multiprocessor communication formats allow communication between more than two devices.
Sleep mode is available to free CPU resources during multiprocessor communication.
The 24-bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate
selection.
•
•
Four error flags and five status flags provide detailed information regarding SCI events.
Capability to use DMA for transmit and receive data.
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7.8 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface
between the RM4x microcontroller and devices compliant with Philips Semiconductor I2C-bus specification
version 2.1 and connected by an I2C-bus™. This module will support any slave or master I2C compatible
device.
7.8.1 Features
The I2C has the following features:
•
Compliance to the Philips I2C-bus specification, v2.1 (The I2C Specification, Philips document number
9398 393 40011)
–
–
–
–
–
–
–
–
Bit/Byte format transfer
7-bit and 10-bit device addressing modes
General call
START byte
Multimaster transmitter/ slave receiver mode
Multimaster receiver/ slave transmitter mode
Combined master transmit/receive and receive/transmit mode
Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)
•
•
•
•
•
•
•
•
•
•
Free data format
Two DMA events (transmit and receive)
DMA event enable/disable capability
Seven interrupts that can be used by the CPU
Module enable/disable capability
The SDA and SCL are optionally configurable as general-purpose I/O
Slew rate control of the outputs
Open-drain control of the outputs
Programmable pullup/pulldown capability on the inputs
Supports Ignore NACK mode
NOTE
This I2C module does not support:
•
•
•
High-speed (HS) mode
C-bus compatibility mode
The combined format in 10-bit address mode (the I2C module sends the slave address
second byte every time it sends the slave address first byte)
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7.8.2 I2C I/O Timing Specifications
Table 7-17. I2C Signals (SDA and SCL) Switching Characteristics(1)
STANDARD MODE
FAST MODE
MIN
PARAMETER
UNIT
MIN
MAX
MAX
149
Cycle time, Internal Module clock for I2C,
prescaled from VCLK
tc(I2CCLK)
75.2
149
100
75.2
ns
f(SCL)
SCL Clock frequency
Cycle time, SCL
0
0
400
kHz
µs
tc(SCL)
10
2.5
Setup time, SCL high before SDA low (for a
repeated START condition)
tsu(SCLH-SDAL)
th(SCLL-SDAL)
4.7
4
0.6
0.6
µs
µs
Hold time, SCL low after SDA low (for a repeated
START condition)
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
250
100
Hold time, SDA valid after SCL low (for I2C bus
devices)
th(SDA-SCLL)
tw(SDAH)
tsu(SCLH-SDAH)
tw(SP)
0
4.7
4.0
3.45(2)
0
0.9
µs
µs
µs
Pulse duration, SDA high between STOP and
START conditions
1.3
Setup time, SCL high before SDA high (for STOP
condition)
0.6
0
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(3)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(3) Cb = The total capacitance of one bus line in pF.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SP)
tw(SCLL)
tr(SCL)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
tf(SCL)
th(SCLL-SDAL)
tsu(SCLH-SDAL)
th(SDA-SCLL)
Stop
Start
Repeated Start
Stop
Figure 7-8. I2C Timings
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NOTE
•
A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
•
•
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW
period (tw(SCLL)) of the SCL signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the
requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr max + tsu(SDA-SCLH)
.
•
Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-
times are allowed.
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7.9 Multibuffered / Standard Serial Peripheral Interface
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display
drivers, and analog-to-digital converters.
7.9.1 Features
Both Standard and MibSPI modules have the following features:
•
•
•
•
16-bit shift register
Receive buffer register
11-bit baud clock generator
SPICLK can be internally-generated (master mode) or received from an external clock source (slave
mode)
•
•
Each word transferred can have a unique format
SPI I/Os not used in the communication can be used as digital input/output signals
Table 7-18. MibSPI/SPI Configurations
MibSPIx/SPIx
MibSPI1
I/Os
MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA
MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA
SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA
MibSPI3
MibSPI5
SPI2
SPI4
SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA
7.9.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a
16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each.
7.9.3 MibSPI Transmit Trigger Events
Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event
and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low
level at a selectable trigger source. For example, up to 15 trigger sources are available which can be used
by each transfer group. These trigger options are listed in Table 7-19 for MIBSPI1, Section 7.9.3.2 for
MIBSPI3 and Section 7.9.3.3 for MibSPI5.
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7.9.3.1 MIBSPI1 Event Trigger Hookup
Table 7-19. MIBSPI1 Event Trigger Hookup
EVENT #
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
TGxCTRL TRIGSRC[3:0]
TRIGGER
No trigger source
GIOA[0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
GIOA[1]
GIOA[2]
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
N2HET1[8]
N2HET1[10]
N2HET1[12]
N2HET1[14]
N2HET1[16]
N2HET1[18]
Internal Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin, or by driving the GIOx pin from an external trigger
source.
7.9.3.2 MIBSPI3 Event Trigger Hookup
Table 7-20. MIBSPI3 Event Trigger Hookup
EVENT #
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
EVENT10
EVENT11
TGxCTRL TRIGSRC[3:0]
TRIGGER
No trigger source
GIOA[0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
GIOA[1]
GIOA[2]
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
HET[8]
N2HET1[10]
N2HET1[12]
N2HET1[14]
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Table 7-20. MIBSPI3 Event Trigger Hookup (continued)
EVENT #
EVENT12
EVENT13
EVENT14
TGxCTRL TRIGSRC[3:0]
TRIGGER
N2HET1[16]
1101
1110
1111
N2HET1[18]
Internal Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin, or by driving the GIOx pin from an external trigger
source.
7.9.3.3 MIBSPI5 Event Trigger Hookup
Table 7-21. MIBSPI5 Event Trigger Hookup
EVENT #
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
TGxCTRL TRIGSRC[3:0]
TRIGGER
No trigger source
GIOA[0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
GIOA[1]
GIOA[2]
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
N2HET1[8]
N2HET1[10]
N2HET1[12]
N2HET1[14]
N2HET1[16]
N2HET1[18]
Internal Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
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NOTE
For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin + selecting the pin to be a GIOx pin, or by driving the
GIOx pin from an external trigger source. If the mux control module is used to select different
functionality instead of the GIOx signal, then care must be taken to disable GIOx from
triggering MibSPI5 transfers; there is no multiplexing on the input connections.
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7.9.4 MibSPI/SPI Master Mode I/O Timing Specifications
Table 7-22. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO.
PARAMETER
MIN
MAX UNIT
1
tc(SPC)M
Cycle time, SPICLK(4)
40
256tc(VCLK)
ns
ns
Pulse duration, SPICLK high (clock
polarity = 0)
tw(SPCH)M
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M – 6
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
2(5)
3(5)
4(5)
5(5)
6(5)
7(5)
Pulse duration, SPICLK low (clock
polarity = 1)
tw(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 0)
tw(SPCL)M
ns
ns
ns
ns
ns
Pulse duration, SPICLK high (clock
polarity = 1)
tw(SPCH)M
Delay time, SPISIMO valid before
SPICLK low (clock polarity = 0)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
th(SPCL-SOMI)M
th(SPCH-SOMI)M
Delay time, SPISIMO valid before
SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 6
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M – tf(SPC) – 4
0.5tc(SPC)M – tr(SPC) – 4
tf(SPC) + 2.2
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
tr(SPC) + 2.2
Hold time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
10
Hold time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
10
C2TDELAY*tc(VCLK) + 2*tc(VCLK)
- tf(SPICS) + tr(SPC) – 7
(C2TDELAY+2) * tc(VCLK)
-
CSHOLD = 0
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
Setup time CS active
until SPICLK high
(clock polarity = 0)
tf(SPICS) + tr(SPC) + 5.5
C2TDELAY*tc(VCLK) + 3*tc(VCLK)
- tf(SPICS) + tr(SPC) – 7
(C2TDELAY+3) * tc(VCLK)
-
tf(SPICS) + tr(SPC) + 5.5
8(6) tC2TDELAY
ns
C2TDELAY*tc(VCLK) + 2*tc(VCLK)
- tf(SPICS) + tf(SPC) – 7
(C2TDELAY+2) * tc(VCLK)
-
Setup time CS active
until SPICLK low
(clock polarity = 1)
tf(SPICS) + tf(SPC) + 5.5
C2TDELAY*tc(VCLK) + 3*tc(VCLK)
- tf(SPICS) + tf(SPC) – 7
(C2TDELAY+3) * tc(VCLK)
-
tf(SPICS) + tf(SPC) + 5.5
0.5*tc(SPC)M
T2CDELAY*tc(VCLK) + tc(VCLK)
+
-
0.5*tc(SPC)M
T2CDELAY*tc(VCLK) + tc(VCLK)
+
-
Hold time SPICLK low until CS inactive
(clock polarity = 0)
tf(SPC) + tr(SPICS) - 7
tf(SPC) + tr(SPICS) + 11
9(6) tT2CDELAY
ns
0.5*tc(SPC)M
T2CDELAY*tc(VCLK) + tc(VCLK)
+
-
0.5*tc(SPC)M
T2CDELAY*tc(VCLK) + tc(VCLK)
+
-
Hold time SPICLK high until CS
inactive (clock polarity = 1)
tr(SPC) + tr(SPICS) - 7
(C2TDELAY+1) * tc(VCLK)
tf(SPICS) – 29
tr(SPC) + tr(SPICS) + 11
-
ns
ns
10
11
tSPIENA
SPIENAn Sample point
(C2TDELAY+1)*tc(VCLK)
SPIENAn Sample point from write to
buffer
tSPIENAW
(C2TDELAY+2)*tc(VCLK)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see Table 5-7.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
6
7
Master In Data
Must Be Valid
SPISOMI
Figure 7-9. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
8
9
10
11
SPIENAn
Figure 7-10. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
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Table 7-23. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO.
PARAMETER
Cycle time, SPICLK
MIN
MAX UNIT
(4)
1
tc(SPC)M
40
256tc(VCLK) ns
Pulse duration, SPICLK high (clock
polarity = 0)
tw(SPCH)M
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
2(5)
ns
ns
Pulse duration, SPICLK low (clock
polarity = 1)
tw(SPCL)M
tw(SPCL)M
tw(SPCH)M
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK low (clock
polarity = 0)
3(5)
Pulse duration, SPICLK high (clock
polarity = 1)
Valid time, SPICLK high after
tv(SIMO-SPCH)M
SPISIMO data valid (clock polarity =
0)
0.5tc(SPC)M – 6
4(5)
ns
Valid time, SPICLK low after
tv(SIMO-SPCL)M
SPISIMO data valid (clock polarity =
1)
0.5tc(SPC)M – 6
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
0.5tc(SPC)M – tr(SPC) – 4
5(5)
6(5)
7(5)
ns
ns
ns
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5tc(SPC)M – tf(SPC) – 4
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
tr(SPC) + 2.2
tf(SPC) + 2.2
10
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
10
0.5*tc(SPC)M
(C2TDELAY+2) * tc(VCLK)
+
-
0.5*tc(SPC)M
(C2TDELAY+2) * tc(VCLK)
+
-
CSHOLD = 0
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
Setup time CS
active until SPICLK
high (clock polarity =
0)
tf(SPICS) + tr(SPC) – 7
tf(SPICS) + tr(SPC) + 5.5
0.5*tc(SPC)M
(C2TDELAY+3) * tc(VCLK)
+
-
0.5*tc(SPC)M
(C2TDELAY+3) * tc(VCLK)
+
-
tf(SPICS) + tr(SPC) – 7
tf(SPICS) + tr(SPC) + 5.5
8(6) tC2TDELAY
ns
0.5*tc(SPC)M
(C2TDELAY+2) * tc(VCLK)
+
-
0.5*tc(SPC)M
(C2TDELAY+2) * tc(VCLK)
+
-
Setup time CS
active until SPICLK
low (clock polarity =
1)
tf(SPICS) + tf(SPC) – 7
tf(SPICS) + tf(SPC) + 5.5
0.5*tc(SPC)M
(C2TDELAY+3) * tc(VCLK)
+
-
0.5*tc(SPC)M
(C2TDELAY+3) * tc(VCLK)
+
-
tf(SPICS) + tf(SPC) – 7
tf(SPICS) + tf(SPC) + 5.5
T2CDELAY*tc(VCLK)
tc(VCLK) - tf(SPC) + tr(SPICS)
+
-
7
T2CDELAY*tc(VCLK)
tc(VCLK) - tf(SPC) + tr(SPICS)
+
+
Hold time SPICLK low until CS
inactive (clock polarity = 0)
11
9(6) tT2CDELAY
ns
T2CDELAY*tc(VCLK)
tc(VCLK) - tr(SPC) + tr(SPICS)
+
-
7
T2CDELAY*tc(VCLK)
tc(VCLK) - tr(SPC) + tr(SPICS)
+
+
Hold time SPICLK high until CS
inactive (clock polarity = 1)
11
(C2TDELAY+1)* tc(VCLK)
-
ns
ns
10 tSPIENA
SPIENAn Sample Point
(C2TDELAY+1)*tc(VCLK)
tf(SPICS) – 29
SPIENAn Sample point from write to
buffer
11 tSPIENAW
(C2TDELAY+2)*tc(VCLK)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see the Table 5-7.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Master Out Data Is Valid
Data Valid
SPISIMO
SPISOMI
6
7
Master In Data
Must Be Valid
Figure 7-11. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
8
9
10
11
SPIENAn
Figure 7-12. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
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7.9.5 SPI Slave Mode I/O Timings
Table 7-24. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =
input, and SPISOMI = output)(1)(2)(3)(4)
NO.
1
PARAMETER
Cycle time, SPICLK(5)
MIN
40
MAX UNIT
tc(SPC)S
ns
2(6)
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
14
ns
ns
14
3(6)
4(6)
14
14
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
td(SPCH-SOMI)S
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
th(SPCL-SIMO)S
th(SPCH-SIMO)S
td(SPCL-SENAH)S
td(SPCH-SENAH)S
td(SCSL-SENAL)S
trf(SOMI) + 20
trf(SOMI) + 20
ns
ns
ns
ns
Delay time, SPISOMI valid after SPICLK low (clock polarity
= 1)
5(6)
Hold time, SPISOMI data valid after SPICLK high (clock
polarity =0)
2
Hold time, SPISOMI data valid after SPICLK low (clock
polarity =1)
2
6(6)
Setup time, SPISIMO before SPICLK low (clock polarity =
0)
4
Setup time, SPISIMO before SPICLK high (clock polarity =
1)
4
2
Hold time, SPISIMO data valid after SPICLK low (clock
polarity = 0)
7(6)
Hold time, SPISIMO data valid after S PICLK high (clock
polarity = 1)
2
Delay time, SPIENAn high after last SPICLK low (clock
polarity = 0)
2.5tc(VCLK)+tr(ENAn)
+
1.5tc(VCLK)
1.5tc(VCLK)
tf(ENAn)
22
8
9
ns
ns
Delay time, SPIENAn high after last SPICLK high (clock
polarity = 1)
2.5tc(VCLK)+ tr(ENAn)
+
22
Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
tc(VCLK)+tf(ENAn)+27
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-7.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI Data Is Valid
SPISOMI
SPISIMO
6
7
SPISIMO Data
Must Be Valid
Figure 7-13. SPI Slave Mode External Timing (CLOCK PHASE = 0)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
SPICSn
9
Figure 7-14. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)
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Table 7-25. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =
input, and SPISOMI = output)(1)(2)(3)(4)
NO.
PARAMETER
Cycle time, SPICLK(5)
MIN
40
MAX
UNIT
1
tc(SPC)S
ns
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
14
2(6)
3(6)
ns
ns
14
14
14
Dealy time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
td(SOMI-SPCL)S
td(SOMI-SPCH)S
th(SPCL-SOMI)S
th(SPCH-SOMI)S
tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
tv(SPCH-SIMO)S
tv(SPCL-SIMO)S
td(SPCH-SENAH)S
td(SPCL-SENAH)S
td(SCSL-SENAL)S
td(SCSL-SOMI)S
trf(SOMI) + 20
trf(SOMI) + 20
4(6)
5(6)
6(6)
7(6)
8
ns
ns
ns
ns
ns
Delay time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity =0)
2
2
4
4
2
2
Hold time, SPISOMI data valid after SPICLK low (clock
polarity =1)
Setup time, SPISIMO before SPICLK high (clock
polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity
= 1)
High time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
High time, SPISIMO data valid after SPICLK low (clock
polarity = 1)
Delay time, SPIENAn high after last SPICLK high
(clock polarity = 0)
1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22
1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22
Delay time, SPIENAn high after last SPICLK low (clock
polarity = 1)
Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
9
tf(ENAn)
tc(VCLK)
tc(VCLK)+tf(ENAn)+ 27
2tc(VCLK)+trf(SOMI)+ 28
ns
ns
Delay time, SOMI valid after SPICSn low (if new data
has been written to the SPI buffer)
10
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-7.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 7-15. SPI Slave Mode External Timing (CLOCK PHASE = 1)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
SPICSn
9
10
SPISOMI
Slave Out Data Is Valid
Figure 7-16. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)
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7.10 Ethernet Media Access Controller
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the CPU and the
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode, with hardware flow control and quality of service (QoS) support.
The EMAC controls the flow of packet data from the RM4x device to the PHY. The MDIO module controls
PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the RM4x device through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
7.10.1 Ethernet MII Electrical and Timing Specifications
1
2
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
VALID
Figure 7-17. MII Receive Timing
Table 7-26. Timing Requirements for EMAC MII Receive
NO.
MIN
8
MAX UNIT
tsu(MIIRXD - MIIRXCLKH)
tsu(MIIRXDV - MIIRXCLKH)
tsu(MIIRXER - MIIRXCLKH)
th(MIIRXCLKH - MIIRXD)
th(MIIRXCLKH - MIIRXDV)
th(MIIRXCLKH - MIIRXER)
Setup time, MII_RXD[3:0] before MII_RX_CLK rising edge
Setup time, MII_RX_DV before MII_RX_CLK rising edge
Setup time, MII_RX_ER before MII_RX_CLK rising edge
Hold time, MII_RXD[3:0] valid after MII_RX_CLK rising edge
Hold time, MII_RX_DV valid after MII_RX_CLK rising edge
Hold time, MII_RX_ER valid after MII_RX_CLK rising edge
ns
ns
ns
ns
ns
ns
1
8
8
8
2
8
8
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1
MII_TX_CLK
MII_TXD[3:0]
MII_TXEN
VALID
Figure 7-18. MII Transmit Timing
Table 7-27. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
NO.
PARAMETER
MIN
5
MAX UNIT
td(MIIRXCLKH - MIITXD)
td(MIIRXCLKH - MIITXEN)
Delay time, MII_TX_CLK rising edge to MII_TXD[3:0] valid
Delay time, MII_TX_CLK rising edge to MII_TXEN valid
25
25
ns
ns
1
5
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7.10.2 Ethernet RMII Electrical and Timing Specifications
1
2
3
RMII_REFCLK
5
5
RMII_TXEN
4
RMII_TXD[1:0]
6
7
RMII_RXD[1:0]
9
8
10
RMII_CRS_DV
11
RMII_RX_ER
Figure 7-19. RMII Timing Diagram
Table 7-28. Timing Requirements for EMAC RMII Receive and RMII_REFCLK
NO.
1
MIN
NOM
MAX UNIT
tc(REFCLK)
Cycle time, RMII_REFCLK
20
ns
2
tw(REFCLKH)
tw(REFCLKL)
tsu(RXD-REFCLK)
th(REFCLK-RXD)
Pulse width, RMII_REFCLK high
7
7
4
2
4
2
4
2
13
13
ns
ns
ns
ns
ns
ns
ns
ns
3
Pulse width, RMII_REFCLK low
6
Input setup time, RMII_RXD[1:0] valid before RMII_REFCLK high
Input hold time, RMII_RXD[1:0] valid after RMII_REFCLK high
7
8
tsu(CRSDV-REFCLK) Input setup time, RMII_CRS_DV valid before RMII_REFCLK high
th(REFCLK-CRSDV) Input hold time, RMII_CRS_DV valid after RMII_REFCLK high
tsu(RXER-REFCLK) Input setup time, RMII_RX_ER valid before RMII_REFCLK high
9
10
11
th(REFCLK-RXER)
Input hold time, RMII_RX_ER valid after RMII_REFCLK high
Table 7-29. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit
NO.
4
PARAMETER
MIN
2
MAX
UNIT
ns
td(REFCLK-TXD)
td(REFCLK-TXEN)
Output delay time, RMII_REFCLK high to RMII_TXD[1:0] valid
Output delay time, RMII_REFCLK high to RMII_TXEN valid
5
2
ns
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7.10.3 Management Data Input/Output (MDIO) Electrical and Timing Specifications
1
3
3
MDCLK
4
5
MDIO
(input)
Figure 7-20. MDIO Input Timing
Table 7-30. Timing Requirements for MDIO Input
NO.
1
MIN
MAX
UNIT
ns
tc(MDCLK)
tw(MDCLK)
tt(MDCLK)
Cycle time, MDCLK
400
180
-
-
-
2
Pulse duration, MDCLK high or low
Transition time, MDCLK
ns
3
5
ns
Setup time, MDIO data input valid before
MDCLK High
ns
4
5
tsu(MDIO-MDCLKH)
th(MDCLKH-MDIO)
33(1)
-
-
Hold time, MDIO data input valid after
MDCLK High
ns
10
(1) This is a discrepancy to IEEE 802.3, but is compatible with many PHY devices.
1
MDCLK
7
MDIO
(output)
Figure 7-21. MDIO Output Timing
Table 7-31. MDIO Output Timing Requirements
NO.
MIN
MAX
UNIT
1
tc(MDCLK)
Cycle time, MDCLK
400
–
ns
Delay time, MDCLK low to MDIO data output
valid
7
td(MDCLKL-MDIO)
–7
100
ns
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8 Device and Documentation Support
8.1 Device Support
8.1.1 Development Support
Texas Instruments (TI) offers an extensive line of development tools for the TMS570LSxRM48Lx family of
MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development:
Software Development Tools
•
Code Composer Studio™ (CCS) Integrated Development Environment (IDE)–
–
–
–
–
C/C++ Compiler
Code generation tools
Assembler/Linker
FPU Optimized Libraries
•
•
Application algorithms
Sample applications code
Hardware Development Tools
•
•
•
Development and evaluation boards
JTAG-based emulators - XDS510™ class, XDS560™ emulator, XDS100v2, XDS110, XDS200
Flash programming tools
For a complete listing of development-support tools, visit the Texas Instruments website at www.ti.com.
8.1.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MCU devices. Each MCU commercial family member has one of three prefixes: X, P, or NULL [blank] (for
example, xRM48L952). These prefixes represent evolutionary stages of product development from
engineering prototypes (X) through fully qualified production devices (NULL[blank]).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications.
P
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
NULL
Fully-qualified production device.
X and P devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
Figure 8-1 shows the numbering and symbol nomenclature for the RM48Lx40.
For additional information on the device nomenclature markings, see the device-specific silicon errata
document listed in Section 8.2.1, Related Documentation from Texas Instruments.
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x RM 4 8 L 9 4 0 D ZWT T R
Prefix:
x = Not Qualified
Removed when qualified
Shipping Options:
R = Tape and Reel
RM = Real Time Microcontroller
Temperature Range:
T = –40oC to 105oC
CPU:
4 = ARM Cortex-R4
Package Type:
ZWT = 337-Pin Plastic BGA with pb-free solder ball
PGE = 144-Pin Plastic Quad Flatpack
Series Number
Die Revision:
Blank = Die Revision C
D = Die Revision D
Architecture:
L = Lockstep
Flash / RAM Size:
9 = 3MB flash, 256KB RAM
7 = 2MB flash, 256KB RAM
5 = 2MB flash, 192KB RAM
Frequency:
0 = 200 MHz
Network Interfaces:
4 = Ethernet only
Figure 8-1. RM48x Device Numbering Conventions
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8.2 Documentation Support
8.2.1 Related Documentation from Texas Instruments
The following documents describe the RM48Lx40 microcontroller.
SPNU503
RM48x 16/32-Bit RISC Flash Microcontroller Technical Reference Manualdetails the
integration, the environment, the functional description, and the programming models for
each peripheral and subsystem in the device.
SPNZ196
SPNZ223
SPNA207
RM48x Microcontroller, Silicon Revision C, Silicon Errata describes the usage notes and
known exceptions to the functional specifications for the device silicon revision C.
RM48x Microcontroller, Silicon Revision D, Silicon Errata describes the usage notes and
known exceptions to the functional specifications for the device silicon revision D.
Calculating Equivalent Power-on-Hours for Hercules™ Safety MCUs details how to use
the spreadsheet to calculate the aging effect of temperature on Texas Instruments Hercules
Safety MCUs.
8.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
TECHNICAL
DOCUMENTS
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TOOLS & SOFTWARE
RM48L940
RM48L740
RM48L540
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
8.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
8.5 Trademarks
Code Composer Studio, XDS510, XDS560, E2E are trademarks of Texas Instruments.
CoreSight is a trademark of ARM Limited.
ARM, Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.
All rights reserved.
All other trademarks are the property of their respective owners.
8.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.7 Glossary
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SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
8.8 Device Identification Code Register
The device identification code register identifies several aspects of the device including the silicon version.
The details of the device identification code register are shown in Table 8-2. The device identification code
register value for this device is:
•
•
•
•
Rev A = 0x802AAD05
Rev B = 0x802AAD15
Rev C = 0x802AAD1D
Rev D = 0x802AAD25
Figure 8-2. Device ID Bit Allocation Register
31
CP-15
R-1
30
29
13
28
27
26
25
24
23
22
21
20
19
3
18
17
16
TECH
R-0
UNIQUE ID
R-00000000010101
15
14
12
11
10
9
8
7
6
5
4
2
1
1
0
0
PERIP
H
PARIT
Y
I/O
VOLT
AGE
RAM
ECC
TECH
R-101
FLASH ECC
R-10
VERSION
R-00000
1
R-0
R-1
R-1
R-1
R-0
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-2. Device ID Bit Allocation Register Field Descriptions
BIT
FIELD
VALUE
DESCRIPTION
Indicates the presence of coprocessor 15
31
CP15
1
CP15 present
30-17
UNIQUE ID
10101
Silicon version (revision) bits.
This bit field holds a unique number for a dedicated device configuration (die).
16-13
12
TECH
Process technology on which the device is manufactured.
0101
0
F021
I/O VOLTAGE
I/O voltage of the device.
I/O are 3.3 V
11
PERIPHERAL
PARITY
Peripheral Parity
1
10
1
Parity on peripheral memories
Flash ECC
10-9
8
FLASH ECC
RAM ECC
Program memory with ECC
Indicates if RAM memory ECC is present.
ECC implemented
7-3
2-0
REVISION
101
Revision of the device.
The platform family ID is always 0b101
160
Device and Documentation Support
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SPNS175C –APRIL 2012–REVISED JUNE 2015
8.9 Die Identification Registers
The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit die ID with the
information as shown in Table 8-3.
Table 8-3. Die-ID Registers
ITEM
X Coord. on Wafer
Y Coord. on Wafer
Wafer #
NUMBER OF BITS
BIT LOCATION
0xFFFFFF7C[11:0]
0xFFFFFF7C[23:12]
0xFFFFFF7C[31:24]
0xFFFFFF80[23:0]
0xFFFFFF80[31:24]
12
12
8
Lot #
24
8
Reserved
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Device and Documentation Support
161
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8.10 Module Certifications
The following communications modules have received certification of adherence to a standard.
162
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8.10.1 DCAN Certification
Figure 8-3. DCAN Certification
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Device and Documentation Support
163
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8.10.2 LIN Certification
8.10.2.1 LIN Master Mode
Figure 8-4. LIN Certification - Master Mode
164
Device and Documentation Support
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SPNS175C –APRIL 2012–REVISED JUNE 2015
8.10.2.2 LIN Slave Mode - Fixed Baud Rate
Figure 8-5. LIN Certification - Slave Mode - Fixed Baud Rate
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8.10.2.3 LIN Slave Mode - Adaptive Baud Rate
Figure 8-6. LIN Certification - Slave Mode - Adaptive Baud Rate
166
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SPNS175C –APRIL 2012–REVISED JUNE 2015
9 Mechanical Packaging and Orderable Information
9.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
without revision of this document. For browser-based versions of this data sheet, refer to the left-hand
navigation.
Copyright © 2012–2015, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
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167
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
RM48L540DPGET
RM48L540DPGETR
RM48L740DZWTT
RM48L940DZWTT
ACTIVE
LQFP
LQFP
PGE
144
144
337
337
60
Green (RoHS
& no Sb/Br)
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
RM48
L540DPGET
PREVIEW
ACTIVE
ACTIVE
PGE
500
90
Green (RoHS
& no Sb/Br)
NIPDAU
SNAGCU
SNAGCU
RM48
L540DPGET
NFBGA
NFBGA
ZWT
Green (RoHS
& no Sb/Br)
RM48
L740DZWTT
ZWT
90
Green (RoHS
& no Sb/Br)
RM48
L940DZWTT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OUTLINE
ZWT0337A
NFBGA - 1.4 mm max height
SCALE 0.950
PLASTIC BALL GRID ARRAY
16.1
15.9
A
B
BALL A1 CORNER
16.1
15.9
1.4 MAX
C
SEATING PLANE
0.12 C
0.45
0.35
BALL TYP
TYP
14.4 TYP
SYMM
(0.8) TYP
(0.8) TYP
W
V
U
T
R
P
N
M
L
14.4
TYP
SYMM
K
J
H
G
F
0.55
337X
0.45
E
D
C
0.15
0.05
C A B
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
0.8 TYP
0.8 TYP
BALL A1 CORNER
4223381/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZWT0337A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
337X ( 0.4)
11
12
13 14 15 16 17 18 19
1
3
4
6
7
8
9
10
2
5
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:7X
METAL UNDER
SOLDER MASK
0.05 MAX
0.05 MIN
(
0.4)
METAL
EXPOSED METAL
(
0.4)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223381/A 02/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZWT0337A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(
0.4) TYP
(0.8) TYP
11
12
13 14 15 16 17 18 19
1
3
4
6
7
8
9
10
2
5
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:7X
4223381/A 02/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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