SCAN90004 [TI]

具有预加重功能的 4 通道 LVDS 缓冲器/中继器;


型号：	SCAN90004
厂家：	TEXAS INSTRUMENTS
描述：	具有预加重功能的 4 通道 LVDS 缓冲器/中继器中继器
文件：	总16页 (文件大小：528K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SCAN90004

www.ti.com

SNLS182P –MAY 2005–REVISED APRIL 2013

SCAN90004 4-Channel LVDS Buffer/Repeater

with Pre-Emphasis

Check for Samples: SCAN90004

FEATURES

DESCRIPTION

The SCAN90004 is a four channel 1.5 Gbps LVDS

buffer/repeater. High speed data paths and flow-

through pinout minimize internal device jitter and

simplify board layout, while configurable pre-

emphasis overcomes ISI jitter effects from lossy

backplanes and cables. The differential inputs

interface to LVDS, and Bus LVDS signals such as

those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes,

as well as CML and LVPECL. The differential inputs

and outputs are internally terminated with a 100Ω

resistor to improve performance and minimize board

space. The repeater function is especially useful for

boosting signals for longer distance transmission over

lossy cables and backplanes.

•

1.5 Gbps Maximum Data Rate Per Channel

Configurable Pre-emphasis Drives Lossy

Backplanes and Cables

•

Low Output Skew and Jitter

LVDS/CML/LVPECL Compatible Input, LVDS

Output

•

On-chip 100Ω Input and Output Termination

12 kV ESD Protection on LVDS Outputs

IEEE 1149.1 JTAG Interface

IEEE 1149.6 Limited Capability

Fault Insertion

Single 3.3V Supply

Integrated testability circuitry supports IEEE1149.1

(JTAG) on single-ended LVTTL/CMOS I/O and

limited IEEE1149.6 capability on high-speed

differential LVDS interconnects. The 3.3V supply,

CMOS process, and LVDS I/O ensure stable high

performance at low power over the entire industrial -

40 to +85°C temperature range.

Very Low Power Consumption

Industrial -40 to +85°C Temperature Range

Small TQFP Package Footprint

See DS90LV004 for Non-JTAG Version

Typical Application

SCAN90004

Cable or Backplane

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SCAN90004

SNLS182P –MAY 2005–REVISED APRIL 2013

www.ti.com

Block and Connection Diagrams

PEM0 PEM1 PWDN

Pre-emphasis

and Control

48 47 46 45 44 43 42 41 40 39 38 37

N/C

TDO

TDI

PEM0

PEM1

V_DD

OUT0+

OUT0-

IN0+

IN0-

V_DD

OUT1+

OUT1-

IN1+

IN1-

SCAN90004

(TQFP)

N/C

V_DD

N/C

V_DD

GND

V_DD

OUT2+

OUT2-

IN2+

IN2-

TMS

TCK

TRST

V_DD

PWDN

13 14 15 16 17 18 19 20 21 22 23 24

OUT3+

OUT3-

IN3+

IN3-

IEEE 1149.1 TAP

(JTAG) & 1149.6

TDI

TDO

TCK TMS TRST

Figure 1. SCAN90004 Block Diagram

Figure 2. Pinout - Top View

Pin Descriptions

Name

TQFP Pin

Number

I/O, Type

Description

DIFFERENTIAL INPUTS

IN0+

IN0−

I, LVDS

Channel 0 inverting and non-inverting differential inputs.

Channel 1 inverting and non-inverting differential inputs.

Channel 2 inverting and non-inverting differential inputs.

Channel 3 inverting and non-inverting differential inputs.

IN1+

IN1−

IN2+

IN2−

IN3+

IN3−

DIFFERENTIAL OUTPUTS

(1)

OUT0+

OUT0−

O, LVDS

Channel 0 inverting and non-inverting differential outputs.

Channel 1 inverting and non-inverting differential outputs.

Channel 2 inverting and non-inverting differential outputs.

Channel 3 inverting and non-inverting differential outputs.

OUT1+

OUT1−

OUT2+

OUT2−

OUT3+

OUT3-

DIGITAL CONTROL INTERFACE

PWDN 12

I, LVTTL

A logic low at PWDN activates the hardware power down mode.

(1) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN90004 device have

been optimized for point-to-point backplane and cable applications.

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SNLS182P –MAY 2005–REVISED APRIL 2013

Pin Descriptions (continued)

Name

TQFP Pin

Number

I/O, Type

Description

PEM0

PEM1

I, LVTTL

Pre-emphasis Control Inputs (affects all Channels)

TDI

I, LVTTL

Test Data Input to support IEEE 1149.1 features

TDO

TMS

TCK

O, LVTTL Test Data Output to support IEEE 1149.1 features

I, LVTTL

Test Mode Select to support IEEE 1149.1 features

Test Clock to support IEEE 1149.1 features

Test Reset to support IEEE 1149.1 features

TRST

POWER

V_DD

3, 4, 5, 7, 10, 11, 28, 29, 32, 33

8, 9, 17, 18, 23, 24, 37, 38, 43, 44

6, 30, 31, 36

I, Power

V_DD= 3.3V, ±5%

Ground

GND

N/C

No Connect

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

(1)

Absolute Maximum Ratings

Supply Voltage (V_DD

)

−0.3V to +4.0V

-0.3V to (V_DD+0.3V)

+40 mA

CMOS Input Voltage

LVDS Input Voltage

(2)

LVDS Output Voltage

LVDS Output Short Circuit Current

Junction Temperature

+150°C

Storage Temperature

−65°C to +150°C

260°C

Lead Temperature (Solder, 4sec)

Max Pkg Power Capacity @ 25°C

1.64W

Thermal Resistance (θ_JA

)

76°C/W

Package Derating above +25°C

13.2mW/°C

12kV

ESD Last Passing Voltage (LVDS output

pins)

HBM, 1.5kΩ, 100pF

EIAJ, 0Ω, 200pF

HBM, 1.5kΩ, 100pF

EIAJ, 0Ω, 200pF

250V

ESD Last Passing Voltage (All other pins)

8kV

250V

(1) Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,

without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. TI

does not recommend operation of products outside of recommended operation conditions.

(2) V_IDmax < 2.4V

Recommended Operating Conditions

Supply Voltage (V_DD

)

3.15V to 3.45V

0V to V_DD

(1)

Input Voltage (V_I)

Output Voltage (V_O)

0V to V_DD

Operating Temperature (T_A) Industrial

(1) V_IDmax < 2.4V

−40°C to +85°C

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SNLS182P –MAY 2005–REVISED APRIL 2013

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Units

Electrical Characteristics

Over recommended operating supply and temperature ranges unless other specified.

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

LVTTL DC SPECIFICATIONS (PWDN, PEM0, PEM1, TDI, TDO, TCK, TMS, TRST)

V_IH

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

2.0

GND

−10

-40

V_DD

0.8

V_IL

I_IH

V_IN= V_DD= V_DDMAX

V_IN= V_SS, V_DD= V_DDMAX

TDI, TMS, TRST

+10

-200

µA

I_IL

I_ILR

C_IN1

C_OUT1

V_CL

V_OH

Any Digital Input Pin to V_SS

Any Digital Output Pin to V_SS

I_CL= −18 mA

3.5

Output Capacitance

5.5

Input Clamp Voltage

−1.5

2.4

−0.8

High Level Output Voltage

(TDO)

I_OH= −12 mA, V_DD= 3.15 V

I_OH= −100 µA, V_DD= 3.15 V

I_OL= 12 mA, V_DD= 3.15 V

I_OL= 100 µA, V_DD= 3.15 V

TDO

V_DD-0.2

V_OL

Low Level Output Voltage

(TDO)

0.5

0.2

I_OS

I_OZ

Output Short Circuit Current

Output TRI-STATE Current

−15

−10

−125

+10

µA

TDO

LVDS INPUT DC SPECIFICATIONS (INn±)

V_TH

Differential Input High Threshold

V_CM= 0.8V to 3.4V,

V_DD= 3.45V

100

(2)

V_TL

Differential Input Low Threshold

V_CM= 0.8V to 3.4V,

V_DD= 3.45V

−100

(2)

V_ID

Differential Input Voltage

Common Mode Voltage Range

Input Capacitance

V_CM= 0.8V to 3.4V, V_DD= 3.45V

V_ID= 150 mV, V_DD= 3.45V

IN+ or IN− to V_SS

100

2400

3.40

V_CMR

C_IN2

I_IN

0.05

5.2

µA

Input Current

V_IN= 3.45V, V_DD= V_DDMAX

V_IN= 0V, V_DD= V_DDMAX

−10

+10

LVDS OUTPUT DC SPECIFICATIONS (OUTn±)

V_OD

Differential Output Voltage,

0% Pre-emphasis

R_L= 100Ω external resistor between OUT+ and

OUT−

250

500

600

(2)

ΔV_OD

Change in V_ODbetween

Complementary States

-35

1.05

-35

1.475

(3)

V_OS

Offset Voltage

1.18

ΔV_OS

Change in V_OSbetween

Complementary States

I_OS

Output Short Circuit Current

Output Capacitance

OUT+ or OUT− Short to GND

−60

−90

C_OUT2

OUT+ or OUT− to GND when TRI-STATE

5.5

SUPPLY CURRENT (Static)

I_CC

Supply Current

All inputs and outputs enabled and active,

terminated with external differential load of 100Ω

between OUT+ and OUT-, 0% pre-emphasis

117

2.7

140

I_CCZ

Supply Current - Power Down

Mode

PWDN = L, 0% pre-emphasis

SWITCHING CHARACTERISTICS—LVDS OUTPUTS

t_LHTDifferential Low to High Transition Use an alternating 1 and 0 pattern at 200 Mb/s,

210

300

(4)

Time

measure between 20% and 80% of V_OD.

t_HLT

Differential High to Low Transition

Time

(1) Typical parameters are measured at V_DD= 3.3V, T_A= 25°C. They are for reference purposes, and are not production-tested.

(2) Differential output voltage V_ODis defined as ABS(OUT+–OUT−). Differential input voltage V_IDis defined as ABS(IN+–IN−).

(3) Output offset voltage V_OSis defined as the average of the LVDS single-ended output voltages at logic high and logic low states.

(4) Not production tested. Specified by a statistical analysis on a sample basis at the time of characterization.

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SNLS182P –MAY 2005–REVISED APRIL 2013

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless other specified.

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t_PLHD

Differential Low to High

Propagation Delay

Use an alternating 1 and 0 pattern at 200 Mb/s,

measure at 50% V_ODbetween input to output.

2.0

3.2

t_PHLD

Differential High to Low

Propagation Delay

2.0

3.2

(4)

t_SKD1

t_SKCC

Pulse Skew

|t_PLHD–t_PHLD|

Output Channel to Channel Skew Difference in propagation delay (t_PLHDor t_PHLD

)

125

(4)

among all output channels.

(4)

t_SKP

t_JIT

Part to Part Skew

Jitter (0% Pre-emphasis)

Common edge, parts at same temp and V_CC

1.1

1.5

(5)

(6)

RJ - Alternating 1 and 0 at 750 MHz

1.1

psrms

psp-p

(7)

DJ - K28.5 Pattern, 1.5 Gbps

(8)

TJ - PRBS 2²³-1 Pattern, 1.5 Gbps

t_ON

LVDS Output Enable Time

LVDS Output Disable Time

Time from PWDN to OUT± change from TRI-STATE

to active.

300

t_OFF

Time from PWDN to OUT± change from active to

TRI-STATE.

SWITCHING CHARACTERISTICS—SCAN FEATURES

f_MAX

t_S

Maximum TCK Clock Frequency

TDI to TCK, H or L

R_L= 500Ω,

C_L= 35 pF

25.0

3.0

0.5

2.5

0.5

10.0

2.5

1.0

MHz

t_H

TDI to TCK, H or L

t_S

TMS to TCK, H or L

t_H

TMS to TCK, H or L

t_W

TCK Pulse Width, H or L

TRST Pulse Width, L

t_W

t_REC

Recovery Time, TRST to TCK

(5) Jitter is not production tested, but specified through characterization on a sample basis.

(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V_ID= 500mV, 50%

duty cycle at 750MHz, t_r= t_f= 50ps (20% to 80%).

(7) Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = V_ID= 500mV, K28.5

pattern at 1.5 Gbps, t_r= t_f= 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).

(8) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been

subtracted. The input voltage = V_ID= 500mV, 2²³-1 PRBS pattern at 1.5 Gbps, t_r= t_f= 50ps (20% to 80%).

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SCAN90004

SNLS182P –MAY 2005–REVISED APRIL 2013

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FEATURE DESCRIPTIONS

INTERNAL TERMINATIONS

The SCAN90004 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω

resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the

device. The LVDS outputs also contain an integrated 100Ω ohm termination resistor, this resistor is used to

reduce the effects of Near End Crosstalk (NEXT) and does not take the place of the 100 ohm termination at the

inputs to the receiving device. The integrated terminations improve signal integrity and decrease the external

component count resulting in space savings.

OUTPUT CHARACTERISTICS

The output characteristics of the SCAN90004 have been optimized for point-to-point backplane and cable

applications, and are not intended for multipoint or multidrop signaling.

POWERDOWN MODE

The PWDN input activates a hardware powerdown mode. When the powerdown mode is active (PWDN=L), all

input and output buffers and internal bias circuitry are powered off and disabled. Outputs are tri-stated in

powerdown mode. JTAG Circuitry is active per the IEEE standard, but does not switch unless TCK is toggling.

When exiting powerdown mode, there is a delay associated with turning on bandgap references and input/output

buffer circuits as indicated in the LVDS Output Switching Characteristics

Upon asserting the power down function (PWDN = Low), and if the Pre-emphasis feature is enable, it is possible

for the driver output to source current for a short amount of time lifting the output common mode to V_DD. To

prevent this occurrence, a load discharge pull down path can be used on either output (1 kΩ to ground

recommended). Alternately, a commonly deployed external failsafe network will also provide this path (see

INPUT FAILSAFE BIASING). The occurrence of this is application dependant, and parameters that will affect if

this is of concern include: AC coupling, use of the powerdown feature, presence of the discharge path, presence

of the failsafe biasing, the usage of the pre-emphasis feature, and input characteristics of the downstream LVDS

Receiver.

PRE-EMPHASIS

Pre-emphasis dramatically reduces ISI jitter from long or lossy transmission media. Two pins are used to select

the pre-emphasis level for all outputs: off, low, medium, or high.

Table 1. Pre-emphasis Control Selection Table

PEM1

PEM0

Pre-Emphasis

Off

Low

Medium

High

INPUT FAILSAFE BIASING

Failsafe biasing of the LVDS link should be considered if the downstream Receiver is ON and enabled when the

source is in TRI-STATE, powered off, or removed. This will set a valid known input state to the active receiver.

This is accomplished by using a pull up resistor to V_DDon the ‘plus’ line, and a pull down resistor to GND on the

‘minus’ line. Resistor values are in the 750 Ω to several k Ω range. The exact value depends upon the desired

common mode bias point, termination resistor(s) and desired input differential voltage setting. Please refer to

application note AN-1194 (SNLA051) “Failsafe Biasing of LVDS interfaces” for more information and a general

discussion.

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SNLS182P –MAY 2005–REVISED APRIL 2013

Design-for-Test (DfT) Features

IEEE 1149.1 (JTAG) SUPPORT

The SCAN90004 supports a fully compliant IEEE 1149.1 interface. The Test Access Port (TAP) provides access

to boundary scan cells at each LVTTL I/O on the device for interconnect testing. Differential pins are included in

the same boundary scan chain but instead contain IEEE1149.6 cells. IEEE1149.6 is the improved IEEE standard

for testing high-speed differential signals.

Refer to the BSDL file located on TI’s website for the details of the SCAN90004 IEEE 1149.1 implementation.

IEEE 1149.6 SUPPORT

AC-coupled differential interconnections on very high speed (1+ Gbps) data paths are not testable using

traditional IEEE 1149.1 techniques. The IEEE 1149.1 structures and methods are intended to test static (DC-

coupled), single ended networks. IEEE 1149.6 is targeted for the testing of high-speed differential (including AC

coupled) networks. The SCAN90004 includes circuitry to support AC-coupled testing on all differential inputs and

outputs and offers limited test capability. The limitations are due to several application specific factors (board

layout, capacitor value, data rate etc.), and also IO compliance (LVDS links in general are DC coupled). The

SCAN90004 has not been tested for full compliance or full compatibility to the IEEE1149.6 standard. Testing of

the device in the targeted application with the appropriate JTAG software will determine what extent of IEEE

1149.6 support is provided by the device.

FAULT INSERTION

Fault Insertion is a technique used to assist in the verification and debug of diagnostic software. During system

testing faults are "injected" to simulate hardware failure and thus help verify the monitoring software can detect

and diagnose these faults. In the SCAN90004 an IEEE1149.1 "stuck-at" instruction can create a stuck-at

condition, either high or low, on any pin or combination of pins. A more detailed description of the stuck-at

feature can be found in TI Applications note AN-1313 (SNLA060).

Application Information

INPUT INTERFACING

The SCAN90004 accepts differential signals and allow simple AC or DC coupling. With a wide common mode

range, the SCAN90004 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The

following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the

SCAN90004 inputs are internally terminated with a 100Ω resistor.

LVDS

Driver

SCAN90004

Receiver

100W Differential T-Line

OUT+

IN+

100W

IN-

OUT-

Figure 3. Typical LVDS Driver DC-Coupled Interface to SCAN90004 Input

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CML3.3V or CML2.5V

Driver

SCAN90004

Receiver

50W

100W Differential T-Line

OUT+

OUT-

IN+

IN-

100W

Figure 4. Typical CML Driver DC-Coupled Interface to SCAN90004 Input

LVPECL

Driver

LVDS

Receiver

100W Differential T-Line

IN+

IN-

OUT+

100W

OUT-

150-250W

Figure 5. Typical LVPECL Driver DC-Coupled Interface to SCAN90004 Input

OUTPUT INTERFACING

The SCAN90004 outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to

most common differential receivers. Figure 6 illustrates typical DC-coupled interface to common differential

receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a

common mode input range that can accommodate LVDS compliant signals, it is recommended to check

respective receiver's data sheet prior to implementing the suggested interface implementation.

SCAN90004

Driver

Differential

Receiver

100W Differential T-Line

OUT+

IN+

CML or

LVPECL or

LVDS

100W

IN-

OUT-

Figure 6. Typical SCAN90004 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver

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SNLS182P –MAY 2005–REVISED APRIL 2013

Typical Performance Characteristics

Power Supply Current

Total Jitter (T_J)

vs.

Bit Data Rate

vs.

Bit Data Rate

350

300

250

200

150

100

120

100

Clock, Max PRE

PRBS-23, Max PRE

VCM = 0.25V

VCM = 2.4V

VCM = 1.2V

Clock, 0% PRE

PRBS-23, 0% PRE

VCM = 0.5V

VCM = 3.05V

1.5

0.25

0.5

0.75

1.0

1.25

1.5

0.5

1.0

2.0

BIT DATA RATE (Gbps)

Dynamic power supply current was measured while

running a clock or PRBS 2²³-1 pattern

with all 4 channels active.

Total Jitter measured at 0V differential while

running a PRBS 2²³-1 pattern

with a single channel active.

V_CC= 3.3V, T_A= +25°C, V_ID= 0.5V, V_CM= 1.2V

V_CC= 3.3V, T_A= +25°C, V_ID= 0.5V, 0% Pre-emphasis

Figure 7.

Figure 8.

Total Jitter (U.I.)

vs.

Bit Data Rate

SCAN90004 as Driver

Total Jitter (U.I.)

vs.

Bit Data Rate

SCAN90004 as Receiver

Total Jitter measured while SCAN90004 output is

driving a PRBS 2⁷-1 NRZ pattern

with a single active channel across a Belden 1700A cable.

V_CC= 3.3V, T_A= +25°C, V_ID= 0.5V, 0% Pre-emphasis.

Data measured at end of specified cable length.

Total Jitter measured at SCAN90004 receiver outputs

after receiving a PRBS 2⁷-1 NRZ pattern

over the specified cable length.

V_CC= 3.3V, T_A= +25°C, V_ID= 0.5V,

data collected at receiver outputs,

receiver located at end of specified Belden 1700A cable length.

Figure 9.

Figure 10.

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Typical Performance Characteristics (continued)

Total Jitter (T_J)

Positive Edge Transition

vs.

Pre-emphasis Level

vs.

Temperature

100 mV/Div

100%

50%

25%

200 ps/Div

-40 -20

100

TEMPERATURE (°C)

Total Jitter measured at 0V differential

while running a PRBS 2²³-1 pattern

with a single channel active.

V_CC= 3.3V, V_ID= 0.5V, V_CM= 1.2V, 1.5

Gbps data rate, 0% Pre-emphasis

Figure 11.

Figure 12.

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REVISION HISTORY

Changes from Revision O (April 2013) to Revision P

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 10

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PACKAGE OPTION ADDENDUM

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10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SCAN90004TVS/NOPB

ACTIVE

TQFP

PFB

250

RoHS & Green

Level-3-260C-168 HR

-40 to 85

SCAN

90004TVS

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

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Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

Name

Type

(mm) (µm) (mm) (mm) (mm)

SCAN90004TVS/NOPB

PFB

TQFP

250

10 x 25

150

315 135.9 7620 12.2

11.1 11.25

Pack Materials-Page 1

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

0,08

0,13 NOM

5,50 TYP

7,20

Gage Plane

6,80

9,20

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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SCAN90004 [TI]

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