SCAN90CP02VY/NOPB [TI]
具有预加重功能和 IEEE 1149.6 的 1.5Gbps 2x2 LVDS 交叉点开关 | NEY | 32 | -40 to 85;
| 型号： | SCAN90CP02VY/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有预加重功能和 IEEE 1149.6 的 1.5Gbps 2x2 LVDS 交叉点开关 | NEY | 32 | -40 to 85 开关 输出元件 |
| 文件： | 总23页 (文件大小：728K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SCAN90CP02
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SNLS168M –JANUARY 2004–REVISED APRIL 2013
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6
Check for Samples: SCAN90CP02
1
FEATURES
DESCRIPTION
The SCAN90CP02 is a 1.5 Gbps 2 x 2 LVDS
crosspoint switch. High speed data paths and flow-
through pinout minimize internal device jitter, while
configurable 0/25/50/100% pre-emphasis overcomes
external ISI jitter effects of lossy backplanes and
cables. The differential inputs interface to LVDS and
Bus LVDS signals such as those on TI's 10-, 16-, and
18- bit Bus LVDS SerDes, as well as CML and
LVPECL. The SCAN90CP02 can also be used with
ASICs and FPGAs. The non-blocking crosspoint
architecture is pin-configurable as a 1:2 clock or data
splitter, 2:1 redundancy mux, crossover function, or
dual buffer for signal booster and stub hider
applications.
2
•
1.5 Gbps per Channel
•
Low Power: 70 mA in Dual Repeater Mode
@1.5 Gbps
•
•
Low Output Jitter
Configurable 0/25/50/100% Pre-Emphasis
Drives Lossy Backplanes and Cables
•
Non-Blocking Architecture Allows 1:2 Splitter,
2:1 Mux, Crossover, and Dual Buffer
Configurations
•
•
Flow-Through Pinout
LVDS/BLVDS/CML/LVPECL Inputs, LVDS
Outputs
Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry
•
•
•
IEEE 1149.1 and 1149.6 Compliant
Single 3.3V Supply
supports
LVTTL/CMOS
testability
and
of
both
single-ended
LVDS PCB
differential
Separate Control of Inputs and Outputs Allows
for Power Savings
interconnect. The 3.3V supply, CMOS process, and
LVDS I/O ensure high performance at low power over
the entire industrial -40 to +85°C temperature range.
•
•
Industrial -40 to +85°C Temperature Range
28-Lead UQFN Package, or 32-Lead LQFP
Package
Block Diagram
PEM00 PEM01
PEM10 PEM11
Channel 0
Channel 1
Pre-emphasis
Pre-emphasis
IN0+
IN0-
OUT0+
OUT0-
OUT1+
OUT1-
IN1+
IN1-
TDI
TDO
TCK
SEL0
SEL1
EN0
Control
Logic
TAP
TMS
TRST
EN1
Figure 1. SCAN90CP02 Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
SCAN90CP02
SNLS168M –JANUARY 2004–REVISED APRIL 2013
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PIN DESCRIPTIONS
UQFN
Pin
Number Number
LQFP
Pin
Pin
Name
I/O, Type
Description
DIFFERENTIAL INPUTS COMMON TO ALL MUXES
IN0+
IN0−
9
10
9
10
I, LVDS
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
compatible.
IN1+
IN1−
12
13
13
14
I, LVDS
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
compatible.
SWITCHED DIFFERENTIAL OUTPUTS
OUT0+
OUT0−
27
26
32
31
O, LVDS
Inverting and non-inverting differential outputs. OUT0± can be connected to any one
pair IN0±, or IN1±. LVDS compatible(1)
.
OUT1+
OUT1−
24
23
28
27
O, LVDS
Inverting and non-inverting differential outputs. OUT1± can be connected to any one
pair IN0±, or IN1±. LVDS compatible(1)
.
DIGITAL CONTROL INTERFACE
SEL0,
SEL1
6
5
7
6
I, LVTTL
I, LVTTL
I, LVTTL
I, LVTTL
Select Control Inputs
Output Enable Inputs
EN0, EN1
7
15
8
17
PEM00,
PEM01
4
3
4
3
Channel 0 Output Pre-emphasis Control Inputs
Channel 1 Output Pre-emphasis Control Inputs
PEM10,
PEM11
2
1
2
1
TDI
19
20
22
23
21
19
24
I, LVTTL
O, LVTTL
I, LVTTL
I, LVTTL
I, LVTTL
Test Data Input to support IEEE 1149.1 features
Test Data Output to support IEEE 1149.1 features
Test Mode Select to support IEEE 1149.1 features
Test Clock to support IEEE 1149.1 features
Test Reset to support IEEE 1149.1 features
Not Connected
TDO
TMS
TCK
18
17
TRST
N/C
21
8, 28
POWER
VDD
11, 14,
16, 22,
25
12, 16,
18, 25,
29
I, Power
VDD = 3.3V ±0.3V. At least 4 low ESR 0.01 µF bypass capacitors should be
connected from VDD to GND plane.
GND
See(2)
5, 11, 15,
20, 26,
30
Ground reference to LVDS and CMOS circuitry.
For the UQFN package, the DAP is used as the primary GND connection to the
device. The DAP is the exposed metal contact at the bottom of the UQFN-28
package. It should be connected to the ground plane with at least 4 vias for optimal
AC and thermal performance.
(1) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN90CP02 device have
been optimized for point-to-point backplane and cable applications.
(2) Note that for the UQFN package GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the
UQFN package.
2
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Connection Diagrams
7
6
5
4
3
2
1
32 31 30 29 28 27 26 25
PEM11
PEM10
PEM01
PEM00
GND
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
TRST
TDO
TDI
N/C
IN0+
IN0-
VDDA
IN1+
IN1-
VDD2
N/C
8
28
27
26
25
24
23
22
OUT0+
OUT0-
VDDA
9
10
11
12
13
14
TMS
GND
TCK
DAP
(GND)
OUT1+
OUT1-
VDD2
SEL1
SEL0
V
DD1
EN0
EN1
9 10 11 12 13 14 15 16
15 16 17 18 19 20 21
Figure 2. UQFN Top View
DAP = GND
Figure 3. LQFP Top View
CONFIGURATION SELECT TRUTH TABLE(1)
SEL0
SEL1
EN0
0
EN1
OUT0
IN0
IN0
IN1
IN1
IN0
IN1
PD
OUT1
IN0
IN1
IN0
IN1
PD
Mode
0
0
1
1
0
1
0
0
X
0
1
1
1
0
1
0
1
1
1
0
1
X
0
0
0
1
0
1:2 Splitter (IN1 powered down)
0
0
Dual Channel Repeater
Dual Channel Switch
0
0
0
0
1:2 Splitter (IN0 powered down)
0
1
Single Channel Repeater (Channel 1 powered down)
Single Channel Switch (IN0 and OUT1 powered down)
Single Channel Switch (IN1 and OUT0 powered down)
Single Channel Repeater (Channel 0 powered down)
Both Channels in Power Down Mode
Invalid State(2)
0
1
PD
1
0
IN0
IN1
PD
1
0
PD
1
1
PD
0
1
0
1
Invalid State(2)
Invalid State(2)
Invalid State(2)
1
0
1
0
(1) PD = Power Down mode to minimize power consumption
X = Don't Care
(2) Entering these states is not forbidden, however device operation is not defined in these states.
PRE-EMPHASIS
The pre-emphasis is used to compensate for long or lossy transmission media. Separate pins are provided for
each output to minimize power consumption. Pre-emphasis is programmable to be off or to preset values per
Table 1.
Output Characteristics
The output characteristics of the SCAN90CP02 device have been optimized for point-to-point backplane and
cable applications.
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Table 1. Pre-emphasis Control Selection Table
Channel 0
Channel 1
Pre-emphasis
PEM01
PEM00
PEM11
PEM10
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0%
25%
50%
100%
Applications Information
Dual Channel Repeater
(SEL0=0, SEL1=1, EN0=0, EN1=0)
1:2 Splitter
(SEL0=0, SEL1=0, EN0=0, EN1=0)
OUT0+
OUT0+
OUT0-
IN0+
IN0-
IN0+
IN0-
OUT0-
OUT1+
OUT1-
OUT1+
OUT1-
IN1+
IN1-
IN1+
IN1-
1:2 Splitter
Dual Channel Switch
(SEL0=1, SEL1=1, EN0=0, EN1=0)
(SEL0=1, SEL1=0, EN0=0, EN1=0)
OUT0+
OUT0-
OUT0+
OUT0-
IN0+
IN0-
IN0+
IN0-
OUT1+
OUT1-
OUT1+
OUT1-
IN1+
IN1-
IN1+
IN1-
Single Channel Repeater
(SEL0=0, SEL1=1, EN0=0, EN1=1)
Single Channel Crossover Switch
(SEL0=0, SEL1=0, EN0=1, EN1=0)
OUT0+
OUT0-
OUT0+
OUT0-
IN0+
IN0-
IN0+
IN0-
OUT1+
OUT1-
OUT1+
OUT1-
IN1+
IN1-
IN1+
IN1-
Single Channel Crossover Switch
(SEL0=1, SEL1=1, EN0=0, EN1=1)
Single Channel Repeater
(SEL0=0, SEL1=1, EN0=1, EN1=0)
OUT0+
OUT0-
OUT0+
OUT0-
IN0+
IN0-
IN0+
IN0-
OUT1+
OUT1-
OUT1+
OUT1-
IN1+
IN1-
IN1+
IN1-
Figure 4. SCAN90CP02 Configuration Select Decode
4
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage (VDD
)
−0.3V to +4.0V
−0.3V to (VDD +0.3V)
−0.3V to +3.6V
−0.3V to +3.6V
40mA
CMOS Input Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Current
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4sec.)
Maximum Package Power Dissipation at 25°C
UQFN-28
4.31 W
LQFP-32
1.47 W
Derating above 25°C
Thermal Resistance, θJA
ESD Rating
UQFN-28
34.5 mW/°C
11.8 mW/°C
29°C/W
LQFP-32
UQFN-28
LQFP-32
85°C/W
HBM, 1.5 kΩ, 100 pF
EIAJ, 0Ω, 200 pF
6.5 kV
>250V
(1) “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be specified. They are not meant to imply that
the device should be operated at these limits.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
RECOMMENDED OPERATING CONDITIONS
Min
3.0
0
Typ
Max
3.6
3.6
85
Unit
V
Supply Voltage (VDD– GND)
Receiver Input Voltage
3.3
V
Operating Free Air Temperature
Junction Temperature
−40
25
°C
°C
150
ELECTRICAL CHARACTERISTICS
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
LVTTL DC SPECIFICATIONS (SEL0, SEL1, EN1, EN2, PEM00, PEM01, PEM10, PEM11, TDI, TCK, TMS, TRST)
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Low Level Input Current
Input Capacitance
2.0
GND
−10
−10
-40
VDD
0.8
V
V
VIL
IIH
VIN = VDD = VDDMAX
VIN = VSS, VDD = VDDMAX
TDI, TMS, TRST
+10
+10
-200
µA
µA
µA
pF
pF
V
IIL
IILR
CIN1
COUT1
VCL
VOH
Any Digital Input Pin to VSS
Any Digital Output Pin to VSS
ICL = −18 mA
3.5
5.5
Output Capacitance
Input Clamp Voltage
−1.5
2.4
−0.8
High Level Output Voltage
(TDO)
IOH = −12 mA, VDD = 3.0 V
IOH = −100 µA, VDD = 3.0 V
IOL = 12 mA, VDD = 3.0 V
IOL = 100 µA, VDD = 3.0 V
TDO
V
VDD-0.2
V
VOL
Low Level Output Voltage
(TDO)
0.5
0.2
V
V
IOS
Output Short Circuit Current
-15
-125
mA
(1) Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested.
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Units
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
LVDS INPUT DC SPECIFICATIONS (IN0±, IN1±)
VTH
VTL
VID
Differential Input High Threshold(2)
Differential Input Low Threshold
Differential Input Voltage
Common Mode Voltage Range
Input Capacitance
VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V
VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V
VCM = 0.8V to 3.55V, VDD = 3.6V
VID = 150 mV, VDD = 3.6V
0
0
100
mV
mV
mV
V
−100
100
VCMR
CIN2
IIN
0.05
3.55
IN+ or IN− to VSS
3.5
pF
µA
µA
Input Current
VIN = 3.6V, VDD = VDDMAX or 0V
VIN = 0V, VDD = VDDMAX or 0V
−10
−10
+10
+10
LVDS OUTPUT DC SPECIFICATIONS (OUT0±, OUT1±)
VOD
Differential Output Voltage,
0% Pre-emphasis(2)
RL = 100Ω between OUT+ and OUT−
250
400
575
mV
ΔVOD
Change in VOD between
Complementary States
Offset Voltage(3)
−35
1.09
−35
35
1.475
35
mV
V
VOS
1.25
ΔVOS
Change in VOS between
Complementary States
mV
IOS
Output Short Circuit Current, One
Complementary Output
OUT+ or OUT− Short to GND
−60
-90
mA
pF
COUT2
Output Capacitance
OUT+ or OUT− to GND when TRI-
STATE
5.5
SUPPLY CURRENT (Static)
ICC0
Supply Current
All inputs and outputs enabled and
active, terminated with differential load of
100Ω between OUT+ and OUT-.
42
22
60
30
mA
mA
ICC1
Supply Current - one channel
powered down
Single channel crossover switch or single
channel repeater modes (1 channel
active, one channel in power down mode)
ICC2
ICCZ
Supply Current - one input powered
down
Splitter mode (One input powered down,
both outputs active)
30
40
mA
mA
TRI-STATE Supply Current
Both input/output Channels in Power
Down Mode
1.4
2.5
SWITCHING CHARACTERISTICS—LVDS OUTPUTS (Figure 5, Figure 6)
tLHT
Differential Low to High Transition
Time
Use an alternating 1 and 0 pattern at 200
Mb/s, measure between 20% and 80% of
70
50
150
135
2.4
215
180
3.5
ps
ps
ns
VOD
.
tHLT
Differential High to Low Transition
Time
tPLHD
tPHLD
Differential Low to High Propagation Use an alternating 1 and 0 pattern at 200
Delay
0.5
0.5
Mb/s, measure at 50% VOD between
input to output.
Differential High to Low Propagation
Delay
2.4
55
3.5
ns
ps
tSKD1
tSKCC
Pulse Skew
|tPLHD–tPHLD
|
120
Output Channel to Channel Skew
Difference in propagation delay (tPLHD or
tPHLD) among all output channels in
Splitter mode (any one input to all
outputs).
0
130
315
ps
(2) Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
(3) Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Jitter (0% Pre-emphasis)(4)
Conditions
RJ - Alternating 1/0 @ 750 MHz(5)
DJ - K28.5 Pattern
Min
Typ(1)
1.4
Max
2.5
Units
psrms
psp-p
psp-p
psp-p
psp-p
tJIT
LQFP
UQFN
LQFP
UQFN
110
42
140
75
1.5 Gbps(6)
TJ - PRBS 223-1 Pattern
1.5 Gbps(7)
113
93
148
126
tON
LVDS Output Enable Time
LVDS Output Disable Time
Time from ENx to OUT± change from
TRI-STATE to active.
50
110
5
150
12
ns
ns
tOFF
tSW
Time from ENx to OUT± change from
active to TRI-STATE.
LVDS Switching Time
SELx to OUT±
Time from configuration select (SELx) to
new switch configuration effective for
OUT±.
110
150
ns
(4) Jitter is not production tested, but specified through characterization on a sample basis.
(5) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50%
duty cycle at 750MHz, tr = tf = 50ps (20% to 80%).
(6) Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5
pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
(7) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been
subtracted. The input voltage = VID = 500mV, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%).
SCAN CIRCUITRY TIMING REQUIREMENTS
Symbol
fMAX
tS
Parameter
Conditions
Min
25.0
1.0
Typ
Max
Units
MHz
ns
Maximum TCK Clock Frequency
TDI to TCK, H or L
RL = 500Ω,
CL = 35 pF
tH
TDI to TCK, H or L
2.0
ns
tS
TMS to TCK, H or L
TMS to TCK, H or L
TCK Pulse Width, H or L
TRST Pulse Width, L
Recovery Time, TRST to TCK
2.0
ns
tH
1.5
ns
tW
10.0
2.5
ns
tW
ns
tREC
2.0
ns
TIMING DIAGRAMS
IN+
VOS=1.2V typical
IN-
IN+
VID
IN-
Figure 5. LVDS Signals
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(OUT+ - OUT-)
80%
20%
80%
0V
20%
tLHT
tHLT
OUT+
OUT-
VOD
Figure 6. LVDS Output Transition Time
(IN+ - IN-)
0.0V
tPLHD
tPHLD
(OUT+ - OUT-)
0.0V
Figure 7. LVDS Output Propagation Delay
Load Configuration "A"
Load Configuration "B"
LOAD or
SELx
tSW
tSW
OUT±
Configuration "B"
Configuration "A"
tOFF
tON
50%
50%
50%
OUT+
OUT-
1.2V
1.2V
50%
Figure 8. Configuration and Output Enable/Disable Timing
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Input Interfacing
The SCAN90CP02 accepts differential signals and allow simple AC or DC coupling. With a wide common mode
range, the SCAN90CP02 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML).
The following three figures illustrate typical DC-coupled interface to common differential drivers.
LVDS
Driver
SCAN90CP02
Receiver
100W Differential T-Line
OUT+
OUT-
IN+
100W
IN-
Figure 9. Typical LVDS Driver DC-Coupled Interface to SCAN90CP02 Input
CML3.3V or CML2.5V
Driver
V
CC
SCAN90CP02
Receiver
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
100W
Figure 10. Typical CML Driver DC-Coupled Interface to SCAN90CP02 Input
LVPECL
Driver
LVDS
Receiver
100W Differential T-Line
IN+
IN-
OUT+
100W
OUT-
150-250W
150-250W
Figure 11. Typical LVPECL Driver DC-Coupled Interface to SCAN90CP02 Input
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Output Interfacing
The SCAN90CP02 outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to
most common differential receivers. Figure 12 illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accommodate LVDS compliant signals, it is recommended to check
respective receiver's data sheet prior to implementing the suggested interface implementation.
SCAN90CP02
Receiver
Differential
Receiver
100W Differential T-Line
IN+
OUT+
CML or
LVPECL or
LVDS
100W
IN-
OUT-
Figure 12. Typical SCAN90CP02 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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TYPICAL PERFORMANCE CHARACTERISTICS FOR UQFN PACKAGE
Power Supply Current vs. Bit Data Rate
Total Jitter (TJ) vs. Bit Data Rate
100
120
100
80
60
40
20
0
100% Pre-emphasis
VCM = 0.5V
90
80
70
60
50
40
VCM = 1.2V
50%
25%
VCM = 2.4V
VCM = 3.1V
0%
0.5
0.7
0.9
1.1
1.3
1.5
0.5
0.7
0.9
1.1
1.3
1.5
BIT DATA RATE (Gbps)
BIT DATA RATE (Gbps)
Dynamic power supply current was measured while running a PRBS Total Jitter measured at 0V differential while running a PRBS 223-1
223-1 pattern in dual channel repeater mode. VCC = 3.3V, TA = +25°C, pattern in single channel repeater mode. VCC = 3.3V, TA = +25°C, VID
VID = 0.5V, VCM = 1.2V
= 0.5V, 0% Pre-emphasis
Figure 13.
Figure 14.
Total Jitter (TJ) vs. Temperature
Positive Edge Transition vs. Pre-emphasis Level
120
115
110
105
100
95
100 mV/Div
100%
50%
25%
0%
90
85
80
200 ps/Div
75
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
Total Jitter measured at 0V differential while running a PRBS 223-1
pattern in dual channel repeater mode. VCC = 3.3V, VID = 0.5V, VCM
=
1.2V, 1.5 Gbps data rate, 0% Pre-emphasis
Figure 15.
Figure 16.
Copyright © 2004–2013, Texas Instruments Incorporated
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11
Product Folder Links: SCAN90CP02
SCAN90CP02
SNLS168M –JANUARY 2004–REVISED APRIL 2013
www.ti.com
DESIGN-FOR-TEST (DFT) FEATURES
IEEE 1149.1 SUPPORT
The SCAN90CP02 supports a fully compliant IEEE 1149.1 interface. The Test Access Port (TAP) provides
access to boundary scan cells at each LVTTL I/O on the device for interconnect testing. Differential pins are
included in the same boundary scan chain but instead contain IEEE1149.6 cells. IEEE1149.6 is the improved
IEEE standard for testing high-speed differential signals.
Refer to the BSDL file located on TI's website for the details of the SCAN90CP02 IEEE 1149.1 implementation.
IEEE 1149.6 SUPPORT
AC-coupled differential interconnections on very high speed (1+ Gbps) data paths are not testable using
traditional IEEE 1149.1 techniques. The IEEE 1149.1 structures and methods are intended to test static (DC-
coupled), single ended networks. IEEE1149.6 is specifically designed for testing high-speed differential, including
AC coupled networks.
The SCAN90CP02 is intended for high-speed signaling up to 1.5 Gbps and includes IEEE1149.6 on all
differential inputs and outputs.
FAULT INSERTION
Fault Insertion is a technique used to assist in the verification and debug of diagnostic software. During system
testing faults are "injected" to simulate hardware failure and thus help verify the monitoring software can detect
and diagnose these faults. In the SCAN90004 an IEEE1149.1 "stuck-at" instruction can create a stuck-at
condition, either high or low, on any pin or combination of pins.
A more detailed description of the stuck-at feature can be found in Texas Instruments Applications note AN-
1313(SNLA060).
12
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Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: SCAN90CP02
SCAN90CP02
www.ti.com
SNLS168M –JANUARY 2004–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision L (April 2013) to Revision M
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
Copyright © 2004–2013, Texas Instruments Incorporated
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13
Product Folder Links: SCAN90CP02
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SCAN90CP02SP/NOPB
SCAN90CP02VY/NOPB
ACTIVE
ACTIVE
UQFN
LQFP
NJD
NEY
28
32
1000 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
SCP02SP
SN
SCAN90
CP02VY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SCAN90CP02SP/NOPB UQFN
NJD
28
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
UQFN NJD 28
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
SCAN90CP02SP/NOPB
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
SCAN90CP02VY/NOPB
NEY
LQFP
32
250
9 X 24
150
322.6 135.9 7620 12.2
11.1 11.25
Pack Materials-Page 3
PACKAGE OUTLINE
NEY0032A
LQFP - 1.6 mm max height
SCALE 1.800
PLASTIC QUAD FLATPACK
7.1
6.9
B
32
25
PIN 1 ID
24
1
7.1
6.9
9.4
TYP
8.6
17
8
A
9
16
0.27
0.17
OPTIONAL:
SHARP CORNERS EXCEPT
PIN 1 ID CORNER
28X 0.8
4X 5.6
32X
0.2
C A B
SEE DETAIL A
1.6 MAX
C
SEATING PLANE
0.09-0.20
TYP
0.25
GAGE PLANE
(1.4)
0.1
0.15
0.05
0.75
0.45
0 -7
DETAIL
A
S
C
A
L
E
:
1
2
DETAIL A
TYPICAL
4219901/A 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
NEY0032A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
25
32
32X (1.6)
1
24
32X (0.4)
SYMM
(8.5)
28X (0.8)
8
17
(R0.05) TYP
9
16
(8.5)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219901/A 10/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
NEY0032A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
25
32
32X (1.6)
1
24
32X (0.4)
SYMM
(8.5)
28X (0.8)
8
17
(R0.05) TYP
16
9
(8.5)
SOLDER PASTE EXAMPLE
SCALE 8X
4219901/A 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
NJD0028A
SPA28A (Rev A)
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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