SCAN921224SLC [TI]
具有 IEEE 1149.1 测试访问的 20 至 66MHz 10 位解串器 | NZA | 49 | -40 to 85;
| 型号： | SCAN921224SLC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 IEEE 1149.1 测试访问的 20 至 66MHz 10 位解串器 | NZA | 49 | -40 to 85 测试 |
| 文件： | 总26页 (文件大小：1046K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SCAN921023, SCAN921224
www.ti.com
SNLS133D –JAN 2001–REVISED APRIL 2013
SCAN921023 and SCAN921224 20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
with IEEE 1149.1 (JTAG) and at-speed BIST
Check for Samples: SCAN921023, SCAN921224
1
FEATURES
DESCRIPTION
The SCAN921023 transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed
Bus LVDS serial data stream with embedded clock.
The SCAN921224 receives the Bus LVDS serial data
stream and transforms it back into a 10-bit wide
parallel data bus and recovers parallel clock. Both
devices are compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture
with the incorporation of the defined boundary-scan
test logic and test access port consisting of Test Data
Input (TDI), Test Data Out (TDO), Test Mode Select
(TMS), Test Clock (TCK), and the optional Test Reset
(TRST). IEEE 1149.1 features provide the designer or
test engineer access to the backplane or cable
interconnects and the ability to verify differential
signal integrity to enhance their system test strategy.
The pair of devices also features an at-speed BIST
mode which allows the interconnects between the
Serializer and Deserializer to be verified at-speed.
2
•
IEEE 1149.1 (JTAG) Compliant and At-Speed
BIST Test Mode
•
Clock Recovery From PLL Lock to Random
Data Patterns
•
•
Ensured Transition Every Data Transfer Cycle
Chipset (Tx + Rx) Power Consumption < 500
mW (typ) @ 66 MHz
•
Single Differential Pair Eliminates Multi-
Channel Skew
•
•
Flow-Through Pinout for Easy PCB Layout
660 Mbps Serial Bus LVDS Data Rate (at 66
MHz Clock)
•
10-bit Parallel Interface for 1 Byte Data Plus 2
Control Bits
•
•
•
Synchronization Mode and LOCK Indicator
Programmable Edge Trigger on Clock
The SCAN921023 transmits data over backplanes or
cable. The single differential pair data path makes
PCB design easier. In addition, the reduced cable,
PCB trace count, and connector size tremendously
reduce cost. Since one output transmits clock and
data bits serially, it eliminates clock-to-data and data-
to-data skew. The powerdown pin saves power by
reducing supply current when not using either device.
Upon power up of the Serializer, you can choose to
activate synchronization mode or allow the
Deserializer to use the synchronization-to-random-
data feature. By using the synchronization mode, the
Deserializer will establish lock to a signal within
specified lock times. In addition, the embedded clock
ensures a transition on the bus every 12-bit cycle.
This eliminates transmission errors due to charged
cable conditions. Furthermore, you may put the
SCAN921023 output pins into TRI-STATE to achieve
a high impedance state. The PLL can lock to
frequencies between 20 MHz and 66 MHz.
High Impedance on Receiver Inputs when
Power is Off
•
•
Bus LVDS Serial Output Rated for 27Ω Load
Small 49-Lead NFBGA Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
SCAN921023, SCAN921224
SNLS133D –JAN 2001–REVISED APRIL 2013
www.ti.com
BLOCK DIAGRAMS
Application
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SNLS133D –JAN 2001–REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The SCAN921023 and SCAN921224 are a 10-bit Serializer and Deserializer chipset designed to transmit data
over differential backplanes at clock speeds from 20 to 66 MHz. The chipset is also capable of driving data over
Unshielded Twisted Pair (UTP) cable.
The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two
passive states: Powerdown and TRI-STATE. In addition to the active and passive states, there are also test
modes for JTAG access and at-speed BIST.
The following sections describe each operation and passive state and the test modes.
Initialization
Initialization of both devices must occur before data transmission begins. Initialization refers to synchronization of
the Serializer and Deserializer PLL's to local clocks, which may be the same or separate. Afterwards,
synchronization of the Deserializer to Serializer occurs.
Step 1: When you apply VCC to both Serializer and/or Deserializer, the respective outputs enter TRI-STATE, and
on-chip power-on circuitry disables internal circuitry. When VCC reaches VCCOK (2.5V) the PLL in each device
begins locking to a local clock. For the Serializer, the local clock is the transmit clock (TCLK) provided by the
source ASIC or other device. For the Deserializer, you must apply a local clock to the REFCLK pin.
The Serializer outputs remain in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the
Serializer is now ready to send data or SYNC patterns, depending on the levels of the SYNC1 and SYNC2 inputs
or a data stream. The SYNC pattern sent by the Serializer consists of six ones and six zeros switching at the
input clock rate.
Note that the Deserializer LOCK output will remain high while its PLL locks to the incoming data or to SYNC
patterns on the input.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete initialization. The Deserializer will
lock to non-repetitive data patterns. However, the transmission of SYNC patterns enables the Deserializer to lock
to the Serializer signal within a specified time. See Figure 11.
The user's application determines control of the SYNC1 and SYNC 2 pins. One recommendation is a direct
feedback loop from the LOCK pin. Under all circumstances, the Serializer stops sending SYNC patterns after
both SYNC inputs return low.
When the Deserializer detects edge transitions at the Bus LVDS input, it will attempt to lock to the embedded
clock information. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK
is low, the Deserializer outputs represent incoming Bus LVDS data.
Data Transfer
After initialization, the Serializer will accept data from inputs DIN0–DIN9. The Serializer uses the TCLK input to
latch incoming Data. The TCLK_R/F pin selects which edge the Serializer uses to strobe incoming data.
TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the SYNC
inputs is high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored regardless of clock edge.
After determining which clock edge to use, a start and stop bit, appended internally, frame the data bits in the
register. The start bit is always high and the stop bit is always low. The start and stop bits function as the
embedded clock bits in the serial stream.
The Serializer transmits serialized data and clock bits (10+2 bits) from the serial data output (DO±) at 12 times
the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate is 66 × 12 = 792 Mega-bits-per-second.
Since only 10 bits are from input data, the serial “payload” rate is 10 times the TCLK frequency. For instance, if
TCLK = 66 MHz, the payload data rate is 66 × 10 = 660 Mbps. The data source provides TCLK and must be in
the range of 20 MHz to 66 MHz nominal.
The Serializer outputs (DO±) can drive a point-to-point connection or in limited multi-point or multi-drop
backplanes. The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and
SYNC2 are low. When DEN is driven low, the Serializer output pins will enter TRI-STATE.
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When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the
embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise
ROUT0–ROUT9 is invalid.
The ROUT0-ROUT9 pins use the RCLK pin as the reference to data. The polarity of the RCLK edge is controlled
by the RCLK_R/F input. See Figure 15.
ROUT(0-9), LOCK and RCLK outputs will drive a maximum of three CMOS input gates (15 pF load) with a 66
MHz clock.
Resynchronization
When the Deserializer PLL locks to the embedded clock edge, the Deserializer LOCK pin asserts a low. If the
Deserializer loses lock, the LOCK pin output will go high and the outputs (including RCLK) will enter TRI-STATE.
The user's system monitors the LOCK pin to detect a loss of synchronization. Upon detection, the system can
arrange to pulse the Serializer SYNC1 or SYNC2 pin to resynchronize. Multiple resynchronization approaches
are possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync
request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are provided for multiple control in a multi-drop
application. Sending sync patterns for resynchronization is desirable when lock times within a specific time are
critical. However, the Deserializer can lock to random data, which is discussed in the next section.
Random Lock Initialization and Resynchronization
The initialization and resynchronization methods described in their respective sections are the fastest ways to
establish the link between the Serializer and Deserializer. However, the SCAN921224 can attain lock to a data
stream without requiring the Serializer to send special SYNC patterns. This allows the SCAN921224 to operate
in “open-loop” applications. Equally important is the Deserializer's ability to support hot insertion into a running
backplane. In the open loop or hot insertion case, we assume the data stream is essentially random. Therefore,
because lock time varies due to data stream characteristics, we cannot possibly predict exact lock time.
However, please see Table 1 for some general random lock times under specific conditions. The primary
constraint on the “random” lock time is the initial phase relation between the incoming data and the REFCLK
when the Deserializer powers up. As described in the next paragraph, the data contained in the data stream can
also affect lock time.
If a specific pattern is repetitive, the Deserializer could enter “false lock” - falsely recognizing the data pattern as
the clocking bits. We refer to such a pattern as a repetitive multi-transition, RMT. This occurs when more than
one Low-High transition takes place in a clock cycle over multiple cycles. This occurs when any bit, except DIN
9, is held at a low state and the adjacent bit is held high, creating a 0-1 transition. In the worst case, the
Deserializer could become locked to the data pattern rather than the clock. Circuitry within the SCAN921224 can
detect that the possibility of “false lock” exists. The circuitry accomplishes this by detecting more than one
potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming
active until the potential “false lock” pattern changes. The false lock detect circuitry expects the data will
eventually change, causing the Deserializer to lose lock to the data pattern and then continue searching for clock
bits in the serial data stream. Graphical representations of RMT are shown in Figure 1. Please note that RMT
only applies to bits DIN0-DIN8.
Powerdown
When no data transfer occurs, you can use the Powerdown state. The Serializer and Deserializer use the
Powerdown state, a low power sleep mode, to reduce power consumption. The Deserializer enters Powerdown
when you drive PWRDN and REN low. The Serializer enters Powerdown when you drive PWRDN low. In
Powerdown, the PLL stops and the outputs enterTRI-STATE, which disables load current and reduces supply
current to the milliampere range. To exit Powerdown, you must drive the PWRDN pin high.
Before valid data exchanges between the Serializer and Deserializer, you must reinitialize and resynchronize the
devices to each other. Initialization of the Serializer takes 510 TCLK cycles. The Deserializer will initialize and
assert LOCK high until lock to the Bus LVDS clock occurs.
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SNLS133D –JAN 2001–REVISED APRIL 2013
TRI-STATE
The Serializer enters TRI-STATE when the DEN pin is driven low. This puts both driver output pins (DO+ and
DO−) into TRI-STATE. When you drive DEN high, the Serializer returns to the previous state, as long as all other
control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
When you drive the REN pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output pins
(ROUT0–ROUT9) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the state of the
PLL.
Table 1. Random Lock Times for the SCAN921224(1)
66 MHz
Units
μS
Maximum
Mean
18
3.0
0.43
μS
Minimum
Conditions:
μS
PRBS 215, VCC = 3.3V
(1) Difference in lock times are due to different starting points in the data
pattern with multiple parts.
Test Modes
In addition to the IEEE 1149.1 test access to the digital TTL pins, the SCAN921023 and SCAN921224 have two
instructions to test the LVDS interconnects. The first is EXTEST. This is implemented at LVDS levels and is only
intended as a go no-go test (e.g. missing cables). The second method is the RUNBIST instruction. It is an "at-
system-speed" interconnect test. It is executed in approximately 33mS with a system clock speed of 66MHz.
There are two bits in the RX BIST data register for notification of PASS/FAIL and TEST_COMPLETE. Pass
indicates that the BER (Bit-Error-Rate) is better than 10-7.
An important detail is that once both devices have the RUNBIST instruction loaded into their respective
instruction registers, both devices must move into the RTI state within 4K system clocks (At a SCLK of 66Mhz
and TCK of 1MHz this allows for 66 TCK cycles). This is not a concern when both devices are on the same scan
chain or LSP, however, it can be a problem with some multi-drop devices. This test mode has been simulated
and verified using TI's SCANSTA111.
Figure 1. DIN0 Held Low-DIN1 Held High Creates
an RMT Pattern
Figure 2. DIN4 Held Low-DIN5 Held High Creates
an RMT Pattern
Figure 3. DIN8 Held Low-DIN9 Held High Creates an RMT Pattern
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to +3.9V
−0.3V to +3.9V
10mS
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
Bus LVDS Receiver Input Voltage
Bus LVDS Driver Output Voltage
Bus LVDS Output Short Circuit Duration
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature
(Soldering, 4 seconds)
49L NFBGA
Maximum Package Power Dissipation Capacity @ 25°C Package:
Package Derating:
1.47 W
11.8 mW/°C above
+25°C
49L NFBGA
θja
85°C/W
ESD Rating
HBM
MM
>2kV
> 250V
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be specified. They are not meant to imply
that the devices should be operated at these limits. The table of ELECTRICAL CHARACTERISTICS specifies conditions of device
operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
RECOMMENDED OPERATING CONDITIONS
Min
3.0
−40
0
Nom
3.3
Max
3.6
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
Receiver Input Range
+25
+85
2.4
°C
V
Supply Noise Voltage (VCC
)
100 mVP-P
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SNLS133D –JAN 2001–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN)
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
GND
ICL = −18 mA
-0.86
±1
−1.5
+10
V
VIN = 0V or 3.6V
−10
μA
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to pins
ROUT, RCLK, LOCK = outputs)
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
GND
VCL
IIN
ICL = −18 mA
−0.62
±1
−1.5
+15
V
VIN = 0V or 3.6V
−10
-20
μA
μA
V
IILR
VOH
VOL
IOS
IOS
Input Current, TMS, TDI, TRST inputs VIN = 0V or 3.6V
-10
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
IOH = −9 mA
IOL = 9 mA
VOUT = 0V
2.2
3.0
VCC
0.5
GND
−15
-15
0.25
−47
-70
V
−85
-100
mA
mA
Output Short Circuit Current, TDO
output
IOZ
TRI-STATE Output Current
PWRDN or REN = 0.8V, VOUT = 0V or VCC
−10
200
1.05
±0.1
290
+10
μA
SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO+ and DO−)
VOD
Output Differential Voltage
(DO+)–(DO−)
RL = 27Ω, see Figure 20
mV
ΔVOD
VOS
Output Differential Voltage Unbalance
Offset Voltage
35
1.3
35
mV
V
1.1
4.8
ΔVOS
IOS
Offset Voltage Unbalance
Output Short Circuit Current
mV
D0 = 0V, DIN = High,PWRDN and DEN =
2.4V
−56
−90
mA
IOZ
IOX
TRI-STATE Output Current
Power-Off Output Current
PWRDN or DEN = 0.8V, DO = 0V or VCC
VCC = 0V, DO=0V or 3.6V
−10
−20
±1
±1
+10
+25
μA
μA
DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−)
VTH
VTL
IIN
Differential Threshold High Voltage
Differential Threshold Low Voltage
Input Current
VCM = +1.1V
+6
−12
±1
+50
mV
mV
μA
−50
−10
−10
VIN = +2.4V, VCC = 3.6V or 0V
VIN = 0V, VCC = 3.6V or 0V
+15
+10
±0.05
μA
SERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
ICCD
Serializer Supply Current
Worst Case
RL = 27Ω
f = 20 MHz
f = 66 MHz
47
75
47
60
90
mA
mA
μA
See Figure 4
ICCXD
Serializer Supply Current Powerdown PWRDN = 0.8V
500
DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
ICCR
Deserializer Supply Current
Worst Case
CL = 15 pF
f = 20 MHz
f = 66 MHz
58
75
mA
mA
See Figure 5
110
130
ICCXR
Deserializer Supply Current
Powerdown
PWRDN = 0.8V, REN = 0.8V
0.36
1.0
mA
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SERIALIZER TIMING REQUIREMENTS FOR TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
Parameter
Transmit Clock Period
Conditions
Min
15.15
0.4T
0.4T
Typ
T
Max
50.0
0.6T
0.6T
6
Units
nS
tTCIH
tTCIL
tCLKT
tJIT
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
0.5T
0.5T
3
nS
nS
nS
pS
(RMS)
See Figure 19
150
SERIALIZER SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tLLHT
Parameter
Conditions
Min
Typ
Max
0.4
Units
Bus LVDS Low-to-High
Transition Time
RL = 27Ω
0.2
nS
CL=10pF to GND(1)
See Figure 6
tLHLT
tDIS
Bus LVDS High-to-Low Transition Time
DIN (0-9) Setup to TCLK
0.25
0.4
nS
nS
RL = 27Ω,
0
CL=10pF to GND
See Figure 9
tDIH
DIN (0-9) Hold from TCLK
4.0
nS
nS
tHZD
DO ± HIGH to
TRI-STATE Delay
RL = 27Ω,
3
10
CL=10pF to GND(2)
See Figure 10
tLZD
tZHD
tZLD
tSPW
tPLD
tSD
DO ± LOW to TRI-STATE Delay
DO ± TRI-STATE to HIGH Delay
DO ± TRI-STATE to LOW Delay
SYNC Pulse Width
3
5
10
10
10
nS
nS
nS
nS
6.5
RL = 27Ω
See Figure 12
5*tTCP
Serializer PLL Lock Time
Serializer Delay
510*tTCP
tTCP+ 1.0
-300
513*tTCP
tTCP+ 2.5 tTCP+ 3.5
nS
nS
pS
pS
RL = 27Ω, see Figure 13
tDJIT
Deterministic Jitter
RL = 27Ω,
20 MHz
66 MHz
-135
-40
35
CL=10pF to GND(3)
-245
160
tRJIT
Random Jitter
RL = 27Ω,
CL=10pF to GND
pS
(RMS)
19
25
(1) tLLHT and tLHLT specifications are specified by design using statistical analysis.
(2) Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
(3) tDJIT specifications are specified by design using statistical analysis.
DESERIALIZER TIMING REQUIREMENTS FOR REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRFCP
Parameter
REFCLK Period
Conditions
Min
15.15
30
Typ
T
Max
50
Units
nS
tRFDC
REFCLK Duty Cycle
50
70
%
tRFCP
tTCP
/
Ratio of REFCLK to TCLK
95
1
3
105
6
tRFTT
REFCLK Transition Time
nS
8
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SNLS133D –JAN 2001–REVISED APRIL 2013
DESERIALIZER SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
tRCP
Receiver out Clock
Period
tRCP = tTCP
See Figure 13
RCLK
15.15
50
nS
tCLH
tCHL
tDD
CMOS/TTL Low-to-High
Transition Time
CL = 15 pF
See Figure 7
Rout(0-9),
LOCK,
RCLK
1.2
1.1
4
4
nS
CMOS/TTL High-to-Low
Transition Time
nS
nS
nS
Deserializer Delay
See Figure 14
All Temp./ All Freq.
1.75*tRCP+1.25 1.75*tRCP+5.0 1.75*tRCP+7.5
1.75*tRCP+2.25 1.75*tRCP+5.0 1.75*tRCP+6.5
Room
Temp./3.3V/20MHz
Room
Temp./3.3V/66MHz
1.75*tRCP+2.25 1.75*tRCP+5.0 1.75*tRCP+6.5
nS
nS
nS
tROS
ROUT Data Valid before
RCLK
See Figure 15
RCLK
20MHz
0.4*tRCP
0.5*tRCP
0.5*tRCP
RCLK
66MHz
0.38*tRCP
tROH
ROUT Data valid after RCLK
See Figure 15
See Figure 16
20MHz
66MHz
−0.4*tRCP
−0.38*tRCP
45
−0.5*tRCP
−0.5*tRCP
50
nS
nS
%
tRDC
tHZR
tLZR
RCLK Duty Cycle
55
10
10
10
10
4
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Rout(0-9)
2.8
nS
nS
nS
nS
μS
2.8
tZHR
tZLR
4.2
4.2
tDSR1
Deserializer PLL Lock
Time from PWRDWN
(with SYNCPAT)
See Figure 17 and
Figure 18(1)
20MHz
66MHz
2.6
0.84
3
μS
tDSR2
Deserializer PLL Lock time
from SYNCPAT
20MHz
66MHz
1
2
μS
μS
0.29
0.8
tZHLK
tRNM
TRI-STATE to HIGH Delay
(power-up)
LOCK
3.7
12
nS
(2)
Deserializer Noise Margin
See Figure 19
20 MHz
66 MHz
1.0
1.6
nS
pS
250
400
(1) For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK running and stable, and
with specific conditions for the incoming data stream (SYNCPATs). It is recommended that the deserializer be initialized using either
tDSR1 timing or tDSR2 timing. tDSR1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-
down mode. Synchronization patterns should be sent to the device before initiating either condition. tDSR2 is the time required to indicate
lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs).
(2) tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. The
Deserializer Noise Margin is specified by design using statistical analysis.
SCAN CIRCUITRY TIMING REQUIREMENTS
Symbol
Parameter
Conditions
Min
Typ
Max
Units
fMAX
Maximum TCK Clock
Frequency
RL = 500Ω, CL = 35 pF
25.0
50.0
MHz
tS
TDI to TCK, H or L
TDI to TCK, H or L
TMS to TCK, H or L
TMS to TCK, H or L
TCK Pulse Width, H or L
TRST Pulse Width, L
1.0
2.0
2.5
1.5
10.0
2.5
2.0
ns
ns
ns
ns
ns
ns
ns
tH
tS
tH
tW
tW
tREC
Recovery Time, TRST to
TCK
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AC TIMING DIAGRAMS AND TEST CIRCUITS
Figure 4. “Worst Case” Serializer ICC Test Pattern
Figure 5. “Worst Case” Deserializer ICC Test Pattern
Figure 6. Serializer Bus LVDS Output Load and Transition Times
Figure 7. Deserializer CMOS/TTL Output Load and Transition Times
Figure 8. Serializer Input Clock Transition Time
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Timing shown for TCLK_R/F = LOW
Figure 9. Serializer Setup/Hold Times
Figure 10. Serializer TRI-STATE Test Circuit and Timing
Figure 11. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays
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Figure 12. SYNC Timing Delays
Figure 13. Serializer Delay
Figure 14. Deserializer Delay
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Timing shown for RCLK_R/F = LOW
Duty Cycle (tRDC) =
Figure 15. Deserializer Data Valid Out Times
Figure 16. Deserializer TRI-STATE Test Circuit and Timing
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Figure 17. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
Figure 18. Deserializer PLL Lock Time from SyncPAT
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SW - Setup and Hold Time (Internal Data Sampling Window)
tDJIT - Serializer Output Bit Position Jitter that results from Jitter on TCLK
tRNM = Receiver Noise Margin Time
Figure 19. Receiver Bus LVDS Input Skew Margin
VOD = (DO+)–(DO−).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
Figure 20. VOD Diagram
Pin Diagrams
Top View
Figure 21. SCAN921023NZA - Serializer
NFBGA Package
See Package Number NZA0049A
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Top View
Figure 22. SCAN921224NZA - Deserializer
NFBGA Package
See Package Number NZA0049A
Serializer Pin Description
Pin Name
DIN
I/O
Ball Id.
Description
I
A3, B1, C1, D1, Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input register.
D2, D3, E1, E2,
F2, F4
TCLKR/F
I
G3
Transmit Clock Rising/Falling strobe select. LVTTL level input. Selects TCLK active edge for
strobing of DIN data. High selects rising edge. Low selects falling edge.
DO+
O
O
I
D7
D5
D6
C7
+ Serial Data Output. Non-inverting Bus LVDS differential output.
DO−
− Serial Data Output. Inverting Bus LVDS differential output.
DEN
Serial Data Output Enable. LVTTL level input. A low puts the Bus LVDS outputs in TRI-STATE.
PWRDN
I
Powerdown. LVTTL level input. PWRDN driven low shuts down the PLL and TRI-STATEs
outputs putting the device into a low power sleep mode.
TCLK
SYNC
I
I
E4
Transmit Clock. LVTTL level input. Input for 20 MHz–66 MHz system clock.
A4, B3
Assertion of SYNC (high) for at least 1024 synchronization symbols to be transmitted on the Bus
LVDS serial output. Synchronization symbols continue to be sent if SYNC continues to be
asserted. TTL level input. The two SYNC pins are ORed.
DVCC
DGND
I
I
C3, C4, E5
Digital Circuit power supply.
A1, C2, F5, E6, Digital Circuit ground.
G4
AVCC
AGND
I
I
A5, A6, B4, B7, Analog power supply (PLL and Analog Circuits).
G5
B5, B6, C6, E7, Analog ground (PLL and Analog Circuits).
F7
TDI
I
F1
G1
E3
F3
G2
Test Data Input to support IEEE 1149.1
Test Data Output to support IEEE 1149.1
Test Mode Select Input to support IEEE 1149.1
Test Clock Input to support IEEE 1149.1
Test Reset Input to support IEEE 1149.1
TDO
TMS
TCK
TRST
N/C
O
I
I
I
N/A
A2, A7, B2, C5, Leave open circuit, do not connect
D4, F6, G6, G7
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Deserializer Pin Description
Pin Name
I/O
Ball Id.
Description
ROUT
O
A5, B4, B6, C4, Data Output. ±9 mA CMOS level outputs.
C7, D6, F5, F7,
G4, G5
RCLKR/F
I
B3
Recovered Clock Rising/Falling strobe select. TTL level input. Selects RCLK active edge for
strobing of ROUT data. High selects rising edge. Low selects falling edge.
RI+
I
I
I
D2
C1
D3
+ Serial Data Input. Non-inverting Bus LVDS differential input.
RI−
− Serial Data Input. Inverting Bus LVDS differential input.
PWRDN
Powerdown. TTL level input. PWRDN driven low shuts down the PLL and TRI-STATEs outputs
putting the device into a low power sleep mode.
LOCK
RCLK
O
O
E1
E2
D1
LOCK goes low when the Deserializer PLL locks onto the embedded clock edge. CMOS level
output. Totem pole output structure, does not directly support wired OR connections.
Recovered Clock. Parallel data rate clock recovered from embedded clock. Used to strobe
ROUT, CMOS level output.
REN
I
I
Output Enable. TTL level input. When driven low, TRI-STATEs ROUT0–ROUT9 and RCLK.
DVCC
A7, B7, C5, C6, Digital Circuit power supply LOCK.
D5
DGND
AVCC
AGND
I
I
I
A1, A6, B5, D7, Digital Circuit ground.
E4, E7, G3
B1, C2, F1, F2, Analog power supply (PLL and Analog Circuits).
G1
A4, B2, F3, F4, Analog ground (PLL and Analog Circuits).
G2
REFCLK
TDI
I
A3
F6
G6
G7
E5
E6
Use this pin to supply a REFCLK signal for the internal PLL frequency.
I
Test Data Input to support IEEE 1149.1
Test Data Output to support IEEE 1149.1
Test Mode Select Input to support IEEE 1149.1
Test Clock Input to support IEEE 1149.1
Test Reset Input to support IEEE 1149.1
TDO
TMS
TCK
O
I
I
I
TRST
N/C
N/A
A2, C3, D4, E3 Leave open circuit, do not connect
DESERIALIZER TRUTH TABLE(1)(2)(3)(4)
INPUTS
OUTPUTS
PWRDN
REN
H
ROUT [0:9]
LOCK
RCLK
H (4)
H
Z
Active
Z
H
L
Z
Active
Z
H
L
X
Z
H
L
Z
Active
Z
(1) Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
(2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined
by RCLK_R/F
(3) ROUT and RCLK are TRI-STATED when LOCK is asserted High.
(4) During Power-up.
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APPLICATION INFORMATION
USING THE SCAN921023 AND SCAN921224
The Serializer and Deserializer chipset is an easy to use transmitter and receiver pair that sends 10 bits of
parallel LVTTL data over a serial Bus LVDS link up to 660 Mbps. An on-board PLL serializes the input data and
embeds two clock bits within the data stream. The Deserializer uses a separate reference clock (REFCLK) and
an onboard PLL to extract the clock information from the incoming data stream and then deserialize the data.
The Deserializer monitors the incoming clock information, determines lock status, and asserts the LOCK output
high when loss of lock occurs.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. In addition, the
constant current source nature of the Bus LVDS outputs minimizes the slope of the speed vs. ICC curve of
conventional CMOS designs.
POWERING UP THE DESERIALIZER
The SCAN921224 can be powered up at any time by following the proper sequence. The REFCLK input can be
running before the Deserializer powers up, and it must be running in order for the Deserializer to lock to incoming
data. The Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission at its
inputs and locks to the incoming data stream.
TRANSMITTING DATA
Once you power up the Serializer and Deserializer, they must be phase locked to each other to transmit data.
Phase locking occurs when the Deserializer locks to incoming data or when the Serializer sends patterns. The
Serializer sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCK output of the
Deserializer remains high until it has locked to the incoming data stream. Connecting the LOCK output of the
Deserializer to one of the SYNC inputs of the Serializer will ensure that enough SYNC patterns are sent to
achieve Deserializer lock.
The Deserializer can also lock to incoming data by simply powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
While the Deserializer LOCK output is low, data at the Deserializer outputs (ROUT0-9) is valid, except for the
specific case of loss of lock during transmission which is further discussed in RECOVERING FROM LOCK
LOSS.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic factors include:
Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise)
Media: ISI, Large VCM shifts
Deserializer: VCC noise
RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data transmission, up to 3 cycles of data that were
previously received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit
requires that invalid clock information be received 4 times in a row to indicate loss of lock. Since clock
information has been lost, it is possible that data was also lost during these cycles. Therefore, after the
Deserializer relocks to the incoming data stream and the Deserializer LOCK pin goes low, at least three previous
data cycles should be suspect for bit errors.
The Deserializer can relock to the incoming data stream by making the Serializer resend SYNC patterns, as
described above, or by random locking, which can take more time, depending on the data patterns being
received.
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HOT INSERTION
All the BLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s)
makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be
unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 25.
PCB CONSIDERATIONS
The Bus LVDS Serializer and Deserializer should be placed as close to the edge connector as possible. In
multiple Deserializer applications, the distance from the Deserializer to the slot connector appears as a stub to
the Serializer driving the backplane traces. Longer stubs lower the impedance of the bus, increase the load on
the Serializer, and lower the threshold margin at the Deserializers. Deserializer devices should be placed much
less than one inch from slot connectors. Because transition times are very fast on the Serializer Bus LVDS
outputs, reducing stub lengths as much as possible is the best method to ensure signal integrity.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-point configuration of a backplane, through a PCB
trace, or through twisted pair cable. In point-to-point configuration, the transmission media need only be
terminated at the receiver end. Please note that in point-to-point configuration, the potential of offsetting the
ground levels of the Serializer vs. the Deserializer must be considered. Also, Bus LVDS provides a +/− 1.2V
common mode range at the receiver inputs.
FAILSAFE BIASING FOR THE SCAN921224
The SCAN921224 has an improved input threshold sensitivity of +/− 50mV versus +/− 100mV for the
DS92LV1210 or DS92LV1212. This allows for greater differential noise margin in the SCAN921224. However, in
cases where the receiver input is not being actively driven, the increased sensitivity of the SCAN921224 can
pickup noise as a signal and cause unintentional locking. For example, this can occur when the input cable is
disconnected.
External resistors can be added to the receiver circuit board to prevent noise pick-up. Typically, the non-inverting
receiver input is pulled up and the inverting receiver input is pulled down by high value resistors. the pull-up and
pull-down resistors (R1 and R2) provide a current path through the termination resistor (RL) which biases the
receiver inputs when they are not connected to an active driver. The value of the pull-up and pull-down resistors
should be chosen so that enough current is drawn to provide a +15mV drop across the termination resistor.
Please see Figure 23 for the Failsafe Biasing Setup.
USING TDJIT AND TRNM TO VALIDATE SIGNAL QUALITY
The parameters tDJIT and tRNM can be used to generate an eye pattern mask to validate signal quality in an actual
application or in simulation.
The parameter tDJIT measures the transmitter's ability to place data bits in the ideal position to be sampled by the
receiver. The typical tDJIT parameter of −80pS indicates that the crossing point of the Tx data is 80pS ahead of
the ideal crossing point. The tDJIT(min) and tDJIT(max) parameters specify the earliest and latest, repectively, time that
a crossing will occur relative to the ideal position.
The parameter tRNM is calculated by first measuring how much of the ideal bit the receiver needs to ensure
correct sampling. After determining this amount, what remains of the ideal bit that is available for external
sources of noise is called tRNM. It is the offset from tDJIT(min or max) for the test mask within the eye opening.
The vertical limits of the mask are determined by the SCAN921224 receiver input threshold of +/− 50mV.
Please refer to the eye mask pattern of Figure 24 for a graphic representation of tDJIT and tRNM
.
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Figure 23. Failsafe Biasing Setup
Figure 24. Using tDJIT and tRNM to Generate an Eye Pattern Mask and Validate Signal Quality
Figure 25. Random Lock Hot Insertion
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
416
416
416
(1)
(2)
(3)
(4/5)
(6)
SCAN921023SLC
SCAN921224SLC
NRND
NFBGA
NFBGA
NFBGA
NZA
49
49
49
Non-RoHS
& Green
Call TI
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-4-260C-72 HR
-40 to 85
-40 to 85
-40 to 85
SCAN921023
SLC
NRND
NZA
Non-RoHS
& Green
Call TI
SCAN921224
SLC
SCAN921224SLC/NOPB
ACTIVE
NZA
RoHS & Green
SNAGCU
SCAN921224
SLC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
SCAN921023SLC
SCAN921224SLC
NZA
NZA
NZA
NFBGA
NFBGA
NFBGA
49
49
49
416
416
416
13 X 32
13 X 32
13 X 32
150
150
150
322.6 135.9 7620
322.6 135.9 7620
322.6 135.9 7620
9.4
9.4
9.4
11.8 11.55
11.8 11.55
11.8 11.55
SCAN921224SLC/NOPB
Pack Materials-Page 1
MECHANICAL DATA
NZA0049A
SLC49A (Rev B)
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