SCAN921821 [TI]

具有预加重功能、IEEE 1149.1 (JTAG) 和全速度 BIST 的双路 18 位串行器;


型号：	SCAN921821
厂家：	TEXAS INSTRUMENTS
描述：	具有预加重功能、IEEE 1149.1 (JTAG) 和全速度 BIST 的双路 18 位串行器
文件：	总16页 (文件大小：1139K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SCAN921821

www.ti.com

SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

SCAN921821 Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed

BIST

Check for Samples: SCAN921821

FEATURES

DESCRIPTION

The SCAN921821 is a dual channel 18-bit serializer

featuring signal conditioning, boundary SCAN, and at-

speed BIST. Each serializer block transforms an 18-

bit parallel LVCMOS/LVTTL data bus into a single

Bus LVDS data stream with embedded clock. This

single serial data stream with embedded clock

simplifies PCB design and reduces PCB cost by

narrowing data paths that in turn reduce PCB size

and layers. The single serial data stream also

reduces cable size, the number of connectors, and

eliminates clock-to-data and data-to-data skew.

•

15-66 MHz Dual 18:1 Serializer with 2.376 Gbps

Total Throughput

•

8-level Selectable Pre-emphasis on Each

Channel Drives Lossy Cables and Backplanes

>15kV HBM ESD Protection on Bus LVDS I/O

Pins

Robust BLVDS Serial Data Transmission with

Embedded Clock for Exceptional Noise

Immunity and Low EMI

•

Power Saving Control Pin for Each Channel

IEEE 1149.1 "JTAG" Compliant

Each channel also has an 8-level selectable pre-

emphasis

feature

that

significantly

extends

performance over lossy interconnect. Each channel

also has its own powerdown pin that saves power by

reducing supply current when the channel is not

being used.

At-Speed BIST - PRBS Generation

No External Coding Required

Internal PLL, No External PLL Components

Required

The SCAN921821 also incorporates advanced

testability features including IEEE 1149.1 and at-

speed BIST PRBS pattern generation to facilitate

verification of board and link integrity

•

Single +3.3V Power Supply

Low Power: 260 mW (typ) Per Channel at 66

MHz with PRBS-15 Pattern

•

Single 3.3 V Supply

Fabricated with Advanced CMOS Process

Technology

•

Industrial −40 to +85°C Temperature Range

Compact 100-ball NFBGA Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SCAN921821

SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

www.ti.com

Block Diagram

PEMA

D_OUTAP

D_OUTAN

D_INA

PWDNA

SYNCA

ENA

PEMB

D_OUTBP

D_OUTBN

D_INB

PWDNB

SYNCB

ENB

Timing

and

Control

TxCLK

TRST

PLL

BISTA

BISTB

IEEE 1149.1

Test Access Port

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

(1)(2)

Absolute Maximum Ratings

Supply Voltage (V_DD

)

−0.3V to +4V

< 30 V/ms

−0.3V to (V_DD+0.3V)

−0.3V to +3.9V

10ms

Supply Voltage (V_DD) Ramp Rate

LVCMOS/LVTTL Input Voltage

LVCMOS/LVTTL Output Voltage

Bus LVDS Driver Output Voltage

Bus LVDS Output Short Circuit Duration

Junction Temperature

+150°C

Storage Temperature

−65°C to +150°C

+220°C

Lead Temperature (Soldering, 4 seconds)

Maximum Package Power Dissipation at 25°C

NFBGA-100

Derating Above 25°C

θ_JA

3.57 W

28.57 mW/°C

35°C/W

Thermal resistance

θ_JC

11.1°C/W

ESD Rating

HBM, 1.5 KΩ, 100 pF

All pins

>8 kV

Bus LVDS pins

>15 kV

MM, 0Ω, 200 pF

>1200 V

CDM

>2 kV

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply

that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

Recommended Operating Conditions

Min

3.15

−40

Nom

3.3

Max

3.45

+85

Units

Supply Voltage (V_DD

)

Operating Free Air Temperature (T_A)

Clock Rate

+25

°C

MHz

mV p-p

Supply Noise

100

DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVCMOS/LVTTL Input DC Specifications

High Level Input

V_IH

2.0

V_DD

0.8

Voltage

Low Level Input

V_IL

GND

−1.5

−20

Voltage

V_CL

I_INH

Input Clamp Voltage

I_CL= −18 mA

-0.7

±2

High Level Input

Current

V_IN= V_DD= V_DDMAX

+20

+10

μA

Low Level Output

Current

I_INL

V_IN= V_SS, V_DD= V_DDMAX

−10

±2

μA

1149.1 (JTAG) DC Specifications

High Level Input

V_IH

2.0

V_DD

0.8

Voltage

Low Level Input

V_IL

GND

−1.5

-20

Voltage

V_CL

I_INH

Input Clamp Voltage

I_CL= −18 mA

-0.7

High Level Input

Current

V_IN= V_DD= V_DDMAX

+20

+200

V_DD

0.5

μA

Low Level Output

Current

I_INL

V_OH

V_OL

I_OS

V_IN= V_SS, V_DD= V_DDMAX

I_OH= −9 mA

-200

2.3

μA

High Level Output

Voltage

Low Level Output

Voltage

I_OL= 9 mA

GND

-100

Output Short Circuit

Current

V_OUT= 0 V

-80

-50

PWDN or EN = 0.8V, V_OUT= 0 V

PWDN or EN = 0.8V, V_OUT= VDD

-10

-30

+10

+30

μA

Output Tri-state

Current

I_OZ

Bus LVDS Output DC Specifications

Output Differential

V_OD

See Figure 10, R_L= 100Ω

450

500

550

Voltage (DO+) - (DO-)

Output Differential

ΔV_OD

1.25

Voltage Unbalance

V_OS

Offset Voltage

1.05

1.2

2.7

Offset Voltage

Unbalance

ΔV_OS

(1) Typical values are given for V_CC= 3.3V and T_A= +25°C.

(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

except VOD, ΔVOD, VTH and VTL which are differential voltages.

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Units

DC Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾

Symbol

Parameter

Conditions

Min

1.10

1.35

1.55

1.80

1.95

2.10

2.15

Typ

1.24

1.47

1.70

1.91

2.08

2.21

2.30

Max

1.35

1.55

1.80

1.95

2.20

2.35

2.50

Pre-Emphasis Level = 1

Pre-Emphasis Level = 2

Pre-Emphasis Level = 3

Pre-Emphasis Level = 4

Pre-Emphasis Level = 5

Pre-Emphasis Level = 6

Pre-Emphasis Level = 7

Pre-Emphasis Output

Voltage Ratio

Q_POV

| V_ODPRE/ V_OD

Output Short Circuit

Current

I_OS

I_OZ

DO = 0V, Din = H, PWDN and EN = 2.4V

-10

-25

-75

(3)

PWDN or EN = 0.8V, DO = 0V

-10

-55

± 1

± 6

+10

+55

µA

TRI-STATE Output

Current

(3)

PWDN or EN = 0.8V, DO = VDD

Power Supply Current (DVDD, PVDD and AVDD Pins)

f = 66 MHz, PRBS-15

Pattern

160

180

240

280

1.0

225

Total Supply Current

(includes load current)

C_L= 15pF,

R_L= 100 Ω

I_DD

f = 66 MHz, Worst Case

Pattern (Checker-Board

Pattern)

f = 66 MHz, PRBS-15

Pattern

Total Supply Current

with Pre-Emphasis

(includes load current)

C_L= 15pF,

R_L= 100 Ω

I_DDP

f = 66 MHz, Worst Case

Pattern (Checker-Board

Pattern)

325

3.0

Supply Current

Powerdown

I_DDX

PWDN = 0.8V, EN = 0.8V

(3) I_OZis measured at each pin. The DOUT pin not under test is floated to isolate the TRI-STATE current flow.

Timing Requirements for TCLK

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t_TCP

Transmit Clock Period

15.2

66.7

Transmit Clock High

Time

t_TCIH

t_TCIL

t_CLKT

t_JIT

0.4T

0.5T

0.6T

Transmit Clock Low

Time

TCLK Input Transition

Time

(3)

TCLK Input Jitter

See

ps (RMS)

(1) Typical values are given for V_CC= 3.3V and T_A= +25°C.

(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

except VOD, ΔVOD, VTH and VTL which are differential voltages.

(3) Specified by design using statistical analysis.

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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Serializer AC Specifications

Bus LVDS Low-to-High

(3)

t_LLHT

t_LHLT

t_DIS

0.3

0.4

See Figure 2,

R_L= 100Ω,

Transition Time

Bus LVDS High-to-Low

Transition Time

C_L=10pF to GND

DIN (0-17) Setup to

TCLK

(3)

1.9

0.6

See Figure 4,

R_L= 100Ω,

DIN (0-17) Hold from

TCLK

C_L=10pF to GND

t_DIH

DO ± HIGH to

TRI-STATE Delay

t_HZD

t_LZD

t_ZHD

t_ZLD

t_SPW

3.9

3.5

3.2

2.4

DO ± LOW to TRI-

STATE Delay

See Figure 5

R_L= 100Ω,

C_L=10pF to GND

DO ± TRI-STATE to

HIGH Delay

DO ± TRI-STATE to

LOW Delay

See Figure 7,

SYNC Pulse Width

5*t_TCP

6*t_TCP

1024*t_TCP

R_L= 100Ω

Serializer PLL Lock

Time

See Figure 6,

t_PLD

t_SD

510*t_TCP

R_L= 100Ω

Serializer Delay

See Figure 8 , R_L= 100Ω

t_TCP+ 2.5 t_TCP+ 4.5 t_TCP+ 6.5

Channel to Channel

Skew

t_SKCC

Room Temperature, V_DD= 3.3V,

66 MHz

(RMS)

t_RJIT

t_DJIT

Random Jitter

6.1

15 MHz

66 MHz

-390

-60

320

Deterministic Jitter

(3)

Figure 9,

1149.1 (JTAG) AC Specifications

Maximum TCK Clock

f_MAX

2.4

2.8

MHz

Frequency

TDI or TMS Setup to

t_S

TCK, H or L

TDI or TMS Hold from

t_H

C_L= 15pF,

R_L= 500 Ω

TCK, H or L

TCK Pulse Width, H or

t_W1

t_W2

TRST Pulse Width, L

Recovery Time, TRST

to TCK

t_REC

(1) Typical values are given for V_CC= 3.3V and T_A= +25°C.

(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

except VOD, ΔVOD, VTH and VTL which are differential voltages.

(3) Specified by design using statistical analysis.

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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

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AC Timing Diagrams and Test Circuits

Figure 1. “Worst Case” Serializer IDD Test Pattern

Figure 2. Serializer Bus LVDS Distributed Output Load and Transition Times

Figure 3. Serializer Input Clock Transition Time

Figure 4. Serializer Setup/Hold Times

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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

Figure 5. Serializer TRI-STATE Test Circuit and Timing

Figure 6. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays

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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

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Figure 7. SYNC Timing Delay

Figure 8. Serializer Delay

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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

Figure 9. Deterministic Jitter and Ideal Bit Position

V_OD= (DO⁺)–(DO⁻).

Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.

Figure 10. V_ODDiagram

Pre-emphasis Truth Table

PEM LEVEL

PEM2

PEM1

PEM0

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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

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Pin Diagram

Figure 11. SCAN921821TVV

Top View

A10

BISTB

DOUTBN

ENB

DOUTAN

DOUTAP

ENA

B10

DINB16

SYNCB

DOUTBP

PEMB1

PEMB0

PEMA1

BISTA

C10

DINB14

PEMA2

SYNCA

DINA16

D10

DINB13

DINB12

DINB17

PEMA0

DINA17

DINA15

DINA13

E10

DINB11

DINB9

DINB15

DINB8

PEMB2

DINA14

DINA12

DINA9

F10

DINB10

DINB7

DINB5

DINA11

DINA4

DINA10

DINA8

G10

DINB6

DINB4

DINB2

DINA1

DINA2

DINA7

DINA6

H10

DINB3

DINB1

TxCLK

TCK

DINA0

DINA5

J10

DINB0

PWDNA

TRST

DINA3

TMS

PWDNB

K10

TDI

TDO

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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

Pin Descriptions

Pin Name

DATA PINS

DINA0-17

DINB0-17

DOUTAP

DOUTAN

DOUTBP

DOUTAN

Pin Count

I/O, Type

Description

Transmitter inputs. There is a pull-down circuitry on each of these pins which are active

if respective PWDNA or PWDNB pin is pulled high.

I, LVCMOS

O,BLVDS

Inverting and non-inverting differential transmitter outputs.

TIMING AND CONTROL PINS

Transmitter reference clock. Used to strobe data at the inputs and to drive the

transmitter PLL. There is a pull-up circuitry on this pin which is always active.

TxCLK

I, LVCMOS

ENA

Transmitter outputs enable pins. There is a pull-down circuitry on each of these pins that

are active if corresponding PWDNA or PWDNB pin is pulled high. When these pins are

set to LOW, the transmitter outputs will be disabled. The PLL will remain locked.

ENB

PWDNA

PWDNB

SYNCA

Stand-by mode pins. There is a pull-down circuitry on each of these pins that are always

active. When these pins are set to LOW, the transmitter will be put in low power mode

and the PLL will lose lock.

I, LVCMOS

Transmitter synchronization pins. There is a pull-down circuitry on each of these pins

that are active if corresponding PWDNA or PWDNB pin is pulled high. When these pins

are set to HIGH, the transmitter will ignore incoming data and send SYNC patterns to

provide a locking reference to receiver(s).

SYNCB

PRE-EMPHASIS PINS

PEMA0-2

8-level pre-emphasis selection pins. There is a pull-down circuitry on each of these pins

which are active if corresponding PWDNA or PWDNB pin is pulled high.

I, LVCMOS

PEMB0-2

JTAG PINS

Test Data Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is

always active.

TDI

TDO

TMS

TCK

TRST

O, LVCMOS Test Data Output to support IEEE 1149.1.

Test Mode Select Input to support IEEE 1149.1. There is a pull-up circuitry on this pin

which is always active.

I, LVCMOS

Test Clock Input to support IEEE 1149.1. There is no failsafe circuitry on this pin.

Test Reset Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is

always active.

BIST PINS

BISTA

BIST selection pins. These pins select which transmitter will generate a PRBS like data.

There is a pull-down circuitry on these pins which are active if corresponding PWDNA or

PWDNB pin is pulled high.

I, LVCMOS

BISTB

POWER PINS

AVDD

I, POWER

Power Supply for the LVDS circuitry.

DVDD

Power Supply for the digital circuitry.

PVDD

Power Supply for the PLL and BG circuitry.

Ground reference for the LVDS circuitry.

Ground reference for the digital circuitry.

Ground reference for the PLL and BG circuitry.

AVSS

DVSS

PVSS

OTHER PINS

N/A

Not connected.

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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013

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REVISION HISTORY

Changes from Revision B (April 2013) to Revision C

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 11

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SCAN921821TSM/NOPB

ACTIVE

NFBGA

NZD

100

240

RoHS & Green

SNAGCU

Level-4-260C-72 HR

-40 to 85

SCAN921821

TSM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TRAY

L - Outer tray length without tabs

KO -

Outer

tray

height

W -

Outer

tray

width

Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center

CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

Name

Type

(mm) (µm) (mm) (mm) (mm)

SCAN921821TSM/

NOPB

NZD

NFBGA

100

240

10 X 24

150

322.6 135.9 7620 12.4

14.9 12.15

Pack Materials-Page 1

MECHANICAL DATA

NZD0100A

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