SCANSTA101SM/NOPB [TI]
低电压 IEEE 1149.1 系统测试访问 (STA) 主设备 | NZA | 49 | -40 to 85;
| 型号： | SCANSTA101SM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低电压 IEEE 1149.1 系统测试访问 (STA) 主设备 | NZA | 49 | -40 to 85 测试 |
| 文件： | 总40页 (文件大小：862K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master
Check for Samples: SCANSTA101
1
FEATURES
DESCRIPTION
The SCANSTA101 is designed to function as a test
master for an IEEE 1149.1 boundary scan test
system. It is suitable for use in embedded IEEE
1149.1 applications and as a component in a stand-
alone boundary scan tester.
2
•
Compatible with IEEE Std. 1149.1 (JTAG) Test
Access Port and Boundary Scan Architecture
•
Supported by Texas Instruments' SCAN Ease
(SCAN Embedded Application Software
Enabler) Software Rev 2.0
The SCANSTA101 is an enhanced version of, and a
•
Uses Generic, Asynchronous Processor
Interface; Compatible with a Wide Range of
Processors and Processor Clock (PCLK)
Frequencies
replacement
for,
the
SCANPSC100.
The
SCANSTA101 supports the IEEE 1149.1 Test Access
Port (TAP) standard and the IEEE 1532 standard for
in-system configuration of programmable devices.
•
•
•
16-Bit Data Interface (IP Scalable to 32-bit)
2k x 32 Bit Dual-Port Memory
The SCANSTA101 improves test vector throughput
and reduces software overhead in the system
processor. The SCANSTA101 presents a simple,
register-based interface to the system processor.
Texas Instruments provides C-language source code
which can be included in the embedded system
software. The combination of the SCANSTA101 and
its support software comprises a simple API for
boundary scan operations.
Load-on-the-Fly (LotF) and Preloaded Vector
Operating Modes Supported
•
•
•
•
On-Board Sequencer Allows Multi-Vector
Operations such as those Required to Load
Data Into an FPGA
On-Board Compares Support Test Data In
(TDI) Validation Against Preloaded Expected
Data
The interface from the SCANSTA101 to the system
processor is implemented by reading and writing
registers, some of which map to locations in the
SCANSTA101 memory. Hardware handshaking and
interrupt lines are provided as part of the processor
interface.
32-Bit Linear Feedback Shift Register (LFSR)
at the Test Data In (TDI) Port for Signature
Compression
State, Shift, and BIST Macros Allow
Predetermined Test Mode Select (TMS)
Sequences to be Utilized
The SCANSTA101 is available as a stand-alone
device packaged in a 49-pin NFBGA package. It is
also available as an IP macro for synthesis in
programmable logic devices.
•
•
Operates at 3.3 V Supply Voltages with 5 V
Tolerant I/O
Outputs Support Power-Down TRI-STATE
Mode.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
SCANSTA101 ARCHITECTURE
Figure 1. SCANSTA101 STA Master and Interfaces
Figure 1 shows a high level view of the SCANSTA101 STA Master and its interfaces. Table 1 provides a brief
description of each of these interfaces. provides a brief description of the device pins and their functions. The
device is composed of three interfaces around a dual-port memory. These interfaces are the Parallel Processor
Interface (PPI), Serial Scan Interface (SSI), and Test and Debug Interface. The System Input block designates
inputs that have global use across the device.
The Test and Debug Interface supports BIST, boundary scan, and internal scan for the SCANSTA101.
Table 1. INTERFACE DESCRIPTIONS
Interface
Description
Parallel Processor Interface
Used for configuration, ScanMaster scan chain loads and reads, programmable device file loads
and reads, and status monitoring.
Serial Scan Interface
Performs parallel to serial conversion, sequences and formats the outgoing serial stream to
conform to 1149.1 protocol.
Test and Debug Interface
System Inputs
IEEE 1149.1 TAP
Interface inputs for system control, i.e. clock, reset and output tristate control.
2
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
CONNECTION DIAGRAM
Figure 2. NFBGA Package Pinout
(Top View)
PIN DESCRIPTIONS
Pin
No. Pins
I/O
Description
Name
VCC
4
4
N/A
N/A
I/O
Power
GND
Ground
D(15:0)
16
Bidirectional Data Bus. Signals are bonded out for the packaged
device.
(1)
D(31:16)
16
I/O
Bidirectional Data Bus. These signals are not available in the packaged
device.
A(4:0)
SCK
5
1
I
I
Address Bus
The system clock that drives all internal timing. TCK_SM is a gated,
divided and buffered version of SCK.
INT
1
1
1
O
I
Interrupt Output
OE
Output enable that will TRI-STATE all 1149.1 "_SM" outputs when high.
DTACK
O
DTACK is used to synchronize asynchronous transfers between the
host and the SCANSTA101. When CE is high, DTACK is tristated.
When CE is low, DTACK is enabled. DTACK goes low when data has
been registered and then goes tri-state when the cycle has completed.
R/W
STB
1
1
I
I
R/W defines a PPI cycle. Read when high, write when low.
Strobe is used for timing all PPI transfers. D(15:0), or D(31:0) in 32-bit
mode (1), are at TRI-STATE when STB is high. Data valid setup is with
respect to the falling edge of STB and data valid hold is with respect to
rising edge of STB.
CE
1
I
Chip Enable, when low, enables the PPI for data transfers. CE can
remain low during back-to-back accesses. D(15:0), or D(31:0) in 32-bit
mode (1), and DTACK are tristated when CE is high.
RST
TDO
1
1
I
Asynchronous reset, when low, initializes the SCANSTA101.
O
Test Data Out is the serial scan output from the SCANSTA101. TDO is
enabled when OE is low.
(1) D(31:16) in the Parallel Processor Interface and TRST1_SM in the Serial Scan Interface are not bonded out for the packaged device.
These are used in the 32-bit IP Macro Mode only.
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
PIN DESCRIPTIONS (continued)
Pin
No. Pins
I/O
Description
Name
TDI
1
1
I
I
Test Data In is the serial scan input to the SCANSTA101.
TMS
Test Mode Select. The Test Mode Select pin is a serial input used to
accept control logic to the test & debug interface.
TCK
1
1
I
I
Test Clock Input for 1149.1
TRST
Test Reset. This pin should be tied to ground by a 1K resistor to hold
the Test and Debug Interface in the Test-Logic-Reset state during
device power-up. This avoids invalid states when ramping supply
voltages.
TDI_SM
TDO_SM
TMS_SM
TCK_SM
1
1
1
1
1
1
I
STA Master Test Data Input in the Serial Scan Interface
STA Master Test Data Output in the Serial Scan Interface
STA Master Test Mode Select in the Serial Scan Interface
STA Master Test Clock in the Serial Scan Interface
STA Master Test Reset output in the Serial Scan Interface
O
O
O
O
O
TRST0_SM
TRST1_SM
(1)
Redundant ScanMaster TRST. This signal is not available for the
packaged device.
TRIST_SM
1
O
The TRI-STATE notification pin exerts a high signal when TDO_SM is
at TRI-STATE
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
(1)(2)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC
DC Input Diode Current (IIK
DC Input Voltage (VI) −0.5V to +4.0V
DC Output Diode Current (IOK
)
−0.5V to +4.0V
−20 mA
)
VI = −0.5V
VO = −0.5V
)
−20 mA
DC Output Voltage (VO) −0.5V to +4.0V
DC Output Source/Sink Current (IO)
DC VCC or Ground Current per Output Pin
DC Latchup Source or Sink Current
Junction Temperature
±50 mA
±50 mA
±300 mA
+150°C
Plastic
Storage Temperature −65°C to +150°C
Lead Temperature (Solder, 4sec)
Max Pkg Power Capacity @ 25°C
49L NFBGA
49L NFBGA
49L NFBGA
220°C
1.47W
Thermal Resistance (θJA
)
85°C/W
Package Derating 11.8mW/°C above +25°C
ESD Last Passing Voltage (Min)
2000V
(1) Absolute maximum ratings are those values beyond which damage to the device may occur. The datasheet specifications should be
met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading
variables. Texas Instruments does not recommend operation of SCAN STA products outside of recommended operation conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage (VCC
)
3.0V to 3.6V
0V to VCC
Input Voltage (VI)
Output Voltage (VO)
0V to VCC
Operating Temperature (TA)
−40°C to +85°C
DC ELECTRICAL CHARACTERISTICS
Over recommended operating supply voltage and temperature ranges unless otherwise specified.
Symbol
VIH
Parameter
Minimum High Input Voltage
Maximum Low Input Voltage
Minimum High Output Voltage
Conditions
Min
Max
Units
VOUT = 0.1V or VCC − 0.1V
VOUT = 0.1V or VCC − 0.1V
IOUT = −100 μA, VIN = VIL or VIH
IOH = −24 mA, VIN = VIL or VIH
2.1
V
V
V
V
VIL
0.8
VOH
VCC-0.2V
2.2
Minimum High Output Voltage,
TDO_SM, TMS_SM, TCK_SM, TRST0_SM
outputs only
Minimum High Output Voltage,
All other outputs including 1149.1
IOH = −12 mA, VIN = VIL or VIH
2.4
V
VOL
Maximum Low Output Voltage
IOUT = +100 μA, VIN = VIL or VIH
0.2
0.5
V
V
Maximum Low Output Voltage,
TDO_SM, TMS_SM, TCK_SM, TRST0_SM
outputs only
IOL = 24 mA, VIN = VIL or VIH
Maximum Low Output Voltage,
all other outputs including 1149.1
IOL = 12mA, VIN = VIL or VIH
0.4
±5.0
-200
5.0
V
IIN
Maximum Input Leakage Current, All pins
except TDI, TMS, TRST, TDI_SM
VIN = VCC for TDI, OE, VIN = VCC
GND for All Others
,
μA
μA
μA
μA
IILR
IIH
Maximum Input Leakage Current, TDI, TMS,
TRST, TDI_SM
VIN = GND
VIN = VCC
-45
Maximum Input Leakage Current, TDI, TMS,
TRST, TDI_SM
IOZ
Maximum TRI-STATE Leakage Current
VIN = VCC, GND, VIN (OE, R/W, CE,
STB) = VIL, VIH
±5.0
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
DC ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified.
Symbol
IOFF
Parameter
Conditions
Min
Max
Units
Power Off Leakage Current
VCC = 0.0V
5.0
μA
All pins except TDI, TMS, TRST, and TDI_SM
ICC
Maximum Quiescent Supply Current
Maximum Supply Current
Maximum ICC/Input
250
1.2
μA
mA
μA
ICCmax
ICCT
All inputs low
VIN = VCC − 0.6V
250
AC ELECTRICAL CHARACTERISTICS/OPERATING REQUIREMENTS
Over recommended operating supply voltage and temperature ranges unless otherwise specified. CL = 50 pF, RL = 500Ω
unless otherwise specified.
Symbol
Parameter
Conditions
# of SCK
Min
Max
Units
(1)(2)
PARALLEL PROCESSOR INTERFACE (PPI)
tS1
tH1
tD1
tD1
tD1
Set Up Time
CE, R/W, Addr, Data to STB
See Figure 12 and Figure 13
0
0
ns
ns
ns
ns
Hold Time
CE, R/W, Addr, Data to DTACK
See Figure 12 and Figure 13
See Figure 12
Propagation Delay
STB low to DTACK low, Register Write
2 or 3
4 or 5
11.5
11.5
Propagation Delay
STB low to DTACK low, Register Read
See Figure 13
Propagation Delay
STB low to DTACK low, Memory Write:
16-bit first access
See Figure 12
See Figure 12
See Figure 13
See Figure 13
3 or 4
7 or 8
9 or 10
3 or 4
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
11.5
11.5
11.5
11.5
10.0
10.0
10.0
10.0
10.0
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tD1
tD1
tD1
tD2
tD2
tD2
tD2
tD2
tD2
Propagation Delay
STB low to DTACK low, Memory Write:
16-bit second access
Propagation Delay
STB low to DTACK low, Memory Read:
16-bit first access
Propagation Delay
STB low to DTACK low, Memory Read:
16-bit second access
Propagation Delay
STB high to DTACK TRISTATE, Register See Figure 12
Write
Propagation Delay
STB high to DTACK TRISTATE, Register See Figure 13
Read
Propagation Delay
STB high to DTACK TRISTATE, Memory See Figure 12
Write: 16-bit first access
Propagation Delay
STB high to DTACK TRISTATE, Memory See Figure 12
Write: 16-bit second access
Propagation Delay
STB high to DTACK TRISTATE, Memory See Figure 13
Read: 16-bit first access
Propagation Delay
STB high to DTACK TRISTATE, Memory See Figure 13
Read: 16-bit second access
(1) Due to uncertainty in the relationship of the STB placement to the system clock, SCK, the STB may be detected during the current or
the next SCK cycle.
(2) An absolute maximum delay can be calculated as: (Max # SCK) x (SCK Period) + tD.For example, for tD1 (STB low to DTACK low,
register write), the # SCK cycles is 2 or 3 and the delay, tD, is 11.5ns. For a SCK with a 100ns period, the absolute maximum delay is (3
x 100ns) + 11.5, or 311.5ns.
6
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
AC ELECTRICAL CHARACTERISTICS/OPERATING REQUIREMENTS (continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified. CL = 50 pF, RL = 500Ω
unless otherwise specified.
Symbol
Parameter
Conditions
# of SCK
Min
Max
Units
ns
(1)(2)
tD3
Propagation Delay
Output data valid to DTACK low, all read See Figure 13
cycles
1
tpHL1
Propagation Delay
STB low to INT low, register write (clears See Figure 12
Interrupt)
10.5
66
5 or 6
ns
tW
Clock Pulse Width, SCK, H or L
Clock Frequency, SCK
3.0
ns
MHz
ns
fMAX
tRELEASE
Release Time, RST to STB
2
Symbol
Parameter
Conditions
Min
Max
Units
SERIAL SCAN INTERFACE (SSI)
tD5
Propagation Delay
SCK to TCK_SM
See Figure 14
11.5
12.0
12.5
15.0
12.5
ns
ns
ns
ns
ns
tD6
Propagation Delay
SCK to TDO_SM
See Figure 14
See Figure 14
See Figure 14
See Figure 14
tD7
Propagation Delay
SCK to TMS_SM
tD8
Propagation Delay - tpLH
SCK to TRIST_SM
tD9
Propagation Delay - tpHL
SCK to TRIST_SM
tD10
tD11
tEN1
Propagation Delay
SCK to TDO_SM disable
See Figure 14
See Figure 14
12.5
14.0
ns
ns
Propagation Delay
SCK to TDO_SM enable
Enable Delay
OE low to TCK_SM, TDO_SM, TMS_SM, or
TRST0_SM
See Figure 14
See Figure 14
12.0
11.0
ns
ns
tDIS1
Disable Delay
OE high to TCK_SM, TDO_SM, TMS_SM, or
TRST0_SM
tEN2
tDIS2
tDIS3
tS2
Enable Delay
OE low to TRIST_SM
10.0
11.5
12.5
ns
ns
ns
ns
ns
Disable Delay
OE high to TRIST_SM
Disable Delay
RST low to TRST0_SM
Setup Time
SCK to TDI_SM
See Figure 14
See Figure 14
3.5
2.0
tH2
Hold Time
SCK to TDI_SM
TEST & DEBUG INTERFACE TIMING REQUIREMENTS (SCAN)
tS
tH
tS
tH
tW
Setup Time
TMS to TCK
2.0
1.0
ns
ns
ns
ns
ns
Hold Time
TMS to TCK
Setup Time
TDI to TCK
1.0
Hold Time
TDI to TCK
2.0
Pulse Width
TCK (H or L)
10.0
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
Symbol
tWL
Parameter
Conditions
Min
Max
Units
Reset Pulse Width
TRST (L)
2.5
ns
tREC
fMAX
Recovery Time
TCK from TRST
2.0
ns
Maximum Clock Frequency, TCK
25
MHz
APPLICATIONS/PROGRAMMERS REFERENCE
Table 2. REGISTER SUMMARY
Address
00h
01h
02h
03h
04h
05h
07h
08h
09h
0Ah
0Bh
0Ch
11h
13h
15h
17h
19h
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Mnemonic
START
Register
Active Register Bits
Reset Value
0000h
Start Register
5
STATUS
INTCTRL
INTSTAT
SETUPR
CLKDIV
Status Register
10
8
0000h
0000h
0000h
0043h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Interrupt Control Register
Interrupt Status Register
Setup Register
8
8
Clock Divider Register
TDI_SM LFSR Exponent Register
TDI_SM LSB Seed Register
TDI_SM MSB Seed Register
TDI_SM LSB Result Register
TDI_SM MSB Result Register
Index Register
6
EXPR
3
LSSEDR
MSSEDR
LSRESR
MSRESR
INDEXR
16
16
16
16
16
16
16
16
16
16
VINDEXR
HTINDEXR
MINDEXR
SINDEXR
BSINDEXR
Vector Index Register
Header/Trailer Index Register
Macro Index Register
Sequencer Index Register
Bridge Support Register
Table 3. MEMORY/REGISTER ADDRESS MAP
A4
A3
A2
A1
A0
Function
Base Address Long Word
Index
Structure/Size
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
Start
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
N/A
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
Status
N/A
Interrupt Control
Interrupt Status
Setup
N/A
N/A
N/A
Clock Divider
N/A
TDI_SM LFSR Exponent
TDI_SM LFSR LSB Seed
TDI_SM LFSR MSB Seed
TDI_SM LFSR LSB Result
TDI_SM LFSR MSB Result
Index Register
N/A
(1)
(1)
(1)
(1)
(2)
N/A
N/A
N/A
N/A
N/A
(3)
TDO_SM
0 - 0x1BF
0 - 0x1BF
See
(3)
TDI_SM
0 x 1C0
See
(1) The TDI_SM LFSR result and seed registers require two sequential reads/writes for each register pair.
(2) The Index register is used to set the individual address pointers. Writing to the Index register will set each of the individual address
pointers (TDO_SM, TDI_SM, Expected, and Mask). The individual address pointers will automatically increment with each long word
read from TDI_SM or each long word written to the TDO_SM, Expected, or Mask memory spaces.
(3) The actual address is calculated from the base address of the memory area plus the content of its address pointer.
8
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
A4
SNLS057J –MAY 2002–REVISED APRIL 2013
Table 3. MEMORY/REGISTER ADDRESS MAP (continued)
A3
A2
A1
A0
Function
Base Address Long Word
Index
Structure/Size
(3)
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
Expected
0 x 380
0 x 540
N/A
0 - 0x1BF
0 - 0x1BF
N/A
See
(3)
Mask
See
Vector Index
Vector 1
16-bit Register
See (4), Table 4
0 x 700
0 x 700
0 x 700
0 x 700
N/A
0x0 - 0x1
0x2 - 0x3
0x4 - 0x5
0x6 - 0x7
N/A
Vector 2
Vector 3
Vector 4
1
1
0
0
0
1
1
0
1
0
Header/Trailer Index
Data Header
Data Trailer
Instruction Header
Instruction Trailer
Macro Index
Macro 1
16-bit Register
See Table 5
0 x 708
0 x 728
0 x 748
0 x 768
N/A
0x0 - 0x1F
0x20 - 0x3F
0x40 - 0x5F
0x60 - 0x7F
N/A
1
1
0
0
1
1
0
1
1
0
16-bit Register
0 x 788
0 x 789
0 x 78A . . .
0 x 797
N/A
0x0
See Table 6,
Table 7 and
Table 8
Macro 2
0x1
Macro 3 . . .
Macro 16
0x2 . . .
0xF
1
1
1
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
Sequencer Index
Sequencer
N/A
16-bit Register
See Table 9
0 x 798
N/A
0x0 - 0x1F
N/A
Scan Bridge Support Index
Scan Bridge Support
16-bit Register
See Table 10
0 x 7B8
0x0 - 0x3F
(4) The upper two bytes of each vector are ignored. These have been inserted to make the space align on long word boundaries.
Table 4. VECTOR STRUCTURE
Bit(s)
Function
0x00 - 0x1F
0x20 - 0x27
0x28 - 0x2E
0x2F
Length (maximum of 4G)
Macro Number (1 of 256) Room for scaleability
Reserved
Preloaded data / Load-on-the-fly (LotF)
Reserved
0x30 - 0x3F
Table 5. HEADER/TRAILER STRUCTURE
Bit(s)
Function
(1)
0x00 - 0x1F
0x20 - 0x3FF
32-bit count
124 bytes (992 bits) header/trailer data
(1) Count must be greater than zero if the Header/Trailer Usage bits are not equal to "000" or "111".
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
Table 6. MACRO STRUCTURE
Bit(s)
Function
Compare
0x1F
0x1E
Use Mask / Compare full length of vector (not including header/trailer)
0x1D - 0x1B
0x1A - 0x18
0x17
Post-shift TCK_SM Count
Pre-shift TCK_SM Count
Sync Bit Support Enable
0x16
Macro Structure Bit 8 Enable (Ignored for the shift macros with or without capture)
0x15
Macro Structure bit 7 Enable (Ignored for the shift macros with or without capture)
0x14 - 0x12
0x11
Header/Trailer Usage
Macro Type bit 1
0x10
Macro Type bit 0
0xF - 0x9
0x8
Last 7 TMS_SM bits
Presented during the falling edge of TCK_SM at terminal count during a Shift macro. Use in the same
manner as other TMS bits for State and BIST Macros.
0x7
Loop Bit if Macro type is Shift (for 1149.1 it would be a 0) or BIST
First 7 TMS_SM Bits (LSB is first bit to be shifted out of TMS_SM)
0x6 - 0x0
Table 7. HEADER/TRAILER USAGE
Bit 2
Bit 1
Bit 0
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Ignore Headers and Trailers
Use Instruction Header
Use Instruction Trailer
Use both Instruction Header and Trailer
Use Data Header
Use Data Trailer
Use both Data Header and Trailer
Reserved
Table 8. Macro Type bits 10 and 11
Bit 1
Bit 0
Function
BIST Macro
Shift Macro
Function
0
0
1
1
0
1
0
1
Loop on loop bit for Vector count. No Data
Loop on loop bit for vector count. Read data from TDO_SM memory
Loop on loop bit for vector count. Read data from TDO_SM memory
Do not loop on loop bit of macro. No data to be shifted
Shift Macro with Capture
State Macro
Table 9. SEQUENCER STRUCTURE
Bit(s)
Function
0x00 - 0x1F
0x20 - 0x2F
0x30 - 0x3F
..x.. - ..x..
Sequence repeat count (up to 255)
Vector repeat count
Vector number
Repeat vector repeat count and vector number
Vector repeat count (up to 255)
Vector number (up to 63)
0x3E0 - 0x3EF
0x3F0 - 0x3FF
10
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
Table 10. SCAN BRIDGE SUPPORT STRUCTURE
Bit(s)
Function
0x00 - 0x0F
0x10 - 0x17
0x18 - 0x1F
0x20 - 0x27
0x28 - 0x2F
..x.. - ..x..
Levels of Scan Bridge support to be inserted in the scan chain
Hierarchical Level 0 Scan Bridge Address
Hierarchical Level 0 Scan Bridge LSP
Hierarchical Level 1 Scan Bridge Address
Hierarchical Level 1 Scan Bridge LSP
Hierarchical Level Scan Bridge Address and LSP
Hierarchical Level 125 Scan Bridge Address
Hierarchical Level 125 Scan Bridge LSP
0x7F0 - 0x7F7
0x7F8 - 0x7FF
MODULE DESCRIPTIONS
Figure 1 shows a high level view of the SCANSTA101. The Parallel Processor Interface (PPI) and the Serial
Scan Interface (SSI) connect to each other through a dual-port memory. The PPI provides a parallel interface for
transferring data into and out of the dual-port memory, and for configuring, controlling and obtaining the status of
the device. The SSI, which resides on the other side of the dual-port memory, provides the parallel-to-serial and
serial-to-parallel conversion paths for providing test data and test control to support the STA Master and IEEE
1532 functions.
DUAL PORT MEMORY
The Dual Port Memory module is a 2048 x 32 bit dual-port memory which acts as the buffer between the PPI and
the SSI. There are seven regions of memory as viewed from the processor side. These regions, shown in
Table 3, are TDO_SM, TDI_SM, Expected, Mask, Vector, Header/Trailer, Macro. Sequencer, and ScanBridge
Support. Each has a pointer which resides in the PPI.
The memory is big endian oriented and is viewed as a single entity from the SSI side, and the SSI maintains a
pointer. The dual port memory module does not include any logic outside of its own macro function, so all the
timing and support logic is included in the PPI and SSI sections. There is no logic included in the SCANSTA101
design to utilize the "busy" indicators to keep the user from overwriting memory locations. The only area where
this could occur in memory would be the TDI_SM memory space since both the SSI and PPI can write to this
space, but the drivers should not allow PPI writes to this area during normal operations. The Texas Instruments
SCAN Ease software does not allow PPI writes to the TDI_SM memory.
PARALLEL PROCESSOR INTERFACE
The overall function of the PPI is to receive the parallel data from the processor; store the data in the appropriate
register or memory location; act on the data if the data are PPI control data; provide status data back to the
processor; and provide a read path for result data to the processor. The PPI consists of seven main blocks of
logic. These blocks are the Edge Detector (ED), Processor Interface Controller (PIC), the Memory/Register
Decoder (MRD), the Word/Long Word Converter (WLWC), the Control Generator (CG), the Status/Interrupt
Generator (SIG) and the Flag Generator (FG).
WORD/LONG WORD CONVERTER
The Word/Long Word Converter (WLWC) has four 16-bit capture registers: a least significant/most significant
(LS/MS) word read capture register pair; and a LS/MS word write capture register pair.
Each register within the write register pair has a separate enable to allow for the necessary control to accomplish
word to long word conversions when in the 16-bit mode. In 32-bit mode, these enables are driven
simultaneously. A mux is provided in front of the MS word write capture register to select between the 32-bit and
16-bit mode external bus.
Only one enable and a mux select is needed to control the read capture register pair to accomplish the long word
to word conversions when in the 16- bit mode. In the 32-bit mode, the mux selection doesn't change, so 32 bits
are always driven. A mux is on either side of the LS word read capture register. The mux at the register output
provides for selection between the 32-bit and 16-bit mode. The mux at the register input is for selection between
register space and memory space.
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
All the control for this block is provided by the PIC and MRD with the 16/32-bit mode enable coming from the
Setup register.
EDGE DETECTOR
The PPI module can support either an asynchronous or synchronous processor interface. For an asynchronous
interface, the circuit initially synchronizes STB and CE to the system clock, SCK, by pipelining these two signals
through two flip-flop stages and then performing an edge detection on STB and CE. For a synchronous parallel
processor interface, this circuit just performs an edge detection. The outputs of this circuit, one clock wide pulses
indicating the detection of negative and positive edges, are used by the Processor Interface Controller (PIC)
state machine to start and to end a processor access.
PROCESSOR INTERFACE CONTROLLER
The Processor Interface Controller (PIC) monitors the incoming processor control signals and sets up the
appropriate internal control signals to move the data into memory or into an internal register on a write or to
move the data out of memory or out of an internal register on a read. The PIC edge detects the CE and the STB
to start the access. The PIC provides the control for the word to long word conversion in the WLWC by
controlling the three enables and the mux select (READ_MSW) to the capture registers. The PIC also controls
when the internal read/write enable is issued to the memory to complete the read/write operation. Timing for
register and memory read and write operations is described in Figure 12 and Figure 13.
MEMORY/REGISTER DECODER
The Memory/Register Decoder (MRD) contains all six index registers (Index, Vector Index, Header/Trailer Index,
Macro Index, Sequencer Index and ScanBridge Support Index) and four address registers (TDI_SM Address,
TDO_SM Address, Expected Address and Mask Address). On the PPI side, both index and address registers are
used to maintain pointers to their respective memory spaces. The Index register sets values in all four address
registers; i.e., writing to the Index register sets all of the address registers. The value written to each address
register is the sum of its base address and the value written to the Index register (the offset). All index and
address registers except the Index register auto-increment with each access to the corresponding memory
space.
The MRD provides the address decode to generate all the control and status register enables for the CG and the
SIG. The MRD also provides the mux selects for the register or memory selection for the read capture operation
in the WLWC.
CONTROL GENERATOR
The Control Generator includes the seven control registers: the Start, Interrupt Control, Setup, Clock Divider,
TDI_SM LFSR Exponent, TDI_SM LFSR LSB Seed, and TDI_SM LFSR MSB Seed registers are included in this
block. The CG issues a strobe to the SSI when a write has been issued to the Start or Setup registers so the SSI
can react to the new control data. The strobe is derived from edge detecting the enables to the Start or Setup
registers. The "new" data to the SSI are the Use Sequencer bit and three Use Vector bits from the Start register,
and the TDO Default Value, TRST, ScanBridge Support Initiate/Release, three-bit Sync Bit Length, and two Test
Loop-back bits from the Setup register.
STATUS/INTERRUPT GENERATOR
The Status/Interrupt Generator comprises the four status registers plus the logic to generate the interrupts and to
clear the interrupts on a read. The registers are the Status, Interrupt Status, TDI_SM LFSR LSB Result and
TDI_SM LFSR MSB Result registers. The SIG receives the LFSR result and strobe signal SSI_LFSR_EN from
the SSI and captures the data in the LSB and MSB registers. The SIG receives the compare result bit value from
the SSI along with the compare result bit clear and the compare result bit load.
The SIG receives the 4 memory space flags from the FG along with their associated load and clear signals so
these bits may be constantly updated. The half-full, half-empty, full and empty flags are generated and updated
regardless of the states of their respective interrupt enables. The SIG also receives the four interrupt enables for
the flags. The SIG also receives the sequencer active and the three vector active signals from the SSI. These
are also updated regardless of the enable state.
12
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
If an interrupt enable is set then an interrupt will be generated. If an interrupt occurs at the same time as the
interrupt status is being read, then the interrupt will be set after the read is complete. All bits in the Interrupt
Status register are cleared when the register is read.
FLAG GENERATOR
The FG takes in the TDI_SM or TDO_SM pointer values from the PPI address pointers, compares them and
generates the appropriate flags. If a flag condition has occurred, it is passed, along with the corresponding load
enable, to the SIG to set the bit in the status register. If the flag condition changes, then the clear for the
corresponding bit is passed to the SIG to clear the flag. The TDO_SM empty and the TDI_SM full flags are
passed to the SSI also. A counter enable is passed from the SSI to indicate to the FG when the SSI's pointer
value has changed. If a decrement and an increment occur at the same time to either of the counters, the
counter value will not change.
PPI INTERFACE TIMING
The processor accesses to SCANSTA101 can be classified into six categories:
•
•
•
•
•
•
register read
register write
16-bit memory read
16-bit memory write
32-bit memory read
32-bit memory write
Register reads and register writes are performed the same whether the device is in 16-bit mode or 32-bit mode.
In 32-bit mode, only the LS word is used. The MS word is ignored. The timing for the 16-bit and 32-bit modes is
exactly the same.
The 16-bit mode memory write is accomplished by performing two consecutive register writes with the only
difference being that the actual write occurs on the second access. The 16-bit mode register read consists of two
accesses, with the first access performed similar to the 16-bit register read but requiring one more clock to
complete the memory access. Since all 32-bits of the memory data are captured on the first access, the second
memory read access is 2 clocks shorter than the first.
The processor initiates a write cycle by asserting CE followed by STB. A set time prior to asserting STB, the R/W
is driven low and the address and data buses are driven by valid address and data, respectively. After edge
detecting the STB and registering all the inputs, the address is decoded to determine which internal address
within the SCANSTA101 will be written by the processor. The DTACK will be asserted on the same rising edge
of SCK on which the negative edge of the STB signal is detected, indicating to the processor that it can deassert
the STB. When the SCANSTA101 detects the positive edge of the STB, it will deassert the DTACK indicating to
the processor that it can start a new cycle. The processor can start a new cycle by asserting the STB and by
driving the address and data buses with new address and data.
A read cycle is similar to the write cycle except that the DTACK will not be asserted until the selected address
location's contents are loaded. So, for a 16-bit register read it takes one more clock than it does for a write cycle.
Reads and writes to the SCANSTA101 memory require two consecutive accesses in the 16-bit external bus
mode. The memory writes are similar to register writes; the processor performs two consecutive 16-bit writes to
write to the selected memory location.
During a memory read, the DTACK line is not asserted until the contents of the memory is loaded into the
capture registers. For this reason the first read from the memory requires five clocks which includes the memory
access time, while the second read is done in three clock cycles.
SERIAL SCAN INTERFACE
The Serial Scan Interface consists of the following units:
•
•
•
•
Clock Divider and TCK_SM Control
TAP Tracker
Pointer Generator
Structure (Sequencer/Vector/Macro/ScanBridge) Decoder
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
•
•
•
•
•
•
Structure (Sequencer/Vector/Macro/ScanBridge) Control Registers
Count Generator
Shifter (TDO_SM/TDI_SM/TMS_SM)
Comparator
Expected and Mask Registers
Serial Scan Interface Controller (SSIC) and ScanBridge Controller
The clock divider unit divides the system clock SCK based on the programmable divisor set in the clock divider to
generate TCK_SM. The TCK_SM control unit gates TCK_SM if the TDO_SM buffer is empty.
The TAP Tracker unit tracks the target's TAP controller state. The TAP Tracker determines whether the target's
TAP controller is in SIR or SDR state, so that the necessary pad bits are inserted.
The shifter block contains two 32-bit shift registers for TDO_SM and TDI_SM respectively, and a 16-bit shift
register for TMS_SM.
The comparator unit compares the serial input on the TDI_SM pin with the expected data, bit by bit, if the
compare bit of the Macro Structure is set. If the compare/mask bit is set, then the comparator unit compares only
those bits that are unmasked.
Expected and Mask Registers contain the data fetched from the memory. This data is used by the comparator to
compare the TDI_SM input with the expected data.
The SSIC provides the timing and control signals to synchronize the operation of the various blocks in the SSI.
The ScanBridge Controller consists of the control logic to set up the ScanBridge hierarchy, if the ScanBridge
Support Initiate/Release bit is enabled, prior to scanning test vectors out of TDO_SM.
CLOCK DIVIDER AND TCK_SM CONTROL
The clock divider is a binary divider with only one bit of the clock divider register set to one at any given time.
The SCANSTA101 SSI ignores bits 0, and 8-15 of the clock divider register, so the supported divisors are 2, 4, 8,
16, 32, 64 and 128.
To generate a TCK_SM of frequency SCK/4, the clock divider register should be set to 4 (00000100). This will
enable the gate at the output of bit 2 of the counter to generate a clock of SCK divided by 4. If in LotF mode, the
TCK_SM enable from the SSIC will gate TCK_SM when the TDO_SM buffer is empty.
TAP TRACKER
The TAP Tracker consists of a 16-bit register to track the IEEE Standard 1149.1 TAP state machine. The register
is one-hot encoded (meaning that only one bit in the TAP tracker register, corresponding to the current TAP
state, is set at a time) and will continuously track the target's TAP Controller based on the TMS_SM sequence.
The TAP Tracker is used by the ScanBridge support controller to determine whether the target's TAP controller is
in SIR or SDR state so that it can insert an appropriate number of pre and post-shift pad bits.
The TAP Tracker will enter Test-Logic Reset state upon setting the TRST bit (bit 5) in the Setup register or by
issuing a sequence of five TMS_SM high bits.
SHIFTER
The Shifter block contains two 32-bit shift registers for TDO_SM and TDI_SM respectively, and one 16-bit shift
register for TMS_SM. The TMS_SM shifter block diagram is shown in Figure 3, the TDO_SM shifter block
diagram is shown in Figure 4, and the TDI_SM shifter block diagram is shown in Figure 5.
Before the start of a vector processing the TMS_SM shifter is loaded with the least significant 16 bits of the
macro structure. Based on the pre-shift TCK_SM count, the TMS_SM shifter will skip (7 - pre-shift count) least
significant bits. e.g., if the pre-shift count is 4, the least significant 3 bits of the TMS_SM shifter will not be used to
drive TMS_SM during pre-shift. Similarly, if the post-shift is less than 7 then, during post shift only the number of
bits equal to the post-shift count following the macro structure bit 8 will be used to drive TMS_SM.
14
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
The SCANSTA101 memory is organized in big endian format. A memory write is accomplished by two
consecutive writes to the same location. When embedded software loads the TDO_SM memory, the least
significant 16 bits are written first and then the most significant 16 bits. Therefore, when the Sequencer or a
Vector is initialized the SSIC can directly fetch and load the long word to the TDO_SM shifter without any
modification.
Figure 3. TMS_SM Shifter
Figure 4. TDO_SM Shifter
Figure 5. TDI_SM Shifter
Reading from TDI_SM memory is accomplished by two consecutive reads. When reading from the TDI_SM
memory, the first read will contain the least significant 16 bits and the second read the most significant 16 bits.
The TDI_SM shifter unit consists of two 32-bit shift registers as shown in Figure 5. The shift register on top in the
figure is the LFSR register. Before using the TDI_SM LFSR register, the LFSR Exponent and LFSR Seed
registers must be written with valid data. The LFSR Exponent register must be written with a 3-bit binary
encoded value that selects one of the five available polynomials. The value written to the LFSR Seed registers is
used to initialize the TDI_SM LFSR register to a predetermined state. Once the test vector has completely
scanned in, the final contents of the LFSR register are transferred to the LFSR Result registers.
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
The 32-bit shift register at the bottom is used to shift in TDI_SM directly in normal mode or to shift in TMS_SM or
TDO_SM in the loop-back mode. After each long word of 32 bits is shifted into this register, the contents of the
register are transferred to the corresponding TDI memory location before the next shift operation.
SHIFTER IMPLEMENTATION
Shift register implementation is illustrated in Figure 6. Shift out enable for the TMS_SM and TDO_SM shifters is
generated by comparing the clock pulse counter output to the clock divider - 1. Shift in enable for the TDI_SM
shifter is generated by comparing the clock pulse counter to the programmable divisor/2 - 1. These enables are
gated by the control signals from SSIC so that data are shifted out (TMS_SM/TDO_SM) or shifted in (TDI_SM)
only when necessary.
Figure 6. Shift Register Implementation and Timing
16
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
COMPARATOR AND EXPECTED/MASK REGISTERS
The One-Bit Comparator, when enabled, compares the TDI_SM input with expected data. When the compare
feature is enabled (in preloaded vector mode only) the SSIC pre-fetches data into Expected and Mask registers
from the address locations for the current vector being processed. The comparator will compare each bit on the
TDI_SM input with the corresponding bit from the expected register. If the mask feature is enabled, then the
comparison is performed only on those bits that are not masked, i.e., on those bits for which the mask is set to
zero. Table 11 shows how the Compare and Use Mask/Compare bits in the Macro Structure are used.
Table 11. Compare and Use Mask/Compare Bit Descriptions
Compare
Use Mask/Compare
Description
0
0
1
1
0
1
0
1
Do Not Compare
Compare with Mask
Compare without Mask
Compare with Mask
The Results of Compare bit (bit 15 of Status register) stores the comparison results in the status register. This bit
defaults to fail (zero) and will be updated only after the current vector is processed. In the case of a single vector
the Results of Compare bit will be set to one (pass) only if all the bits in the scanned in vector match the
expected vector. However, in the case of the sequencer only the results of final vector comparison will be taken
into account.
Each vector within the sequencer is repeated until the vector repeat count is exhausted. The sequence is
repeated until the sequencer repeat count is exhausted.
Figure 7 illustrates the compare logic.
After reset and before every sequencer process, flip-flops 1 and 3 are initialized to zero while flip-flop 2 is set to
1. When the compare feature is enabled flip-flop 1 is continuously updated with the immediate comparison
results (1 for pass and 0 for fail). Flip-flop 2 is reset to zero when a mismatch occurs and remains in this state for
the remainder of the current vector processing. When the current vector is completely processed flip-flop 3
(Results of Compare register) will be updated with the current status.
Figure 7. Compare Logic
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
SERIAL SCAN INTERFACE CONTROLLER AND SCANBRIDGE CONTROLLER
The Serial Scan Interface Controller (SSIC) remains in the Idle state until new data are written to the Start
register. When this event occurs the following operations are performed:
1. If the ScanBridge Support Initiate/Release bit was not set previously and is currently set in the Setup
register, the SSIC initializes the ScanBridge Controller (SBC) to perform the following steps to set up all
ScanBridges in the hierarchy.
(a) Determine the number of levels of ScanBridge support to be inserted (from the ScanBridge support
structure)
(b) Sequence TMS_SM so that all ScanBridges in the same level of hierarchy enter the SIR state, and then
shift in the address (from the ScanBridge structure) to select a ScanBridge in the current level of
hierarchy. The ScanBridge's TAP controller is then sequenced through the Update-IR state.
(c) Sequence TMS_SM so that the selected ScanBridge's TAP controller enters the SIR state, then scan in
the MODESEL instruction to put its mode register in the data path.
(d) Sequence the selected ScanBridge's TAP controller to enter the Shift-DR state and scan in the LSP
contents (from the ScanBridge structure) into its mode register. The ScanBridge's TAP controller is then
sequenced through the Update-DR state.
(e) Repeat Step 1C, but this time scan in the UNPARK instruction so that the LSP is inserted into the active
scan chain.
(f) Sequence the ScanBridge's TAP controller to enter the RTI state (the LSP will not be unparked until its
TAP controller enters RTI).
(g) Repeat Steps 1B through Step 1G to configure the ScanBridges in the remaining hierarchy levels. One
set of pre-shift pad and post-shift pad bits is added to the patterns for each hierarchy level between the
STA Master and the ScanBridge being configured. The pad bits are used to bypass the intermediate
levels of hierarchy.
(h) For the subsequent vectors, if the TAP Tracker enters the
(a) SDR state, the SCANSTA101 will add one pre-shift bit for the pad register and one post-shift bit for
the bypass register for each level of hierarchy.
(b) SIR state, the SCANSTA101 will add one pre-shift bit for the pad register and eight post-shift bits for
the ScanBridge instruction register for each level of hierarchy. The eight post-shift bits will be all
ones, forcing the ScanBridge into bypass mode.
(i) The pad bits need to be stripped when loading a vector into TDI_SM. This will be done by having a
status flag to indicate whether the vector that is being scanned out has ScanBridge support or not. If the
scanned-out vector has ScanBridge support, then the pad bits will be stripped when the TAP Tracker
enters the SDR or SIR states.
2. If the ScanBridge Support Initiate/Release bit was set previously and is currently reset in the Setup register,
the SSIC will toggle TCK_SM five times while TMS_SM is held high. This will return all selected ScanBridges
to the wait-for-address state and park the LSPs in the Test-Logic-Reset state. When the ScanBridge support
is released the user should make sure that the Use Vector and Use Sequencer bits in the Start register are
not set, so that the SSIC will not start processing a vector or the sequencer immediately after releasing the
ScanBridge support. Once the ScanBridge support is released the user may start processing a vector or the
sequencer by writing to the Start register.
3. If the sequencer is enabled (the Use Sequencer bit in the Start register is one),
(a) Clear the Results of Compare bit and set the Using Sequencer bit in the Status register.
(b) Fetch the sequence repeat count.
(c) If the sequence repeat count is zero, the sequence is complete so reset the Using Sequencer bit and
return to the Idle state, otherwise fetch the next vector number and its repeat count.
(d) If the vector number is zero, decrement the sequence repeat count and return to Step 3C. If the vector
number is illegal, i.e., other than 001, 010, 011, or 100, decrement the sequence repeat count and return
to Step 3C.
(e) If the vector repeat count is equal to zero, fetch the next vector number and its repeat count and go to
Step 3D. If the repeat count is non-zero fetch the vector structure.
(f) If the pre-load bit in the vector structure is not set, reset the Using Sequencer bit and return to the Idle
state.
4. If the sequencer is not enabled but a vector is enabled (the Use Vector bits in the Start register are non-
zero), fetch the current vector structure and set the appropriate Using Vector bits in the Status register. If
neither the sequencer nor a vector is enabled, return to the Idle state.
5. Fetch the Macro Structure to be used, set the vector/macro control bits and store the TMS_SM bits in the
18
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
Structure Control registers.
6. If the Pre-shift TCK_SM Count is not zero, then enable TCK_SM and drive TMS_SM using the first seven
bits of the macro until the Pre-shift TCK_SM Count is zero. During pre-shift, TDO_SM will be driven with its
previous value.
7. If the macro type is State then,
(a) If the Macro Structure Bit 7 is enabled, set TMS_SM to the bit 7 value of the macro structure and drive
TDO_SM with its previous value.
(b) If the Macro Structure Bit 8 is enabled, set TMS_SM to the bit 8 value of the macro structure and drive
TDO_SM with it's previous value and then go to Step 10.
(c) If the sequencer is being used, then decrement the vector repeat count and return to Step 3E. If a vector
is being used, return to the Idle state.
8. If the macro type is BIST then,
(a) If the Macro Structure Bit 7 is enabled, set the count length, set TMS_SM to the bit 7 value of the macro
structure and drive TDO_SM with the default value (Setup register bit 6) until the count length is zero.
(b) If the Macro Structure Bit 8 is enabled, set TMS_SM to the bit 8 value of the macro structure and drive
TDO_SM with the default value (Setup register bit 6) and then go to Step 10.
(c) If the sequencer is being used then, decrement the vector repeat count and return to Step 3E. If a vector
is being used, return to the Idle state.
9. If the macro type is Shift or Shift with Capture then,
(a) If the macro type is Shift with Capture, enable TDI capture.
(b) If the Sync Bit Support Enable bit is set, fetch sync bit count, set the count length, set TMS_SM to the
loop bit and drive the TDO_SM high until sync bit count is zero.
(c) If the ScanBridge Support Initiate/Release bit is set, drive the TDO_SM with pre- PAD bit (high) and
while TMS_SM remains set to the loop bit. Repeat for each level of hierarchy.
(d) If the Use Data/Instruction Header is enabled, fetch the header length and data, set the count length, and
drive the TDO_SM with header data until the header length is zero and while TMS_SM remains set to
the loop bit.
(e) If the Compare or Mask/Compare is set, enable the comparator.
(f) Set the vector count length, and drive the TDO_SM with vector data until the count length is one and
while TMS_SM remains set to the loop bit. In the LotF mode if the count length is not zero and the TDO
buffer is empty, then gate TCK_SM until more data are available in the TDO buffer. When TCK_SM is
disabled TMS_SM and TDO_SM will be driven with their previous values.
(g) If the Use Data/Instruction Trailer is enabled, fetch the trailer length and data, set the count length, and
drive TDO_SM with trailer data until the trailer length is one and while TMS_SM remains set to the loop
bit.
(h) If the ScanBridge Support Initiate/Release bit is set:
(a) If the TAP tracker is in the Shift-IR state and the number of levels of hierarchy is greater than one,
set the count length to eight, and drive TDO_SM with post-shift pad bits (all high) until the count
length is zero for each level of hierarchy and while TMS_SM remains set to the loop bit.
(b) If the TAP tracker is in the Shift-DR state and the number of levels of hierarchy is greater than one,
drive TDO_SM with a post-shift pad bit (high) for each level of hierarchy and while TMS_SM remains
set to the loop bit.
(c) For the final level of hierarchy or if there is only one level of hierarchy, and if the TAP tracker is in the
Shift-IR state, set the count length to eight, and drive TDO_SM with post-shift pad bits (all high) until
the count length is one and while TMS_SM remains set to the loop bit.
(i) If the Sync Bit Support Enable is set, fetch sync bit count, set the count length, and drive the TDO_SM
high until sync bit count is one and while TMS_SM remains set to the loop bit.
(j) Set TMS_SM to bit 8 of the TMS_SM Macro Structure sequence and drive TDO_SM with the final vector
bit or trailer bit or post-shift pad bit or sync bit. After shifting out the final vector bit, disable the
comparator and register the comparison results.
10. If the post-shift TCK_SM Count is not zero, then enable TCK_SM and drive TMS_SM using the last seven
bits of the macro until the post-shift TCK_SM Count is zero.
11. If the Sequencer is being used,
(a) Decrement the sequence repeat count and return to Step 3C if the Compare or Mask/Compare is
enabled and the results of compare is a fail.
(b) Decrement the vector repeat count and return to Step 3E if the if the Compare or Mask/Compare is
enabled and the results of compare is a pass.
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
(c) Decrement the vector repeat count and return to Step 3E if the Compare or Mask/ Compare is not
enabled.
12. If the Vector is being used return to the Idle state.
MODE REGISTER WRITE TO VECTOR/SEQUENCER START
Figure 8 shows the timing from the processor write to the start of vector processing. Figure 9 shows the timing
from the processor write to the start of sequencer processing. A processor write to the Start registers is indicated
by a "new data" pulse. On the same SCK rising edge when the "new data" is detected to be high, the Start or
Setup register contents will be updated with new data. So, the decoding of the enables takes place during the
next clock cycle to determine whether to process the sequencer or a vector. Therefore, one clock after the "new
data" is detected, the SSIC starts loading the pointer register on consecutive cycles with the appropriate
addresses to fetch the Sequencer, Vector and Macro Structures. Once the headers are decoded and Structure
Control Registers are set up, the SSIC loads the pointer register so that data from the TDO_SM memory area is
fetched and loaded into the TDO_SM shifter before being shifted out. However if there are any sync bits and/or
header bits and/or ScanBridge support is enabled, then the sync bits and/or header bits and/or ScanBridge pre-
PAD bits will be loaded into the TDO_SM shifter before processing the actual test vector. Once the actual test
vector is completely shifted out, again depending on the ScanBridge support and/or the use of trailers, post-PAD
bits and the trailer bits are loaded and shifted out through the TDO_SM shifter.
The count length will be decremented by one with each shift. After shifting out all the current shifter contents the
shifter will be loaded with new data before the falling edge of the next TCK_SM, if the count length is not
exhausted. In the case where data cannot be loaded from the memory before the next falling edge of TCK_SM,
the TCK_SM will be gated until the data is available.
Figure 8. Timing from Mode Register Write to Vector Start
Figure 9. Timing from Mode Register to Sequencer Start
20
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
WRITING AND READING PARTIAL LONG WORDS
Care should be taken when writing a partial long word to TDO_SM memory or reading a partial long word from
TDI_SM memory. Since the TDO_SM shifter shifts out LSB first, the valid (meaningful) bits within a partial long
word (i.e., long word containing less than 32 valid bits to be shifted to the scan chain) must be stored and written
into the memory as the least significant bits. This will assure that the desired bits will be accurately loaded into
the TDO_SM shifter and shifted out to the boundary scan chain. For instance, to shift a 3-bit (110) sequence the
partial long word should be written to the TDO_SM memory as shown in Figure 10 (only the least significant 16
bits are shown). A subsequent enable and load of the vector structure with the correct length will initialize the
shift operation and only the bits that are significant will be shifted out to the scan chain.
Figure 10. Writing a Partial Long Word to the TDO_SM Memory
Data is shifted from the scan chain into the TDI_SM shifter from MSB to LSB. Consequently, the valid
(meaningful) bits in a partial long word shifted into the TDI_SM shifter will reside in the upper significant bit
locations. For example, if a scan operation involves shifting and evaluating 69 bits returning to TDI_SM, the
TDI_SM memory will be loaded with two long words (i.e., two full long words plus a partial long word containing 5
meaningful bits). If the last 5 bits shifted back to the TDI_SM shifter are 11010, then upon completion of the shift
operation, the TDI_SM shifter will contain the following partial long word as shown in Figure 11 (only the most
significant 16 bits are shown), which will subsequently be loaded into the TDI_SM memory.
Following a read of a partial long word, the embedded test software must adjust the position of the valid bits read
from the TDI_SM shifter/buffer or the position of the expected data to assure that an accurate comparison is
made (and the non-meaningful bits are masked).
Figure 11. Reading a Partial Long Word from the TDI_SM Memory
TDO_SM IMPLEMENTATION
The behavior of the TDO_SM output depends on the macro type that is being processed and the SETUP register
bits 11 and 10, as shown in Table 12, regardless of the TAP tracker state. For shift macros, the TDO_SM output
also depends on the current macro structure's TMS_SM bit number as explained below.
Table 12. TDO_SM Output Behavior
SETUP[11:10]
TDO_SM
00
Hold Previous value
(1)
01 or 10
11
Default TDO value (Bit 6 of the SETUP register)
High Impedance
(1) Default TDO value (bit 6 of the SETUP register) may be set to a 0 when SETUP[11:10]=01 and to a 1 when SETUP[11:10]=10.
For BIST and STATE macros, the TDO_SM output behaves as shown in the above table.
For the shift macros, with or without capture, the TDO_SM output behaves as per the table only when the
corresponding TMS_SM output is not driven by the macro structure bit 7 or 8. On each falling edge of the
TCK_SM following the TCK_SM falling edge on which the TMS_SM changes state from bit 6 of the macro
structure to bit 7 of the macro structure, the serial test vector data fetched from the memory is presented on the
TDO_SM output. On the falling edge of the TCK_SM on which the final bit of the test vector is presented on the
TDO_SM output, the TMS_SM is presented with macro structure bit 8. On the subsequent TCK_SM falling
edges, and on the TCK_SM falling edges before the TMS_SM changes state from bit 6 to bit 7 of the macro
structure, the TDO_SM will behave as per the table above.
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
HARDWARE INTERFACE DETAILS
Table 13. System Interface Signal Description
Signal Name
SCK
No. of
Bits
Pin Type
Driver Type
Freq. MHz Description
1
I
LVTTL
66
System Clock: This is the main clock signal to the SCANSTA101.
SCK is used to clock all internal circuitry
RST
1
I,H
LVTTL
N/A
Hardware Reset signal (with hysteresis (H)): This is the
SCANSTA101 asynchronous reset signal. This signal resets the
entire SCANSTA101 and sets all registers to their respective
default values.
OE
1
I
LVTTL
N/A
Output enable: will TRI-STATE all 1149.1 outputs when high.
Table 14. Parallel Processor Interface Signal Descriptions
Signal Name
No. of
Bits
Pin Type
Driver Type
Freq. MHz Description
DATA(31:16)
16
I/O
LVTTL (weakest
driver)
N/A
Bidirectional Data Bus. Not bonded out in packaged part. These
are only used in the 32-bit macro version.
DATA(15:0)
ADDRESS(4:0)
CE
16
5
I/O
LVTTL
LVTTL
LVTTL
N/A
N/A
N/A
Bidirectional Data Bus.
I
I
Address Bus
1
Chip Enable, when low, enables the PPI for transfers.
DATA(31:0) and DTACK are tristated when CE is high.
R/W
STB
1
1
I
I
LVTTL
LVTTL
N/A
N/A
Read/Write defines a PPI cycle. Read when high, write when low.
Strobe is used for timing all PPI transfers. DATA(31:0) are
tristated when STB is high. Data valid setup is with respect to the
falling edge of STB and data valid hold is with respect to rising
edge of STB.
DTACK
1
1
O
O
O/D
N/A
N/A
Data Acknowledge (open drain - sustained tristate). DTACK is
used to synchronize asynchronous transfers between the host
and the SCANSTA101. During write cycles, DTACK goes low
when data has been registered and then goes to high impedance
when the cycle has been completed. During read cycles DTACK
goes low when data bus is driven with the valid data and then
goes to high impedance when the cycle has been completed.
INT
LVTTL
Interrupt is used to trigger a host interrupt for any of the defined
interrupt events. Signal is active high.
Table 15. Serial Scan Interface Signal Descriptions
Signal Name
TDI_SM
No.
1
Pin Type
Driver Type
LVTTL
Freq. MHz
Description
I
up to 25 ScanMaster Test Data Input (weak pullup)
up to 25 ScanMaster Test Data Output
up to 25 ScanMaster Test Mode Select
up to 25 ScanMaster Test Clock
TDO_SM
1
O
O
O
O
O
O
LVTTL
TMS_SM
1
LVTTL
TCK_SM
1
LVTTL
TRST0_SM
TRST1_SM
TRIST_SM
1
LVTTL
N/A
N/A
N/A
ScanMaster Test Reset
1
LVTTL
Redundant ScanMaster Test Reset (not bonded out)
1
LVTTL
The tristate notification pin exerts a high when TDO_SM is
tristated.
22
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
Figure 12. PPI Write Cycle Timing Diagram
Figure 13. PPI Read Cycle Timing Diagram
Figure 14. SSI Timing Diagram with Clock Divider set to 4
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
Figure 15. SSI Timing Diagram with Clock Divider set to 8
Table 16. SCANSTA101 1149.1 Signal Descriptions
No. of
Bits
Signal Name
Pin Type
Driver Type
Freq. MHz
Description
TDO
TDI
1
1
1
1
1
O
I,U
I,U
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
up to 25 SCANSTA101 Test Data Out
up to 25 SCANSTA101 Test Data In (pullup (U))
up to 25 SCANSTA101 Test Mode Select (pullup (U))
up to 25 SCANSTA101 Test Clock
TMS
TCK
TRST
I,U,H
N/A
SCANSTA101 Test Reset (pullup (U) & hysteresis (H))
SAFE MODE
This device implements the following design rules to provide Single Event Upset/Single Event Error (SEU/SEE)
protection:
•
•
Triple modular redundancy (TMR) for TRST0_SM and TRST1_SM outputs with the help of a TMR D flip-flop .
After reset all scan interface outputs are driven to SEU tolerant safe values as shown below:
–
–
–
–
–
TMS_SM = 1
TCK_SM = 0
TDO_SM = high-Z
TRST0_SM = 0
TRST1_SM = 0
•
The EXTEST and the HIGHZ outputs from the JTAG TAP controller are gated with TRST to protect the
boundary scan cells from inadvertently entering the test mode.
CLOCK GENERATION AND DISTRIBUTION
Input Clock (SCK): Up to 66 MHz
Output Clock (TCK_SM): TCK_SM is a divided, registered version of SCK.
•
•
Selectable: to 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, and 1/128 of SCK.
Frequency: up to 25 MHz
24
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
RESET STRATEGY
The incoming external hardware reset (RST) will be synchronized to the incoming clock (SCK) and is combined
with the soft reset to generate a synchronized internal reset (SYS_RST_N). During operation, the chip can be
reset by writing a '1' to the Reset bit in the Setup register. All logic throughout the device will be initialized, all
control and status registers will be in a known default state, all PPI memory address pointers will default to their
respective base addresses, the SSI memory pointer will default to zero, the Tap Tracker will be reset to TLR, and
the clock division counter will be initialized to all zeroes after deassertion of the internal reset. The Reset bit in
the Setup register is self clearing. The TRST bit in the Setup register, when set, resets the SSI logic and drives
the TRST0_SM and TRST1_SM to zero.
SOFTWARE INTERFACE DETAILS
REGISTER DEFINITIONS
The following sections include descriptions of each addressable register in the ScanMaster memory space.
Following the title of the particular register, the mnemonic for the register is included in parentheses as well as
the physical address location in hexadecimal notation (value preceded by $). KEY- RO: Read Only; RW:
Read/Write.
Table 17. Start Register (START) ($00)
Bit(s)
15:14
13
Type
RO
Field
Address Offset
Reset Value
00b
Reset Source
SYS_RST
Reserved
0
0
0
0
0
0
RW
RO
Onboard Memory BIST
Reserved
0b
12:9
8
0000b
0b
RW
RO
Use Sequencer
Reserved Use Vector x
Use Vector x
SYS_RST
(1)
7:3
0000h
000b
2:0
RW
SYS_RST
(1) Reserved Use Vector x for future growth for the number of vectors.
Onboard Memory BIST
ScanMaster memory BIST enable. This bit is self clearing when BIST result is written to the Memory
BIST Result bit in the Status register.
'1'
Initiate on chip memory BIST
On chip memory BIST complete
Sequencer enable/disable (For preloaded vectors only)
Enable sequencer
'0'
Use Sequencer
'1'
'0'
Disable sequencer
Use Vector <2:0>
Use Vector x designates the vector "x" which is enabled, where "x" is the vector number, a binary
encoding of bits <2:0>. Only vectors 1 through 4 are valid. Vectors 5 through 7 reserved for future
use.
'000'
'001'
'010'
'011'
'100'
No vector enabled
Vector 1 enabled
Vector 2 enabled
Vector 3 enabled
Vector 4 enabled
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
(1)
Table 18. Status Register (STATUS) ($01)
Bit(s)
15
14
13
12
11
10
9
Type
RW
RW
RW
RW
RW
RW
RW
RW
RO
Field
Address Offset
Reset Value
Reset Source
(2)
Results of Compare
0
0
0
0
0
0
0
0
0
0
0b
0b
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
BIST Running
Memory BIST Result
TDO Status Half-empty
TDO Status Empty
TDI Status Full
0b
(3)
0b
0b
0b
(3)
TDI Status Half-full
0b
8
Using Sequencer
0b
(4)
7:3
2:0
Reserved Using Vector x
Using Vector x
00000b
000b
RW
SYS_RST
(1) Write capability to the register is only for test and debug purposes. Drivers should disable writes to the register during normal operation.
(2) Results of Compare bit is toggled after a compare is complete and it is set to the mismatch state when sequencer is kicked off again.
Remains in last state until next compare completed or until set to the mismatch state.
(3) Half full or half empty designates 56 long words.
(4) Reserved Using Vector x for future growth for the number of vectors.
Results of Compare
Results of compare between TDI_SM and Expected memory space
Compare match
'1'
'0'
Compare mismatch
BIST Running
Indicates the BIST operation is still active
BIST operation active
'1'
'0'
BIST operation complete or BIST operation not running
ScanMaster BIST result. BIST result will be held until overwritten by next BIST operation.
Passed memory BIST
Memory BIST Result
'1'
'0'
Failed memory BIST
TDO Status Half
TDO_SM memory space status half empty
TDO_SM memory space half empty
TDO_SM memory space not half empty
TDO_SM memory space status empty
TDO_SM memory space empty
'1'
'0'
TDO Status Empty
'1'
'0'
TDO_SM memory space not empty
TDI_SM memory space status full
TDI_SM memory space full
TDI Status Full
'1'
'0'
TDI_SM memory space not full
TDI Status Half
TDI_SM memory space status half full
TDI_SM memory space half full
'1'
'0'
TDI_SM memory space not half full
Sequencer active and processing. Bit cleared when sequence complete.
Sequencer active
Using Sequencer
'1'
'0'
Sequencer inactive
Using Vector<2:0>
Using Vector x designates the vector "x" currently running, where "x" is the vector number, a binary encoding of
bits <2:0>. Only vectors 1 through 4 are valid. Vectors 5 through 7 reserved for future use. Field cleared when
vectors complete.
'000'
'001'
'010'
'011'
'100'
No vector active.
Vector 1 active.
Vector 2 active.
Vector 3 active.
Vector 4 active.
26
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
Table 19. Interrupt Control Register (INTCTRL) ($02)
Bit(s)
15:13
12
Type
RO
Field
Address Offset
Reset Value
Reset Source
Reserved
0
0
0
0
0
0
0
0
000b
0b
(1)
RW
RW
RW
RW
RW
RO
TDO Half-empty Interrupt Enable
TDO Empty Interrupt Enable
TDI Full Interrupt Enable
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
11
0b
10
0b
(1)
9
TDI Half-full Interrupt Enable
0b
(2)
8
Sequencer Interrupt Enable
0b
(3)
7:3
2:0
Reserved Vector x Interrupt Enable
00000b
000b
(2)
RW
Vector x Interrupt Enable
SYS_RST
(1) Half full or half empty designates 56 long words.
(2) Drivers should not allow Sequencer Interrupt Enable and Vector x Interrupt Enable to be set at same time. Sequencer Interrupt Enable
has priority over the Vector x Interrupt Enable.
(3) Reserved Vector x Interrupt Enable for future growth for the number of vectors.
TDO Half-empty Interrupt Enable
TDO_SM memory space half empty interrupt enable
Enable TDO_SM memory space half empty interrupt
Disable TDO_SM memory space half empty interrupt
TDO_SM memory space empty interrupt enable
Enable TDO_SM memory space empty interrupt
Disable TDO_SM memory space empty interrupt
TDI_SM memory space full interrupt enable
Enable TDI_SM memory space full interrupt
Disable TDI_SM memory space full interrupt
TDI_SM memory space half full interrupt enable
Enable TDI_SM memory space half full interrupt
Disable TDI_SM memory space half full interrupt
Sequencer activity complete interrupt enable
Enable Sequencer activity complete interrupt
Disable Sequencer activity complete interrupt
'1'
'0'
TDO Empty Interrupt Enable
'1'
'0'
TDI Full Interrupt Enable
'1'
'0'
TDI Half-full Interrupt Enable
'1'
'0'
Sequencer Interrupt Enable
'1'
'0'
Vector Interrupt Enable<2:0>
Vector "x" complete interrupt enable, where "x" is the vector number, a binary encoding of bits
<2:0>. Only vector interrupts 1 through 4 are valid. Vector interrupts 5 through 7 reserved for future
use.
'000'
'001'
'010'
'011'
'100'
No vector interrupt enabled
Vector 1 interrupt enabled
Vector 2 interrupt enabled
Vector 3 interrupt enabled
Vector 4 interrupt enabled
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
(1)
Table 20. Interrupt Status Register (INTSTAT) ($03)
Bit(s)
15:13
12
Type
RO
Field
Address Offset
Reset Value
Reset Source
Reserved
0
0
0
0
0
0
0
0
00b
0b
(2)
RW
RW
RW
RW
RW
RO
TDO Half-empty Interrupt
TDO Empty Interrupt
TDI Full Interrupt
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
11
1b
10
0b
(2)
9
TDI Half-full Interrupt
0b
8
Sequencer Interrupt
0b
(3) (4)
7:3
2:0
Reserved Vector x Interrupt
00000b
000b
(4)
RW
Vector x Interrupt
SYS_RST
(1) This register is writable in debug mode only.
(2) Half full or half empty designates 56 long words.
(3) Reserved Vector x Interrupt for future growth for the number of vectors.
(4) Drivers shouldn't allow Sequencer Interrupt and Vector x Interrupt to be set at same time. Sequencer Interrupt has priority over the
Vector x Interrupt.
TDO Half-empty Interrupt
TDO_SM memory space half empty status
TDO_SM memory space half empty
TDO_SM memory space not half empty
TDO_SM memory space empty status
TDO_SM memory space empty
TDO_SM memory space not empty
TDI_SM memory space full status
TDI_SM memory space full
'1'
'0'
TDO Empty Interrupt
'1'
'0'
TDI Full Interrupt
'1'
'0'
TDI_SM memory space not full
TDI Half-full Interrupt
TDI_SM memory space half full status
TDI_SM memory space half full
TDI_SM memory space not half full
Sequencer completed status
'1'
'0'
Sequencer Interrupt
'1'
'0'
Sequencer processing completed
Sequencer processing or not started
Vector Interrupt<2:0>
Vector "x" completed status, where "x" is the vector number, a binary encoding of bits <2:0>. Only
vectors 1 through 4 are valid. Vectors 5 through 7 reserved for future use.
'000'
'001'
'010'
'011'
'100'
No vector completed activity
Vector 1 completed
Vector 2 completed
Vector 3 completed
Vector 4 completed
Table 21. Setup Register (SETUPR) ($04)
Bit(s)
15
Type
Field
Address Offset
Reset Value
Reset Source
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
16/32 bit Mode
Reserved
0
0
0
0
0
0
0
0
0
0
0b
00h
00b
000b
1b
SYS_RST
14:10
11:10
9:7
6
TDO_SM Ctrl
Sync Bit Length
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
Default TDO Value
5
Debug Mode
0b
4
ScanBridge Support Initiate/ Release
0b
3
TRST
0b
2
Reset
0b
1:0
Test Loop-Back
11b
28
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
16/32 bit Mode
Selects 16-bit or 32-bit external interface mode
32-bit external interface mode (used in macro form only)
16-bit external interface mode
TDO_SM Control bits
'1'
'0'
TDO_SM Ctrl<11:10>
'00'
Hold previous value
'01'
Default TDO Value
'10'
'11'
Default TDO Value
High impedance
Sync Bit Length "x"
Sync Bit Length bits represents the number of sync bits to be used when the Sync Bit Support
Enable bit (17 in the Macro Structure) is set. The value "x" is the binary encoded numeric value.
Default TDO Value
The value in this register will be sent out on the TDO_SM pin when performing a BIST or a STATE
Macro.
'1'
Drive TDO_SM to one.
Drive TDO_SM to zero.
Control bit to put SCANSTA101 in debug mode
Debug mode.
'0'
Debug Mode
'1'
'0'
Normal mode.
ScanBridge Support Initiate/Release ScanBridge support enable
'1'
'0'
Enable ScanBridge support
Disable ScanBridge support
TRST
Reset
Processor initiated ScanMaster test reset (on TRST0_SM and TRST1_SM_N). Bit is cleared by a
processor write.
'1'
'0'
Set TRST outputs low (active) and reset SSI logic.
Set TRST outputs high
Processor commanded synchronous reset to the serial scan logic for 2 clocks. This bit is self
clearing.
'1'
'0'
Reset the entire chip.
Release serial scan logic reset
Test loop-back mode bits
Normal operation
Test Loop-Back<1:0>
'00'
'01'
'10'
'11'
Loop-back TDO_SM to TDI_SM
Loop-back TMS_SM to TDI_SM
All Dot1 (1149.1) pins placed in SEU tolerant safe mode with: TMS_SM = 1, TCK_SM = 0,
TDO_SM = Z, TRST0_SM = 0
Table 22. Clock Divider Register (CLKDIV) ($05)
Bit(s)
15:8
7:1
Type
RO
Field
Address Offset
Reset Value
Reset Source
Reserved
Divisor
0
0
0
00h
00h
0b
RW
RO
SYS_RST
(1)
0
Reserved (hard coded)
(1) LSB of the Clock Divider register is hard coded to zero.
Divisor<7:1>
Clock divisor for the division of the SCK clock to the serial scan clock.
'0000000'
'0000001'
'0000010'
'0000100'
'0001000'
'0010000'
'0100000'
'1000000'
No serial scan clock generated.
Divide SCK by 2
Divide SCK by 4
Divide SCK by 8
Divide SCK by 16
Divide SCK by 32
Divide SCK by 64
Divide SCK by 128
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
Table 23. TDI_SM LFSR Exponent Register (EXPR) ($07)
Bit(s)
15:3
2:0
Type
RO
Field
Address Offset
Reset Value
0000h
Reset Source
Reserved
LFSR
0
0
RW
000b
SYS_RST
LFSR Exponent<2:0>
LFSR exponent. Binary encoding for the selection between three polynomials.
No polynomial selected
Polynomial 1: X32 + X7 + X5 + X3 + X2 + X + 1
Polynomial 2: X32 + X28 + X27 + X + 1
'000'
'001'
'010'
'011'
Polynomial 3: X32 + X7 + X6 + X2 + 1
(1)(2)
Table 24. TDI_SM LFSR LSB Seed Register (LSSEDR) ($08)
Bit(s)
Type
Field
Address Offset
Reset Value
Reset Source
15:0
RW
LSW LFSR Seed
0
0000h
SYS_RST
(1) LSW LFSR Seed<15:0> is the LS word of the LFSR seed.
(2) This register along with register MSSEDR form a register pair and should be read/written with two consecutive read/write accesses.
(1)(2)
Table 25. TDI_SM LFSR MSB Seed Register (MSSEDR) ($09)
Bit(s)
Type
Field
Address Offset
Reset Value
Reset Source
15:0
RW
MSW LFSR Seed
0
0000h
SYS_RST
(1) MSW LFSR Seed <15:0> is the MS word of the LFSR seed.
(2) This register along with register LSSEDR form a register pair and should be read/ written with two consecutive read/write accesses.
(1)(2)
Table 26. TDI_SM LFSR LSB Result Register (LSRESR) ($0A)
Bit(s)
Type
Field
LSW LFSR Result
Address Offset
Reset Value
Reset Source
15:0
RW
0
0000h
SYS_RST
(1) LSW LFSR Result<15:0> is the LS word of the LFSR result.
(2) This register along with register MSRESR form a register pair and should be read/written with two consecutive read/write accesses.
(1)(2)
Table 27. TDI_SM LFSR MSB Result Register (MSRESR) ($0B)
Bit(s)
Type
Field
MSW LFSR Result
Address Offset
Reset Value
Reset Source
15:0
RW
0
0000h
SYS_RST
(1) MSW LFSR Result<15:0> is the MS word of the LFSR result.
(2) This register along with register LSRESR form a register pair and should be read/ written with two consecutive read/write accesses.
(1)(2)(3)
Table 28. Index Register (INDEXR) ($0C)
Bit(s)
Type
Field
Address Offset
Reset Value
Reset Source
15:0
RW
Index
0
0000h
SYS_RST
(1) Index<15:0> sets the individual address memory pointer.
(2) Address memory pointer must be on a long word boundary.
(3) Writing to this register sets the TDO_SM, TDI_SM, Expected and Mask pointers. These pointers will automatically increment with each
long word read from the TDI_SM space and each long word write to the other TDO_SM, Expected and Mask spaces.
(1)(2)
Table 29. Vector Index Register (VINDEXR) ($11)
Bit(s)
Type
Field
Address Offset
Reset Value
Reset Source
15:0
RW
Vector Index
0
0000h
SYS_RST
(1) Vector Index<15:0> sets the Vector address memory pointer.
(2) Address memory pointer must be on a long word boundary.
30
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
(1)(2)
Table 30. Header/Trailer Index Register (HTINDEXR) ($13)
Bit(s)
Type
Field
Header/Trailer Index
Address Offset
Reset Value
Reset Source
15:0
RW
0
0000h
SYS_RST
(1) Header/Trailer Index<15:0> sets the Header/Trailer address memory pointer.
(2) Address memory pointer must be on a long word boundary.
(1)(2)
Table 31. Macro Index Register (MINDEXR) ($15)
Bit(s)
Type
Field
Address Offset
Reset Value
Reset Source
15:0
RW
Macro Index
0
0000h
SYS_RST
(1) Macro Index<15:0> sets the Macro address memory pointer.
(2) Address memory pointer must be on a long word boundary.
(1)(2)
Table 32. Sequencer Index Register (SINDEXR) ($17)
Bit(s)
Type
Field
Address Offset
Reset Value
Reset Source
15:0
RW
Sequencer Index
0
0000h
SYS_RST
(1) Sequencer Index<15:0> sets the Sequencer address memory pointer.
(2) Address memory pointer must be on a long word boundary.
(1)(2)
Table 33. ScanBridge Support Index Register (BSINDEXR) ($19)
Bit(s)
Type
Field
Address Offset
Reset Value
0000h
Reset Source
15:0
RW
ScanBridge Index
0
SYS_RST
(1) ScanBridge Index<15:0> sets the ScanBridge Support address memory pointer.
(2) Address memory pointer must be on a long word boundary.
TESTABILITY DETAILS - IEEE 1149.1 SUPPORT
Table 34. Supported IEEE 1149.1 Instruction Set
Instruction Mnemonic
EXTEST
Binary Instruction Code
Description
Allows off-chip circuitry and interconnect to be tested.
000
001
SAMPLE/PRELOAD
Allows snapshot of normal operation. Also allows data to be loaded on
parallel output boundary scan registers.
BYPASS
111
Places device in bypass mode so that there is single shift register stage
between TDI and TDO.
IDCODE
HIGHZ
010
011
100
Allows scanning of the device identification register.
Will TRI-STATE all output drivers with the exception of TDO.
CLAMP
Allows the state of the signals driven from component pins to be
determined from the boundary-scan register while the BYPASS register
is selected as the serial path between TDI and TDO.
RUNBIST
110
101
Enables on chip BIST logic to perform memory BIST.
SCANTEST
Allows the assertion of internal test_mode signal to prevent the
asynchronous resets from inadvertently resetting the flip-flops during
internal scan. Used in factory test.
Table 35. IDCODE Register Description
Version
Part Number
Manufacturer Identity
Start Bit
"0000"
"1111 1100 0001 0111"
"000 0000 1111"
"1"
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: SCANSTA101
SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013
www.ti.com
Table 36. Boundary Scan Register Definition
BSR
Bit#
Signal Name
BSR
Bit#
Signal Name
BSR
Bit#
Signal Name
BSR
Bit#
Signal Name
0
1
2
3
4
5
6
7
8
9
SCK
RST
10
11
12
13
14
15
16
17
18
19
DTACK
INT
20
21
22
23
24
25
26
27
28
29
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
TDO_SM
TMS_SM
30
31
32
33
34
TCK_SM
TRST0_SM
TDI_SM
OE
R/W
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
STB
CE
TRIST
ADDRESS[4]
ADDRESS[3]
ADDRESS[2]
ADDRESS[1]
ADDRESS[0]
BIST SUPPORT
The memory BIST can be initiated through JTAG interface using the RUNBIST instruction or by setting the
Onboard Memory BIST bit in the Start register. When the memory BIST is initiated through the JTAG interface
the result of pass/fail will be set in the Memory BIST Result bit in the Status register and also in the BIST status
register that can be accessed through the JTAG interface. The BIST status register is a one bit register and is
connected in the serial path of TDO and TDI when the RUNBIST instruction is scanned into the instruction
register. Once the BIST is done, the contents of the BIST status register can be scanned out to determine
whether the memory BIST passed or failed. If the memory BIST is initiated through the Onboard Memory BIST
bit in the Start register the result of pass/fail will be set only in the BIST Result bit in the status register. The
memory BIST will initialize the memory to zero.
32
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101
SCANSTA101
www.ti.com
SNLS057J –MAY 2002–REVISED APRIL 2013
REVISION HISTORY
April, 2013 – Changed layout of National Data Sheet to TI format.
January, 2010 – Applications information updates and clarification. No specification changes.
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Links: SCANSTA101
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SCANSTA101SM/NOPB
SCANSTA101SMX/NOPB
ACTIVE
NFBGA
NFBGA
NZA
49
49
416
RoHS & Green
SNAGCU
Level-4-260C-72 HR
Level-4-260C-72 HR
-40 to 85
-40 to 85
SCANSTA101
SM
ACTIVE
NZA
2000 RoHS & Green
SNAGCU
SCANSTA101
SM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SCANSTA101SMX/NOPB NFBGA
NZA
49
2000
330.0
16.4
7.3
7.3
2.1
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA NZA 49
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
SCANSTA101SMX/NOPB
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
SCANSTA101SM/NOPB
NZA
NFBGA
49
416
13 X 32
150
322.6 135.9 7620
9.4
11.8 11.55
Pack Materials-Page 3
MECHANICAL DATA
NZA0049A
SLC49A (Rev B)
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
相关型号：
SCANSTA111MT/NOPB
IC SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48, TSSOP-48, Microprocessor IC:Other
NSC
©2020 ICPDF网 联系我们和版权申明