SCANSTA112VS [TI]

7 端口多点 IEEE 1149.1 (JTAG) 多路复用器 | NEZ | 100 | -40 to 85;


型号：	SCANSTA112VS
厂家：	TEXAS INSTRUMENTS
描述：	7 端口多点 IEEE 1149.1 (JTAG) 多路复用器 \| NEZ \| 100 \| -40 to 85 外围集成电路复用器
文件：	总23页 (文件大小：1236K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SCANSTA112

www.ti.com

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer

Check for Samples: SCANSTA112

FEATURES

DESCRIPTION

The SCANSTA112 extends the IEEE Std. 1149.1 test

bus into a multidrop test bus environment. The

advantage of a multidrop approach over a single

serial scan chain is improved test throughput and the

ability to remove a board from the system and retain

test access to the remaining modules. Each

SCANSTA112 supports up to 7 local IEEE1149.1

scan chains which can be accessed individually or

combined serially.

•

True IEEE 1149.1 Hierarchical and Multidrop

Addressable Capability

•

The 8 Address Inputs Support up to 249

Unique Slot Addresses, an Interrogation

Address, Broadcast Address, and 4 Multi-Cast

Group Addresses (Address 000000 is

Reserved)

•

7 IEEE 1149.1-Compatible Configurable Local

Scan Ports

Addressing is accomplished by loading the instruction

Backplane and inter-board testing can easily be

accomplished by parking the local TAP Controllers in

one of the stable TAP Controller states via a Park

instruction. The 32-bit TCK counter enables built in

self test operations to be performed on one port while

other scan chains are simultaneously tested.

Bi-directional Backplane and LSP₀Ports are

Interchangeable Slave Ports

Capable of Ignoring TRST of the Backplane

Port when it Becomes the Slave.

Stitcher Mode Bypasses Level 1 and 2

Protocols

Mode Register₀Allows Local TAPs to be

Bypassed, Selected for Insertion into the Scan

Chain Individually, or Serially in Groups of

Two or Three

The STA112 has a unique feature in that the

backplane port and the LSP0 port are bidirectional.

They can be configured to alternatively act as the

master or slave port so an alternate test master can

take control of the entire scan chain network from the

LSP0 port while the backplane port becomes a slave.

•

Transparent Mode can be Enabled with a

Single Instruction to Conveniently Buffer the

Backplane IEEE 1149.1 Pins to Those on a

Single Local Scan Port

General Purpose Local Port Pass Through Bits

are Useful for Delivering Write Pulses for Flash

Programming or Monitoring Device Status.

•

Known Power-Up State

TRST on all Local Scan Ports

32-bit TCK Counter

16-bit LFSR Signature Compactor

Local TAPs can Become TRI-STATE via the OE

Input to Allow an Alternate Test Master to Take

Control of the Local TAPs (LSP_0-3have a TRI-

STATE Notification Output)

•

3.0-3.6V V_CCSupply Operation

Supports Live Insertion/Withdrawal

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SCANSTA112

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

www.ti.com

LSP0

LSP1

LSP2

Buffer with

JTAG

FPGA

vendor1

with JTAG

FPGA

vendor2

with JTAG

ASIC

with

JTAG

Buffer with

JTAG

LSP3

Buffer with

JTAG

Backplane

IEEE 1149.1

Test Bus

LSP4

Processor

with JTAG

Flash

Memory

SCANSTA112

R/W

Figure 1. Typical use of SCANSTA112 for board-level management of multiple scan chains.

Backplane IEEE

1149.1

Test Bus

Figure 2. Example of SCANSTA112 in a multidrop addressable backplane.

Introduction

The SCANSTA112 is the third device in a series that enable multi-drop address and multiplexing of IEEE-1149.1

scan chains. The SCANSTA112 is a superset of its predecessors - the SCANPSC110 and the SCANSTA111.

The STA112 has all features and functionality of these two previous devices.

The STA112 is essentially a support device for the IEEE 1149.1 standard. It is primarily used to partition scan

chains into managable sizes, or to isolate specific devices onto a seperate chain (Figure 1). The benefits of

multiple scan chains are improved fault isolation, faster test times, faster programiing times, and smaller vector

sets.

In addition to scan chain partitioning, the device is also addressable for use in a multidrop backplane

environment (Figure 2). In this configuration, multiple IEEE-1149.1 accessible cards with an STA112 on board

can utilize the same backplane test bus for system-level IEEE-1149.1 access. This approach facilitates a system-

wide commitment to structural test and programming throughout the entire system life sycle.

Architecture

Figure 3 shows the basic architecture of the 'STA112. The device's major functional blocks are illustrated here.

The TAP Controller, a 16-state state machine, is the central control for the device. The instruction register and

various test data registers can be scanned to exercise the various functions of the 'STA112 (these registers

behave as defined in IEEE Std. 1149.1).

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

www.ti.com

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

The 'STA112 selection controller provides the functionality that allows the 1149.1 protocol to be used in a multi-

drop environment. It primarily compares the address input to the slot identification and enables the 'STA112 for

subsequent scan operations.

The Local Scan Port Network (LSPN) contains multiplexing logic used to select different port configurations. The

LSPN control block contains the Local Scan Port Controllers (LSPC) for each Local Scan Port (LSP₀, LSP₁...

LSP_n). This control block receives input from the 'STA112 instruction register, mode registers, and the TAP

controller. Each local port contains all four boundary scan signals needed to interface with the local TAPs plus

the optional Test Reset signal (TRST).

The TDI/TDO Crossover Master/Slave logic is used to define the bidirectional B0 and B1 ports in a Master/Slave

configuration.

Block Diagram

TDI_B1, A0_B1A1_B1

TDI/TDO

A0_B0, A1_B0

Y0_B0, Y1_B0

TDO_B0

Crossover

Master/

Slave

TMS_B1TCK_B1TRST_B1

TDO_B1TRIST_B1Y0_B1Y1_B1

Logic

TCK_B0

TMS_B0

TAP

Controller

TDO₀₁TCK₀₁TMS₀₁

TDI/TDO

TRST₀₁Y0₀₁Y1₀₁TRIST₀₁

TRST_B0

Crossover

TDI₀₁A0₀₁A1₀₁

Local

Scan

Port

Selection

Control

Master/

Slave

Logic

S_0-7

ADDMASK

Network

TDO_02-03TCK_{02_03}TMS_02-03

TRST_02-03TRIST_02-03

Instruction

TDI_B0

TDI_02-03

TRIST_B0

Boundary

SGPIO

MstrPortSel

TDO_04-06TCK_04-06

TMS_04-06TRST_04-06

32-bit Counter

MultiCast

LFSR

TDI_04-06

RESET

ByPass

Control

LSP

Controller

Mode_0-3

PortEnable

Mode_0-3

LSPSel_0-6

MPSel_B1/B0

SB/S

TRANS

TLR_TRST

TLR_TRST₆

Figure 3. SCANSTA112 Block Diagram

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

www.ti.com

Connection Diagrams

S₀

A10

TCK₀₆

TDO₀₆

V_CC

TMS₀₅

GND

TCK₀₄

TMS₀₄

V_CC

TDO₀₃

S₁

B10

GND

TDI₀₆

TCK₀₅

TDO₀₅

TRST₀₄

TCK₀₃

TMS₀₃

TRIST₀₂

S₇

S₃

C10

V_CC

TMS₀₆

TRST₀₅

TDO₀₄

TDI₀₄

GND

V_CC

TCK₀₂

S₅

S₄

D10

ADDMASK TRANS

TRST₀₆

TRST₀₃

TRIST₀₃

TRST₀₂

TMS₀₂

GND

S₆

S₂

E10

A1₀₁

V_CC

LSPsel₀

LSPsel₁

TDI₀₅

TDI₀₃

TDO₀₂

TDI₀₂

F10

V_CC

LSPsel₂

LSPsel₃

SB/S

A0_B1

A0₀₁

RESET

TCK₀₁

Y0₀₁

G10

GND

LSPsel₄

LSPsel₆

TRST_B0

A0_B0

A1_B1

TDO₀₁

TMS₀₁

Y1₀₁

TRIST₀₁

H10

LSPsel₅

V_CC

GND

TMS_B0

A1_B0

TRST_B1TRIST_B1

V_CC

TDI₀₁

TRST₀₁

J10

MPsel_B1/B0TDO_B0

TCK_B0

Y1_B0

TDO_B1

TCK_B1

TMS_B1

GND

TLRTRST₆

GND

K10

TDI_B0

V_CC

TRIST_B0

Y0_B0

GND

TDI_B1

V_CC

Y1_B1

Y0_B1

TLRTRST

Figure 4. (NFBGA Top view)

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

www.ti.com

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

Figure 5. TQFP pinout

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

www.ti.com

PIN DESCRIPTIONS

No.

Pin Name

Pins

I/O

Description

VCC

GND

N/A Power

N/A Ground

RESET

RESET Input: will force a reset of the device regardless of the current state.

ADDRESS MASK input: Allows masking of lower slot input pins.

ADDMASK

MPsel_B1/B0

MASTER PORT SELECTION: Controls selection of LSP_B0or LSP_B1as the backplane port. The

unselected port becomes LSP₀₀. A value of "0" will select LSP_B0as the master port.

SB/S

Selects ScanBridge or Stitcher Mode.

LSPsel _(0-6)

TRANS

In Stitcher Mode these inputs define which LSP's are to be included in the scan chain

Transparent Mode enable input: The value of this pin is loaded into the TRANSENABLE bit of the

control register at power-up. This value is used to control the presence of registers and pad-bits in

the scan chain while in the stitcher mode.

TLR_TRST

Sets the driven value of TRST_0-5when LSP TAPs are in TLR and the device is not being reset.

During RESET = "0" or TRST_B= "0" (IgnoreReset = "0") TRST_n= "0". This pin is to be tied low to

match the function of the SCANSTA111

TLR_TRST₆

TDI_B0, TDI_B1

This pin affects TRST of LSP₆only. This pin is to be tied low to match the function of the

SCANSTA111

BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the 'STA112 through this

input pin. MPsel_B1/B0determines which port is the master backplane port and which is LSP₀₀. This

input has a 25KΩ internal pull-up resistor and no ESD clamp diode (ESD is controlled with an

alternate method). When the device is power-off (V_DDfloating), this input appears to be a capacitive

load to ground ⁽¹⁾. When V_DD= 0V (i.e.; not floating but tied to V_SS) this input appears to be a

capacitive load with the pull-up to ground.

TMS_B0, TMS_B1

I/O

BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the

'STA112. Also controls sequencing of the TAPs which are on the local scan chains. MPsel_B1/B0

determines which port is the master backplane port and which is LSP₀₀. This bidirectional TRI-

STATE pin has 24mA of drive current, with a 25KΩ internal pull-up resistor and no ESD clamp

diode (ESD is controlled with an alternate method). When the device is power-off (V_DDfloating), this

input appears to be a capacitive load to ground ⁽¹⁾. When V_DD= 0V (i.e.; not floating but tied to V_SS

this input appears to be a capacitive load with the pull-up to ground.

)

TDO_B0, TDO_B1

TCK_B0, TCK_B1

I/O

BACKPLANE TEST DATA OUTPUT: This output drives test data from the 'STA112 and the local

TAPs, back toward the scan master controller. This bidirectional TRI-STATE pin has 12mA of drive

current. MPsel_B1/B0determines which port is the master backplane port and which is LSP₀₀. Output

is sampled during interrogation addressing. When the device is power-off (V_DD= 0V or floating), this

(1)

output appears to be a capacitive load

TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls all

scan operations of the 'STA112 and of the local scan ports. MPsel_B1/B0determines which port is the

master backplane port and which is LSP₀₀. These bidirectional TRI-STATE pins have 24mA of drive

current with hysterisis. This input has no pull-up resistor and no ESD clamp diode (ESD is controlled

with an alternate method). When the device is power-off (V_DDfloating), this input appears to be a

capacitive load to ground ⁽¹⁾. When V_DD= 0V (i.e.; not floating but tied to V_SS) this input appears to

be a capacitive load to ground.

TRST_B0, TRST_B1

I/O

TEST RESET: An asynchronous reset signal (active low) which initializes the 'STA112 logic.

MPsel_B1/B0determines which port is the master backplane port and which is LSP₀₀. This

bidirectional TRI-STATE pin has 24mA of drive current, with a 25KΩ internal pull-up resistor and no

ESD clamp diode (ESD is controlled with an alternate method). When the device is power-off (V_DD

floating), this pin appears to be a capacitive load to ground ⁽¹⁾. When V_DD= 0V (i.e.; not floating but

tied to V_SS) this input appears to be a capacitive load with the pull-up to ground.

TRIST_B0, TRIST_B1

TRIST_(01-03)

TRI-STATE NOTIFICATION OUTPUT: This signal is asserted high when the associated TDO is

TRI-STATEd. Associated means TRIST_B0is for TDO_B0, TRIST₀₁is for TDO₀₁, etc. This output has

12mA of drive current.

A0_B0, A1_B0, A0_B1

A1_B1

BACKPLANE PASS-THROUGH INPUT: A general purpose input which is driven to the Y_nof a

single selected LSP. (Not available when multiple LSPs are selected). This input has a 25KΩ

internal pull-up resistor. MPsel_B1/B0determines which port is the master backplane port and which is

LSP₀₀

Y0_B0, Y1_B0, Y0_B1

Y1_B1

BACKPLANE PASS-THROUGH OUTPUT: A general purpose output which is driven from the A_nof

a single selected LSP. (Not available when multiple LSPs are selected). This TRI-STATE output has

12mA of drive current. MPsel_B1/B0determines which port is the master backplane port and which is

LSP₀₀

(1) Refer to the IBIS model on our website for I/O characteristics.

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

www.ti.com

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

PIN DESCRIPTIONS (continued)

No.

Pin Name

Pins

I/O

Description

S_(0-7)

SLOT IDENTIFICATION: The configuration of these pins is used to identify (assign a unique

address to) each 'STA112 on the system backplane

OUTPUT ENABLE for the Local Scan Ports, active low. When high, this active-low control signal

TRI-STATEs all local scan ports on the 'STA112, to enable an alternate resource to access one or

more of the local scan chains.

TDO_(01-06)

TDI_(01-06)

TMS_(01-06)

TEST DATA OUTPUTS: Individual output for each of the local scan ports . These TRI-STATE

outputs have 12mA of drive current.

TEST DATA INPUTS: Individual scan data input for each of the local scan ports. This input has a

25KΩ internal pull-up resistor.

TEST MODE SELECT OUTPUTS: Individual output for each of the local scan ports. TMS_ndoes not

provide a pull-up resistor (which is assumed to be present on a connected TMS input, per the IEEE

1149.1 requirement) . These TRI-STATE outputs have 24mA of drive current.

TCK_(01-06)

TRST_(01-06)

A0₀₁, A1₀₁

LOCAL TEST CLOCK OUTPUTS: Individual output for each of the local scan ports. These are

buffered versions of TCK_B. These TRI-STATE outputs have 24mA of drive current.

LOCAL TEST RESETS: A gated version of TRST_B. These TRI-STATE outputs have 24mA of drive

current.

LOCAL PASS-THROUGH INPUTS: General purpose inputs which can be driven to the backplane

pin Y_B. (Only on LSP₀and LSP₁. Only available when a single LSP is selected) . These inputs have

a 25KΩ internal pull-up resistor.

Y0₀₁, Y1₀₁

LOCAL PASS-THROUGH OUTPUT: General purpose outputs which can be driven from the

backplane pin A_B. (Only on LSP₀and LSP₁. Only available when a single LSP is selected) . These

TRI-STATE outputs have 12mA of drive current.

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

www.ti.com

APPLICATION OVERVIEW

ADDRESSING SCHEME

The SCANSTA112 architecture extends the functionality of the IEEE 1149.1 Standard by supplementing that

protocol with an addressing scheme which allows a test controller to communicate with specific 'STA112s within

a network of 'STA112s. That network can include both multi-drop and hierarchical connectivity. In effect, the

'STA112 architecture allows a test controller to dynamically select specific portions of such a network for

participation in scan operations. This allows a complex system to be partitioned into smaller blocks for testing

purposes. The 'STA112 provides two levels of test-network partitioning capability. First, a test controller can

select individual 'STA112s, specific sets of 'STA112s (multi-cast groups), or all 'STA112s (broadcast). This

'STA112-selection process is supported by a Level-1 communication protocol. Second, within each selected

'STA112, a test controller can select one or more of the chip's seven local scan-ports. That is, individual local

ports can be selected for inclusion in the (single) scan-chain which a 'STA112 presents to the test controller. This

mechanism allows a controller to select specific scan-chains within the overall scan network. The port-selection

process is supported by a Level-2 protocol.

HIERARCHICAL SUPPORT

Multiple SCANSTA112's can be used to assemble a hierarchical boundary-scan tree. In such a configuration, the

system tester can configure the local ports of a set of 'STA112s so as to connect a specific set of local scan-

chains to the active scan chain. Using this capability, the tester can selectively communicate with specific

portions of a target system. The tester's scan port is connected to the backplane scan port of a root layer of

'STA112s, each of which can be selected using multi-drop addressing. A second tier of 'STA112s can be

connected to this root layer, by connecting a local port (LSP) of a root-layer 'STA112 to the backplane port of a

second-tier 'STA112. This process can be continued to construct a multi-level scan hierarchy. 'STA112 local

ports which are not cascaded into higher-level 'STA112s can be thought of as the terminal leaves of a scan tree.

The test master can select one or more target leaves by selecting and configuring the local ports of an

appropriate set of 'STA112s in the test tree.

STANDARD SCANBRIDGE MODE

ScanBridge mode refers to functionality and protocol that has been used since the introduction of the PSC110 in

1993. This functionality consists of a multidrop addressable IEEE1149.1 switch. This enables one (or more)

device to be selected from many that are connected to a parallel IEEE1149.1 bus or backplane. The second

function that ScanBridge mode accomplishes is to act as a mux for multiple IEEE1149.1 local scan chains. The

Local Scan Ports (LSP) of the device creates a connection between one or more of the local scan chains to the

backplane bus.

To accomplish this functionality the ScanBridge has two levels of protocol and an operational mode. Level 1

protocol refers to the required actions to address/select the desired ScanBridge. Level 2 protocol is required to

configuring the mux'ing function and enable the connection (UNPARK) between the local scan chain and the

backplane bus via an LSP. Upon completion of level 1 and 2 protocols the ScanBridge is prepared for its

operational mode. This is where scan vectors are moved from the backplane bus to the desired local scan

chain(s).

STITCHER MODE

Stitcher Mode is a method of skipping level 1 and 2 protocol of the ScanBridge mode of operation. This is

accomplished via external pins. When in stitcher mode the SCANSTA112 will go directly to the operational mode.

TRANSPARENT MODE

Transparent mode refers to a condition of operation in which there are no pad-bits or SCANSTA112 registers in

the scan chain. The Transparent mode of operation is available in both ScanBridge and Stitcher modes. Only the

activation method differs. Once transparent mode has been activated there is no difference in operation.

Transparent mode allows for the use of vectors that have been generated for a chain where these bits were not

included.

Check with your ATPG tool vendor to ensure support of these features.

For details regarding the internal operation of the SCANSTA112 device, refer to applications note AN-

1259(SNLA055) SCANSTA112 Designers Reference.

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

www.ti.com

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Supply Voltage (V_CC

)

−0.3V to +4.0V

−20 mA

DC Input Diode Current (I_IK) V_I= −0.5V

DC Input Voltage (V_I)

−0.5V to +3.9V

−20 mA

DC Output Diode Current (I_OK) V_O= −0.5V

DC Output Voltage (V_O)

−0.3V to +3.9V

±50 mA

DC Output Source/Sink Current (I_O)

DC V_CCor Ground Current per Output Pin

DC Latchup Source or Sink Current

Junction Temperature (Plastic)

Storage Temperature

±50 mA

±300 mA

+150°C

−65°C to +150°C

220°C

Lead Temperature (Solder, 4sec)

100L NFBGA

100L TQFP

100L NFBGA

100L TQFP

100L NFBGA

100L TQFP

100L NFBGA

100L TQFP

220°C

Max Package Power Capacity @ 25°C

3.57W

2.11W

Thermal Resistance (θ_JA

)

35°C/W

59.1°C/W

28.57mW/°C

16.92mW/°C

2500V

Package Derating above +25°C

ESD Last Passing Voltage (HBM Min)

(1) Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,

without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. TI

does not recommend operation of SCAN STA products outside of recommended operation conditions.

RECOMMENDED OPERATING CONDITIONS

Supply Voltage (V_CC) 'STA112

3.0V to 3.6V

0V to V_CC

Input Voltage (V_I)

Output Voltage (V_O)

0V to V_CC

Operating Temperature (T_A) Industrial

−40°C to +85°C

DC ELECTRICAL CHARACTERISTICS

Over recommended operating supply voltage and temperature ranges unless otherwise specified

Symbol

V_IH

Parameter

Minimum High Input Voltage

Conditions

V_OUT= 0.1V or

_CC−0.1V

V_OUT= 0.1V or

_CC−0.1V

Min

Max

Units

2.1

V_IL

Maximum Low Input Voltage

0.8

V_OH

Minimum High Output Voltage

All Outputs and I/O Pins

I_OUT= −100 μA

V_IN= V_IHor V_IL

I_OUT= −12 mA

All Outputs Loaded

V_CC- 0.2v

2.4

V_OH

Minimum High Output Voltage

TDO_B0, TDO_B1, TRIST_B0, TRIST_B1, Y0_B0, Y1_B0, Y0_B1

Y1_B1, TDO_(01-06), Y0₀₁, Y1₀₁, TRIST_(01-03)

V_OH

Minimum High Output Voltage

I_OUT= −24mA

2.2

TMS_B0, TMS_B1, TCK_B0, TCK_B1, TRST_B0, TRST_B1

TMS_(01-06), TCK_(01-06), TRST_(01-06)

V_OL

Maximum Low Output Voltage

All Outputs and I/O Pins

I_OUT= +100 μA

0.2

V_IN= V_IHor V_IL

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

www.ti.com

DC ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating supply voltage and temperature ranges unless otherwise specified

Symbol

V_OL

Parameter

Maximum Low Output Voltage

Conditions

I_OUT= +12 mA

Min

Max

Units

0.4

TDO_B0, TDO_B1, TRIST_B0, TRIST_B1, Y0_B0, Y1_B0, Y0_B1

Y1_B1, TDO_(01-06), Y0₀₁, Y1₀₁, TRIST_(01-03)

V_OL

Maximum Low Output Voltage

I_OUT= +24mA

0.55

TMS_B0, TMS_B1, TCK_B0, TCK_B1, TRST_B0, TRST_B1

TMS_(01-06), TCK_(01-06), TRST_(01-06)

VIKL

I_IN

Maximum Input Clamp Diode Voltage

Maximum Input Leakage Current

(non-resistor input pins)

IIK = -18mA

-1.2

V_IN= V_CCor GND

±5.0

μA

I_ILR

Input Current Low

V_IN= GND

-45

-200

µA

(Input and I/O pins with pull-up resistors: TDI_B0, TDI_B1

TMS_B0, TMS_B1, TRST_B0, TRST_B1, A0_B0, A1_B0, A0_B1

A1_B1, TDI_(01-06), A0₀₁, A1₀₁

)

I_IH

Input High Current

V_IN= V_CC

5.0

µA

(Input and I/O pins with pull-up resistors: TDI_B0, TDI_B1

TMS_B0, TMS_B1, TRST_B0, TRST_B1, A0_B0, A1_B0, A0_B1

A1_B1, TDI_(01-06), A0₀₁, A1₀₁

)

I_OFF

Power-off Leakage Current

V_CC= 0V, V_IN= 3.6V⁽¹⁾

±5.0

μA

Outputs and I/O pins without pull-up resistors

Outputs and I/O pins with pull-up resistors

Maximum TRI-STATE Leakage Current

Outputs and I/O pins without pull-up resistors

Maximum Quiescent Supply Current

Maximum Dynamic Supply Current

±200

±5.0

μA

I_OZ

I_CC

V_IN= V_CCor GND

3.8

I_CCD

V_IN= V_CCor GND, Input

Freq = 25MHz

(1) Specified by equivalent test method.

AC ELECTRICAL CHARACTERISTICS: SCAN BRIDGE MODE

Over recommended operating supply voltage and temperature ranges unless otherwise specified⁽¹⁾

Symbol

t_PHL

Parameter

Conditions

Typ

Max

Units

Propagation Delay

8.5

13.5

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

TCK_B0to TDO_B0or TDO_B1

Propagation Delay

TCK_B1to TDO_B0or TDO_B1

Propagation Delay

TCK_B0to TDO_(01-06)

Propagation Delay

TCK_B1to TDO_(01-06)

Propagation Delay

TMS_B0to TMS_B1

8.5

7.5

8.0

14.0

12.5

13.0

12.0

Propagation Delay

TMS_B1to TMS_B0

Propagation Delay

TMS_B0to TMS_(01-06)

Propagation Delay

TMS_B1to TMS_(01-06)

Propagation Delay

TCK_B0to TCK_B1

(1) R_L= 500Ω to GND, C_L= 50pF to GND, t_R/t_F= 2.5ns, Frequency = 25MHz, V_M= 1.5V

10 Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

www.ti.com

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

AC ELECTRICAL CHARACTERISTICS: SCAN BRIDGE MODE (continued)

Over recommended operating supply voltage and temperature ranges unless otherwise specified⁽¹⁾

Symbol

Parameter

Conditions

Typ

Max

Units

t_PHL

Propagation Delay

TCK_B1to TCK_B0

8.0

12.0

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

Propagation Delay

TCK_B0to TCK_(01-06)

Propagation Delay

TCK_B1to TCK_(01-06)

Propagation Delay

TCK_B0to TRST_B1

Propagation Delay

TCK_B1to TRST_B0

Propagation Delay

TCK_B0to TRST_(01-06)

Propagation Delay

TCK_B1to TRST_(01-06)

Propagation Delay

TCK_Bnto TRIST_Bn

Propagation Delay

TCK_Bnto TRIST_(01-03)

Propagation Delay

7.5

12.0

18.0

18.5

12.5

12.0

14.5

9.0

11.5

12.0

8.5

t_PHL

8.0

t_PZL

t_PZH

t_PHL

t_PLH

9.0

TCK_Bnto TDO_Bnor TDO_(01-06)

Propagation Delay

An to Yn

6.0

AC TIMING CHARACTERISTICS: SCAN BRIDGE MODE

Over recommended operating supply voltage and temperature ranges unless otherwise specified⁽¹⁾⁽²⁾

Symbol

Parameter

Conditions

Min

Max

Units

t_S

t_H

t_S

t_H

t_S

t_H

Setup Time

2.5

TMS_Bnto TCK_Bn

Hold Time

1.5

3.0

2.0

1.0

3.5

TMS_Bnto TCK_Bn

Setup Time

TDI_Bnto TCK_Bn

Hold Time

TDI_Bnto TCK_Bn

Setup Time

TDI_(01-06)to TCK_Bn

Hold Time

TDI_(01-06)to TCK_Bn

(1) Specified by Design (GBD) by statistical analysis

(2) R_L= 500Ω to GND, C_L= 50pF to GND, t_R/t_F= 2.5ns, Frequency = 25MHz, V_M= 1.5V

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

www.ti.com

AC TIMING CHARACTERISTICS: SCAN BRIDGE MODE (continued)

Over recommended operating supply voltage and temperature ranges unless otherwise specified⁽¹⁾⁽²⁾

Symbol

t_REC

Parameter

Conditions

Min

Max

Units

Recovery Time

TCK_Bnfrom TRST_Bn

Clock Pulse Width

TCK_Bn(H or L)

1.0

t_W

t_R/t_F= 1.0ns

10.0

2.5

t_WL

Reset Pulse Width

TRST_Bn(L)

t_R/t_F= 1.0ns

F_MAX

Maximum Clock Frequency⁽³⁾

t_R/t_F= 1.0ns

MHz

(3) When sending vectors one-way to a target device on an LSP (such as in FPGA/PLD configuration/programming), the clock frequency

may be increased above this specification. In Scan Mode (expecting to capture returning data at the LSP), the F_MAXmust be limited to

the above specification.

AC ELECTRICAL CHARACTERISTICS: STITCHER TRANSPARENT MODE

Over recommended operating supply voltage and temperature ranges unless otherwise specified

(1)

Symbol

Parameter

Conditions

Typ

Max

Units

t_PHL

Propagation Delay

12.5

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

TDI_B0to TDO_B1, TDI_B1to TDO_B0

Propagation Delay

12.5

TDI_B0to TDO₀₁, TDI_B1to TDO₀₁

Propagation Delay

TDI_LSPnto TDO_LSPn+1

Propagation Delay

TMS_B0to TMS_B1, TMS_B1to TMS_B0

Propagation Delay

TMS_B0to TMS_(01-06), TMS_B1to TMS_(01-06)

Propagation Delay

TRST_B0to TRST_B1, TRST_B1to TRST_B0

Propagation Delay

TRST_B0to TRST_(01-06), TRST_B1to TRST_(01-06)

(1) R_L= 500Ω to GND, C_L= 50pF to GND, t_R/t_F= 2.5ns, Frequency = 25MHz, V_M= 1.5V

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

www.ti.com

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

TEST CIRCUIT DIAGRAMS

Figure 6. Waveforms for an Unparked STA112 in the Shift-DR (IR) TAP Controller State

Figure 7. Reset Waveforms

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

www.ti.com

Figure 8. Output Enable Waveforms

Capacitance & I/O Characteristics

Refer to TI's website for IBIS models at www.ti.com.com/lsds/ti/analog/interface.page

Submit Documentation Feedback

Product Folder Links: SCANSTA112

SCANSTA112

www.ti.com

SNLS161I –DECEMBER 2002–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision H (April 2013) to Revision I

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 14

Submit Documentation Feedback

Product Folder Links: SCANSTA112

PACKAGE OPTION ADDENDUM

www.ti.com

17-Mar-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SCANSTA112SM

SCANSTA112SM/NOPB

SCANSTA112SMX

ACTIVE

NFBGA

TQFP

NZD

100

240

Non-RoHS

& Green

Call TI

Level-3-235C-168 HR

Level-4-260C-72 HR

Level-3-235C-168 HR

Level-4-260C-72 HR

Level-3-260C-168 HR

-40 to 85

SCANSTA112

Samples

ACTIVE

NRND

NZD

240

RoHS & Green

SNAGCU

Call TI

SCANSTA112

NZD

1000

Non-RoHS

& Green

SCANSTA112

SCANSTA112SMX/NOPB

SCANSTA112VS

ACTIVE

NZD

1000 RoHS & Green

SNAGCU

Call TI

SCANSTA112

Samples

NEZ

Non-RoHS

& Green

SCANSTA112

SCANSTA112VS/NOPB

SCANSTA112VSX/NOPB

TQFP

NEZ

RoHS & Green

NIPDAU

SCANSTA112

TQFP

NEZ

1000 RoHS & Green

SCANSTA112

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-Mar-2023

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SCANSTA112SMX

NFBGA

NZD

NEZ

100

1000

330.0

24.4

32.4

10.3

18.0

10.3

18.0

2.0

1.6

16.0

24.0

32.0

SCANSTA112SMX/NOPB NFBGA

SCANSTA112VSX/NOPB TQFP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SCANSTA112SMX

SCANSTA112SMX/NOPB

SCANSTA112VSX/NOPB

NFBGA

TQFP

NZD

NEZ

100

1000

367.0

45.0

55.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TRAY

L - Outer tray length without tabs

KO -

Outer

tray

height

W -

Outer

tray

width

Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center

CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

Name

Type

(mm) (µm) (mm) (mm) (mm)

SCANSTA112SM

SCANSTA112SM/NOPB

SCANSTA112VS

NZD

NEZ

NFBGA

TQFP

100

240

10 X 24

6 X 15

6 x 15

150

322.6 135.9 7620 12.4

322.6 135.9 7620 20.3

14.9 12.15

15.4 15.45

SCANSTA112VS

TQFP

SCANSTA112VS/NOPB

TQFP

Pack Materials-Page 3

MECHANICAL DATA

NEZ0100A

PFD0100A

TYPICAL

VJD100A (Rev C)

www.ti.com

MECHANICAL DATA

NZD0100A

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SCANSTA112VS [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E