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SM320C6457-HIREL

ZHCSFA5 –JULY 2016

SM320C6457-HIREL 通信基础设施数字信号处理器

1 器件概述

1.1 特性

1

专用集成电路 (ASIC) 等等）

• 高性能定点数字信号处理器 (DSP) - SM320C6457-

HIREL

– 32MB 总可寻址外部存储空间

– 1.18ns、1ns 和 0.83ns 指令周期时间

– 850MHz 和 1GHz 时钟速率

– 8 个 32 位指令/周期

– 8000MIPS/MMACS 和 9600MIPS/MMACS（16

位）

• 32 位 DDR2 存储器控制器 (DDR2-667 SDRAM)

• 4 个 1× 串行 RapidIO^®链路（或 1 个 4×），兼容

v1.3

– 1.25Gbps、2.5Gbps、3.125Gbps 三种链路速率

– 消息传递，DirectIO 支持，错误管理扩展，拥塞

控制

– 扩展级外壳温度

– 符合 IEEE 1149.6 标准的 I/O

• EDMA3 控制器（64 个独立通道）

• 32 位/16 位主机端口接口 (HPI)

• 2 个 1.8V McBSP

•

-55ºC 至 100ºC (1GHz)

• TMS320C64x+™DSP 内核

– 专用 SPLOOP 指令

– 紧凑型指令（16 位）

• 10/100/1000 Mb/s 以太网 MAC (EMAC)

– 符合 IEEE 802.3 标准

– 指令集增强

– 异常处理

– 支持 SGMII，兼容 v1.8

– 8 个独立的发送 (TX) 通道和 8 个独立的接收

(RX) 通道

• TMS320C64x+ 超级模块 L1/L2 存储器架构：

– 256KB (32Kb) L1P 程序缓存 [直接映射]

– 256KB (32Kb) L1D 数据缓存 [2 路组相连]

• 2 个 64 位通用定时器

– 16MB (2048Kb) L2 统一映射 Ram/缓存 [灵活分

配]

– 可配置为 4 个 32 位定时器

– 可配置为看门狗定时器模式

• UTOPIA

•

最高可配置为 1MB 的 L2 缓存

– 512KB (64Kb) L3 ROM

– 时间戳计数器

• 增强型 VCP2

– 支持 694 个以上 7.95Kbps AMR 的语音通道

– 可编程代码参数

• 2 个增强型 Turbo 解码器协处理器（TCP2_A 和

TCP2_B）

– UTOPIA 第 2 级从 ATM 控制器

– 8 位发送和接收操作，每个方向高达 50MHz

– 用户定义的单元格式，高达 64 字节

• 1 个 1.8V 内部集成电路 (I2C) 总线

• 16 个通用 I/O (GPIO) 引脚

• 系统锁相环 (PLL) 和 PLL 控制器

• DDR PLL，专用于 DDR2 存储器控制器

• 支持高级事件触发 (AET)

– 每个 TCP2 支持多达 8 个 2Mbps 3GPP (6 次迭

代）

– 可编程的 Turbo 代码和解码参数

• 尾数法：小尾数法，大尾数法

• 64 位外部存储器接口 (EMIFA)

• 支持跟踪功能的器件

• 支持 IP 安全保护功能

• IEEE-1149.1 和 IEEE-1149.6 (JTAG™) 边界扫描兼

容

– 可与异步存储器（SRAM、闪存和 EEPROM）以

及同步存储器（SBSRAM、ZBT SRAM）无缝连

接

• 688 引脚球栅阵列 (BGA) 封装（GMH 后

缀），0.8mm 焊球间距

– 支持连接标准同步器件和定制逻辑（现场可编程

门阵列 (FPGA)、复杂可编程逻辑器件 (CPLD)、

• 0.065µm/7 层铜金属工艺 (CMOS)

• 3.3V、1.8V、1.1V (I/O)；1.1V 和 1.2V（内部）

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SPRS948

SM320C6457-HIREL

ZHCSFA5 –JULY 2016

www.ti.com.cn

1.2 应用

•

远端射频单元

•

语音处理

生物识别

软件定义的无线电

1.3 说明

TMS320C64x+™ DSP（包括 SM320C6457-HIREL 器件）是 TMS320C6000™DSP 平台上的高性能定点

DSP 系列产品。SM320C6457-HIREL 器件基于德州仪器 (TI) 开发的第 3 代高性能、高级 VelociTI™超长指

令字 (VLIW) 架构，这使得该系列 DSP 非常适合包括视频和电信基础设施、成像/医疗以及无线基础设施

(WI) 在内的各类应用。C64x+ 器件向上代码兼容属于 C6000™ DSP 平台的早期器件。

基于 65nm 的工艺技术以及凭借高达 96 亿条指令每秒 (MIPS) [或 9600 16 位 MMAC 每周期] 的性能

（1.2GHz 时钟速率时），SM320C6457-HIREL 器件提供了一套应对高性能 DSP 编程挑战的经济高效型解

决方案。SM320C6457-HIREL DSP 可以灵活地利用高速控制器以及阵列处理器的数值计算能力。

C64x+ DSP 内核采用 8 个功能单元、2 个寄存器文件以及 2 个数据路径。与早期 C6000 器件一样，其中 2

个功能单元为乘法器或 .M 单元。C64x 内核每个时钟周期执行 4 次 16 位 × 16 位乘法累加，相比之

下，C64x+ .M 单元的乘法吞吐量可增加一倍。因此，C64x+ 内核每个周期可以执行 8 次 16 位 × 16 位

MAC。采用 1.2GHz 时钟速率时，这意味着每秒可以执行 9600次 16 位 MMAC。此外，C64x+ 内核上的每

个乘法器每个时钟周期可以计算 1 次 32 位 × 32 位 MAC 或 4 次 8 位 × 8 位 MAC。

SM320C6457-HIREL 器件含有串行 RapidIO®。该高带宽外设可为板上包含多个 DSP 的应用（例如，视

频和电信基础设施以及医疗/成像）显著提升系统性能并降低系统成本。

SM320C6457-HIREL DSP 集成有大量的片上存储器，构成一个第 2 级存储器系统。SM320C6457-HIREL

器件上的 1 级 (L1) 程序存储器和数据存储器的大小均为 32KB。该存储器可以配置为映射 RAM、缓存或二

者的某种组合。当配置为缓存时，L1 程序存储器 (L1P) 是一个直接映射缓存，而 L1 数据存储器 (L1D) 是一

个 2 路组相连缓存。2 级 (L2) 存储器由程序空间和数据空间共享，大小为 2048KB。L2 存储器也可以配置

为映射 RAM、缓存或二者的某种组合。L2 可配置为高达 1MB 的缓存。此外，C64x+ 超级模块还具有 32

位外设配置 (CFG) 端口、内部 DMA (IDMA) 控制器、具有复位/启动控制的系统组件、中断/异常控制、掉电

控制以及用于时间戳的自由运行 32 位定时器。

外设集包括：1 个内部集成电路总线模块 (I²C)；2 个多通道缓冲串行端口 (McBSP)；1 个用于异步传输模式

(ATM) 从 [UTOPIA 从器件] 端口的 8 位通用测试和运行 PHY 接口；2 个 64 位通用定时器（也可配置为 4

个 32 位定时器）；1 个用户可配置的 16 位或 32 位主机端口接口 (HPI16/HPI32)；1 个支持可编程中断/事

件生成模式的 16 引脚通用输入/输出端口 (GPIO)；1 个 10/100/1000 以太网介质访问控制器 (EMAC)（可在

SM320C6457-HIREL DSP 内核处理器和网络之间提供一个高效接口）；1 个管理数据输入/输出 (MDIO) 模

块（也属于 EMAC，可以连续轮询全部 32 个 MDIO 地址以枚举系统内的所有 PHY 器件）；1 个可连接同

步和异步外设的无缝外部存储器接口（64 位 EMIFA）；以及 1 个 32 位 DDR2 SDRAM 接口。

2

器件概述

SM320C6457-HIREL

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1.4 说明（续）

SM320C6457-HIREL 器件具有 3 个高性能嵌入式协处理器 [1 个增强型维特比解码器协处理器 (VCP2) 和 2

个增强型 Turbo 解码器协处理器（TCP2_A 和 TCP2_B）]，可以显著加速片上的通道解码操作。VCP2 的

运行速度为 CPU 时钟的三分之一，可以解码超过 694 个 7.95Kbps 自适应多速率 (AMR) [K = 9，R = 1/3]

语音通道。VCP2 支持约束长度 K = 5、6、7、8 和 9，比率 R = 3/4、1/2、1/3、1/4 和 1/5 以及灵活的多

项式，同时能够生成硬决策或软决策。每个运行速度为 CPU 时钟三分之一的 TCP2 可以解码多达 50 个

384Kbps 或 8 个 2Mbps Turbo 编码通道（假设 6 次迭代）。TCP2 实现 max*log-map 算法，旨在支持第

三代合作项目（3GPP 和 3GPP2）所需的全部多项式和比率，且支持完全可编程的帧长和 Turbo 交错。解

码参数，例如迭代次数以及停止标准，也都可编程。VCP2/TCP2 与 CPU 之间通过 EDMA3 控制器进行通

信。

SM320C6457-HIREL 器件配有一套完整的开发工具，其中包括：新款 C 编译器、用于简化编程和调度过程

的汇编优化器以及用于查看源代码执行的 Windows^®调试器接口。

器件信息⁽¹⁾

封装

产品型号

SM320C6457-HIREL

(1) 更多信息请参见节 7，机械封装和可订购产品信息。

封装尺寸

23.00mm x 23.00mm

FCBGA (688)

器件概述

3

SM320C6457-HIREL

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1.5 功能方框图

图 1-1 给出了 SM320C6457-HIREL 器件的功能框图。

C6457

32

DDR2

Mem Ctlr

DDR2 SDRAM

PLL2

64

EMIFA

I/O Devices

L1P SRAM/Cache Direct-Mapped

32K Bytes

TCP2_A

TCP2_B

VCP2

L1P Memory Controller (Memory Protect/Bandwidth Mgmt)

C64x+ DSP Core

McBSP0

McBSP1

Control Registers

SPLOOP Buffer

Instruction Fetch

16-/32-bit

Instruction Dispatch

L2

Instruction

Decode

In-Circuit Emulation

Data Path B

Cache

Memory

2048K

Bytes

Serial Rapid

I/O

M

e

g

a

m

o

d

u

l

Data Path A

HPI (32/16)

UTOPIA

A Register File

A31−A16

B Register File

B31−B16

A15−A0

B15−B0

e

.M1

xx

.M2

xx

.L1

.S1

.D1

.D2

.S2

.L2

EMAC

10/100/1000

SGMII

MDIO

L1D Memory Controller (Memory Protect/Bandwidth Mgmt)

16

GPIO16

I2C

L1D SRAM/Cache

2-Way

Set-Associative

32K Bytes Total

Timer1^(A)

HI

EDMA 3.0

L3 ROM

LO

Device

Configuration

Logic

PLL1 and

PLL1

Timer0^(A)

Controller

Secondary

HI

Switched Central

Resource

LO

Boot Configuration

图 1-1. 功能框图

(A) 每个 TIMER 外设（TIMER1 和 TIMER0）均可配置为 1 个 64 位通用定时器、2 个 32 位通用定时器或者 1 个看门狗定时器。

4

器件概述

SM320C6457-HIREL

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内容

1

器件概述.................................................... 1

4.8 Peripherals .......................................... 46

Detailed Description.................................. 166

5.1 Device Overview................................... 166

5.2 CPU (DSP Core) Description ...................... 167

5.3 C64x+ Megamodule ............................... 170

5.4 Memory Map Summary............................ 185

5.5 Device Configuration............................... 187

5.6 System Interconnect ............................... 193

5.7 Boot Modes ........................................ 198

5.8 Rake Search Accelerator (RSA)................... 200

器件和文档支持......................................... 201

6.1 器件命名规则....................................... 201

6.2 工具与软件 ......................................... 201

6.3 文档支持 ........................................... 202

6.4 社区资源 ........................................... 203

6.5 商标 ................................................ 204

6.6 静电放电警告....................................... 204

6.7 Glossary............................................ 204

机械、封装和可订购信息 .............................. 205

1.1 特性 ................................................... 1

1.2 应用 ................................................... 2

1.3 说明 ................................................... 2

1.4 说明（续）........................................... 3

1.5 功能方框图............................................ 4

修订历史记录............................................... 6

Terminal Configuration and Functions.............. 7

3.1 Pin Diagram .......................................... 7

3.2 Pin Attributes ......................................... 8

3.3 Signal Descriptions.................................. 31

Specifications ........................................... 37

4.1 Absolute Maximum Ratings......................... 37

4.2 ESD Ratings ........................................ 38

4.3 Recommended Operating Conditions............... 38

4.4 Electrical Characteristics............................ 39

4.5 Thermal Resistance Characteristics ................ 39

4.6 Timing and Switching Characteristics............... 40

5

2

3

6

4

4.7

Power Supply to Peripheral I/O Mapping ........... 44

7

内容

5

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2 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

注释

7 月 2016

*

最初发布。

6

修订历史记录

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3 Terminal Configuration and Functions

3.1 Pin Diagram

Figure 3-1 shows the ball locations for the 688-pin GMH package and is used in conjunction with Table 4-

1 through Table 4-27 to locate signal names and ball grid numbers.

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21 23 25 27

2

4

6

8 10 12 14 16 18 20 22 24 26 28

Figure 3-1. GMH 688-Pin Ball Grid Array (BGA) Package

Terminal Configuration and Functions

7

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3.2 Pin Attributes

Table 3-2 identifies the external signal names, the associated pin (ball) numbers along with the

mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal

pullup/pulldown resistors, and a functional pin description. For more detailed information on device

configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see

Section 5.5.

Use the symbol definitions in Table 3-1 when reading Table 3-2.

Table 3-1. I/O Functional Symbol Definitions

FUNCTIONAL

SYMBOL

Table 3-2

COLUMN HEADING

DEFINITION

Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ

resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup

resistors and situations in which external pulldown/pullup resistors are required, see

Section 5.5.6.

IPD or IPU

IPD/IPU

A

GND

I

Analog signal

Type

Ground

Input terminal

O

Output terminal

S

Supply voltage

Z

Three-state terminal or high impedance

Table 3-2. Pin Attributes

BALL

SIGNAL NAME

NO.

TYPE IPD/IPU DESCRIPTION

CLOCK/PLL CONFIGURATIONS

CORECLKN

CORECLKP

ALTCORECLK

AH7

AH6

AF6

I

Clock Input for PLL1 (differential).

Alternate Core Clock (single-ended) input to main PLL [vs. CORECLK(N|P)].

Core Clock Select. Selects between CORECLK(N|P) and ALTCORECLK to the Main

PLL.

CORECLKSEL

AE6

•

When CORECLKSEL = 0, it selects the differential clock [CORECLK(N|P)].

When CORECLKSEL = 1, it selects the single-ended clock [ALTCORECLK].

SYSCLKOUT

DDRREFCLKN

DDRREFCLKP

ALTDDRCLK

AD7

E6

O/Z

IPD

SYSCLKOUT is the clock output at 1/10 (default rate) of the device speed.

DDR Reference Clock Input to DDR PLL (differential).

I

D6

DDR Reference Clock Input to DDR PLL (differential).

C6

Alternate DDR Clock (single-ended) input to DDR PLL [vs. DDRREFCLK(N|P)].

DDR Clock Select. Selects between DDRREFCLK(N|P) and ALTDDRCLK to the DDR

PLL.

DDRCLKSEL

G6

I

•

When DDRCLKSEL = 0, it selects the differential clock [DDRREFCLK(N|P)].

When DDRCLKSEL = 1, it selects the single-ended clock [ALTDDRCLK].

RIOSGMIICLKN

RIOSGMIICLKP

AG6

AG7

RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes (differential).

JTAG EMULATION

TMS

TDO

TDI

Y2

I

IPU

JTAG test-port mode select

AF1

AB1

AH3

AE2

O/Z

JTAG test-port data out

I

IPU

IPD

JTAG test-port data in

TCK

TRST

JTAG test-port clock

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see Section 4.8.19.3.1.

8

Terminal Configuration and Functions

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Table 3-2. Pin Attributes (continued)

BALL

NO.

SIGNAL NAME

EMU0(3)

EMU1(3)

EMU2

TYPE IPD/IPU DESCRIPTION

AD5

AE5

AH5

AE4

AH4

AG4

AF4

AG2

AG3

AD4

AE3

AF2

AE1

AF3

AC1

AD1

AD3

AA1

AC2

Emulation pin 0

Emulation pin 1

Emulation pin 2

Emulation pin 3

Emulation pin 4

Emulation pin 5

Emulation pin 6

Emulation pin 7

Emulation pin 8

Emulation pin 9

Emulation pin 10

Emulation pin 11

Emulation pin 12

Emulation pin 13

Emulation pin 14

Emulation pin 15

Emulation pin 16

Emulation pin 17

Emulation pin 18

EMU3

EMU4

EMU5

EMU6

EMU7

EMU8

EMU9

I/O/Z

IPU

EMU10

EMU11

EMU12

EMU13

EMU14

EMU15

EMU16

EMU17

EMU18

RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS

RESET

NMI

AH23

AE19

I

Device reset

Nonmaskable interrupt, edge-driven (rising edge).

NOTE: Any noise on the NMI pin may trigger an NMI interrupt. Therefore, if the NMI pin

is not used, it is recommended that the NMI pin be grounded instead of relying on the

IPD.

I

IPD

RESETSTAT

POR

AF23

AG22

F23

D23

C23

D24

C25

A25

C24

B25

F5

O

I

Reset Status pin. The RESETSTAT pin indicates when the device is in reset

Power on reset.

GP15

GP14

GP13

GP12

GP11

GP10

GP09

GP08

GP07

GP06

GP05

GP04

GP03

GP02

GP01

GP00

General-purpose input/output (GPIO) pins (I/O/Z). GPIO[15:0] pins are multiplexed at

power-on reset for configuration latching:

•

GPIO[0] is mapped to LENDIAN

GPIO[4:1] are mapped to BOOTMODE[3:0] (see Section 5.7)

GPIO[8:5] are mapped to DEVNUM[3:0]

GPIO[13:9] are mapped to CFGGP[4:0]

GPIO[14] is mapped to HPIWIDTH

I/O/Z

IPD

C5

F6

GPIO[15] is mapped to ECLKINSEL

B5

B4

D5

E5

A5

Terminal Configuration and Functions

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Table 3-2. Pin Attributes (continued)

BALL

SIGNAL NAME

NO.

TYPE IPD/IPU DESCRIPTION

HOST PORT INTERFACE (HPI)

HINT

L4

M5

L6

I/O/Z

Host interrupt from DSP to host (O/Z)

HCNTL1

HCNTL0

Host control -selects between control, address, or data registers (I) [default]

Host half-word select — first or second half-word (not necessarily high or low order).

HHWIL

L3

I/O/Z

For HPI16 bus width selection only] (I) [default]

Host read or write select (I) [default]

Host address strobe (I) [default]

HR/W

HAS

K5

M4

M3

L2

I/O/Z

HCS

Host chip select (I) [default]

HDS1

HDS2

HRDY

HD31

HD30

HD29

HD28

HD27

HD26

HD25

HD24

HD23

HD22

HD21

HD20

HD19

HD18

HD17

HD16

HD15

HD14

HD13

HD12

HD11

HD10

HD09

HD08

HD07

HD06

HD05

HD04

HD03

HD02

HD01

HD00

Host data strobe 1 (I) [default]

L5

Host data strobe 2 (I) [default]

M6

P3

N6

T5

P6

U5

N1

V2

M1

U6

V1

U1

N2

T1

P2

R1

N3

T2

P4

U2

N4

W1

R5

T3

N5

R4

T6

U4

R6

T4

P5

K6

W2

Host ready from DSP to host (O/Z) [default]

I/O/Z

Host-port data [31:16] pin (I/O/Z) [default]

I/O/Z

Host-port data [15:0] pin (I/O/Z) [default]

10

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Table 3-2. Pin Attributes (continued)

BALL

NO.

SIGNAL NAME

ABA1

TYPE IPD/IPU DESCRIPTION

EMIFA (64-BIT) — CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

EMIFA bank address control (ABA[1:0]). Active-low bank selects for the 64-bit EMIFA.

V24

V25

•

When interfacing to 16-bit Asynchronous devices, ABA1 carries bit 1 of the byte

address.

O/Z

IPD

IPU

ABA0

•

For an 8-bit Asynchronous interface, ABA[1:0] are used to carry bits 1 and 0 of the

byte address.

ACE5

ACE4

ACE3

V26

U27

W25

EMIFA memory space enables.

•

Enabled by bits 28 through 31 of the word address

Only one pin is asserted during any external data access

O/Z

NOTE

The SM320C6457-HIREL device does not have ACE0

and ACE1 pins.

ACE2

W26

ABE06

ABE05

ABE04

ABE03

ABE02

ABE01

ABE00

L25

L28

L27

Y28

W27

Y24

Y25

EMIFA byte-enable control.

•

Decoded from the low-order address bits. The number of address bits or byte

enables used depends on the width of external memory.

O/Z

IPU

•

Byte-write enables for most types of memory.

EMIFA (64-BIT) — BUS ARBITRATION

EMIFA hold-request-acknowledge to the host

EMIFA hold request from the host

EMIFA bus request output

AHOLDA

AHOLD

N25

R28

L26

O

I

IPU

ABUSREQ

O

EMIFA (64-BIT) — ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL

EMIFA external input clock. The EMIFA input clock (AECLKIN or SYSCLK7 clock) is

selected at reset via the pullup/pulldown resistor on the GPIO[15] pin.

AECLKIN

N28

I

IPD

NOTE: AECLKIN is the default for the EMIFA input clock.

EMIFA output clock [at EMIFA input clock (AECLKIN or SYSCLK7) frequency]

Asynchronous memory write-enable/Programmable synchronous interface write-enable

Asynchronous memory ready input

AECLKOUT

AAWE/ASWE

AARDY

V28

AA24

K28

O/Z

I

IPD

IPU

AR/W

W24

AE25

O/Z

Asynchronous memory read/write

AAOE/ASOE

Asynchronous/Programmable synchronous memory output-enable

Programmable synchronous address strobe or read-enable

•

For programmable synchronous interface, the R_ENABLE field in the Chip Select x

Configuration Register selects between ASADS and ASRE:

ASADS/ASRE

R25

O/Z

IPU

–

If R_ENABLE = 0, then the ASADS/ASRE signal functions as the ASADS signal.

If R_ENABLE = 1, then the ASADS/ASRE signal functions as the ASRE signal.

Terminal Configuration and Functions

11

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Table 3-2. Pin Attributes (continued)

BALL

SIGNAL NAME

NO.

TYPE IPD/IPU DESCRIPTION

EMIFA (64-BIT) — ADDRESS

EMIFA external address (word address) (O/Z)

EMIFA (64-BIT) — DATA

AEA19

AEA18

AEA17

AEA16

AEA15

AEA14

AEA13

AEA12

AEA11

AEA10

AEA09

AEA08

AEA07

AEA06

AEA05

AEA04

AEA03

AEA02

AEA01

AEA00

P24

M25

M24

P25

P26

T24

R26

N27

T25

N24

M26

R24

N26

T28

U28

R27

T27

T26

U26

U25

O/Z

IPD

O/Z

IPU

IPD

O/Z

IPD

AED63

AED62

AED61

AED60

AED59

AED58

AED57

AED56

AED55

AED54

AED53

AED52

AED51

AED50

AED49

AED48

AED47

AED46

AED45

AED44

AED43

AED42

AED41

AED40

AED39

G24

A26

C26

C27

E26

D27

D25

F26

H24

H25

D26

F27

B27

G26

B26

G27

J24

I/O/Z

IPU

EMIFA external data

K25

J25

J26

H26

J27

C28

J28

D28

12

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Table 3-2. Pin Attributes (continued)

BALL

NO.

SIGNAL NAME

AED38

AED37

AED36

AED35

AED34

AED33

AED32

AED31

AED30

AED29

AED28

AED27

AED26

AED25

AED24

AED23

AED22

AED21

AED20

AED19

AED18

AED17

AED16

AED15

AED14

AED13

AED12

AED11

AED10

AED09

AED08

AED07

AED06

AED05

AED04

AED03

AED02

AED01

AED00

TYPE IPD/IPU DESCRIPTION

K24

F28

G25

G28

K27

L24

K26

I/O/Z

IPU

EMIFA external data

Y26

AF28

AA28

AB26

Y27

AB25

AA26

AB24

AA25

AA27

AC28

AG27

AE28

AF27

AD28

AF26

AE27

AG25

AC27

AD26

AC25

AE26

AF25

AC26

AD25

AH26

AH25

AD27

AF24

AG26

AE24

AC24

I/O/Z

IPU

EMIFA external data

Terminal Configuration and Functions

13

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Table 3-2. Pin Attributes (continued)

BALL

SIGNAL NAME

NO.

TYPE IPD/IPU DESCRIPTION

DDR2 MEMORY CONTROLLER

DDRDQM0

DDRDQM1

DDRDQM2

DDRDQM3

DDRBA0

DDRBA1

DDRBA2

DDRA00

C10

C7

O/Z

DDR2 EMIF Data Masks

C19

C22

C14

D14

E14

F17

E17

D17

C17

E16

D16

C16

B16

D15

C15

B15

A15

A14

B14

A13

B13

A17

B17

A12

B12

C11

D11

A10

B10

C9

DDR Bank Address

DDRA01

DDRA02

DDRA03

DDRA04

DDRA05

DDRA06

O/Z

DDR2 EMIF Address Bus

DDRA07

DDRA08

DDRA09

DDRA10

DDRA11

DDRA12

DDRA13

DDRCLKOUTP0

DDRCLKOUTN0

DDRCLKOUTP1

DDRCLKOUTN1

DDRD00

DDRD01

DDRD02

DDRD03

DDRD04

DDRD05

DDRD06

DDRD07

DDRD08

DDRD09

DDRD10

DDRD11

DDRD12

DDRD13

DDRD14

DDRD15

DDRD16

DDRD17

DDRD18

DDRD19

DDRD20

O/Z

DDR2 EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)

D9

C8

D8

E8

O/Z

DDR2 EMIF Data Bus

F8

B7

A7

B6

A6

B18

A18

C18

D18

A20

14

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Table 3-2. Pin Attributes (continued)

BALL

NO.

SIGNAL NAME

DDRD21

TYPE IPD/IPU DESCRIPTION

B20

C20

D20

A21

B21

C21

D21

A23

B23

A24

B24

E12

D12

E13

C12

D13

E10

D10

E7

DDRD22

DDRD23

DDRD24

DDRD25

DDRD26

O/Z

DDR2 EMIF Data Bus

DDRD27

DDRD28

DDRD29

DDRD30

DDRD31

DDRCAS

O/Z

DDR2 EMIF Column Address Strobe

DDR2 EMIF Row Address Strobe

DDR2 EMIF Chip Enable

DDRRAS

DDRCE

DDRWE

DDR2 EMIF Write Enable

DDRCKE

DDR2 EMIF Clock Enable

DDRDQS0P

DDRDQS0N

DDRDQS1P

DDRDQS1N

DDRDQS2P

DDRDQS2N

DDRDQS3P

DDRDQS3N

DDRRCVENIN0

DDRRCVENOUT0

DDRRCVENIN1

DDRRCVENOUT1

DDRODT

D7

I/O/Z

DDR2 EMIF Data Strobe

E19

D19

E22

D22

A9

I

O/Z

I

B9

DDR2 EMIF Data Strobe Gate Input/Outputs to help meet DDR Timing

E20

F20

E15

A27

C13

O/Z

I

DDR2 EMIF On Die Termination Outputs used to set termination on the SDRAMs

DDR2 Slew rate control

DDRSLRATE

V_REFSSTL

A

Reference Voltage Input for SSTL18 buffers used by DDR2 EMIF (V_{DDS18_2}

)

TIMER 1

TOUT1L

TINP1L

AF19

AG19

O/Z

I

IPD

Timer 1 output pin for lower 32-bit counter

Timer 1 input pin for lower 32-bit counter

TIMER 0

TOUT0L

TINP0L

AG20

AH20

O/Z

I

IPD

Timer 0 output pin for lower 32-bit counter

Timer 0 input pin for lower 32-bit counter

INTER-INTEGRATED CIRCUIT (I²C)

SCL

SDA

F24

E24

I/O/Z

I²C clock. When the I²C module is used, use an external pullup resistor.

I²C data. When I²C is used, ensure there is an external pullup resistor.

Terminal Configuration and Functions

15

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Table 3-2. Pin Attributes (continued)

BALL

SIGNAL NAME

NO.

TYPE IPD/IPU DESCRIPTION

MULTICHANNEL BUFFERED SERIAL PORT (McBSP)

CLKS0

CLKR0

CLKX0

DR0

AA4

Y5

I

IPD

McBSP0 Module Clock

I/O/Z

I

McBSP0 Receive Clock

McBSP0 Transmit Clock

McBSP0 Receive Data

AB3

Y6

DX0

W6

V4

O/Z

I/O/Z

I

McBSP0 Transmit Data

McBSP0 Receive Frame Sync

McBSP0 Transmit Frame Sync

McBSP1 Module Clock

FSR0

FSX0

CLKS1

CLKR1

CLKX1

DR1

W4

Y1

Y4

I/O/Z

I

McBSP1 Receive Clock

McBSP1 Transmit Clock

McBSP1 Receive Data

AA3

W3

Y3

DX1

O/Z

I/O/Z

McBSP1 Transmit Data

McBSP1 Receive Frame Sync

McBSP1 Transmit Frame Sync

FSR1

FSX1

V5

W5

UNIVERSAL TEST AND OPERATIONS PHY INTERFACE for ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE]

UTOPIA SLAVE (ATM CONTROLLER) — TRANSMIT INTERFACE

UXCLK

A4

I

Source clock for UTOPIA transmit driven by Master ATM Controller.

Transmit cell available status output signal from UTOPIA Slave.

UXCLAV

C3

O/Z

•

0 indicates a complete cell is NOT available for transmit

1 indicates a complete cell is available for transmit

UTOPIA transmit interface enable input signal. Asserted by the Master ATM Controller to

indicate that the UTOPIA Slave should put out on the Transmit Data Bus the first byte of

valid data and the UXSOC signal in the next clock cycle.

UXENB

UXSOC

B3

G4

I

Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the rising

edge of the UXCLK, indicating that the first valid byte of the cell is available on the 8-bit

Transmit Data Bus (UXDATA[7:0]).

O/Z

UXADDR4

UXADDR3

UXADDR2

UXADDR1

UXADDR0

UXDATA7

UXDATA6

UXDATA5

UXDATA4

UXDATA3

UXDATA2

UXDATA1

UXDATA0

J4

H5

K3

J5

UTOPIA transmit address pins (UXADDR[4:0]) (I) 5-bit Slave transmit address input pins

driven by the Master ATM Controller to identify and select one of the Slave devices (up

to 31 possible) in the ATM System.

I

H4

F3

E4

C4

A3

H3

G3

F4

E3

UTOPIA 8-bit transmit data bus (I/O/Z) Using the Transmit Data Bus, the UTOPIA Slave

(on the rising edge of the UXCLK) transmits the 8-bit ATM cells to the Master ATM

Controller.

O/Z

16

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Table 3-2. Pin Attributes (continued)

BALL

NO.

TYPE IPD/IPU DESCRIPTION

UTOPIA SLAVE (ATM CONTROLLER) — RECEIVE INTERFACE

URCLK

C1

B2

I

Source clock for UTOPIA receive driven by Master ATM Controller.

Receive cell available status output signal from UTOPIA Slave.

URCLAV

O/Z

•

0 indicates NO space is available to receive a cell from Master ATM Controller.

1 indicates space is available to receive a cell from Master ATM Controller.

UTOPIA receive interface enable input signal. Asserted by the Master ATM Controller to

indicate to the UTOPIA Slave to sample the Receive Data Bus (URDATA[7:0]) and

URSOC signal in the next clock cycle or thereafter.

URENB

URSOC

K4

G2

I

Receive Start-of-Cell signal. This signal is output by the Master ATM Controller to

indicate to the UTOPIA Slave that the first valid byte of the cell is available to sample on

the 8-bit Receive Data Bus (URDATA[7:0]).

URADDR4

URADDR3

URADDR2

URADDR1

URADDR0

URDATA7

URDATA6

URDATA5

URDATA4

URDATA3

URDATA2

URDATA1

URDATA0

K1

K2

J1

UTOPIA receive address pins [URADDR[4:0] (I)]: 5-bit Slave receive address input pins

driven by the Master ATM Controller to identify and select one of the Slave devices (up

to 31 possible) in the ATM System.

I

J3

H2

G1

F2

F1

E2

E1

D2

D1

C2

UTOPIA 8-bit Receive Data Bus (I/O/Z). Using the Receive Data Bus, the UTOPIA Slave

(on the rising edge of the URCLK) can receive the 8-bit ATM cell data from the Master

ATM Controller.

I

SERIAL RAPIDIO (SRIO)

RIORXN0

RIORXP0

RIORXN1

RIORXP1

RIORXN2

RIORXP2

RIORXN3

RIORXP3

RIOTXN0

RIOTXP0

RIOTXN1

RIOTXP1

RIOTXN2

RIOTXP2

RIOTXN3

RIOTXP3

AG8

AG9

AF11

AF10

AH13

AH12

AE13

AE12

AE9

I

Serial RapidIO Receive Data (4 links)

AE8

AH9

AH10

AF13

AF14

AG13

AG14

O

Serial RapidIO Transmit data (4 links)

ETHERNET MAC (EMAC) AND SGMII

SGMIIRXN

SGMIIRXP

SGMIITXN

SGMIITXP

AF16

AF17

AH15

AH14

I

Ethernet MAC SGMII Receive Data

O

Ethernet MAC SGMII Transmit Data

Terminal Configuration and Functions

17

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Table 3-2. Pin Attributes (continued)

BALL

SIGNAL NAME

NO.

TYPE IPD/IPU DESCRIPTION

MANAGEMENT DATA INPUT/OUTPUT (MDIO)

MDIO

AH19

AH18

I/O/Z

O

IPU

IPD

MDIO Data

MDCLK

MDIO Clock

VOLTAGE CONTROL TERMINALS

PTV18

A16

A

PTV Compensation NMOS Reference Input. Install with 47-Ω, 5% resistor to GND

SUPPLY VOLTAGE MONITOR TERMINALS

1.1-V CV_DDSupply Monitor

CV_DDMON

U19

U22

G23

A

DV_DD33MON

DV_DD18MON

3.3-V DV_DDSupply Monitor

1.8-V DV_DDSupply Monitor

SUPPLY VOLTAGE TERMINALS

AE10

AE16

AC10

AC12

AC14

AC16

U13

V_DDR18

S

1.8-V I/O supply voltage (SRIO/SGMII SerDes regulator supply).

SRIO/SGMII analog supply:

1.1-V I/O supply voltage

Do not use core supply.

V_DDA11

V12

SRIO/SGMII SerDes digital supply:

1.1-V I/O supply voltage

V14

V_DDD11

S

W11

W13

W15

AD9

Do not use core supply.

AD11

AD13

AD15

AD17

AF9

SRIO/SGMII SerDes termination supply:

1.1-V I/O supply voltage

V_DDT11

S

Do not use core supply.

AF15

AG11

AH17

AA6

AB18

AB20

AB7

AC19

AC21

AC3

AC8

DV_DD18

S

1.8-V I/O supply voltage

AD18

AD22

AF18

AG5

AH1

B11

B19

B22

18

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Table 3-2. Pin Attributes (continued)

BALL

NO.

TYPE IPD/IPU DESCRIPTION

B8

E11

E21

E23

E9

F10

F12

F14

F16

F18

G11

G13

G15

G17

G19

G21

G7

DV_DD18

S

1.8-V I/O supply voltage

G9

J7

V6

Y7

A1

A28

AA23

AB22

AB28

AC23

AD24

AH24

AH28

D3

E25

E27

H1

DV_DD33

S

3.3-V I/O supply voltage

H22

H27

J23

K22

L1

L23

L7

M22

M27

N23

N7

P1

P22

Terminal Configuration and Functions

19

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Table 3-2. Pin Attributes (continued)

BALL

SIGNAL NAME

NO.

P27

R23

R3

TYPE IPD/IPU DESCRIPTION

R7

T22

U7

DV_DD33

S

3.3-V I/O supply voltage

V22

V3

W23

Y22

K10

K12

K14

K16

K18

L11

L13

L15

L17

L19

M10

M12

M14

M16

M18

N11

N13

N15

N17

CV_DD

S

1.1-V core supply voltage

20

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Table 3-2. Pin Attributes (continued)

BALL

NO.

TYPE IPD/IPU DESCRIPTION

N19

P10

P12

P14

P16

P18

R11

R13

R15

R17

R19

T12

T14

T16

T18

U11

U15

U17

V10

V16

V18

W17

W19

AC5

F7

CV_DD

S

1.1-V core supply voltage

PLLV₁

PLLV₂

S

1.8-V PLL Supply

Terminal Configuration and Functions

21

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Table 3-2. Pin Attributes (continued)

BALL

SIGNAL NAME

NO.

TYPE IPD/IPU DESCRIPTION

GROUND PINS

A11

A19

A2

A22

A8

AA2

AA22

AA7

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB19

AB21

AB23

AB27

AB6

VSS

GND

Ground pins

AB8

AB9

AC11

AC13

AC15

AC17

AC18

AC20

AC22

AC9

AD10

AD12

AD14

AD16

AD19

AD2

22

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Table 3-2. Pin Attributes (continued)

BALL

NO.

TYPE IPD/IPU DESCRIPTION

AD23

AD8

AE11

AE14

AE15

AE17

AE18

AF5

AF8

AG1

AG10

AG12

AG15

AG17

AG18

AG24

AG28

AH11

AH16

AH2

AH27

AH8

B1

VSS

GND

Ground pins

B28

D4

E18

E28

F11

F13

F15

F19

F21

F22

F25

F9

G10

G12

G14

Terminal Configuration and Functions

23

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Table 3-2. Pin Attributes (continued)

BALL

SIGNAL NAME

NO.

G16

G18

G20

G22

G8

TYPE IPD/IPU DESCRIPTION

H23

H28

H7

J2

J22

K11

K13

K15

K17

K19

K23

K7

L10

L12

L14

L16

L18

L22

M11

M13

M15

M17

M19

M2

VSS

GND

Ground pins

M23

M28

M7

N10

N12

N14

N16

N18

N22

24

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Table 3-2. Pin Attributes (continued)

BALL

NO.

TYPE IPD/IPU DESCRIPTION

P11

P13

P15

P17

P19

P23

P28

P7

R12

R14

R16

R18

R2

R22

T11

T13

T15

T17

T19

T23

T7

VSS

GND

Ground pins

U10

U12

U14

U16

U18

U23

U24

U3

V11

V13

V15

V17

V19

V23

V27

V7

W10

W12

W14

W16

W18

W22

W7

VSS

GND

Ground pins

Y23

Terminal Configuration and Functions

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Table 3-2. Pin Attributes (continued)

BALL

SIGNAL NAME

NO.

TYPE IPD/IPU DESCRIPTION

RESERVED PINS

Reserved - Unconnected

Reserved - Connect to GND

Reserved - Unconnected

Reserved - Pullup to DV_DD18with 10-kΩ resistor.

Reserved - Connected to CV_DD

Reserved - Unconnected

RSV01

RSV02

RSV03

RSV04

RSV05

RSV06

RSV07

RSV08

RSV09

RSV10

RSV11

RSV12

RSV13

RSV14

RSV15

RSV16

RSV17

RSV18

RSV19

RSV20

RSV21

RSV22

RSV23

RSV24

RSV25

RSV26

RSV27

RSV28

RSV29

AC4

AB2

I/O/Z

O/Z

A

IPU

IPD

AB4

AD20

AD21

AE20

AE21

AE7

A

O

AF7

O

H6

O

J6

O

AB5

A

AA5

A

AF20

AF21

AF12

AG16

AH21

AG21

AC6

AC7

AE23

R10

I/O/Z

A

IPU

A

I

IPU

S

T10

S

AD6

G5

O/Z

IPD

AE22

AF22

AG23

AH22

26

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3.2.1 Pin Map

Figure 3-2 through Figure 3-5 show the SM320C6457-HIREL pin assignments in four quadrants (A, B, C,

and D).

2

3

4

7

8

9

10

11

12

13

14

1

5

6

V_{DDS18_1}

V_SS

AH

AG

AF

AE

AD

AC

AB

AA

Y

TCLK

EMU4

EMU2

CORECLKP CORECLKN

RIOTXN1

RIOTXP1

RIORXN1

RIORXP1

SGMIITXP

AH

AG

AF

AE

AD

AC

AB

AA

Y

RIOSGMII

CLKN

RIOSGMII

CLKP

V_{DDS18_1}

V_SS

V_DDT

V_SS

EMU7

EMU8

EMU13

EMU10

EMU5

EMU6

EMU3

EMU9

RSV01

RSV03

CLKS0

CLKR1

FSX0

RIORXN0

RIORXP0

RIOTXN3

RIOTXN2

RIORXN3

V_DDT

RIOTXP3

ALTCORE

CLK

V_SS

V_DDT

TDO

EMU12

EMU15

EMU14

TDI

EMU11

RSV09

RSV08

RIORXP1

RIORXN1

RSV16

RIORXP3

V_SS

RIOTXP2

CORE

CLKSEL

V_DDR4

V_SS

EMU1

EMU0

RIOTXP0

RIOTXN0

TRST

SYSCLK

OUT

V_SS

V_DDT

V_SS

V_DDA

V_SS

V_DDT

V_SS

V_DDA

V_SS

EMU16

RSV24

RSV20

V_SS

V_{DDS18_1}

V_DDA18V1

V_SS

V_DDA

V_SS

EMU18

RSV02

V_SS

RSV21

V_{DDS18_1}

V_SS

CLKX0

CLKX1

DX1

RSV12

RSV13

CLKR0

FSX1

V_{DDS18_1}

V_SS

V_{DDS18_1}

V_SS

EMU17

CLKS1

HD11

TMS

HD00

HD25

HD13

HD15

DR0

V_SS

V_DDD

V_SS

V_DDD

V_SS

V_DDD

V_SS

V_DDD

V_SS

W

DR1

DX0

W

V_{DDS18_1}

V_DDS33

V_SS

V_DD

V_SS

V

HD22

HD21

HD19

FSR0

FSR1

V

V_DDS33

V_SS

V_DD

V_DDD

V_SS

U

HD05

HD27

HD23

HD06

U

V_SS

V_DD

V_SS

V_DD

T

HD09

HD03

HD29

RSV23

T

V_SS

V_DDS33

V_DD

V_SS

V_DD

V_SS

R

HD17

1

HD07

4

HD10

5

HD04

6

RSV23

10

R

2

3

7

8

9

11

12

13

14

Figure 3-2. SM320C6457-HIREL Pin Map (Bottom View) [Quadrant A]

Terminal Configuration and Functions

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15

16

17

18

19

20

21

22

23

24

25

26

27

28

SGMIITXN

AH

V_SS

AED05

V_DDT

MDCLK

MDIO

TINP0L

RSV18

RSV29

RESET

V_{DDS33_1}

AED06

V_SS

V_{DDS33_1}

AH

AG

AF

AE

AD

AC

AB

AA

Y

V_SS

AED14

AED02

AG

AF

AE

AD

AC

AB

AA

Y

RSV17

V_SS

TINP1L

TOUT1L

NMI

TOUT0L

RSV14

RSV06

RSV19

RSV15

RSV07

POR

RSV28

AED20

AED18

AED15

AED04

AED13

V_SS

RESETSTAT

V_DDT

SGMIIRXN SGMIIRXP

V_{DDS18_2}

RSV27

AED03

AED09

AOE

AED16

AED10

AED30

AED19

AED17

AED21

V_{DDS33_1}

V_SS

V_DDT

V_SS

RSV26

RSV22

AED01

V_DDR3

V_{DDS18_2}

V_{DDS33_1}

V_DDT

V_SS

RSV04

RSV05

AED07

AED11

AED26

AED23

AED12

AED08

V_{DDS18_2}

V_SS

V_{DDS33_1}

V_SS

AED00

AED24

ASDWE

V_{DDS18_2}

V_SS

V_{DDS33_1}

V_SS

V_DDA

V_SS

V_{DDS18_2}

V_SS

AED28

AED25

V_SS

V_{DDS18_2}

V_SS

V_{DDS33_1}

AED22

AED27

ABE02

V_SS

AED29

V_SS

V_{DDS33_1}

ABE01

ARNW

ABE00

ACE3

AED31

ACE2

ABE03

ABE07

V_DDD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_{DDS33_1}

V_SS

W

V_{DDS33_1}

V_SS

ABA1

ABA0

ACE5

AEA01

AEA02

AECLKOUT

AEA05

V

V_DDMON

V_DD

V_SS

AEA00

AEA11

ACE4

AEA03

U

V_DD33MON

U

V_SS

AEA06

AEA14

T

V_{DDS33_1}

T

V_DD

V_SS

V_DD

V_SS

V_DD

V_{DDS33_1}

AEA08

24

AADS

25

AEA13

26

AEA04

27

AHOLD

28

R

V_SS

R

15

16

17

18

19

20

21

22

23

Figure 3-3. TCI648F Pin Map (Bottom View) [Quadrant B]

28

Terminal Configuration and Functions

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15

16

17

18

19

20

21

22

23

24

25

26

27

28

V_{DDS33_1}

V_SS

V_DD

V_SS

V_DD

V_SS

P

N

M

L

AEA19

AEA16

AEA15

P

N

M

L

V_{DDS33_1}

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_{DDS33_1}

V_SS

AECLKIN

AEA10

AEA17

AED33

AEA07

AEA09

AEA12

AHOLDA

AEA18

V_SS

V_{DDS33_1}

V_SS

V_{DDS33_1}

ABUSREQ0

ABE06

AED46

AED45

AED54

ABE04

AED34

AED42

V_{DDS33_1}

ABE05

AARDY

AED40

V_SS

V_{DDS33_1}

V_SS

K

J

AED38

AED47

AED32

AED44

K

J

V_SS

V_{DDS33_1}

V_SS

AED55

AED43

H

G

F

H

G

F

V_DDS18

V_SS

V_DDS18

V_SS

V_DDS18

V_SS

V_DDS18

V_SS

V_DDS18

V_SS

V_DD18MON

AED63

SCL

AED36

AED50

AED56

AED59

AED53

AED61

AED49

AED48

AED35

AED37

V_SS

DDRRCVEN

OUT1

V_SS

V_DDS18

V_SS

DDRA00

DDRA01

DDRA02

DDRA03

GP15

AED52

DDRRCVEN

IN1

V_{DDS33_1}

V_DDS18

E

D

C

B

A

DDRODT

DDRA08

DDRA09

DDRA10

DDRA04

DDRA05

DDRA06

DDRA07

DDRDQS2P

DDRDQS3P

SDA

E

D

C

B

A

DDRD19 DDRDQS2N DDRD23

DDRD27 DDRDQS3N

GP14

GP13

GP12

GP09

DDRD31

AED57

GP11

AED58

AED60

AED51

AED39

AED41

V_SS

DDRD18

DDRD16

DDRDQM2

DDRD22

DDRD21

DDRD26

DDRD25

DDRDQM3

DDRCLK

OUT_N1

V_DDS18

DDRD29

GP08

DDRCLK

OUT_P1

V_{DDS33_1}

V_SS

DDRA11

15

PTV18

16

DDRD17

18

DDRD20

20

DDRD24

21

DDRD28

23

DDRD30

24

GP10

25

AED62

26

DDRSLRATE

27

17

19

22

28

Figure 3-4. TCI648F Pin Map (Bottom View) [Quadrant C]

Terminal Configuration and Functions

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2

3

4

5

7

8

9

10

11

12

13

14

1

6

V_DD

V_SS

V_DD

V_SS

V_DD

V_DDS33

HD28

HD18

V_SS

P

N

M

L

HD31

HD14

HD02

P

N

M

L

V_DDS33

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

HD26

HD20

HD16

HCS

HD12

HAS

HD08

HCNTL1

HDS2

HD30

HRDY

V_SS

HD24

V_DDS33

HHWIL

HCNTL0

HD01

HDS1

HINT

V_SS

K

J

URADDR4 URADDR3 UXADDR2

URENB

HR/W

K

J

V_SS

V_DDS18

URADDR2

URADDR1 UXADDR4 UXADDR1

RSV11

V_DDS33

V_SS

H

G

F

URADDR0

URSOC

UXDATA3

UXDATA2

UXDATA7

UXDATA0

V_DDS33

UXADDR0 UXADDR3

RSV10

H

G

F

V_DDS18

V_SS

V_DDS18

V_SS

V_DDS18

URDATA7

URDATA5

URDATA3

URDATA1

URCLK

UXSOC

UXDATA1

UXDATA6

V_SS

RSV25

GP07

GP01

GP02

GP06

GP04

DDRCLKSEL

V_SS

V_DDA18V2

V_SS

V_DDS18

V_SS

V_DDS18

V_SS

V_DDS18

URDATA6

URDATA4

URDATA2

URDATA0

URCLAV

GP05

DDRD11

DDRREF

CLKN

V_DDS18

E

D

C

B

A

DDRDQS1P DDRD10

DDRDQS1N DDRD09

DDRDQS0P

DDRBA2

DDRBA1

DDRBA0

DDRA13

E

D

C

B

A

DDRCAS

DDRRAS

DDRWE

DDRD01

DDRCE

DDRCKE

V_REFSSTL

DDRREF

CLKP

DDRD07 DDRDQS0N DDRD03

UXCLAV

UXENB

UXDATA5

GP03

ALTDDRCLK DDRDQM1

DDRD08

DDRD06

DDRDQM0

DDRD05

DDRD02

DDRRCVEN

OUT0

DDRCLK

OUT_N0

V_SS

V_DDS18

DDRD14

DDRD12

DDRRCVEN

IN0

DDRCLK

OUT_P0

V_DDS33

V_SS

UXDATA4

UXCLK

GP00

5

DDRD15

DDRD13

DDRD04

10

DDRD00

12

DDRA12

14

1

2

3

4

6

7

8

9

11

13

Figure 3-5. TCI648F Pin Map (Bottom View) [Quadrant D]

30

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3.3 Signal Descriptions

Figure 3-6 shows the CPU and core peripheral signal groups.

CORECLKP

CORECLKN

Clock/PLL1

ALTCORECLK

and

RESETSTAT

RESET

NMI

Reset and

Interrupts

CORECLKSEL

SYSCLKOUT

AV_DD118

PLL Controller

POR

DDRREFCLKP

DDRREFCLKN

ALTDDRCLK

DDRCLKSEL

Clock/PLL2

AV_DD218

TMS

TDO

TDI

TCK

TRST

Reserved

RSV

IEEE Standard

1149.1

(JTAG)

EMU0

EMU1

Emulation

•

EMU14

EMU15

EMU16

EMU17

EMU18

Peripheral

Enable/Disable

Control/Status

Figure 3-6. CPU and Peripheral Signals

Terminal Configuration and Functions

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Figure 3-7 shows the timer peripheral I/O, the general purpose I/O, the Serial RapidIO, and the general

purpose I/O reference clock, transmit, and receive signals.

TOUTL0

TINPL0

TINPL1

Timer 0

Timer 1

TOUTL1

Timers (64-Bit)

GP[7]

GP[6]

GP[5]

GP[4]

GP[15]

GP[14]

GP[13]

GP[12]

GP[11]

GP[10]

GP[9]

GPIO

GP[3]

GP[2]

GP[1]

GP[0]

GP[8]

General-Purpose Input/Output (GPIO) Port

RIOTXN0

RIOTXP0

RIOTXN1

RIOTXP1

RIOTXN2

RIOTXP2

RIOTXN3

RIOTXP3

RIOSGMIICLKN^(A)

RIOSGMIICLKP^(A)

Transmit

Clock

RIORXN0

RIORXP0

RIORXN1

RIORXP1

RIORXN2

RIORXP2

RIORXN3

RIORXP3

Receive

RapidIO

Figure 3-7. Timers/GPIO/RapidIO Peripheral Signals

(A) Reference clock to drive RapidIO and SGMII.

32

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Figure 3-8 shows the EMIFA and DDR2 peripheral interfaces.

64

Data

AED[63:0]

AECLKIN

ACE5^(A)

ACE4^(A)

ACE3^(A)

AECLKOUT

Memory Map

Space Select

ACE2^(A)

External

Memory I/F

Control

20

Address

AEA[19:0]

ASWE/AAWE

AARDY

ABE7

ABE6

AR/W

AAOE/ASOE

ASADS/ASRE

ABE5

ABE4

ABE3

ABE2

Byte Enables

ABE1

ABE0

AHOLD

Bus

AHOLDA

ABUSREQ

Arbitration

Bank Address

ABA[1:0]

EMIFA (64-bit Data Bus)

DDRCLKOUTP[1:0]

DDRCLKOUTN[1:0]

DDRCKE

32

DDRD[31:0]

Data

DDRCAS

DDRRAS

DDRWE

Memory Map

Address

DDRCE

DDRDQSP[3:0]

DDRDQSN[3:0]

External

Memory

Controller

14

DDRA[13:0]

DDRRCVENIN[2:0]

DDRRCVENOUT[2:0]

DDRODT

DDRDQM0

DDRDQM1

DDRDQM2

DDRDQM3

DDRSLRATE

V_REFSSTL

Byte Enables

DDRBA0

DDRBA1

DDRBA2

Bank Address

DDR2 Memory Controller (32-bit Data Bus)

Figure 3-8. EMIFA and DDR2 Memory Controller Peripheral Signals

(A) The EMIFA ACE0 and ACE1 are not functionally supported on SM320C6457-HIREL devices.

Terminal Configuration and Functions

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Figure 3-9 shows the HPI, McBSP, and I²C peripheral signals.

HPI^(A)

32

(Host-Port Interface)

HD[15:0]

HD[31:16]

Data

HAS

HR/W

HCS

HCNTL0

HCNTL1

Register Select

Control

HDS1

HDS2

HRDY

Half-Word

Select

HHWIL

(HPI16 ONLY)

HINT

McBSP1

Transmit

McBSP0

Transmit

CLKX0

CLKX1

FSX0

DX0

FSX1

DX1

CLKR0

FSR0

DR0

CLKR1

FSR1

DR1

Receive

Clock

Receive

Clock

CLKS0

CLKS1

McBSPs

(Multichannel Buffered Serial Ports)

SCL

SDA

I2C

Figure 3-9. HPI/McBSP/I²C Peripheral Signals

(A) When the HPI is enabled, the number of HPI pins used depends on the HPI configuration (HPI16 or HPI32).

34

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Figure 3-10 shows the EMAC/MDIO (SGMII) peripheral signals.

Ethernet MAC

(EMAC)

SGMIITXN

SGMIITXP

SGMII

Transmit

MDIO

SGMIIRXN

SGMIIRXP

SGMII

Receive

MDCLK

RIOSGMIICLKN^(A)

RIOSGMIICLKP^(A)

SGMII

Clock

Ethernet MAC (EMAC) and MDIO

Figure 3-10. EMAC/MDIO (SGMII) Peripheral Signals

(A) Reference clock to drive RapidIO and SGMII.

Terminal Configuration and Functions

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Figure 3-11 shows the UTOPIA peripheral signals.

UTOPIA (SL AVE)

URDA TA7

URDA TA6

URDA TA5

URDA TA4

URDA TA3

URDA TA2

UXDATA7

UXDATA6

UXDATA5

UXDATA4

UXDATA3

UXDATA2

UXDATA1

UXDATA0

Receive

Transmit

URDA TA1

URDA TA0

UXENB

URENB

URADDR4

UXADDR4

UXADDR3

UXADDR2

UXADDR1

UXADDR0

UXCL AV

UXSOC

URADDR3

URADDR2

URADDR1

URADDR0

URCL AV

URSOC

Control/Status

Clock

URCLK

UXCLK

Figure 3-11. UTOPIA Peripheral Signals

36

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4 Specifications

4.1 Absolute Maximum Ratings

Over operating junction temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

1.35

2.45

3.6

UNIT

CV_DD

DV_DD18

DV_DD33

0.49 ×

DV_DD18

0.51 ×

DV_DD18

V_REFSSTL

Supply voltage⁽²⁾

V

V_DD11, V_DDD11, V_DDT11

V_DDR18

–0.3

1.35

2.45

AV_DD118, AV_DD218

V_SSground

0

DV_DD18

0.3

+

LVCMOS (1.8 V)

–0.3

DV_DD33

0.3

+

LVCMOS (3.3 V)

DDR2

I²C

–0.3

2.45

Input voltage, V_I

V

D_VDD18

0.3

+

LVDS

LJCB

SerDes

–0.3

1.35

D_VDD11

0.3

+

DV_DD18

0.3

LVCMOS (1.8 V)

LVCMOS (3.3 V)

–0.3

DV_DD33

0.3

Output voltage, V_O

V

DDR2

I²C

–0.3

2.45

DV_DD11

0.3

+

SerDes

–0.3

–55

Operating case temperature,

T_C

Extended

1-GHz CPU

100

°C

LVCMOS (1.8 V)

LVCMOS (3.3 V)

DDR2

20%

Overshoot/undershoot⁽³⁾

overshoot/undershoot for

20% of signal duty cycle

V

I²C

Storage temperature, T_stg

–65

150

°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS

.

(3) Overshoot/undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS

signals is DV_DD18+ 0.2 × DV_DD18and maximum undershoot value would be V_SS- 0.2 × DV_DD18

Specifications

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4.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM)⁽²⁾

Charged-device model (CDM)⁽³⁾⁽⁴⁾

±1000

±500

V_ESD

ESD stress voltage⁽¹⁾

V

(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP 155 states that 500V HBM allows

safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary

precautions are taken. Pins listed as 1000V may actually have higher performance.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP 157 states that 250V CDM allows safe

manufacturing with a standard ESD control process. Pins listed as 250V may actually have higher performance.

(4) Based on JESD22-C101C (Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of

Microelectronic Components), the C6457 device’s charged-device model (CDM) sensitivity classification is Class II (200 V to < 500 V).

Specifically, DDR memory interface and SerDes pins conform to ±200-V level. All other pins conform to ±500 V.

4.3 Recommended Operating Conditions

MIN

1.067

NOM

MAX UNIT

850-MHz CPU

1-GHz CPU

1.1

1.133

V

CV_DD

Supply core voltage

1.067

1.1

1.133

DV_DD18

DV_DD33

V_REFSSTL

V_DDR18

V_DDA11

V_DDD11

V_DDT11

PLLV₁

PLLV₂

V_SS

1.8-V supply I/O voltage

1.71

1.8

1.89

3.465

V

3.3-V supply I/O voltage

3.135

3.3

DDR2 reference voltage

SRIO/SGMII SerDes regulator supply

SRIO/SGMII SerDes analog supply

SRIO/SGMII SerDes digital supply

SRIO/SGMII SerDes termination supply

PLL1 analog supply

0.49 × DV_DD18

1.71

0.5 × DV_DD18

0.51 × DV_DD18

1.89

1.8

1.1

1.8

0

1.045

1.155

1.045

1.155

1.045

1.155

1.71

1.89

PLL2 analog supply

1.71

1.89

Ground

0

LVCMOS (1.8 V)

0.65 × DV_DD18

2

LVCMOS (3.3 V)

I²C

V_IH

High-level input voltage

0.7 × DV_DD18

DDR2 EMIF

V_REFSSTL

+

DV_DD18+ 0.3

0.125

LVCMOS (1.8 V)

LVCMOS (3.3 V)

DDR2 EMIF

I²C

0.35 × DV_DD18

0.8

V

V_IL

Low-level input voltage

-0.3

–55

V_REFSSTL– 0.1

0.3 × DV_DD18

Operating case

temperature

T_C

Extended

1-GHz CPU

100

°C

38

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4.4 Electrical Characteristics

over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)

PARAMETER

LVCMOS (1.8 V)

TEST CONDITIONS⁽¹⁾

MIN

DV_DD18– 0.45

2.4

TYP

MAX UNIT

I_O= I_OH

LVCMOS (3.3 V)

DDR2

I_O= -2 mA

V_OHHigh-level output voltage

V_OLLow-level output voltage

V

1.4

I²C

0.1 × DV_DD18

LVCMOS (1.8 V)

LVCMOS (3.3 V)

DDR2

I_O= I_OL

0.45

0.4

I_O= 2 mA

V

0.4

I_O= 3 mA, pulled up to

1.8 V

I²C

0.4

No IPD/IPU

–5

50

5

170

-50

1

LVCMOS (1.8 V)

Internal pullup

Internal pulldown

No IPD/IPU

100

–170

–1

-100

I_I⁽²⁾

Input current [DC]

µA

LVCMOS (3.3 V)

I²C

Internal pullup

Internal pulldown

0.1 × DV_DD18V < V_I<

70

150

270

–70

–270

–150

–20

20

–8

0.9 × DV_DD18

V

EMU[18:00], GPIO[15:0],

TIMO[1:0]

SYSCLKOUT, TDO, CLKR0,

CLKX0, DX0, FSR0, FSX0,

CLKR1, CLKX1, DX1, FSR1,

FSX1, AECLKOUT

–6

High-level output current

[DC]

I_OH

mA

RESETSTAT, MDIO, MDCLK

DDR2

–4

4

LVCMOS (3.3 V), except

AECLKOUT

–4

8

EMU[18:00], GPIO[15:0],

TIM[1:0]

SYSCLKOUT, TDO, CLKR0,

CLKX0, DX0, FSR0, FSX0,

CLKR1, CLKX1, DX1, FSR1,

FSX1, AECLKOUT

6

Low-level output current

[DC]

I_OL

mA

µA

RESETSTAT, MDIO, MDCLK

DDR2

4

–4

LVCMOS (3.3 V), except

AECLKOUT

4

(3)

I_OZ

LVCMOS (1.8 V)

LVCMOS (3.3 V)

–20

20

Off-state output current

[DC]

(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

(2) I_Iapplies to input-only pins and bi-directional pins. For input-only pins, I_Iindicates the input leakage current. For bi-directional pins, I_I

includes input leakage current and off-state (Hi-Z) output leakage current.

(3) I_OZapplies to output-only pins, indicating off-state (Hi-Z) output leakage current.

4.5 Thermal Resistance Characteristics

Table 4-1 shows the thermal resistance characteristics for the PBGA - GMH mechanical package.

Table 4-1. Thermal Resistance Characteristics GMH Package

NO.

1

°C/W

1.53

8.1

Rθ_JC

Rθ_JB

Junction-to-case

Junction-to-board

2

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4.6 Timing and Switching Characteristics

4.6.1 Timing Parameters and Information

This section describes the conditions used to capture the electrical data seen in this chapter.

Data Manual Timing Reference Point

Tester Terminal Electronics

42 W

3.5 nH

Output Under Test

Transmission Line

Zo = 50 W

(see Note A)

Device Terminal

(see Note B)

4.0 pF

1.85 pF

Figure 4-1. Test Load Circuit for AC Timing Measurements

(A) The data manual provides timing at the device terminal. For output timing analysis, the tester terminal electronics and its transmission

line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect.

The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet

timings.

(B) Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device terminal.

The load capacitance value stated is only for characterization and measurement of AC timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

4.6.1.1 1.8-V Signal Transition Levels

All input and output timing parameters are referenced to 0.9 V for both 0 and 1 logic levels.

V_ref= 0.9 V

Figure 4-2. Input and Output Voltage Reference Levels for 1.8-V AC Timing Measurements

All rise and fall transition timing parameters are reference to V_ILMAX and V_IHMIN for input clocks.

V_ref= V_IHMIN (or V_OHMIN)

Figure 4-3. Rise and Fall Transition Time Voltage Reference Levels

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4.6.1.2 3.3-V Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both 0 and 1 logic levels.

V_ref= 1.5 V

Figure 4-4. Input and Output Voltage Reference Levels for 3.3-V AC Timing Measurements

All rise and fall transition timing parameters are referenced to V_ILMAX and V_IHMIN for input clocks, V_OL

MAX and V_OHMIN for output clocks.

V_ref= V_IHMIN (or V_OHMIN)

Figure 4-5. Rise and Fall Transition Time Voltage Reference Levels

4.6.1.3 3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

4.6.1.4 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information

specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to

attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis

application report (SPRA839). If needed, external logic hardware such as buffers may be used to

compensate any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external

device and from the external device to the DSP. This round-trip delay tends to negatively impact the input

setup time margin, but also tends to improve the input hold time margins (see Table 4-2 and Figure 4-6).

Table 4-2. Board-Level Timing Example

(see Figure 4-6)

NO.

1

DESCRIPTION

Clock route delay

2

Minimum DSP hold time

3

Minimum DSP setup time

External device hold time requirement

External device setup time requirement

Control signal route delay

External device hold time

External device access time

DSP hold time requirement

DSP setup time requirement

Data route delay

4

5

6

7

8

9

10

11

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Figure 4-6 shows a general transfer between the DSP and an external device. The figure also shows

board route delays and how they are perceived by the DSP and the external device

AECLKOUT

(Output from DSP)

1

AECLKOUT

(Input to External Device)

2

3

Control Signals ^(A)

(Output from DSP)

4

5

6

Control Signals

(Input to External Device)

7

8

Data Signals ^(B)

(Output from External Device)

9

10

11

Data Signals ^(B)

(Input to DSP)

Figure 4-6. Board-Level Input/Output Timings

(A) Control signals include data for writes.

(B) Data signals are generated during reads from an external device.

4.6.2 Power Supply Sequencing

The following sections describe the proper power-supply sequencing and timing needed to properly power

on the C6457 DSP. This section also describes proper power-supply decoupling methods.

TI recommends the power-supply sequence shown in Figure 4-7 and described in Table 4-3. The figure

shows that the 1.8-V I/O supply should be ramped first. This is followed by the scaled core supply and the

fixed 1.1-V supplies which must ramp within 5 ms of each other. The 3.3-V I/O supply should ramp up last.

Some TI power supply devices include features that facilitate power sequencing; for example, Auto-Track

or Slow-Start/Enable features. For more information, visit www.ti.com/dsppower. See the TMS320TCI6468

and TMS329C6457 DSPs Hardware Design Guide (SPRAAV7) for further details on proper power-supply

sequencing.

DV_DD18

V_REFSSTL(DDR2)

1

CV_DD11

DV_DD11

2

DV_DD33

3

POR

Figure 4-7. Power Supply Sequence

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Table 4-3. Timing Requirements for Power Supply Sequence

NO.

MIN

MAX UNIT

1

2

3

t_su(DVDD18-

DVDD11)

Setup Time, DV_DD18and V_REFSSTLsupplies stable before DV_DD11and CV_DD11supplies

stable

0.5

200 ms

t_su(DVDD11-

DVDD33)

Setup Time, DV_DD11and CV_DD11supplies stable before DV_DD33supply stable

0.5

200 ms

µs

t_{h(DVDD33-POR)}

Hold time, POR low after DV_DD33supplies stable

100

4.6.2.1 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as

possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum

distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a

yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling

capacitors, therefore physically smaller capacitors should be used while maintaining the largest available

capacitance value. As with the selection of any component, verification of capacitor availability over the

product's production lifetime should be considered.

4.6.2.2 Power-Down Operation

One of the power goals for the C6457 is to reduce power dissipation due to unused peripherals. There are

different ways to power down peripherals on the device.

After device reset, all peripherals on the C6457 device are in a disabled state and must be enabled by

software before being used. It is possible to enable only the peripherals needed by the application while

keeping the rest disabled. Note that peripherals in a disabled state are held in reset with their clocks

gated. For more information on how to enable peripherals, see Section 5.5.2

Peripherals used for booting, like I²C and HPI, are automatically enabled after device reset. It is possible

to disable peripherals used for booting after the boot process is complete. This, too, results in gating of the

clock(s) to the powered-down peripheral. Once a peripheral is powered-down, it must remain powered

down until the next device reset.

The C64x+ Megamodule also allows for software-driven power-down management for all of the C64x+

megamodule components through its Power-Down Controller (PDC). The CPU can power-down part or

the entire C64x+ megamodule through the power-down controller based on its own execution thread or in

response to an external stimulus from a host or global controller. More information on the power-down

features of the C64x+ Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide

(SPRU871).

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4.7 Power Supply to Peripheral I/O Mapping

over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)

POWER SUPPLY

I/O BUFFER TYPE

ASSOCIATED PERIPHERAL

CORECLK(P|N) PLL input buffers

CV_DD

Supply core voltage

LJCB

DDRREFCLK(N|P) PLL input buffers

RIOSGMIICLK(N|P) SERDES PLL input buffers

ALTCORECLK PLL input buffer

ALTDDRCLK PLL input buffer

POR/RESET input buffers

All GPIO peripheral I/O buffer

LVCMOS (1.8 V)

All McBSP0/McBSP1 peripheral I/O buffer

All MDIO peripheral I/O buffer

DV_DD18

1.8-V supply I/O voltage

All Timer0/Timer1 peripheral I/O buffer

NMI input buffers

DDR2 (1.8V)

All DDR2 memory controller peripheral I/O buffer

All I²C peripheral I/O buffer

Open-drain (1.8 V)

All EMIFA peripheral I/O buffer

ALL HPI peripheral I/O buffer

DV_DD33

3.3-V supply I/O voltage

LVCMOS (3.3 V)

CML

ALL UTOPIA peripheral I/O buffer

SRIO/SGMII SerDes CML I/O buffer

V_DDA11

SRIO/SGMII SerDes analog supply

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4.7.1 Reset Timing

Table 4-4. Reset Timing Requirements⁽¹⁾⁽²⁾

(see Figure 4-8 and Figure 4-9)

NO.

MIN

MAX UNIT

1

t_{h(SUPPLY-POR)}Hold Time, POR low after supplies stable and input clocks valid

1000

ns

t_su(RESETH-

PORH)

Setup Time, RESET high to POR high

2

1000

ns

4

7

8

t_w(RESET)

Pulse Duration, RESET low

24C

12C

ns

t_s(BOOT)

t_h(BOOT)

Setup time, boot mode and configuration pins valid before POR or RESET high

Hold time, bootmode and configuration pins valid after POR or RESET high

(1) If CORECLKSEL = 0, C = 1 ÷ CORECLK(N|P) frequency in ns.

(2) If CORECLKSEL = 1, C = 1 ÷ ALTCORECLK frequency in ns.

Table 4-5. Reset Switching Characteristics Over Recommended Operating Conditions

(see Figure 4-8 and Figure 4-9)

NO.

3

PARAMETER

MIN

MAX UNIT

t_{d(PORH-RSTATH)}

Delay Time, POR high to RESETSTAT high

Delay Time, RESET high to RESETSTAT high

200

5

µs

5

t_{d(RESETH-RSTATH)}

Table 4-6. Warm Reset Switching Characteristics Over Recommended Operating Conditions

(see Figure 4-9 and Figure 4-10)

NO.

PARAMETER

MIN

MAX UNIT

9

t_{su(PORH-RESETL)}

Setup time, POR high to RESET low

1.34

ns

1

2

POR

RESET

3

RESETSTAT

7

Boot and Device

Configuration Pins

8

Figure 4-8. Power-On Reset Timing

Specifications

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POR

RESET

4

5

RESETSTAT

Figure 4-9. Warm Reset Timing — RESETSTAT Relative to RESET

POR

RESET

9

Figure 4-10. Warm Reset Timing — Setup Time Between POR De-Asserted and RESET Asserted

4.7.2 Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V_IHand V_IL(or between V_ILand V_IH) in a monotonic

manner.

4.8 Peripherals

This section describes the various peripherals on the C6457 DSP. Peripheral specific information, timing

diagrams, electrical specifications and register memory maps are described in this chapter.

4.8.1 Enhanced Direct Memory Access (EDMA3) Controller

The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-

mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data

movement between external memory and internal memory), performs sorting or subframe extraction of

various data structures, services event-driven peripherals such as a McBSP or the UTOPIA port, and

offloads data transfers from the device CPU.

The EDMA3 includes the following features:

•

Fully orthogonal transfer description

–

3 transfer dimensions:

•

Array (multiple bytes)

Frame (multiple arrays)

Block (multiple frames)

–

Single event can trigger transfer of array, frame, or entire block

Independent indexes on source and destination

•

Flexible transfer definition:

–

Increment or FIFO transfer addressing modes

Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous

transfers, all with no CPU intervention

–

Chaining allows multiple transfers to execute with one event

256 PaRAM entries

–

Used to define transfer context for channels

Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry

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•

64 DMA channels

–

Manually triggered (CPU writes to channel controller register), external event triggered, and chain

triggered (completion of one transfer triggers another)

8 Quick DMA (QDMA) channels

–

Used for software-driven transfers

Triggered upon writing to a single PaRAM set entry

•

6 transfer controllers and 6 event queues with programmable system-level priority

Interrupt generation for transfer completion and error conditions

Debug visibility

–

Queue watermarking/threshold allows detection of maximum usage of event queues

Error and status recording to facilitate debug

Each of the transfer controllers has a direct connection to the switched central resource (SCR). Table 5-20

lists the peripherals that can be accessed by the transfer controllers.

4.8.1.1 EDMA3 Device-Specific Information

The EDMA supports two addressing modes: constant addressing and increment addressing mode.

Constant addressing mode is applicable to a very limited set of use cases; for most applications increment

mode can be used. On the C6457 DSP, the EDMA can use constant addressing mode only with the

Enhanced Viterbi-Decoder Coprocessor (VCP2) and the Enhanced Turbo Decoder Coprocessor (TCP2).

Constant addressing mode is not supported by any other peripheral or internal memory in the C6457 DSP.

Note that increment mode is supported by all C6457 peripherals, including VCP2 and TCP2. For more

information on these two addressing modes, see the TMS320C6457 DSP Enhanced DMA (EDMA3)

Controller User's Guide (SPRUGK6).

A DSP interrupt must be generated at the end of an HPI boot operation to begin execution of the loaded

application. Because the DSP interrupt generated by the HPI is mapped to the EDMA event DSP_EVT

(DMA channel 0), it will get recorded in bit 0 of the EDMA Event Register (ER). This event must be

cleared by software before triggering transfers on DMA channel 0. The EDMA3 on the C6457 DSP

supports active memory protection, but it does not support proxied memory protection.

4.8.1.2 EDMA3 Channel Synchronization Events

The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move

data between system memories. DMA channels can be triggered by synchronization events generated by

system peripherals. Table 4-7 lists the source of the synchronization event associated with each of the

DMA channels. On the C6457, the association of each synchronization event and DMA channel is fixed

and cannot be reprogrammed.

For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured,

processed, prioritized, linked, chained, and cleared, etc., see theTMS320C6457 DSP Enhanced DMA

(EDMA3) Controller User's Guide (SPRUGK6).

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Table 4-7. C6457 EDMA3 Channel Synchronization Events⁽¹⁾

EDMA CHANNEL

EVENT NAME

DSP_EVT

TEVTLO0

TEVTHI0

-

EVENT DESCRIPTION

0⁽²⁾

HPI-to-DSP event

1

Timer 0 Lower Counter Event

Timer 0 High Counter Event

None

2

3 - 8

9

ETBHFULLINT

ETBFULLINT

ETBACQINT

XEVT0

Embedded Trace Buffer (ETB) is half full

Embedded Trace Buffer (ETB) is full

Embedded Trace Buffer (ETB) acquisition is complete

McBSP0 Transmit Event

McBSP0 Receive Event

McBSP1 Transmit Event

McBSP1 Receive Event

Timer 1 Lower Counter Event

Timer 1 High Counter Event

None

10

11

12

13

REVT0

14

XEVT1

15

REVT1

16

TEVTLO1

TEVTHI1

-

17

18

19

INTDST0

INTDST1

INTDST2

INTDST3

INTDST4

INTDST5

INTDST6

-

RapidIO Interrupt 0

RapidIO Interrupt 1

RapidIO Interrupt 2

RapidIO Interrupt 3

RapidIO Interrupt 4

RapidIO Interrupt 5

RapidIO Interrupt 6

None

20

21

22

23

24

25

26 - 27

28

VCP2REVT

VCP2XEVT

TCP2AREVT

TCP2AXEVT

UREVT

VCP2 Receive Event

VCP2 Transmit Event

TCP2_A Receive Event

TCP2_A Transmit Event

UTOPIA Receive Event

TCP2_B Receive Event

TCP2_B Transmit Event

None

29

30

31

32

33

TCP2BREVT

TCP2BXEVT

-

34

35 - 39

40

UXEVT

UTOPIA Transmit Event

None

I²C Receive Event

I²C Transmit Event

None

41 - 43

44

-

ICREVT

ICXEVT

-

45

46 - 47

48

GPINT0

GPINT1

GPINT2

GPINT3

GPINT4

GPINT5

GPINT6

GPINT7

GPINT8

GPIO event 0

49

GPIO event 1

50

GPIO event 2

51

GPIO event 3

52

GPIO event 4

53

GPIO event 5

54

GPIO event 6

55

GPIO event 7

56

GPIO event 8

(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate

transfer completion events. For more detailed information on EDMA event-transfer chaining, see theTMS320C6457 DSP Enhanced

DMA (EDMA3) Controller User's Guide (SPRUGK6).

(2) HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This

event must be cleared by software before triggering transfers on DMA channel 0.

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Table 4-7. C6457 EDMA3 Channel Synchronization Events⁽¹⁾(continued)

EDMA CHANNEL

EVENT NAME

GPINT9

EVENT DESCRIPTION

57

58

59

60

61

62

63

GPIO event 9

GPIO event 10

GPIO event 11

GPIO event 12

GPIO event 13

GPIO event 14

GPIO event 15

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

GPINT15

4.8.1.3 EDMA3 Peripheral Register Description(s)

Table 4-8. EDMA3 Registers

HEX ADDRESS

02A0 0000

02A0 0004

02A0 0008 - 02A0 00FC

02A0 0100

02A0 0104

02A0 0108

02A0 010C

02A0 0110

02A0 0114

02A0 0118

02A0 011C

02A0 0120

02A0 0124

02A0 0128

02A0 012C

02A0 0130

02A0 0134

02A0 0138

02A0 013C

02A0 0140

02A0 0144

02A0 0148

02A0 014C

02A0 0150

02A0 0154

02A0 0158

02A0 015C

02A0 0160

02A0 0164

02A0 0168

02A0 016C

02A0 0170

02A0 0174

02A0 0178

02A0 017C

ACRONYM

PID

REGISTER NAME

Peripheral ID Register

CCCFG

EDMA3CC Configuration Register

Reserved

-

DCHMAP0

DCHMAP1

DCHMAP2

DCHMAP3

DCHMAP4

DCHMAP5

DCHMAP6

DCHMAP7

DCHMAP8

DCHMAP9

DCHMAP10

DCHMAP11

DCHMAP12

DCHMAP13

DCHMAP14

DCHMAP15

DCHMAP16

DCHMAP17

DCHMAP18

DCHMAP19

DCHMAP20

DCHMAP21

DCHMAP22

DCHMAP23

DCHMAP24

DCHMAP25

DCHMAP26

DCHMAP27

DCHMAP28

DCHMAP29

DCHMAP30

DCHMAP31

DMA Channel 0 Mapping Register

DMA Channel 1 Mapping Register

DMA Channel 2 Mapping Register

DMA Channel 3 Mapping Register

DMA Channel 4 Mapping Register

DMA Channel 5 Mapping Register

DMA Channel 6 Mapping Register

DMA Channel 7 Mapping Register

DMA Channel 8 Mapping Register

DMA Channel 9 Mapping Register

DMA Channel 10 Mapping Register

DMA Channel 11 Mapping Register

DMA Channel 12 Mapping Register

DMA Channel 13 Mapping Register

DMA Channel 14 Mapping Register

DMA Channel 15 Mapping Register

DMA Channel 16 Mapping Register

DMA Channel 17 Mapping Register

DMA Channel 18 Mapping Register

DMA Channel 19 Mapping Register

DMA Channel 20 Mapping Register

DMA Channel 21 Mapping Register

DMA Channel 22 Mapping Register

DMA Channel 23 Mapping Register

DMA Channel 24 Mapping Register

DMA Channel 25 Mapping Register

DMA Channel 26 Mapping Register

DMA Channel 27 Mapping Register

DMA Channel 28 Mapping Register

DMA Channel 29 Mapping Register

DMA Channel 30 Mapping Register

DMA Channel 31 Mapping Register

Specifications

49

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

02A0 0180

02A0 0184

02A0 0188

02A0 018C

02A0 0190

02A0 0194

02A0 0198

02A0 019C

02A0 01A0

02A0 01A4

02A0 01A8

02A0 01AC

02A0 01B0

02A0 01B4

02A0 01B8

02A0 01BC

02A0 01C0

02A0 01C4

02A0 01C8

02A0 01CC

02A0 01D0

02A0 01D4

02A0 01D8

02A0 01DC

02A0 01E0

02A0 01E4

02A0 01E8

02A0 01EC

02A0 01F0

02A0 01F4

02A0 01F8

02A0 01FC

02A0 0200

02A0 0204

02A0 0208

02A0 020C

02A0 0210

02A0 0214

02A0 0218

02A0 021C

02A0 0220 - 02A0 023C

02A0 0240

02A0 0244

02A0 0248

02A0 024C

02A0 0250

02A0 0254

ACRONYM

REGISTER NAME

DCHMAP32

DCHMAP33

DCHMAP34

DCHMAP35

DCHMAP36

DCHMAP37

DCHMAP38

DCHMAP39

DCHMAP40

DCHMAP41

DCHMAP42

DCHMAP43

DCHMAP44

DCHMAP45

DCHMAP46

DCHMAP47

DCHMAP48

DCHMAP49

DCHMAP50

DCHMAP51

DCHMAP52

DCHMAP53

DCHMAP54

DCHMAP55

DCHMAP56

DCHMAP57

DCHMAP58

DCHMAP59

DCHMAP60

DCHMAP61

DCHMAP62

DCHMAP63

QCHMAP0

QCHMAP1

QCHMAP2

QCHMAP3

QCHMAP4

QCHMAP5

QCHMAP6

QCHMAP7

-

DMA Channel 32 Mapping Register

DMA Channel 33 Mapping Register

DMA Channel 34 Mapping Register

DMA Channel 35 Mapping Register

DMA Channel 36 Mapping Register

DMA Channel 37 Mapping Register

DMA Channel 38 Mapping Register

DMA Channel 39 Mapping Register

DMA Channel 40 Mapping Register

DMA Channel 41 Mapping Register

DMA Channel 42 Mapping Register

DMA Channel 43 Mapping Register

DMA Channel 44 Mapping Register

DMA Channel 45 Mapping Register

DMA Channel 46 Mapping Register

DMA Channel 47 Mapping Register

DMA Channel 48 Mapping Register

DMA Channel 49 Mapping Register

DMA Channel 50 Mapping Register

DMA Channel 51 Mapping Register

DMA Channel 52 Mapping Register

DMA Channel 53 Mapping Register

DMA Channel 54 Mapping Register

DMA Channel 55 Mapping Register

DMA Channel 56 Mapping Register

DMA Channel 57 Mapping Register

DMA Channel 58 Mapping Register

DMA Channel 59 Mapping Register

DMA Channel 60 Mapping Register

DMA Channel 61 Mapping Register

DMA Channel 62 Mapping Register

DMA Channel 63 Mapping Register

QDMA Channel 0 Mapping Register

QDMA Channel 1 Mapping Register

QDMA Channel 2 Mapping Register

QDMA Channel 3 Mapping Register

QDMA Channel 4 Mapping Register

QDMA Channel 5 Mapping Register

QDMA Channel 6 Mapping Register

QDMA Channel 7 Mapping Register

Reserved

DMAQNUM0

DMAQNUM1

DMAQNUM2

DMAQNUM3

DMAQNUM4

DMAQNUM5

DMA Queue Number Register 0

DMA Queue Number Register 1

DMA Queue Number Register 2

DMA Queue Number Register 3

DMA Queue Number Register 4

DMA Queue Number Register 5

50

Specifications

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

02A0 0258

02A0 025C

02A0 0260

02A0 0264 - 02A0 027C

02A0 0280

02A0 0284

02A0 0288 - 02A0 02FC

02A0 0300

02A0 0304

02A0 0308

02A0 030C

02A0 0310

02A0 0314

02A0 0318

02A0 031C

02A0 0320

02A0 0324 - 02A0 033C

02A0 0340

02A0 0344

02A0 0348

02A0 034C

02A0 0350

02A0 0354

02A0 0358

02A0 035C

02A0 0360

02A0 0364

02A0 0368

02A0 036C

02A0 0370

02A0 0374

02A0 0378

02A0 037C

02A0 0380

02A0 0384

02A0 0388

02A0 038C

02A0 0390

02A0 0394

02A0 0398

02A0 039C

02A0 0400

02A0 0404

02A0 0408

02A0 040C

02A0 0410

02A0 0414

DMAQNUM6

DMAQNUM7

QDMAQNUM

-

DMA Queue Number Register 6

DMA Queue Number Register 7

QDMA Queue Number Register

Reserved

QUETCMAP

QUEPRI

-

Queue to TC Mapping Register

Queue Priority Register

Reserved

EMR

Event Missed Register

EMRH

Event Missed Register High

Event Missed Clear Register

Event Missed Clear Register High

QDMA Event Missed Register

QDMA Event Missed Clear Register

EDMA3CC Error Register

EDMA3CC Error Clear Register

Error Evaluate Register

EMCR

EMCRH

QEMR

QEMCR

CCERR

CCERRCLR

EEVAL

-

Reserved

DRAE0

DRAEH0

DRAE1

DRAEH1

DRAE2

DRAEH2

DRAE3

DRAEH3

DRAE4

DRAEH4

DRAE5

DRAEH5

DRAE6

DRAEH6

DRAE7

DRAEH7

QRAE0

QRAE1

QRAE2

QRAE3

QRAE4

QRAE5

QRAE6

QRAE7

Q0E0

DMA Region Access Enable Register for Region 0

DMA Region Access Enable Register High for Region 0

DMA Region Access Enable Register for Region 1

DMA Region Access Enable Register High for Region 1

DMA Region Access Enable Register for Region 2

DMA Region Access Enable Register High for Region 2

DMA Region Access Enable Register for Region 3

DMA Region Access Enable Register High for Region 3

DMA Region Access Enable Register for Region 4

DMA Region Access Enable Register High for Region 4

DMA Region Access Enable Register for Region 5

DMA Region Access Enable Register High for Region 5

DMA Region Access Enable Register for Region 6

DMA Region Access Enable Register High for Region 6

DMA Region Access Enable Register for Region 7

DMA Region Access Enable Register High for Region 7

QDMA Region Access Enable Register for Region 0

QDMA Region Access Enable Register for Region 1

QDMA Region Access Enable Register for Region 2

QDMA Region Access Enable Register for Region 3

QDMA Region Access Enable Register for Region 4

QDMA Region Access Enable Register for Region 5

QDMA Region Access Enable Register for Region 6

QDMA Region Access Enable Register for Region 7

Event Queue 0 Entry Register 0

Q0E1

Event Queue 0 Entry Register 1

Q0E2

Event Queue 0 Entry Register 2

Q0E3

Event Queue 0 Entry Register 3

Q0E4

Event Queue 0 Entry Register 4

Q0E5

Event Queue 0 Entry Register 5

Specifications

51

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

02A0 0418

02A0 041C

02A0 0420

02A0 0424

02A0 0428

02A0 042C

02A0 0430

02A0 0434

02A0 0438

02A0 043C

02A0 0440

02A0 0444

02A0 0448

02A0 044C

02A0 0450

02A0 0454

02A0 0458

02A0 045C

02A0 0460

02A0 0464

02A0 0468

02A0 046C

02A0 0470

02A0 0474

02A0 0478

02A0 047C

02A0 0480

02A0 0484

02A0 0488

02A0 048C

02A0 0490

02A0 0494

02A0 0498

02A0 049C

02A0 04A0

02A0 04A4

02A0 04A8

02A0 04AC

02A0 04B0

02A0 04B4

02A0 04B8

02A0 04BC

02A0 04C0

02A0 04C4

02A0 04C8

02A0 04CC

02A0 04D0

ACRONYM

REGISTER NAME

Q0E6

Q0E7

Q0E8

Q0E9

Q0E10

Q0E11

Q0E12

Q0E13

Q0E14

Q0E15

Q1E0

Q1E1

Q1E2

Q1E3

Q1E4

Q1E5

Q1E6

Q1E7

Q1E8

Q1E9

Q1E10

Q1E11

Q1E12

Q1E13

Q1E14

Q1E15

Q2E0

Q2E1

Q2E2

Q2E3

Q2E4

Q2E5

Q2E6

Q2E7

Q2E8

Q2E9

Q2E10

Q2E11

Q2E12

Q2E13

Q2E14

Q2E15

Q3E0

Q3E1

Q3E2

Q3E3

Q3E4

Event Queue 0 Entry Register 6

Event Queue 0 Entry Register 7

Event Queue 0 Entry Register 8

Event Queue 0 Entry Register 9

Event Queue 0 Entry Register 10

Event Queue 0 Entry Register 11

Event Queue 0 Entry Register 12

Event Queue 0 Entry Register 13

Event Queue 0 Entry Register 14

Event Queue 0 Entry Register 15

Event Queue 1 Entry Register 0

Event Queue 1 Entry Register 1

Event Queue 1 Entry Register 2

Event Queue 1 Entry Register 3

Event Queue 1 Entry Register 4

Event Queue 1 Entry Register 5

Event Queue 1 Entry Register 6

Event Queue 1 Entry Register 7

Event Queue 1 Entry Register 8

Event Queue 1 Entry Register 9

Event Queue 1 Entry Register 10

Event Queue 1 Entry Register 11

Event Queue 1 Entry Register 12

Event Queue 1 Entry Register 13

Event Queue 1 Entry Register 14

Event Queue 1 Entry Register 15

Event Queue 2 Entry Register 0

Event Queue 2 Entry Register 1

Event Queue 2 Entry Register 2

Event Queue 2 Entry Register 3

Event Queue 2 Entry Register 4

Event Queue 2 Entry Register 5

Event Queue 2 Entry Register 6

Event Queue 2 Entry Register 7

Event Queue 2 Entry Register 8

Event Queue 2 Entry Register 9

Event Queue 2 Entry Register 10

Event Queue 2 Entry Register 11

Event Queue 2 Entry Register 12

Event Queue 2 Entry Register 13

Event Queue 2 Entry Register 14

Event Queue 2 Entry Register 15

Event Queue 3 Entry Register 0

Event Queue 3 Entry Register 1

Event Queue 3 Entry Register 2

Event Queue 3 Entry Register 3

Event Queue 3 Entry Register 4

52

Specifications

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

02A0 04D4

02A0 04D8

Q3E5

Q3E6

Event Queue 3 Entry Register 5

Event Queue 3 Entry Register 6

Event Queue 3 Entry Register 7

Event Queue 3 Entry Register 8

Event Queue 3 Entry Register 9

Event Queue 3 Entry Register 10

Event Queue 3 Entry Register 11

Event Queue 3 Entry Register 12

Event Queue 3 Entry Register 13

Event Queue 3 Entry Register 14

Event Queue 3 Entry Register 15

Event Queue 4 Entry Register 0

Event Queue 4 Entry Register 1

Event Queue 4 Entry Register 2

Event Queue 4 Entry Register 3

Event Queue 4 Entry Register 4

Event Queue 4 Entry Register 5

Event Queue 4 Entry Register 6

Event Queue 4 Entry Register 7

Event Queue 4 Entry Register 8

Event Queue 4 Entry Register 9

Event Queue 4 Entry Register 10

Event Queue 4 Entry Register 11

Event Queue 4 Entry Register 12

Event Queue 4 Entry Register 13

Event Queue 4 Entry Register 14

Event Queue 4 Entry Register 15

Reserved

02A0 04DC

02A0 04E0

Q3E7

Q3E8

02A0 04E4

Q3E9

02A0 04E8

Q3E10

Q3E11

Q3E12

Q3E13

Q3E14

Q3E15

Q4E0

02A0 04EC

02A0 04F0

02A0 04F4

02A0 04F8

02A0 04FC

02A0 0500

02A0 0504

Q4E1

02A0 0508

Q4E2

02A0 050C

Q4E3

02A0 0510

Q4E4

02A0 0514

Q4E5

02A0 0518

Q4E6

02A0 051C

Q4E7

02A0 0520

Q4E8

02A0 0524

Q4E9

02A0 0528

Q4E10

Q4E11

Q4E12

Q4E13

Q4E14

Q4E15

-

02A0 052C

02A0 0530

02A0 0534

02A0 0538

02A0 053C

02A0 0540 - 02A0 05FC

02A0 0600

QSTAT0

QSTAT1

QSTAT2

QSTAT3

QSTAT4

QSTAT5

-

Queue Status Register 0

02A0 0604

Queue Status Register 1

02A0 0608

Queue Status Register 2

02A0 060C

Queue Status Register 3

02A0 0610

Queue Status Register 4

02A0 0614

Queue Status Register 5

02A0 0618 - 02A0 061C

02A0 0620

Reserved

QWMTHRA

QWMTHRB

-

Queue Watermark Threshold A Register

Queue Watermark Threshold B Register

Reserved

02A0 0624

02A0 0628 - 02A0 063C

02A0 0640

CCSTAT

-

EDMA3CC Status Register

02A0 0644 - 02A0 06FC

02A0 0700 - 02A0 07FC

02A0 0800

Reserved

-

Reserved

MPFAR

MPFSR

MPFCR

MPPAG

MPPA0

MPPA1

Memory Protection Fault Address Register

Memory Protection Fault Status Register

Memory Protection Fault Command Register

Memory Protection Page Attribute Register G

Memory Protection Page Attribute Register 0

Memory Protection Page Attribute Register 1

02A0 0804

02A0 0808

02A0 080C

02A0 0810

02A0 0814

Specifications

53

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

02A0 0818

ACRONYM

REGISTER NAME

MPPA2

MPPA3

MPPA4

MPPA5

MPPA6

MPPA7

-

Memory Protection Page Attribute Register 2

Memory Protection Page Attribute Register 3

Memory Protection Page Attribute Register 4

Memory Protection Page Attribute Register 5

Memory Protection Page Attribute Register 6

Memory Protection Page Attribute Register 7

Reserved

02A0 081C

02A0 0820

02A0 0824

02A0 0828

02A0 082C

02A0 082C - 02A0 0FFC

02A0 1000

ER

Event Register

02A0 1004

ERH

Event Register High

02A0 1008

ECR

Event Clear Register

02A0 100C

02A0 1010

ECRH

ESR

Event Clear Register High

Event Set Register

02A0 1014

ESRH

CER

Event Set Register High

02A0 1018

Chained Event Register

02A0 101C

02A0 1020

CERH

EER

Chained Event Register High

Event Enable Register

02A0 1024

EERH

EECR

EECRH

EESR

EESRH

SER

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

02A0 1028

02A0 102C

02A0 1030

02A0 1034

02A0 1038

02A0 103C

02A0 1040

SERH

SECR

SECRH

-

Secondary Event Register High

Secondary Event Clear Register

Secondary Event Clear Register High

Reserved

02A0 1044

02A0 1048 - 02A0 104C

02A0 1050

IER

Interrupt Enable Register

02A0 1054

IERH

IECR

IECRH

IESR

IESRH

IPR

Interrupt Enable High Register

Interrupt Enable Clear Register

Interrupt Enable Clear High Register

Interrupt Enable Set Register

Interrupt Enable Set High Register

Interrupt Pending Register

Interrupt Pending High Register

Interrupt Clear Register

02A0 1058

02A0 105C

02A0 1060

02A0 1064

02A0 1068

02A0 106C

02A0 1070

IPRH

ICR

02A0 1074

ICRH

IEVAL

-

Interrupt Clear High Register

Interrupt Evaluate Register

Reserved

02A0 1078

02A0 107C

02A0 1080

QER

QDMA Event Register

02A0 1084

QEER

QEECR

QEESR

QSER

QSECR

-

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

02A0 1088

02A0 108C

02A0 1090

02A0 1094

02A0 1098 - 02A0 1FFF

54

Specifications

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

Shadow Region 0 Channel Registers

Event Register

02A0 2000

02A0 2004

02A0 2008

02A0 200C

02A0 2010

02A0 2014

02A0 2018

02A0 201C

02A0 2020

02A0 2024

02A0 2028

02A0 202C

02A0 2030

02A0 2034

02A0 2038

02A0 203C

02A0 2040

02A0 2044

02A0 2048 - 02A0 204C

02A0 2050

02A0 2054

02A0 2058

02A0 205C

02A0 2060

02A0 2064

02A0 2068

02A0 206C

02A0 2070

02A0 2074

02A0 2078

02A0 207C

02A0 2080

02A0 2084

02A0 2088

02A0 208C

02A0 2090

02A0 2094

02A0 2098 - 02A0 21FF

ER

ERH

Event Register High

ECR

Event Clear Register

ECRH

ESR

Event Clear Register High

Event Set Register

ESRH

CER

Event Set Register High

Chained Event Register

CERH

EER

Chained Event Register High

Event Enable Register

EERH

EECR

EECRH

EESR

EESRH

SER

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

Secondary Event Register High

Secondary Event Clear Register

Secondary Event Clear Register High

Reserved

SERH

SECR

SECRH

-

IER

Interrupt Enable Register

Interrupt Enable Register High

Interrupt Enable Clear Register

Interrupt Enable Clear Register High

Interrupt Enable Set Register

Interrupt Enable Set Register High

Interrupt Pending Register

Interrupt Pending Register High

Interrupt Clear Register

IERH

IECR

IECRH

IESR

IESRH

IPR

IPRH

ICR

ICRH

IEVAL

-

Interrupt Clear Register High

Interrupt Evaluate Register

Reserved

QER

QDMA Event Register

QEER

QEECR

QEESR

QSER

QSECR

-

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

Specifications

55

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

Shadow Region 1 Channel Registers

Event Register

02A0 2200

02A0 2204

02A0 2208

02A0 220C

02A0 2210

02A0 2214

02A0 2218

02A0 221C

02A0 2220

02A0 2224

02A0 2228

02A0 222C

02A0 2230

02A0 2234

02A0 2238

02A0 223C

02A0 2240

02A0 2244

02A0 2248 - 02A0 224C

02A0 2250

02A0 2254

02A0 2258

02A0 225C

02A0 2260

02A0 2264

02A0 2268

02A0 226C

02A0 2270

02A0 2274

02A0 2278

02A0 227C

02A0 2280

02A0 2284

02A0 2288

02A0 228C

02A0 2290

02A0 2294

02A0 2298 - 02A0 23FF

ER

ERH

Event Register High

ECR

Event Clear Register

ECRH

ESR

Event Clear Register High

Event Set Register

ESRH

CER

Event Set Register High

Chained Event Register

CERH

EER

Event Enable Register

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

Secondary Event Register High

Secondary Event Clear Register

Secondary Event Clear Register High

Reserved

EERH

EECR

EECRH

EESR

EESRH

SER

SERH

SECR

SECRH

-

Interrupt Enable Register

Interrupt Enable Register High

Interrupt Enable Clear Register

Interrupt Enable Clear Register High

Interrupt Enable Set Register

Interrupt Enable Set Register High

Interrupt Pending Register

Interrupt Pending Register High

Interrupt Clear Register

IER

IERH

IECR

IECRH

IESR

IESRH

IPR

IPRH

ICR

Interrupt Clear Register High

Interrupt Evaluate Register

Reserved

ICRH

IEVAL

-

QDMA Event Register

QER

QEER

QEECR

QEESR

QSER

QSECR

-

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

56

Specifications

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

Shadow Region 2 Channel Registers

Event Register

02A0 2400

02A0 2404

02A0 2408

02A0 240C

02A0 2410

02A0 2414

02A0 2418

02A0 241C

02A0 2420

02A0 2424

02A0 2428

02A0 242C

02A0 2430

02A0 2434

02A0 2438

02A0 243C

02A0 2440

02A0 2444

02A0 2448 - 02A0 244C

02A0 2450

02A0 2454

02A0 2458

02A0 245C

02A0 2460

02A0 2464

02A0 2468

02A0 246C

02A0 2470

02A0 2474

02A0 2478

02A0 247C

02A0 2480

02A0 2484

02A0 2488

02A0 248C

02A0 2490

02A0 2494

02A0 2498 - 02A0 25FF

ER

ERH

Event Register High

ECR

Event Clear Register

ECRH

ESR

Event Clear Register High

Event Set Register

ESRH

CER

Event Set Register High

Chained Event Register

CERH

EER

Chained Event Register High

Event Enable Register

EERH

EECR

EECRH

EESR

EESRH

SER

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

Secondary Event Register High

Secondary Event Clear Register

Secondary Event Clear Register High

Reserved

SERH

SECR

SECRH

-

IER

Interrupt Enable Register

Interrupt Enable Register High

Interrupt Enable Clear Register

Interrupt Enable Clear Register High

Interrupt Enable Set Register

Interrupt Enable Set Register High

Interrupt Pending Register

Interrupt Pending Register High

Interrupt Clear Register

IERH

IECR

IECRH

IESR

IESRH

IPR

IPRH

ICR

ICRH

IEVAL

-

Interrupt Clear Register High

Interrupt Evaluate Register

Reserved

QER

QDMA Event Register

QEER

QEECR

QEESR

QSER

QSECR

-

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

Specifications

57

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

Shadow Region 3 Channel Registers

Event Register

02A0 2600

02A0 2604

02A0 2608

02A0 260C

02A0 2610

02A0 2614

02A0 2618

02A0 261C

02A0 2620

02A0 2624

02A0 2628

02A0 262C

02A0 2630

02A0 2634

02A0 2638

02A0 263C

02A0 2640

02A0 2644

02A0 2648 - 02A0 264C

02A0 2650

02A0 2654

02A0 2658

02A0 265C

02A0 2660

02A0 2664

02A0 2668

02A0 266C

02A0 2670

02A0 2674

02A0 2678

02A0 267C

02A0 2680

02A0 2684

02A0 2688

02A0 268C

02A0 2690

02A0 2694

02A0 2698 - 02A0 27FF

ER

ERH

Event Register High

ECR

Event Clear Register

ECRH

ESR

Event Clear Register High

Event Set Register

ESRH

CER

Event Set Register High

Chained Event Register

CERH

EER

Chained Event Register High

Event Enable Register

EERH

EECR

EECRH

EESR

EESRH

SER

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

Secondary Event Register High

Secondary Event Clear Register

Secondary Event Clear Register High

Reserved

SERH

SECR

SECRH

-

IER

Interrupt Enable Register

Interrupt Enable Register High

Interrupt Enable Clear Register

Interrupt Enable Clear Register High

Interrupt Enable Set Register

Interrupt Enable Set Register High

Interrupt Pending Register

Interrupt Pending Register High

Interrupt Clear Register

IERH

IECR

IECRH

IESR

IESRH

IPR

IPRH

ICR

ICRH

IEVAL

-

Interrupt Clear Register High

Interrupt Evaluate Register

Reserved

QER

QDMA Event Register

QEER

QEECR

QEESR

QSER

QSECR

-

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

58

Specifications

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

Shadow Region 4 Channel Registers

Event Register

02A0 2800

02A0 2804

02A0 2808

02A0 280C

02A0 2810

02A0 2814

02A0 2818

02A0 281C

02A0 2820

02A0 2824

02A0 2828

02A0 282C

02A0 2830

02A0 2834

02A0 2838

02A0 283C

02A0 2840

02A0 2844

02A0 2848 - 02A0 284C

02A0 2850

02A0 2854

02A0 2858

02A0 285C

02A0 2860

02A0 2864

02A0 2868

02A0 286C

02A0 2870

02A0 2874

02A0 2878

02A0 287C

02A0 2880

02A0 2884

02A0 2888

02A0 288C

02A0 2890

02A0 2894

02A0 2898 - 02A0 29FF

ER

ERH

Event Register High

ECR

Event Clear Register

ECRH

ESR

Event Clear Register High

Event Set Register

ESRH

CER

Event Set Register High

Chained Event Register

CERH

EER

Chained Event Register High

Event Enable Register

EERH

EECR

EECRH

EESR

EESRH

SER

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

Secondary Event Register High

Secondary Event Clear Register

Secondary Event Clear Register High

Reserved

SERH

SECR

SECRH

-

IER

Interrupt Enable Register

Interrupt Enable Register High

Interrupt Enable Clear Register

Interrupt Enable Clear Register High

Interrupt Enable Set Register

Interrupt Enable Set Register High

Interrupt Pending Register

Interrupt Pending Register High

Interrupt Clear Register

IERH

IECR

IECRH

IESR

IESRH

IPR

IPRH

ICR

ICRH

IEVAL

-

Interrupt Clear Register High

Interrupt Evaluate Register

Reserved

QER

QDMA Event Register

QEER

QEECR

QEESR

QSER

QSECR

-

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

Specifications

59

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

Shadow Region 5 Channel Registers

Event Register

02A0 2A00

02A0 2A04

02A0 2A08

02A0 2A0C

02A0 2A10

02A0 2A14

02A0 2A18

02A0 2A1C

02A0 2A20

02A0 2A24

02A0 2A28

02A0 2A2C

02A0 2A30

02A0 2A34

02A0 2A38

02A0 2A3C

02A0 2A40

02A0 2A44

02A0 2A48 - 02A0 2A4C

02A0 2A50

02A0 2A54

02A0 2A58

02A0 2A5C

02A0 2A60

02A0 2A64

02A0 2A68

02A0 2A6C

02A0 2A70

02A0 2A74

02A0 2A78

02A0 2A7C

02A0 2A80

02A0 2A84

02A0 2A88

02A0 2A8C

02A0 2A90

02A0 2A94

02A0 2A98 - 02A0 2BFF

ER

ERH

Event Register High

ECR

Event Clear Register

ECRH

ESR

Event Clear Register High

Event Set Register

ESRH

CER

Event Set Register High

Chained Event Register

CERH

EER

Chained Event Register High

Event Enable Register

EERH

EECR

EECRH

EESR

EESRH

SER

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

Secondary Event Register High

Secondary Event Clear Register

Secondary Event Clear Register High

Reserved

SERH

SECR

SECRH

-

IER

Interrupt Enable Register

Interrupt Enable Register High

Interrupt Enable Clear Register

Interrupt Enable Clear Register High

Interrupt Enable Set Register

Interrupt Enable Set Register High

Interrupt Pending Register

Interrupt Pending Register High

Interrupt Clear Register

IERH

IECR

IECRH

IESR

IESRH

IPR

IPRH

ICR

ICRH

IEVAL

-

Interrupt Clear Register High

Interrupt Evaluate Register

Reserved

QER

QDMA Event Register

QEER

QEECR

QEESR

QSER

QSECR

-

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

60

Specifications

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

Shadow Region 6 Channel Registers

Event Register

02A0 2C00

02A0 2C04

02A0 2C08

02A0 2C0C

02A0 2C10

02A0 2C14

02A0 2C18

02A0 2C1C

02A0 2C20

02A0 2C24

02A0 2C28

02A0 2C2C

02A0 2C30

02A0 2C34

02A0 2C38

02A0 2C3C

02A0 2C40

02A0 2C44

02A0 2C48 - 02A0 2C4C

02A0 2C50

02A0 2C54

02A0 2C58

02A0 2C5C

02A0 2C60

02A0 2C64

02A0 2C68

02A0 2C6C

02A0 2C70

02A0 2C74

02A0 2C78

02A0 2C7C

02A0 2C80

02A0 2C84

02A0 2C88

02A0 2C8C

02A0 2C90

02A0 2C94

02A0 2C98 - 02A0 2DFF

ER

ERH

Event Register High

ECR

Event Clear Register

ECRH

ESR

Event Clear Register High

Event Set Register

ESRH

CER

Event Set Register High

Chained Event Register

CERH

EER

Chained Event Register High

Event Enable Register

EERH

EECR

EECRH

EESR

EESRH

SER

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

Secondary Event Register High

Secondary Event Clear Register

Secondary Event Clear Register High

Reserved

SERH

SECR

SECRH

-

IER

Interrupt Enable Register

Interrupt Enable Register High

Interrupt Enable Clear Register

Interrupt Enable Clear Register High

Interrupt Enable Set Register

Interrupt Enable Set Register High

Interrupt Pending Register

Interrupt Pending Register High

Interrupt Clear Register

IERH

IECR

IECRH

IESR

IESRH

IPR

IPRH

ICR

ICRH

IEVAL

-

Interrupt Clear Register High

Interrupt Evaluate Register

Reserved

QER

QDMA Event Register

QEER

QEECR

QEESR

QSER

QSECR

-

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

Specifications

61

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Table 4-8. EDMA3 Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

Shadow Region 7 Channel Registers

Event Register

02A0 2E00

02A0 2E04

02A0 2E08

02A0 2E0C

02A0 2E10

02A0 2E14

02A0 2E18

02A0 2E1C

02A0 2E20

02A0 2E24

02A0 2E28

02A0 2E2C

02A0 2E30

02A0 2E34

02A0 2E38

02A0 2E3C

02A0 2E40

02A0 2E44

02A0 2E48 - 02A0 2E4C

02A0 2E50

02A0 2E54

02A0 2E58

02A0 2E5C

02A0 2E60

02A0 2E64

02A0 2E68

02A0 2E6C

02A0 2E70

02A0 2E74

02A0 2E78

02A0 2E7C

02A0 2E80

02A0 2E84

02A0 2E88

02A0 2E8C

02A0 2E90

02A0 2E94

02A0 2E98 - 02A0 2FFF

ER

ERH

Event Register High

ECR

Event Clear Register

ECRH

ESR

Event Clear Register High

Event Set Register

ESRH

CER

Event Set Register High

Chained Event Register

CERH

EER

Chained Event Register High

Event Enable Register

EERH

EECR

EECRH

EESR

EESRH

SER

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

Secondary Event Register High

Secondary Event Clear Register

Secondary Event Clear Register High

Reserved

SERH

SECR

SECRH

-

IER

Interrupt Enable Register

Interrupt Enable Register High

Interrupt Enable Clear Register

Interrupt Enable Clear Register High

Interrupt Enable Set Register

Interrupt Enable Set Register High

Interrupt Pending Register

Interrupt Pending Register High

Interrupt Clear Register

IERH

IECR

IECRH

IESR

IESRH

IPR

IPRH

ICR

ICRH

IEVAL

-

Interrupt Clear Register High

Interrupt Evaluate Register

Reserved

QER

QDMA Event Register

QEER

QEECR

QEESR

QSER

QSECR

-

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

62

Specifications

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Table 4-9. EDMA3 Parameter RAM

HEX ADDRESS RANGE

02A0 4000 - 02A0 401F

02A0 4020 - 02A0 403F

02A0 4040 - 02A0 405F

02A0 4060 - 02A0 407F

02A0 4080 - 02A0 409F

02A0 40A0 - 02A0 40BF

02A0 40C0 - 02A0 40DF

02A0 40E0 - 02A0 40FF

02A0 4100 - 02A0 411F

02A0 4120 - 02A0 413F

...

ACRONYM

REGISTER NAME

Parameter Set 0

Parameter Set 1

Parameter Set 2

Parameter Set 3

Parameter Set 4

Parameter Set 5

Parameter Set 6

Parameter Set 7

Parameter Set 8

Parameter Set 9

...

-

02A0 47E0 - 02A0 47FF

02A0 4800 - 02A0 481F

02A0 4820 - 02A0 483F

...

-

Parameter Set 63

Parameter Set 64

Parameter Set 65

...

02A0 5FC0 - 02A0 5FDF

02A0 5FE0 - 02A0 5FFF

-

Parameter Set 254

Parameter Set 255

Table 4-10. EDMA3 Transfer Controller 0 Registers

HEX ADDRESS RANGE

02A2 0000

ACRONYM

PID

REGISTER NAME

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved

02A2 0004

TCCFG

-

02A2 0008 - 02A2 00FC

02A2 0100

TCSTAT

-

EDMA3TC Channel Status Register

Reserved

02A2 0104 - 02A2 011C

02A2 0120

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

Error Register

02A2 0124

Error Enable Register

02A2 0128

Error Clear Register

02A2 012C

Error Details Register

02A2 0130

Error Interrupt Command Register

Reserved

02A2 0134 - 02A2 013C

02A2 0140

RDRATE

-

Read Rate Register

02A2 0144 - 02A2 023C

02A2 0240

Reserved

SAOPT

SASRC

SACNT

SADST

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

-

Source Active Options Register

Source Active Source Address Register

Source Active Count Register

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

02A2 0244

02A2 0248

02A2 024C

02A2 0250

02A2 0254

02A2 0258

02A2 025C

02A2 0260

Source Active Destination Address B-Reference Register

Reserved

02A2 0264 - 02A2 027C

02A2 0280

DFCNTRLD

DFSRCBREF

DFDSTBREF

-

Destination FIFO Set Count Reload

02A2 0284

Destination FIFO Set Destination Address B Reference Register

Reserved

02A2 0288

02A2 028C - 02A2 02FC

Specifications

63

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Table 4-10. EDMA3 Transfer Controller 0 Registers (continued)

HEX ADDRESS RANGE

02A2 0300

ACRONYM

DFOPT0

DFSRC0

DFCNT0

DFDST0

DFBIDX0

DFMPPRXY0

-

REGISTER NAME

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

Destination FIFO Count Register 0

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

Destination FIFO Memory Protection Proxy Register 0

Reserved

02A2 0304

02A2 0308

02A2 030C

02A2 0310

02A2 0314

02A2 0318 - 02A2 033C

02A2 0340

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1

DFMPPRXY1

-

Destination FIFO Options Register 1

Destination FIFO Source Address Register 1

Destination FIFO Count Register 1

Destination FIFO Destination Address Register 1

Destination FIFO BIDX Register 1

Destination FIFO Memory Protection Proxy Register 1

Reserved

02A2 0344

02A2 0348

02A2 034C

02A2 0350

02A2 0354

02A2 0358 - 02A2 037C

02A2 0380

DFOPT2

DFSRC2

DFCNT2

DFDST2

DFBIDX2

DFMPPRXY2

-

Destination FIFO Options Register 2

Destination FIFO Source Address Register 2

Destination FIFO Count Register 2

Destination FIFO Destination Address Register 2

Destination FIFO BIDX Register 2

Destination FIFO Memory Protection Proxy Register 2

Reserved

02A2 0384

02A2 0388

02A2 038C

02A2 0390

02A2 0394

02A2 0398 - 02A2 03BC

02A2 03C0

DFOPT3

DFSRC3

DFCNT3

DFDST3

DFBIDX3

DFMPPRXY3

-

Destination FIFO Options Register 3

Destination FIFO Source Address Register 3

Destination FIFO Count Register 3

Destination FIFO Destination Address Register 3

Destination FIFO BIDX Register 3

Destination FIFO Memory Protection Proxy Register 3

Reserved

02A2 03C4

02A2 03C8

02A2 03CC

02A2 03D0

02A2 03D4

02A2 03D8 - 02A2 7FFC

Table 4-11. EDMA3 Transfer Controller 1 Registers

HEX ADDRESS RANGE

02A2 8000

ACRONYM

PID

REGISTER NAME

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved

02A2 8004

TCCFG

-

02A2 8008 - 02A2 80FC

02A2 8100

TCSTAT

-

EDMA3TC Channel Status Register

Reserved

02A2 8104 - 02A2 811C

02A2 8120

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

Error Register

02A2 8124

Error Enable Register

Error Clear Register

02A2 8128

02A2 812C

Error Details Register

Error Interrupt Command Register

Reserved

02A2 8130

02A2 8134 - 02A2 813C

02A2 8140

RDRATE

-

Read Rate Register

02A2 8144 - 02A2 823C

02A2 8240

Reserved

SAOPT

SASRC

SACNT

Source Active Options Register

Source Active Source Address Register

Source Active Count Register

02A2 8244

02A2 8248

64

Specifications

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Table 4-11. EDMA3 Transfer Controller 1 Registers (continued)

HEX ADDRESS RANGE

02A2 824C

ACRONYM

SADST

REGISTER NAME

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

02A2 8250

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

-

02A2 8254

02A2 8258

02A2 825C

02A2 8260

Source Active Destination Address B-Reference Register

Reserved

02A2 8264 - 02A2 827C

02A2 8280

DFCNTRLD

DFSRCBREF

DFDSTBREF

-

Destination FIFO Set Count Reload

Destination FIFO Set Destination Address B Reference Register

Reserved

02A2 8284

02A2 8288

02A2 828C - 02A2 82FC

02A2 8300

DFOPT0

DFSRC0

DFCNT0

DFDST0

DFBIDX0

DFM PPRXY0

-

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

Destination FIFO Count Register 0

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

02A2 8304

02A2 8308

02A2 830C

02A2 8310

02A2 8314

Destination FIFO Memory Protection Proxy Register 0

Reserved

02A2 8318 - 02A2 833C

02A2 8340

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1

DFMPPRXY1

-

Destination FIFO Options Register 1

Destination FIFO Source Address Register 1

Destination FIFO Count Register 1

Destination FIFO Destination Address Register 1

Destination FIFO BIDX Register 1

02A2 8344

02A2 8348

02A2 834C

02A2 8350

02A2 8354

Destination FIFO Memory Protection Proxy Register 1

Reserved

02A2 8358 - 02A2 837C

02A2 8380

DFOPT2

DFSRC2

DFCNT2

DFDST2

DFBIDX2

DFMPPRXY2

-

Destination FIFO Options Register 2

Destination FIFO Source Address Register 2

Destination FIFO Count Register 2

Destination FIFO Destination Address Register 2

Destination FIFO BIDX Register 2

02A2 8384

02A2 8388

02A2 838C

02A2 8390

02A2 8394

Destination FIFO Memory Protection Proxy Register 2

Reserved

02A2 8398 - 02A2 83BC

02A2 83C0

DFOPT3

DFSRC3

DFCNT3

DFDST3

DFBIDX3

DFMPPRXY3

-

Destination FIFO Options Register 3

Destination FIFO Source Address Register 3

Destination FIFO Count Register 3

Destination FIFO Destination Address Register 3

Destination FIFO BIDX Register 3

02A2 83C4

02A2 83C8

02A2 83CC

02A2 83D0

02A2 83D4

Destination FIFO Memory Protection Proxy Register 3

Reserved

02A2 83D8 - 02A2 FFFC

Specifications

65

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Table 4-12. EDMA3 Transfer Controller 2 Registers

HEX ADDRESS RANGE

02A3 0000

ACRONYM

PID

REGISTER NAME

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved

02A3 0004

TCCFG

-

02A3 0008 - 02A3 00FC

02A3 0100

TCSTAT

-

EDMA3TC Channel Status Register

Reserved

02A3 0104 - 02A3 011C

02A3 0120

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

Error Register

02A3 0124

Error Enable Register

02A3 0128

Error Clear Register

02A3 012C

Error Details Register

02A3 0130

Error Interrupt Command Register

Reserved

02A3 0134 - 02A3 013C

02A3 0140

RDRATE

-

Read Rate Register

02A3 0144 - 02A3 023C

02A3 0240

Reserved

SAOPT

SASRC

SACNT

SADST

Source Active Options Register

Source Active Source Address Register

Source Active Count Register

02A3 0244

02A3 0248

02A3 024C

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

Source Active Destination Address B-Reference Register

Reserved

02A3 0250

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

-

02A3 0254

02A3 0258

02A3 025C

02A3 0260

02A3 0264 - 02A3 027C

02A3 0280

DFCNTRLD

DFSRCBREF

DFDSTBREF

-

Destination FIFO Set Count Reload

Destination FIFO Set Destination Address B Reference Register

Reserved

02A3 0284

02A3 0288

02A3 028C - 02A3 02FC

02A3 0300

DFOPT0

DFSRC0

DFCNT0

DFDST0

DFBIDX0

DFMPPRXY0

-

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

Destination FIFO Count Register 0

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

Destination FIFO Memory Protection Proxy Register 0

Reserved

02A3 0304

02A3 0308

02A3 030C

02A3 0310

02A3 0314

02A3 0318 - 02A3 033C

02A3 0340

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1

DFMPPRXY1

-

Destination FIFO Options Register 1

Destination FIFO Source Address Register 1

Destination FIFO Count Register 1

Destination FIFO Destination Address Register 1

Destination FIFO BIDX Register 1

Destination FIFO Memory Protection Proxy Register 1

Reserved

02A3 0344

02A3 0348

02A3 034C

02A3 0350

02A3 0354

02A3 0358 - 02A3 037C

02A3 0380

DFOPT2

DFSRC2

DFCNT2

DFDST2

DFBIDX2

DFMPPRXY2

Destination FIFO Options Register 2

Destination FIFO Source Address Register 2

Destination FIFO Count Register 2

Destination FIFO Destination Address Register 2

Destination FIFO BIDX Register 2

Destination FIFO Memory Protection Proxy Register 2

02A3 0384

02A3 0388

02A3 038C

02A3 0390

02A3 0394

66

Specifications

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Table 4-12. EDMA3 Transfer Controller 2 Registers (continued)

HEX ADDRESS RANGE

02A3 0398 - 02A3 03BC

02A3 03C0

ACRONYM

-

REGISTER NAME

Reserved

DFOPT3

DFSRC3

DFCNT3

DFDST3

DFBIDX3

DFMPPRXY3

-

Destination FIFO Options Register 3

Destination FIFO Source Address Register 3

Destination FIFO Count Register 3

Destination FIFO Destination Address Register 3

Destination FIFO BIDX Register 3

Destination FIFO Memory Protection Proxy Register 3

Reserved

02A3 03C4

02A3 03C8

02A3 03CC

02A3 03D0

02A3 03D4

02A3 03D8 - 02A3 7FFC

Table 4-13. EDMA3 Transfer Controller 3 Registers

HEX ADDRESS RANGE

02A3 8000

ACRONYM

PID

REGISTER NAME

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved

02A3 8004

TCCFG

-

02A3 8008 - 02A3 80FC

02A3 8100

TCSTAT

-

EDMA3TC Channel Status Register

Reserved

02A3 8104 - 02A3 811C

02A3 8120

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

Error Register

02A3 8124

Error Enable Register

02A3 8128

Error Clear Register

02A3 812C

Error Details Register

02A3 8130

Error Interrupt Command Register

Reserved

02A3 8134 - 02A3 813C

02A3 8140

RDRATE

-

Read Rate Register

02A3 8144 - 02A3 823C

02A3 8240

Reserved

SAOPT

SASRC

SACNT

SADST

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

-

Source Active Options Register

Source Active Source Address Register

Source Active Count Register

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

02A3 8244

02A3 8248

02A3 824C

02A3 8250

02A3 8254

02A3 8258

02A3 825C

02A3 8260

Source Active Destination Address B-Reference Register

Reserved

02A3 8264 - 02A3 827C

02A3 8280

DFCNTRLD

DFSRCBREF

DFDSTBREF

-

Destination FIFO Set Count Reload

Destination FIFO Set Destination Address B Reference Register

Reserved

02A3 8284

02A3 8288

02A3 828C - 02A3 82FC

02A3 8300

DFOPT0

DFSRC0

DFCNT0

DFDST0

DFBIDX0

DFMPPRXY0

-

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

Destination FIFO Count Register 0

02A3 8304

02A3 8308

02A3 830C

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

02A3 8310

02A3 8314

Destination FIFO Memory Protection Proxy Register 0

Reserved

02A3 8318 - 02A3 833C

02A3 8340

DFOPT1

DFSRC1

Destination FIFO Options Register 1

Destination FIFO Source Address Register 1

02A3 8344

Specifications

67

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Table 4-13. EDMA3 Transfer Controller 3 Registers (continued)

HEX ADDRESS RANGE

02A3 8348

ACRONYM

DFCNT1

DFDST1

DFBIDX1

DFMPPRXY1

-

REGISTER NAME

Destination FIFO Count Register 1

Destination FIFO Destination Address Register 1

Destination FIFO BIDX Register 1

Destination FIFO Memory Protection Proxy Register 1

Reserved

02A3 834C

02A3 8350

02A3 8354

02A3 8358 - 02A3 837C

02A3 8380

DFOPT2

DFSRC2

DFCNT2

DFDST2

DFBIDX2

DFMPPRXY2

-

Destination FIFO Options Register 2

Destination FIFO Source Address Register 2

Destination FIFO Count Register 2

Destination FIFO Destination Address Register 2

Destination FIFO BIDX Register 2

Destination FIFO Memory Protection Proxy Register 2

Reserved

02A3 8384

02A3 8388

02A3 838C

02A3 8390

02A3 8394

02A3 8398 - 02A3 83BC

02A3 83C0

DFOPT3

DFSRC3

DFCNT3

DFDST3

DFBIDX3

DFMPPRXY3

-

Destination FIFO Options Register 3

Destination FIFO Source Address Register 3

Destination FIFO Count Register 3

Destination FIFO Destination Address Register 3

Destination FIFO BIDX Register 3

Destination FIFO Memory Protection Proxy Register 3

Reserved

02A3 83C4

02A3 83C8

02A3 83CC

02A3 83D0

02A3 83D4

02A3 83D8 - 02A3 FFFC

Table 4-14. EDMA3 Transfer Controller 4 Registers

HEX ADDRESS RANGE

02A4 0000

ACRONYM

PID

REGISTER NAME

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved

02A4 0004

TCCFG

-

02A4 0008 - 02A4 00FC

02A4 0100

TCSTAT

-

EDMA3TC Channel Status Register

Reserved

02A4 0104 - 02A4 011C

02A4 0120

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

Error Register

02A4 0124

Error Enable Register

02A4 0128

Error Clear Register

02A4 012C

Error Details Register

02A4 0130

Error Interrupt Command Register

Reserved

02A4 0134 - 02A4 013C

02A4 0140

RDRATE

-

Read Rate Register

02A4 0144 - 02A4 023C

02A4 0240

Reserved

SAOPT

SASRC

SACNT

SADST

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

-

Source Active Options Register

Source Active Source Address Register

Source Active Count Register

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

Source Active Destination Address B-Reference Register

Reserved

02A4 0244

02A4 0248

02A4 024C

02A4 0250

02A4 0254

02A4 0258

02A4 025C

02A4 0260

02A4 0264 - 02A4 027C

02A4 0280

DFCNTRLD

DFSRCBREF

Destination FIFO Set Count Reload

Destination FIFO Set Destination Address B Reference Register

02A4 0284

68

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Table 4-14. EDMA3 Transfer Controller 4 Registers (continued)

HEX ADDRESS RANGE

02A4 0288

ACRONYM

DFDSTBREF

-

REGISTER NAME

Destination FIFO Set Destination Address B Reference Register

Reserved

02A4 028C - 02A4 02FC

02A4 0300

DFOPT0

DFSRC0

DFCNT0

DFDST0

DFBIDX0

DFMPPRXY0

-

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

Destination FIFO Count Register 0

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

02A4 0304

02A4 0308

02A4 030C

02A4 0310

02A4 0314

Destination FIFO Memory Protection Proxy Register 0

Reserved

02A4 0318 - 02A4 033C

02A4 0340

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1

DFMPPRXY1

-

Destination FIFO Options Register 1

Destination FIFO Source Address Register 1

Destination FIFO Count Register 1

Destination FIFO Destination Address Register 1

Destination FIFO BIDX Register 1

02A4 0344

02A4 0348

02A4 034C

02A4 0350

02A4 0354

Destination FIFO Memory Protection Proxy Register 1

Reserved

02A4 0358 - 02A4 037C

02A4 0380

DFOPT2

DFSRC2

DFCNT2

DFDST2

DFBIDX2

DFMPPRXY2

-

Destination FIFO Options Register 2

Destination FIFO Source Address Register 2

Destination FIFO Count Register 2

Destination FIFO Destination Address Register 2

Destination FIFO BIDX Register 2

02A4 0384

02A4 0388

02A4 038C

02A4 0390

02A4 0394

Destination FIFO Memory Protection Proxy Register 2

Reserved

02A4 0398 - 02A4 03BC

02A4 03C0

DFOPT3

DFSRC3

DFCNT3

DFDST3

DFBIDX3

DFMPPRXY3

-

Destination FIFO Options Register 3

Destination FIFO Source Address Register 3

Destination FIFO Count Register 3

Destination FIFO Destination Address Register 3

Destination FIFO BIDX Register 3

02A4 03C4

02A4 03C8

02A4 03CC

02A4 03D0

02A4 03D4

Destination FIFO Memory Protection Proxy Register 3

Reserved

02A4 03D8 - 02A4 7FFC

Table 4-15. EDMA3 Transfer Controller 5 Registers

HEX ADDRESS RANGE

02A4 8000

ACRONYM

PID

REGISTER NAME

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved

02A4 8004

TCCFG

-

02A4 8008 - 02A4 80FC

02A4 8100

TCSTAT

-

EDMA3TC Channel Status Register

Reserved

02A4 8104 - 02A4 811C

02A4 8120

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

Error Register

02A4 8124

Error Enable Register

Error Clear Register

Error Details Register

Error Interrupt Command Register

Reserved

02A4 8128

02A4 812C

02A4 8130

02A4 8134 - 02A4 813C

02A4 8140

RDRATE

-

Read Rate Register

Reserved

02A4 8144 - 02A4 823C

02A4 8240

SAOPT

Source Active Options Register

Specifications

69

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Table 4-15. EDMA3 Transfer Controller 5 Registers (continued)

HEX ADDRESS RANGE

02A4 8244

ACRONYM

SASRC

REGISTER NAME

Source Active Source Address Register

Source Active Count Register

02A4 8248

SACNT

02A4 824C

SADST

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

Source Active Destination Address B-Reference Register

Reserved

02A4 8250

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

-

02A4 8254

02A4 8258

02A4 825C

02A4 8260

02A4 8264 - 02A4 827C

02A4 8280

DFCNTRLD

DFSRCBREF

DFDSTBREF

-

Destination FIFO Set Count Reload

Destination FIFO Set Destination Address B Reference Register

Reserved

02A4 8284

02A4 8288

02A4 828C - 02A4 82FC

02A4 8300

DFOPT0

DFSRC0

DFCNT0

DFDST0

DFBIDX0

DFMPPRXY0

-

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

Destination FIFO Count Register 0

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

02A4 8304

02A4 8308

02A4 830C

02A4 8310

02A4 8314

Destination FIFO Memory Protection Proxy Register 0

Reserved

02A4 8318 - 02A4 833C

02A4 8340

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1

DFMPPRXY1

-

Destination FIFO Options Register 1

Destination FIFO Source Address Register 1

Destination FIFO Count Register 1

Destination FIFO Destination Address Register 1

Destination FIFO BIDX Register 1

02A4 8344

02A4 8348

02A4 834C

02A4 8350

02A4 8354

Destination FIFO Memory Protection Proxy Register 1

Reserved

02A4 8358 - 02A4 837C

02A4 8380

DFOPT2

DFSRC2

DFCNT2

DFDST2

DFBIDX2

DFMPPRXY2

-

Destination FIFO Options Register 2

Destination FIFO Source Address Register 2

Destination FIFO Count Register 2

Destination FIFO Destination Address Register 2

Destination FIFO BIDX Register 2

02A4 8384

02A4 8388

02A4 838C

02A4 8390

02A4 8394

Destination FIFO Memory Protection Proxy Register 2

Reserved

02A4 8398 - 02A4 83BC

02A4 83C0

DFOPT3

DFSRC3

DFCNT3

DFDST3

DFBIDX3

DFMPPRXY3

-

Destination FIFO Options Register 3

Destination FIFO Source Address Register 3

Destination FIFO Count Register 3

Destination FIFO Destination Address Register 3

Destination FIFO BIDX Register 3

02A4 83C4

02A4 83C8

02A4 83CC

02A4 83D0

02A4 83D4

Destination FIFO Memory Protection Proxy Register 3

Reserved

02A4 83D8 - 02A4 FFFC

70

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4.8.2 Interrupts

4.8.2.1 Interrupt Sources and Interrupt Controller

The CPU interrupts on the C6457 device are configured through the C64x+ Megamodule Interrupt

Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the

twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced

emulation logic. The 128 system events consist of both internally-generated events (within the

megamodule) and chip-level events. Table 4-16 shows the mapping of system events. For more

information on the Interrupt Controller, see the TMS320C64x+ Megamodule Reference Guide (SPRU871).

Table 4-16. C6457 System Event Mapping

EVENT NUMBER

INTERRUPT EVENT

EVT0

DESCRIPTION

0⁽¹⁾

1⁽¹⁾

2⁽¹⁾

3⁽¹⁾

4 - 8

9⁽¹⁾

Output of event combiner 0 in interrupt controller, for events 1 - 31.

Output of event combiner 1 in interrupt controller, for events 32 - 63.

Output of event combiner 2 in interrupt controller, for events 64 - 95.

Output of event combiner 3 in interrupt controller, for events 96 - 127.

Reserved. These system events are not connected and, therefore, not used.

EMU interrupt for:

EVT1

EVT2

EVT3

Reserved

EMU_DTDMA

•

Host scan access

DTDMA transfer complete

AET interrupt

10

11⁽¹⁾

12⁽¹⁾

13(1)

14⁽¹⁾

15

None

EMU_RTDXRX

EMU_RTDXTX

IDMA0

This system event is not connected and, therefore, not used.

EMU real-time data exchange (RTDX) receive complete

EMU RTDX transmit complete

IDMA channel 0 interrupt

IDMA1

IDMA channel 1 interrupt

DSPINT

HPI-to-DSP interrupt

16

I2CINT

I²C interrupt

17

MACINT

Ethernet MAC interrupt

18

AEASYNCERR

Reserved

INTDST0

EMIFA error interrupt

19

Reserved. This system event is not connected and, therefore, not used.

RapidIO interrupt 0

20

21

INTDST1

RapidIO interrupt 1

22

INTDST2

RapidIO interrupt 2

23

INTDST3

RapidIO interrupt 3

24

EDMA3CC_GINT

MACRXINT

MACTXINT

MACTHRESH

INTDST4

EDMA3 channel global completion interrupt

Ethernet MAC receive interrupt

Ethernet MAC transmit interrupt

Ethernet MAC receive threshold interrupt

RapidIO interrupt 4

25

26

27

28

29

INTDST5

RapidIO interrupt 5

30

INTDST6

RapidIO interrupt 6

31

Reserved

VCP2_INT

TCP2A_INT

TCP2B_INT

Reserved

UINT

Reserved. These system events are not connected and, therefore, not used.

VCP2 error interrupt

32

33

TCP2_A error interrupt

34

TCP2_B error interrupt

35

Reserved. These system events are not connected and, therefore, not used.

UTOPIA interrupt

36

37 - 39

Reserved

Reserved. These system events are not connected and, therefore, not used.

(1) This system event is generated from within the C64x+ megamodule.

Specifications

71

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Table 4-16. C6457 System Event Mapping (continued)

EVENT NUMBER

INTERRUPT EVENT

RINT0

DESCRIPTION

40

41

McBSP0 receive interrupt

McBSP0 transmit interrupt

McBSP1 receive interrupt

McBSP1 transmit interrupt

Reserved. Do not use.

GPIO interrupt

XINT0

42

RINT1

43

XINT1

44 - 50

51

Reserved

GPINT0

52

GPINT1

GPIO interrupt

53

GPINT2

GPIO interrupt

54

GPINT3

GPIO interrupt

55

GPINT4

GPIO interrupt

56

GPINT5

GPIO interrupt

57

GPINT6

GPIO interrupt

58

GPINT7

GPIO interrupt

59

GPINT8

GPIO interrupt

60

GPINT9

GPIO interrupt

61

GPINT10

GPIO interrupt

62

GPINT11

GPIO interrupt

63

GPINT12

GPIO interrupt

64

GPINT13

GPIO interrupt

65

GPINT14

GPIO interrupt

66

GPINT15

GPIO interrupt

67

TINTLO0

Timer 0 lower counter interrupt

Timer 0 higher counter interrupt

Timer 1 lower counter interrupt

Timer 1 higher counter interrupt

EDMA3CC completion interrupt - Mask0

EDMA3CC completion interrupt - Mask1

EDMA3CC completion interrupt - Mask2

EDMA3CC completion interrupt - Mask3

EDMA3CC completion interrupt - Mask4

EDMA3CC completion interrupt - Mask5

EDMA3CC completion interrupt - Mask6

EDMA3CC completion interrupt - Mask7

EDMA3CC error interrupt

68

TINTHI0

69

TINTLO1

70

TINTHI1

71

EDMA3CC_INT0

EDMA3CC_INT1

EDMA3CC_INT2

EDMA3CC_INT3

EDMA3CC_INT4

EDMA3CC_INT5

EDMA3CC_INT6

EDMA3CC_INT7

EDMA3CC_ERRINT

Reserved

72

73

74

75

76

77

78

79

80

Reserved. This system event is not connected and, therefore, not used.

EDMA3TC0 error interrupt

81

EDMA3TC0_ERRINT

EDMA3TC1_ERRINT

EDMA3TC2_ERRINT

EDMA3TC3_ERRINT

EDMA3CC_AET

EDMA3TC4_ERRINT

EDMA3TC5_ERRINT

Reserved

82

EDMA3TC1 error interrupt

83

EDMA3TC2 error interrupt

84

EDMA3TC3 error interrupt

85

EDMA3CC AET Event

86

EDMA3TC4 error interrupt

87

EDMA3TC5 error interrupt

88 - 93

94

Reserved. These system events are not connected and, therefore, not used.

Overflow condition occurred in ETB

Underflow condition occurred in ETB

Interrupt Controller dropped CPU interrupt event

EMC invalid IDMA parameters

ETBOVFLINT

ETBUNFLINT

INTERR

95

96⁽¹⁾

97⁽¹⁾

EMC_IDMAERR

72

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Table 4-16. C6457 System Event Mapping (continued)

EVENT NUMBER

INTERRUPT EVENT

Reserved

DESCRIPTION

98 - 99

100⁽¹⁾

101⁽¹⁾

102 - 112

113⁽¹⁾

114 - 115

116⁽¹⁾

117⁽¹⁾

118⁽¹⁾

119⁽¹⁾

120⁽¹⁾

121⁽¹⁾

122⁽¹⁾

123⁽¹⁾

124⁽¹⁾

125⁽¹⁾

126⁽¹⁾

127⁽¹⁾

Reserved. These system events are not connected and, therefore, not used.

EFI interrupt from side A

EFIINTA

EFIINTB

EFI interrupt from side B

Reserved

Reserved. These system events are not connected and, therefore, not used.

L1P single bit error detected during DMA read

Reserved. These system events are not connected and, therefore, not used.

L2 single bit error detected

L1P_ED1

Reserved

L2_ED1

L2_ED2

L2 two bit error detected

PDC_INT

Powerdown sleep interrupt

SYS_CMPA

L1P_CMPA

L1P_DMPA

L1D_CMPA

L1D_DMPA

L2_CMPA

L2_DMPA

IDMA_CMPA

IDMA_BUSERR

CPU memory protection fault

L1P CPU memory protection fault

L1P DMA memory protection fault

L1D CPU memory protection fault

L1D DMA memory protection fault

L2 CPU memory protection fault

L2 DMA memory protection fault

IDMA CPU memory protection fault

IDMA bus error interrupt

4.8.2.2 External Interrupts Electrical Data/Timing

Table 4-17. Timing Requirements for External Interrupts⁽¹⁾

(see Figure 4-11)

NO.

MIN

6P

MAX UNIT

1

2

t_w(NMIL)

t_w(NMIH)

Width of the NMI interrupt pulse low

Width of the NMI interrupt pulse high

ns

6P

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

2

1

NMI

Figure 4-11. NMI Interrupt Timing

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4.8.3 Reset Controller

The reset controller detects the different type of resets supported on the C6457 device and manages the

distribution of those resets throughout the device.

The C6457 device has several types of resets:

•

Power-on reset

Warm reset

System reset

CPU reset

Table 4-18 explains further the types of reset, the reset initiator, and the effects of each reset on the

device. For more information on the effects of each reset on the PLL controllers and their clocks, see

Section 4.7.1.

Table 4-18. Reset Types

TYPE

INITIATOR

POR pin

EFFECT(S)

Resets the entire chip including the test and emulation logic. The device configuration pins are

latched only during POR.

Power-on Reset

Resets everything except for the test and emulation logic and PLL2. The emulator stays alive

during warm reset. The device configuration pins are not re-latched. DDR2 memory contents

will be preserved if the user places the DDR2 SDRAM in “Self-Refresh” mode before starting a

Warm Reset sequence.

Warm Reset

RESET pin

Emulator

System reset, by default, behaves as hard reset, but can be configured as soft reset if initiated

by Serial RapidIO or PLLCTL. Emulator-initiated reset is always a hard reset.

Serial RapidIO

PLLCTL⁽¹⁾

•

Hard reset effects are the same as those of a warm reset.

Soft reset means external memory contents can be maintained, it does not affect the clock

logic, or the power control logic of the peripherals. See Section 4.8.3.3 for more details.

System Reset

A system reset does not reset the test and emulation circuitry. The device configuration pins are

also not re-latched.

CPU Local Reset

Watchdog Timer

CPU local reset.

(1) All masters in the device have access to the PLLCTL registers.

74

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4.8.3.1 Power-on Reset (POR Pin)

Power-on reset is initiated by the POR pin and is used to reset the entire device, including the test and

emulation logic. Power-on reset is also referred to as a cold reset because the device usually goes

through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power

supplies have reached their normal operating conditions. Note that a device power-up cycle is not required

to initiate a power-on reset. For power-on reset, the main PLL controller comes up in bypass mode and

the PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL controller.

For the secondary PLL, the PLL is enabled and always clocking when POR is not asserted.

The following sequence must be followed during a power-on reset:

1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted

(driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After

the POR pin is de-asserted (driven high), all Z group pins, low group pins, and high group pins are set

to their reset state and will remain at their reset state until otherwise configured by their respective

peripheral. All peripherals that are power managed, are disabled after a Power-on Reset and must be

enabled through the Device State Control registers (for more details, see Section 5.5.2).

2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset

synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in

reset.

3. POR must be held active until all supplies on the board are stable then for at least an additional 100 µs

+ 2000 CLKIN2 cycles.

4. The POR pin can now be de-asserted. Reset sampled pin values are latched at this point. PLL2 is

taken out of reset and begins its locking sequence, and all power-on device initialization also begins.

5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time,

PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of

both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their

respective system reference clocks. After the pause, the system clocks are restarted at their default

divide by settings.

6. The device is now out of reset and device execution begins as dictated by the selected boot mode.

NOTE

To most of the device, reset is de-asserted only when the POR and RESET pins are both

de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is

held low past the low period of the POR pin, most of the device will remain in reset. The

RESET pin should not be tied together with the POR pin.

Specifications

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4.8.3.2 Warm Reset (RESET Pin)

A warm reset will reset everything on the device except the PLLs, PLL controller, test, and emulation logic.

POR should also remain de-asserted during this time.

The following sequence must be followed during a warm reset:

1. The RESET pin is pulled active low for a minimum of 24 CLKIN1 cycles. During this time the RESET

signal is able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z

for modules affected by RESET, to prevent off-chip contention during the warm reset.

2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.

3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that

configuration pins are not re-latched and clocking is unaffected within the device.

4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).

NOTE

The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise,

if POR is activated (brought low), the minimum POR pulse width must be met. The RESET

pin should not be tied together with the POR pin.

NOTE

The DDR2 SDRAM contents will also be preserved if the user places the SDRAM into Self-

Refresh mode before starting a Warm Reset sequence. Please see theTMS320C6457 DSP

DDR2 Memory Controller User’s Guide (SPRUGK5).

4.8.3.3 System Reset

In a System Reset, test and emulation logic are unaffected. The device configuration pins are also not re-

latched. System reset can be initiated by the emulator or Serial RapidIO or by the PLLCTL:

•

Emulator Initiated System Reset: The emulator initiated System Reset is always a Hard Reset. The

effects of a Hard Reset are the same as a Warm Reset (defined in Section 4.8.3.2).

•

Serial RapidIO Initiated System Reset: The Serial Rapid IO initiated System Reset can be

configured by the RSTCFG register (see Section 4.8.3.6.3) as a Soft Reset or Hard Reset. For more

information on the Serial RapidIO initiated system reset, see Section 4.2 of the TMS320C6457 DSP

Serial RapidIO (SRIO) User's Guide (SPRUGK4).

•

PLLCTL Initiated System Reset: The PLLCTL module can initiate a System Reset using the

RSTCTRL register; see Section 4.8.3.6.2. The PLLCTL initiated System Reset can be configured by

the RSTCFG register (see Section 4.8.3.6.3) as a Soft Reset or Hard Reset.

In the case of a Soft Reset, the clock logic or the power control logic of the peripherals are not affected,

and, therefore, the enabled/disabled state of the peripherals is not affected. The following external

memory contents are maintained during a soft reset:

•

DDR2 Memory Controller: The DDR2 Memory Controller registers are not reset. In addition, the

DDR2 SDRAM memory content is retained if the user places the DDR2 SDRAM in self-refresh mode

before invoking the soft reset.

•

EMIFA: The contents of the memory connected to the EMIFA are retained. The EMIFA registers are

not reset.

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During a soft reset, the following happens:

1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to

propagate through the system. Internal system clocks are not affected. PLLs also remain locked.

2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the

PLL controllers pause their system clocks for about 10 cycles.

–

At this point:

–

The state of the peripherals before the soft reset is not changed. For example, if McBSP0 was

in the enabled state before soft reset, it will remain in the enabled state after soft reset.

The I/O pins are controlled as dictated by the DEVSTAT register.

The DDR2 Memory Controller and EMIFA registers retain their previous values. Only the DDR2

Memory Controller and EMIFA state machines are reset by the soft reset.

–

The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.

The boot sequence is started after the system clocks are restarted. Since the configuration pins (including

the BOOTMODE[3:0] pins) are not latched with a System Reset, the previous values, as shown in the

DEVSTAT register, are used to select the boot mode.

4.8.3.4 CPU Reset

Timer1 can provide a local CPU reset if it is set up in watchdog mode.

4.8.3.5 Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority

reset request. The reset request priorities are as follows (high to low):

•

Power-on reset

Warm reset and system reset

4.8.3.6 Reset Controller Register

There are three reset controller registers: Reset Type Status (RSTYPE) register (029A 00E4), Software

Reset Control (RSTCTRL) register (029A 00E8), and Reset Configuration (RSTCFG) register (029A

00EC). All three registers fall in the same memory range as the PLL1 Controller registers [029A 0000 -

029A 0170] (see Table 4-24).

Specifications

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4.8.3.6.1 Reset Type Status Register

The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur

simultaneously, this register latches the highest priority reset source. The Reset Type Status register is

shown in Figure 4-12 and described in Table 4-19.

Figure 4-12. Reset Type Status Register (RSTYPE) (Address - 029A 00E4h)

31

15

30

29

13

28

27

26

25

24

23

22

21

20

19

18

17

16

Reserved

EMU-

RST

Reserved

R-0

14

R-0

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved

SRIOR

ST

Reserved

PLLCTR WRST POR

LRST

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-19. Reset Type Status Register (RSTYPE) Field Descriptions

Bit

31:29

28

Acronym

Reserved

EMU-RST

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

•

System reset initiated by emulator.

0 = Not the last reset to occur.

1 = The last reset to occur.

27:9

8

Reserved

SRIORST

Reserved. Read only. Always reads as 0. Writes have no effect.

•

System reset initiated by SRIO.

0 = Not the last reset to occur.

1 = The last reset to occur.

7:3

2

Reserved

Reserved. Read only. Always reads as 0. Writes have no effect.

PLLCTLRST

•

System reset initiated by PLLCTL.

0 = Not the last reset to occur.

1 = The last reset to occur.

1

0

WRST

POR

•

Warm reset.

0 = Warm reset was not the last reset to occur.

1 = Warm reset was the last reset to occur.

•

Power-on reset.

0 = Power-on reset was not the last reset to occur.

1 = Power-on reset was the last reset to occur.

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4.8.3.6.2 Software Reset Control Register

This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The

key value is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the

RSTCTRL or the RSTCFG is written, the key is invalidated. Every write must be set up with a valid key.

The Software Reset Control register (RSTCTRL) is shown in Figure 4-13 and described in Table 4-20.

Figure 4-13. Software Reset Control Register (RSTCTRL) (Hex Address - 029A 00E8h)

31

15

30

14

29

13

28

27

26

25

24

23

22

21

20

19

18

17

16

Reserved

R-0x0000

SWRST⁽¹⁾

R/W-0x

12

11

10

9

8

7

6

5

4

3

2

1

0

KEY

R/W-0x0003

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) Writes are conditional based on valid key.

Table 4-20. Software Reset Control Register Field Descriptions

Bit

31:17

16

Acronym

Reserved

SWRST

Description

Reserved.

•

Software reset

0 = Reset

1 = Not reset

KEY

15:0

•

Key used to enable writes to RSTCTRL and RSTCFG.

Specifications

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4.8.3.6.3 Reset Configuration Register

This register is used to configure the type of system resets initiated by the SRIO module or a PLL

controller; i.e., a hard reset or a soft reset. By default, both the system resets will be hard resets. The

Reset Configuration register (RSTCFG) is shown in Figure 4-14 and described in Table 4-21.

Figure 4-14. Reset Configuration Register (RSTCFG) (Address - 029A 00ECh)

31

15

30

29

28

27

11

26

10

25

9

24

Reserved

R-0x2000

23

22

21

5

20

4

19

3

18

2

17

1

16

14

13

12

8

7

6

0

Reserved

PLLCTL

RSTTY

PE

R/W-0⁽¹⁾

Reserved

R-0x000

SRIOR

STTY

PE

R-0x000

R/W-

0x0⁽¹⁾

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) Writes are conditional based on valid key. For details, see Section 4.8.3.6.2.

Table 4-21. Reset Configuration Register (RSTCFG) Field Descriptions

Bit

31:14

13

Acronym

Description

Reserved

Reserved.

PLLCTLRSTTYPE

PLL controller initiates a software driven reset of type:

•

0 = Hard reset (default)

1 = Soft reset

12:1

0

Reserved

Reserved.

SRIORSTTYPE

SRIO module initiates a reset of type:

•

0 = Hard Reset (default)

1 = Soft Reset

4.8.4 PLL1 and PLL1 Controller

This section provides a description of the PLL1 controller. For details on the operation of the PLL

controller module, see the TMS320C6457 DSP Software-Programmable Phase-Locked Loop (PLL)

Controller User's Guide (SPRUGL3).

NOTE

The PLL1 controller registers can be accessed by any master in the device.

The main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios,

alignment, and gating for the system clocks to the device. Figure 4-15 shows a block diagram of the PLL

controller. The following paragraphs define the clocks and PLL controller parameters.

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6484

Main PLL Controller

Main PLL

/1

xM

SYSREFCLK

CORECLK(N|P)

ALTCORECLK

C64x+

Megamodule

CORECLKSEL

/2

/x

SYSCLK2

SYSCLK3

To L2 and L2

PDCL

DV_DD18

EMI

Filter

C1

PLLV₁

C2

/3

/6

/y

/z

560 pF

0.01 µF

SYSCLK4 (chip_clk3)

SYSCLK5 (chip_clk6)

SYSCLK6 (mcbsp_clks)

SYSCLK7 (emifa_mclk)

To Switch Fabric,

Peripherals,

Accelerators

/p

/1

SYSCLK8 (slow_sysclk)

SYSCLK9 (rsa_clk)

Figure 4-15. PLL1 and PLL1 Controller

The inputs, multiply factor within the PLL, and post-division for each of the chip-level clocks from the PLL

output. The PLL controller also controls reset propagation through the chip, clock alignment, and test

points. The PLL controller monitors the PLL status and provides an output signal indicating when the PLL

is locked.

PLL1 power is supplied externally via the PLL1 power-supply pin (PLLV1). An external EMI filter circuit

must be added to PLLV1, as shown in Figure 4-15. The 1.8-V supply of the EMI filter must be from the

same 1.8-V power plane supplying the I/O power-supply pin, DV_DD18. TI requires EMI filter manufacturer

Murata, part number NFM18CC222R1C3 or NFM18CC223R1C3.

All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the C64x+ DSP

device as possible. For the best performance, TI recommends that all the PLL external components be on

a single side of the board without jumpers, switches, or components other than those shown. For reduced

PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1,

C2, and the EMI Filter).

The minimum CORECLK rise and fall times should also be observed. For the input clock timing

requirements, see Section 4.8.4.4.

Specifications

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CAUTION

The PLL controller module as described in the TMS320C6457 DSP Software-

Programmable Phase-Locked Loop (PLL) Controller User's Guide (SPRUGL3)

includes a superset of features, some of which are not supported on the C6457

DSP. The following sections describe the registers that are supported; it should

be assumed that any registers not included in these sections is not supported

by the C6457 DSP. Furthermore, only the bits within the registers described

here are supported. Avoid writing to any reserved memory location or changing

the value of reserved bits.

4.8.4.1 PLL1 Controller Device-Specific Information

4.8.4.1.1 Internal Clocks and Maximum Operating Frequencies

The main PLL, used to drive the core, the switch fabric, and a majority of the peripheral clocks (all but the

DDR2 clock) requires a PLL controller to manage the various clock divisions, gating, and synchronization.

The main PLL controller has several SYSCLK outputs that are listed below, along with the clock

description. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL.

Note that dividers are not programmable unless explicitly mentioned in the description below.

•

SYSREFCLK: Full-rate clock (GEM_CLK1) for C64x+ megamodule.

SYSCLK2: 1/2-rate clock (GEM_L2_CLK) used to clock the L2 and L2 powerdown controller.

SYSCLK3: 1/x-rate clock (GEM_TRACE_CLK) for emulation and trace logic of the DSP. The default

rate for this clock is 1/3. This is programmable from /1 to /32, where this clock does not violate the

maximum clock rate of 333 MHz. The data rate on the trace pins are 1/2 of this clock.

•

SYSCLK4: 1/3-rate clock (CHIP_CLK3) for the switched central resources (SCRs), EDMA3, VCP2,

TCP2_A, TCP2_B, SRIO, as well as the data bus interfaces of the EMIFA and DDR2 memory

controller.

•

SYSCLK5: 1/6-rate clock (CHIP_CLK6) for other peripherals (PLL controller, PSC, L3 ROM, McBSPs,

Timer64s, EMAC, HPI, UTOPIA, I²C, and GPIO).

SYSCLK6: 1/y-rate clock (CHIP_CLKS) for an optional McBSP CLKS module input to drive the clock

generator. The default for this clock is 1/10. This is programmable from /6 to /32, where this clock does

not violate the maximum clock rate of 100 MHz. This clock is also output to the SYSCLKOUT pin.

•

SYSCLK7: 1/z-rate clock (EMIF_MCLK) for an optional internal clock for EMIFA. The default for this

clock is 1/10. This is programmable from /6 to /32, where this clock does not violate the maximum

clock rate of 166 MHz. The data rate at the pins must not violate 100 MHz.

SYSCLK8: 1/p-rate clock (SLOW_SYSCLK). The default for this clock is 1/10. This is programmable

from /10 to /32.

NOTE

In case any of the other programmable SYSCLKs are set slower than 1/10 rate, then

SYSCLK8 (SLOW_SYSCLK) needs to be programmed to either match, or be slower than,

the slowest SYSCLK in the system.

Note that there is a minimum and maximum operating frequency for CORECLK(N|P), ALTCORECLK,

SYSREFCLK, SYSCLK3, SYSCLK6, and SYSCLK7. The PLL1 controller must not be configured to

exceed any of these constraints (certain combinations of external core clock input, internal dividers, and

PLL multiply ratios might not be supported). For the PLL clocks input and output frequency ranges, see

Table 4-22.

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Table 4-22. Timing Requirements for Reset

CLOCK SIGNAL

MIN

50

MAX UNIT

61.44 MHz

1200 MHz

333 MHz

100 MHz

166 MHz

CORECLK(N|P)

ALTCORECLK

SYSREFCLK

SYSCLK3

50

400

SYSCLK6

SYSCLK7

4.8.4.1.2 PLL1 Controller Operating Modes

The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is

determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is

generated from the device input clock CORECLK(N|P) using the divider POSTDIV and the PLL multiplier

PLLM. In bypass mode, CORECLK(N|P) is fed directly to SYSREFCLK.

All hosts (HPI, etc.) must hold off accesses to the DSP while the frequency of its internal clocks is

changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration

has completed.

4.8.4.1.3 PLL1 Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to

become stable after device powerup. The PLL should not be operated until this stabilization time has

expired.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in

order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the

PLL1 reset time value, see Table 4-23.

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1

with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The

PLL1 lock time is given in Table 4-23.

Table 4-23. PLL1 Stabilization, Lock, and Reset Times

MIN

TYP

MAX

UNIT

PLL stabilization time

PLL lock time

100

µs

2000 × C⁽¹⁾

PLL reset time

1000

ns

(1) C = CORECLK(N|P) cycle time in ns.

Specifications

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4.8.4.2 PLL1 Controller Memory Map

The memory map of the PLL1 controller is shown in Table 4-24. Note that only registers documented here

are accessible on the C6457. Other addresses in the PLL1 controller memory map should not be

modified.

Table 4-24. PLL1 Controller Registers (Including Reset Controller)

HEX ADDRESS RANGE

029A 0000 - 029A 00E3

029A 00E4

ACRONYM

REGISTER NAME

Reserved

-

RSTYPE

Reset Type Status Register (Reset Controller)

Software Reset Control Register

Reset Configuration Register

Reserved

029A 00E8

RSTCTRL

029A 00EC

RSTCFG

029A 00F0 - 029A 00FF

029A 0100

-

PLLCTL

PLL Control Register

Reserved

029A 0104

-

029A 0108

-

Reserved

029A 010C

-

Reserved

029A 0110

PLLM

PLL Multiplier Control Register

Reserved

029A 0114

-

029A 0118

-

Reserved

029A 011C

-

Reserved

029A 0120

PLLDIV3

PLL Controller Divider 3 Register

Reserved

029A 0124

-

029A 0128

POSTDIV

PLL Post-Divider Register

Reserved

029A 012C

-

029A 0130

-

Reserved

029A 0134

-

Reserved

029A 0138

PLLCMD

PLL Controller Command Register

PLL Controller Status Register

PLL Controller Clock Align Control Register

PLLDIV Ratio Change Status Register

Reserved

029A 013C

PLLSTAT

029A 0140

ALNCTL

029A 0144

DCHANGE

029A 0148

-

029A 014C

-

Reserved

029A 0150

SYSTAT

SYSCLK Status Register

Reserved

029A 0154

-

029A 0158

-

Reserved

029A 015C

-

Reserved

029A 0160 - 029A 0164

029A 0168

-

Reserved

PLLDIV6

PLLDIV7

PLLDIV8

-

PLL Controller Divider 6 Register

PLL Controller Divider 7 Register

PLL Controller Divider 8 Register

Reserved

029A 016C

029A 0170

029A 0174 - 029B FFFF

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4.8.4.3 PLL1 Controller Registers

This section provides a description of the PLL1 controller registers. For details on the operation of the PLL

controller module, see theTMS320C6457 DSP Software-Programmable Phase-Locked Loop (PLL)

Controller User's Guide (SPRUGL3).

NOTE

The PLL1 controller registers can be accessed by any master in the device.

CAUTION

Not all of the registers documented in the TMS320C6457 DSP Software-

Programmable Phase-Locked Loop (PLL) Controller User's Guide (SPRUGL3)

are supported on the C6457. Only those registers documented in this section

are supported. Furthermore, only the bits within the registers described here

are supported. Avoid writing to any reserved memory location or changing the

value of reserved bits.

4.8.4.3.1 PLL1 Control Register

The PLL1control register (PLLCTL) is shown in Figure 4-16 and described in Table 4-25.

Figure 4-16. PLL1 Control Register (PLLCTL) (Address - 029A 0100h)

31

15

30

14

29

13

28

27

26

10

25

9

24

Reserved

R-0

23

22

21

20

19

18

17

1

16

0

12

11

8

7

6

5

4

3

2

Reserved

Rsvd

Reserved

R/W-0

PLL

RST

Rsvd

PLLP PLLEN

WRDN

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

R/W-0

R-1

R/W-1

R-0

R/W-0 R/W-0

Table 4-25. PLL1 Control Register (PLLCTL) Field Descriptions

Bit

31:8

7

Acronym

Reserved

PLLRST

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

Reserved. Writes to this register must keep this bit as 0.

Reserved. Read only. Always reads as 1. Writes have no effect.

Reserved. Writes to this register must keep this bit as 0.

PLL reset bit

6

5:4

3

•

0 = PLL reset is released

1 = PLL reset is asserted

2

1

Reserved

Reserved. Read only. Always reads as 0. Writes have no effect.

PLL power-down mode select bit

PLLPWRDN

•

0 = PLL is operational

1 = PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off

0

PLLEN

PLL enable bit

•

0 = Bypass mode. Divider POSTDIV and PLL are bypassed. All the system clocks (SYSCLKn) are divided

down directly from input reference clock.

•

1 = PLL mode. Divider POSTDIV and PLL are not bypassed. PLL output path is enabled. All the system

clocks (SYSCLKn) are divided down from PLL output.

Specifications

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4.8.4.3.2 PLL Multiplier Control Register

The PLL multiplier control register (PLLM) is shown in Figure 4-17 and described in Table 4-26. The PLLM

register defines the input reference clock frequency multiplier in conjunction with the PLL divider ratio bits

(RATIO) in the PLL controller post-divider register (POSTDIV).

Figure 4-17. PLL Multiplier Control Register (PLLM) (Address - 029A 0110h)

31

15

30

14

29

13

28

12

27

11

26

25

9

24

Reserved

R-0

23

22

6

21

5

20

4

19

3

18

17

1

16

0

10

Reserved

R-0

8

7

2

PLLM

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-26. PLL Multiplier Control Register (PLLM) Field Descriptions

Bit

31:5

4:0

Acronym Description

Reserved Reserved. Read only. Always reads as 0. Writes have no effect.

PLLM

PLL multiplier bits. Defines the frequency multiplier of the input reference clock in conjunction with the PLL divider

ratio bits

(RATIO) in POSTDIV.

•

000000 = × 1

000001 = × 2

000010 = × 3

000011 = × 4

000100 = × 5

000101 = × 6

000110 = × 7

000111 = × 8

001000 = × 9

001001 = × 10

001010 = × 11

001011 = × 12

001100 = × 13

001101 = × 14

001110 = × 15

001111 = × 16

•

010000 = × 17

010001 = × 18

010010 = × 19

010011 = × 20

010100 = × 21

010101 = × 22

010110 = × 23

010111 = × 24

011000 = × 25

011001 = × 26

011010 = × 27

011011 = × 28

011100 = × 29

011101 = × 30

011110 = × 31

011111 = × 32

•

100000 = × 33

100001 = × 34

100010 = × 35

100011 = × 36

100100 = × 37

100101 = × 38

100110 = × 39

100111 = × 40

101000 = × 41

101001 = × 42

101010 = × 43

101011 = × 44

101100 = × 45

101101 = × 46

101110 = × 47

101111 = × 48

•

110000 = × 49

110001 = × 50

110010 = × 51

110011 = × 52

110100 = × 53

110101 = × 54

110110 = × 55

110111 = × 56

111000 = × 57

111001 = × 58

111010 = × 59

111011 = × 60

111100 = × 61

111101 = × 62

111110 = × 63

111111 = × 64

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4.8.4.3.3 PLL Post-Divider Control Register

The PLL post-divider control register (POSTDIV) is shown in Figure 4-18 and described in Table 4-27.

Figure 4-18. PLL Post-Divider Control Register (POSTDIV) (Address - 029A 0128)

31

15

30

14

29

13

28

12

27

11

26

25

24

Reserved

R-0

23

22

6

21

5

20

4

19

3

18

17

1

16

0

10

9

8

7

2

POST

DEN

Reserved

R-0

RATIO

R/W-1

R/W-2h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-27. PLL Post-Divider Control Register (POSTDIV) Field Descriptions

Bit

31:16

15

Acronym

Reserved

POSTDEN

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

Post-divider enable bit.

•

0 = Post-divider is disabled. No clock output.

1 = Post-divider is enabled.

14:5

4:0

Reserved

RATIO

Reserved. Read only. Always reads as 0. Writes have no effect.

0 through 1Fh are divider ratio bits:

•

0 = ÷ 1. Divide frequency by 1.

1h = ÷ 2. Divide frequency by 2.

2h = ÷ 3. Divide frequency by 3.

3h through 1Fh = Reserved, do not use.

Specifications

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4.8.4.3.4 PLL Controller Divider 3 Register

The PLL controller divider 3 register (PLLDIV3) is shown in Figure 4-19 and described in Table 4-28.

Figure 4-19. PLL Controller Divider 3 Register (PLLDIV3) (Address - 029A 015Ch)

31

30

14

29

13

28

12

27

11

26

10

25

9

24

Reserved

R-0

23

22

6

21

5

20

4

19

3

18

17

1

16

0

15

8

7

2

D3EN

R/W-1

Reserved

R-0

RATIO

R/W-2h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-28. PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions

Bit

31:16

15

Acronym

Reserved

D3EN

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

Divider 3 enable bit.

•

0 = Divider 3 is disabled. No clock output.

1 = Divider 3 is enabled.

14:5

4:0

Reserved

RATIO

Reserved. Read only. Always reads as 0. Writes have no effect.

0 through 1Fh are divider ratio bits:

•

0 = ÷ 1. Divide frequency by 1.

1h = ÷ 2. Divide frequency by 2.

2h = ÷ 3. Divide frequency by 3.

3h = ÷ 4. Divide frequency by 4.

4h through 1Fh = ÷ 5 to ÷ 32. Divide frequency by 5 to divide frequency by 32.

88

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4.8.4.3.5 PLL Controller Divider 6 Register

The PLL controller divider 6 register (PLLDIV6) is shown in Figure 4-20 and described in Table 4-29.

Figure 4-20. PLL Controller Divider 6 Register (PLLDIV6) Address - 029A 0168)

31

30

29

13

28

12

27

11

26

25

24

Reserved

R-0

23

22

6

21

5

20

4

19

3

18

17

1

16

0

15

14

10

9

8

7

2

D6EN

R/W-1

Reserved

RATIO

R-0

R/W-

9h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-29. PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions

Bit

31:16

15

Acronym

Reserved

D6EN

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

Divider 6 enable bit.

•

0 = Divider 6 is disabled. No clock output.

1 = Divider 6 is enabled.

14:5

4:0

Reserved

RATIO

Reserved. Read only. Always reads as 0. Writes have no effect.

0 through 1Fh are divider ratio bits:

•

0 = ÷ 1. Divide frequency by 1.

1h = ÷ 2. Divide frequency by 2.

2h = ÷ 3. Divide frequency by 3.

3h = ÷ 4. Divide frequency by 4.

4h through 1Fh = ÷ 5 to ÷ 32. Divide frequency by 5 to divide frequency by 32.

Specifications

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4.8.4.3.6 PLL Controller Divider 7 Register

The PLL controller divider 7 register (PLLDIV7) is shown in Figure 4-21 and described in Table 4-30.

Figure 4-21. PLL Controller Divider 7 Register (PLLDIV7) (Address - 029A 016Ch)

31

30

14

29

13

28

12

27

11

26

10

25

9

24

Reserved

R-0

23

22

6

21

5

20

4

19

3

18

17

1

16

0

15

8

7

2

D7EN

R/W-1

Reserved

R-0

RATIO

R/W-9h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-30. PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions

Bit

31:16

15

Acronym

Reserved

D7EN

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

Divider 7 enable bit.

•

0 = Divider 6 is disabled. No clock output.

1 = Divider 6 is enabled.

14:5

4:0

Reserved

RATIO

Reserved. Read only. Always reads as 0. Writes have no effect.

0 through 1Fh are divider ratio bits:

•

0 = ÷ 1. Divide frequency by 1.

1h = ÷ 2. Divide frequency by 2.

2h = ÷ 3. Divide frequency by 3.

3h = ÷ 4. Divide frequency by 4.

4h through 1Fh = ÷ 5 to ÷ 32. Divide frequency by 5 to divide frequency by 32.

90

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4.8.4.3.7 PLL Controller Divider 8 Register

The PLL controller divider 8 register (PLLDIV7) is shown in Figure 4-22 and described in Table 4-31.

Figure 4-22. PLL Controller Divider 8 Register (PLLDIV8) (Address - 029A 0170)

31

30

14

29

13

28

12

27

11

26

10

25

9

24

Reserved

R-0

23

22

6

21

5

20

4

19

3

18

17

1

16

0

15

8

7

2

D8EN

R/W-1

Reserved

R-0

RATIO

R/W-9h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-31. PLL Controller Divider 8 Register (PLLDIV8) Field Descriptions

Bit

31:16

15

Acronym

Reserved

D8EN

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

Divider 8 enable bit.

•

0 = Divider 6 is disabled. No clock output.

1 = Divider 6 is enabled.

14:5

4:0

Reserved

RATIO

Reserved. Read only. Always reads as 0. Writes have no effect.

0 through 1Fh are divider ratio bits:

•

0 = ÷ 1. Divide frequency by 1.

1h = ÷ 2. Divide frequency by 2.

2h = ÷ 3. Divide frequency by 3.

3h = ÷ 4. Divide frequency by 4.

4h through 1Fh = ÷ 5 to ÷ 32. Divide frequency by 5 to divide frequency by 32.

Specifications

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4.8.4.3.8 PLL Controller Command Register

The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is

shown in Figure 4-23 and described in Table 4-32.

Figure 4-23. PLL Controller Command Register (PLLCMD) (Address - 029A 0138h)

31

15

30

14

29

13

28

12

27

11

26

10

25

9

24

Reserved

R-0

23

22

6

21

5

20

4

19

3

18

2

17

1

16

8

7

0

Reserved

GOSE

T

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-32. PLL Controller Command Register (PLLCMD) Field Descriptions

Bit

31:2

1

Acronym

Reserved

GOSET

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

0

GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1 to initiate a

GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operations have

completed.

•

0 = No effect. Write of 0 clears bit to 0.

1 = Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further writes

of 1 can initiate the GO operation.

92

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4.8.4.3.9 PLL Controller Status Register

The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in

Figure 4-24 and described in Table 4-33.

Figure 4-24. PLL Controller Status Register (PLLSTAT) (Address - 029A 013C)

31

15

30

14

29

13

28

12

27

11

26

10

25

9

24

Reserved

R-0

23

22

6

21

5

20

4

19

3

18

2

17

1

16

8

7

0

Reserved

GOST

AT

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-33. PLL Controller Status Register (PLLSTAT) Field Descriptions

Bit

31:1

0

Acronym

Reserved

GOSTAT

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

GO operation status.

•

0 = GO operation is not in progress. SYSCLK divide ratios are not being changed.

1 = GO operation is in progress. SYSCLK divide ratios are being changed.

Specifications

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4.8.4.3.10 PLL Controller Clock Align Control Register

The PLL controller clock align control register (ALNCTL) is shown in Figure 4-25 and described in Table 4-

34.

Figure 4-25. PLL Controller Clock Align Control Register (ALNCTL) (Address - 029A 0140)

31

15

30

14

29

13

28

12

27

11

26

25

9

24

Reserved

R-0

23

22

6

21

5

20

19

18

2

17

16

0

10

Reserved

R-0

8

7

4

3

1

ALN5 ALN4

R-1 R-1

Reserved

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-34. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions

Bit

31:5

4:3

Acronym

Description

Reserved

Reserved. Read only. Always reads as 0. Writes have no effect.

SYSCLKn alignment. Do not change the default values of these fields.

ALNn

•

0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set to 1,

SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.

•

1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set. The

SYSCLKn ratio is set to the ratio programmed in the RATIO bit in PLLDIVn

2:0

Reserved

Reserved. Read only. Always reads as 0. Writes have no effect.

94

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4.8.4.3.11 PLLDIV Ratio Change Status Register

Whenever a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the PLLDIV

ratio change status registers (DCHANGE). During the GO operation, the PLL controller will change the

divide ratio of only the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be

automatically aligned to other clocks. The PLLDIV divider ratio change status register is shown in

Figure 4-26 and described in Table 4-35.

Figure 4-26. PLLDIV Divider Ratio Change Status Register (DCHANGE) (Address - 029A 0144)

31

15

30

14

29

13

28

12

27

11

26

25

9

24

Reserved

R-0

23

22

6

21

5

20

19

18

2

17

16

0

10

Reserved

R-0

8

7

4

3

1

SYS5 SYS4

R-0 R-0

Reserved

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-35. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions

Bit

31:5

4

Acronym

Description

Reserved

SYS5

Reserved. Read only. Always reads as 0. Writes have no effect.

•

Identifies when the SYSCLK5 divide ratio has been modified.

0 = SYSCLK5 ratio has not been modified. When GOSET is set, SYSCLK5 will not be affected.

1 = SYSCLK5 ratio has been modified. When GOSET is set, SYSCLK5 will change to the new ratio.

3

SYS4

•

Identifies when the SYSCLK4 divide ratio has been modified.

0 = SYSCLK4 ratio has not been modified. When GOSET is set, SYSCLK4 will not be affected.

1 = SYSCLK4 ratio has been modified. When GOSET is set, SYSCLK4 will change to the new ratio.

2:0

Reserved

Reserved. Read only. Always reads as 0. Writes have no effect.

Specifications

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4.8.4.3.12 SYSCLK Status Register

The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLKn). SYSTAT is

shown in Figure 4-27 and described in Table 4-36.

Figure 4-27. SYSCLK Status Register (SYSTAT) (Address - 029A 0150)

31

15

30

14

29

13

28

12

27

11

26

25

9

24

Reserved

R-0

23

22

6

21

5

20

19

18

17

16

10

8

7

4

3

2

1

0

Reserved

SYS5 SYS4 SYS3 SYS2

Rsvd

ON

R-0

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-36. SYSCLK Status Register (SYSTAT) Field Descriptions

Bit

31:4

4:1

Acronym

Reserved

SYSnON

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

SYSCLKn on status.

•

0 = SYSCLKn is gated.

1 = SYSCLKn is on.

0:

Reserved

Reserved. Read only. Always reads as 1. Writes have no effect.

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4.8.4.4 PLL1 Controller Input and Output Electrical Data/Timing

Table 4-37. CORECLK(N|P) and ALTCORECLK Timing Requirements⁽¹⁾

NO.

MIN

MAX UNIT

CORECLK(N|P) and ALTCORECLK

1

2

3

4

5

t_c(SYSCLK)

t_w(SYSCLKH)

t_w(SYSCLKL)

t_t(SYSCLK)

t_j(SYSCLK)

Cycle time, CORECLK(N|P) or ALTCORECLK

Pulse duration, CORECLK(N|P) or ALTCORECLK high

Pulse duration, CORECLK(N|P) or ALTCORECLK low

Transition time, CORECLK(N|P) or ALTCORECLK

Period Jitter (peak-to-peak), CORECLK(N|P) or ALTCORECLK

SYSCLKOUT

16.27

0.45 x C₁

50

20.00 ns

ns

1300 ps

100 ps

1

2

3

4

t_c(CKO)

Cycle time, SYSCLKOUT

10 x C₁

32 x C₁ns

t_w(CKOH)

t_w(CKOL)

t_t(CKO)

Pulse duration, SYSCLKOUT high

4 x C₁- 0.7 32 x C₁+ 0.7 ns

1.0 ns

Pulse duration, SYSCLKOUT low

Transition time, SYSCLKOUT

(1) If CORECLKSEL = 0, C₁= CORECLK(N|P) cycle time in ns. If CORECLKSEL = 1, C₁= ALTCORECLK cycle time in ns.

1

5

4

2

CORECLK(N|P)

3

4

Figure 4-28. CORECLK(N|P) and ALTCORECLK Timing

4.8.5 PLL2

The secondary PLL generates interface clocks for the DDR2 memory controller. Using the DDRCLKSEL

pin the user can select the input source of PLL2 as either the DDRREFCLK or the ALTDDRCLK clock

reference sources.

When coming out of power-on reset, PLL2 is enabled and initialized.

As shown in Figure 4-29, the PLL2 multiplier is fixed at a ×10 multiplier rate followed by a fixed /2 divider

resulting in an effective x5 multiplier going to the DDR2PHY and attached DDR2 memory.

DDR PLL

PLLOUT

DDR2

PHY

by 2

÷

DDRREFCLK(N|P)

ALTDDRCLK

x10

DDRCLKSEL

PLLV₂

EMI

DV_DD18

Filter

C1

C2

560 pF

0.01 µF

Figure 4-29. PLL2 Block Diagram

Specifications

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PLL2 power is supplied externally via the PLL2 power supply (PLLV₂). An external PLL filter circuit must

be added to PLLV₂as shown in Figure 4-29. The 1.8-V supply for the EMI filter must be from the same

1.8-V power plane supplying the I/O power-supply pin, DV_DD18. TI requires EMI filter manufacturer Murata

NFM18CC222R1C3 or NFM18CC223R1C3. For more information on the external PLL filter or the EMI

filter, see the TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide (SPRAAV7).

All PLL external components (capacitors and the EMI filter) should be placed as close to the C64x+ DSP

device as possible. For the best performance, TI requires that all the PLL external components be on a

single side of the board without jumpers, switches, or components other than the ones shown. For

reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external

components (capacitors and the EMI filter). The minimum CLKIN2 rise and fall times should also be

observed.

4.8.5.1 PLL2 Device-Specific Information

4.8.5.1.1 Internal Clocks and Maximum Operating Frequencies

As shown in Figure 4-29, the output of PLL2, PLLOUT, is divided by 2 and directly fed to the DDR2

memory controller. This clock is used by the DDR2 memory controller to generate DDR2CLKOUT(N|P)0

and DDR2CLKOUT(N|P)1. Note that, internally, the data bus interface of the DDR2 memory controller is

clocked by SYSCLK4 and PLL1 controller.

Note that there is a minimum and maximum operating frequency for DDRREFCLK and associated

DDR2CLKOUT(N|P)0 and DDR2CLKOUT(N|P)1. For the PLL clocks input and output frequency ranges,

see Table 4-38.

Table 4-38. PLL2 Clock Frequency Ranges

SIGNAL

MIN

40

MAX UNIT

66.67 MHz

333 MHz

DDRREFCLK (PLLEN = 1)

DDR2CLKOUT0(P|N) and DDR2CLKOUT1(P|N)

200

4.8.5.1.2 PLL2 Operating Modes

Unlike the PLL1 which can operate in by-pass and PLL mode, the PLL2 only operates in PLL mode. In

PLL mode, DDR2CLKOUT0(P|N) and DDR2CLKOUT1 (P|N) are generated by an effective x5 multiplier

consisting of the PLL2 fixed x10 multiplier followed by a /2 divider.

The PLL2 is affected by power-on reset. During power-on resets, the internal clocks of the PLL2 are

affected as described in Section 4.8.3.

PLL2 is unlocked only during the power-up sequence (see Section 4.8.3) and is locked by the time the

RESETSTAT pin goes high. It does not lose lock during any of the other reset

4.8.5.2 PLL2 Input Clock Electrical Data/Timing

Table 4-39. Timing Requirements for DDRREFCLK(N|P) and ALTDDRCLK⁽¹⁾

(see Figure 4-30)

NO.

1

MIN

15.00

MAX UNIT

25.00 ns

t_c(CLKIN2)

t_w(CLKIN2H)

t_w(CLKIN2L)

t_t(CLKIN2)

Cycle time, DDRREFCLK(N|P) or ALTDDRCLK

2

Pulse duration, DDRREFCLK(N|P) or ALTDDRCLK high

Pulse duration, DDRREFCLK(N|P) or ALTDDRCLK low

Transition time, DDRREFCLK(N|P) or ALTDDRCLK

Period jitter (peak-to-peak), DDRREFCLK(N|P) or ALTDDRCLK

0.45 × C₂

50

0.55 × C₂ns

1300 ps

3

4

5

t_J(CLKIN2)

0.02 ×

tc_(CLKIN2)

(1) If DDRCLKSEL = 0, C₂= DDRREFCLK(N|P) cycle time in ns. If DDRCLKSEL = 1, C₂= ALTDDRCLK cycle time in ns.

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1

5

4

2

DDRREFCLK(N|P)

3

4

Figure 4-30. DDRREFCLK(N|P) Timing

4.8.6 DDR2 Memory Controller

The 32-bit DDR2 Memory Controller bus of the C6457 is used to interface to JESD79-2B standard-

compliant DDR2 SDRAM devices. The DDR2 external bus interfaces only to DDR2 SDRAM devices; it

does not share the bus with any other types of peripherals. The decoupling of DDR2 memories from other

devices both simplifies board design and provides I/O concurrency from a second external memory

interface, EMIFA.

The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum

throughput of the DDR2 bus. The clock frequency of the DDR2 bus is equal to the CLKIN2 frequency

multiplied by 10. The internal data bus clock frequency of the DDR2 Memory Controller is fixed at a divide-

by-three ratio of the CPU frequency. The maximum DDR2 throughput is determined by the smaller of the

two bus frequencies. The DDR2 bus is designed to sustain a throughput of up to 2.67 Gbyte/sec at a 667-

MHz data rate (333-MHz clock rate) as long as data requests are pending in the DDR2 Memory

Controller.

4.8.6.1 DDR2 Memory Controller Device-Specific Information

The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces

such as EMIF, McBSP, and HPI. For these other interfaces, the device timing was specified in terms of

data manual specifications and I/O buffer information specification (IBIS) models.

For the C6457 DDR2 memory bus, the approach is to specify compatible DDR2 devices and provide the

printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has

performed the simulation and system characterization to ensure all DDR2 interface timings in this solution

are met. The complete DDR2 system solution is documented in the TMS320C6457 DDR2 Implementation

Guidelines application report (SPRAB21).

TI supports only designs that follow the board design guidelines outlined in the application report.

The DDR2 memory controller on the C6457 device supports the following memory topologies:

•

A 32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices.

A 16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device.

A race condition may exist when certain masters write data to the DDR2 memory controller. For example,

if master A passes a software message via a buffer in external memory and does not wait for indication

that the write completes, when master B attempts to read the software message, then the master B read

may bypass the master A write and, thus, master B may read stale data and, therefore, receive an

incorrect message.

Specifications

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Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete

before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have

a hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

1. Perform the required write.

2. Perform a dummy write to the DDR2 memory controller module ID and revision register.

3. Perform a dummy read to the DDR2 memory controller module ID and revision register.

4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The

completion of the read in step 3 ensures that the previous write was done.

4.8.6.2 DDR2 Memory Controller Peripheral Register Description(s)

Table 4-40. DDR2 Memory Controller Registers

HEX ADDRESS RANGE

7800 0000

ACRONYM

REGISTER NAME

MIDR

DDR2 Memory Controller Module and Revision Register

DDR2 Memory Controller Status Register

DDR2 Memory Controller SDRAM Configuration Register

DDR2 Memory Controller SDRAM Refresh Control Register

DDR2 Memory Controller SDRAM Timing 1 Register

DDR2 Memory Controller SDRAM Timing 2 Register

Reserved

7800 0004

DMCSTAT

7800 0008

SDCFG

7800 000C

SDRFC

7800 0010

SDTIM1

7800 0014

SDTIM2

7800 0018

-

7800 0020

BPRIO

DDR2 Memory Controller Burst Priority Register

Reserved

7800 0024 - 7800 004C

7800 0050 - 7800 0078

7800 007C - 7800 00BC

7800 00C0 - 7800 00E0

7800 00E4

-

Reserved

-

Reserved

-

Reserved

DMCCTL

-

DDR2 Memory Controller Control Register

Reserved

7800 00E8 - 7FFF FFFF

4.8.6.3 DDR2 Memory Controller Electrical Data/Timing

The TMS320C6457 DDR2 Implementation Guidelines application report (SPRAB21) specifies a complete

DDR2 interface solution for the C6457 as well as a list of compatible DDR2 devices. TI has performed the

simulation and system characterization to ensure all DDR2 interface timings in this solution are met;

therefore, no electrical data/timing information is supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application

report.

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4.8.7 External Memory Interface A (EMIFA)

The EMIFA can interface to a variety of external devices or ASICs, including:

•

Pipelined and flow-through synchronous-burst SRAM (SBSRAM)

ZBT (zero bus turnaround) SRAM and late write SRAM

Synchronous FIFOs

Asynchronous memory, including SRAM, ROM, and Flash

For more information about the EMIF peripheral, see the TMS320C6457 DSP External Memory Interface

(EMIF) User's Guide (SPRUGK2).

4.8.7.1 EMIFA Device-Specific Information

Timing analysis must be done to verify all AC timings are met. TI recommends using I/O buffer information

specification (IBIS) to analyze all AC timings.

To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS

Models for Timing Analysis application report (SPRA839).

To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines

(for the EMIF output signals, see Table 3-2).

A race condition may exist when certain masters write data to the EMIFA. For example, if master A

passes a software message via a buffer in external memory and does not wait for indication that the write

completes, when master B attempts to read the software message, then the master B read may bypass

the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.

Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete

before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have

a hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

1. Perform the required write.

2. Perform a dummy write to the EMIFA module ID and revision register.

3. Perform a dummy read to the EMIFA module ID and revision register.

4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The

completion of the read in step 3 ensures that the previous write was done.

Specifications

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4.8.7.2 EMIFA Peripheral Register Description(s)

Table 4-41. EMIFA Registers

HEX ADDRESS RANGE

7000 0000

ACRONYM

REGISTER NAME

MIDR

Module ID and Revision Register

Status Register

7000 0004

STAT

7000 0008

-

Reserved

7000 000C - 7000 001C

7000 0020

-

Reserved

BURST_PRIO

Burst Priority Register

Reserved

7000 0024 - 7000 004C

7000 0050 - 7000 007C

7000 0080

-

CE2CFG

CE3CFG

CE4CFG

CE5CFG

-

Reserved

EMIFA CE2 Configuration Register

EMIFA CE3 Configuration Register

EMIFA CE4 Configuration Register

EMIFA CE5 Configuration Register

Reserved

7000 0084

7000 0088

7000 008C

7000 0090 - 7000 009C

7000 00A0

AWCC

-

EMIFA Async Wait Cycle Configuration Register

Reserved

7000 00A4 - 7000 00BC

7000 00C0

INTRAW

INTMSK

INTMSKSET

INTMSKCLR

-

EMIFA Interrupt RAW Register

EMIFA Interrupt Masked Register

EMIFA Interrupt Mask Set Register

EMIFA Interrupt Mask Clear Register

Reserved

7000 00C4

7000 00C8

7000 00CC

7000 00D0 - 7000 00DC

7000 00E0 - 77FF FFFF

-

Reserved

4.8.7.3 EMIFA Electrical Data/Timing

This section describes the electrical timing for the EMIFA peripheral.

4.8.7.3.1 AECLKIN and AECLKOUT Timing

Table 4-42. EMIFA AECLKIN Timing Requirements⁽¹⁾⁽²⁾

(see Figure 4-31)

NO.

MIN

10⁽³⁾

2.7

MAX UNIT

1

2

3

4

5

t_c(EKI)

t_w(EKIH)

t_w(EKIL)

t_t(EKI)

Cycle time, AECLKIN

40 ns

ns

Pulse duration, AECLKIN high

Pulse duration, AECLKIN low

Transition time, AECLKIN

Period Jitter, AECLKIN

2.7

ns

2

ns

t_j(EKI)

0.02E⁽⁴⁾ns

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

(2) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

(3) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times

are based on internal logic speed; the maximum usable speed of the EMIF may be lower due to AC timing requirements.

(4) This timing applies only when AECLKIN is used for EMIFA.

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1

5

4

2

AECLKIN

3

4

Figure 4-31. EMIFA AECLKIN Timing

Table 4-43. EMIFA AECLKOUT Switching Characteristics^(1)(2)(3)(4)

(see Figure 4-32)

NO.

PARAMETER

MIN

E - 0.7

MAX UNIT

E + 0.7 ns

1

2

3

4

5

6

t_c(EKO)

Cycle time, AECLKOUT

t_w(EKOH)

t_w(EKOL)

Pulse duration, AECLKOUT high

Pulse duration, AECLKOUT low

Transition time, AECLKOUT

EH - 0.7

EL - 0.7

EH + 0.7 ns

EL + 0.7 ns

t_t(EKO)

1

8

ns

t_d(EKIH-EKOH)

t_d(EKIL-EKOL)

Delay time, AECLKIN high to AECLKOUT high

Delay time, AECLKIN low to AECLKOUT low

1

(1) Over Recommended Operating Conditions.

(2) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

(3) The reference points for the rise and fall transitions are measured at V_OLMAX and V_OHMIN.

(4) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.

AECLKIN

1

6

4

5

2

3

4

AECLKOUT1

Figure 4-32. EMIFA AECLKOUT Timing

Specifications

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4.8.7.3.2 Asynchronous Memory Timing

This section describes the asynchronous EMIFA Read, Write, EM_WAIT Read and EM_WAIT Write timing

requirements and switching characteristics.

Table 4-44. EMIFA Asynchronous Memory Read Switching Characteristics⁽¹⁾⁽²⁾

(see Figure 4-33)

NO.

PARAMETER

MIN

(RS + RST + RH (RS + RST + RH

+ 3) × E - 1 + 3) × E + 1

(RS + RST + RH (RS + RST + RH

MAX UNIT

EMIF read cycle time when ew = 0. Meaning not in extended wait

mode

ns

3

t_c(ACEL-read)

EMIF read cycle time when ew = 1. Meaning extended wait mode

enabled

+ 3) × E - 1

+ 3) × E + 1

Output setup time from ACEn low to AAOE/ASOE low. SS = 0, not in

select strobe mode

t_osu(ACEL-

AAOEL)

4

5

(RS+1) × E-1.5

ns

Output setup time from ACEn low to AAOE/ASOE low. SS = 1, in

select strobe mode

Output hold time from AAOE/ASOE high to ACEn high. SS = 0, not in

select strobe mode

t_oh(AAOEH-

ACEH)

(RS+1) × E-1.9

Output hold time from AAOE/ASOE high to ACEn high. SS = 1, in

select strobe mode

6

7

t_osu(ABAV-

AAOEL)

Output setup time from ABA valid to AAOE/ASOE low

(RS+1) × E-1.5

(RS+1) × E-1.9

ns

Output hold time from AAOE/ASOE high to BA invalid

toh(AAOEH-

ABAV)

8

9

t_{osu(AEAV-OEL)}Output setup time from AEA valid to AAOE/ASOE low

(RS+1) × E-1.5

(RS+1) × E-1.9

ns

t_oh(AAOEH-

Output hold time from AAOE/ASOE high to AEA invalid

AEAV)

AAOE/ASOE active time low, when ew = 0, extended wait mode is

disabled

10 t_w(AAOEL)

(RST+1) × E - 6

(RST+1) × E + 6 ns

AAOE/ASOE active time low, when ew = 1, extended wait mode is

enabled

(1) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

(2) RS, RST, RH, WS, WST, WH, and TA are all based on the memory mapped register values. This means that the actual value listed

here is the value in EMIF cycles - 1.

Example: For read setup of 1 EMIF cycle, RS = 0.

Table 4-45. EMIFA Asynchronous Memory Read Timing Requirements

(see Figure 4-33)

NO.

MIN

MAX UNIT

12 t_su(AEDV-

Input setup time from AED valid to AAOE/ASOE high

6.5

ns

AAOEH)

13 t_{h(AAOEH-AEDV)}Input hold time from AAOE/ASOE high to AED invalid

0

ns

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1

3

ACE[5:2]

AR/W

ABA[1:0]

AEA[19:0]

4

6

8

5

7

9

10

AAOE

12

13

AED[63:0]

AAWE

Figure 4-33. EMIFA Asynchronous Memory Read Timing

Table 4-46. EMIFA Asynchronous Memory Write Timing Requirements⁽¹⁾⁽²⁾

(see Figure 4-34)

NO.

MIN

MAX UNIT

(WS + WST

WH + TA + 4) + WH + TA + ns

EMIF write cycle time when ew = 0, extended wait mode

(WS + WST +

15 t_{c(ACEL-write)}

EMIF write cycle time when ew = 1, extended wait mode is enabled.

× E - 1

4) × E + 1

Output setup time from ACEn low to ASWE/AAWE low. SS = 0, not in select

strobe mode

t_osu(ACEL-

AAWEL)

(WS+1) × E-

1.7

16

ns

Output setup time from ACEn low to ASWE/AAWE low. SS = 1, in select

strobe mode

Output hold time from ASWE/AAWE high to ACEn high. SS = 0, not in select

strobe mode

t_oh(AAWEH-

ACEH)

(WS+1) × E-

1.8

17

Output hold time from ASWE/AAWE high to ACEn high. SS = 1, in select

strobe mode

Output setup time from AR/W valid to ASWE/AAWE low

Output hold time from ASWE/AAWE high to AR/W invalid

Output setup time from BA valid to ASWE/AAWE low

Output hold time from ASWE/AAWE high to ABA invalid

Output setup time from AEA valid to ASWE/AAWE low

Output hold time from ASWE/AAWE high to AEA invalid

(WS+1) × E-

1.7

18 t_{osu(WV-AAWEL)}

19 t_{oh(AAWEH-WIV)}

t_osu(ABAV-

ns

(WS+1) × E-

1.8

(WS+1) × E-

1.7

20

21

22

23

AAWEL)

t_oh(AAWEH-

ABAIV)

(WS+1) × E-

1.8

t_osu(AEAV-

AAWEL)

(WS+1) × E-

1.7

t_oh(AAWEH-

AEAIV)

(WS+1) × E-

1.8

ASWE/AAWE active time low, when ew = 0. Extended wait mode is disabled.

ASWE/AAWE active time low, when ew = 1. Extended wait mode is enabled.

Output setup time from AED valid to ASWE/AAWE low

(WST+1) × E -

5.8

24 t_w(AAWEL)

ns

t_osu(AEDV-

(WS+1) × E-

5.0

26

27

ns

AAWEL)

t_oh(AAWEH-

Output hold time from ASWE/AAWE high to AED invalid

(WS+1) × E-

2.5

AEDIV)

(1) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

(2) RS, RST, RH, WS, WST, WH, and TA are all based on the memory mapped register values. This means that the actual value listed

here is the value in EMIF cycles - 1.

Example: For read setup of 1 EMIF cycle, RS = 0.

Specifications

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1

15

ACE[5:2]

AR/W

ABA[1:0]

AEA[19:0]

16

18

20

22

17

19

21

23

24

AAWE

26

27

AED[63:0]

AAOE

Figure 4-34. EMIFA Asynchronous Memory Write Timing

Table 4-47. EMIFA EM_Wait Read Timing Requirements⁽¹⁾

(see Figure 4-35)

NO.

MIN

MAX UNIT

2E

2

t_w(AARDY)

Pulse duration, AARDY assertion and deassertion minimum time

Setup time, AARDY asserted before AAOE high

14 t_{d(AARDY-AAOEH)}

4E + 6

(1) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

Table 4-48. EMIFA EM_Wait Read Switching Characteristics⁽¹⁾

(see Figure 4-35)

NO.

PARAMETER

MIN

MAX UNIT

11 t_{d(AARDYH-AAOEH)}

Delay time from AARDY deasserted to AAOE/ASOE high

4E + 6

(1) E = the EMIF input clock (AECLKIN or SYSCLK7) period in ns for EMIFA.

Setup

Strobe

Extended Due to EM_WAIT

Strobe

Hold

ACE[5:2]

ABA[1:0]

AEA[19:0]

AED[63:0]

AAOE

14

11

2

Deasserted

Asserted

AARDY

Figure 4-35. EMIFA EM_Wait Read Timing

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Table 4-49. EMIFA EM_Wait Write Timing Requirements

(see Figure 4-36)

NO.

MIN

Pulse duration, AARDY assertion and deassertion minimum time

Delay time from AARDY deasserted to ASWE/AAWE high

MAX

UNIT

2

t_w(AARDY)

2E

25 t_d(AARDYH-

AAWEH)

4E + 6.0

28 t_su(AARDY-

AAWEH)

Setup time, AARDY asserted before ASWE/AAWE high

Setup

Strobe

Extended Due to EM_WAIT

Strobe

Hold

ACE[5:2]

ABA[1:0]

AEA[19:0]

AED[63:0]

AAWE

28

25

2

Deasserted

Asserted

AARDY

Figure 4-36. EMIFA EM_Wait Write Timing

4.8.7.3.3 Programmable Synchronous Interface Timing

This section describes the synchronous EMIFA Read and Write timing requirements.

The following parameters are programmable via the EMIFA CE Configuration registers (CEnCFG) (see

Table 4-51) and via the EMIFA Chip Select n Configuration Register (CESECn):

•

Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency

Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes

inactive after the final command has been issued (CE_EXT = 0). For synchronous FIFO interface,

ACEx is active when ASOE is active (CE_EXT = 1).

•

Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface,

ASADS/ASRE acts as ASADS with deselect cycles (R_ENABLE = 0). For FIFO interface,

ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1).

Figure 4-37, Figure 4-38, and Figure 4-39 are given as examples diagrams depicting some of the

programmable options.

•

In Figure 4-37, R_LTNCY = 2, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

In Figure 4-38, W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

In Figure 4-39, W_LTNCY = 1, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

Table 4-50. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module

(see Figure 4-37)

NO.

6

MIN

2

MAX UNIT

t_su(EDV-EKOH)

t_h(EKOH-EDV)

Setup time, read AEDx valid before AECLKOUT high

Hold time, read AEDx valid after AECLKOUT high

ns

7

1.5

Specifications

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Table 4-51. Switching Characteristics for Programmable Synchronous Interface Cycles for EMIFA

Module⁽¹⁾

(see Figure 4-37, Figure 4-38, and Figure 4-39)

NO.

1

PARAMETER

MIN

MAX UNIT

4.9 ns

ns

t_d(EKOH-CEV)

t_d(EKOH-BEV)

t_d(EKOH-BEIV)

t_d(EKOH-EAV)

t_d(EKOH-EAIV)

t_d(EKOH-ADSV)

t_d(EKOH-OEV)

Delay time, AECLKOUT high to ACEx valid

Delay time, AECLKOUT high to ABEx valid

Delay time, AECLKOUT high to ABEx invalid

Delay time, AECLKOUT high to AEAx valid

Delay time, AECLKOUT high to AEAx invalid

Delay time, AECLKOUT high to ASADS/ASRE valid

Delay time, AECLKOUT high to ASOE valid

Delay time, AECLKOUT high to AEDx valid

Delay time, AECLKOUT high to AEDx invalid

Delay time, AECLKOUT high to ASWE valid

1.3

2

3

1.3

4

4.9 ns

ns

5

1.3

8

4.9 ns

5.2 ns

ns

9

10 t_d(EKOH-EDV)

11 t_d(EKOH-EDIV)

12 t_d(EKOH-WEV)

1.3

4.9 ns

(1) Over recommended operating conditions.

READ latency = 2

AECLKOUT

1

2

1

3

5

ACEx

ABE[7:0]

BE1

BE2

BE3

BE4

4

AEA[19:0]/ABA[1:0]

AED[63:0]

EA1

EA2

EA3

EA4

7

6

Q1

Q2

Q3

Q4

8

9

8

(B)

ASADS/ASRE

9

(B)

AAOE/ASOE

(B)

AAWE/ASWE

Figure 4-37. EMIFA Programmable Synchronous Interface Read Timing (With Read Latency = 2)^(A)

(A) In this figure R_LTNCY = 2, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

(B) AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

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Write Latency = 1

AECLKOUT

1

3

ACEx

2

BE1

BE2

EA2

BE3

EA3

Q2

BE4

ABE[7:0]

5

4

AEA[19:0]/ABA[1:0]

AED[63:0]

EA1

10

EA4

Q3

10

11

8

Q1

Q4

8

(B)

ASADS/ASRE

(B)

AAOE/ASOE

12

(B)

AAWE/ASWE

Figure 4-38. EMIFA Programmable Synchronous Interface Write Timing (With Write Latency = 0)^(A)

(A) In this figure W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

(B) AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

Write Latency = 1

AECLKOUT

1

3

ACEx

2

BE1

BE2

EA2

BE3

EA3

Q2

BE4

EA4

Q3

ABE[7:0]

5

4

AEA[19:0]/ABA[1:0]

AED[63:0]

EA1

10

11

8

Q1

Q4

8

(B)

ASADS/ASRE

(B)

AAOE/ASOE

12

(B)

AAWE/ASWE

Figure 4-39. EMIFA Programmable Synchronous Interface Write Timing (With Write Latency = 1)^(A)

(A) In this figure W_LTNCY = 1, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

(B) AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

Specifications

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4.8.8 I²C Peripheral

The inter-integrated circuit (I²C) module provides an interface between a C64x+ DSP and other devices

compliant with Philips Semiconductors Inter-IC bus (I²C bus) specification version 2.1 and connected by

way of an I²C bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit

data to/from the DSP through the I²C module.

4.8.8.1 I²C Device-Specific Information

The C6457 device includes an I²C peripheral module. NOTE: when using the I²C module, ensure there

are external pullup resistors on the SDA and SCL pins.

The I²C modules on the C6457 may be used by the DSP to control local peripheral ICs (DACs, ADCs,

etc.) or may be used to communicate with other controllers in a system or to implement a user interface.

The I²C port supports:

•

Compatible with Philips I²C specification revision 2.1 (January 2000)

Fast mode up to 400 Kbps (no fail-safe I/O buffers)

Noise filter to remove noise 50 ns or less

7-bit and 10-bit device addressing modes

Multi-master (transmit/receive) and slave (transmit/receive) functionality

Events: DMA, interrupt, or polling

Slew-rate limited open-drain output buffers

Figure 4-40 shows a block diagram of the I²C module.

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I²C Module

Clock

Prescale

Peripheral Clock

(CPU/6)

I²CPSC

Control

Bit Clock

Generator

Own

Address

I²COAR

I²CSAR

I²CMDR

I²CCNT

I²CEMDR

SCL

Noise

Filter

I²C Clock

I²CCLKH

I²CCLKL

Slave

Address

Mode

Data

Count

Transmit

I²CXSR

Transmit

Shift

Extended

Mode

Transmit

Buffer

I²CDXR

SDA

Interrupt/DMA

I²CIMR

Noise

Filter

I²C Data

Interrupt

Mask/Status

Receive

I²CDRR

Receive

Buffer

Interrupt

Status

I²CSTR

Interrupt

Vector

I²CRSR

I²CIVR

Receive

Shift

Shading denotes control/status registers.

Figure 4-40. I²C Module Block Diagram

Specifications

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4.8.8.2 I²C Peripheral Register Description(s)

Table 4-52. I²C Registers

HEX ADDRESS RANGE

02B0 4000

ACRONYM

ICOAR

ICIMR

ICSTR

ICCLKL

ICCLKH

ICCNT

ICDRR

ICSAR

ICDXR

ICMDR

ICIVR

ICEMDR

ICPSC

ICPID1

ICPID2

-

REGISTER NAME

I²C own address register

I²C interrupt mask/status register

I²C interrupt status register

I²C clock low-time divider register

I²C clock high-time divider register

I²C data count register

02B0 4004

02B0 4008

02B0 400C

02B0 4010

02B0 4014

02B0 4018

I²C data receive register

02B0 401C

I²C slave address register

I²C data transmit register

I²C mode register

I²C interrupt vector register

I²C extended mode register

I²C prescaler register

I²C peripheral identification register 1 [Value: 0x0000 0105]

I²C peripheral identification register 2 [Value: 0x0000 0005]

Reserved

02B0 4020

02B0 4024

02B0 4028

02B0 402C

02B0 4030

02B0 4034

02B0 4038

02B0 403C - 02B0 405C

02B0 4060 - 02B3 407F

02B0 4080 - 02B3 FFFF

-

Reserved

-

Reserved

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4.8.8.3 I²C Electrical Data/Timing

4.8.8.3.1 Inter-Integrated Circuits (I²C) Timing

Table 4-53. I²C Timing Requirements⁽¹⁾

(see Figure 4-41)

STANDARD MODE

FAST MODE

NO.

MIN

MAX

MIN

MAX UNIT

1

2

t_c(SCL)

Cycle time, SCL

10

2.5

us

Setup time, SCL high before SDA low (for a repeated START

condition)

t_{su(SCLH-SDAL)}

4.7

4

0.6

us

3

Hold time, SCL low after SDA low (for a START and a

repeated START condition)

t_h(SDAL-SCLL)

4

5

6

7

8

t_w(SCLL)

t_w(SCLH)

Pulse duration, SCL low

Pulse duration, SCL high

4.7

4

1.3

0.6

100⁽²⁾

0⁽³⁾

us

ns

t_{su(SDAV-SCLH)}Setup time, SDA valid before SCL high

t_h(SCLL-SDAV)

Hold time, SDA valid after SCL low (For I²C bus devices)

250

0⁽³⁾

3.45

0.9⁽⁴⁾

us

Pulse duration, SDA high between STOP and START

conditions

t_w(SDAH)

4.7

1.3

us

9

Rise time, SDA

Rise time, SCL

Fall time, SDA

Fall time, SCL

20 +

0.1C_b

t_r(SDA)

t_r(SCL)

t_f(SDA)

t_f(SCL)

1000

300

ns

(5)

10

11

12

20 +

(5)

0.1C_b

20 +

(5)

0.1C_b

20 +

300

(5)

0.1C_b

13 t_{su(SCLH-SDAH)}Setup time, SCL high before SDA high (for STOP condition)

4

0.6

0

us

ns

pF

14 t_w(SP)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

50

(5)

15 C_b

400

(1) The I²C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down

(2) A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then

be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line t_rmax + t_su(SDA-SCLH)= 1000 + 250 = 1250 ns

(according to the Standard-mode I²C-Bus Specification) before the SCL line is released.

(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHminof the SCL signal) to bridge the

undefined region of the falling edge of SCL.

(4) The maximum t_h(SDA-SCLL)has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.

(5) C_b= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

11

9

SDA

SCL

6

8

14

4

13

5

10

1

12

3

2

7

3

Stop

Start

Repeated

Start

Stop

Figure 4-41. I²C Receive Timing

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Table 4-54. I²C Switching Characteristics⁽¹⁾

(see Figure 4-42)

STANDARD MODE

FAST MODE

UNIT

NO.

PARAMETER

Cycle time, SCL

MIN

MAX

MIN

MAX

S

16 t_c(SCL)

10

2.5

ms

Setup time, SCL high to SDA low (for a repeated START

condition)

17 t_{su(SCLH-SDAL)}

4.7

4

0.6

ms

Hold time, SDA low after SCL low (for a START and a

repeated START condition)

18 t_h(SDAL-SCLL)

19 t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

ms

ns

20 t_w(SCLH)

Pulse duration, SCL high

21 t_d(SDAV-SDLH)

22 t_v(SDLL-SDAV)

Delay time, SDA valid to SCL high

Valid time, SDA valid after SCL low (For I²C bus devices)

250

0

0.9 ms

Pulse duration, SDA high between STOP and START

conditions

23 t_w(SDAH)

4.7

1.3

ms

(1)

24 t_r(SDA)

25 t_r(SCL)

26 t_f(SDA)

27 t_f(SCL)

Rise time, SDA

Rise time, SCL

Fall time, SDA

Fall time, SCL

1000

300

20 + 0.1C_b

300 ns

ms

(1)

20 + 0.1C_b

300

28 t_d(SCLH-SDAH)Delay time, SCL high to SDA high (for STOP condition)

29 C_p

Capacitance for each I²C pin

4

0.6

10

10 pF

(1) C_b= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

26

24

SDA

21

23

19

28

20

25

SCL

16

27

18

17

22

18

Stop

Start

Repeated

Start

Stop

Figure 4-42. I²C Transmit Timing

114

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4.8.9 Host-Port Interface (HPI) Peripheral

4.8.9.1 HPI Device-Specific Information

The C6457 device includes a user-configurable 16-bit or 32-bit Host-port interface (HPI16/HPI32). The

HPIWIDTH pin allows the user configuration of the HPI as a 16-bit or 32-bit peripheral.

Table 4-55. HPIWIDTH Selection

CONFIGURATION PIN SETTING

HPIWIDTH

PERIPHERAL FUNCTION SELECTED

HPI DATA LOWER

HPI DATA UPPER

Hi-Z

0 (default is HPI16 mode)

1 (HPI32 mode)

Enabled

Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the

C6457.

An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the

EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA

channel 0.

4.8.9.2 HPI Peripheral Register Description(s)

Table 4-56. HPI Control Registers

HEX ADDRESS

RANGE

ACRONYM

REGISTER NAME

COMMENTS

0288 0000

-

Reserved

The CPU has read/write access to the

HPI power and emulation management register PWREMU_MGMT register; the Host does not

have any access to this register.

PWREMU

_MGMT

0288 0004

0288 0008 -

0288 0024

-

Reserved

0288 0028

0288 002C

-

Reserved

The Host and the CPU have read/write

0288 0030

HPIC

HPI control register

access to the HPIC register.⁽¹⁾

HPIA

The Host has read/write access to the HPIA

registers. The CPU has only read access to

the HPIA registers.

0288 0034

0288 0038

(HPIAW)⁽²⁾

HPI address register (Write)

HPIA (HPIAR)⁽²⁾HPI address register (Read)

0288 000C -

028B 007F

-

Reserved

0288 0080 -

028B FFFF

(1) The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an

interrupt from the host.

(2) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that

HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the

perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes,

see the TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

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4.8.9.3 HPI Electrical Data/Timing

Table 4-57. Host-Port Interface Timing Requirements⁽¹⁾⁽²⁾

(see Table 4-58 and see Figure 4-43, Figure 4-44, Figure 4-45, Figure 4-46, Figure 4-47, Figure 4-48, Figure 4-49, and

Figure 4-50)

NO.

MIN

5

MAX UNIT

9

t_{su(HASL-HSTBL)}

Setup time, HAS low before HSTROBE low

Hold time, HAS low after HSTROBE low

Setup time, select signals⁽³⁾valid before HAS low

Hold time, select signals⁽³⁾valid after HAS low

Pulse duration, HSTROBE low

ns

10 t_{h(HSTBL-HASL)}

11 t_{su(SELV-HASL)}

12 t_h(HASL-SELV)

13 t_w(HSTBL)

2

5

15

2M

5

14 t_w(HSTBH)

Pulse duration, HSTROBE high between consecutive accesses

Setup time, select signals⁽³⁾valid before HSTROBE low

Hold time, select signals⁽³⁾valid after HSTROBE low

Setup time, host data valid before HSTROBE high

Hold time, host data valid after HSTROBE high

Setup time, HCS low before HSTROBE low

15 t_{su(SELV-HSTBL)}

16 t_{h(HSTBL-SELV)}

17 t_{su(HDV-HSTBH)}

18 t_h(HSTBH-HDV)

37 t_{su(HCSL-HSTBL)}

5

1

0

Hold time, HSTROBE low after HRDY low. HSTROBE should not be

inactivated until HRDY is active (low); otherwise, HPI writes will not

complete properly.

38 t_{h(HRDYL-HSTBL)}

1.1

ns

(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(2) M = SYSCLK5 period = 6 ÷ CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.

(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.

Table 4-58. Host-Port Interface Switching Characteristics⁽¹⁾⁽²⁾

(see Table 4-57 and see Figure 4-43, Figure 4-44, Figure 4-45, Figure 4-46, Figure 4-47, Figure 4-48, Figure 4-49, and

Figure 4-50)

NO. PARAMETER

MIN

MAX UNIT

Case 1. HPIC or HPIA read

1

15

Case 2. HPID read with no auto-increment⁽³⁾

9 × M + 20

Delay time, HSTROBE low to DSP

data valid

Case 3. HPID read with auto-increment and

read FIFO initially empty⁽³⁾

1

t_d(HSTBL-HDV)

ns

9 × M + 20

Case 4. HPID read with auto-increment and

data previously prefetched into the read FIFO

1

15

4

t_dis(HSTBH-

HDV)

2

3

4

Disable time, HD high-impedance from HSTROBE high

1

3

ns

t_en(HSTBL-HD)Enable time, HD driven from HSTROBE low

15 ns

12 ns

t_d(HSTBL-

HRDYH)

Delay time, HSTROBE low to HRDY high

t_d(HSTBH-

HRDYH)

5

6

Delay time, HSTROBE high to HRDY high

12 ns

Case 1. HPID read with no auto-increment⁽³⁾

10 × M + 20

t_d(HSTBL-

HRDYL)

Delay time, HSTROBE low to HRDY

low

ns

Case 2. HPID read with auto-increment and

read FIFO initially empty⁽³⁾

10 × M + 20

t_d(HDV-

HRDYL)

7

Delay time, HD valid to HRDY low

0

ns

Case 1. HPIA write⁽³⁾

Case 2. HPID write with no auto-increment⁽³⁾

5 × M + 20

t_d(HSTBH-

HRDYL)

Delay time, HSTROBE high to

HRDY low

34

t_d(HSTBL-

HRDYL)

35

36

Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not empty⁽³⁾

40 × M + 20 ns

12 ns

t_d(HASL-

HRDYH)

Delay time, HAS low to HRDY high

(1) M = SYSCLK5 period = 6 ÷ CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.

(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3) Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.

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HCS

HAS

HCNTL[1:0]

HR/W

HHWIL

13

16

13

16

15

37

14

(A)

HSTROBE

3

1

2

HD[15:0]

38

4

7

6

(B)

HRDY

Figure 4-43. HPI16 Read Timing (HAS Not Used, Tied High)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(B) Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and

the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the

TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

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HCS

HAS

12

11

12

11

HCNTL[1:0]

12

11

12

11

HR/W

12

11

12

11

HHWIL

10

9

10

9

37

13

37

14

(A)

HSTROBE

1

3

1

3

2

HD[15:0]

7

38

36

6

(B)

HRDY

Figure 4-44. HPI16 Read Timing (HAS Used)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(B) Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and

the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the

TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

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HCS

HAS

HCNTL[1:0]

HR/W

HHWIL

16

13

16

15

13

37

15

37

14

(A)

HSTROBE

18

17

HD[15:0]

34

38

4

34

5

35

5

(B)

HRDY

Figure 4-45. HPI16 Write Timing (HAS Not Used, Tied High)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(B) Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and

the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the

TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

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HCS

HAS

12

11

12

11

HCNTL[1:0]

12

11

12

11

HR/W

12

11

12

11

14

HHWIL

9

10

9

37

13

(A)

HSTROBE

13

18

17

HD[15:0]

34

35

34

5

36

5

38

(B)

HRDY

Figure 4-46. HPI16 Write Timing (HAS Used)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(B) Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and

the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the

TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

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HAS (input)

16

15

HCNTL[1:0] (input)

HR/W (input)

13

(A)

HSTROBE (input)

37

HCS (input)

1

2

3

HD[31:0] (output)

38

7

6

4

(B)

HRDY (output)

Figure 4-47. HPI32 Read Timing (HAS Not Used, Tied High)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(B) Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and

the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the

TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

(C) The timing t_w(HSTBH), HSTROBE high pulse duration, must be met between consecutive HPI accesses in HPI32 mode.

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10

HAS (input)

12

11

HCNTL[1:0] (input)

HR/W (input)

9

13

(A)

HSTROBE (input)

37

HCS (input)

1

2

3

HD[31:0] (output)

7

38

6

36

(B)

HRDY (output)

Figure 4-48. HPI32 Read Timing (HAS Used)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(B) Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and

the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the

TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

(C) The timing t_w(HSTBH), HSTROBE high pulse duration, must be met between consecutive HPI accesses in HPI32 mode.

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HAS (input)

16

15

HCNTL[1:0]

(input)

HR/W (input)

13

(A)

HSTROBE

(input)

37

HCS (input)

18

17

HD[31:0] (input)

38

34

35

5

4

(B)

HRDY (output)

Figure 4-49. HPI32 Write Timing (HAS Not Used, Tied High)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(B) Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and

the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the

TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

(C) The timing t_w(HSTBH), HSTROBE high pulse duration, must be met between consecutive HPI accesses in HPI32 mode.

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10

HAS (input)

12

11

HCNTL[1:0]

(input)

HR/W (input)

9

13

(A)

HSTROBE

(input)

37

HCS (input)

18

17

HD[31:0] (input)

35

34

38

36

5

(B)

HRDY (output)

Figure 4-50. HPI32 Write Timing (HAS Used)

(A) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(B) Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and

the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the

TMS320C6457 DSP Host Port Interface (HPI) User's Guide (SPRUGK7).

(C) The timing t_w(HSTBH), HSTROBE high pulse duration, must be met between consecutive HPI accesses in HPI32 mode.

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4.8.10 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:

•

Full-duplex communication

Double-buffered data registers, which allow a continuous data stream

Independent framing and clocking for receive and transmit

Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially

connected analog-to-digital (A/D) and digital-to-analog (D/A) devices

•

External shift clock or an internal, programmable frequency shift clock for data transfer

For more detailed information on the McBSP peripheral, see the TMS320C6457 DSP Multichannel

Buffered Serial Port (McBSP) Reference Guide (SPRUGK8).

4.8.10.1 McBSP Device-Specific Information

The CLKS signal for MCBSP0 and MCBSP1 can be sourced from an external pin or by the PLL1

controller; for details, see Section 4.8.4. If the clock from the PLL1 controller is used, the clock is shared

between the two McBSPs.

4.8.10.1.1 McBSP Peripheral Register Description(s)

Table 4-59. McBSP 0 Registers

HEX ADDRESS RANGE

028C 0000

ACRONYM

DRR0

REGISTER NAME

McBSP0 Data Receive Register via Configuration Bus⁽¹⁾

McBSP0 Data Receive Register via EDMA3 Bus

McBSP0 Data Transmit Register via Configuration Bus

McBSP0 Data Transmit Register via EDMA Bus

McBSP0 Serial Port Control Register

3000 0000

DRR0

028C 0004

DXR0

3000 0010

DXR0

028C 0008

SPCR0

RCR0

028C 000C

028C 0010

McBSP0 Receive Control Register

XCR0

McBSP0 Transmit Control Register

028C 0014

SRGR0

MCR0

McBSP0 Sample Rate Generator register

028C 0018

McBSP0 Multichannel Control Register

028C 001C

028C 0020

RCERE00

XCERE00

PCR0

McBSP0 Enhanced Receive Channel Enable Register 0 Partition A/B

McBSP0 Enhanced Transmit Channel Enable Register 0 Partition A/B

McBSP0 Pin Control Register

028C 0024

028C 0028

RCERE10

XCERE10

RCERE20

XCERE20

RCERE30

XCERE30

-

McBSP0 Enhanced Receive Channel Enable Register 1 Partition C/D

McBSP0 Enhanced Transmit Channel Enable Register 1 Partition C/D

McBSP0 Enhanced Receive Channel Enable Register 2 Partition E/F

McBSP0 Enhanced Transmit Channel Enable Register 2 Partition E/F

McBSP0 Enhanced Receive Channel Enable Register 3 Partition G/H

McBSP0 Enhanced Transmit Channel Enable Register 3 Partition G/H

Reserved

028C 002C

028C 0030

028C 0034

028C 0038

028C 003C

028C 0040 - 028F FFFF

(1) The CPU and EDMA3 controller can only read the register, they cannot write to it.

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Table 4-60. McBSP 1 Registers

HEX ADDRESS RANGE

0290 0000

ACRONYM

REGISTER NAME

DRR1

McBSP1 Data Receive Register via Configuration Bus(1)

McBSP1 Data Receive Register via EDMA bus

McBSP1 Data Transmit Register via configuration bus

McBSP1 Data Transmit Register via EDMA bus

McBSP1 serial port control register

3400 0000

0290 0004

DXR1

3400 0010

DXR1

0290 0008

SPCR1

RCR1

0290 000C

0290 0010

McBSP1 Receive Control Register

XCR1

McBSP1 Transmit Control Register

0290 0014

SRGR1

MCR1

McBSP1 sample rate generator register

McBSP1 multichannel control register

0290 0018

0290 001C

0290 0020

RCERE01

XCERE01

PCR1

McBSP1 Enhanced Receive Channel Enable Register 0 Partition A/B

McBSP1 Enhanced Transmit Channel Enable Register 0 Partition A/B

McBSP1 Pin Control Register

0290 0024

0290 0028

RCERE11

XCERE11

RCERE21

XCERE21

RCERE31

XCERE31

-

McBSP1 Enhanced Receive Channel Enable Register 1 Partition C/D

McBSP1 Enhanced Transmit Channel Enable Register 1 Partition C/D

McBSP1 Enhanced Receive Channel Enable Register 2 Partition E/F

McBSP1 Enhanced Transmit Channel Enable Register 2 Partition E/F

McBSP1 Enhanced Receive Channel Enable Register 3 Partition G/H

McBSP1 Enhanced Transmit Channel Enable Register 3 Partition G/H

Reserved

0290 002C

0290 0030

0290 0034

0290 0038

0290 003C

0290 0040 - 0293 FFFF

4.8.10.2 McBSP Electrical Data/Timing

Table 4-61. McBSP Timing Requirements⁽¹⁾

(see Figure 4-51)

NO.

MIN

MAX UNIT

2

3

t_c(CKRX)

t_w(CKRX)

Cycle time, CLKR/X

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

10P⁽²⁾

0.5t_c(CKRX)- 1⁽²⁾

ns

Pulse duration, CLKR/X high or CLKR/X low

9

1.3

6

5

6

7

8

t_su(FRH-CKRL)

t_h(CKRL-FRH)

t_su(DRV-CKRL)

t_h(CKRL-DRV)

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

ns

3

8

0.9

3

Hold time, DR valid after CLKR low

3.1

9

10 t_su(FXH-CKXL)

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

1.3

6

11 t_h(CKXL-FXH)

3

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

126

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Table 4-62. Switching Characteristics for McBSP^(1)(2)(3)

(see Figure 4-51)

NO. PARAMETER

MIN

1.4

MAX UNIT

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS

input.⁽⁴⁾

1

2

3

4

t_{d(CKSH-CKRXH)}

t_c(CKRX)

10 ns

ns

Cycle time, CLKR/X

CLKR/X int

10P^{(5) (6) (7)}

0.5t_c(CKRX)

-

t_w(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

Delay time, CLKR high to internal FSR valid

ns

1

t_d(CKRH-FRV)

CLKR int

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

FSX int

-2.1

-1.7

1.7

-3.9

2

3

9

4

9

4

9

ns

9

t_d(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

12 t_{dis(CKXH-DXHZ)}Disable time, DX Hi-Z following last data bit from CLKX high

ns

13 t_d(CKXH-DXV)

Delay time, CLKX high to DX valid

-3.9

2

-2.3 + D1⁽⁸⁾5.6 +

D2⁽⁸⁾

1.9 + D1⁽⁸⁾9 + D2⁽⁸⁾

Delay time, FSX high to DX valid applies ONLY when in data

delay 0 (XDATDLY = 00b) mode

14 t_d(FXH-DXV)

ns

FSX ext

(1) Over recommended operating conditions.

(2) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(3) Minimum delay times also represent minimum output hold times.

(4) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.

(5) Minimum CLKR ÷ X cycle times must be met, even when CLKR ÷ X is generated by an internal clock source. Minimum CLKR ÷ X cycle

times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements

(6) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(7) Use whichever value is greater

(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

Specifications

127

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CLKS^(A)

1

2

3

4

CLKR

FSR (int)

FSR (ext)

DR

4

5

6

7

8

Bit(n-1)

(n-2)

(n-3)

2

3

CLKX

9

FSX (int)

11

10

FSX (ext)

FSX (XDATDLY=00b)

13^(B)

14

13^(B)

Bit(n-1)

12

(n-2)

(n-3)

DX

Bit 0

Figure 4-51. McBSP Timing

(A) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.

(B) Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.

Table 4-63. Timing Requirements for FSR When GSYNC = 1

(see Figure 4-52)

NO.

MIN

MAX UNIT

1

2

t_su(FRH-CKSH)

t_h(CKSH-FRH)

Setup time, FSR high before CLKS high

Hold time, FSR high after CLKS high

4

ns

CLKS

1

2

FSR external

CLKR/X

(no need to resync)

CLKR/X

(needs resync)

Figure 4-52. FSR Timing When GSYNC = 1

128

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Table 4-64. SPI Timing Requirements as Master or Slave: CLKSTP = 10b, CLKXP = 0⁽¹⁾⁽²⁾

(see Figure 4-53)

MASTER

SLAVE

NO.

MIN

12

4

MAX

MIN

2-12P

5+24P

MAX UNIT

4

5

t_su(DRV-CKXL)

t_h(CKXL-DRV)

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

ns

(1) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

Table 4-65. SPI Switching Characteristics as Master or Slave: CLKSTP = 10b, CLKXP = 0^{(1)(2)(3)(4)(5)}

(see Figure 4-53)

MASTER

MIN

T-2

SLAVE

MIN

NO.

PARAMETERS

MAX

T+3

L+3

4

MAX UNIT

1

2

3

t_d(CKXL-FXH)

t_d(FXL-CKXH)

t_d(CKXH-DXV)

Delay time, FSX high after CLKX low

Delay time, CLKX high after FSX low

Delay time, CLKX high to DX valid

ns

L-3

-2

12P+2.8

24P+17

ns

Disable time, DX high impedance following last data bit

from CLKX low

6

t_{dis(CKXL-DXHZ)}

L-2

L+3

ns

Disable time, DX high impedance following last data bit

from FSX high

7

8

t_{dis(FXH-DXHZ)}

td_(FXL-DXV)

4P+3

12P+17

18P+17

ns

Delay time, FSX low to DX valid

8P+1.8

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3) S = Sample rate generator input clock = 6P if CLKSM = 1

S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd

(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

CLKX

1

2

8

FSX

7

6

3

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

Bit 0

(n-2)

(n-4)

Figure 4-53. SPI Timing as Master or Slave: CLKSTP = 10b, CLKXP = 0

Specifications

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Table 4-66. SPI Timing Requirements as Master or Slave: CLKSTP = 10b, CLKXP = 1⁽¹⁾⁽²⁾

(see Figure 4-54)

MASTER

SLAVE

MIN

NO.

MIN

12

4

MAX

MAX UNIT

4

5

t_su(DRV-CKXH)

t_h(CKXH-DRV)

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

2-12P

5+24P

ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 4-67. SPI Switching Characteristics as Master or Slave: CLKSTP = 10b, CLKXP = 1^{(1)(2)(3)(4)(5)}

(see Figure 4-54)

MASTER

MIN

SLAVE

MIN

NO.

PARAMETER

MAX

T+3

MAX UNIT

1

2

t_d(CKXH-FXH)

t_d(FXL-CKXL)

Delay time, FSX high after CLKX high

Delay time, CLKX low after FSX low

Delay time, CLKX low to DX valid

T-2

ns

H-3

H+3

12P +

2.8

3

6

t_d(CKXL-DXV)

-2

4

24P + 17

ns

Disable time, DX high impedance following last data bit

from CLKX high

t_{dis(CKXH-DXHZ)}

H-2

H+3

Disable time, DX high impedance following last data bit

from FSX high

7

8

t_{dis(FXH-DXHZ)}

t_d(FXL-DXV)

4P+3

8P+2

12P+17

18P+17

ns

Delay time, FSX low to DX valid

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3) S = Sample rate generator input clock = 6P if CLKSM = 1

S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd

(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

CLKX

1

2

8

FSX

7

6

3

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

Bit 0

(n-2)

(n-3)

(n-4)

Figure 4-54. SPI Timing as Master or Slave: CLKSTP = 10b, CLKXP = 1

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Table 4-68. SPI Timing Requirements as Master or Slave: CLKSTP = 11b, CLKXP = 0⁽¹⁾⁽²⁾

(see Figure 4-55)

MASTER

SLAVE

NO.

MIN

12

4

MAX

MIN

2-12P

5+24P

MAX UNIT

4

5

t_su(DRV-CKXH)

t_h(CKXH-DRV)

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 4-69. SPI Switching Characteristics as Master or Slave: CLKSTP = 11b, CLKXP = 0^{(1)(2)(3)(4)(5)}

(see Figure 4-55)

MASTER

MIN

L-2

SLAVE

MIN

NO.

PARAMETER

MAX

L+3

T+3

4

MAX UNIT

1

2

3

t_d(CKXL-FXH)

t_d(FXL-CKXH)

t_d(CKXL-DXV)

Delay time, FSX high after CLKX low

Delay time, CLKX high after FSX low

Delay time, CLKX low to DX valid

ns

T-3

-2

12P+2.8

12P+3

24P+17

ns

Disable time, DX high impedance following last data bit

from CLKX low

6

7

t_{dis(CKXL-DXHZ)}

t_{dis(FXL-DXHZ)}

-2

4

20P+17

18P+17

ns

Disable time, DX high impedance following last data bit

from FSX low

H-2

H+4

8P+2

ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3) S = Sample rate generator input clock = 6P if CLKSM = 1

S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd

(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

CLKX

1

2

7

FSX

DX

6

3

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

DR

Bit 0

(n-2)

(n-4)

Figure 4-55. SPI Timing as Master or Slave: CLKSTP = 11b, CLKXP = 0

Table 4-70. SPI Timing Requirements as Master or Slave: CLKSTP = 11b, CLKXP = 1⁽¹⁾⁽²⁾

(see Figure 4-56)

MASTER

SLAVE

MIN

NO.

MIN

12

4

MAX

MAX UNIT

4

5

t_su(DRV-CKXH)

t_h(CKXH-DRV)

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

2-12P

5+24P

ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

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Table 4-71. SPI Switching Characteristics as Master or Slave: CLKSTP = 11b, CLKXP = 1^{(1)(2)(3)(4)(5)}

(see Figure 4-56)

MASTER

MIN

SLAVE

MIN

NO.

PARAMETER

MAX

H+3

T+3

4

MAX UNIT

1

2

3

t_d(CKXH-FXL)

t_d(FXL-CKXL)

t_d(CKXH-DXV)

Delay time, FSX low after CLKX high

Delay time, CLKX low after FSX low

Delay time, CLKX high to DX valid

H-2

ns

T-3

-2

12P+2.8

12P+3

24P+17

ns

Disable time, DX high impedance following last data bit

from CLKX high

6

7

t_{dis(CKXH-DXHZ)}

t_{dis(FXL-DXHZ)}

-2

4

20P+17

18P+17

ns

Disable time, DX high impedance following last data bit

from FSX low

L-2

L+4

8P+2

ns

(1) P = 1/SYSREFCLK frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3) S = Sample rate generator input clock = 6P if CLKSM = 1

S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even; H = (CLKGDV + 1)/2 * S if CLKGDV is odd

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd

(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

CLKX

1

2

FSX

DX

7

6

3

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

DR

(n-2)

(n-3)

(n-4)

Figure 4-56. SPI Timing as Master or Slave: CLKSTP = 11b, CLKXP = 1

4.8.11 Ethernet MAC (EMAC)

The Ethernet Media Access Controller (EMAC) module provides an efficient interface between the C6457

DSP core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/second

[Mbps]), and 100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-

duplex mode, with hardware flow control and quality-of-service (QOS) support.

The EMAC module conforms to the IEEE 802.3-2002 standard, describing the Carrier Sense Multiple

Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE

802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).

Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER.

Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will

intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame

will be detected as an error by the network.

The EMAC control module is the main interface between the device core processor, the MDIO module,

and the EMAC module. The relationship between these three components is shown in Figure 4-57. The

EMAC control module contains the necessary components to allow the EMAC to make efficient use of

device memory, plus it controls device interrupts. The EMAC control module incorporates 8K-bytes of

internal RAM to hold EMAC buffer descriptors.

132

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Interrupt

Controller

DMA Memory

Transfer Controller

Configuration Bus

Peripheral Bus

EMAC Control Module

EMAC/MDIO

Interrupt

EMAC Module

MDIO Module

MDIO Bus

Ethernet Bus

Figure 4-57. EMAC, MDIO, and EMAC Control Modules

For more detailed information on the EMAC/MDIO, see the TMS320C6457 DSP EMAC/MDIO Module

Reference Guide (SPRUGK9).

4.8.11.1 EMAC Device-Specific Information

The EMAC module on the device supports Serial Gigabit Media Independent Interface (SGMII). The

SGMII interface conforms to version 1.8 of the industry standard specification.

Specifications

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4.8.11.2 EMAC Peripheral Register Description(s)

The memory maps of the EMAC are shown in Table 4-72 through Table 4-77.

Table 4-72. Ethernet MAC (EMAC) Control Registers

HEX ADDRESS

02C8 0000

ACRONYM

TXIDVER

REGISTER NAME

Transmit Identification and Version Register

Transmit Control Register

02C8 0004

TXCONTROL

TXTEARDOWN

-

02C8 0008

Transmit Teardown register

02C8 000F

Reserved

02C8 0010

RXIDVER

Receive Identification and Version Register

Receive Control Register

02C8 0014

RXCONTROL

RXTEARDOWN

-

02C8 0018

Receive Teardown Register

02C8 001C

Reserved

02C8 0020 - 02C8 007C

02C8 0080

-

Reserved

TXINTSTATRAW

TXINTSTATMASKED

TXINTMASKSET

TXINTMASKCLEAR

MACINVECTOR

MACEOIVECTOR

-

Transmit Interrupt Status (Unmasked) Register

Transmit Interrupt Status (Masked) Register

Transmit Interrupt Mask Set Register

Transmit Interrupt Mask Clear Register

MAC Input Vector Register

02C8 0084

02C8 0088

02C8 008C

02C8 0090

02C8 0094

MAC End of Interrupt Vector Register

Reserved

02C8 0098 - 02C8 019C

02C8 00A0

RXINTSTATRAW

RXINTSTATMASKED

RXINTMASKSET

RXINTMASKCLEAR

MACINTSTATRAW

MACINTSTATMASKED

MACINTMASKSET

MACINTMASKCLEAR

-

Receive Interrupt Status (Unmasked) Register

Receive Interrupt Status (Masked) Register

Receive Interrupt Mask Set Register

Receive Interrupt Mask Clear Register

MAC Interrupt Status (Unmasked) Register

MAC Interrupt Status (Masked) Register

MAC Interrupt Mask Set Register

MAC Interrupt Mask Clear Register

Reserved

02C8 00A4

02C8 00A8

02C8 00AC

02C8 00B0

02C8 00B4

02C8 00B8

02C8 00BC

02C8 00C0 - 02C8 00FC

02C8 0100

RXMBPENABLE

RXUNICASTSET

RXUNICASTCLEAR

RXMAXLEN

Receive Multicast/Broadcast/Promiscuous Channel Enable Register

Receive Unicast Enable Set Register

Receive Unicast Clear Register

02C8 0104

02C8 0108

02C8 010C

Receive Maximum Length Register

02C8 0110

RXBUFFEROFFSET

Receive Buffer Offset Register

02C8 0114

RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register

02C8 0118 - 02C8 011C

02C8 0120

-

Reserved

RX0FLOWTHRESH

RX1FLOWTHRESH

RX2FLOWTHRESH

RX3FLOWTHRESH

RX4FLOWTHRESH

RX5FLOWTHRESH

RX6FLOWTHRESH

RX7FLOWTHRESH

RX0FREEBUFFER

RX1FREEBUFFER

RX2FREEBUFFER

RX3FREEBUFFER

Receive Channel 0 Flow Control Threshold Register

Receive Channel 1 Flow Control Threshold Register

Receive Channel 2 Flow Control Threshold Register

Receive Channel 3 Flow Control Threshold Register

Receive Channel 4 Flow Control Threshold Register

Receive Channel 5 Flow Control Threshold Register

Receive Channel 6 Flow Control Threshold Register

Receive Channel 7 Flow Control Threshold Register

Receive Channel 0 Free Buffer Count Register

Receive Channel 1 Free Buffer Count Register

Receive Channel 2 Free Buffer Count Register

Receive Channel 3 Free Buffer Count Register

02C8 0124

02C8 0128

02C8 012C

02C8 0130

02C8 0134

02C8 0138

02C8 013C

02C8 0140

02C8 0144

02C8 0148

02C8 014C

134

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Table 4-72. Ethernet MAC (EMAC) Control Registers (continued)

HEX ADDRESS

ACRONYM

RX4FREEBUFFER

RX5FREEBUFFER

RX6FREEBUFFER

RX7FREEBUFFER

MACCONTROL

MACSTATUS

EMCONTROL

FIFOCONTROL

MACCONFIG

SOFTRESET

MACSRCADDRLO

MACSRCADDRHI

MACHASH1

MACHASH2

BOFFTEST

TPACETEST

RXPAUSE

TXPAUSE

-

REGISTER NAME

02C8 0150

02C8 0154

Receive Channel 4 Free Buffer Count Register

Receive Channel 5 Free Buffer Count Register

Receive Channel 6 Free Buffer Count Register

Receive Channel 7 Free Buffer Count Register

MAC Control Register

02C8 0158

02C8 015C

02C8 0160

02C8 0164

MAC Status Register

02C8 0168

Emulation Control Register

02C8 016C

02C8 0170

FIFO Control Register

MAC Configuration Register

Soft Reset Register

02C8 074

02C8 01D0

02C8 01D4

02C8 01D8

02C8 01DC

02C8 01E0

02C8 01E4

02C8 01E8

02C8 01EC

02C8 0300 - 02C8 03FC

02C8 0400 - 02C8 04FC

02C8 0500

MAC Source Address Low Bytes Register

MAC Source Address High Bytes Register

MAC Hash Address Register 1

MAC Hash Address Register 2

Back Off Test Register

Transmit Pacing Algorithm Test Register

Receive Pause Timer Register

Transmit Pause Timer Register

Reserved

-

Reserved

MACADDRLO

MACADDRHI

MACINDEX

-

MAC Address Low Bytes Register (used in Receive Address Matching)

MAC Address High Bytes Register (used in Receive Address Matching)

MAC Index Register

02C8 0504

02C8 0508

02C8 050C - 02C8 05FC

02C8 0600

Reserved

TX0HDP

Transmit Channel 0 DMA Head Descriptor Pointer Register

Transmit Channel 1 DMA Head Descriptor Pointer Register

Transmit Channel 2 DMA Head Descriptor Pointer Register

Transmit Channel 3 DMA Head Descriptor Pointer Register

Transmit Channel 4 DMA Head Descriptor Pointer Register

Transmit Channel 5 DMA Head Descriptor Pointer Register

Transmit Channel 6 DMA Head Descriptor Pointer Register

Transmit Channel 7 DMA Head Descriptor Pointer Register

Receive Channel 0 DMA Head Descriptor Pointer Register

Receive t Channel 1 DMA Head Descriptor Pointer Register

Receive Channel 2 DMA Head Descriptor Pointer Register

Receive t Channel 3 DMA Head Descriptor Pointer Register

Receive Channel 4 DMA Head Descriptor Pointer Register

Receive t Channel 5 DMA Head Descriptor Pointer Register

Receive Channel 6 DMA Head Descriptor Pointer Register

Receive t Channel 7 DMA Head Descriptor Pointer Register

Transmit Channel 0 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 1 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 2 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 3 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 4 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 5 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register

02C8 0604

TX1HDP

02C8 0608

TX2HDP

02C8 060C

02C8 0610

TX3HDP

TX4HDP

02C8 0614

TX5HDP

02C8 0618

TX6HDP

02C8 061C

02C8 0620

TX7HDP

RX0HDP

02C8 0624

RX1HDP

02C8 0628

RX2HDP

02C8 062C

02C8 0630

RX3HDP

RX4HDP

02C8 0634

RX5HDP

02C8 0638

RX6HDP

02C8 063C

02C8 0640

RX7HDP

TX0CP

02C8 0644

TX1CP

02C8 0648

TX2CP

02C8 064C

02C8 0650

TX3CP

TX4CP

02C8 0654

TX5CP

02C8 0658

TX6CP

Specifications

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Table 4-72. Ethernet MAC (EMAC) Control Registers (continued)

HEX ADDRESS

02C8 065C

ACRONYM

TX7CP

RX0CP

RX1CP

RX2CP

RX3CP

RX4CP

RX5CP

RX6CP

RX7CP

-

REGISTER NAME

Transmit Channel 7 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 0 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 1 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 2 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 3 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 4 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 5 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 6 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 7 Completion Pointer (Interrupt Acknowledge) Register

Reserved

02C8 0660

02C8 0664

02C8 0668

02C8 066C

02C8 0670

02C8 0674

02C8 0678

02C8 067C

02C8 0680 - 02C8 06FC

02C8 0700 - 02C8 077C

02C8 0780 - 02C8 0FFF

-

Reserved

-

Reserved

Table 4-73. EMAC Statistics Registers

HEX ADDRESS

ACRONYM

REGISTER NAME

02C8 0200

RXGOODFRAMES

Good Receive Frames Register

Broadcast Receive Frames Register (Total number of Good Broadcast Frames

Receive)

02C8 0204

RXBCASTFRAMES

Multicast Receive Frames Register (Total number of Good Multicast Frames

Received)

02C8 0208

02C8 020C

02C8 0210

RXMCASTFRAMES

RXPAUSEFRAMES

RXCRCERRORS

Pause Receive Frames Register

Receive CRC Errors Register (Total number of Frames Received with CRC

Errors)

Receive Alignment/Code Errors register (Total number of frames received with

alignment/code errors)

02C8 0214

RXALIGNCODEERRORS

Receive Oversized Frames Register (Total number of Oversized Frames

Received)

02C8 0218

02C8 021C

02C8 0220

RXOVERSIZED

RXJABBER

Receive Jabber Frames Register (Total number of Jabber Frames Received)

Receive Undersized Frames Register (Total number of Undersized Frames

Received)

RXUNDERSIZED

02C8 0224

02C8 0228

02C8 022C

RXFRAGMENTS

RXFILTERED

Receive Frame Fragments Register

Filtered Receive Frames Register

Received QOS Filtered Frames Register

RXQOSFILTERERED

Receive Octet Frames Register (Total number of Received Bytes in Good

Frames)

02C8 0230

RXOCTETS

02C8 0234

02C8 0238

02C8 023C

02C8 0240

02C8 0244

02C8 0248

02C8 024C

02C8 0250

02C8 0254

02C8 0258

02C8 025C

02C8 0260

02C8 0264

02C8 0268

TXGOODFRAMES

TXBCASTFRAMES

TXMCASTFRAMES

TXPAUSEFRAMES

TXDEFERED

Good Transmit Frames Register (Total number of Good Frames Transmitted)

Broadcast Transmit Frames Register

Multicast Transmit Frames Register

Pause Transmit Frames Register

Deferred Transmit Frames Register

TXCOLLISION

Transmit Collision Frames Register

TXSINGLECOLL

TXMULTICOLL

TXEXCESSIVECOLL

TXLATECOLL

Transmit Single Collision Frames Register

Transmit Multiple Collision Frames Register

Transmit Excessive Collision Frames Register

Transmit Late Collision Frames Register

Transmit Under Run Error Register

TXUNDERRUN

TXCARRIERSENSE

TXOCTETS

Transmit Carrier Sense Errors Register

Transmit Octet Frames Register

FRAME64

Transmit and Receive 64 Octet Frames Register

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Table 4-73. EMAC Statistics Registers (continued)

HEX ADDRESS

ACRONYM

FRAME65T127

FRAME128T255

FRAME256T511

FRAME512T1023

FRAME1024TUP

NETOCTETS

REGISTER NAME

02C8 026C

02C8 0270

Transmit and Receive 65 to 127 Octet Frames Register

Transmit and Receive 128 to 255 Octet Frames Register

Transmit and Receive 256 to 511 Octet Frames Register

Transmit and Receive 512 to 1023 Octet Frames Register

Transmit and Receive 1024 to 1518 Octet Frames Register

Network Octet Frames Register

02C8 0274

02C8 0278

02C8 027C

02C8 0280

02C8 0284

RXSOFOVERRUNS

RXMOFOVERRUNS

RXDMAOVERRUNS

-

Receive FIFO or DMA Start of Frame Overruns Register

Receive FIFO or DMA Middle of Frame Overruns Register

Receive DMA Start of Frame and Middle of Frame Overruns Register

Reserved

02C8 0288

02C8 028C

02C8 0290 - 02C8 02FC

Table 4-74. EMAC Descriptor Memory

HEX ADDRESS

ACRONYM

REGISTER NAME

02E0 0000 - 02E0 3FFF

-

EMAC Descriptor Memory

Table 4-75. SGMII Control Registers

HEX ADDRESS

02C4 0000

ACRONYM

REGISTER NAME

IDVER

Identification and Version register

Software Reset Register

Control Register

02C4 0004

SOFT_RESET

02C4 0010

CONTROL

02C4 0014

STATUS

Status Register

02C4 0018

MR_ADV_ABILITY

Advertised Ability Register

Reserved

02C4 001C

-

02C4 0020

MR_LP_ADV_ABILITY

Link Partner Advertised Ability Register

Reserved

02C4 0024

-

02C4 0030

TX_CFG

RX_CFG

AUX_CFG

-

Transmit Configuration Register

Receive Configuration Register

Auxiliary Configuration Register

Reserved

02C4 0034

02C4 0038

02C4 0040 - 02C4 0048

Table 4-76. EMIC Control Registers

HEX ADDRESS

02C8 1000

02C8 1004

02C8 1008

02C8 100C

02C8 1010

02C8 1014

02C8 1018

02C8 101C

02C8 1040

02C8 1044

02C8 1048

02C8 104C

02C8 1070

02C8 1074

ACRONYM

REGISTER NAME

IDVER

SOFT_RESET

EM_CONTROL

INT_CONTROL

C_RX_THRESH_EN

C_RX_EN

Identification and Version register

Software Reset Register

Emulation Control Register

Interrupt Control Register

Receive Threshold Interrupt Enable Register

Receive Interrupt Enable Register

Transmit Interrupt Enable Register

Misc Interrupt Enable Register

C_TX_EN

C_MISC_EN

C_RX_THRESH_STAT

C_RX_STAT

Receive Threshold Masked Interrupt Status Register

Receive Interrupt Masked Interrupt Status Register

Transmit Interrupt Masked Interrupt Status Register

Misc Interrupt Masked Interrupt Status Register

Receive Interrupts Per Millisecond

Transmit Interrupts Per Millisecond

C_TX_STAT

C_MISC_STAT

C_RX_IMAX

C_TX_IMAX

Specifications

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4.8.11.3 EMAC Electrical Data/Timing (SGMII)

The TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide application report (SPRAAV7)

specifies a complete EMAC and SGMII interface solutions for the C6457 as well as a list of compatible

EMAC and SGMII devices. TI has performed the simulation and system characterization to ensure all

EMAC and SGMII interface timings in this solution are met; therefore, no electrical data/timing information

is supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application

report.

4.8.12 Management Data Input/Output (MDIO)

The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to

interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.

Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY

attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC

module for correct operation. The module is designed to allow almost transparent operation of the MDIO

interface, with very little maintenance from the core processor.

The EMAC control module is the main interface between the device core processor, the MDIO module,

and the EMAC module. The relationship between these three components is shown in Figure 4-57.

For more detailed information on the EMAC/MDIO, see the TMS320C6457 DSP EMAC/MDIO Module

Reference Guide (SPRUGK9).

4.8.12.1 MDIO Peripheral Register Description(s)

The memory map of the MDIO is shown in Table 4-77.

Table 4-77. MDIO Registers

HEX ADDRESS

02C8 1800

ACRONYM

VERSION

REGISTER NAME

MDIO Version Register

02C8 1804

CONTROL

MDIO Control Register

02C8 1808

ALIVE

MDIO PHY Alive Status Register

MDIO PHY Link Status Register

02C8 180C

LINK

02C8 1810

LINKINTRAW

LINKINTMASKED

-

MDIO link Status Change Interrupt (unmasked) Register

MDIO link Status Change Interrupt (masked) Register

Reserved

02C8 1814

02C8 1818 - 02C8 181C

02C8 1820

USERINTRAW

USERINTMASKED

USERINTMASKSET

USERINTMASKCLEAR

-

MDIO User Command Complete Interrupt (Unmasked) Register

MDIO User Command Complete Interrupt (Masked) Register

MDIO User Command Complete Interrupt Mask Set Register

MDIO User Command Complete Interrupt Mask Clear Register

Reserved

02C8 1824

02C8 1828

02C8 182C

02C8 1830 - 02C8 187C

02C8 1880

USERACCESS0

USERPHYSEL0

USERACCESS1

USERPHYSEL1

-

MDIO User Access Register 0

02C8 1884

MDIO User PHY Select Register 0

MDIO User Access Register 1

02C8 1888

02C8 188C

MDIO User PHY Select Register 1

Reserved

02C8 1890 - 02C8 1FFF

138

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4.8.12.2 MDIO Electrical Data/Timing

Table 4-78. MDIO Input Timing Requirements

(see Figure 4-58)

NO.

MIN

400

180

MAX UNIT

1

t_c(MDCLK)

2a t_w(MDCLKH)

2b t_w(MDCLKL)

Cycle time, MDCLK

ns

Pulse duration, MDCLK high

Pulse duration, MDCLK low

Transition time, MDCLK

3

4

5

t_t(MDCLK)

5

ns

t_{su(MDIO-MDCLKH)}Setup time, MDIO data input valid before MDCLK high

10

t_{h(MDCLKH-MDIO)}

Hold time, MDIO data input valid after MDCLK high

1

MDCLK

4

5

MDIO

(input)

Figure 4-58. MDIO Input Timing

Table 4-79. MDIO Output Switching Characteristics⁽¹⁾

(see Figure 4-59)

NO. PARAMETER

MIN

MAX UNIT

7

t_{d(MDCLKL-MDIO)}Delay time, MDCLK low to MDIO data output valid

100

ns

(1) Over recommended operating conditions.

1

MDCLK

7

MDIO

(input)

Figure 4-59. MDIO Output Timing

Specifications

139

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4.8.13 Timers

The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send

synchronization events to the EDMA3 channel controller.

4.8.13.1 Timers Device-Specific Information

The C6457 device has two general-purpose timers, Timer0 and Timer1, each of which can be configured

as a general-purpose timer or as a watchdog timer. When configured as a general-purpose timer, each

timer can be programmed as a 64-bit timer or as two separate 32-bit timers.

Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx

and TOUTLx are connected to the low counter. The high counter does not have any external device pins.

4.8.13.1.1 Timer Watchdog Select

As mentioned previously, the timers can operate in watchdog mode. When in watchdog mode, the event

output from Timer1 can optionally reset the CPU. In order for the event to trigger the reset when this

operation is desired, the Timer1 watchdog reset selection register (WDRSTSEL) should be set to 1. The

WDRSTSEL register is shown in Figure 4-60 and described in Table 4-80.

Figure 4-60. Timer1 Watchdog Reset Selection Register (WDRSTSEL) (Address - 0288 0920h)

31

15

30

14

29

13

28

12

27

11

26

25

24

Reserved

R- 0000 0000 0000 0000 0000 0000 0000 000

23

22

21

20

4

19

3

18

2

17

1

16

10

9

8

7

6

5

0

Reserved

WDRS

TSEL

R- 0000 0000 0000 0000 0000 0000 0000 000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

R/W-0

Table 4-80. Timer1 Watchdog Reset Selection Register (WDRSTSEL) Field Descriptions

Bit

31:1

0

Acronym

Description

Reserved

Reserved.

WRDSTSEL

Reset Select for Watchdog Timer1

•

0 = TOUT1L does not cause a reset to the C64x+ megamodule (default)

1 = TOUT1L causes a reset to the C64x+ megamodule

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4.8.13.2 Timers Peripheral Register Description(s)

Table 4-81. Timer 0 Registers

HEX ADDRESS RANGE

0294 0000

ACRONYM

REGISTER NAME

-

Reserved

0294 0004

EMUMGT_CLKSPD0

Timer 0 Emulation Management/Clock Speed Register

Reserved

0294 0008

-

0294 000C

Reserved

0294 0010

CNTLO0

CNTHI0

PRDLO0

PRDHI0

TCR0

TGCR0

WDTCR0

-

Timer 0 Counter Register Low

Timer 0 Counter Register High

Timer 0 Period Register Low

Timer 0 Period Register High

Timer 0 Control Register

Timer 0 Global Control Register

Timer 0 Watchdog Timer Control Register

Reserved

0294 0014

0294 0018

0294 001C

0294 0020

0294 0024

0294 0028

0294 002C

0294 0030

-

Reserved

0294 0034 - 0297 FFFF

-

Reserved

Table 4-82. Timer 1 Registers

HEX ADDRESS RANGE

0298 0000

ACRONYM

REGISTER NAME

-

Reserved

0298 0004

EMUMGT_CLKSPD1

Timer 1 Emulation Management/Clock Speed Register

Reserved

0298 0008

-

0298 000C

Reserved

0298 0010

CNTLO1

CNTHI1

PRDLO1

PRDHI1

TCR1

TGCR1

WDTCR1

-

Timer 1 Counter Register Low

Timer 1 Counter Register High

Timer 1 Period Register Low

Timer 1 Period Register High

Timer 1 Control Register

Timer 1 Global Control Register

Timer 1 Watchdog Timer Control Register

Reserved

0298 0014

0298 0018

0298 001C

0298 0020

0298 0024

0298 0028

0298 002C

0298 0030

-

Reserved

0298 0034 - 0299 FFFF

-

Reserved

Specifications

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4.8.13.3 Timers Electrical Data/Timing

The below tables and figures describe the timing requirements and switching characteristics of both the

Timer0 and Timer1 peripherals.

Table 4-83. Timer Input Timing Requirements⁽¹⁾

(see Figure 4-61)

NO.

1

MIN

12C

MAX UNIT

t_w(TIMIH)

t_w(TIMIL)

Pulse duration, TIMI high

Pulse duration, TIMI low

ns

2

(1) If CORECLKSEL = 0, C = 1/CORECLK(NIP) frequency in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency in ns.

Table 4-84. Timer Output Switching Characteristics⁽¹⁾⁽²⁾

(see Figure 4-61)

NO.

3

PARAMETER

MIN

12C - 3

MAX UNIT

t_w(TIMOH)

t_w(TIMOL)

Pulse duration, TIMO high

Pulse duration, TIMO low

ns

4

(1) Over recommended operating conditions.

(2) If CORECLKSEL = 0, C = 1/CORECLK(NIP) frequency in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency in ns.

2

1

TIMIx

4

3

TIMOx

Figure 4-61. Timer Timing

142

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4.8.14 Enhanced Viterbi-Decoder Coprocessor (VCP2)

4.8.14.1 VCP2 Device-Specific Information

The C6457 device has a high-performance embedded Viterbi-Decoder Coprocessor (VCP2) that

significantly speeds up channel-decoding operations on-chip. The VCP2, operating at CPU clock divided-

by-3, can decode more than 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels.

The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and

flexible polynomials, while generating hard decisions or soft decisions. Communications between the

VCP2 and the CPU are carried out through the EDMA3 controller.

The VCP2 supports:

•

Unlimited frame sizes

Code rates 3/4, 1/2, 1/3, 1/4, and 1/5

Constraint lengths 5, 6, 7, 8, and 9

Programmable encoder polynomials

Programmable reliability and convergence lengths

Hard and soft decoded decisions

Tail and convergent modes

Yamamoto logic

Tail biting logic

Various input and output FIFO lengths

For more detailed information on the VCP2, see the TMS320C6457 DSP Viterbi-Decoder Coprocessor 2

(VCP2) Reference Guide (SPRUGK0).

4.8.14.2 VCP2 Peripheral Register Description

Table 4-85. VCP2 Registers

EDMA BUS HEX ADDRESS

RANGE

CONFIGURATION BUS HEX ADDRESS

RANGE

ACRONYM

VCPIC0

VCPIC1

VCPIC2

VCPIC3

VCPIC4

VCPIC5

-

REGISTER NAME

5800 0000

5800 0004

-

VCP2 Input Configuration Register 0

VCP2 Input Configuration Register 1

VCP2 Input Configuration Register 2

VCP2 Input Configuration Register 3

VCP2 Input Configuration Register 4

VCP2 Input Configuration Register 5

Reserved

5800 0008

5800 000C

5800 0010

5800 0014

5800 0018 - 5800 0044

5800 0048

-

VCPOUT0

VCPOUT1

-

VCP2 Output Register 0

5800 004C

VCP2 Output Register 1

5800 0050 - 5800 007C

Reserved

VCP2 Branch Metrics Write FIFO

Register

5800 0080

N/A

VCPWBM

5800 0084 - 5800 009C

-

Reserved

5800 00C0

N/A

VCPRDECS

VCPPID

VCPEXE

VCPEND

VCPSTAT0

VCPSTAT1

VCPERR

-

VCP2 Decisions Read FIFO Register

VCP2 Peripheral ID Register

VCP2 Execution Register

VCP2 Endian Mode Register

VCP2 Status Register 0

VCP2 Status Register 1

VCP2 Error Register

02B8 0000

02B8 0018

02B8 0020

02B8 0040

02B8 0044

02B8 0050

-

N/A

-

Reserved

Specifications

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Table 4-85. VCP2 Registers (continued)

EDMA BUS HEX ADDRESS

RANGE

CONFIGURATION BUS HEX ADDRESS

RANGE

ACRONYM

VCPEMU

-

REGISTER NAME

N/A

02B8 0060

VCP2 Emulation Control Register

Reserved

N/A

02B8 0064 - 02B9 FFFF

5800 1000

5800 2000

5800 3000

5800 6000

5800 F000

-

BM

Branch Metrics

SM

State Metric

TBHD

TBSD

IO

Traceback Hard Decision

Traceback Soft Decision

Decoded Bits

4.8.15 Enhanced Turbo Decoder Coprocessor (TCP2)

4.8.15.1 TCP2 Device-Specific Information

The C6457 device has two high-performance embedded Turbo-Decoder Coprocessors (TCP2_A and

TCP2_B) that significantly speed up channel-decoding operations on-chip. Each TCP2, operating at CPU

clock divided-by-3, can decode up to fifty 384-Kbps or eight 2-Mbps turbo-encoded channels (assuming 6

iterations). The TCP2 implements the max * log-map algorithm and is designed to support all polynomials

and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable

frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping

criteria are also programmable. Communications between the TCP2 and the CPU are carried out through

the EDMA3 controller.

Each TCP2 supports:

•

Parallel concatenated convolutional turbo decoding using the MAP algorithm

All turbo code rates greater than or equal to 1/5

3GPP and CDMA2000 turbo encoder trellis

3GPP and CDMA2000 block sizes in standalone mode

Larger block sizes in shared processing mode

Both max log MAP and log MAP decoding

Sliding windows algorithm with variable reliability and prolog lengths

The prolog reduction algorithm

Execution of a minimum and maximum number of iterations

The SNR stopping criteria algorithm

The CRC stopping criteria algorithm

For more detailed information on the TCP2, see the TMS320C6457 DSP Turbo-Decoder Coprocessor 2

(TCP2) Reference Guide (SPRUGK1).

144

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Table 4-86. TCP2_A Registers

EDMA BUS HEX ADDRESS

CONFIGURATION BUS HEX ADDRESS

RANGE

ACRONYM

REGISTER NAME

5000 0000

5000 0004

5000 0008

5000 000C

5000 0010

5000 0014

5000 0018

5000 001C

5000 0020

5000 0024

5000 0028

5000 002C

5000 0030

5000 0034

5000 0038

5000 003C

5000 0040

5000 0044

5000 0048

5001 0000

5003 0000

5004 0000

5005 0000

5006 0000

5007 0000

5008 0000

5009 0000

500A 0000

500B 0000

-

TCPIC0

TCPIC1

TCPIC2

TCPIC3

TCPIC4

TCPIC5

TCPIC6

TCPIC7

TCPIC8

TCPIC9

TCPIC10

TCPIC11

TCPIC12

TCPIC13

TCPIC14

TCPIC15

TCPOUT0

TCPOUT1

TCPOUT2

X0

TCP2 Input Configuration Register 0

TCP2 Input Configuration Register 1

TCP2 Input Configuration Register 2

TCP2 Input Configuration Register 3

TCP2 Input Configuration Register 4

TCP2 Input Configuration Register 5

TCP2 Input Configuration Register 6

TCP2 Input Configuration Register 7

TCP2 Input Configuration Register 8

TCP2 Input Configuration Register 9

TCP2 Input Configuration Register 10

TCP2 Input Configuration Register 11

TCP2 Input Configuration Register 12

TCP2 Input Configuration Register 13

TCP2 Input Configuration Register 14

TCP2 Input Configuration Register 15

TCP2 Output Parameters Register 0

TCP2 Output Parameters Register 1

TCP2 Output Parameters Register 2

TCP2 Data/Sys and Parity Memory

TCP2 Extrinsic Mem 0

-

N/A

W0

N/A

W1

TCP2 Extrinsic Mem 1

N/A

I0

TCP2 Interleaver Memory

O0

TCP2 Output/Decision Memory

TCP2 Scratch Pad Memory

N/A

S0

N/A

T0

TCP2 Beta State Memory

N/A

C0

TCP2 CRC Memory

N/A

B0

TCP2 Beta Prolog Memory

N/A

A0

TCP2 Alpha Prolog Memory

02BA 0000

02BA 004C

02BA 0050

02BA 0060

02BA 0068

02BA 0070

02BA 0074 - 02BA 00FF

TCPPID

TCPEXE

TCPEND

TCPERR

TCPSTAT

TCPEMU

-

TCP2 Peripheral Identification Register

TCP2 Execute Register

N/A

TCP2 Endianness Register

TCP2 Error Register

TCP2 Status Register

TCP2 Emulation Register

Reserved

Specifications

145

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Table 4-87. TCP2_B Registers

EDMA BUS HEX ADDRESS

RANGE

CONFIGURATION BUS HEX ADDRESS

RANGE

ACRONYM

REGISTER NAME

5010 0000

5010 0004

5010 0008

5010 000C

5010 0010

5010 0014

5010 0018

5010 001C

5010 0020

5010 0024

5010 0028

5010 002C

5010 0030

5010 0034

5010 0038

5010 003C

5010 0040

5010 0044

5010 0048

5011 0000

5013 0000

5014 0000

5015 0000

5016 0000

5017 0000

5018 0000

5019 0000

501A 0000

501B 0000

-

TCPIC0

TCPIC1

TCPIC2

TCPIC3

TCPIC4

TCPIC5

TCPIC6

TCPIC7

TCPIC8

TCPIC9

TCPIC10

TCPIC11

TCPIC12

TCPIC13

TCPIC14

TCPIC15

TCPOUT0

TCPOUT1

TCPOUT2

X0

TCP2 Input Configuration Register 0

TCP2 Input Configuration Register 1

TCP2 Input Configuration Register 2

TCP2 Input Configuration Register 3

TCP2 Input Configuration Register 4

TCP2 Input Configuration Register 5

TCP2 Input Configuration Register 6

TCP2 Input Configuration Register 7

TCP2 Input Configuration Register 8

TCP2 Input Configuration Register 9

TCP2 Input Configuration Register 10

TCP2 Input Configuration Register 11

TCP2 Input Configuration Register 12

TCP2 Input Configuration Register 13

TCP2 Input Configuration Register 14

TCP2 Input Configuration Register 15

TCP2 Output Parameters Register 0

TCP2 Output Parameters Register 1

TCP2 Output Parameters Register 2

TCP2 Data/Sys and Parity Memory

TCP2 Extrinsic Mem 0

-

N/A

W0

N/A

W1

TCP2 Extrinsic Mem 1

N/A

I0

TCP2 Interleaver Memory

O0

TCP2 Output/Decision Memory

TCP2 Scratch Pad Memory

N/A

S0

N/A

T0

TCP2 Beta State Memory

N/A

C0

TCP2 CRC Memory

N/A

B0

TCP2 Beta Prolog Memory

N/A

A0

TCP2 Alpha Prolog Memory

02BA 0100

02BA 014C

02BA 0150

02BA 0160

02BA 0168

02BA 0170

02BA 0174 - 02BB FFFF

TCPPID

TCPEXE

TCPEND

TCPERR

TCPSTAT

TCPEMU

-

TCP2 Peripheral Identification Register

TCP2 Execute Register

N/A

TCP2 Endianness Register

TCP2 Error Register

TCP2 Status Register

TCP2 Emulation Register

Reserved

146

Specifications

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4.8.16 UTOPIA

4.8.16.1 UTOPIA Device-Specific Information

The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz, 8-Bit Slave-

only interface. The UTOPIA is more simplistic than the Ethernet MAC, in that the UTOPIA is serviced

directly by the EDMA3 controller. The UTOPIA peripheral contains two, two-cell FIFOs, one for transmit

and one for receive, with which to buffer up data sent/received across the pins. There is a transmit and a

receive event to the EDMA3 channel controller to enable servicing.

For more detailed information on the UTOPIA peripheral, see the TMS320C6457 DSP Universal Test and

Operations PHY Interface for ATM 2 (UTOPIA2) (SPRUGL1).

4.8.16.2 UTOPIA Peripheral Register Description(s)

Table 4-88. UTOPIA Registers

HEX ADDRESS RANGE

02B4 0000

ACRONYM

REGISTER NAME

UTOPIA Control Register

Reserved

UCR

02B4 0004

-

02B4 0008

-

Reserved

02B4 000C

-

Reserved

02B4 0010

-

Reserved

02B4 0014

CDR

EIER

EIPR

-

Clock Detect Register

Error Interrupt Enable Register

Error Interrupt Pending Register

Reserved

02B4 0018

02B4 001C

02B4 0020 - 02B4 01FF

02B4 0200 - 02B7 FFFF

-

Reserved

Table 4-89. UTOPIA Data Queues (Receive and Transmit) Registers

HEX ADDRESS RANGE

3D00 0000 - 3D00 007F

3D00 0080 - 3D00 03FF

3D00 0400 - 3D00 047F

3D00 0480 - 3D00 07FF

ACRONYM

REGISTER NAME

URQ

UTOPIA Receive (RX) Data Queue

Reserved

-

UXQ

-

UTOPIA Transmit (TX) Data Queue

Reserved

4.8.16.3 UTOPIA Electrical Data/Timing

Table 4-90. UXCLK Timing Requirements⁽¹⁾

(see Figure 4-62)

NO.

MIN

20

MAX UNIT

ns

1

2

3

4

t_c(UXCK)

t_w(UXCKH)

t_w(UXCKL)

t_t(UXCK)

Cycle time, UXCLK

Pulse duration, UXCLK high

Pulse duration, UXCLK low

Transition time, UXCLK

0.4t_c(UXCK)

0.6t_c(UXCK)ns

2

ns

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

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1

4

2

UXCLK

3

4

Figure 4-62. UXCLK Timing

Table 4-91. URCLK Timing Requirements⁽¹⁾

(see Figure 4-63)

NO.

MIN

MAX UNIT

ns

1

2

3

4

t_c(URCK)

t_w(URCKH)

t_w(URCKL)

t_t(URCK)

Cycle time, URCLK

20

Pulse duration, URCLK high

Pulse duration, URCLK low

Transition time, URCLK

0.4t_c(URCK)

0.6t_c(URCK)ns

2

ns

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

1

4

2

URCLK

3

4

Figure 4-63. URCLK Timing

Table 4-92. UTOPIA Slave Transmit Timing Requirements

(see Figure 4-64)

NO.

MIN

4

MAX UNIT

2

3

8

9

t_{su(UXAV-UXCH)}

t_h(UXCH-UXAV)

Setup time, UXADDR valid before UXCLK high

Hold time, UXADDR valid after UXCLK high

ns

1

t_{su(UXENBL-UXCH)}Setup time, UXENB low before UXCLK high

t_{h(UXCH-UXENBL)}Hold time, UXENB low after UXCLK high

4

1

Table 4-93. UTOPIA Slave Transmit Cycles Switching Characteristics⁽¹⁾

(see Figure 4-64)

No.

Parameter

Min

2

Max Unit

12 ns

1

4

5

6

t_d(UXCH-UXDV)

Delay time, UXCLK high to UXDATA valid

t_{d(UXCH-UXCLAV)}

t_{d(UXCH-UXCLAVL)}

Delay time, UXCLK high to UXCLAV driven active value

Delay time, UXCLK high to UXCLAV driven inactive low

2

12 ns

2

12 ns

t_{d(UXCH-UXCLAVHZ)}Delay time, UXCLK high to UXCLAV going Hi-Z

9

18.5 ns

t_w(UXCLAVL-

UXCLAVHZ)

7

Pulse duration (low), UXCLAV low to UXCLAV Hi-Z

2

ns

10 t_d(UXCH-UXSV)

Delay time, UXCLK high to UXSOC valid

12 ns

(1) Over recommended operating conditions.

148

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UXCLK

1

3

P45

P46

N

P47

P48

H1

UXDATA[7:0]

2

0 x1F

UXADDR[4:0]

0x1F

N

0x1F

N + 1

7

0x1F

6

4

5

N

8

UXCLAV

UXENB

UXSOC

9

10

Figure 4-64. UTOPIA Slave Transmit Timing^(A)

(A) The UTOPIA slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC

signals).

Table 4-94. UTOPIA Slave Receive Timing Requirements

(see Figure 4-65)

NO.

1

MIN

4

MAX UNIT

t_{su(URDV-URCH)}

t_h(URCH-URDV)

t_{su(URAV-URCH)}

t_h(URCH-URAV)

Setup time, URDATA valid before URCLK high

Hold time, URDATA valid after URCLK high

Setup time, URADDR valid before URCLK high

Hold time, URADDR valid after URCLK high

ns

2

1

3

4

1

9

t_{su(URENBL-URCH)}Setup time, URENB low before URCLK high

4

10 t_{h(URCH-URENBL)}

11 t_{su(URSH-URCH)}

12 t_h(URCH-URSH)

Hold time, URENB low after URCLK high

Setup time, URSOC high before URCLK high

Hold time, URSOC high after URCLK high

1

4

1

Table 4-95. Switching Characteristics for UTOPIA Slave Receive Cycles⁽¹⁾

(see Figure 4-65)

NO.

PARAMETER

MIN

3

MAX UNIT

12 ns

18.5 ns

ns

5

6

7

t_{d(URCH-URCLAV)}

t_{d(URCH-URCLAVL)}

Delay time, URCLK high to URCLAV driven active value

Delay time, URCLK high to URCLAV driven inactive low

3

t_{d(URCH-URCLAVHZ)}Delay time, URCLK high to URCLAV going Hi-Z

9

t_w(URCLAVL-

URCLAVHZ)

Pulse duration (low), URCLAV low to URCLAV Hi-Z

8

3

(1) Over recommended operating conditions.

Specifications

149

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URCLK

URDATA[7:0]

URADDR[4:0]

2

1

P48

H1

H2

H3

4

5

3

N

0x1F

N+1

0x1F

N+2

8

0x1F

7

6

URCLAV

URENB

URSOC

N

N+1

N+2

10

9

11

12

Figure 4-65. UTOPIA Slave Receive Timing^(A)

(A) The UTOPIA slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and URSOC

signals).

4.8.17 Serial RapidIO (SRIO) Port

The SRIO port on the C6457 device is a high-performance, low pin-count interconnect aimed for

embedded markets. The use of the RapidIO interconnect in a baseband board design can create a

homogeneous interconnect environment, providing even more connectivity and control among the

components. RapidIO is based on the memory and device addressing concepts of processor buses where

the transaction processing is managed completely by hardware. This enables the RapidIO interconnect to

lower the system cost by providing lower latency, reduced overhead of packet data processing, and higher

system bandwidth, all of which are key for wireless interfaces. The RapidIO interconnect offers very low

pin-count interfaces with scalable system bandwidth based on 10-Gigabit per second (Gbps) bidirectional

links.

The PHY part of the RIO consists of the physical layer and includes the input and output buffers (each

serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the

parallel-to-serial/serial-to-parallel converters.

The C6457 device supports four 1× or one 4× Serial RapidIO links. The RapidIO interface should be

designed to operate at a data rate of 3.125 Gbps per differential pair. This equals 12.5 raw GBaud/s for

the 4× RapidIO port, or approximately 9 Gbps data throughput rate.

150

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4.8.17.1 Serial RapidIO Device-Specific Information

The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as

EMIFA, HPI, and McBSP. For these other interfaces, the device timing was specified in terms of data

manual specifications and I/O buffer information specification (IBIS) models.

For the C6457 SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing

two DSPs connected via a 4× SRIO link directly to the user. TI has performed the simulation and system

characterization to ensure all SRIO interface timings in this solution are met. The complete SRIO system

solution is documented in the TMS320TCI6484 and TMS320C6457 SerDes Implementation Guidelines

application report (SPRAAY1).

NOTE

TI supports only designs that follow the board design guidelines outlined in the application

report.

The Serial RapidIO peripheral is a master peripheral in the C6457 DSP. It conforms to the RapidIO™

Interconnect Specification, Part VI: Physical Layer 1×/4× LP-Serial Specification, Revision 1.3.

4.8.17.2 Serial RapidIO Peripheral Register Description(s)

Table 4-96. RapidIO Control Registers

HEX ADDRESS RANGE

02D0 0000

ACRONYM

RIO_PID

REGISTER NAME

Peripheral Identification Register

Peripheral Control Register

Reserved

02D0 0004

RIO_PCR

02D0 0008 - 02D0 001C

02D0 0020

-

RIO_PER_SET_CNTL0

RIO_PER_SET_CNTL1

-

Peripheral Settings Control Register 0

Peripheral Settings Control Register 1

Reserved

02D0 0024

02D0 0028 - 02D0 002C

02D0 0030

RIO_GBL_EN

RIO_GBL_EN_STAT

RIO_BLK0_EN

RIO_BLK0_EN_STAT

RIO_BLK1_EN

RIO_BLK1_EN_STAT

BLK2_EN

Peripheral Global Enable Register

Peripheral Global Enable Status

Block Enable 0

02D0 0034

02D0 0038

02D0 003C

02D0 0040

Block Enable Status 0

Block Enable 1

02D0 0044

Block Enable Status 1

Block Enable 2

02D0 0048

02D0 004C

02D0 0050

BLK2_EN_STAT

BLK3_EN

Block Enable Status 2

Block Enable 3

02D0 0054

BLK3_EN_STAT

BLK4_EN

Block Enable Status 3

Block Enable 4

02D0 0058

02D0 005C

02D0 0060

BLK4_EN_STAT

BLK5_EN

Block Enable Status 4

Block Enable 5

02D0 0064

BLK5_EN_STAT

BLK6_EN

Block Enable Status 5

Block Enable 6

02D0 0068

02D0 006C

02D0 0070

BLK6_EN_STAT

BLK7_EN

Block Enable Status 6

Block Enable 7

02D0 0074

BLK7_EN_STAT

BLK8_EN

Block Enable Status 7

Block Enable 8

02D0 0078

02D0 007C

02D0 0080

BLK8_EN_STAT

DEVICEID_REG1

DEVICEID_REG2

DEVICEID_REG3

Block Enable Status 8

RapidIO DEVICEID1 Register

RapidIO DEVICEID2 Register

RapidIO DEVICEID3 Register

02D0 0084

02D0 0088

Specifications

151

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Table 4-96. RapidIO Control Registers (continued)

HEX ADDRESS RANGE

02D0 008C

02D0 0090

02D0 0094

02D0 0098

02D0 009C

02D0 00A0

02D0 00A4

02D0 00A8

02D0 00AC

02D0 00B0 - 02D0 00FC

02D0 0100

02D0 0104

02D0 0108

02D0 010C

02D0 0110

02D0 0114

02D0 0118

02D0 011C

02D0 0120

02D0 0124

02D0 0128

02D0 012C

02D0 0130 - 02D0 01FC

02D0 0200

02D0 0204

02D0 0208

02D0 020C

02D0 0210

02D0 0214

02D0 0218

02D0 021C

02D0 0220

02D0 0224

02D0 0228

02D0 022C

02D0 0230

02D0 0234

02D0 0238

02D0 023C

02D0 0240

02D0 0244

02D0 0248

02D0 024c

ACRONYM

REGISTER NAME

DEVICEID_REG4

RapidIO DEVICEID4 Register

PF_16B_CNTL0

Packet Forwarding Register 0 for 16-bit Device IDs

Packet Forwarding Register 0 for 8-bit Device IDs

Packet Forwarding Register 1 for 16-bit Device IDs

Packet Forwarding Register 1 for 8-bit Device IDs

Packet Forwarding Register 2 for 16-bit Device IDs

Packet Forwarding Register 2 for 8-bit Device IDs

Packet Forwarding Register 3 for 16-bit Device IDs

Packet Forwarding Register 3 for 8-bit Device IDs

Reserved

PF_8B_CNTL0

PF_16B_CNTL1

PF_8B_CNTL1

PF_16B_CNTL2

PF_8B_CNTL2

PF_16B_CNTL3

PF_8B_CNTL3

-

SERDES_CFGRX0_CNTL

SerDes Receive Channel Configuration Register 0

SerDes Receive Channel Configuration Register 1

SerDes Receive Channel Configuration Register 2

SerDes Receive Channel Configuration Register 3

SerDes Transmit Channel Configuration Register 0

SerDes Transmit Channel Configuration Register 1

SerDes Transmit Channel Configuration Register 2

SerDes Transmit Channel Configuration Register 3

SerDes Macro Configuration Register 0

SerDes Macro Configuration Register 1

SerDes Macro Configuration Register 2

SerDes Macro Configuration Register 3

Reserved

SERDES_CFGRX1_CNTL

SERDES_CFGRX2_CNTL

SERDES_CFGRX3_CNTL

SERDES_CFGTX0_CNTL

SERDES_CFGTX1_CNTL

SERDES_CFGTX2_CNTL

SERDES_CFGTX3_CNTL

SERDES_CFG0_CNTL

SERDES_CFG1_CNTL

SERDES_CFG2_CNTL

SERDES_CFG3_CNTL

-

DOORBELL0_ICSR

DOORBELL Interrupt Condition Status Register 0

Reserved

-

DOORBELL0_ICCR

DOORBELL Interrupt Condition Clear Register 0

Reserved

-

DOORBELL1_ICSR

DOORBELL Interrupt Condition Status Register 1

Reserved

-

DOORBELL1_ICCR

DOORBELL Interrupt Condition Clear Register 1

Reserved

-

DOORBELL2_ICSR

DOORBELL Interrupt Condition Status Register 2

Reserved

-

DOORBELL2_ICCR

DOORBELL Interrupt Condition Clear Register 2

Reserved

-

DOORBELL3_ICSR

DOORBELL Interrupt Condition Status Register 3

Reserved

-

DOORBELL3_ICCR

DOORBELL Interrupt Condition Clear Register 3

Reserved

-

RX_CPPI_ICSR

RX CPPI Interrupt Condition Status Register

Reserved

-

RX_CPPI_ICCR

RX CPPI Interrupt Condition Clear Register

Reserved

-

02D0 0250

02D0 0254

02D0 0258

02D0 025C

TX_CPPI_ICSR

TX CPPI Interrupt Condition Status Register

Reserved

-

TX_CPPI_ICCR

-

TX CPPI Interrupt Condition Clear Register

Reserved

152

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Table 4-96. RapidIO Control Registers (continued)

HEX ADDRESS RANGE

02D0 0260

ACRONYM

LSU_ICSR

REGISTER NAME

LSU Interrupt Condition Status Register

Reserved

02D0 0264

-

02D0 0268

LSU_ICCR

LSU Interrupt Condition Clear Register

Reserved

02D0 026C

-

02D0 0270

ERR_RST_EVNT_ICSR

-

Error, Reset, and Special Event Interrupt Condition Status Register

Reserved

02D0 0274

02D0 0278

ERR_RST_EVNT_ICCR

-

Error, Reset, and Special Event Interrupt Condition Clear Register

Reserved

02D0 027C

02D0 0280

DOORBELL0_ICRR

DOORBELL0_ICRR2

-

DOORBELL0 Interrupt Condition Routing Register

DOORBELL 0 Interrupt Condition Routing Register 2

Reserved

02D0 0284

02D0 0288 - 02D0 028C

02D0 0290

DOORBELL1_ICRR

DOORBELL1_ICRR2

-

DOORBELL1 Interrupt Condition Routing Register

DOORBELL 1 Interrupt Condition Routing Register 2

Reserved

02D0 0294

02D0 0298 - 02D0 029C

02D0 02A0

DOORBELL2_ICRR

DOORBELL2_ICRR2

-

DOORBELL2 Interrupt Condition Routing Register

DOORBELL 2 Interrupt Condition Routing Register 2

Reserved

02D0 02A4

02D0 02A8 - 02D0 02AC

02D0 02B0

DOORBELL3_ICRR

DOORBELL3_ICRR2

-

DOORBELL3 Interrupt Condition Routing Register

DOORBELL 3 Interrupt Condition Routing Register 2

Reserved

02D0 02B4

02D0 02B8 - 02D0 02BC

02D0 02C0

RX_CPPI_ICRR

RX_CPPI_ICRR2

-

Receive CPPI Interrupt Condition Routing Register

Receive CPPI Interrupt Condition Routing Register 2

Reserved

02D0 02C4

02D0 02C8 - 02D0 02CC

02D0 02D0

TX_CPPI_ICRR

TX_CPPI_ICRR2

-

Transmit CPPI Interrupt Condition Routing Register

Transmit CPPI Interrupt Condition Routing Register 2

Reserved

02D0 02D4

02D0 02D8 - 02D0 02DC

02D0 02E0

LSU_ICRR0

LSU Interrupt Condition Routing Register 0

LSU Interrupt Condition Routing Register 1

LSU Interrupt Condition Routing Register 2

LSU Interrupt Condition Routing Register 3

Error, Reset, and Special Event Interrupt Condition Routing Register

Error, Reset, and Special Event Interrupt Condition Routing Register 2

Error, Reset, and Special Event Interrupt Condition Routing Register 3

Reserved

02D0 02E4

LSU_ICRR1

02D0 02E8

LSU_ICRR2

02D0 02EC

LSU_ICRR3

02D0 02F0

ERR_RST_EVNT_ICRR

ERR_RST_EVNT_ICRR2

ERR_RST_EVNT_ICRR3

-

02D0 02F4

02D0 02F8

02D0 02FC

02D0 0300

INTDST0_DECODE

INTDST1_DECODE

INTDST2_DECODE

INTDST3_DECODE

INTDST4_DECODE

INTDST5_DECODE

INTDST6_DECODE

INTDST7_DECODE

INTDST0_RATE_CNTL

INTDST1_RATE_CNTL

INTDST2_RATE_CNTL

INTDST3_RATE_CNTL

INTDST4_RATE_CNTL

INTDST Interrupt Status Decode Register 0

INTDST Interrupt Status Decode Register 1

INTDST Interrupt Status Decode Register 2

INTDST Interrupt Status Decode Register 3

INTDST Interrupt Status Decode Register 4

INTDST Interrupt Status Decode Register 5

INTDST Interrupt Status Decode Register 6

INTDST Interrupt Status Decode Register 7

INTDST Interrupt Rate Control Register 0

INTDST Interrupt Rate Control Register 1

INTDST Interrupt Rate Control Register 2

INTDST Interrupt Rate Control Register 3

INTDST Interrupt Rate Control Register 4

02D0 0304

02D0 0308

02D0 030C

02D0 0310

02D0 0314

02D0 0318

02D0 031C

02D0 0320

02D0 0324

02D0 0328

02D0 032C

02D0 0330

Specifications

153

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Table 4-96. RapidIO Control Registers (continued)

HEX ADDRESS RANGE

02D0 0334

02D0 0338

02D0 033C

02D0 0340 - 02D0 03FC

02D0 0400

02D0 0404

02D0 0408

02D0 040C

02D0 0410

02D0 0414

02D0 0418

02D0 041C

02D0 0420

02D0 0424

02D0 0428

02D0 042C

02D0 0430

02D0 0434

02D0 0438

02D0 043C

02D0 0440

02D0 0444

02D0 0448

02D0 044C

02D0 0450

02D0 0454

02D0 0458

02D0 045C

02D0 0460

02D0 0464

02D0 0468

02D0 046C

02D0 0470

02D0 0474

02D0 0478

02D0 047C

02D0 0480 - 02D0 04FC

02D0 0500

02D0 0504

02D0 0508

02D0 050C

02D0 0510

02D0 0514

02D0 0518

02D0 051C

02D0 0520

02D0 0524

ACRONYM

INTDST5_RATE_CNTL

INTDST6_RATE_CNTL

INTDST7_RATE_CNTL

-

REGISTER NAME

INTDST Interrupt Rate Control Register 5

INTDST Interrupt Rate Control Register 6

INTDST Interrupt Rate Control Register 7

Reserved

LSU1_REG0

LSU1 Control Register 0

LSU1_REG1

LSU1 Control Register 1

LSU1_REG2

LSU1 Control Register 2

LSU1_REG3

LSU1 Control Register 3

LSU1_REG4

LSU1 Control Register 4

LSU1_REG5

LSU1 Control Register 5

LSU1_REG6

LSU1 Control Register 6

LSU1_FLOW_MASKS1

LSU2_REG0

LSU1 Congestion Control Flow Mask Register

LSU2 Control Register 0

LSU2_REG1

LSU2 Control Register 1

LSU2_REG2

LSU2 Control Register 2

LSU2_REG3

LSU2 Control Register 3

LSU2_REG4

LSU2 Control Register 4

LSU2_REG5

LSU2 Control Register 5

LSU2_REG6

LSU2 Control Register 6

LSU2_FLOW_MASKS2

LSU3_REG0

LSU2 Congestion Control Flow Mask Register

LSU3 Control Register 0

LSU3_REG1

LSU3 Control Register 1

LSU3_REG2

LSU3 Control Register 2

LSU3_REG3

LSU3 Control Register 3

LSU3_REG4

LSU3 Control Register 4

LSU3_REG5

LSU3 Control Register 5

LSU3_REG6

LSU3 Control Register 6

LSU3_FLOW_MASKS3

LSU4_REG0

LSU3 Congestion Control Flow Mask Register

LSU4 Control Register 0

LSU4_REG1

LSU4 Control Register 1

LSU4_REG2

LSU4 Control Register 2

LSU4_REG3

LSU4 Control Register 3

LSU4_REG4

LSU4 Control Register 4

LSU4_REG5

LSU4 Control Register 5

LSU4_REG6

LSU4 Control Register 6

LSU4_FLOW_MASKS4

-

LSU4 Congestion Control Flow Mask Register

Reserved

QUEUE0_TXDMA_HDP

QUEUE1_TXDMA_HDP

QUEUE2_TXDMA_HDP

QUEUE3_TXDMA_HDP

QUEUE4_TXDMA_HDP

QUEUE5_TXDMA_HDP

QUEUE6_TXDMA_HDP

QUEUE7_TXDMA_HDP

QUEUE8_TXDMA_HDP

QUEUE9_TXDMA_HDP

Queue Transmit DMA Head Descriptor Pointer Register 0

Queue Transmit DMA Head Descriptor Pointer Register 1

Queue Transmit DMA Head Descriptor Pointer Register 2

Queue Transmit DMA Head Descriptor Pointer Register 3

Queue Transmit DMA Head Descriptor Pointer Register 4

Queue Transmit DMA Head Descriptor Pointer Register 5

Queue Transmit DMA Head Descriptor Pointer Register 6

Queue Transmit DMA Head Descriptor Pointer Register 7

Queue Transmit DMA Head Descriptor Pointer Register 8

Queue Transmit DMA Head Descriptor Pointer Register 9

154

Specifications

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ZHCSFA5 –JULY 2016

Table 4-96. RapidIO Control Registers (continued)

HEX ADDRESS RANGE

02D0 0528

ACRONYM

REGISTER NAME

QUEUE10_TXDMA_HDP

QUEUE11_TXDMA_HDP

QUEUE12_TXDMA_HDP

QUEUE13_TXDMA_HDP

QUEUE14_TXDMA_HDP

QUEUE15_TXDMA_HDP

-

Queue Transmit DMA Head Descriptor Pointer Register 10

Queue Transmit DMA Head Descriptor Pointer Register 11

Queue Transmit DMA Head Descriptor Pointer Register 12

Queue Transmit DMA Head Descriptor Pointer Register 13

Queue Transmit DMA Head Descriptor Pointer Register 14

Queue Transmit DMA Head Descriptor Pointer Register 15

Reserved

02D0 052C

02D0 0530

02D0 0534

02D0 0538

02D0 053C

02D0 0540 - 02D0 057C

02D0 0580

QUEUE0_TXDMA_CP

QUEUE1_TXDMA_CP

QUEUE2_TXDMA_CP

QUEUE3_TXDMA_CP

QUEUE4_TXDMA_CP

QUEUE5_TXDMA_CP

QUEUE6_TXDMA_CP

QUEUE7_TXDMA_CP

QUEUE8_TXDMA_CP

QUEUE9_TXDMA_CP

QUEUE10_TXDMA_CP

QUEUE11_TXDMA_CP

QUEUE12_TXDMA_CP

QUEUE13_TXDMA_CP

QUEUE14_TXDMA_CP

QUEUE15_TXDMA_CP

-

Queue Transmit DMA Completion Pointer Register 0

Queue Transmit DMA Completion Pointer Register 1

Queue Transmit DMA Completion Pointer Register 2

Queue Transmit DMA Completion Pointer Register 3

Queue Transmit DMA Completion Pointer Register 4

Queue Transmit DMA Completion Pointer Register 5

Queue Transmit DMA Completion Pointer Register 6

Queue Transmit DMA Completion Pointer Register 7

Queue Transmit DMA Completion Pointer Register 8

Queue Transmit DMA Completion Pointer Register 9

Queue Transmit DMA Completion Pointer Register 10

Queue Transmit DMA Completion Pointer Register 11

Queue Transmit DMA Completion Pointer Register 12

Queue Transmit DMA Completion Pointer Register 13

Queue Transmit DMA Completion Pointer Register 14

Queue Transmit DMA Completion Pointer Register 15

Reserved

02D0 0584

02D0 0588

02D0 058C

02D0 0590

02D0 0594

02D0 0598

02D0 059C

02D0 05A0

02D0 05A4

02D0 05A8

02D0 05AC

02D0 05B0

02D0 05B4

02D0 05B8

02D0 05BC

02D0 05D0 - 02D0 05FC

02D0 0600

QUEUE0_RXDMA_HDP

QUEUE1_RXDMA_HDP

QUEUE2_RXDMA_HDP

QUEUE3_RXDMA_HDP

QUEUE4_RXDMA_HDP

QUEUE5_RXDMA_HDP

QUEUE6_RXDMA_HDP

QUEUE7_RXDMA_HDP

QUEUE8_RXDMA_HDP

QUEUE9_RXDMA_HDP

QUEUE10_RXDMA_HDP

QUEUE11_RXDMA_HDP

QUEUE12_RXDMA_HDP

QUEUE13_RXDMA_HDP

QUEUE14_RXDMA_HDP

QUEUE15_RXDMA_HDP

-

Queue Receive DMA Head Descriptor Pointer Register 0

Queue Receive DMA Head Descriptor Pointer Register 1

Queue Receive DMA Head Descriptor Pointer Register 2

Queue Receive DMA Head Descriptor Pointer Register 3

Queue Receive DMA Head Descriptor Pointer Register 4

Queue Receive DMA Head Descriptor Pointer Register 5

Queue Receive DMA Head Descriptor Pointer Register 6

Queue Receive DMA Head Descriptor Pointer Register 7

Queue Receive DMA Head Descriptor Pointer Register 8

Queue Receive DMA Head Descriptor Pointer Register 9

Queue Receive DMA Head Descriptor Pointer Register 10

Queue Receive DMA Head Descriptor Pointer Register 11

Queue Receive DMA Head Descriptor Pointer Register 12

Queue Receive DMA Head Descriptor Pointer Register 13

Queue Receive DMA Head Descriptor Pointer Register 14

Queue Receive DMA Head Descriptor Pointer Register 15

Reserved

02D0 0604

02D0 0608

02D0 060C

02D0 0610

02D0 0614

02D0 0618

02D0 061C

02D0 0620

02D0 0624

02D0 0628

02D0 062C

02D0 0630

02D0 0634

02D0 0638

02D0 063C

02D0 0640 - 02D0 067C

02D0 0680

QUEUE0_RXDMA_CP

QUEUE1_RXDMA_CP

QUEUE2_RXDMA_CP

QUEUE3_RXDMA_CP

QUEUE4_RXDMA_CP

QUEUE5_RXDMA_CP

Queue Receive DMA Completion Pointer Register 0

Queue Receive DMA Completion Pointer Register 1

Queue Receive DMA Completion Pointer Register 2

Queue Receive DMA Completion Pointer Register 3

Queue Receive DMA Completion Pointer Register 4

Queue Receive DMA Completion Pointer Register 5

02D0 0684

02D0 0688

02D0 068C

02D0 0690

02D0 0694

Specifications

155

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Table 4-96. RapidIO Control Registers (continued)

HEX ADDRESS RANGE

02D0 0698

ACRONYM

QUEUE6_RXDMA_CP

QUEUE7_RXDMA_CP

QUEUE8_RXDMA_CP

QUEUE9_RXDMA_CP

QUEUE10_RXDMA_CP

QUEUE11_RXDMA_CP

QUEUE12_RXDMA_CP

QUEUE13_RXDMA_CP

QUEUE14_RXDMA_CP

QUEUE15_RXDMA_CP

-

REGISTER NAME

Queue Receive DMA Completion Pointer Register 6

Queue Receive DMA Completion Pointer Register 7

Queue Receive DMA Completion Pointer Register 8

Queue Receive DMA Completion Pointer Register 9

Queue Receive DMA Completion Pointer Register 10

Queue Receive DMA Completion Pointer Register 11

Queue Receive DMA Completion Pointer Register 12

Queue Receive DMA Completion Pointer Register 13

Queue Receive DMA Completion Pointer Register 14

Queue Receive DMA Completion Pointer Register 15

Reserved

02D0 069C

02D0 06A0

02D0 06A4

02D0 06A8

02D0 06AC

02D0 06B0

02D0 06B4

02D0 06B8

02D0 06BC

02D0 06C0 - 02D0 006FC

02D0 0700

TX_QUEUE_TEAR_DOWN

TX_CPPI_FLOW_MASKS0

TX_CPPI_FLOW_MASKS1

TX_CPPI_FLOW_MASKS2

TX_CPPI_FLOW_MASKS3

TX_CPPI_FLOW_MASKS4

TX_CPPI_FLOW_MASKS5

TX_CPPI_FLOW_MASKS6

TX_CPPI_FLOW_MASKS7

-

Transmit Queue Teardown Register

02D0 0704

Transmit CPPI Supported Flow Mask Register 0

Transmit CPPI Supported Flow Mask Register 1

Transmit CPPI Supported Flow Mask Register 2

Transmit CPPI Supported Flow Mask Register 3

Transmit CPPI Supported Flow Mask Register 4

Transmit CPPI Supported Flow Mask Register 5

Transmit CPPI Supported Flow Mask Register 6

Transmit CPPI Supported Flow Mask Register 7

Reserved

02D0 0708

02D0 070C

02D0 0710

02D0 0714

02D0 0718

02D0 071C

02D0 0720

02D0 0724 - 02D0 073C

02D0 0740

RX_QUEUE_TEAR_DOWN

RX_CPPI_CNTL

Receive Queue Teardown Register

02D0 0744

Receive CPPI Control Register

02D0 0748 - 02D0 07DC

02D0 07E0

-

Reserved

TX_QUEUE_CNTL0

TX_QUEUE_CNTL1

TX_QUEUE_CNTL2

TX_QUEUE_CNTL3

-

Transmit CPPI Weighted Round Robin Control Register 0

Transmit CPPI Weighted Round Robin Control Register 1

Transmit CPPI Weighted Round Robin Control Register 2

Transmit CPPI Weighted Round Robin Control Register 3

Reserved

02D0 07E4

02D0 07E8

02D0 07EC

02D0 07F0 - 02D0 07FC

02D0 0800

RXU_MAP_L0

Mailbox-to-Queue Mapping Register L0

Mailbox-to-Queue Mapping Register H0

Mailbox-to-Queue Mapping Register L1

Mailbox-to-Queue Mapping Register H1

Mailbox-to-Queue Mapping Register L2

Mailbox-to-Queue Mapping Register H2

Mailbox-to-Queue Mapping Register L3

Mailbox-to-Queue Mapping Register H3

Mailbox-to-Queue Mapping Register L4

Mailbox-to-Queue Mapping Register H4

Mailbox-to-Queue Mapping Register L5

Mailbox-to-Queue Mapping Register H5

Mailbox-to-Queue Mapping Register L6

Mailbox-to-Queue Mapping Register H6

Mailbox-to-Queue Mapping Register L7

Mailbox-to-Queue Mapping Register H7

Mailbox-to-Queue Mapping Register L8

Mailbox-to-Queue Mapping Register H8

02D0 0804

RXU_MAP_H0

02D0 0808

RXU_MAP_L1

02D0 080C

RXU_MAP_H1

02D0 0810

RXU_MAP_L2

02D0 0814

RXU_MAP_H2

02D0 0818

RXU_MAP_L3

02D0 081C

RXU_MAP_H3

02D0 0820

RXU_MAP_L4

02D0 0824

RXU_MAP_H4

02D0 0828

RXU_MAP_L5

02D0 082C

RXU_MAP_H5

02D0 0830

RXU_MAP_L6

02D0 0834

RXU_MAP_H6

02D0 0838

RXU_MAP_L7

02D0 083C

RXU_MAP_H7

02D0 0840

RXU_MAP_L8

02D0 0844

RXU_MAP_H8

156

Specifications

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Table 4-96. RapidIO Control Registers (continued)

HEX ADDRESS RANGE

02D0 0848

02D0 084C

02D0 0850

02D0 0854

02D0 0858

02D0 085C

02D0 0860

02D0 0864

02D0 0868

02D0 086C

02D0 0870

02D0 0874

02D0 0878

02D0 087C

02D0 0880

02D0 0884

02D0 0888

02D0 088C

02D0 0890

02D0 0894

02D0 0898

02D0 089C

02D0 08A0

02D0 08A4

02D0 08A8

02D0 08AC

02D0 08B0

02D0 08B4

02D0 08B8

02D0 08BC

02D0 08C0

02D0 08C4

02D0 08C8

02D0 08CC

02D0 08D0

02D0 08D4

02D0 08D8

02D0 08DC

02D0 08E0

02D0 08E4

02D0 08E8

02D0 08EC

02D0 08F0

02D0 08F4

02D0 08F8

02D0 08FC

02D0 0900

ACRONYM

REGISTER NAME

RXU_MAP_L9

RXU_MAP_H9

RXU_MAP_L10

RXU_MAP_H10

RXU_MAP_L11

RXU_MAP_H11

RXU_MAP_L12

RXU_MAP_H12

RXU_MAP_L13

RXU_MAP_H13

RXU_MAP_L14

RXU_MAP_H14

RXU_MAP_L15

RXU_MAP_H15

RXU_MAP_L16

RXU_MAP_H16

RXU_MAP_L17

RXU_MAP_H17

RXU_MAP_L18

RXU_MAP_H18

RXU_MAP_L19

RXU_MAP_H19

RXU_MAP_L20

RXU_MAP_H20

RXU_MAP_L21

RXU_MAP_H21

RXU_MAP_L22

RXU_MAP_H22

RXU_MAP_L23

RXU_MAP_H23

RXU_MAP_L24

RXU_MAP_H24

RXU_MAP_L25

RXU_MAP_H25

RXU_MAP_L26

RXU_MAP_H26

RXU_MAP_L27

RXU_MAP_H27

RXU_MAP_L28

RXU_MAP_H28

RXU_MAP_L29

RXU_MAP_H29

RXU_MAP_L30

RXU_MAP_H30

RXU_MAP_L31

RXU_MAP_H31

FLOW_CNTL0

Mailbox-to-Queue Mapping Register L9

Mailbox-to-Queue Mapping Register H9

Mailbox-to-Queue Mapping Register L10

Mailbox-to-Queue Mapping Register H10

Mailbox-to-Queue Mapping Register L11

Mailbox-to-Queue Mapping Register H11

Mailbox-to-Queue Mapping Register L12

Mailbox-to-Queue Mapping Register H12

Mailbox-to-Queue Mapping Register L13

Mailbox-to-Queue Mapping Register H13

Mailbox-to-Queue Mapping Register L14

Mailbox-to-Queue Mapping Register H14

Mailbox-to-Queue Mapping Register L15

Mailbox-to-Queue Mapping Register H15

Mailbox-to-Queue Mapping Register L16

Mailbox-to-Queue Mapping Register H16

Mailbox-to-Queue Mapping Register L17

Mailbox-to-Queue Mapping Register H17

Mailbox-to-Queue Mapping Register L18

Mailbox-to-Queue Mapping Register H18

Mailbox-to-Queue Mapping Register L19

Mailbox-to-Queue Mapping Register H19

Mailbox-to-Queue Mapping Register L20

Mailbox-to-Queue Mapping Register H20

Mailbox-to-Queue Mapping Register L21

Mailbox-to-Queue Mapping Register H21

Mailbox-to-Queue Mapping Register L22

Mailbox-to-Queue Mapping Register H22

Mailbox-to-Queue Mapping Register L23

Mailbox-to-Queue Mapping Register H23

Mailbox-to-Queue Mapping Register L24

Mailbox-to-Queue Mapping Register H24

Mailbox-to-Queue Mapping Register L25

Mailbox-to-Queue Mapping Register H25

Mailbox-to-Queue Mapping Register L26

Mailbox-to-Queue Mapping Register H26

Mailbox-to-Queue Mapping Register L27

Mailbox-to-Queue Mapping Register H27

Mailbox-to-Queue Mapping Register L28

Mailbox-to-Queue Mapping Register H28

Mailbox-to-Queue Mapping Register L29

Mailbox-to-Queue Mapping Register H29

Mailbox-to-Queue Mapping Register L30

Mailbox-to-Queue Mapping Register H30

Mailbox-to-Queue Mapping Register L31

Mailbox-to-Queue Mapping Register H31

Flow Control Table Entry Register 0

Specifications

157

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Table 4-96. RapidIO Control Registers (continued)

HEX ADDRESS RANGE

02D0 0904

ACRONYM

FLOW_CNTL1

FLOW_CNTL2

FLOW_CNTL3

FLOW_CNTL4

FLOW_CNTL5

FLOW_CNTL6

FLOW_CNTL7

FLOW_CNTL8

FLOW_CNTL9

FLOW_CNTL10

FLOW_CNTL11

FLOW_CNTL12

FLOW_CNTL13

FLOW_CNTL14

FLOW_CNTL15

-

REGISTER NAME

Flow Control Table Entry Register 1

Flow Control Table Entry Register 2

Flow Control Table Entry Register 3

Flow Control Table Entry Register 4

Flow Control Table Entry Register 5

Flow Control Table Entry Register 6

Flow Control Table Entry Register 7

Flow Control Table Entry Register 8

Flow Control Table Entry Register 9

Flow Control Table Entry Register 10

Flow Control Table Entry Register 11

Flow Control Table Entry Register 12

Flow Control Table Entry Register 13

Flow Control Table Entry Register 14

Flow Control Table Entry Register 15

Reserved

02D0 0908

02D0 090C

02D0 0910

02D0 0914

02D0 0918

02D0 091C

02D0 0920

02D0 0924

02D0 0928

02D0 092C

02D0 0930

02D0 0934

02D0 0938

02D0 093C

02D0 0940 - 02D0 09FC

RapidIO Peripheral-Specific Registers

02D0 1000

02D0 1004

DEV_ID

Device Identity CAR

DEV_INFO

Device Information CAR

Assembly Identity CAR

Assembly Information CAR

Processing Element Features CAR

Reserved

02D0 1008

ASBLY_ID

02D0 100C

ASBLY_INFO

02D0 1010

PE_FEAT

02D0 1014

-

02D0 1018

SRC_OP

Source Operations CAR

Destination Operations CAR

Reserved

02D0 101C

DEST_OP

02D0 1020 - 02D0 1048

02D0 104C

-

PE_LL_CTL

Processing Element Logical Layer Control CSR

Reserved

02D0 1050 - 02D0 1054

02D0 1058

-

LCL_CFG_HBAR

LCL_CFG_BAR

BASE_ID

Local Configuration Space Base Address 0 CSR

Local Configuration Space Base Address 1 CSR

Base Device ID CSR

02D0 105C

02D0 1060

02D0 1064

-

Reserved

02D0 1068

HOST_BASE_ID_LOCK

COMP_TAG

-

Host Base Device ID Lock CSR

Component Tag CSR

02D0 106C

02D0 1070 - 02D0 10FC

Reserved

RapidIO Extended Features -LP Serial Registers

02D0 1100

02D0 1104 - 02D0 1118

02D0 1120

SP_MB_HEAD

-

1×/4× LP Serial Port Maintenance Block Header

Reserved

SP_LT_CTL

SP_RT_CTL

-

Port Link Time-Out Control CSR

Port Response Time-Out Control CSR

Reserved

02D0 1124

02D0 1128 - 02D0 1138

02D0 113C

SP_GEN_CTL

SP0_LM_REQ

SP0_LM_RESP

SP0_ACKID_STAT

-

Port General Control CSR

02D0 1140

Port 0 Link Maintenance Request CSR

Port 0 Link Maintenance Response CSR

Port 0 Local Acknowledge ID Status CSR

Reserved

02D0 1144

02D0 1148

02D0 114C - 02D0 1154

02D0 1158

SP0_ERR_STAT

Port 0 Error and Status CSR

158

Specifications

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Table 4-96. RapidIO Control Registers (continued)

HEX ADDRESS RANGE

02D0 115C

ACRONYM

SP0_CTL

REGISTER NAME

Port 0 Control CSR

02D0 1160

SP1_LM_REQ

SP1_LM_RESP

SP1_ACKID_STAT

-

Port 1 Link Maintenance Request CSR

Port 1 Link Maintenance Response CSR

Port 1 Local Acknowledge ID Status CSR

Reserved

02D0 1164

02D0 1168

02D0 116C - 02D0 1174

02D0 1178

SP1_ERR_STAT

SP1_CTL

Port 1 Error and Status CSR

Port 1 Control CSR

02D0 117C

02D0 1180

SP2_LM_REQ

SP2_LM_RESP

SP2_ACKID_STAT

-

Port 2 Link Maintenance Request CSR

Port 2 Link Maintenance Response CSR

Port 2 Local Acknowledge ID Status CSR

Reserved

02D0 1184

02D0 1188

02D0 118C - 02D0 1194

02D0 1198

SP2_ERR_STAT

SP2_CTL

Port 2 Error and Status CSR

Port 2 Control CSR

02D0 119C

02D0 11A0

SP3_LM_REQ

SP3_LM_RESP

SP3_ACKID_STAT

-

Port 3 Link Maintenance Request CSR

Port 3 Link Maintenance Response CSR

Port 3 Local Acknowledge ID Status CSR

Reserved

02D0 11A4

02D0 11A8

02D0 11AC - 02D0 11B4

02D0 11B8

SP3_ERR_STAT

SP3_CTL

Port 3 Error and Status CSR

Port 3 Control CSR

02D0 11BC

02D0 11C0 -02D0 1FFC

-

Reserved

RapidIO Extended Feature -Error Management Registers

02D0 2000

02D0 2004

ERR_RPT_BH

-

Error Reporting Block Header

Reserved

02D0 2008

ERR_DET

ERR_EN

Logical/Transport Layer Error Detect CSR

Logical/Transport Layer Error Enable CSR

02D0 200C

02D0 2010

H_ADDR_CAPT

ADDR_CAPT

ID_CAPT

CTRL_CAPT

-

Logical/Transport Layer High Address Capture CSR

Logical/Transport Layer Address Capture CSR

Logical/Transport Layer Device ID Capture CSR

Logical/Transport Layer Control Capture CSR

Reserved

02D0 2014

02D0 2018

02D0 201C

02D0 2020 - 02D0 2024

02D0 2028

PW_TGT_ID

-

Port-Write Target Device ID CSR

Reserved

02D0 202C - 02D0 203C

02D0 2040

SP0_ERR_DET

SP0_RATE_EN

Port 0 Error Detect CSR

02D0 2044

Port 0 Error Enable CSR

02D0 2048

SP0_ERR_ATTR_CAPT_DBG0 Port 0 Attributes Error Capture CSR 0

02D0 204C

SP0_ERR_CAPT_DBG1

SP0_ERR_CAPT_DBG2

SP0_ERR_CAPT_DBG3

SP0_ERR_CAPT_DBG4

-

Port 0 Packet/Control Symbol Error Capture CSR 1

02D0 2050

Port 0 Packet/Control Symbol Error Capture CSR 2

Port 0 Packet/Control Symbol Error Capture CSR 3

Port 0 Packet/Control Symbol Error Capture CSR 4

Reserved

02D0 2054

02D0 2058

02D0 205C - 02D0 2064

02D0 2068

SP0_ERR_RATE

SP0_ERR_THRESH

-

Port 0 Error Rate CSR 0

02D0 206C

Port 0 Error Rate Threshold CSR

Reserved

02D0 2070 - 02D0 207C

02D0 2080

SP1_ERR_DET

SP1_RATE_EN

Port 1 Error Detect CSR

02D0 2084

Port 1 Error Enable CSR

02D0 2088

SP1_ERR_ATTR_CAPT_DBG0 Port 1 Attributes Error Capture CSR 0

SP1_ERR_CAPT_DBG1 Port 1 Packet/Control Symbol Error Capture CSR 1

02D0 208C

Specifications

159

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Table 4-96. RapidIO Control Registers (continued)

HEX ADDRESS RANGE

02D0 2090

ACRONYM

SP1_ERR_CAPT_DBG2

SP1_ERR_CAPT_DBG3

SP1_ERR_CAPT_DBG4

-

REGISTER NAME

Port 1 Packet/Control Symbol Error Capture CSR 2

Port 1 Packet/Control Symbol Error Capture CSR 3

Port 1 Packet/Control Symbol Error Capture CSR 4

Reserved

02D0 2094

02D0 2098

02D0 209C - 02D0 20A4

02D0 20A8

SP1_ERR_RATE

SP1_ERR_THRESH

-

Port 1 Error Rate CSR

02D0 20AC

Port 1 Error Rate Threshold CSR

Reserved

02D0 20B0 - 02D0 20BC

02D0 20C0

SP2_ERR_DET

SP2_RATE_EN

Port 2 Error Detect CSR

02D0 20C4

Port 2 Error Enable CSR

02D0 20C8

SP2_ERR_ATTR_CAPT_DBG0 Port 2 Attributes Error Capture CSR 0

02D0 20CC

SP2_ERR_CAPT_DBG1

SP2_ERR_CAPT_DBG2

SP2_ERR_CAPT_DBG3

SP2_ERR_CAPT_DBG4

-

Port 2 Packet/Control Symbol Error Capture CSR 1

02D0 20D0

Port 2 Packet/Control Symbol Error Capture CSR 2

Port 2 Packet/Control Symbol Error Capture CSR 3

Port 2 Packet/Control Symbol Error Capture CSR 4

Reserved

02D0 20D4

02D0 20D8

02D0 20DC - 02D0 20E4

02D0 20E8

SP2_ERR_RATE

SP2_ERR_THRESH

-

Port 2 Error Rate CSR

02D0 20EC

Port 2 Error Rate Threshold CSR

Reserved

02D0 20F0 - 02D0 20FC

02D0 2100

SP3_ERR_DET

SP3_RATE_EN

Port 3 Error Detect CSR

02D0 2104

Port 3 Error Enable CSR

02D0 2108

SP3_ERR_ATTR_CAPT_DBG0 Port 3 Attributes Error Capture CSR 0

02D0 210C

SP3_ERR_CAPT_DBG1

SP3_ERR_CAPT_DBG2

SP3_ERR_CAPT_DBG3

SP3_ERR_CAPT_DBG4

-

Port 3 Packet/Control Symbol Error Capture CSR 1

02D0 2110

Port 3 Packet/Control Symbol Error Capture CSR 2

Port 3 Packet/Control Symbol Error Capture CSR 3

Port 3 Packet/Control Symbol Error Capture CSR 4

Reserved

02D0 2114

02D0 2118

02D0 211C - 02D0 2124

02D0 2128

SP3_ERR_RATE

SP3_ERR_THRESH

-

Port 3 Error Rate CSR

02D0 212C

Port 3 Error Rate Threshold CSR

Reserved

02D0 2130 -02D1 0FFC

Implementation Registers

02D1 1000 - 02D1 1FFC

02D1 2000

-

Reserved

SP_IP_DISCOVERY_TIMER Port IP Discovery Timer in 4x mode

02D1 2004

SP_IP_MODE

IP_PRESCAL

-

Port IP Mode CSR

02D1 2008

Port IP Prescaler Register

Reserved

02D1 200C

02D1 2010

SP_IP_PW_IN_CAPT0

SP_IP_PW_IN_CAPT1

SP_IP_PW_IN_CAPT2

SP_IP_PW_IN_CAPT3

-

Port-Write-In Capture CSR Register 0

Port-Write-In Capture CSR Register 1

Port-Write-In Capture CSR Register 2

Port-Write-In Capture CSR Register 3

Reserved

02D1 2014

02D1 2018

02D1 201C

02D1 2020 - 02D1 3FFC

02D1 4000

SP0_RST_OPT

SP0_CTL_INDEP

SP0_SILENCE_TIMER

SP0_MULT_EVNT_CS

-

Port 0 Reset Option CSR

02D1 4004

Port 0 Control Independent Register

Port 0 Silence Timer Register

Port 0 Multicast-Event Control Symbol Request Register

Reserved

02D1 4008

02D1 400C

02D1 4010

02D1 4014

SP0_CS_TX

Port 0 Control Symbol Transmit Register

Reserved

02D1 4018 - 02D1 40FC

-

160

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Table 4-96. RapidIO Control Registers (continued)

HEX ADDRESS RANGE

02D1 4100

ACRONYM

SP1_RST_OPT

SP1_CTL_INDEP

SP1_SILENCE_TIMER

SP1_MULT_EVNT_CS

-

REGISTER NAME

Port 1 Reset Option CSR

Port 1 Control Independent Register

Port 1 Silence Timer Register

02D1 4104

02D1 4108

02D1 410C

Port 1 Multicast-Event Control Symbol Request Register

Reserved

02D1 4110

02D1 4114

SP1_CS_TX

-

Port 1 Control Symbol Transmit Register

Reserved

02D1 4118 - 02D1 41FC

02D1 4200

SP2_RST_OPT

SP2_CTL_INDEP

SP2_SILENCE_TIMER

SP2_MULT_EVNT_CS

SP2_CS_TX

-

Port 2 Reset Option CSR

02D1 4204

Port 2 Control Independent Register

Port 2 Silence Timer Register

Port 2 Multicast-Event Control Symbol Request Register

Port 2 Control Symbol Transmit Register

Reserved

02D1 4208

02D1 420C

02D1 4214

02D1 4218 - 02D1 42FC

02D1 4300

SP3_RST_OPT

SP3_CTL_INDEP

SP3_SILENCE_TIMER

SP3_MULT_EVNT_CS

-

Port 3 Reset Option CSR

02D1 4304

Port 3 Control Independent Register

Port 3 Silence Timer Register

Port 3 Multicast-Event Control Symbol Request Register

Reserved

02D1 4308

02D1 430C

02D1 4310

02D1 4314

SP3_CS_TX

-

Port 3 Control Symbol Transmit Register

Reserved

02D1 4318 - 02D2 0FFF

02D2 1000 - 02DF FFFF

-

Reserved

4.8.17.3 Serial RapidIO Electrical Data/Timing

The TMS320TCI6484 and TMS320C6457 SerDes Implementation Guidelines application report

(SPRAAY1) specifies a complete printed circuit board (PCB) solution for the C6457 as well as a list of

compatible SRIO devices showing two DSPs connected via a 4× SRIO link. TI has performed the

simulation and system characterization to ensure all SRIO interface timings in this solution are met;

therefore, no electrical data/timing information is supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application

report.

Serial RapidIO is electrically compliant with the RapidIO™ Interconnect Specification, Part VI: Physical

Layer 1×/4× LP-Serial Specification, Revision 1.3.

Specifications

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4.8.18 General-Purpose Input/Output (GPIO)

4.8.18.1 GPIO Device-Specific Information

On the C6457, the GPIO peripheral pins GP[15:0] are also used to latch configuration pins. For more

detailed information on device/peripheral configuration and the C6457 device pin muxing, see Section 5.5.

4.8.18.2 GPIO Peripheral Register Description(s)

Table 4-97. GPIO Registers

HEX ADDRESS RANGE

02B0 0008

ACRONYM

REGISTER NAME

BINTEN

GPIO interrupt per bank enable register

Reserved

02B0 000C

-

02B0 0010

DIR

GPIO Direction Register

GPIO Output Data register

GPIO Set Data register

02B0 0014

OUT_DATA

SET_DATA

CLR_DATA

IN_DATA

SET_RIS_TRIG

CLR_RIS_TRIG

SET_FAL_TRIG

CLR_FAL_TRIG

-

02B0 0018

02B0 001C

GPIO Clear Data Register

GPIO Input Data Register

GPIO Set Rising Edge Interrupt Register

GPIO Clear Rising Edge Interrupt Register

GPIO Set Falling Edge Interrupt Register

GPIO Clear Falling Edge Interrupt Register

Reserved

02B0 0020

02B0 0024

02B0 0028

02B0 002C

02B0 0030

02B0 008C

02B0 0090 - 02B0 00FF

02B0 0100 - 02B0 3FFF

-

Reserved

-

Reserved

4.8.18.3 GPIO Electrical Data/Timing

Table 4-98. GPIO Input Timing Requirements⁽¹⁾

(see Figure 4-66)

NO.

MIN

12C

MAX UNIT

1

2

t_w(GPOH)

t_w(GPOL)

Pulse duration, GPOx high

Pulse duration, GPOx low

ns

(1) If CORECLKSEL = 0, C = 1 ÷ CORECLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1 ÷ ALTCORECLK frequency, in ns.

Table 4-99. GPIO Output Switching Characteristics⁽¹⁾⁽²⁾

(see Figure 4-66)

NO. PARAMETER

MIN

12C - 3

MAX UNIT

1

2

t_w(GPOH)

t_w(GPOL)

Pulse duration, GPOx high

Pulse duration, GPOx low

ns

(1) Over recommended operating conditions.

(2) If CORECLKSEL = 0, C = 1 ÷ CORECLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1 ÷ ALTCORECLK frequency, in ns.

2

1

GPIx

4

3

GPOx

Figure 4-66. GPIO Timing

162

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4.8.19 Emulation Features and Capability

4.8.19.1 Advanced Event Triggering (AET)

The C6457 device supports Advanced Event Triggering (AET). This capability can be used to debug

complex problems as well as understand performance characteristics of user applications. AET provides

the following capabilities:

•

Hardware Program Breakpoints: specify addresses or address ranges that can generate events such

as halting the processor or triggering the trace capture.

•

Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate

events such as halting the processor or triggering the trace capture.

•

Counters: count the occurrence of an event or cycles for performance monitoring.

State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to

precisely generate events for complex sequences.

For more information on AET, see the following documents:

•

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report

(SPRA753)

•

Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded

Microprocessor Systems application report (SPRA387)

4.8.19.2 Trace

The C6457 device supports Trace. Trace is a debug technology that provides a detailed, historical

account of application code execution, timing, and data accesses. Trace collects, compresses, and

exports debug information for analysis. Trace works in real-time and does not impact the execution of the

system.

For more information on board design guidelines for Trace Advanced Emulation, see the 60-Pin Emulation

Header Technical Reference (SPRU655).

4.8.19.2.1 Trace Electrical Data/Timing

(1)

Table 4-100. Switching Characteristics for Trace

(see Figure 4-67)

NO. PARAMETER

MIN

2.4

1.5

2.4

1.5

MAX UNIT

1

2

t_w(DPnH)

Pulse duration, DPn/EMUn high

ns

t_w(DPnH)90%

t_w(DPnL)

Pulse duration, DPn/EMUn high detected at 90% Voh

Pulse duration, DPn/EMUn low

t_w(DPnL)10%

Pulse duration, DPn/EMUn low detected at 10% Voh

Output skew time, time delay difference between DPn/EMUn pins

configured as trace

3

t_sko(DPn)

-500

500 ps

(1) Over recommended operating conditions.

A

t_PLH

t_PHL

1

2

B

C

3

Figure 4-67. Trace Timing

Specifications

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4.8.19.3 IEEE 1149.1 JTAG

The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan

supported allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0])

required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification

(IEEE1149.1), while all of the SerDes (SRIO and SGMII) support the AC-coupled net test defined in AC-

Coupled Net Test Specification (IEEE1149.6).

It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain

fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant

with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit

Specification (EAI/JESD8-5).

4.8.19.3.1 IEEE 1149.1 JTAG Compatibility Statement

For maximum reliability, the C6457 DSP includes an internal pulldown (IPD) on the TRST pin to ensure

that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be

properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive

TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of

an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the

DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan

operations.

4.8.19.3.2 JTAG Electrical Data/Timing

Table 4-101. JTAG Test Port Timing Requirements

(see Figure 4-68)

NO.

1

MIN

10

2

MAX UNIT

t_c(TCK)

Cycle time, TCK

20 ns

ns

3

t_{su(TDIV-TCKH)}

t_h(TCKH-TDIV)

Setup time, TDI/TMS/TRST valid before TCK high

Hold time, TDI/TMS/TRST valid after TCK high

4

5

ns

Table 4-102. JTAG Test Port Switching Characteristics⁽¹⁾

(see Figure 4-68)

NO. PARAMETER

MIN

MAX UNIT

2

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

0.25 x t_c(TCK)ns

(1) Over recommended operating conditions.

1

TCK

TDO

2

4

3

TDI/TMS/TRST

Figure 4-68. JTAG Test-Port Timing

164

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4.8.19.3.3 HS-RTDX Electrical Data/Timing

Table 4-103. Timing Requirements for HS-RTDX

(see Figure 4-69)

NO.

MIN

MAX UNIT

1

2

3

t_c(TCK)

Cycle time, TCK

20

1.5

ns

t_{su(TDIV-TCKH)}

t_h(TCKH-TDIV)

Setup time, EMUn valid before TCK high

Hold time, EMUn valid after TCK high

Table 4-104. Switching Characteristics for HS-RTDX⁽¹⁾

(see Figure 4-69)

NO. PARAMETER

MIN

MAX UNIT

4

t_d(TCKL-TDOV)

Delay time, TCK high to EMUn valid

3

16.5 ns

(1) Over recommended operating conditions.

1

TCK

4

2

3

EMU[n]

Figure 4-69. HS-RTDX Timing

Specifications

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5 Detailed Description

5.1 Device Overview

Table 5-1 provides an overview of the SM320C6457-HIREL DSP. The table shows significant features of

the SM320C6457-HIREL device, including the capacity of on-chip RAM, the peripherals, the CPU

frequency, and the package and pin count.

Table 5-1. Characteristics of the SM320C6457-HIREL Processor

HARDWARE FEATURES

SM320C6457-HIREL

EMIFA (64-bit bus width) (clock source = AECLKIN or SYSCLK7)

1

DDR2 Memory Controller (32-bit bus width) [1.8 V I/O] (clock source =

DDRREFCLKN|P)

EDMA3 (64 independent channels) [CPU/3 clock rate]

High-speed 1×/4× Serial RapidIO Port (4 lanes)

I²C

1

HPI (32-or 16-bit user selectable)

1 (HPI16 or HPI32)

Peripherals

McBSPs (internal or external clock source up to 100 Mbps)

UTOPIA (8-bit mode, 50-MHz, slave-only)

10/100/1000 Ethernet MAC (EMAC)

Management Data Input/Output (MDIO)

2

1

64-Bit Timers (configurable) (internal clock source = CPU/6 clock

frequency)

2 64-bit or 4 32-bit

General-Purpose Input/Output Port (GPIO)

VCP2 (clock source = CPU/3 clock frequency)

TCP2 (clock source = CPU/3 clock frequency)

Size (Bytes)

16

1

Decoder

Coprocessors

2

2176K

32KB L1 Program Memory Controller

[SRAM/Cache] 32KB L1 Data Memory

Controller [SRAM/Cache] 2048KB L2 Unified

Memory/Cache 64KB L3 ROM

On-Chip Memory

Organization

C64x+

Megamodule

Revision ID

Megamodule Revision ID Register (address location: 0181 2000h)

See Section 5.3.6

JTAG BSDL_ID

Frequency

JTAGID register (address location: 0288 0818h)

MHz

See Section 5.5.5

850 and 1000 (1 GHz)

1.18 ns, 1 ns, and 0.83 ns (0.85- and 1-GHz

CPU)

Cycle Time

Voltage

ns

850-MHz

CPU

1.1 V

Core (V)

1-GHz CPU

1.1 V

850-MHz

CPU

1.1 V, 1.8 V, and 3.3 V

I/O (V)

1-GHz CPU

1.1 V, 1.8 V, and 3.3 V

Bypass (×1), (×4 to ×32)

PLL1 and PLL1

Controller

CLKIN1 frequency multiplier

Options

PLL2

DDR2 Clock

23 mm × 23 mm

µm

×10

BGA Package

688-Pin Flip-Chip Plastic BGA (GMH)

0.065 µm

Process

Technology

Product Status

Production Data (PD)

PD

Device Part

Numbers

SM320C6457CGMHS

(For more details on the C64x+™ DSP part numbering, see 图 6-1)

166

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5.2 CPU (DSP Core) Description

The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two

data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-

bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data

address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-

bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in

register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the

next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one

instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units

perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from

memory to the register file and store results from the register file into memory.

The C64x+ CPU extends the performance of the C64x core through enhancements and new features.

Each C64x+ .M unit can perform one of the following each clock cycle: one 32 × 32 bit multiply, two 16 ×

16 bit multiplies, two 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies with add

operations, and four 16 × 16 multiplies with add/subtract capabilities (including a complex multiply). There

is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms

such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes

four 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex

multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-

bit imaginary values. The 32 × 32 bit multiply instructions provide the extended precision necessary for

audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a

pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data

performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2

comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit

which increases the performance of algorithms that do searching and sorting. Finally, to increase data

packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit

and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack

instructions return parallel results to output precision including saturation support.

Other new features include:

•

SPLOOP — A small instruction buffer in the CPU that aids in creation of software pipelining loops

where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size

associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

•

Compact Instructions — The native instruction size for the C6000 devices is 32 bits. Many common

instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+

compiler can restrict the code to use certain registers in the register file. This compression is

performed by the code generation tools.

•

Instruction Set Enhancements — As noted above, there are new instructions such as 32-bit

multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field

multiplication.

Exception Handling — Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to

detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and

from system events (such as a watchdog time expiration).

Privilege — Defines user and supervisor modes of operation, allowing the operating system to give a

basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with

read, write, and execute permissions.

Time-Stamp Counter — Primarily targeted for Real-Time Operating System (RTOS) robustness, a

free-running time-stamp counter is implemented in the CPU, which is not sensitive to system stalls.

Detailed Description

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For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following

documents:

•

TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732)

TMS320C64x+ DSP Cache User's Guide (SPRU862)

TMS320C64x+ Megamodule Reference Guide (SPRU871)

TMS320C64x to TMS320C64x+ CPU Migration Guide (SPRAA84)

Figure 5-1 shows the DSP core functional units and data paths.

168

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Figure 2-1

TMS320C64x+ CPU (DSP Core) Data Paths

Even

register

file A

src1

src2

Odd

register

file A

(A0, A2,

A4...A30)

(A1, A3,

A5...A31)

.L1

odd dst

even dst

long src

(D)

8

32 MSB

32 LSB

ST1b

ST1a

8

long src

even dst

odd dst

src1

(D)

Data path A

.S1

src2

32

(A)

(B)

dst2

dst1

src1

.M1

src2

(C)

32 MSB

32 LSB

LD1b

LD1a

dst

src1

src2

.D1

DA1

2x

1x

Even

register

file B

Odd

register

file B

src2

DA2

.D2

(B0, B2,

B4...B30)

src1

dst

(B1, B3,

B5...B31)

32 LSB

LD2a

LD2b

32 MSB

src2

(C)

.M2

src1

dst2

32

(B)

(A)

dst1

src2

src1

.S2

odd dst

even dst

long src

(D)

Data path B

8

32 MSB

32 LSB

ST2a

ST2b

8

long src

even dst

(D)

odd dst

src2

.L2

src1

Control Register

Figure 5-1. TMS320C64x+ CPU (DSP Core) Data Paths

(A) On .M unit, dst2 is 32 MSB. ____(B) On .M unit, dst1 is 32 LSB. ____(C) On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit,

src2 is 64 bits. (D) On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

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5.3 C64x+ Megamodule

The C64x+ Megamodule consists of several components:

•

The C64x+ CPU and associated C64x+ Megamodule core

Level-one and level-two memories (L1P, L1D, L2)

Interrupt controller

Power-down controller

External memory controller

A dedicated power/sleep controller (LPSC)

The C64x+ Megamodule also provides support for memory protection and bandwidth management (for

resources local to the C64x+ Megamodule). Figure 5-2 shows a block diagram of the C64x+ Megamodule.

32KB L1P

Memory Controller (PMC) With

Memory Protect/Bandwidth Mgmt

C64x+ DSP Core

Instruction Fetch

16-/32-bit Instruction Dispatch

Control Registers

L2 Cache/

SRAM

2048KB

In-Circuit Emulation

Boot

Controller

Instruction Decode

Data Path A

A Register File

Data Path B

B Register File

PLLC

LPSC

GPSC

A31-A16

A15-A0

B31-B16

B15-B0

DMA Switch

Fabric

.M1

.L1 .S1 xx .D1

xx

.M2

.D2 xx .S2 .L2

xx

Data Memory Controller (DMC) With

Memory Protect/Bandwidth Mgmt

CFG Switch

Fabric

32KB L1D

Figure 5-2. 64x+ Megamodule Block Diagram

For more detailed information on the TMS320C64x+ megamodule on the C6457 device, see the

TMS320C64x+ Megamodule Reference Guide (SPRU871).

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5.3.1 Memory Architecture

The C6457 device contains a 2048KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a

32KB level-1 data memory (L1D). All memory on the C6457 has a unique location in the memory map

(see Table 5-14).

After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache

can be reconfigured via software through the L1PMODE field of the L1P Configuration Register

(L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C64x+

Megamodule. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the

TMS320C6457 Bootloader User's Guide (SPRUGL5).

For more information on the operation L1 and L2 caches, see the TMS320C64x+ DSP Cache User's

Guide (SPRU862).

5.3.1.1 L1P Memory

The L1P memory configuration for the C6457 device is as follows:

•

Region 0 size is 0K bytes (disabled)

Region 1 size is 32K bytes with no wait states

Figure 5-3 shows the available SRAM/cache configurations for L1P.

L1P mode bits

Block base

address

000

001

010

011

100

L1P memory

16K bytes

00E0 0000h

1/2

SRAM

3/4

SRAM

7/8

SRAM

direct

mapped

cache

All

SRAM

00E0 4000h

00E0 6000h

8K bytes

direct

mapped

cache

4K bytes

direct

mapped

cache

00E0 7000h

00E0 8000h

dm

cache

Figure 5-3. C6457 L1P Memory Configurations

Detailed Description

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5.3.1.2 L1D Memory

The L1D memory configuration for the C6457 device is as follows:

•

Region 0 size is 0K bytes (disabled)

Region 1 size is 32K bytes with no wait states

Figure 5-4 shows the available SRAM/cache configurations for L1D.

L1D mode bits

Block base

address

000

001

010

011

100

L1D memory

16K bytes

00F0 0000h

1/2

SRAM

3/4

SRAM

7/8

SRAM

All

SRAM

2-way

cache

00F0 4000h

00F0 6000h

8K bytes

2-way

cache

4K bytes

2-way

cache

00F0 7000h

00F0 8000h

2-way

cache

Figure 5-4. C6457 L1D Memory Configurations

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5.3.1.3 L2 Memory

The L2 memory configuration for the C6457 device is as follows:

•

Memory size is 2048KB

Starting address is 0080 0000h

L2 memory can be configured as all SRAM or as part 4-way set-associative cache. The amount of L2

memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration

Register (L2CFG) of the C64x+ Megamodule. Figure 5-5 shows the available SRAM/cache configurations

for L2. By default, L2 is configured as all SRAM after device reset.

L2 mode bits

011

Block base

address

000

001

010

100

101

110

L2 memory

0080 0000h

1/2

SRAM

1024K bytes

3/4

SRAM

7/8

SRAM

0090 0000h

15/16

SRAM

31/32

SRAM

63/64

SRAM

ALL

SRAM

512K bytes

0098 0000h

009C 0000h

4-way

cache

256K bytes

4-way

cache

128K bytes

64K bytes

4-way

cache

009E 0000h

009F 0000h

4-way

cache

32K bytes

4-way

cache

009F 8000h

009F FFFFh

4-way

cache

Figure 5-5. C6457 L2 Memory Configurations

Detailed Description

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5.3.1.4 L3 Memory

The L3 ROM on the device is 64KB. The contents of the ROM are divided into two partitions. The first is

the ROM bootloader with the primary purpose of containing software to boot the device. There is no

requirement to block accesses from this portion to the ROM. The second partition is the secure portion of

ROM, which has a secure kernel that is necessary for support of security features on the device. The

secure portion of ROM cannot be accessed both on secure, and non-secure parts. Only secure

supervisors should have access.

Emulation accesses follows the same rules of the secure portion of the ROM. Emulation can access the

non-secure portion of the ROM, but cannot read the secure portion of the ROM.

5.3.2 Memory Protection

Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,

and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16

pages of L1P (2KB each), 16 pages of L1D (2KB each), and 64 pages of L2 (32KB each). The L1D, L1P,

and L2 memory controllers in the C64x+ Megamodule are equipped with a set of registers that specify the

permissions for each memory page.

Each page may be assigned with fully orthogonal user and supervisor read, write, and execute

permissions. In addition, a page may be marked as either (or both) locally accessible or globally

accessible. A local access is a direct CPU access to L1D, L1P, and L2, while a global access is initiated

by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers

programmed by the CPU count as global accesses. On a secure device, pages can be restricted to secure

access only (default) or opened up for public, non-secure access.

The CPU and each of the system masters on the device are all assigned a privilege ID (see Table 5-2). It

is only possible to specify whether memory pages are locally or globally accessible.

Table 5-2. Available Memory Page Protection Scheme With Privilege ID

PRIVID MODULE

DESCRIPTION

0

1

2

3

4

5

C64x+ Megamodule

Reserved

EMAC

RapidIO and RapidIO CPPI

HPI

The AID0 and LOCAL bits of the memory protection page attribute registers specify the memory page

protection scheme, see Table 5-3.

Table 5-3. Available Memory Page Protection Schemes

AID0 BIT

LOCAL BIT DESCRIPTION

0

1

No access to memory page is permitted.

Only direct access by CPU is permitted.

Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by

the CPU).

1

0

1

All accesses permitted

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Faults are handled by software in an interrupt (or an exception, programmable within the C64x+

megamodule interrupt controller) service routine. A CPU or DMA access to a page without the proper

permissions will:

•

Block the access — reads return zero, writes are ignored

Capture the initiator in a status register — ID, address, and access type are stored

Signal event to CPU interrupt controller

The software is responsible for taking corrective action to respond to the event and resetting the error

status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the

TMS320C64x+ Megamodule Reference Guide (SPRU871).

5.3.3 Bandwidth Management

When multiple requestors contend for a single C64x+ Megamodule resource, the conflict is resolved by

granting access to the highest priority requestor. The following four resources are managed by the

Bandwidth Management control hardware:

•

Level 1 Program (L1P) SRAM/Cache

Level 1 Data (L1D) SRAM/Cache

Level 2 (L2) SRAM/Cache

Memory-mapped registers configuration bus

The priority level for operations initiated within the C64x+ Megamodule are declared through registers in

the C64x+ Megamodule. These operations are:

•

CPU-initiated transfers

User-programmed cache coherency operations

IDMA-initiated transfers

The priority level for operations initiated outside the C64x+ Megamodule by system peripherals is declared

through the Priority Allocation Register (PRI_ALLOC), see Section 5.6.4. System peripherals with no fields

in PRI_ALLOC have their own registers to program their priorities.

More information on the bandwidth management features of the C64x+ Megamodule can be found in the

TMS320C64x+ Megamodule Reference Guide (SPRU871).

5.3.4 Power-Down Control

The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The

power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cache

control hardware, the CPU, and the entire C64x+ Megamodule. These power-down features can be used

to design systems for lower overall system power requirements.

NOTE

The C6457 does not support power-down modes for the L2 memory at this time.

More information on the power-down features of the C64x+ Megamodule can be found in the

TMS320C64x+ Megamodule Reference Guide (SPRU871).

Detailed Description

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5.3.5 Megamodule Resets

Table 5-4 shows the reset types supported on the C6457 device and they affect the resetting of the

Megamodule, either both globally or just locally.

Table 5-4. Megamodule Reset (Global or Local)

RESET TYPE

Power-On Reset

Warm Reset

System Reset

CPU Reset

GLOBAL MEGAMODULE RESET

LOCAL MEGAMODULE RESET

Y

N

Y

For more detailed information on the global and local Megamodule resets, see the TMS320C64x+

Megamodule Reference Guide (SPRU871). And for more detailed information on device resets, see

Section 4.8.3.

5.3.6 Megamodule Revision

The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID

Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Figure 5-6

and described in Table 5-5. The C64x+ Megamodule revision is dependant on the silicon revision being

used.

Figure 5-6. Megamodule Revision ID Register (MM_REVID) (Address - 0181 2000h)⁽¹⁾

31

15

30

14

29

13

28

12

27

11

26

10

25

9

24

23

22

6

21

5

20

4

19

3

18

2

17

1

16

0

VERSION

R-5h

8

7

REVISION

R-n

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) I_OZapplies to output-only pins, indicating off-state (Hi-Z) output leakage current.

Table 5-5. Megamodule Revision ID Register (MM_REVID) Field Descriptions

Bit

Acronym

Value

Description

31:16 VERSION

5h

Version of the C64x+ Megamodule implemented on the device. This field is always read

as 5h.

15:0

REVISION

-

Revision of the C64x+ Megamodule version implemented on the device.

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5.3.7 C64x+ Megamodule Register Descriptions

Table 5-6. Megamodule Interrupt Registers

HEX ADDRESS RANGE

0180 0000

ACRONYM

EVTFLAG0

EVTFLAG1

EVTFLAG2

EVTFLAG3

-

REGISTER NAME

Event Flag Register 0 (Events [31:0])

Event Flag Register 1

Event Flag Register 2

Event Flag Register 3

Reserved

0180 0004

0180 0008

0180 000C

0180 0010 - 0180 001C

0180 0020

EVTSET0

EVTSET1

EVTSET2

EVTSET3

-

Event Set Register 0 (Events [31:0])

Event Set Register 1

Event Set Register 2

Event Set Register 3

Reserved

0180 0024

0180 0028

0180 002C

0180 0030 - 0180 003C

0180 0040

EVTCLR0

EVTCLR1

EVTCLR2

EVTCLR3

-

Event Clear Register 0 (Events [31:0])

Event Clear Register 1

Event Clear Register 2

Event Clear Register 3

Reserved

0180 0044

0180 0048

0180 004C

0180 0050 - 0180 007C

0180 0080

EVTMASK0

EVTMASK1

EVTMASK2

EVTMASK3

-

Event Mask Register 0 (Events [31:0])

Event Mask Register 1

Event Mask Register 2

Event Mask Register 3

Reserved

0180 0084

0180 0088

0180 008C

0180 0090 - 0180 009C

0180 00A0

MEVTFLAG0

MEVTFLAG1

MEVTFLAG2

MEVTFLAG3

-

Masked Event Flag Status Register 0 (Events [31:0])

Masked Event Flag Status Register 1

Masked Event Flag Status Register 2

Masked Event Flag Status Register 3

Reserved

0180 00A4

0180 00A8

0180 00AC

0180 00B0 - 0180 00BC

0180 00C0

EXPMASK0

EXPMASK1

EXPMASK2

EXPMASK3

-

Exception Mask Register 0 (Events [31:0])

Exception Mask Register 1

Exception Mask Register 2

Exception Mask Register 3

Reserved

0180 00C4

0180 00C8

0180 00CC

0180 00D0 - 0180 00DC

0180 00E0

MEXPFLAG0

MEXPFLAG1

MEXPFLAG2

MEXPFLAG3

-

Masked Exception Flag Register 0

Masked Exception Flag Register 1

Masked Exception Flag Register 2

Masked Exception Flag Register 3

Reserved

0180 00E4

0180 00E8

0180 00EC

0180 00F0 - 0180 00FC

0180 0100

-

Reserved

0180 0104

INTMUX1

INTMUX2

INTMUX3

-

Interrupt Multiplexor Register 1

Interrupt Multiplexor Register 2

Interrupt Multiplexor Register 3

Reserved

0180 0108

0180 010C

0180 0110 - 0180 013C

0180 0140

AEGMUX0

AEGMUX1

-

Advanced Event Generator Mux Register 0

Advanced Event Generator Mux Register 1

Reserved

0180 0144

0180 0148 - 0180 017C

0180 0180

INTXSTAT

INTXCLR

Interrupt Exception Status Register

Interrupt Exception Clear Register

0180 0184

Detailed Description

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Table 5-6. Megamodule Interrupt Registers (continued)

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

Dropped Interrupt Mask Register

Reserved

0180 0188

0180 0188 - 0180 01BC

0180 01C0

INTDMASK

-

EVTASRT

-

Event Asserting Register

Reserved

0180 01C4 - 0180 FFFF

Table 5-7. Megamodule Powerdown Control Registers

HEX ADDRESS RANGE

0181 0000

ACRONYM

PDCCMD

-

REGISTER NAME

Power-down controller command register

Reserved

0181 0004 - 0181 1FFF

Table 5-8. Megamodule Revision Register

HEX ADDRESS RANGE

0181 2000

ACRONYM

MM_REVID

-

REGISTER NAME

Megamodule Revision ID Register

Reserved

0181 2004 - 0181 2FFF

Table 5-9. Megamodule IDMA Registers

HEX ADDRESS RANGE

0182 0000

ACRONYM

IDMA0STAT

IDMA0MASK

IMDA0SRC

IDMA0DST

IDMA0CNT

-

REGISTER NAME

IDMA Channel 0 Status Register

IDMA Channel 0 Mask Register

IDMA Channel 0 Source Address Register

IDMA Channel 0 Destination Address Register

IDMA Channel 0 Count Register

Reserved

0182 0004

0182 0008

0182 000C

0182 0010

0182 0014 - 0182 00FC

0182 0100

IDMA1STAT

-

IDMA Channel 1 Status Register

Reserved

0182 0104

0182 0108

IMDA1SRC

IDMA1DST

IDMA1CNT

-

IDMA Channel 1 Source Address Register

IDMA Channel 1 Destination Address Register

IDMA Channel 1 Count Register

Reserved

0182 010C

0182 0110

0182 0114 - 0182 017C

0182 0180

-

Reserved

0182 0184 - 0182 01FF

-

Reserved

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Table 5-10. Megamodule Cache Configuration Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

L2 Cache Configuration Register

Reserved

0184 0000

0184 0004 - 0184 001F

0184 0020

L2CFG

-

L1PCFG

L1P Configuration Register

L1P Cache Control Register

Reserved

0184 0024

L1PCC

0184 0028 - 0184 003F

0184 0040

-

L1DCFG

L1D Configuration Register

L1D Cache Control Register

Reserved

0184 0044

L1DCC

0184 0048 - 0184 0FFF

0184 1000 - 0184 104F

0184 1050 - 0184 3FFF

0184 4000

-

See Table 5-13

-

Reserved

L2WBAR

L2WWC

-

L2 Writeback Base Address Register — for Block Writebacks

L2 Writeback Word Count Register

Reserved

0184 4004

0184 4008 - 0184 400C

0184 4010

L2WIBAR

L2 Writeback and Invalidate Base Address Register — for Block

Writebacks

0184 4014

0184 4018

L2WIWC

L2IBAR

L2IWC

L1PIBAR

L1PIWC

L1DWIBAR

L1DWIWC

-

L2 Writeback and Invalidate word count register

L2 Invalidate Base Address Register

L2 Invalidate Word Count Register

L1P Invalidate Base Address Register

L1P Invalidate Word Count Register

L1D Writeback and Invalidate Base Address Register

L1D Writeback and Invalidate Word Count Register

Reserved

0184 401C

0184 4020

0184 4024

0184 4030

0184 4034

0184 4038

0184 4040

L1DWBAR

L1DWWC

L1DIBAR

L1DIWC

-

L1D Writeback Base Address Register — for Block Writebacks

L1D Writeback Word Count Register

L1D Invalidate Base Address Register

L1D Invalidate Word Count Register

Reserved

0184 4044

0184 4048

0184 404C

0184 4050 - 0184 4FFF

0184 5000

L2WB

L2 Global Writeback Register

L2 Global Writeback and Invalidate Register

L2 Global Invalidate Register

Reserved

0184 5004

L2WBINV

L2INV

0184 5008

0184 500C - 0184 5024

0184 5028

-

L1PINV

-

L1P Global Invalidate Register

Reserved

0184 502C - 0184 503C

0184 5040

L1DWB

L1DWBINV

L1DINV

-

L1D Global Writeback Register

L1D Global Writeback and Invalidate Register

L1D Global Invalidate Register

Reserved

0184 5044

0184 5048

0184 504C - 0184 5FFF

0184 6000 - 0184 640F

0184 6410 - 0184 7FFF

0184 8000 - 0184 81FC

0184 8200 - 0184 823C

0184 8240 - 0184 827C

0184 8280

-

See Table 5-11

-

Reserved

MAR0 to MAR127

Reserved

MAR128 to MAR143 Reserved

MAR144 to MAR159 Reserved

MAR160

MAR161

MAR162

MAR163

Controls EMIFA CE2 Range A000 0000 - A0FF FFFF

0184 8284

Controls EMIFA CE2 Range A100 0000 - A1FF FFFF

Controls EMIFA CE2 Range A200 0000 - A2FF FFFF

Controls EMIFA CE2 Range A300 0000 - A3FF FFFF

0184 8288

0184 828C

Detailed Description

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Table 5-10. Megamodule Cache Configuration Registers (continued)

HEX ADDRESS RANGE

ACRONYM

MAR164

MAR165

MAR166

MAR167

MAR168

MAR169

MAR170

MAR171

MAR172

MAR173

MAR174

MAR175

MAR176

MAR177

MAR178

MAR179

MAR180

MAR181

MAR182

MAR183

MAR184

MAR185

MAR186

MAR187

MAR188

MAR189

MAR190

MAR191

MAR192

MAR193

MAR194

MAR195

MAR196

MAR197

MAR198

MAR199

MAR200

MAR201

MAR202

MAR203

MAR204

MAR205

MAR206

MAR207

MAR208

MAR209

MAR210

REGISTER NAME

0184 8290

0184 8294

0184 8298

0184 829C

0184 82A0

0184 82A4

0184 82A8

0184 82AC

0184 82B0

0184 82B4

0184 82B8

0184 82BC

0184 82C0

0184 82C4

0184 82C8

0184 82CC

0184 82D0

0184 82D4

0184 82D8

0184 82DC

0184 82E0

0184 82E4

0184 82E8

0184 82EC

0184 82F0

0184 82F4

0184 82F8

0184 82FC

0184 8300

0184 8304

0184 8308

0184 830C

0184 8310

0184 8314

0184 8318

0184 831C

0184 8320

0184 8324

0184 8328

0184 832C

0184 8330

0184 8334

0184 8338

0184 833C

0184 8340

0184 8344

0184 8348

Controls EMIFA CE2 Range A400 0000 - A4FF FFFF

Controls EMIFA CE2 Range A500 0000 - A5FF FFFF

Controls EMIFA CE2 Range A600 0000 - A6FF FFFF

Controls EMIFA CE2 Range A700 0000 - A7FF FFFF

Controls EMIFA CE2 Range A800 0000 - A8FF FFFF

Controls EMIFA CE2 Range A900 0000 - A9FF FFFF

Controls EMIFA CE2 Range AA00 0000 - AAFF FFFF

Controls EMIFA CE2 Range AB00 0000 - ABFF FFFF

Controls EMIFA CE2 Range AC00 0000 - ACFF FFFF

Controls EMIFA CE2 Range AD00 0000 - ADFF FFFF

Controls EMIFA CE2 Range AE00 0000 - AEFF FFFF

Controls EMIFA CE2 Range AF00 0000 - AFFF FFFF

Controls EMIFA CE3 Range B000 0000 - B0FF FFFF

Controls EMIFA CE3 Range B100 0000 - B1FF FFFF

Controls EMIFA CE3 Range B200 0000 - B2FF FFFF

Controls EMIFA CE3 Range B300 0000 - B3FF FFFF

Controls EMIFA CE3 Range B400 0000 - B4FF FFFF

Controls EMIFA CE3 Range B500 0000 - B5FF FFFF

Controls EMIFA CE3 Range B600 0000 - B6FF FFFF

Controls EMIFA CE3 Range B700 0000 - B7FF FFFF

Controls EMIFA CE3 Range B800 0000 - B8FF FFFF

Controls EMIFA CE3 Range B900 0000 - B9FF FFFF

Controls EMIFA CE3 Range BA00 0000 - BAFF FFFF

Controls EMIFA CE3 Range BB00 0000 - BBFF FFFF

Controls EMIFA CE3 Range BC00 0000 - BCFF FFFF

Controls EMIFA CE3 Range BD00 0000 - BDFF FFFF

Controls EMIFA CE3 Range BE00 0000 - BEFF FFFF

Controls EMIFA CE3 Range BF00 0000 - BFFF FFFF

Controls EMIFA CE4 Range C000 0000 - C0FF FFFF

Controls EMIFA CE4 Range C100 0000 - C1FF FFFF

Controls EMIFA CE4 Range C200 0000 - C2FF FFFF

Controls EMIFA CE4 Range C300 0000 - C3FF FFFF

Controls EMIFA CE4 Range C400 0000 - C4FF FFFF

Controls EMIFA CE4 Range C500 0000 - C5FF FFFF

Controls EMIFA CE4 Range C600 0000 - C6FF FFFF

Controls EMIFA CE4 Range C700 0000 - C7FF FFFF

Controls EMIFA CE4 Range C800 0000 - C8FF FFFF

Controls EMIFA CE4 Range C900 0000 - C9FF FFFF

Controls EMIFA CE4 Range CA00 0000 - CAFF FFFF

Controls EMIFA CE4 Range CB00 0000 - CBFF FFFF

Controls EMIFA CE4 Range CC00 0000 - CCFF FFFF

Controls EMIFA CE4 Range CD00 0000 - CDFF FFFF

Controls EMIFA CE4 Range CE00 0000 - CEFF FFFF

Controls EMIFA CE4 Range CF00 0000 - CFFF FFFF

Controls EMIFA CE5 Range D000 0000 - D0FF FFFF

Controls EMIFA CE5 Range D100 0000 - D1FF FFFF

Controls EMIFA CE5 Range D200 0000 - D2FF FFFF

180

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Table 5-10. Megamodule Cache Configuration Registers (continued)

HEX ADDRESS RANGE

ACRONYM

MAR211

MAR212

MAR213

MAR214

MAR215

MAR216

MAR217

MAR218

MAR219

MAR220

MAR221

MAR222

MAR223

MAR224

MAR225

MAR226

MAR227

MAR228

MAR229

MAR230

MAR231

MAR232

MAR233

MAR234

MAR235

MAR236

MAR237

MAR238

MAR239

REGISTER NAME

0184 834C

0184 8350

0184 8354

0184 8358

0184 835C

0184 8360

0184 8364

0184 8368

0184 836C

0184 8370

0184 8374

0184 8378

0184 837C

0184 8380

0184 8384

0184 8388

0184 838C

0184 8390

0184 8394

0184 8398

0184 839C

0184 83A0

0184 83A4

0184 83A8

0184 83AC

0184 83B0

0184 83B4

0184 83B8

0184 83BC

0184 83C0 - 0184 83FC

Controls EMIFA CE5 Range D300 0000 - D3FF FFFF

Controls EMIFA CE5 Range D400 0000 - D4FF FFFF

Controls EMIFA CE5 Range D500 0000 - D5FF FFFF

Controls EMIFA CE5 Range D600 0000 - D6FF FFFF

Controls EMIFA CE5 Range D700 0000 - D7FF FFFF

Controls EMIFA CE5 Range D800 0000 - D8FF FFFF

Controls EMIFA CE5 Range D900 0000 - D9FF FFFF

Controls EMIFA CE5 Range DA00 0000 - DAFF FFFF

Controls EMIFA CE5 Range DB00 0000 - DBFF FFFF

Controls EMIFA CE5 Range DC00 0000 - DCFF FFFF

Controls EMIFA CE5 Range DD00 0000 - DDFF FFFF

Controls EMIFA CE5 Range DE00 0000 - DEFF FFFF

Controls EMIFA CE5 Range DF00 0000 - DFFF FFFF

Controls DDR2 CE0 Range E000 0000 - E0FF FFFF

Controls DDR2 CE0 Range E100 0000 - E1FF FFFF

Controls DDR2 CE0 Range E200 0000 - E2FF FFFF

Controls DDR2 CE0 Range E300 0000 - E3FF FFFF

Controls DDR2 CE0 Range E400 0000 - E4FF FFFF

Controls DDR2 CE0 Range E500 0000 - E5FF FFFF

Controls DDR2 CE0 Range E600 0000 - E6FF FFFF

Controls DDR2 CE0 Range E700 0000 - E7FF FFFF

Controls DDR2 CE0 Range E800 0000 - E8FF FFFF

Controls DDR2 CE0 Range E900 0000 - E9FF FFFF

Controls DDR2 CE0 Range EA00 0000 - EAFF FFFF

Controls DDR2 CE0 Range EB00 0000 - EBFF FFFF

Controls DDR2 CE0 Range EC00 0000 - ECFF FFFF

Controls DDR2 CE0 Range ED00 0000 - EDFF FFFF

Controls DDR2 CE0 Range EE00 0000 - EEFF FFFF

Controls DDR2 CE0 Range EF00 0000 - EFFF FFFF

MAR240 to MAR255 Reserved

Table 5-11. Megamodule Error Detection Correct Registers

HEX ADDRESS RANGE

0184 6000

ACRONYM

-

REGISTER NAME

Reserved

0184 6004

L2EDSTAT

L2EDCMD

L2EDADDR

L2EDEN0

L2EDEN1

L2EDCPEC

L2EDNPEC

-

L2 Error Detection Status Register

L2 Error Detection Command Register

L2 Error Detection Address Register

L2 Error Detection Enable Map 0 Register

L2 Error Detection Enable Map 1 Register

L2 Error Detection — Correctable Parity Error Count Register

L2 Error Detection — Non-Correctable Parity Error Count Register

Reserved

0184 6008

0184 600C

0184 6010

0184 6014

0184 6018

0184 601C

0184 6020 - 0184 6400

0184 6404

L1PEDSTAT

L1PEDCMD

L1PEDADDR

L1P Error Detection Status Register

L1P Error Detection Command Register

L1P Error Detection Address Register

0184 6408

0184 640C

Detailed Description

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Table 5-12. Megamodule L1/L2 Memory Protection Registers

HEX ADDRESS RANGE

ACRONYM

L2MPFAR

L2MPFSR

L2MPFCR

-

REGISTER NAME

0184 A000

0184 A004

L2 memory protection fault address register

L2 memory protection fault status register

L2 memory protection fault command register

Reserved

0184 A008

0184 A00C - 0184 A0FF

0184 A100

L2MPLK0

L2MPLK1

L2MPLK2

L2MPLK3

L2MPLKCMD

L2MPLKSTAT

-

L2 memory protection lock key bits [31:0]

L2 memory protection lock key bits [63:32]

L2 memory protection lock key bits [95:64]

L2 memory protection lock key bits [127:96]

L2 memory protection lock key command register

L2 memory protection lock key status register

Reserved

0184 A104

0184 A108

0184 A10C

0184 A110

0184 A114

0184 A118 - 0184 A1FF

0184 A200

L2MPPA0

L2MPPA1

L2MPPA2

L2MPPA3

L2MPPA4

L2MPPA5

L2MPPA6

L2MPPA7

L2MPPA8

L2MPPA9

L2MPPA10

L2MPPA11

L2MPPA12

L2MPPA13

L2MPPA14

L2MPPA15

L2MPPA16

L2MPPA17

L2MPPA18

L2MPPA19

L2MPPA20

L2MPPA21

L2MPPA22

L2MPPA23

L2MPPA24

L2MPPA25

L2MPPA26

L2MPPA27

L2MPPA28

L2MPPA29

L2MPPA30

L2MPPA31

-

L2 memory protection page attribute register 0

L2 memory protection page attribute register 1

L2 memory protection page attribute register 2

L2 memory protection page attribute register 3

L2 memory protection page attribute register 4

L2 memory protection page attribute register 5

L2 memory protection page attribute register 6

L2 memory protection page attribute register 7

L2 memory protection page attribute register 8

L2 memory protection page attribute register 9

L2 memory protection page attribute register 10

L2 memory protection page attribute register 11

L2 memory protection page attribute register 12

L2 memory protection page attribute register 13

L2 memory protection page attribute register 14

L2 memory protection page attribute register 15

L2 memory protection page attribute register 16

L2 memory protection page attribute register 17

L2 memory protection page attribute register 18

L2 memory protection page attribute register 19

L2 memory protection page attribute register 20

L2 memory protection page attribute register 21

L2 memory protection page attribute register 22

L2 memory protection page attribute register 23

L2 memory protection page attribute register 24

L2 memory protection page attribute register 25

L2 memory protection page attribute register 26

L2 memory protection page attribute register 27

L2 memory protection page attribute register 28

L2 memory protection page attribute register 29

L2 memory protection page attribute register 30

L2 memory protection page attribute register 31

Reserved

0184 A204

0184 A208

0184 A20C

0184 A210

0184 A214

0184 A218

0184 A21C

0184 A220

0184 A224

0184 A228

0184 A22C

0184 A230

0184 A234

0184 A238

0184 A23C

0184 A240

0184 A244

0184 A248

0184 A24C

0184 A250

0184 A254

0184 A258

0184 A25C

0184 A260

0184 A264

0184 A268

0184 A26C

0184 A270

0184 A274

0184 A278

0184 A27C

0184 A280 - 0184 A2FC⁽¹⁾

0184 0300 - 0184 A3FF

0184 A400

-

Reserved

L1PMPFAR

L1 program (L1P) memory protection fault address register

(1) Please see the TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide (SPRAAV7) for more information about individual

peripheral I/O.

182

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Table 5-12. Megamodule L1/L2 Memory Protection Registers (continued)

HEX ADDRESS RANGE

ACRONYM

L1PMPFSR

L1PMPFCR

-

REGISTER NAME

0184 A404

0184 A408

L1P memory protection fault status register

L1P memory protection fault command register

Reserved

0184 A40C - 0184 A4FF

0184 A500

L1PMPLK0

L1PMPLK1

L1PMPLK2

L1PMPLK3

L1PMPLKCMD

L1PMPLKSTAT

-

L1P memory protection lock key bits [31:0]

L1P memory protection lock key bits [63:32]

L1P memory protection lock key bits [95:64]

L1P memory protection lock key bits [127:96]

0184 A504

0184 A508

0184 A50C

0184 A510

L1P memory protection lock key command register

L1P memory protection lock key status register

Reserved

0184 A514

0184 A518 - 0184 A5FF

0184 A600 - 0184 A63C⁽²⁾

0184 A640

-

Reserved

L1PMPPA16

L1PMPPA17

L1PMPPA18

L1PMPPA19

L1PMPPA20

L1PMPPA21

L1PMPPA22

L1PMPPA23

L1PMPPA24

L1PMPPA25

L1PMPPA26

L1PMPPA27

L1PMPPA28

L1PMPPA29

L1PMPPA30

L1PMPPA31

-

L1P memory protection page attribute register 16

L1P memory protection page attribute register 17

L1P memory protection page attribute register 18

L1P memory protection page attribute register 19

L1P memory protection page attribute register 20

L1P memory protection page attribute register 21

L1P memory protection page attribute register 22

L1P memory protection page attribute register 23

L1P memory protection page attribute register 24

L1P memory protection page attribute register 25

L1P memory protection page attribute register 26

L1P memory protection page attribute register 27

L1P memory protection page attribute register 28

L1P memory protection page attribute register 29

L1P memory protection page attribute register 30

L1P memory protection page attribute register 31

Reserved

0184 A644

0184 A648

0184 A64C

0184 A650

0184 A654

0184 A658

0184 A65C

0184 A660

0184 A664

0184 A668

0184 A66C

0184 A670

0184 A674

0184 A678

0184 A67C

0184 A680 - 0184 ABFF

0184 AC00

L1DMPFAR

L1DMPFSR

L1DMPFCR

-

L1 data (L1D) memory protection fault address register

L1D memory protection fault status register

L1D memory protection fault command register

Reserved

0184 AC04

0184 AC08

0184 AC0C - 0184 ACFF

0184 AD00

L1DMPLK0

L1DMPLK1

L1DMPLK2

L1DMPLK3

L1DMPLKCMD

L1DMPLKSTAT

-

L1D memory protection lock key bits [31:0]

L1D memory protection lock key bits [63:32]

L1D memory protection lock key bits [95:64]

L1D memory protection lock key bits [127:96]

L1D memory protection lock key command register

L1D memory protection lock key status register

Reserved

0184 AD04

0184 AD08

0184 AD0C

0184 AD10

0184 AD14

0184 AD18 - 0184 ADFF

0184 AE00 - 0184 AE3C⁽³⁾

0184 AE40

-

Reserved

L1DMPPA16

L1DMPPA17

L1DMPPA18

L1DMPPA19

L1D memory protection page attribute register 16

L1D memory protection page attribute register 17

L1D memory protection page attribute register 18

L1D memory protection page attribute register 19

0184 AE44

0184 AE48

0184 AE4C

(2) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0 - L1PMPPA15) of the C64x+

Megamodule. These registers are not supported for the C6457 device.

(3) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0 - L1DMPPA15) of the C64x+

Megamodule. These registers are not supported for the C6457 device.

Detailed Description

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Table 5-12. Megamodule L1/L2 Memory Protection Registers (continued)

HEX ADDRESS RANGE

ACRONYM

L1DMPPA20

L1DMPPA21

L1DMPPA22

L1DMPPA23

L1DMPPA24

L1DMPPA25

L1DMPPA26

L1DMPPA27

L1DMPPA28

L1DMPPA29

L1DMPPA30

L1DMPPA31

-

REGISTER NAME

0184 AE50

0184 AE54

L1D memory protection page attribute register 20

L1D memory protection page attribute register 21

L1D memory protection page attribute register 22

L1D memory protection page attribute register 23

L1D memory protection page attribute register 24

L1D memory protection page attribute register 25

L1D memory protection page attribute register 26

L1D memory protection page attribute register 27

L1D memory protection page attribute register 28

L1D memory protection page attribute register 29

L1D memory protection page attribute register 30

L1D memory protection page attribute register 31

Reserved

0184 AE58

0184 AE5C

0184 AE60

0184 AE64

0184 AE68

0184 AE6C

0184 AE70

0184 AE74

0184 AE78

0184 AE7C

0184 AE80 - 0185 FFFF

Table 5-13. CPU Megamodule Bandwidth Management Registers

HEX ADDRESS RANGE

0182 0200

ACRONYM

EMCCPUARBE

EMCIDMAARBE

EMCSDMAARBE

EMCMDMAARBE

-

REGISTER NAME

EMC CPU Arbitration Control Register

EMC IDMA Arbitration Control Register

EMC Slave DMA Arbitration Control Register

EMC Master DMA Arbitration Control Register

Reserved

0182 0204

0182 0208

0182 020C

0182 0210 - 0182 02FF

0184 1000

L2DCPUARBU

L2DIDMAARBU

L2DSDMAARBU

L2DUCARBU

-

L2D CPU Arbitration Control Register

L2D IDMA Arbitration Control Register

L2D Slave DMA Arbitration Control Register

L2D User Coherence Arbitration Control Register

Reserved

0184 1004

0184 1008

0184 100C

0184 1010 - 0184 103F

0184 1040

L1DCPUARBD

L1DIDMAARBD

L1DSDMAARBD

L1DUCARBD

L1D CPU Arbitration Control Register

L1D IDMA Arbitration Control Register

L1D Slave DMA Arbitration Control Register

L1D User Coherence Arbitration Control Register

0184 1044

0184 1048

0184 104C

184

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5.4 Memory Map Summary

Table 5-14 shows the memory map address ranges of the SM320C6457-HIREL device. The external

memory configuration register address ranges in the SM320C6457-HIREL device begin at the hex

address location 0x7000 0000 for EMIFA and hex address location 0x7800 0000 for DDR2 Memory

Controller.

Table 5-14. SM320C6457-HIREL Memory Map Summary

MEMORY BLOCK DESCRIPTION

BLOCK SIZE (BYTES)

HEX ADDRESS RANGE

0000 0000 - 007F FFFF

0080 0000 - 009F FFFF

00A0 0000 - 00DF FFFF

00E0 0000 - 00E0 7FFF

00E0 8000 - 00EF FFFF

00F0 0000 - 00F0 7FFF

00F0 8000 - 00FF FFFF

0100 0000 - 017F FFFF

0180 0000 - 01BF FFFF

01C0 0000 - 0287 FFFF

0288 0000 - 0288 00FF

0288 0100 - 0288 07FF

0288 0800 - 0288 0BFF

0288 0C00 - 028B FFFF

028C 0000 - 028C 00FF

028C 0100 - 028F FFFF

0290 0000 - 0290 00FF

0290 0100 - 0293 FFFF

0294 0000 - 0294 007F

0294 0080 - 0297 FFFF

0298 0000 - 0298 007F

0298 0080 - 0299 FFFF

029A 0000 - 029A 01FF

029A 0200 - 029F FFFF

02A0 0000 - 02A0 7FFF

02A0 8000 - 02A1 FFFF

02A2 0000 - 02A2 03FF

02A2 0400 - 02A2 7FFF

02A2 8000 - 02A2 83FF

02A2 8400 - 02A2 FFFF

02A3 0000 - 02A3 03FF

02A3 0400 - 02A3 7FFF

02A3 8000 - 02A3 83FF

02A3 8400 - 02A3 FFFF

02A4 0000 - 02A4 03FF

02A4 0400 - 02A4 7FFF

02A4 8000 - 02A4 83FF

02A4 8400 - 02AB FFFF

02AC 0000 - 02AC 0FFF

02AC 1000 - 02AC FFFF

02AD 0000 - 02AD 1FFF

Reserved

8M

2M

L2 SRAM

Reserved

4M

L1P SRAM

32K

Reserved

1M - 32K

32K

L1D SRAM

Reserved

1M -32K

8M

Reserved

C64x+ Megamodule Registers

Reserved

4M

12.5M

256

HPI Control Registers

Reserved

2K - 256

1K

Chip-Level Registers

Reserved

253K

256

McBSP 0 Registers

Reserved

256K - 256

256

McBSP 1 Registers

Reserved

256K - 256

128

Timer 0 Registers

Reserved

256K - 128

128

Timer 1 Registers

Reserved

128K - 128

512

PLL Controller (including Reset Controller) Registers

Reserved

384K - 512

32K

EDMA3 Channel Controller Registers

Reserved

96K

EDMA3 Transfer Controller 0 Registers

Reserved

1K

31K

EDMA3 Transfer Controller 1 Registers

Reserved

1K

31K

EDMA3 Transfer Controller 2 Registers

Reserved

1K

31K

EDMA3 Transfer Controller 3 Registers

Reserved

1K

31K

EDMA3 Transfer Controller 4 Registers

Reserved

1K

31K

EDMA3 Transfer Controller 5 Registers

Reserved

1K

479K

4K

Power / Sleep Controller (PSC)

Reserved

60K

Embedded Trace Buffer (ETB)

8K

Detailed Description

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Table 5-14. SM320C6457-HIREL Memory Map Summary (continued)

MEMORY BLOCK DESCRIPTION

Reserved

BLOCK SIZE (BYTES)

184K

HEX ADDRESS RANGE

02AD 2000 - 02AF FFFF

02B0 0000 - 02B0 00FF

02B0 0100 - 02B0 3FFF

02B0 4000 - 02B0 407F

02B0 4080 - 02B3 FFFF

02B4 0000 - 02B4 01FF

02B4 0200 - 02B7 FFFF

02B8 0000 - 02B8 00FF

02B8 0100 - 02B9 FFFF

02BA 0000 - 02BA 00FF

02BA 0100 - 02BA 01FF

02BA 0200 - 02C3 FFFF

02C4 0000 - 02C4 00FF

02C4 0100 - 02C7 FFFF

02C8 0000 - 02C8 07FF

02C8 0800 - 02C8 0FFF

02C8 1000 - 02C8 10FF

02C8 1100 - 02C8 17FF

02C8 1800 - 02C8 18FF

02C8 1900 - 02C8 1FFF

02C8 2000 - 02C8 3FFF

02C8 4000 - 02CF FFFF

02D0 0000 - 02D2 0FFF

02D2 1000 - 02DF FFFF

02E0 0000 - 02E0 3FFF

02E0 4000 - 02EF FFFF

02F0 0000 - 02FF FFFF

0300 0000 - 0FFF FFFF

1000 0000 - 2FFF FFFF

3000 0000 - 3000 00FF

3000 0100 - 33FF FFFF

3400 0000 - 3400 00FF

3400 0100 - 3BFF FFFF

3C00 0000 - 3C00 FFFF

3C01 0000 - 3CFF FFFF

3D00 0000 - 3D00 007F

3D00 0080 - 3D00 03FF

3D00 0400 - 3D00 047F

3D00 0480 - 4FFF FFFF

5000 0000 - 500F FFFF

5010 0000 - 501F FFFF

5020 0000 - 57FF FFFF

5800 0000 - 5800 FFFF

5801 0000 - 6FFF FFFF

7000 0000 - 7000 00FF

7000 0100 - 77FF FFFF

7800 0000 - 7800 00FF

GPIO Registers

Reserved

256

16K - 256

128

I2C Data and Control Registers

Reserved

240K - 128

512

UTOPIA Control Registers

Reserved

256K - 512

256

VCP2 Control Registers

Reserved

128K - 256

256

TCP2_A Control Registers

TCP2_B Control Registers

Reserved

256

640K - 512

256

SGMII Control

Reserved

256K - 256

2K

EMAC Control

Reserved

2K

EMAC Interrupt Controller

Reserved

256

2K - 256

256

MDIO Control Registers

Reserved

2K - 256

8K

EMAC Descriptor Memory

Reserved

496K

RapidIO Control Registers

Reserved

132K

892K

RapidIO Descriptor Memory

Reserved

16K

1M - 16K

1M

Reserved

208M

Reserved

512M

McBSP 0 Data

256

Reserved

64M - 256

256

McBSP 1 Data

Reserved

128M - 256

64K

L3 ROM

Reserved

16M - 64K

128

UTOPIA Receive (RX) Data

Reserved

896

UTOPIA Transmit (TX) Data

Reserved

128

304M - 1152

1M

TCP2_A Data

TCP2_B Data

1M

Reserved

126M

VCP2 Data

64K

Reserved

384M - 64K

256

EMIFA (EMIF64) Configuration Registers

Reserved

128M - 256

256

DDR2 EMIF Configuration Registers

186

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Table 5-14. SM320C6457-HIREL Memory Map Summary (continued)

MEMORY BLOCK DESCRIPTION

Reserved

BLOCK SIZE (BYTES)

HEX ADDRESS RANGE

128M - 256

512M

7800 0100 - 7FFF FFFF

8000 0000 - 9FFF FFFF

A000 0000 - A07F FFFF

A080 0000 - AFFF FFFF

B000 0000 - B07F FFFF

B080 0000 - BFFF FFFF

C000 0000 - C07F FFFF

C080 0000 - CFFF FFFF

D000 0000 - D07F FFFF

D080 0000 - DFFF FFFF

E000 0000 - FFFF FFFF

Reserved

EMIFA CE2 Data -SBSRAM/Async

Reserved

8M

256M - 8M

8M

EMIFA CE3 Data -SBSRAM/Async

Reserved

256M - 8M

8M

EMIFA CE4 Data -SBSRAM/Async

Reserved

256M - 8M

8M

EMIFA CE5 Data -SBSRAM/Async

Reserved

256M - 8M

512M

DDR2 EMIF CE0 Data

5.5 Device Configuration

On the C6457 device, certain device configurations like boot mode and endianess, are selected at device

power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on

reset. By default, the peripherals on the C6457 device are disabled and need to be enabled by software

before being used.

5.5.1 Device Configuration at Device Reset

Table 5-15 describes the C6457 device configuration pins. The logic level is latched at power-on reset to

determine the device configuration. The logic level on the device configuration pins can be set by using

external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive

these pins. When using a control device, care should be taken to ensure there is no contention on the

lines when the device is out of reset. The device configuration pins are sampled during power-on reset

and are driven after the reset is removed. To avoid contention, the control device must stop driving the

device configuration pins of the DSP.

NOTE

If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the

internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use

of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown

resistors and situations in which external pullup/pulldown resistors are required, see

Section 5.5.6.

Detailed Description

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Table 5-15. C6457 Device Configuration Pins

CONFIGURATION

NO.

IPD/IPU⁽¹⁾

FUNCTIONAL DESCRIPTION

Device Endian mode (LENDIAN)

GPIO[0]

A5

IPU

•

0 = Device operates in Big Endian mode.

1 = Device operates in Little Endian mode (default).

GPIO[4:1]

Boot Mode Selection (BOOTMODE [3:0])

[B5, B4, D5,

E5]

IPD

•

These pins select the boot mode for the device. For more information on the boot

modes, see Section 5.7.2.

GPIO[8:5]

[B25, F5, C5,

F6]

Device Number (DEVNUM[3:0])

GPIO[13:9]

Configuration General-Purpose Inputs (CFGGP[4:0])

[C23, D24,

C25, A25,

C24]

•

The value of these pins is latched to the Device Status Register following power-

on reset and is used by the software.

GPIO[14]

GPIO[15]

HPI peripheral bus width select (HPIWIDTH)

•

0 = HPI operates in HPI16 mode (default).

HPI bus is 16-bits wide; HD[15:0] pins are used and the remaining HD[31:16] pins

are reserved pins in the Hi-Z state.

D23

F23

IPD

•

1 = HPI operates in HPI32 mode.

HPI bus is 32 bits wide; HD[31:0] pins are used.

EMIFA input clock source select (ECLKINSEL).

•

0 = ECLKIN (default mode)

1 = SYSCLK7 (CPU/x) Clock Rate.

The SYSCLK7 clock rate is software selectable via the Software PLL1 Controller.

By default, SYSCLK7 is selected as CPU ÷ 10 clock rate.

CORECLKSEL

DDRCLKSEL

Core Clock Select

AE6

G6

•

0 = CORECLK(N|P) is the input to main PLL.

1 = ALTCORECLK is used as the input to main PLL.

DDR Clock Select

•

0 = DDRREFCLK(N|P) is the input to DDR PLL.

1 = ALTDDRCLK is used as the input to DDR PLL.

(1) All voltage values are with respect to V_SS

.

5.5.2 Peripheral Selection After Device Reset

Several of the peripherals on the C6457 are controlled by the Power Sleep Controller (PSC). By default,

the SRIO, TCP2_A, TCP2_B, and VCP are held in reset and clock-gated. The memories in these modules

are also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the software

enables the modules (turns on clocks and de-asserts reset) before these modules can be used.

In addition, the EMIFA, HPI, and UTOPIA come up clock-gated and held in reset. Memories in these

modules are already enabled. Software is required to enable these modules before they are used as well.

If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically

enable the module.

All other modules come up enabled by default and there is no special software sequence to enable. For

more detailed information on the PSC usage, see the TMS320C6457 DSP Power/Sleep Controller PSC

User's Guide (SPRUGL4).

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5.5.3 Device State Control Registers

The C6457 device has a set of registers that are used to control the status of its peripherals. These

registers are shown in Table 5-16 and described in the next sections.

Table 5-16. Device State Control Registers⁽¹⁾

HEX ADDRESS RANGE

ACRONYM

DESCRIPTION

Parameters for DSP device ID. Also referred to as JTAG or BSDL ID. These are readable by

the configuration bus and can be accessed via the JTAG and the CPU.

0288 0818

JTAGID

0288 081C

0288 0820

-

Reserved

DEVSTAT

-

Stores parameters latched from configuration pins

Reserved

0288 0824 - 0288 0837

Two successive key writes are required to get write access to any of the device state control

registers. KICK0 is the first key register. The written data must be 0x83E70B13 to unlock it

and it must be written before the KICK1 register. Writing any other value will lock the device

state control registers.

0288 0838

KICK0

KICK1

KICK1 is the second key register to be unlocked in order to get write access to any of the

device state control registers. The written data must be 0x95A4F1E0 to unlock it and it must

be written after the KICK0 register. Writing any other value will lock the device state control

registers.

0288 083C

0288 0840

DSP_BOOT

_ADDR

DSP boot address

0288 0844 - 0288 090F

0288 0910

-

Reserved

DEVCFG

MACID1

MACID2

-

Parameters set through software for device configuration

EFUSE derived MAC address for C6457

Reserved

0288 0914

0288 0918

0288 0922 - 0288 091B

0288 091C

PRI_ALLOC

WDRSTSEL

Sets priority for Master peripherals

Reset select for Watchdog (Timer1)

0288 0920

(1) Writes are conditional based on valid keys written to both the KICK0 and KICK1 registers.

5.5.4 Device Status Register Description

The device status register depicts the device configuration selected upon power-on reset. Once set, these

bits will remain set until a power-on reset. For the actual register bit names and their associated bit field

descriptions, see Figure 5-7 and Table 5-18.

Table 5-17 shows the parameters that are set through software to configure different components on the

device. The configuration is done through the device configuration DEVCFG register, which is one-time

writeable through software. The register is reset on all hard resets and is locked after the first write.

Table 5-17. Device Configuration Register Fields

FIELD

RESET

DESCRIPTION

SETTINGS

Device Configuration 1 Register Fields

CLKS0

0b

McBSP0 CLKS Select

•

0 = CLKS0 device pin

•

1 = chip_clks from Main.PLL

CLKS1

0b

McBSP1 CLKS Select

•

0 = CLKS1 device pin

•

1 = chip_clks from Main.PLL

SYSCLKOUTEN

1b

SYSCLKOUT Enable

•

0 = No clock output

•

1 = Clock output enabled

Detailed Description

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Figure 5-7. Device Configuration Status Register (DEVSTAT) (HEX ADDRESS - 0288 0820h)⁽¹⁾

31

15

30

29

28

27

26

25

24

Reserved

R-0

23

22

21

20

19

18

17

16

14

13

12

11

CFGGP

R-n

10

9

8

7

6

5

4

3

2

1

0

ECLKI HPIWI

NSEL

LENDI

AN

DEVNUM

R

BOOTMODE

R

DTH

0

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

Table 5-18. Device Configuration Status Register Field Descriptions

Bit

Acronym

Description

31:16 Reserved

Reserved. Read only, writes have no effect.

15

ECLKINSEL

HPIWIDTH

CFGGP[4:0]

EMIFA input clock select — shows the status of what clock mode is enabled or disabled for EMIFA.

•

0 = ECLKIN (default mode)

1 = SYSCLK7 (CPU ÷ x) Clock Rate. The SYSCLK7 clock rate is software selectable via the PLL1

Controller. By default, SYSCLK7 is selected as CPU ÷ 10 clock rate.

14

HPI bus width control bit — shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit

mode.

•

0 = HPI operates in 16-bit mode. (default)

1 = HPI operates in 32-bit mode

13:9

Used as general-purpose inputs for configuration purposes. These pins are latched at power-on reset. These

values can be used by software routines for boot operations.

8:5

4:1

DEVNUM[3:0]

Device number.

BOOTMODE[3:0]

Determines the boot method for the device. For more information on bootmode, see Section 5.7.2.

•

0000 = No Boot

0001 = I²C Master Boot (Slave Address 0x50)

0010 = I²C Master Boot (Slave Address 0x51)

0011 = I²C Slave Boot

0100 = HPI Boot

0101 = EMIFA Boot

0110 = EMAC Master Boot

0111 = EMAC Slave Boot

1000 = EMAC Forced Mode Boot

1001 = Reserved

1010 = RapidIO Boot (Configuration 0)

1011 = RapidIO Boot (Configuration 1)

1100 = RapidIO Boot (Configuration 2)

1101 = RapidIO Boot (Configuration 3)

111x = Reserved

0

LENDIAN

Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode

or Little Endian mode (default).

0 = System is operating in Big Endian mode

1 = System is operating in Little Endian mode (default)

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5.5.5 JTAG ID (JTAGID) Register Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the

C6457 device, the JTAG ID register resides at address location 0x0288 0818. For the actual register bit

names and their associated bit field descriptions, see Figure 5-8 and Table 5-19.

Figure 5-8. JTAG ID (JTAGID) Register (HEX ADDRESS - 0288 0818h)⁽¹⁾

31

15

30

VARIANT

R-0000

14 13

29

28

12

27

11

26

10

25

9

24

8

23

22

21

20

4

19

3

18

2

17

1

16

PART NUMBER (16-bit)

7

6

5

0

PART NUMBER (Continued)

R-0000 0000 1001 0110b

MANUFACTURER

0000 0010 111b

LSB

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.

Table 5-19. JTAG ID (JTAGID) Register Field Descriptions

Bit

Acronym

Value

Description

31:28 VARIANT

0000

Variant (4-Bit) value. The value of this field depends on the silicon revision

being used.

27:12 PART NUMBER

0000 0000 1001 0110b

0000 0010 111b

1b

Part Number for boundary scan

Manufacturer

11:1

0

MANUFACTURER

LSB

This bit is read as a 1 for C6457

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5.5.6 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the C6457 device always be at a valid logic level and

not floating. This may be achieved via pullup/pulldown resistors. The C6457 device features internal pullup

(IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for

external pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

•

Device Configuration Pins: If the pin is both routed out and are not driven (in Hi-Z state), an external

pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.

•

Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external

pullup/pulldown resistor to pull the signal to the opposite rail.

For the device configuration pins (listed in Table 5-15), if they are both routed out and are not driven (in

Hi-Z state), it is strongly recommended that an external pullup/pulldown resistor be implemented.

Although, internal pullup/pulldown resistors exist on these pins and they may match the desired

configuration value, providing external connectivity can help ensure that valid logic levels are latched on

these device configuration pins. In addition, applying external pullup/pulldown resistors on the device

configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

•

Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure

to include the leakage currents of all the devices connected to the net, as well as any internal pullup or

pulldown resistors.

•

Decide a target value for the net. For a pulldown resistor, this should be below the lowest V_ILlevel of

all inputs connected to the net. For a pullup resistor, this should be above the highest V_IHlevel of all

inputs on the net. A reasonable choice would be to target the V_OLor V_OHlevels for the logic family of

the limiting device; which, by definition, have margin to the V_ILand V_IHlevels.

•

Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will

reach the target pulled value when maximum current from all devices on the net is flowing through the

resistor. The current to be considered includes leakage current plus, any other internal and external

pullup/pulldown resistors on the net.

For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value

of the external resistor. Verify that the resistance is small enough that the weakest output buffer can

drive the net to the opposite logic level (including margin).

•

Remember to include tolerances when selecting the resistor value.

For pullup resistors, also remember to include tolerances on the DV_DDrail.

For most systems:

•

A 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should

confirm this resistor value is correct for their specific application.

•

A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while

meeting the above criteria. Users should confirm this resistor value is correct for their specific

application.

For more detailed information on input current (I_I), and the low-level/high-level input voltages (V_ILand V_IH)

for the C6457 device, see Section 4.4.

To determine which pins on the C6457 device include internal pullup/pulldown resistors, see Table 3-2.

5.6 System Interconnect

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On the C6457 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system

peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency,

concurrent data transfers between master peripherals and slave peripherals; for example, through a

switch fabric the CPU can send data to the Viterbi co-processor (VCP2) without affecting a data transfer

between the HPI and the DDR2 memory controller. The switch fabrics also allow for seamless arbitration

between the system masters when accessing system slaves.

5.6.1 Internal Buses, Bridges, and Switch Fabrics

Two types of buses exist in the C6457 device: data buses and configuration buses. Some C6457

peripherals have both a data bus and a configuration bus interface, while others only have one type of

interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral.

Configuration buses are mainly used to access the register space of a peripheral and the data buses are

used mainly for data transfers. However, in some cases, the configuration bus is also used to transfer

data. For example, data is transferred to the VCP2 and TCP2 via their configuration bus. Similarly, the

data bus can also be used to access the register space of a peripheral. For example, the EMIFA and

DDR2 memory controller registers are accessed through their data bus interface.

The C64x+ Megamodule, the EDMA3 traffic controllers, and the various system peripherals can be

classified into two categories: masters and slaves.

Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for

their data transfers. Slaves on the other hand rely on the EDMA3 to perform transfers to and from them.

Examples of masters include the EDMA3 traffic controllers, SRIO, EMAC, and HPI. Examples of slaves

include the McBSP, UTOPIA, and I²C.

The C6457 device contains two switch fabrics through which masters and slaves communicate. The data

switch fabric, known as the data switched central resource (SCR), is a high-throughput interconnect

mainly used to move data across the system (for more information, see Section 5.6.2). The data SCR

connects masters to slaves via 128-bit data buses running at a SYSCLK4 frequency (SYSCLK4 is

generated from PLL controller). Peripherals that have a 128-bit data bus interface running at this speed

can connect directly to the data SCR; other peripherals require a bridge.

The configuration switch fabric, also known as the configuration switch central resource (SCR), is mainly

used by the C64x+ Megamodule to access peripheral registers (for more information, see Section 5.6.3).

The configuration SCR connects C64x+ Megamodule to slaves via 32-bit configuration buses running at a

SYSCLK4 frequency (SYSCLK4 is generated from PLL controller). As with the data SCR, some

peripherals require the use of a bridge to interface to the configuration SCR. Note that the data SCR also

connects to the configuration SCR.

Bridges perform a variety of functions:

•

Conversion between configuration bus and data bus.

Width conversion between peripheral bus width and SCR bus width.

Frequency conversion between peripheral bus frequency and SCR bus frequency.

For example, the EMIFA requires a bridge to convert its 64-bit data bus interface into a 128-bit interface

so that it can connect to the data SCR. In the case of the TCP2 and VCP2, a bridge is required to connect

the data SCR to the 64-bit configuration bus interface.

Note that some peripherals can be accessed through the data SCR and also through the configuration

SCR.

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5.6.2 Data Switch Fabric Connections

Figure 5-9 shows the connection between slaves and masters through the data switched central resource

(SCR). Masters are shown on the left and slaves on the right. The data SCR connects masters to slaves

via 128-bit data buses running at a SYSCLK4 frequency. SYSCLK4 is supplied by the PLL controller and

is fixed at a frequency equal to the CPU frequency divided by 3.

Configuration Bus

Data Bus

EDMA3 Channel

Controller

Events

SLAVE

Data SCR

32

MASTER

S

TCP2_A

VCP2

128

32

Bridge

M

128

M0

M1

M2

M3

M4

M5

S0

32

128

S1

S2

S3

S4

S5

128

M

Bridge

TCP2_B

EDMA3

Transfer

128

Controllers

CFG

SCR

32

S

McBSP0

McBSP1

128-bit

128

32

M

Bridge

32

128

EMAC

HPI

M

Bridge

S

32

L3 ROM

UTOPIA

S

Bridge

128

M

Bridge

DDR2

Memory

Controller

32

128

Serial RapidIO

(Descriptor)

M

S

Bridge

Serial

RapidIO

(Data)

128

64

128

Bridge

EMIFA

Megamodule

Figure 5-9. Data Switched Central Resource Block Diagram

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Masters are shown on the left and slaves on the right. The data SCR connects masters to slaves via 128-

bit data buses running at a SYSCLK4 frequency. SYSCLK4 is supplied by the PLL controller and is fixed

at a frequency equal to the CPU frequency divided by 3.

Some peripherals and the C64x+ Megamodule have both slave and master ports. Note that each EDMA3

transfer controller has an independent connection to the data SCR.

The Serial RapidIO (SRIO) peripheral has two connections to the data SCR. The first connection is used

when descriptors are being fetched from system memory. The other connection is used for all other data

transfers.

Note that masters can access the configuration SCR through the data SCR. The configuration SCR is

described in Section 5.6.3.

Not all masters on the C6457 DSP may connect to all slaves. Allowed connections are summarized in

Table 5-20.

Table 5-20. SCR Connection Matrix

CONFIGURATION

SCR

DDR2 MEMORY

CONTROLLER

VCP2

Y

TCP2_A

TCP2_B

McBSPs

L3 ROM

UTOPIA

EMIFA

MEGAMODULE

TC0

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

TC1

N

TC2

N

TC3

N

TC4

N

TC5

N

EMAC

HPI

N

SRIO⁽¹⁾

N

MEGAMODULE

Y

(1) Applies to both descriptor and data accesses by the SRIO peripheral.

5.6.3 Configuration Switch Fabric

Figure 5-10 shows the connection between the C64x+ Megamodule and the configuration switched central

resource (SCR). The configuration SCR is mainly used by the C64x+ Megamodule to access peripheral

registers. The data SCR also has a connection to the configuration SCR which allows masters to access

most peripheral registers. The only registers not accessible by the data SCR through the configuration

SCR are the device configuration registers and the PLL controller registers; these can only be accessed

by the C64x+ Megamodule.

The configuration SCR uses 32-bit configuration buses running at SYSCLK4 frequency. SYSCLK4 is

supplied by the PLL controller and is fixed at a frequency equal to the CPU frequency divided by 3.

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Configuration Bus

Data Bus

32

CFG SCR

TCP2_A

S

32

MUX

M

TCP2_B

VCP2

S

32

M

32

S

ETB

32

Bridge

McBSPs (x2)

S

GPIO

32

S

UTOPIA

32

GPSC

32

S

I2C

HPI

S

Timers (x2)

32

32-bit

32

M

Bridge

MUX

EMAC

MDIO

32

S

Megamodule

S

M

CP-GMAC

32

Ethernet

CPPI

S

32

Data SCR

S

CP-SGMII

SERDES

32

PLL

S

Controller^(A)

Device

Configuration

32

S

Registers^(A)

S

Serial RapidIO

(Data)

32

M

MUX

32

Serial RapidIO

(Descriptor)

EDMA3 CC

32

S

EDMA3 TC0

EDMA3 TC2

32

S

EDMA3 TC1

32

M

Bridge

MUX

EDMA3 TC3

32

EDMA3 TC4

Note A: Only accessible by

the C64x+ Megamodule

32

S

EDMA3 TC5

Figure 5-10. Configuration Switched Central Resource (SCR) Block Diagram

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5.6.4 Bus Priorities

On the C6457 device, bus priority is programmable for each master. The register bit fields and default

priority levels for C6457 bus masters are shown in Table 5-21.

Table 5-21. C6457 Default Bus Master Priorities

BUS MASTER

EDMA3TC0

DEFAULT PRIORITY LEVEL

PRIORITY CONTROL

0

1

0

1

2

7

QUEPRI.PRIQ0 (EDMA3 register)

QUEPRI.PRIQ1 (EDMA3 register)

QUEPRI.PRIQ2 (EDMA3 register)

QUEPRI.PRIQ3 (EDMA3 register)

QUEPRI.PRIQ4 (EDMA3 register)

QUEPRI.PRIQ5 (EDMA3 register)

PRI_ALLOC.EMAC

EDMA3TC1

EDMA3TC2

EDMA3TC3

EDMA3TC4

EDMA3TC5

EMAC

SRIO (Data Access)

SRIO (Descriptor Access)

HPI

PER_SET_CNTL.CBA_TRANS_PRI (SRIO register)

PRI_ALLOC.SRIO_CPPI

PRI_ALLOC.HOST

C64x+ Megamodule (MDMA port)

MDMAARBE.PRI (C64x+ Megamodule Register)

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The priority levels should be tuned to obtain the best system performance for a particular application.

Lower values indicate higher priorities. For some masters, the priority values are programmed at the

system level by configuring the PRI_ALLOC register. Details on the PRI_ALLOC register are shown in

Figure 5-11 and Table 5-22. The C64x+ megamodule, SRIO, and EDMA masters contain registers that

control their own priority values.

Figure 5-11. Priority Allocation Register (PRI_ALLOC) (0x0288 091C)⁽¹⁾

31

15

30

14

29

13

28

27

11

26

10

25

24

Reserved

R-0000 0000 0000 0000

23

22

21

5

20

19

3

18

2

17

16

0

12

9

8

7

6

4

1

Reserved

R-0000 000

HPI

SRIO_CPPI

R/W-001

EMAC

R/W-001

R/W-010

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) I_Iapplies to input-only pins and bi-directional pins. For input-only pins, I_Iindicates the input leakage current. For bi-directional pins, I_I

includes input leakage current and off-state (Hi-Z) output leakage current.

Table 5-22. Priority Allocation Register (PRI_ALLOC) Field Descriptions

Bit

Acronym

Value

Description

31:16 Reserved

0000 0000 0000 0000 Reserved.

15:9

8:6

Reserved

HOST

0000 000

010

Reserved.

Priority of the HPI peripheral.

5:3

SRIO_CPPI

001

Priority of the Serial RapidIO when accessing descriptors from system memory. This

priority is set in the peripheral, itself.

2:0

EMAC

001

Priority of the EMAC peripheral.

The priority is enforced when several masters in the system are vying for the same endpoint. Note that the

configuration SCR port on the data SCR is considered a single endpoint meaning priority will be enforced

when multiple masters try to access the configuration SCR. Priority is also enforced on the configuration

SCR side when a master (through the data SCR) tries to access the same endpoint as the C64x+

megamodule.

In the PRI_ALLOC register, the HOST field applies to the priority of the HPI peripheral. The EMAC fields

specify the priority of the EMAC peripheral. The SRIO_CPPI field is used to specify the priority of the

Serial RapidIO when accessing descriptors from system memory. The priority for Serial RapidIO data

accesses is set in the peripheral itself.

5.7 Boot Modes

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes

are software driven, using the BOOTMODE[3:0] device configuration inputs to determine the software

configuration that must be completed. From a hardware perspective, there are two possible boot modes:

•

Public ROM Boot - C64x+ Megamodule is released from reset and begins executing from the L3

ROM base address. After performing the boot process (e.g., from I²C ROM, Ethernet, or RapidIO), the

C64x+ Megamodule then begins execution from the L2 RAM base address.

Secure ROM Boot - On secure devices, the C64x+ Megamodule is released from reset and begin

executing from secure ROM. Software in the secure ROM will free up internal RAM pages, after which

the C64x+ Megamodule initiates the boot process. The C64x+ Megamodule performs any

authentication and decryption required on the bootloaded image prior to beginning execution.

The boot process performed by the C64x+ Megamodule in public ROM boot and secure ROM boot are

determined by the BOOTMODE[3:0] value in the DEVSTAT register. The C64x+ Megamodule reads this

value, and then executes the associated boot process in software. Table 5-23 shows the supported boot

modes.

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Table 5-23. SM320C6457-HIREL Supported Boot Modes

MODE NAME

No Boot

I²C Master Boot A

BOOTMODE[3:0] DESCRIPTION

0000b

0001b

No Boot

Slave I²C address is 0x50. The C64x+ Megamodule configures I²C, acts as a master to the

I²C bus and copies data from an I²C EEPROM or a device acting as an I²C slave to the DSP

using a predefined boot table format. The destination address and length are contained within

the boot table.

I²C Master Boot B

I²C Slave Boot

0010b

0011b

Similar to I²C boot A except the slave I²C address is 0x51.

The C64x+ Megamodule configures I²C and acts as a slave and will accept data and code

section packets through the I2C interface. It is required that an I²C master is present in the

system.

HPI Boot

0100b

0101b

0110b

0111b

1000b

Host boot.

EMIFA Boot

External memory boot from ACE3 space (0xB0000000 address).

EMAC Master Boot

EMAC Slave Boot

TI Ethernet Boot. The C64x+ Megamodule configures EMAC and EDMA, if required, and

brings the code image into the internal on-chip memory via the protocol defined by the boot

method (EMAC bootloader).

EMAC Forced-Mode

Boot

Reserved

1001b

1010b

Reserved

RapidIO Boot

(Config 0)

RapidIO Boot

(Config 1)

1011b

1100b

1101b

The C64x+ Megamodule configures the SRIO and an external host loads the application via

SRIO peripheral, using directIO protocol. A doorbell interrupt is used to indicate that the code

has been loaded. For more details on the RapidIO configurations, see Table 5-24.

RapidIO Boot

(Config 2)

RapidIO Boot

(Config 3)

The C64x+ Megamodule configures Serial RapidIO, EMAC, and EDMA, if required, and brings the code

image into the internal on-chip memory via the protocol defined by the boot method (SRIO EMAC

bootloader).

Table 5-24. Serial RapidIO (SRIO) Supported Boot Modes

SRIO BOOT MODE

SERDES CLOCK

125 MHz

LINK RATE

1.25 Gbps

3.125 Gbps

1.25 Gbps

3.125 Gbps

SRIO BOOT CONFIGURATION

Four 1× SRIO links

One 4× SRIO link

Bootmode 10 - Config 0

Bootmode 11 - Config 1

Bootmode 12 - Config 2

Bootmode 13 - Config 3

125 MHz

156.25 MHz

One 4× SRIO link

All the other BOOTMODE[3:0] modes are reserved.

5.7.1 Second-Level Bootloaders

Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader

allows for any level of customization to current boot methods as well as the definition of a completely

customized boot.

5.7.2 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data

sections. The DSP's internal registers are programmed with predetermined values. The boot sequence is

started automatically after each power-on reset, warm reset, and system reset. A local reset to an

individual C64x+ Megamodule should not affect the state of the hardware boot controller on the device.

For more details on the initiators of the resets, see Section 4.8.3.

Detailed Description

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The SM320C6457-HIREL supports several boot processes begins execution at the ROM base address,

which contains the bootloader code necessary to support various device boot modes. The boot processes

are software driven; using the BOOTMODE[3:0] device configuration inputs to determine the software

configuration that must be completed.

5.8 Rake Search Accelerator (RSA)

On the C6457 device, there are two Rake Search Accelerators (RSAs). These RSAs are connected

directly to the C64x+ CPU. The RSA is an extension of the C64x+ CPU. The CPU performs send/receive

to the RSAs via the .L and .S functional units.

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6 器件和文档支持

6.1 器件命名规则

为了指出产品开发周期的阶段，TI 为所有数字信号处理 (DSP) 器件和支持工具的部件号指定了前缀。每个

DSP 商用系列成员产品具有以下三个前缀中的一个：TMX、TMP、或 TMS（例

如，TMX320C6457GMH）。德州仪器 (TI) 建议为其支持的工具使用三个可能前缀指示符中的两个：TMDX

和 TMDS。这些前缀代表了产品开发的发展阶段，即从工程原型 (TMX/TMDX) 直到完全合格的生产器件/工

具 (TMS/TMDS)。

器件开发进化流程：

•

TMX：试验器件不一定代表最终器件的电气技术规格

TMP：最终的芯片模型符合器件的电气技术规格，但是未经完整的质量和可靠性验证

TMS：完全合格的生产器件

支持工具开发发展流程：

•

TMDX：还未经德州仪器 (TI) 完整内部质量测试的开发支持产品。

TMDS：完全合格的开发支持产品

TMX 和 TMP 器件和 TMDX 开发支持工具在供货时附带如下免责条款：

“开发的产品用于内部评估用途。”

•

TMS 器件和 TMDS 开发支持工具已进行完全特性描述，并且器件的质量和可靠性已经完全论证。TI 的标准

保修证书适用。

预测显示原型器件（TMX 或者 TMP）的故障率大于标准生产器件。由于它们的预计的最终使用故障率仍未

定义，德州仪器 (TI) 建议不要将这些器件用于任何生产系统。只有合格的生产器件将被使用。

TI 器件的命名规则也包括一个带有器件系列名称的后缀。这个后缀表示封装类型（例如，GMH），温度范

围（例如，“空白”是默认温度范围），并以兆赫为单位的器件速度范围（例如，空白是

[1GHz]）。

1000MHz

图 6-1 提供了解读任一 TMS320C64x+™ DSP 系列产品完整器件名称的图例。

要获取采用 GMH 封装类型的 C6457 的部件号以及更多订购信息，请访问 TI 网站 www.ti.com 或者联系您

的 TI 销售代表。

SM

320

C6457

(

)

(

)

(

)

GMH

PREFIX

DEVICE SPEED RANGE

Blank = 1 GHz

TMX = Experimental device

TMS = Qualified device

TEMPERATURE RANGE

1 GHz: A = –55°C to +100°C

DEVICE FAMILY

320 = TMS320 DSP family

DEVICE

C64x+ DSP: C6457

PACKAGE TYPE^(A)

GMH = 688-pin plastic BGA, with Pb-ed solder balls

SILICON REVISION

D = Silicon Rev 1.4

图 6-1. TMS320C64x+™ DSP 器件命名规则（包括 C6457 DSP）

(A) BGA = 球栅阵列

6.2 工具与软件

为了方便客户基于 C6457 器件开发自己的特性和软件，德州仪器 (TI) 针对 TMS320C6000™ DSP 平台提

供了大量的开发工具，其中包括评估处理器性能、生成代码、开发算法工具、以及完全集成和调试软件及硬

件模块的工具。工具支持文档以电子文档形式提供，包含在 Code Composer Studio™集成开发环境 (IDE)

中。

器件和文档支持

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下列产品支持开发基于 C6000™ DSP 的应用：

•

软件开发工具:

–

Code Composer Studio™ 集成开发环境 (IDE)，其中包括编辑器、C/C++/汇编代码生成工具、调试

工具以及其他开发工具。

–

可扩展实时基础软件 (DSP/BIOS™)，提供支持所有 DSP 应用所需的基本运行时目标软件。

•

硬件开发工具:

–

扩展开发系统 (XDS™) 仿真器（支持 C6000™ DSP 多处理器系统调试）

EVM（评估模块）

6.3 文档支持

表 6-1 中列出的文档介绍了 C6457 通信基础设施数字信号处理器。www.ti.com.cn 网站上提供了这些文档的

副本。提示：请在 www.ti.com 上的搜索框中输入文献编号。

可从 C6000 DSP 产品文件夹 (www.ti.com/c6000) 中获取介绍 C6457、相关外设及其他技术材料的最新文

档。

表 6-1. 相关文档

TI 文献编号

说明

SPRU732

TMS320C64x/C64x+ DSP CPU 和指令集参考指南. 介绍 TMS320C6000 DSP 系列的 TMS320C64x 和

TMS320C64x+ 数字信号处理器 (DSP) 的 CPU 架构、管线、指令集和中断。C64x/C64x+ DSP 产品包括 C6000

DSP 平台中的定点器件。C64x+ DSP 是 C64x DSP 的增强版，增加了功能并扩展了指令集。

SPRU871

SPRAA84

SPRU889

SPRU925

SPRU725

《TMS320C64x+ 超级模块参考指南》。介绍 TMS320C64x+ 数字信号处理器 (DSP) 超级模块。针对内部直接存

储器访问 (IDMA) 控制器、中断控制器、掉电控制器、存储器保护、带宽管理以及存储器和缓存进行讨论。

TMS320C64x 至 TMS320C64x+ CPU 迁移指南. 介绍从德州仪器 TMS320C64x 数字信号处理器 (DSP) 至

TMS320C64x+ DSP 的迁移。该文档旨在指出这两种内核的差异，并不涉及相同的器件功能。

《高速 DSP 系统设计参考指南》。提供应对高速 DSP 系统设计诸多挑战的相关建议。这些建议信息针对 C5000

和 C6000 DSP 平台的 DSP 音频、视频及通信系统。

TMS320TCI648x DSP 外部存储器接口 (EMIF) 用户指南. 该文档介绍 TMS320TCI648x DSP 系列数字信号处理器

(DSP) 的外部存储器接口 (EMIF) 的操作。

《TMS320TCI648x DSP 通用输入/输出 (GPIO) 用户指南》。该文档介绍 TMS320TCI648x DSP 系列数字信号处

理器 (DSP) 的通用输入/输出 (GPIO) 外设。GPIO 外设提供专用的通用引脚，可以配置为输入或输出。当配置为输

入时，可以通过读取内部寄存器的状态检测输入的状态。当配置为输出时，可以写入内部寄存器以控制输出引脚上

驱动的状态。

SPRU874

SPRUE11

SPRU806

《TMS320TCI648x DSP 主机端口接口 (HPI) 用户指南》。该文档介绍 TMS320TCI648x 数字信号处理器 (DSP)

的主机端口接口 (HPI)。借助 HPI，外部主机处理器（主机）能够使用一个 16 位 (HPI16) 或 32 位 (HPI32) 接口直

接访问 DSP 资源（包括内部和外部存储器）。

《TMS320TCI648x DSP 内部集成电路 (I²C) 模块用户指南》。该文档介绍 TMS320TCI648x 数字信号处理器

(DSP) 的内部集成电路 (I²C) 模块。I²C 在 TMS320TCI648x 器件与符合 Philips Semiconductors 内部 IC 总线 (I²C

总线) 规范版本 2.1 并通过 I²C 总线连接的其他器件之间提供一个接口。该文档假定读者熟悉 I²C 总线规范。

《TMS320TCI648x DSP 软件可编程锁相环 (PLL) 控制器 UG》。该文档介绍 TMS320TCI648x 数字信号处理器

(DSP) 的软件可编程锁相环 (PLL) 控制器的操作。PLL 控制器利用可通过软件配置的倍频器和分频器从内部修改输

入信号，既灵活又方便。生成的时钟输出传递给 TMS320TCI648x DSP 内核、外设以及 TMS320TCI648x DSP 内

的其他模块。

SPRU818

SPRUE10

《TMS320TCI648x DSP 64 位定时器用户指南》。该文档简要介绍 TMS320TCI648x DSP 的 64 位定时器。该定

时器可配置为一个通用 64 位定时器、双通用 32 位定时器或者一个看门狗定时器。当配置为双 32 位定时器时，这

两半部分可以搭配使用（链接模式），也可以彼此独立使用（非链接模式）。

《TMS320TCI648x DSP Turbo 解码器协处理器 2 (TCP2) 参考指南》。第三代 (3G) 移动通信标准中的高比特率

数据通道的通道编码要求对 turbo 编码的数据进行解码。一些 TMS320C6000™ DSP 系列数字信号处理器 (DSP)

的 Turbo 解码器协处理器 (TCP) 设计用于按照 IS2000 和 3GPP 无线标准执行该操作。本文档介绍 TCP 的操作和

编程。

SPRUE09

SPRUFC4

《TMS320TCI648x DSP 维特比解码器协处理器 2 (VCP2) 参考指南》。第三代 (3G) 移动通信标准中的语音和低

比特率数据通道的通道编码要求对卷积编码数据进行解码。TMS320TCI648x 器件的维特比解码器协处理器 2

(VCP2) 设计用于按照 IS2000 及 3GPP 无线标准进行维特比解码。VCP2 协处理器设计用于针对 2G 和 3G 无线

系统执行前向纠错。VCP2 协处理器与德州仪器 (TI) DSP 组合使用可以提供一个成本非常低的高效协同解决方

案。VCP2 可以支持 1941 个 12.2Kbps A 类 3G 语音通道运行在 333MHz 下。本文档介绍 VCP2 的操作和编程。

《TMS320TCI6484 DSP 以太网介质访问控制器 (EMAC)/管理数据输入输出 (MDIO) 用户指南》。该文档给出了

TMS320TCI6487/8 器件集成的以太网介质访问控制器 (EMAC) 和物理层 (PHY) 器件管理数据输入输出 (MDIO)

模块的功能描述。其中包括 EMAC 和 MDIO 模块的特性，架构和操作的相关讨论，与外部的连接方式以及寄存

器说明。

202

器件和文档支持

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ZHCSFA5 –JULY 2016

表 6-1. 相关文档 (continued)

TI 文献编号

说明

SPRUGK5

《TMS320C6457 DSP DDR2 存储器控制器用户指南》。该文档介绍 TMS320C6457 数字信号处理器 (DSP) 的

DDR2 存储器控制器。

SPRUGK6

SPRUGK2

SPRUGL2

《TMS320C6457 DSP 增强型 DMA (EDMA3) 控制器用户指南》。该文档介绍 TMS320C6457 器件上的增强型

DMA (EDMA3) 控制器。

《TMS320C6457 DSP 外部存储器接口 (EMIF) 用户指南》。该文档介绍 TMS320C6457 DSP 系列数字信号处理

器 (DSP) 的外部存储器接口 (EMIF) 的操作。

《TMS320C6457 DSP 通用输入/输出 (GPIO) 用户指南》。该文档介绍 TMS320C6457 DSP 系列数字信号处理器

(DSP) 的通用输入/输出 (GPIO) 外设。GPIO 外设提供专用的通用引脚，可以配置为输入或输出。当配置为输入

时，可以通过读取内部寄存器的状态检测输入的状态。当配置为输出时，可以写入内部寄存器以控制输出引脚上驱

动的状态。

SPRUGK7

SPRUGK3

《TMS320C6457 DSP 主机端口接口 (HPI) 用户指南》。该文档介绍 TMS320C6457 数字信号处理器 (DSP) 的主

机端口接口 (HPI)。借助 HPI，外部主机处理器（主机）能够使用一个 16 位 (HPI16) 或 32 位 (HPI32) 接口直接访

问 DSP 资源（包括内部和外部存储器）。

《TMS320C6457 DSP 内部集成电路 (I²C) 模块用户指南》。该文档介绍 TMS320C6457 数字信号处理器 (DSP)

的内部集成电路 (I²C) 模块。I²C 在 TMS320C6457 器件与符合 Philips Semiconductors 内部 IC 总线 (I²C 总线)

规范版本 2.1 并通过 I²C 总线连接的其他器件之间提供一个接口。该文档假定读者熟悉 I²C 总线规范。

SPRUGK4

SPRUGL3

《TMS320C6457 串行 RapidIO (SRIO) 用户指南》。该文档介绍 TMS320C6457 器件的 RapidIO (SRIO)。

《TMS320C6457 DSP 软件可编程锁相环 (PLL) 控制器 UG》。该文档介绍 TMS320C6457 数字信号处理器

(DSP) 的软件可编程锁相环 (PLL) 控制器的操作。PLL 控制器利用可通过软件配置的倍频器和分频器从内部修改输

入信号，既灵活又方便。生成的时钟输出传递给 TMS320C6457 DSP 内核、外设以及 TMS320C6457 DSP 内的

其他模块。

SPRUGL0

SPRUGK1

《TMS320C6457 DSP 64 位定时器用户指南》。该文档简要介绍 TMS320C6457 DSP 的 64 位定时器。该定时器

可配置为一个通用 64 位定时器、双通用 32 位定时器或者一个看门狗定时器。当配置为双 32 位定时器时，这两半

部分可以搭配使用（链接模式），也可以彼此独立使用（非链接模式）。

《TMS320C6457 DSP Turbo 解码器协处理器 2 (TCP2) 参考指南》。第三代 (3G) 移动通信标准中的高比特率数

据通道的通道编码要求对 turbo 编码的数据进行解码。一些 TMS320C6000™ DSP 系列数字信号处理器 (DSP) 的

Turbo 解码器协处理器 (TCP) 设计用于按照 IS2000 和 3GPP 无线标准执行该操作。本文档介绍 TCP 的操作和编

程。

SPRUGL1

SPRUGK0

《TMS320C6457 DSP ATM 2 通用测试和运行 PHY 接口 (UTOPIA2) 用户指南》。该文档介绍 TMS320C6000™

DSP 系列 TMS320C6457 数字信号处理器 (DSP) 中用于异步传输模式 (ATM) 2 的通用测试和运行 PHY 接口

(UTOPIA2)。

《TMS320C6457 DSP 维特比解码器协处理器 2 (VCP2) 参考指南》。第三代 (3G) 移动通信标准中的语音和低比

特率数据通道的通道编码要求对卷积编码数据进行解码。TMS320C6457 器件的维特比解码器协处理器 2 (VCP2)

设计用于按照 IS2000 及 3GPP 无线标准进行维特比解码。VCP2 协处理器设计用于针对 2G 和 3G 无线系统执行

前向纠错。VCP2 协处理器与德州仪器 (TI) DSP 组合使用可以提供一个成本非常低的高效协同解决方案。VCP2

可以支持 1941 个 12.2Kbps A 类 3G 语音通道运行在 333MHz 下。本文档介绍 VCP2 的操作和编程。

SPRUGK9

《TMS320C6457 DSP 以太网介质访问控制器 (EMAC)/管理数据输入输出 (MDIO) 用户指南》。该文档给出了

TMS320C6457 器件集成的以太网介质访问控制器 (EMAC) 和物理层 (PHY) 器件管理数据输入输出 (MDIO) 模块

的功能描述。其中包括 EMAC 和 MDIO 模块的特性，架构和操作的相关讨论，与外部的连接方式以及寄存器说

明。

SPRUGK8

SPRUGL4

SPRUGL5

《TMS320C6457 DSP 多通道缓冲串行端口 (McBSP) 参考指南》。该文档介绍 TMS320C6000™ DSP 系列数字

信号处理器 (DSP) 的多通道缓冲串行端口 (McBSP) 的操作。

《TMS320C6457 DSP 电源/休眠控制器 (PSC) 用户指南》。该文档介绍 TMS320C6457 器件的电源/休眠控制器

(PSC) 的使用。

《TMS320C6457 DSP 自举程序用户指南》。本文档介绍 TMS320C6457 数字信号处理器 (DSP) 随附的片上自

举程序的特性。

6.3.1 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me)

注册后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史

记录。

6.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术

规范和标准且不一定反映 TI 的观点；请见 TI 的使用条款。

TI E2E™ 在线社区 TI 工程师对工程师 (E2E) 社区。此社区的创建目的是为了促进工程师之间协作。在

e2e.ti.com 中，您可以咨询问题、共享知识、探索思路，在同领域工程师的帮助下解决问题。

器件和文档支持

203

提交文档反馈意见

产品主页链接: SM320C6457-HIREL

SM320C6457-HIREL

ZHCSFA5 –JULY 2016

www.ti.com.cn

德州仪器 (TI) 嵌入式处理器维基网站德州仪器 (TI) 嵌入式处理器维基网站。此网站的建立是为了帮助开发

人员从德州仪器 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体

知识的创新和增长。

6.5 商标

TMS320C64x+, TMS320C6000, VelociTI, Code Composer Studio, E2E are trademarks of Texas

Instruments.

Windows is a registered trademark of Microsoft Corporation.

All other trademarks are the property of their respective owners.

6.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

6.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

204

器件和文档支持

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SM320C6457-HIREL

www.ti.com.cn

ZHCSFA5 –JULY 2016

7 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知

且不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

机械、封装和可订购信息

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型号：	SM320C6457-HIREL
厂家：	TEXAS INSTRUMENTS
描述：	高可靠性产品 C6457 定点 DSP
文件：	总207页 (文件大小：1815K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SM320C6457-HIREL [TI]

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