SM320DM6446-HIREL [TI]
Digital Media System-on-Chip;
| 型号： | SM320DM6446-HIREL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Digital Media System-on-Chip |
| 文件： | 总228页 (文件大小：1940K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM320DM6446
Digital Media System-on-Chip
www.ti.com
SPRS607A–JUNE 2009–REVISED JUNE 2009
1 Digital Media System-on-Chip (DMSoC)
1.1 Features
•
High-Performance Digital Media SoC
•
ARM926EJ-S Core
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–
–
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594-MHz C64x+™ Clock Rates
297-MHz ARM926EJ-S™ Clock Rates
Eight 32-Bit C64x+ Instructions/Cycle
4752 C64x+ MIPS
Fully Software-Compatible With C64x /
ARM9™
–
Support for 32-Bit and 16-Bit (Thumb®
Mode) Instruction Sets
DSP Instruction Extensions and Single
Cycle MAC
ARM® Jazelle® Technology
EmbeddedICE-RT™ Logic for Real-Time
Debug
–
–
–
–
Extended Temperature Devices Available
•
•
ARM9 Memory Architecture
•
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
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–
–
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16K-Byte Instruction Cache
8K-Byte Data Cache
16K-Byte RAM
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Eight Highly Independent Functional Units
•
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
8K-Byte ROM
Embedded Trace Buffer™ (ETB11™) With 4KB
Memory for ARM9 Debug
•
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
•
•
Endianness: Little Endian for ARM and DSP
Video Processing Subsystem
–
Front End Provides:
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Load-Store Architecture With Non-Aligned
Support
•
•
CCD and CMOS Imager Interface
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
–
–
–
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64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
•
•
Preview Engine for Real-Time Image
Processing
Glueless Interface to Common Video
Decoders
Additional C64x+™ Enhancements
•
•
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
•
•
Histogram Module
Auto-Exposure, Auto-White Balance and
Auto-Focus Module
•
Hardware Support for Modulo Loop
Operation
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Resize Engine
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C64x+ Instruction Set Features
–
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Resize Images From 1/4x to 4x
Separate Horizontal/Vertical Control
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Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
Compact 16-Bit Instructions
Additional Instructions to Support Complex
Multiplies
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Back End Provides:
•
•
Hardware On-Screen Display (OSD)
Four 54-MHz DACs for a Combination of
–
–
Composite NTSC/PAL Video
Luma/Chroma Separate Video
(S-video)
•
C64x+ L1/L2 Memory Architecture
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Component (YPbPr or RGB) Video
(Progressive)
–
–
–
32K-Byte L1P Program RAM/Cache (Direct
Mapped)
80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
64K-Byte L2 Unified Mapped RAM/Cache
(Flexible RAM/Cache Allocation)
•
Digital Output
–
–
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8-/16-bit YUV or up to 24-Bit RGB
HD Resolution
Up to 2 Video Windows
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2009, Texas Instruments Incorporated
SM320DM6446
Digital Media System-on-Chip
SPRS607A–JUNE 2009–REVISED JUNE 2009
www.ti.com
•
External Memory Interfaces (EMIFs)
–
–
IEEE 802.3 Compliant
Media Independent Interface (MII)
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32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
•
•
VLYNQ™ Interface (FPGA Interface)
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Asynchronous16-Bit Wide EMIF (EMIFA)
With 128M-Byte Address Reach
Host Port Interface (HPI) with 16-Bit
Multiplexed Address/Data
•
Flash Memory Interfaces
•
USB Port With Integrated 2.0 PHY
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–
–
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NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
USB 2.0 High-/Full-Speed (480-Mbps) Client
USB 2.0 High-/Full-/Low-Speed Host
(Mini-Host, Supporting One External
Device)
•
Flash Card Interfaces
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–
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Multimedia Card (MMC)/Secure Digital (SD)
with Secure Data I/O (SDIO)
Compact Flash Controller With True IDE
Mode
•
•
Three Pulse Width Modulator (PWM) Outputs
On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash or UART
SmartMedia
•
•
•
•
ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
Individual Power-Saving Modes for ARM/DSP
Flexible PLL Clock Generators
•
•
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
IEEE-1149.1 (JTAG) Boundary-
Scan-Compatible
•
•
One 64-Bit Watch Dog Timer
•
•
Up to 71 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
Three UARTs (One with RTS and CTS Flow
Control)
361-Pin Pb-Free BGA Package
(ZWT Suffix), 0.8-mm Ball Pitch
•
•
•
One Serial Peripheral Interface (SPI) With Two
Chip-Selects
Master/Slave Inter-Integrated Circuit (I2C
Bus™)
•
•
•
0.09-µm/6-Level Cu Metal Process (CMOS)
3.3-V and 1.8-V I/O, 1.2-V Internal
Applications:
Audio Serial Port (ASP)
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–
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I2S
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–
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Digital Media
Networked Media Encode/Decode
Video Imaging
AC97 Audio Codec Interface
Standard Voice Codec Interface (AIC12)
•
10/100 Mb/s Ethernet MAC (EMAC)
1.2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
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•
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•
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Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in A-Temp (–40°C/105°C) Temperature Range(1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
(1) Additional temperature ranges are available - contact factory
2
Digital Media System-on-Chip (DMSoC)
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SM320DM6446
Digital Media System-on-Chip
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SPRS607A–JUNE 2009–REVISED JUNE 2009
1.3 Description
The TMS320DM6446 devices (also referenced as DM6446 and including the SM320DM6446) leverages
TI’s DaVinci™ technology to meet the networked media encode and decode application processing needs
of next-generation embedded devices.
The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, high processing performance, and long battery life through the
maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set
Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an
ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core incorporates:
•
•
•
A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual
index virtual tag (VIVT).
The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the
TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation
high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas
Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a
code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of
the C64x+™ DSP with added functionality and an expanded instruction set.
Any reference to the C64x™ DSP or C64x™ CPU also applies, unless otherwise noted, to the C64x+™
DSP and C64x+™ CPU, respectively.
With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the
C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million
MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details
on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide
(literature number SPRU732).
The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level
cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the
Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)
consists of an 512K-bit memory space that is shared between program and data space. L2 memory can
be configured as mapped memory, cache, or combinations of the two.
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SM320DM6446
Digital Media System-on-Chip
SPRS607A–JUNE 2009–REVISED JUNE 2009
www.ti.com
The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a
Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio
serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers;
1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable
interrupt/event generation modes, multiplexed with other peripherals;
3 UARTs with hardware
handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory
interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a
higher speed synchronous memory interface for DDR2.
The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging
peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing
Back-End (VPBE) output with imaging co-processor (VICP) used for display.
The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine
(Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The
CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices
(CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS
sensor or CCD and converts from an RGB Bayer Pattern to YUV4:2:2. The Histogram and H3A modules
provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image
data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is
between 64 and 1024.
The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a
Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate
OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window
allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz,
providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC
also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of
8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and
the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps)
and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS)
support.
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the
MDIO module transparently monitors its link state by reading the PHY status register. Link change events
are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link
status of the device without continuously performing costly MDIO accesses.
The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or
communicate with host processors. The DM6446 also provides multimedia card support, MMC/SD, with
SDIO support.
The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging
processing tasks from the DSP core, making more DSP MIPS available for common video and imaging
algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please
contact your nearest TI sales representative.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The DM6446 has a complete set of development tools for both the ARM and DSP. These include C
compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™
debugger interface for visibility into source code execution.
4
Digital Media System-on-Chip (DMSoC)
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Digital Media System-on-Chip
www.ti.com
SPRS607A–JUNE 2009–REVISED JUNE 2009
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
BT.656,
Y/C,
Raw (Bayer)
Video-Imaging
JTAG Interface
Coprocessor (VICP)
Video Processing Subsystem (VPSS)
System Control
ARM Subsystem
DSP Subsystem
Front End
Back End
8b BT.656,
Y/C,
Input
Clock(s)
PLLs/Clock
Generator
ARM926EJ-S CPU
C64x+t DSP CPU
24b RGB
64 KB L2 RAM
16 KB
8 KB
10b DAC
On-Screen Video
Display Encoder
Resizer
CCD
Controller
Video
I-Cache D-Cache
Power/Sleep
Controller
NTSC/
PAL,
10b DAC
10b DAC
10b DAC
Histogram/
3A
32 KB
80 KB
(OSD)
(VENC)
L1 Pgm L1 Data
S-Video,
RGB,
16 KB RAM
16 KB ROM
Pin
Multiplexing
Preview
Interface
YPbPr
Switched Central Resource (SCR)
Peripherals
Serial Interfaces
System
General-
Purpose
Timer
Audio
Serial
Port
Watchdog
Timer
EDMA
2
I C
SPI
PWM
UART
Program/Data Storage
Connectivity
EMAC
DDR2
Mem Ctlr
(16b/32b)
Async EMIF/
NAND/
SmartMedia
ATA/
Compact
Flash
USB 2.0
PHY
MMC/
VLYNQ
With
HPI
SD/
MDIO
SDIO
Figure 1-1. TMS320DM6446 Functional Block Diagram
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SM320DM6446
Digital Media System-on-Chip
SPRS607A–JUNE 2009–REVISED JUNE 2009
www.ti.com
Contents
1
2
Digital Media System-on-Chip (DMSoC) ............ 1
6.1 Parameter Information .............................. 86
6.2
Recommended Clock and Control Signal Transition
1.1 Features .............................................. 1
Behavior ............................................. 87
1.2
SUPPORTS DEFENSE, AEROSPACE, AND
MEDICAL APPLICATIONS........................... 2
6.3 Power Supplies...................................... 87
6.4 Reset ................................................ 97
1.3 Description............................................ 3
1.4 Functional Block Diagram ............................ 5
Device Overview ......................................... 6
2.1 Device Characteristics................................ 6
2.2 Device Compatibility .................................. 8
2.3 ARM Subsystem...................................... 8
2.4 DSP Subsystem..................................... 12
2.5 Memory Map Summary ............................. 16
2.6 Pin Assignments .................................... 19
2.7 Terminal Functions.................................. 24
2.8 Device Support ...................................... 56
Device Configurations................................. 59
3.1 System Module Registers ........................... 59
3.2 Power Considerations............................... 59
3.3 Bootmode ........................................... 60
3.4 Configurations at Reset ............................. 64
3.5 Configurations After Reset .......................... 68
3.6 Emulation Control ................................... 79
System Interconnect................................... 81
4.1 System Interconnect Block Diagram ................ 82
Device Operating Conditions ........................ 83
6.5
External Clock Input From MXI/CLKIN Pin ........ 100
6.6 Clock PLLs......................................... 102
6.7 Interrupts........................................... 110
6.8
General-Purpose Input/Output (GPIO)............. 117
Enhanced Direct Memory Access (EDMA)
6.9
Controller........................................... 120
6.10 External Memory Interface (EMIF)................. 132
6.11 ATA/CF ............................................ 140
6.12 MMC/SD/SDIO..................................... 153
6.13 Video Processing Sub-System (VPSS) Overview . 156
6.14 Host-Port Interface (HPI)........................... 179
3
6.15 USB 2.0 ............................................ 182
6.16 Universal Asynchronous Receiver/Transmitter
(UART) ............................................. 191
6.17 Serial Peripheral Interface (SPI) ................... 194
6.18 Inter-Integrated Circuit (I2C) ....................... 198
6.19 Audio Serial Port (ASP)............................ 202
6.20 Ethernet Media Access Controller (EMAC) ........ 206
6.21 Management Data Input/Output (MDIO)........... 213
6.22 Timer............................................... 215
6.23 Pulse Width Modulator (PWM)..................... 217
6.24 VLYNQ ............................................. 219
6.25 IEEE 1149.1 JTAG ................................ 223
Mechanical Packaging and Orderable
Information............................................. 225
7.1 Thermal Data for ZWT ............................. 225
7.1.1 Packaging Information............................. 225
4
5
5.1
Absolute Maximum Ratings Over Operating Case
Temperature Range
(Unless Otherwise Noted) ................................. 83
5.2 Recommended Operating Conditions............... 84
7
5.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............ 85
6
Peripheral and Electrical Specifications........... 86
2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the TMS320DM6446 SoC. The table shows significant features of the
device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the
C64x+ DSP, and the package type with pin count.
6
Contents
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Digital Media System-on-Chip
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SPRS607A–JUNE 2009–REVISED JUNE 2009
Table 2-1. Characteristics of the Processor
HARDWARE FEATURES
DM6446
DDR2 Memory Controller
DDR2 (16/32-bit bus width)
Asynchronous (8/16-bit bus width) RAM, Flash
(NOR, NAND)
Asynchronous EMIF (EMIFA)
Compact Flash
MMC/SD with secure data input/output (SDIO)
SmartMedia/xD
Flash Cards
EDMA
64 independent channels
8 QDMA channels
2 64-Bit General Purpose (each configurable as 2
separate 32-bit timers)
Timers
1 64-Bit Watchdog
UART
3 (one with RTS and CTS flow control)
Peripherals
SPI
I2C
1 (supports 2 slave devices)
Not all peripherals pins are
available at the same time
(for more detail, see the
Device Configurations
section).
1 (Master/Slave)
1
Audio Serial Port [ASP]
10/100 Ethernet MAC with Management Data
Input/Output
1
VLYNQ
1
1 (16-bit multiplexed address/data)
Up to 71
HPI
General-Purpose Input/Output Port
PWM
3 outputs
ATA/CF
1 (ATA/ATAPI-6)
1 Input (VPFE)
1 Output (VPBE)
Configurable Video Ports
High Speed Device
High Speed Host
USB 2.0
Size (Bytes)
160KB RAM, 8KB ROM
DSP
•
•
•
32KB L1 Program (L1P)/Cache (up to 32KB)
80KB L1 Data (L1D)/Cache (up to 32KB)
64KB Unified Mapped RAM/Cache (L2)
On-Chip Memory
Organization
ARM
•
•
•
•
16KB I-cache
8KB D-cache
16KB RAM
8KB ROM
CPU ID + CPU Rev ID
Control Status Register (CSR.[31:16])
0x1000
C64x+ Megamodule
Revision
Revision ID Register (MM_REVID[15:0])
(address location: 0x0181 2000)
0x0000 (Silicon Revision 1.3 and earlier)
0x0003 (Silicon Revision 2.1)
JTAGID Register
(address location: 0x01C4 0028)
0x0B70 002F (Silicon Revision 1.3 and earlier)
0x1B70 002F (Silicon Revision 2.1)
JTAG BSDL_ID
CPU Frequency
DSP 594 MHz
ARM 297 MHz
DSP 1.68 ns
ARM 3.37 ns
1.2 V
Cycle Time
Core (V)
I/O (V)
Voltage
1.8 V, 3.3 V
CLKIN frequency multiplier
(27 MHz reference)
PLL Options
x1 (Bypass), x22
BGA Package
16 x 16 mm
361-Pin BGA (ZWT)
Process Technology
µm
0.09 µm
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Device Overview
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SM320DM6446
Digital Media System-on-Chip
SPRS607A–JUNE 2009–REVISED JUNE 2009
www.ti.com
Table 2-1. Characteristics of the Processor (continued)
HARDWARE FEATURES
DM6446
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product Status(1)
PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
2.2 Device Compatibility
The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.
The C64x+ DSP core is code-compatible with the C6000™ DSP platform and supports features of the
C64x DSP family.
2.3 ARM Subsystem
The ARM Subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In
general, the ARM is responsible for configuration and control of the device; including the DSP Subsystem,
the VPSS Subsystem, and a majority of the peripherals and external memories.
The ARM Subsystem includes the following features:
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ARM926EJ-S RISC processor
ARMv5TEJ (32/16-bit) instruction set
Little endian
Co-Processor 15 (CP15)
MMU
16KB Instruction cache
8KB Data cache
Write Buffer
16KB Internal RAM (32-bit wide access)
8KB Internal ROM (ARM bootloader for non-EMIFA boot options)
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
ARM Interrupt controller
PLL Controller
Power and Sleep Controller (PSC)
System Module
2.3.1 ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
•
•
ARM926EJ -S integer core
CP15 system control coprocessor
8
Device Overview
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•
•
•
•
•
•
Memory Management Unit (MMU)
Separate instruction and data Caches
Write buffer
Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces
Separate instruction and data AHB bus interfaces
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
2.3.2 CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM
subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions,
when the ARM in a privileged mode such as supervisor or system mode.
2.3.3 MMU
The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux®,
Windows® CE, Ultron®, ThreadX®, etc. A single set of two level page tables stored in main memory is
used to control the address translation, permission checks and memory region attributes for both data and
instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the
information held in the page tables. The MMU features are:
•
•
Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
Mapping sizes are:
–
–
–
–
1MB (sections)
64KB (large pages)
4KB (small pages)
1KB (tiny pages)
•
Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
•
•
•
•
Hardware page table walks
Invalidate entire TLB, using CP15 register 8
Invalidate TLB entry, selected by MVA, using CP15 register 8
Lockdown of TLB entries, using CP15 register 10
2.3.4 Caches and Write Buffer
The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following
features:
•
•
Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
•
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables.
•
•
Critical-word first cache refilling
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
•
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
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•
Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
2.3.5 Tightly Coupled Memory (TCM)
ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt
Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM
and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides
for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the
D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be
stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM
sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to
the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to
the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.
Instruction and Data accesses are differentiated via accessing different memory map regions, with the
instruction region from 0x0000 through 0x7FFF and data from 0x8000 through 0xFFFF. The instruction
region at 0x0000 and data region at 0x8000 map to the same physical 16KB TCM RAM. Placing the
instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,
as required by the ARM architecture. The internal 16-KB RAM is split into two physical banks of 8KB
each, which allows simultaneous instruction and data accesses to be accomplished if the code and data
are in separate banks.
2.3.6 Advanced High-Performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
2.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the DM6446 also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
•
•
Trace Port provides real-time trace capability for the ARM9.
Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The DM6446 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer.
The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured
trace data.
2.3.8 ARM Memory Mapping
The ARM memory map is shown in Section 2.5, Memory Map Summary of this document. The ARM has
access to memories shown in the following sections.
2.3.8.1 ARM Internal Memories
The ARM has access to the following ARM internal memories:
•
16KB ARM Internal RAM on TCM interface, logically separated into two 8KB pages to allow
simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data
(D-TCM) to the different memory regions.
•
8KB ARM Internal ROM
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2.3.8.2 External Memories
The ARM has access to the following external memories:
•
•
•
•
DDR2 Synchronous DRAM
Asynchronous EMIF / NOR Flash / NAND Flash
ATA/CF
Flash card devices:
–
–
–
MMC/SD with SDIO
xD
SmartMedia
2.3.8.3 DSP Memories
The ARM has access to the following DSP memories:
•
•
•
L2 RAM
L1P RAM
L1D RAM
2.3.8.4 ARM-DSP Integration
DM6446 ARM and DSP integration features are as follows:
•
•
•
DSP visibility from ARM’s memory map, see Section 2.5, Memory Map Summary, for details
Boot Modes for DSP - see Device Configurations section, Section 3.3.3, DSP Boot, for details
ARM control of DSP boot / reset - see Device Configurations section, Section 3.3.2, ARM Boot, for
details
•
•
ARM control of DSP isolation and powerdown / powerup - see Section 3, Device Configurations, for
details
ARM & DSP Interrupts - see Section 6.7.1, ARM CPU Interrupts, and Section 6.7.2, DSP Interrupts, for
details
2.3.9 Peripherals
The ARM9 has access to all of the peripherals on the DM6446 device with the exception of the VICP.
2.3.10 PLL Controller (PLLC)
The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for
configuring DM6446’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following
configuration and control:
•
•
•
•
•
PLL Bypass Mode
Set PLL multiplier parameters
Set PLL divider parameters
PLL power down
Oscillator power down
The PLLs are briefly described in this document in the Clocking section. For more detailed information on
the PLLs and PLL Controller register descriptions, see Section 2.8.3, Documentation Support, of this
document for the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14).
2.3.11 Power and Sleep Controller (PSC)
The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings
accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating
and power domain shut-off. Brief details on the PSC are given in Section 6.3, Power Supplies. For more
detailed information and complete register descriptions for the PSC, see Section 2.8.3, Documentation
Support, for the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14).
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2.3.12 ARM Interrupt Controller (AINTC)
The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ
(interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this
document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see
Section 2.8.3, Documentation Support for the ARM Subsystem Guide.
2.3.13 System Module
The ARM Subsystem includes the System module. The System module consists of a set of registers for
configuring and controlling a variety of system functions. For details and register descriptions for the
System module, see Section 3, Device Configurations and see Section 2.8.3, Documentation Support, for
the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14).
2.3.14 Power Management
DM6446 has several means of managing power consumption. There is extensive use of clock gating,
which reduces the power used by global device clocks and individual peripheral clocks. Clock
management can be utilized to reduce clock frequencies in order to reduce switching power. For more
details on power management techniques, see Section 3, Device Configurations, Section 6, Peripheral
and Electrical Specifications, and see Section 2.8.3, Documentation Support, for the TMS320DM644x
ARM Subsystem Reference Guide (literature number SPRUE14).
DM6446 gives the programmer full flexibility to use any and all of the previously mentioned capabilities to
customize an optimal power management strategy. Several typical power management scenarios are
described in the following sections.
2.4 DSP Subsystem
The DSP Subsystem includes the following features:
•
•
•
•
•
C64x+ DSP CPU
32KB L1 Program (L1P)/Cache (up to 32KB)
80KB L1 Data (L1D)/Cache (up to 32KB)
64KB Unified Mapped RAM/Cache (L2)
Little endian
2.4.1 C64x+ DSP CPU Description
The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain
32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be
data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit
data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are
stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or
32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
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modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for audio and other
high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•
SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
•
Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•
•
•
•
Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following
documents:
•
•
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)
TMS320C64x Technical Overview (literature number SPRU395)
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Even
register
file A
(A0, A2,
A4...A30)
src1
src2
Odd
register
file A
(A1, A3,
A5...A31)
.L1
odd dst
even dst
long src
(D)
8
32 MSB
32 LSB
ST1b
ST1a
8
long src
even dst
odd dst
src1
(D)
Data path A
.S1
src2
32
32
(A)
(B)
dst2
dst1
src1
.M1
src2
(C)
32 MSB
32 LSB
LD1b
LD1a
dst
src1
src2
.D1
.D2
DA1
2x
1x
Even
register
file B
(B0, B2,
B4...B30)
Odd
register
file B
(B1, B3,
B5...B31)
src2
DA2
src1
dst
32 LSB
LD2a
LD2b
32 MSB
src2
(C)
.M2
src1
dst2
32
32
(B)
(A)
dst1
src2
src1
.S2
odd dst
even dst
long src
(D)
Data path B
8
8
32 MSB
32 LSB
ST2a
ST2b
long src
even dst
(D)
odd dst
.L2
src2
src1
Control Register
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-1. SM320C64x+™ CPU (DSP Core) Data Paths
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2.4.2 DSP Memory Mapping
The DSP memory map is shown in Section 2.5. Configuration of the control registers for DDR2, EMIFA,
and ARM Internal RAM is supported by the ARM. The DSP has access to memories shown in the
following sections.
2.4.2.1 ARM Internal Memories
The DSP has access to the 16KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only).
2.4.2.2 External Memories
The DSP has access to the following External memories:
•
•
DDR2 Synchronous DRAM
Asynchronous EMIF / NOR Flash
2.4.2.3 DSP Internal Memories
The DSP has access to the following DSP memories:
•
•
•
L2 RAM
L1P RAM
L1D RAM
2.4.2.4 C64x+ CPU
The C64x+ core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB
direct mapped cache and the Level 1 Data cache (L1D) is 80 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 64 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.
Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device.
Table 2-2. C64x+ Cache Registers
HEX ADDRESS RANGE
0x0184 0000
REGISTER ACRONYM
L2CFG
DESCRIPTION
L2 Cache configuration register
0x0184 0020
L1PCFG
L1PCC
L1P Size Cache configuration register
L1P Freeze Mode Cache configuration register
L1D Size Cache configuration register
L1D Freeze Mode Cache configuration register
Reserved
0x0184 0024
0x0184 0040
L1DCFG
L1DCC
0x0184 0044
0x0184 0048 - 0x0184 0FFC
0x0184 1000
-
EDMAWEIGHT
-
L2 EDMA access control register
Reserved
0x0184 1004 - 0x0184 1FFC
0x0184 2000
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
-
L2 allocation register 0
0x0184 2004
L2 allocation register 1
0x0184 2008
L2 allocation register 2
0x0184 200C
L2 allocation register 3
0x0184 2010 - 0x0184 3FFF
0x0184 4000
Reserved
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2IBAR
L2 writeback base address register
L2 writeback word count register
L2 writeback invalidate base address register
L2 writeback invalidate word count register
L2 invalidate base address register
L2 invalidate word count register
L1P invalidate base address register
L1P invalidate word count register
L1D writeback invalidate base address register
0x0184 4004
0x0184 4010
0x0184 4014
0x0184 4018
0x0184 401C
L2IWC
0x0184 4020
L1PIBAR
L1PIWC
L1DWIBAR
0x0184 4024
0x0184 4030
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Table 2-2. C64x+ Cache Registers (continued)
HEX ADDRESS RANGE
0x0184 4034
REGISTER ACRONYM
L1DWIWC
-
DESCRIPTION
L1D writeback invalidate word count register
Reserved
0x0184 4038
0x0184 4040
L1DWBAR
L1DWWC
L1DIBAR
L1DIWC
L1D Block Writeback
0x0184 4044
L1D Block Writeback
0x0184 4048
L1D invalidate base address register
L1D invalidate word count register
Reserved
0x0184 404C
0x0184 4050 - 0x0184 4FFF
0x0184 5000
-
L2WB
L2 writeback all register
0x0184 5004
L2WBINV
L2INV
L2 writeback invalidate all register
L2 Global Invalidate without writeback
Reserved
0x0184 5008
0x0184 500C - 0x0184 5027
0x0184 5028
-
L1PINV
L1P Global Invalidate
0x0184 502C - 0x0184 5039
0x0184 5040
-
Reserved
L1DWB
L1D Global Writeback
0x0184 5044
L1DWBINV
L1DINV
L1D Global Writeback with Invalidate
L1D Global Invalidate without writeback
Reserved 0x0000 0000 - 0x01FF FFFF
0x0184 5048
0x0184 8000 - 0x0184 8004
0x0184 8008 - 0x0184 8024
0x0184 8028 - 0x0184 802C
0x0184 8030 - 0x0184 803C
0x0184 8040 - 0x0184 8104
MAR0 - MAR1
MAR2 - MAR9
MAR10 - MAR11
MAR12 - MAR15
MAR16 - MAR65
Memory Attribute Registers for EMIFA 0x0200 0000 - 0x09FF FFFF
Reserved 0x0A00 0000 - 0x0BFF FFFF
Memory Attribute Registers for VLYNQ 0x0C00 0000 - 0x0FFF FFFF
Reserved 0x1000 0000 - 0x41FF FFFF
Memory Attribute Registers for EMIFA/VLYNQ Shadow 0x4200 0000 -
0x4FFF FFFF
0x0184 8108 - 0x0184 813C
MAR66 - MAR79
0x0184 8140- 0x0184 81FC
0x0184 8200 - 0x0184 823C
0x0184 8240 - 0x0184 83FC
MAR80 - MAR127
MAR128 - MAR143
MAR144 - MAR255
Reserved 0x5000 0000 - 0x7FFF FFFF
Memory Attribute Registers for DDR2 0x8000 0000 - 0x8FFF FFFF
Reserved 0x9000 0000 - 0xFFFF FFFF
2.4.3 Peripherals
The DSP has controllability for the following peripherals:
•
•
•
•
VICP
EDMA
ASP
2 Timers (Timer 0 and Timer1) that can each be configured as 1 64-bit or 2 32-bit timers
2.4.4 DSP Interrupt Controller
The DSP Interrupt Controller accepts device interrupts and appropriately maps them to the DSP’s
available interrupts. The DSP Interrupt Controller is briefly described in this document in the Interrupts
section. For more detailed on the DSP Interrupt Controller, see the Documentation Support section of this
document for the C64x+ CPU User's Guide.
2.5 Memory Map Summary
Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of
the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories
associated with its two processors and various subsystems. To help simplify software development a
unified memory map is used where possible to maintain a consistent view of device resources across all
bus masters.
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Table 2-3. Memory Map Summary
START
ADDRESS
END
ADDRESS
SIZE
(Bytes)
EDMA/
PERIPHERAL
ARM
C64x+
HPI
VPSS
0x0000 0000
0x0000 2000
0x0000 4000
0x0000 6000
0x0000 8000
0x0000 A000
0x0000 C000
0x0000 E000
0x0001 0000
0x0010 0000
0x0020 0000
0x0080 0000
0x0081 0000
0x00E0 8000
0x00E1 0000
0x00F0 4000
0x00F1 0000
0x00F1 8000
0x0180 0000
0x01BC 0000
0x01BC 1000
0x01BC 1800
0x01BC 1900
0x01C0 0000
0x0200 0000
0x0A00 0000
0x0C00 0000
0x1000 0000
0x1000 8000
0x1000 A000
0x1000 C000
0x1000 E000
0x1001 0000
0x1110 0000
0x1120 0000
0x1180 0000
0x1181 0000
0x11E0 8000
0x11E1 0000
0x11F0 4000
0x11F1 0000
0x11F1 8000
0x0000 1FFF
0x0000 3FFF
0x0000 5FFF
0x0000 7FFF
0x0000 9FFF
0x0000 BFFF
0x0000 DFFF
0x0000 FFFF
0x000F FFFF
0x001F FFFF
0x007F FFFF
0x0080 FFFF
0x00E0 7FFF
0x00E0 FFFF
0x00F0 3FFF
0x00F0 FFFF
0x00F1 7FFF
0x017F FFFF
0x01BB FFFF
0x01BC 0FFF
0x01BC 17FF
0x01BC 18FF
0x01BF FFFF
0x01FF FFFF
0x09FF FFFF
0x0BFF FFFF
0x0FFF FFFF
0x1000 7FFF
0x1000 9FFF
0x1000 BFFF
0x1000 DFFF
0x1000 FFFF
0x110F FFFF
0x111F FFFF
0x117F FFFF
0x1180 FFFF
0x11E0 7FFF
0x11E0 FFFF
0x11F0 3FFF
0x11F0 FFFF
0x11F1 7FFF
0x1FFF FFFF
8K
8K
ARM RAM0 (Instruction)
ARM RAM1 (Instruction)
ARM ROM (Instruction)
Reserved
Reserved
Reserved
8K
8K
8K
ARM RAM0 (Data)
ARM RAM1 (Data)
ARM ROM (Data)
Reserved
ARM RAM0
ARM RAM1
ARM ROM
ARM RAM0
ARM RAM1
ARM ROM
8K
8K
8K
960K
1M
VICP
6M
Reserved
64K
6112K
32K
976K
48K
32K
9120K
3840K
4K
L2 RAM/Cache
Reserved
Reserved
L1P Cache
Reserved
Reserved
Reserved
L1D RAM
L1D Cache
Reserved
ARM ETB Memory
ARM ETB Registers
ARM IceCrusher
2K
CFG Space
256
255744 Reserved
CFG Bus Peripherals(1)
Reserved
4M
CFG Bus Peripherals
CFG Bus Peripherals
EMIFA (Data)
CFG Bus Peripherals
EMIFA (Data)
Reserved
128M EMIFA (Code and Data)
32M
64M
32K
8K
Reserved
VLYNQ (Remote)
Reserved
VLYNQ (Remote)
Reserved
ARM RAM0
ARM RAM1
ARM ROM
ARM RAM0
8K
ARM RAM1
8K
ARM ROM
Reserved
8K
17344K
1M
Reserved
Reserved
Reserved
6M
64K
L2 RAM/Cache
L2 RAM/Cache
Reserved
L2 RAM/Cache
Reserved
6112K Reserved
32K L1P Cache
976K Reserved
L1P Cache
Reserved
L1P Cache
Reserved
48K
32K
L1D RAM
L1D RAM
L1D RAM
L1D RAM/Cache
L1D RAM/Cache
Reserved
L1D RAM/Cache
Reserved
241M- Reserved
32K
0x2000 0000
0x2000 8000
0x4200 0000(2)
0x5000 0000
0x8000 0000
0x9000 0000
0x2000 7FFF
32K
DDR2 Control Registers
DDR2 Control Registers
Reserved
DDR2 Control Registers
Reserved
DDR2 Control Registers
Reserved
0x41FF FFFF 544M-32k Reserved
0x4FFF FFFF
0x7FFF FFFF
0x8FFF FFFF
0xFFFF FFFF
224M Reserved
768M Reserved
256M DDR2
EMIFA/VLYNQ Shadow
Reserved
EMIFA/VLYNQ Shadow
Reserved
DDR2
DDR2
DDR2
DDR2
1792M Reserved
Reserved
Reserved
Reserved
Reserved
(1) HPI's access to the configuration bus peripherals is limited to the power and sleep controller registers, PLL1 and PLL2 registers, and
HPI configuration registers.
(2) EMIFA shadow memory started a 0x4200 0000 is physically the same memory as location 0x0200 0000. Memory range 0x200 0000
through 0x09FF FFFF should only be used by C64x+ for data accesses. Memory range 0x4200 0000 through 0x4FFF FFFF can be
used by C64x+ for both code execution and data accesses.
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Table 2-4. Configuration Memory Map Summary
START
END
SIZE
ARM/EDMA
C64x+
ADDRESS
ADDRESS
(Bytes)
0x0180 0000
0x0181 0000
0x0181 1000
0x0181 2000
0x0182 0000
0x0183 0000
0x0184 0000
0x0185 0000
0x0188 0000
0x01BC 0000
0x01BC 0100
0x01BC 0200
0x01BC 1000
0x01BC 1800
0x01BC 1900
0x01C0 0000
0x01C1 0000
0x01C1 0400
0x01C1 8800
0x01C1 A000
0x01C2 0000
0x01C2 0400
0x01C2 0800
0x01C2 0C00
0x01C2 1000
0x01C2 1400
0x01C2 1800
0x01C2 1C00
0x01C2 2000
0x01C2 2400
0x01C2 2800
0x01C2 2C00
0x01C4 0000
0x01C4 0800
0x01C4 0C00
0x01C4 1000
0x01C4 2000
0x01C4 2030
0x0180 FFFF
0x0181 0FFF
0x0181 1FFF
0x0181 2FFF
0x0182 FFFF
0x0183 FFFF
0x0184 FFFF
0x0187 FFFF
0x01BB FFFF
0x01BC 00FF
0x01BC 01FF
0x01BC 0FFF
0x01BC 17FF
0x01BC 18FF
0x01BF FFFF
0x01C0 FFFF
0x01C1 03FF
0x01C1 07FF
0x01C1 9FFF
0x01C1 FFFF
0x01C2 03FF
0x01C2 07FF
0x01C2 0BFF
0x01C2 0FFF
0x01C2 13FF
0x01C2 17FF
0x01C2 1BFF
0x01C2 1FFF
0x01C2 23FF
0x01C2 27FF
0x01C2 2BFF
0x01C3 FFFF
0x01C4 07FF
0x01C4 0BFF
0x01C4 0FFF
0x01C4 1FFF
0x01C4 202F
0x01C4 2033
64K
4K
C64x+ Interrupt Controller
C64x+ Powerdown Controller
C64x+ Security ID
C64x+ Revision ID
C64x+ EMC
4K
4K
64K
64K
64K
192K
3328K
256
256
3.5K
2K
Reserved
Reserved
C64x+ Memory System
Reserved
Reserved
Reserved
ARM ETB Memory
Pin Manager and Trace
ARM ETB Registers
ARM Ice Crusher
Reserved
256
255744 Reserved
64K
1K
1K
6K
24K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
117K
2K
1K
1K
4K
48
EDMA CC
EDMA TC0
EDMA TC1
EDMA CC
EDMA TC0
EDMA TC1
Reserved
UART0
UART1
Reserved
UART2
Reserved
I2C
Timer0
Timer0
Timer1
Timer1
Timer2 (Watchdog)
PWM0
PWM1
Reserved
PWM2
Reserved
System Module
PLL Controller 1
PLL Controller 2
Power and Sleep Controller
Reserved
System Module
Reserved
Power and Sleep Controller
Reserved
4
DDR2 VTP Reg
DDR2 VTP Reg
18
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Table 2-4. Configuration Memory Map Summary (continued)
START
END
SIZE
ARM/EDMA
C64x+
ADDRESS
0x01C4 2034
0x01C4 2400
0x01C4 8000
0x01C4 8400
0x01C6 0000
0x01C6 4000
0x01C6 6000
0x01C6 6800
0x01C6 7000
0x01C6 7800
0x01C6 8000
0x01C7 0000
0x01C7 4000
0x01C8 0000
0x01C8 1000
0x01C8 2000
0x01C8 4000
0x01C8 4800
0x01C8 5000
0x01CC 0000
0x01CE 0000
0x01D0 0000
0x01E0 0000
0x01E0 1000
0x01E0 2000
0x01E0 4000
0x01E1 0000
0x01E2 0000
0x01E4 0000
0x0200 0000
0x0400 0000
0x0600 0000
0x0800 0000
0x0A00 0000
0x0C00 0000
ADDRESS
(Bytes)
0x01C4 23FF
0x01C4 7FFF
0x01C4 83FF
0x01C5 FFFF
0x01C6 3FFF
0x01C6 5FFF
0x01C6 67FF
0x01C6 6FFF
0x01C6 77FF
0x01C6 7FFF
0x01C6 FFFF
0x01C7 3FFF
0x01C7 FFFF
0x01C8 0FFF
0x01C8 1FFF
0x01C8 3FFF
0x01C8 47FF
0x01C8 4FFF
0x01CB FFFF
0x01CD FFFF
0x01CF FFFF
0x01DF FFFF
0x01E0 0FFF
0x01E0 1FFF
0x01E0 3FFF
0x01E0 FFFF
0x01E1 FFFF
0x01E3 FFFF
0x01FF FFFF
0x03FF FFFF
0x05FF FFFF
0x07FF FFFF
0x09FF FFFF
0x0BFF FFFF
0x0FFF FFFF
1K - 52
23K
1K
Reserved
ARM Interrupt Controller
Reserved
95K
16K
8K
Reserved
USB2.0 Registers / RAM
ATA/CF
2K
2K
SPI
2K
GPIO
2K
HPI
HPI
32K
16K
48K
4K
Reserved
VPSS Registers
Reserved
EMAC Control Registers
EMAC Control Module Registers
EMAC Control Module RAM
MDIO Control Registers
4K
Reserved
8K
2K
2K
Reserved
VICP
236K
128K
128K
1M
VICP
Reserved
Reserved
ASP
4K
EMIFA Control
VLYNQ Control Registers
ASP
4K
8K
48K
64K
128K
1792K
32M
32M
32M
32M
32M
64M
Reserved
MMC/SD/SDIO
Reserved
Reserved
EMIFA Data/Code (CS2)
EMIFA Data/Code (CS3)
EMIFA Data/Code (CS4)
EMIFA Data/Code (CS5)
Reserved
EMIFA Data (CS2)
EMIFA Data (CS3)
EMIFA Data (CS4)
EMIFA Data (CS5)
Reserved
VLYNQ (Remote)
2.6 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. For more information on pin
muxing, see Section 3.5.2, Multiplexed Pin Configurations, of this document.
2.6.1 Pin Map (Bottom View)
Figure 2-2 through Figure 2-5 show the bottom view of the package pin assignments in four quadrants (A,
B, C, and D).
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1
2
3
4
5
6
7
8
9
10
W
V
U
T
W
RSV3
DDR_D[4]
DDR_D[7]
DDR_D[9]
DDR_D[12]
DDR_D[14]
DDR_CLK0
DDR_CLK0
DDR_A[12]
DDR_A[11]
V
U
T
DDR_D[2]
DDR_D[0]
DDR_D[3]
DDR_D[1]
DDR_D[6]
DDR_D[5]
DDR_D[8]
DDR_D[11]
DDR_D[10]
DDR_D[13]
DDR_D[15]
DDR_RAS
DDR_CAS
DDR_CKE
DDR_BS[0]
DDR_WE
RSV7
DDR_BS[1]
DDR_BS[2]
DDR_CS
DDR_A[8]
DDR_A[10]
DDR_DQS[0]
DDR_DQS[1]
EM_CS5/
GPIO8/
VLYNQ_
CLOCK
EM_CS4/
GPIO9/
VLYNQ_
SCRUN
EM_A[21]/
GPIO10/
VLYNQ_TXD0
DDR_
DQM[0]
DDR_
DQM[1]
DV
DDR_VDDDLL
DDR2
EM_A[17]/
GPIO14/
EM_A[20]/
GPIO11/
EM_A[19]/
GPIO12/
EM_A[16]/
GPIO15/
EM_A[12]/
GPIO19
R
P
N
M
L
R
P
N
M
L
V
V
V
DV
V
SS
SS
SS
SS
DDR2
VLYNQ_TXD2 VLYNQ_RXD0 VLYNQ_TXD1 VLYNQ_RXD2
EM_A[15]/
GPIO16/
EM_A[14]/
GPIO17/
EM_A[18]/
GPIO13/
EM_A[10]/
GPIO21
EM_A[11]/
GPIO20
DV
DV
V
DV
DDR2
DDR2
DDR2
SS
VLYNQ_TXD3 VLYNQ_RXD3 VLYNQ_RXD1
EM_A[6]/
GPIO25
EM_A[7]/
GPIO24
EM_A[8]/
GPIO23
EM_A[13]/
GPIO18
DV
V
DV
V
DV
V
SS
DD18
SS
DDR2
SS
DDR2
EM_A[9]/
GPIO22
MXO
PLLV
RSV24
RSV6
V
DV
V
CV
V
CV
DD18
SS
DD18
SS
DD
DD
SS
DD
DD
DD
MXI/CLKIN
MXV
RESET
MXV
V
DV
CV
CV
DD
CV
CV
SS
DD
SS
DD18
CLK_OUT0/
GPIO48
EM_A[3]/
GPIO28
EM_A[5]/
GPIO26
EM_A[4]/
GPIO27
DV
DD18
K
K
V
V
CV
CV
DDDSP
SS
SS
DDDSP
1
2
3
4
5
6
7
8
9
10
Figure 2-2. Pin Map [Quadrant A]
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11
12
13
14
15
16
17
18
19
W
V
U
T
W
V
U
T
DDR_A[6]
DDR_A[5]
DDR_A[0]
DDR_D[16]
DDR_D[18]
DDR_D[21]
DDR_D[27]
DDR_D[29]
RSV4
DDR_A[7]
DDR_A[9]
DDR_A[4]
DDR_A[3]
DDR_ZN
DDR_A[2]
DDR_A[1]
DDR_ZP
DDR_D[17]
DDR_DQS[2]
DDR_DQM[2]
DDR_D[19]
DDR_D[20]
DDR_VREF
DDR_D[22]
DDR_DQS[3]
DDR_DQM[3]
DAC_RBIAS
DDR_D[24]
DDR_D[25]
DDR_D[23]
DDR_D[28]
DDR_D[26]
DDR_D[30]
DDR_D[31]
DDR_
VSSDLL
V
V
_
DAC_IOUT_D
DAC_IOUT_C
SSA 1P1V
R
P
N
M
L
R
P
N
M
L
DV
V
DV
DV
DV
V
DV
DAC_V
_
DDA 1P8V
DDR2
SS
DDR2
SS
DDR2
REF
V
DV
V
DV
V
V
_
V _
SSA 1P8V
DAC_IOUT_B DAC_IOUT_A
SS
DDR2
SS
DDR2
SS
DDA 1P1V
CI4/CCD12/
UART_RTS2
CI5/CCD13/
UART_CTS2
CI6/CCD14/
UART_TXD2
CI7/CCD15/
UART_RXD2
DV
V
V
CI3/CCD11
CI0/CCD8
YI4/CCD4
DDR2
SS
DDR2
SS
V
CV
V
DV
CI1/CCD9
YI5/CCD5
CI2/CCD10
YI6/CCD6
HD
PCLK
VD
SS
DD
SS
DD18
V
CV
V
YI7/CCD7
SS
DD
DD18
SS
K
K
CV
CV
V
DV
V
SS
YI0/CCD0
16
YI1/CCD1
17
YI2/CCD2
18
YI3/CCD3
19
DDDSP
11
DD
SS
DD18
12
13
14
15
Figure 2-3. Pin Map [Quadrant B]
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11
12
13
14
15
16
17
18
19
USB_
USB_
V
DDA3P3
J
H
G
F
J
CV
CV
V
CV
V
DV
DD18
USB_ID
USB_VBUS
DDDSP
SS
DDDSP
SS
V
SSA3P3
H
G
F
CV
V
V
DV
V
USB_V
USB_V
USB_R1
USB_DM
USB_DP
M24XO
DDDSP
DDDSP
SS
DD18
SS
SS1P8
DD1P8
USB_
USB_
USB_
V
DDA1P2LD0
V
V
V
DV
DD18
SS
SS
SS
SS
V
V
SSREF
SSA1P2LD0
DV
DV
DV
DV
CV
M24V
M24V
SS
M24XI
DD33
DD33
DD33
DD18
DD
DD
CLK_OUT1/
TIM_IN/
GPIO49
GPIOV33_10/ GPIOV33_7/
RXD3 RXD0
GPIO1/
C_WE
YOUT4/R4/
AEAW4
E
E
D
C
B
A
GPIO5/G1
YOUT5/R5
YOUT6/R6
YOUT7/R7
GPIOV33_12/ GPIOV33_4/
YOUT0/G5/
AEAW0
YOUT1/G6/
AEAW1
YOUT2/G7/
AEAW2
YOUT3/R3/
AEAW3
D
GPIO2/G0
GPIO38/R1
VCLK
RXDV
TXD1
GPIOV33_8/
RXD1
GPIOV33_6/
TXD3
GPIO0/
LCD_OE
GPIO3/B0/
LCD_FIELD
PWM0/
GPIO45
C
COUT7/G4
HSYNC
VSYNC
VPBECLK
COUT6/G3
GPIOV33_3/
TXD0
GPIOV33_9/
RXD2
GPIOV33_0/
TXEN
GPIO4/R0/
C_FIELD
PWM1/R2/
GPIO46
COUT1/B4/
BTSEL1
COUT3/B6/
DSP_BT
B
COUT5/G2
GPIOV33_5/
TXD2
GPIOV33_2/
COL
GPIOV33_1/
TXCLK
PWM2/
B2/GPIO47
COUT0/B3/
BTSEL0
COUT2/B5/
EM_WIDTH
A
GPIO6/B1
14
COUT4/B7
18
RSV2
19
11
12
13
15
16
17
Figure 2-4. Pin Map [Quadrant C]
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1
2
3
4
5
6
7
8
9
10
EM_A[0]/
DA2/
HCNTL1/
GPIO53
EM_A[2]/
(CLE)/
HCNTL0
EM_A[1]/
(ALE)/
HHWIL
EM_BA[0]/
DA0/
HINT
GPIO50/
ATA_CS0
J
H
G
F
J
V
DV
V
CV
CV
CV
SS
DD18
SS
DDDSP
DDDSP
EM_BA[1]/
DA1/
GPIO52
EM_OE/(RE)/
(IORD)/DIOR/
HDS1
EM_D14/
DD14/
HD14
GPIO51/
ATA_CS1
DMACK/
UART_TXD1
H
DV
V
CV
V
SS
DD18
SS
DDDSP
DDDSP
EM_WE/(WE)/
(IOWR)/DIOW/
HDS2
EM_R/W/
INTRQ/
HR/W
EM_D11/
DD11/
HD11
EM_D10/
DD10/
HD10
DMARQ/
UART_RXD1
G
V
DV
V
DV
V
SS
SS
DD18
SS
DD18
EM_WAIT/
(RDY/BSY)/
IORDY/
EM_D13/
DD13/
HD13
EM_D8/
DD8/
HD8
EM_D6/
DD6/
HD6
EM_D2/
DD2/
HD2
F
DV
V
DV
V
DV
DD33
DD18
SS
DD18
SS
HRDY
EM_D15/
DD15/
HD15
EM_D9/
DD9/
HD9
EM_D3/
DD3/
HD3
EM_D4/
DD4/
HD4
EM_D0/
DD0/
HD0
GPIOV33_15/
MDIO
E
D
C
B
A
E
TMS
DV
V
SD_DATA1
SD_DATA2
SD_DATA3
SD_CMD
DD18
SS
EM_D12/
DD12/
HD12
EM_D5/
DD5/
HD5
EM_D1/
DD1/
HD1
UART_RXD0/
GPIO35
GPIOV33_13/
RXER
D
RSV5
EMU0
EMU1
RTCK
TRST
SD_DATA0
EM_D7/
DD7/
HD7
UART_TXD0/
GPIO36
GPIOV33_14/
CRS
C
EM_CS2/
HCS
GPIO7
SCL/
GPIO43
FSR/
GPIO32
FSX/
GPIO31
SPI_EN1/
HDDIR/
GPIO42
SPI_DI/
GPIO40
CLKX/
GPIO29
GPIOV33_16/
MDCLK
B
EM_CS3
SDA/GPIO44
TDO
DX/
GPIO33
SPI_DO/
GPIO41
SPI_CLK/
GPIO39
SPI_EN0/
GPIO37
CLKR/
GPIO30
GPIOV33_11/
RXCLK
A
RSV1
1
TDI
5
TCK
6
DR/
GPIO34
SD_CLK
2
3
4
7
8
9
10
Figure 2-5. Pin Map [Quadrant D]
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2.7 Terminal Functions
The terminal functions tables (Table 2-5 through Table 2-30) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and see the Device
Configurations section of this data manual.
Table 2-5. BOOT Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)(3)
BOOT
DESCRIPTION
NAME
NO.
These pins are multiplexed between ARM boot mode and
the VPBE. At reset, the boot mode inputs BTSEL0 and
BTSEL1 are sampled to determine the ARM boot
configuration. See below for the boot modes set by these
inputs. See the Bootmode section for more details.
After reset, these are video encoder outputs COUT0 and
COUT1, or RGB666/888 Blue output data bits 3 and 4
B3/B4.
COUT0/
B3/
BTSEL0
IPD
DVDD18
A16
I/O/Z
BTSEL1
BTSEL0
ARM Boot Mode
ARM ROM Boot (NAND) [default]
ARM EMIFA Boot (NOR)
ARM ROM Boot (HPI)
0
0
1
1
0
1
0
1
COUT1/
B4/
BTSEL1
IPD
DVDD18
B16
A17
B17
I/O/Z
I/O/Z
I/O/Z
ARM ROM Boot (UART0)
This pin is multiplexed between EMIFA and the VPBE. At
reset, the input state is sampled to set the EMIFA data
bus width (EM_WIDTH). For an 8-bit wide EMIFA data
bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data bus,
EM_WIDTH = 1.
COUT2/
B5/
EM_WIDTH
IPD
DVDD18
After reset, it is video encoder output COUT2 or
RGB666/888 Blue output data bit 5 B5.
This pin is multiplexed between DSP boot and the VPBE.
At reset, the input state is sampled to set the DSP boot
source DSP_BT. The DSP is booted by the ARM when
DSP_BT=0. The DSP boots from EMIFA when
DSP_BT=1.
COUT3/
B6/
DSP_BT
IPD
DVDD18
After reset, it is video encoder output COUT3 or
RGB666/888 Blue data bit 6 output B6.
YOUT0/
G5/
AEAW0
IPD
DVDD18
D15
D16
I/O/Z
I/O/Z
These pins are multiplexed between EMIFA and the
VPBE. At reset, the input states of AEAW[4:0] are
sampled to set the EMIFA address bus width. See the
Peripheral Selection at Device Reset section for details.
YOUT1/
G6/
AEAW1
IPD
DVDD18
YOUT2/
G7/
AEAW2
After reset, these are video encoder outputs YOUT[0:4]
or RGB666/888 Red and Green data bit outputs G5, G6,
G7, R3, and R4.
IPD
DVDD18
D17
D18
E15
I/O/Z
I/O/Z
I/O/Z
YOUT3/
R3/
AEAW3
IPD
DVDD18
YOUT4/
R4/
AEAW4
IPD
DVDD18
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-6. Oscillator/PLL Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2)
DESCRIPTION
NO.
OSCILLATOR, PLL
Crystal input MXI for MX oscillator (system oscillator, typically 27 MHz). If a crystal
input is not used, but instead a physical clock-in source is supplied, this is the
external oscillator clock input.
MXI/CLKIN
MXO
L1
M1
L5
I
O
DVDD18
Crystal output for MX oscillator. If a crystal input is not used, but instead a physical
clock-in source is supplied, MXO should be left as a No Connect.
DVDD18
1.8-V power supply for MX oscillator. If a crystal input is not used, but instead a
physical clock-in source is supplied, MXVDD should still be connected to the 1.8-V
power supply.
(3)
MXVDD
MXVSS
M24XI
S
Ground for MX oscillator. If a crystal input is not used, but instead a physical
clock-in source is supplied, MXVSS should still be connected to ground.
(3)
L2
GND
I
Crystal input for M24 oscillator (24 MHz for USB). If a crystal input is not used, but
instead a physical clock-in source is supplied, this is the external oscillator clock
input. When the USB peripheral is not used, M24XI should be left as a No Connect.
F18
DVDD18
Crystal output for M24 oscillator. If a crystal input is not used, but instead a physical
clock-in source is supplied, M24XO should be left as a No Connect. When the USB
peripheral is not used, M24XO should be left as a No Connect.
M24XO
M24VDD
F19
F16
O
S
DVDD18
1.8-V power supply for M24 oscillator. If a crystal input is not used, but instead a
physical clock-in source is supplied, M24VDD should still be connected to the 1.8-V
power supply. When the USB peripheral is not used, M24VDD should be connected
to the 1.8-V power supply.
(3)
Ground for M24 oscillator. If a crystal input is not used, but instead a physical
clock-in source is supplied, M24VSS should still be connected to ground. When the
USB peripheral is not used, M24VSS should be connected to ground.
(3)
(3)
M24VSS
F17
M2
GND
S
PLLVDD18
1.8-V power supply for PLLs (system).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
Table 2-7. Clock Generator Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)
DESCRIPTION
NAME
NO.
CLOCK GENERATOR
This pin is multiplexed between the PLL1 clock generator and GPIO.
For the PLL1 clock generator, it is clock output CLK_OUT0. This is configurable for
13.5 MHz or 27 MHz clock outputs.
CLK_OUT0/
GPIO48
K1
I/O/Z
I/O/Z
DVDD18
CLK_OUT1/
TIM_IN/
GPIO49
This pin is multiplexed between the USB clock generator, timer, and GPIO.
For the USB clock generator, it is clock output CLK_OUT1. This is configurable for
12 MHz or 24 MHz clock outputs.
E19
DVDD18
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
Table 2-8. RESET and JTAG Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
RESET
IPU
DVDD18
RESET
L4
I
This is the active low global reset input.
JTAG
IPU
DVDD18
TMS
E6
I
JTAG test-port mode select input
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal
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Digital Media System-on-Chip
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Table 2-8. RESET and JTAG Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
–
O/Z
TDO
TDI
B5
JTAG test-port data output
JTAG test-port data input
JTAG test-port clock input
DVDD18
IPU
DVDD18
A5
A6
B6
D7
C6
D6
I
IPU
DVDD18
TCK
I
–
O/Z
RTCK
TRST
EMU1
EMU0
JTAG test-port return clock output
DVDD18
IPD
DVDD18
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1
JTAG compatibility statement portion of this data manual .
I
IPU
I/O/Z
Emulation pin 1
Emulation pin 0
DVDD18
IPU
I/O/Z
DVDD18
Table 2-9. EMIFA Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
EMIFA BOOT CONFIGURATION
This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is
sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit wide EMIFA
data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data bus, EM_WIDTH = 1.
After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit 5
B5.
COUT2/
B5/
EM_WIDTH
IPD
I/O/Z
A17
B17
DVDD18
This pin is multiplexed between DSP boot and the VPBE. At reset, the input state is
sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM when
DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1.
After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6 output
B6.
COUT3/
B6/
DSP_BT
IPD
I/O/Z
DVDD18
YOUT0/
G5/
AEAW0
IPD
I/O/Z
D15
D16
D17
D18
E15
DVDD18
YOUT1/
G6/
AEAW1
IPD
I/O/Z
DVDD18
These pins are multiplexed between EMIFA and the VPBE. At reset, the input states
of AEAW[4:0] are sampled to set the EMIFA address bus width. See the Peripheral
Selection at Device Reset section for details.
After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and
Green data bit outputs G5, G6, G7, R3, and R4.
YOUT2/
G7/
AEAW2
IPD
I/O/Z
DVDD18
YOUT3/
R3/
AEAW3
IPD
I/O/Z
DVDD18
YOUT4/
R4/
AEAW4
IPD
I/O/Z
DVDD18
EMIFA FUNCTIONAL PINS: ASYNC / NOR
This pin is multiplexed between EMIFA and HPI.
EM_CS2/
HCS
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous
memories (i.e., NOR flash) or NAND flash. This is the chip select for the default boot
and ROM boot modes.
C2
B1
I/O/Z
I/O/Z
DVDD18
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous
memories (i.e., NOR flash) or NAND flash.
EM_CS3
DVDD18
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-9. EMIFA Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
EM_CS4/
GPIO9/
VLYNQ_SCRUN
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories
(i.e., NOR flash) or NAND flash.
T2
I/O/Z
I/O/Z
I/O/Z
DVDD18
DVDD18
DVDD18
EM_CS5/
GPIO8/
VLYNQ_CLOCK
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories
(i.e., NOR flash) or NAND flash.
T1
EM_R/W/
INTRQ/
HR/W
This pin is multiplexed between EMIFA, ATA/CF, and HPI.
For EMIFA, it is read/write output EM_R/W.
G3
EM_WAIT/
(RDY/BSY)/
IORDY/
IPU
DVDD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For EMIFA, it is wait state extension input EM_WAIT.
F1
H4
I/O/Z
I/O/Z
HRDY
EM_OE/
(RE)/
(IORD)/
DIOR/
HDS1
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For EMIFA, it is output enable output EM_OE.
DVDD18
EM_WE
(WE)
(IOWR)/
DIOW/
HDS2
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For NAND/SmartMedia/xD or EMIFA, it is write enable output EM_WE.
G2
J3
I/O/Z
I/O/Z
DVDD18
This pin is multiplexed between EMIFA, ATA/CF, and HPI.
For EMIFA, this is the Bank Address 0 output (EM_BA[0]).
When connected to an 8-bit asynchronous memory, this pin is the lowest order bit of
the byte address.
When connected to a 16-bit asynchronous memory, this pin has the same function
as EMIF address pin 22 (EM_A[22]).
EM_BA[0]/
DA0/
HINT
IPD
DVDD18
This pin is multiplexed between EMIFA, ATA/CF, and GPIO.
For EMIFA, this is the Bank Address 1 output EM_BA[1].
When connected to a 16 bit asynchronous memory this pin is the lowest order bit of
the 16-bit word address.
When connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the
address.
EM_BA[1]/
DA1/
GPIO52
H2
I/O/Z
DVDD18
EM_A[21]/
GPIO10/
VLYNQ_TXD0
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 21 output EM_A[21].
T3
R3
R4
P5
R2
R5
P3
P4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
EM_A[20]/
GPIO11/
VLYNQ_RXD0
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 20 output EM_A[20].
EM_A[19]/
GPIO12/
VLYNQ_TXD1
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 19 output EM_A[19].
EM_A[18]/
GPIO13/
VLYNQ_RXD1
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 18 output EM_A[18].
EM_A[17]/
GPIO14/
VLYNQ_TXD2
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 17 output EM_A[17].
EM_A[16]/
GPIO15/
VLYNQ_RXD2
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 16 output EM_A[16].
EM_A[15]/
GPIO16/
VLYNQ_TXD3
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 15 output EM_A[15].
EM_A[14]/
GPIO17/
VLYNQ_RXD3
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 14 output EM_A[14].
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Table 2-9. EMIFA Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
EM_A[13]/
GPIO18
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 13 output EM_A[13].
N4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
EM_A[12]/
GPIO19
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 12 output EM_A[12].
R1
P2
P1
M4
N3
N2
N1
K3
K4
K2
EM_A[11]/
GPIO20
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 11 output EM_A[11].
EM_A[10]/
GPIO21
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 10 output EM_A[10].
EM_A[9]/
GPIO22
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 9 output EM_A[9].
EM_A[8]/
GPIO23
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 8 output EM_A[8].
EM_A[7]/
GPIO24
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 7 output EM_A[7].
EM_A[6]/
GPIO25
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 6 output EM_A[6].
EM_A[5]/
GPIO26
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 5 output EM_A[5].
EM_A[4]/
GPIO27
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 4 output EM_A[4].
EM_A[3]/
GPIO28
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is address bit 3 output EM_A[3].
EM_A[2]/
(CLE)/
HCNTL0
This pin is multiplexed between EMIFA and HPI.
For EMIFA, this pin is the EM_A[2] address line.
J1
J2
I/O/Z
I/O/Z
DVDD18
EM_A[1]/
(ALE)/
HHWIL
DVDD18
This pin is multiplexed between EMIFA (NAND/SmartMedia.xD) and HPI.
This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.
EM_A[0]/
DA2/
HCNTL1/
GPIO53
For EMIFA, this is Address output EM_A[0], which is the least significant bit on a
32-bit word address.
When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the
address.
J4
I/O/Z
DVDD18
For an 8-bit asynchronous memory, this pin is the 3rd bit of the address.
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Table 2-9. EMIFA Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
EM_D0/
DD0/
HD0
E5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
EM_D1/
DD1/
HD1
D3
F5
E3
E4
D2
F4
C1
F3
E2
G5
G4
D1
F2
H5
E1
EM_D2/
DD2/
HD2
EM_D3/
DD3/
HD3
EM_D4/
DD4/
HD4
EM_D5/
DD5/
HD5
EM_D6/
DD6/
HD6
EM_D7/
DD7/
HD7
These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases
they are used as a 16 bit bi-directional data bus.
For EMIFA (NAND), these are EM_D[15:0].
EM_D8/
DD8/
HD8
EM_D9/
DD9/
HD9
EM_D10/
DD10/
HD10
EM_D11/
DD11/
HD11
EM_D12/
DD12/
HD12
EM_D13/
DD13/
HD13
EM_D14/
DD14/
HD14
EM_D15/
DD15/
HD15
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Table 2-9. EMIFA Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
EMIFA FUNCTIONAL PINS: NAND / SMARTMEDIA / xD
EM_A[1]/
(ALE)/
HHWIL
This pin is multiplexed between EMIFA and HPI.
For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE).
J2
J1
I/O/Z
I/O/Z
DVDD18
EM_A[2]/
(CLE)/
HCNTL0
This pin is multiplexed between EMIFA and HPI.
For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE).
DVDD18
EM_WAIT/
(RDY/BSY)/
IORDY/
IPU
DVDD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For NAND/SmartMedia/xD, it is ready/busy input (RDY/BSY).
F1
H4
I/O/Z
I/O/Z
HRDY
EM_OE/
(RE)/
(IORD)/
DIOR/
HDS1
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For NAND/SmartMedia/xD, it is read enable output (RE).
DVDD18
EM_WE
(WE)
(IOWR)/
DIOW/
HDS2
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For NAND/SmartMedia/xD, it is write enable output (WE).
G2
C2
I/O/Z
I/O/Z
DVDD18
This pin is multiplexed between EMIFA and HPI.
EM_CS2/
HCS
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous
memories (i.e. NOR flash) or NAND flash. This is the chip select for the default boot
and ROM boot modes.
DVDD18
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous
memories (i.e. NOR flash) or NAND flash.
EM_CS3
B1
T2
I/O/Z
I/O/Z
DVDD18
DVDD18
EM_CS4/
GPIO9/
VLYNQ_SCRUN
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip
Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or
NAND flash.
EM_CS5/
GPIO8/
VLYNQ_CLOCK
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip
Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or
NAND flash.
T1
I/O/Z
DVDD18
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Table 2-9. EMIFA Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
EM_D0/
DD0/
HD0
E5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
EM_D1/
DD1/
HD1
D3
F5
E3
E4
D2
F4
C1
F3
E2
G5
G4
D1
F2
H5
E1
EM_D2/
DD2/
HD2
EM_D3/
DD3/
HD3
EM_D4/
DD4/
HD4
EM_D5/
DD5/
HD5
EM_D6/
DD6/
HD6
EM_D7/
DD7/
HD7
These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases
they are used as a 16 bit bi-directional data bus.
For EMIFA (NAND), these are EM_D[15:0].
EM_D8/
DD8/
HD8
EM_D9/
DD9/
HD9
EM_D10/
DD10/
HD10
EM_D11/
DD11/
HD11
EM_D12/
DD12/
HD12
EM_D13/
DD13/
HD13
EM_D14/
DD14/
HD14
EM_D15/
DD15/
HD15
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Table 2-10. DDR2 Memory Controller Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
DDR2 Memory Controller
DDR2 Clock
DDR_CLK0
DDR_CLK0
DDR_CKE
W7
W8
V8
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DDR2 Differential clock
DDR2 Clock Enable
DDR_CS
T9
DDR2 Active low chip select
DDR2 Active low Write enable
DDR_WE
T8
DDR_DQM[3]
DDR_DQM[2]
DDR_DQM[1]
DDR_DQM[0]
DDR_RAS
T16
T14
T6
DDR2 Data mask outputs
DQM3: For upper byte data bus DDR_D[31:24]
DQM2: For DDR_D[23:16]
DQM1: For DDR_D[15:8]
DQM0: For lower byte DDR_D[7:0]
T4
U7
T7
DDR2 Row Access Signal output
DDR2 Column Access Signal output
DDR_CAS
DDR_DQS[0]
DDR_DQS[1]
DDR_DQS[2]
U4
U6
U14
Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to
the DDR2 memory when writing and inputs when reading. They are used to
synchronize the data transfers.
DQS3 : For upper byte DDR_D[31:24]
DQS2: For DDR_D[23:16]
DQS1: For DDR_D[15:8]
DQS0: For bottom byte DDR_D[7:0]
DDR_DQS[3]
U16
I/O/Z
DVDDR2
DDR_BS[0]
DDR_BS[1]
DDR_BS[2]
DDR_A[12]
DDR_A[11]
DDR_A[10]
DDR_A[9]
DDR_A[8]
DDR_A[7]
DDR_A[6]
DDR_A[5]
DDR_A[4]
DDR_A[3]
DDR_A[2]
DDR_A[1]
DDR_A[0]
U8
V9
I/O/Z
DVDDR2
Bank select outputs (BS[2:0]). Two are required to support 1Gb DDR2 memories.
U9
W9
W10
U10
U11
V10
V11
W11
W12
V12
U12
V13
U13
W13
I/O/Z
DVDDR2
DDR2 address bus
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
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Table 2-10. DDR2 Memory Controller Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
U19
V19
W18
V18
W17
U18
U17
V17
T17
V16
W16
U15
V15
W15
V14
W14
V7
DDR_D[31]
DDR_D[30]
DDR_D[29]
DDR_D[28]
DDR_D[27]
DDR_D[26]
DDR_D[25]
DDR_D[24]
DDR_D[23]
DDR_D[22]
DDR_D[21]
DDR_D[20]
DDR_D[19]
DDR_D[18]
DDR_D[17]
DDR_D[16]
DDR_D[15]
DDR_D[14]
DDR_D[13]
DDR_D[12]
DDR_D[11]
DDR_D[10]
DDR_D[9]
I/O/Z
DVDDR2
DDR2 data bus can be configured as 32 bits wide or 16 bits wide.
W6
V6
W5
V5
U5
W4
V4
DDR_D[8]
DDR_D[7]
W3
V3
DDR_D[6]
DDR_D[5]
U3
DDR_D[4]
W2
V2
DDR_D[3]
DDR_D[2]
V1
DDR_D[1]
U2
DDR_D[0]
U1
(3)
(3)
(3)
DDR_VREF
DDR_VSSDLL
DDR_VDDDLL
T15
T11
T10
I
Reference voltage input for the SSTL_18 IO buffers.
Ground for the DDR2 Digital Locked Loop.
GND
S
Power (1.8 Volts) for the DDR2 Digital Locked Loop.
Impedance control for DDR2 outputs. This must be connected via a 200 Ω resistor
(3)
(3)
DDR_ZN
DDR_ZP
T12
T13
O/Z
O/Z
to DVDDR2
Impedance control for DDR2 outputs. This must be connected via a 200 Ω resistor
to VSS
.
.
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Table 2-11. I2C Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)
DESCRIPTION
NAME
NO.
I2C
SCL/
GPIO43
This pin is multiplexed between I2C and GPIO.
For I2C, it is clock output SCL.
C4
B4
I/O/Z
I/O/Z
DVDD18
DVDD18
SDA/
GPIO44
This pin is multiplexed between I2C and GPIO.
For I2C, it is bi-directional data signal SDA.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
Table 2-12. Audio Serial Port (ASP) Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)
DESCRIPTION
NAME
NO.
Audio Serial Port (ASP)
CLKX/
GPIO29
This pin is multiplexed between ASP and GPIO.
For ASP, it is Transmit clock IO CLKX.
B8
A8
C8
C7
B7
A7
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
CLKR/
GPIO30
This pin is multiplexed between ASP and GPIO.
For ASP, it is Receive clock IO CLKR.
FSX/
GPIO31
This pin is multiplexed between ASP and GPIO.
For ASP, it is Transmit frame synchronization IO FSX.
FSR/
GPIO32
This pin is multiplexed between ASP and GPIO.
For ASP, it is Receive frame synchronization IO FSR.
DX/
GPIO33
This pin is multiplexed between ASP and GPIO.
For ASP, it is Data Transmit output DX.
DR/
GPIO34
This pin is multiplexed between ASP and GPIO.
For ASP, it is Data Receive input DR.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
Table 2-13. SPI Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)
DESCRIPTION
NAME
NO.
Serial Peripheral Interface (SPI)
SPI_EN0/
GPIO37
This pin is multiplexed between SPI and GPIO.
When used by SPI, it is SPI slave device 0 enable output SPI_EN0.
A4
B2
I/O/Z
I/O/Z
DVDD18
DVDD18
SPI_EN1/
HDDIR/
GPIO42
This pin is multiplexed between SPI, ATA, and GPIO.
When used by SPI, it is SPI slave device 1 enable output SPI_EN1.
SPI_CLK/
GPIO39
This pin is multiplexed between SPI and GPIO.
For SPI, it is clock output SPI_CLK.
A3
B3
A2
I/O/Z
I/O/Z
I/O/Z
DVDD18
DVDD18
DVDD18
SPI_DI/
GPIO40
This pin is multiplexed between SPI and GPIO.
For SPI, it is data input SPI_DI.
SPI_DO/
GPIO41
This pin is multiplexed between SPI and GPIO.
For SPI it is data output SPI_DO.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
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Table 2-14. EMAC and MDIO Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2)
DESCRIPTION
NO.
EMAC
GPIOV33_0/
TXEN
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Transmit Enable output TXEN.
B13
A13
A12
C12
A11
D12
B12
A10
D11
D10
C10
E11
B11
C11
E12
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
GPIOV33_1/
TXCLK
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Transmit Clock input TXCLK.
GPIOV33_2/
COL
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Collision Detect input COL.
GPIOV33_6/
TXD3
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Transmit Data 3 output TXD3.
GPIOV33_5/
TXD2
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Transmit Data 2 output TXD2.
GPIOV33_4/
TXD1
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Transmit Data 1 output TXD1.
GPIOV33_3/
TXD0
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Transmit Data 0 output TXD0.
GPIOV33_11/
RXCLK
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Receive Clock input RXCLK.
GPIOV33_12/
RXDV
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Receive Data Valid input RXDV.
GPIOV33_13/
RXER
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Receive Error input RXER.
GPIOV33_14/
CRS
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Carrier Sense input CRS.
GPIOV33_10/
RXD3
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Receive Data 3 input RXD3.
GPIOV33_9/
RXD2
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Receive Data 2 input RXD2.
GPIOV33_8/
RXD1
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Receive data 1 input RXD1.
GPIOV33_7/
RXD0
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Receive Data 0 input RXD0.
MDIO
GPIOV33_16/
MDCLK
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Management Data Clock output MDCLK.
B10
E10
I/O/Z
I/O/Z
DVDD33
DVDD33
GPIOV33_15/
MDIO
This pin is multiplexed between GPIO and Ethernet MAC.
In Ethernet MAC mode, it is Management Data IO MDIO.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
Table 2-15. GPIOV33 Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)
DESCRIPTION
NAME
NO.
GPIOV33
GPIOV33_16/
MDCLK
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_16.
B10
E10
C10
D10
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD33
DVDD33
DVDD33
DVDD33
GPIOV33_15/
MDIO
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_15.
GPIOV33_14/
CRS
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_14.
GPIOV33_13/
RXER
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_13.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
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Table 2-15. GPIOV33 Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
OTHER(2)
DESCRIPTION
NO.
GPIOV33_12/
RXDV
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_12.
D11
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
GPIOV33_11/
RXCLK
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_11.
A10
E11
B11
C11
E12
C12
A11
D12
B12
A12
A13
B13
GPIOV33_10/
RXD3
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_10.
GPIOV33_9/
RXD2
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_9.
GPIOV33_8/
RXD1
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_8.
GPIOV33_7/
RXD0
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_7.
GPIOV33_6/
TXD3
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_6.
GPIOV33_5/
TXD2
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_5.
GPIOV33_4/
TXD1
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_4.
GPIOV33_3/
TXD0
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_3.
GPIOV33_2/
COL
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_2.
GPIOV33_1/
TXCLK
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, it is 3.3V GPIO GPIOV33_1.
GPIOV33_0/
TXEN
This pin is multiplexed between GPIO and Ethernet MAC.
In GPIO mode, this pin is 3.3V GPIO pin GPIOV33_0.
Table 2-16. Standalone GPIOV18 Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2)
DESCRIPTION
NO.
Standalone GPIOV18
This pin is standalone and functions as GPIO7.
GPIO7
C3
I/O/Z
DVDD18
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
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Table 2-17. USB Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
USB 2.0
Crystal input for M24 oscillator (24 MHz for USB).
If a crystal input is not used, but instead a physical clock-in source is supplied, this
is the external oscillator clock input.
M24XI
F18
I
DVDD18
When the USB peripheral is not used, M24XI should be left as a No Connect.
Crystal output for M24 oscillator.
If a crystal input is not used, but instead a physical clock-in source is supplied,
M24XO should be left as a No Connect.
M24XO
F19
F16
O
DVDD18
When the USB peripheral is not used, M24XO should be left as a No Connect.
1.8-V power supply for M24 oscillator.
If a crystal input is not used, but instead a physical clock-in source is supplied,
M24VDD should still be connected to the 1.8-V power supply.
(3)
M24VDD
S
When the USB peripheral is not used, M24VDD should be connected to the 1.8-V
power supply.
Ground for M24 oscillator.
If a crystal input is not used, but instead a physical clock-in source is supplied,
M24VSS should still be connected to ground.
(3)
(3)
M24VSS
F17
J17
GND
A I/O
When the USB peripheral is not used, M24VSS should be connected to ground.
5-V input that signifies that VBUS is connected.
USB_VBUS
When the USB peripheral is not used, the USB_VBUS signal should be either
pulled down or pulled up via a 10-kΩ resistor.
USB operating mode identification pin. For Host mode operation, pull down this pin
to ground (VSS) via an external 1.5-kΩ resistor. For Device mode operation, pull up
this pin to DVDD33 rail via an external 1.5-kΩ resistor.
USB_ID
J16
A I/O
When the USB peripheral is not used, the USB_ID signal should be either pulled
down or pulled up via a 10-kΩ resistor.
USB_DP
USB_DM
G19
H19
A I/O
A I/O
USB bi-directional Data Differential signal pair [positive/negative].
When the USB peripheral is not used, the USB_DP signal should be pulled high
and the USB_DM signal should be pulled down via a 10-kΩ resistor.
Reference current output. This must be connected via a 10-kΩ ±1% resistor to
USB_VSSREF
.
(3)
(3)
USB_R1
H18
G16
A I/O
GND
When the USB peripheral is not used, the USB_R1 signal should be connected via
a 10-kΩ resistor to USB_VSSREF
.
Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to
USB_R1.
USB_VSSREF
When the USB peripheral is not used, the USB_VSSREF signal should be connected
to VSS
.
Analog 3.3 V power supply for USB phy.
(3)
(3)
(3)
USB_VDDA3P3
USB_VSSA3P3
USB_VDD1P8
J19
J18
H17
S
GND
S
When the USB peripheral is not used, the USB_VDDA3P3 signal should be
connected to DVDD33
.
Analog ground for USB phy. When the USB peripheral is not used, the
USB_VSSA3P3 signal should be connected to VSS
1.8-V I/O power supply for USB phy.
.
When the USB peripheral is not used, the USB_VDD1P8 signal should be connected
to DVDD18
.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
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Table 2-17. USB Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
I/O Ground for USB phy.
When the USB peripheral is not used, the USB_VSS1P8 signal should be connected
(3)
USB_VSS1P8
H16
GND
to VSS
Core Power supply LDO output for USB phy. This must be connected via a 1-µF
capacitor to VSS
When the USB peripheral is not used, the USB_VDDA1P2LDO signal should still be
connected via a 1-µF capacitor to VSS
Core Ground for USB phy. This is the ground for the LDO and must be connected to
VSS
When the USB peripheral is not used, the USB_VSSA1P2LDO signal should still be
connected to VSS
.
.
(3)
USB_VDDA1P2LDO G18
S
.
.
(3)
USB_VSSA1P2LDO
G17
GND
.
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Table 2-18. VLYNQ Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2)
DESCRIPTION
NO.
VLYNQ
EM_CS5/
GPIO8/
VLYNQ_CLOCK
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For VLYNQ, it is the clock (VLYNQ_CLOCK).
T1
T2
P3
R2
R4
T3
P4
R5
P5
R3
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
EM_CS4/
GPIO9/
VLYNQ_SCRUN
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For VLYNQ, it is the Serial Clock run request (VLYNQ_SCRUN).
EM_A[15]/
GPIO16/
VLYNQ_TXD3
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3.
EM_A[17]/
GPIO14/
VLYNQ_TXD2
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2.
EM_A[19]/
GPIO12/
VLYNQ_TXD1
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1.
EM_A[21]/
GPIO10/
VLYNQ_TXD0
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For VLYNQ, it is bit 0 of the transmit bus (VLYNQ_TXD0).
EM_A[14]/
GPIO17/
VLYNQ_RXD3
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3.
EM_A[16]/
GPIO15/
VLYNQ_RXD2
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2.
EM_A[18]/
GPIO13/
VLYNQ_RXD1
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1.
EM_A[20]/
GPIO11/
VLYNQ_RXD0
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
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Table 2-19. VPFE Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
VIDEO/IMAGE IN (VPFE)
–
Pixel clock input used to load image data into the CCD Controller (CCDC) on pins
CI[7:0] and YI[7:0].
PCLK
VD
M19
L19
I
DVDD18
–
Vertical synchronization signal that can be either an input (slave mode) or an output
(master mode), which signals the start of a new frame to the CCDC.
I/O/Z
I/O/Z
DVDD18
–
Horizontal synchronization signal that can be either an input (slave mode) or an
output (master mode), which signals the start of a new line to the CCDC.
HD
M18
DVDD18
This pin is multiplexed between the CCDC and UART2.
When used by the CCDC as input CI7, it supports several modes.
In 16-bit CCD Analog-Front-End (AFE) mode, it is input CCD15.
In 16-bit YCbCr mode, it is time multiplexed between CB7 and CR7 inputs.
In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and CR7 of the upper
8-bit channel.
CI7/
CCD15/
UART_RXD2
IPD
DVDD18
N19
N18
N17
N16
I/O/Z
I/O/Z
I/O/Z
I/O/Z
This pin is multiplexed between the CCDC and UART2.
When used by the CCDC as input CI6, it supports several modes. In 16-bit CCD
AFE mode, it is input CCD14.
In 16-bit YCbCr mode, it is time multiplexed between CB6 and CR6 inputs.
In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and CR6 of the upper
8-bit channel.
CI6/
CCD14/
UART_TXD2
IPD
DVDD18
This pin is multiplexed between the CCDC and UART2. When used by the CCDC as
input CI5, it supports several modes.
In 16-bit CCD AFE mode, it is input CCD13.
In 16-bit YCbCr mode, it is time multiplexed between CB5 and CR5 inputs.
In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and CR5 of the upper
8-bit channel.
CI5/
CCD13/
UART_CTS2
IPD
DVDD18
This pin is multiplexed between the CCDC and UART2. When used by the CCDC as
input CI4, it supports several modes.
In 16-bit CCD AFE mode, it is input CCD12.
In 16-bit YCbCr mode, it is time multiplexed between CB4 and CR4 inputs.
In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and CR4 of the upper
8-bit channel.
CI4/
CCD12/
UART_RTS2
IPD
DVDD18
This pin is CCDC input CI3 and it supports several modes. In 16-bit CCD AFE
mode, it is input CCD11.
In 16-bit YCbCr mode, it is time multiplexed between CB3 and CR3 inputs.
In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and CR3 of the upper
8-bit channel.
CI3/
CCD11
IPD
DVDD18
N15
M17
M16
M15
L18
I
I
I
I
I
This pin is CCDC input CI2 and it supports several modes. In 16-bit CCD AFE
mode, it is input CCD10.
In 16-bit YCbCr mode, it is time multiplexed between CB2 and CR2 inputs.
In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and CR2 of the upper
8-bit channel.
CI2/
CCD10
IPD
DVDD18
This pin is CCDC input CI1 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD9.
In 16-bit YCbCr mode, it is time multiplexed between CB1 and CR1 inputs.
In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and CR1 of the upper
8-bit channel.
CI1/
CCD9
IPD
DVDD18
This pin is CCDC input CI0 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD8.
In 16-bit YCbCr mode, it is time multiplexed between CB0 and CR0 inputs.
In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and CR0 of the upper
8-bit channel.
CI0/
CCD8
IPD
DVDD18
This pin is CCDC input YI7 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD7.
In 16-bit YCbCr mode, it is input Y7.
In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and CR7 of the lower
8-bit channel.
YI7/
CCD7
IPD
DVDD18
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-19. VPFE Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
This pin is CCDC input YI6 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD6.
In 16-bit YCbCr mode, it is input Y6.
In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and CR6 of the lower
8-bit channel.
YI6/
CCD6
IPD
DVDD18
L17
I
This pin is CCDC input YI5 and it supports several modes. In 16-bit CCD AFE
mode, it is input CCD5.
In 16-bit YCbCr mode, it is input Y5.
In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and CR5 of the lower
8-bit channel.
YI5/
CCD5
IPD
DVDD18
L16
L15
K19
K18
K17
K16
I
This pin is CCDC input YI4 and it supports several modes.
In 16-bit CCD Analog-Front-End (AFE) mode, it is input CCD4.
In 16-bit YCbCr mode, it is input Y4.
In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and CR4 of the lower
8-bit channel.
YI4/
CCD4
IPD
DVDD18
I
This pin is CCDC input YI3 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD3.
In 16-bit YCbCr mode, it is input Y3.
In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and CR3 of the lower
8-bit channel.
YI3/
CCD3
IPD
DVDD18
I
This pin is CCDC input YI2 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD2.
In 16-bit YCbCr mode, it is input Y2.
In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and CR2 of the lower
8-bit channel.
YI2/
CCD2
IPD
DVDD18
I
This pin is CCDC input YI1 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD1.
In 16-bit YCbCr mode, it is input Y1.
In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and CR1 of the lower
8-bit channel.
YI1/
CCD1
IPD
DVDD18
I
This pin is CCDC input YI0 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD0.
In 16-bit YCbCr mode, it is input Y0.
In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and CR0 of the lower
8-bit channel.
YI0/
CCD0
IPD
DVDD18
I
GPIO1/
C_WE
This pin is multiplexed between GPIO and the VPFE.
In VPFE mode, it is the CCD Controller write enable input C_WE.
E13
B14
I/O/Z
I/O/Z
DVDD18
DVDD18
GPIO4/
R0/
C_FIELD
This pin is multiplexed between GPIO, the VPFE, and the VPBE.
In VPFE mode, it is CCDC field identification bidirectional signal C_FIELD.
Table 2-20. VPBE Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
VIDEO OUT (VPBE)
DESCRIPTION
NAME
NO.
IPD
DVDD18
HSYNC
C17
I/O/Z
VPBE Horizontal Sync signal that can be either an input or an output.
IPD
DVDD18
VSYNC
VCLK
C18
D19
C19
I/O/Z
I/O/Z
I/O/Z
VPBE Vertical Sync signal that can be either an input or an output.
VPBE Clock Output
DVDD18
IPD
DVDD18
VPBECLK
VPBE Clock Input
COUT0/
B3/
BTSEL0
This pin is multiplexed between ARM boot mode and the VPBE.
After reset, this pin is either video encoder outputs COUT0, or
RGB666/888 Blue output data bits 3, B3.
IPD
DVDD18
A16
I/O/Z
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-20. VPBE Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
COUT1/
B4/
BTSEL1
This pin is multiplexed between ARM boot mode and the VPBE.
After reset, this pin is either video encoder outputs COUT1, or
RGB666/888 Blue output data bits 4, B4.
IPD
I/O/Z
B16
DVDD18
COUT2/
B5/
EM_WIDTH
This pin is multiplexed between EMIFA and the VPBE.
After reset, it is video encoder output COUT2 or RGB666/888 Blue output
data bit 5 B5.
IPD
I/O/Z
A17
B17
DVDD18
COUT3/
B6/
DSP_BT
This pin is multiplexed between DSP boot and the VPBE.
After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit
6 output B6.
IPD
I/O/Z
DVDD18
COUT4/
B7
A18
B18
B19
C16
O
O
O
O
DVDD18
DVDD18
DVDD18
DVDD18
Video encoder output COUT4 or RGB666/888 Blue data bit 7 output B7.
Video encoder output COUT5 or RGB666/888 Green data bit 2 output G2.
Video encoder output COUT6 or RGB666/888 Green data bit 3 output G3.
Video encoder output COUT7 or RGB666/888 Green data bit 4 output G4.
COUT5/
G2
COUT6/
G3
COUT7/
G4
YOUT0/
G5/
AEAW0
IPD
DVDD18
D15
D16
D17
D18
E15
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
YOUT1/
G6/
AEAW1
IPD
DVDD18
YOUT2/
G7/
AEAW2
These pins are multiplexed between EMIFA and the VPBE.
After reset, these are video encoder outputs YOUT[0:4] or RGB666/888
Red and Green data bit outputs G5, G6, G7, R3, and R4.
IPD
DVDD18
YOUT3/
R3/
AEAW3
IPD
DVDD18
YOUT4/
R4/
AEAW4
IPD
DVDD18
YOUT5/
R5
E16
E17
E18
C13
D13
O
O
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
Video encoder output YOUT5 or RGB666/888 Red data bit 5 output R5.
Video encoder output YOUT6 or RGB666/888 Red data bit 6 output R6.
Video encoder output YOUT7 or RGB666/888 Red data bit 7 output R7.
YOUT6/
R6
YOUT7/
R7
O
GPIO0/
LCD_OE
This pin is multiplexed between GPIO and the VPBE.
In VPBE mode, it is the LCD output enable LCD_OE.
I/O/Z
I/O/Z
GPIO2/
G0
This pin is multiplexed between GPIO and the VPBE.
In VPBE mode, it is RGB888 Green data bit 0 output G0.
GPIO3/
B0/
LCD_FIELD
This pin is multiplexed between GPIO, and the VPBE.
In VPBE mode, it is RGB888 Blue data bit 0 output B0 or LCD interlaced
bidirectional LCD_FIELD.
C14
B14
I/O/Z
I/O/Z
DVDD18
GPIO4/
R0/
C_FIELD
This pin is multiplexed between GPIO, the VPFE, and the VPBE.
In VPBE mode, it is RGB888 Red data bit 0 output R0.
DVDD18
GPIO5/
G1
This pin is multiplexed between GPIO and the VPBE.
In VPBE mode, it is RGB888 Green data bit 1 output G1.
E14
A14
D14
I/O/Z
I/O/Z
I/O/Z
DVDD18
DVDD18
DVDD18
GPIO6/
B1
This pin is multiplexed between GPIO and the VPBE.
In VPBE mode, it is RGB888 Blue data bit 1 output B1.
GPIO38/
R1
This pin is multiplexed between VPBE and GPIO.
In VPBE mode, it is RGB888 Red output data bit 1.
PWM1/
R2/
GPIO46
This pin is multiplexed between PWM1, VPBE, and GPIO.
In VPBE mode, it is RGB888 Red output bit 2 (R2).
B15
I/O/Z
DVDD18
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Table 2-20. VPBE Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
PWM2/
B2/
GPIO47
This pin is multiplexed between PWM2, VPBE, and GPIO.
In VPBE mode, it is RGB888 Blue output bit 2 (B2).
A15
I/O/Z
DVDD18
Table 2-21. DAC [Part of VPBE] Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
DAC[A:D]
Reference voltage input (0.5 V). When the DAC is not used, the DAC_VREF signal
should be connected to VSS
(3)
DAC_VREF
DAC_IOUT_A
DAC_IOUT_B
DAC_IOUT_C
DAC_IOUT_D
VDDA_1P8V
R17
P19
P18
R19
T19
R18
P17
P16
T18
A I
.
Output of DAC A. When the DAC is not used, the DAC_IOUT_A signal should be
left as a No Connect.
A O
A O
A O
A O
Output of DAC B. When the DAC is not used, the DAC_IOUT_B signal should be
left as a No Connect.
Output of DAC C. When the DAC is not used, the DAC_IOUT_C signal should be
left as a No Connect.
Output of DAC D. When the DAC is not used, the DAC_IOUT_D signal should be
left as a No Connect.
1.8-V analog I/O power. When the DAC is not used, the VDDA_1P8V signal should be
(3)
S
connected to VSS
Analog I/O ground. When the DAC is not used, the VSSA_1P8V signal should be
connected to VSS
1.20-V analog core supply voltage. When the DAC is not used, the VDDA_1P1V signal
should be connected to VSS
Analog core ground. When the DAC is not used, the VSSA_1P1V signal should be
connected to VSS
.
(3)
VSSA_1P8V
GND
.
(3)
VDDA_1P1V
S
.
(3)
VSSA_1P1V
GND
.
External resistor connection for current bias configuration. This pin must be
connected via a 4-kΩ resistor to VSSA_1P8V. When the DAC is not used, the
(3)
DAC_RBIAS
R16
A I
DAC_RBIAS signal should be connected to VSS
.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
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Table 2-22. UART0, UART1, UART2 Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
UART2
CI7/
CCD15/
UART_RXD2
IPD
I/O/Z
This pin is multiplexed between the CCDC and UART2.
When used by UART2 it is the receive data input UART_RXD2.
N19
N18
N17
N16
DVDD18
CI6/
CCD14/
UART_TXD2
IPD
I/O/Z
This pin is multiplexed between the CCDC and UART2.
In UART2 mode, it is the transmit data output UART_TXD2.
DVDD18
CI5/
CCD13/
UART_CTS2
IPD
I/O/Z
This pin is multiplexed between the CCDC and UART2.
In UART2 mode, it is the clear to send input UART_CTS2.
DVDD18
CI4/
CCD12/
UART_RTS2
IPD
I/O/Z
This pin is multiplexed between the CCDC and UART2.
In UART2 mode, it is the ready to send output UART_RTS2.
DVDD18
UART1
DMACK/
UART_TXD1
This pin is multiplexed between ATA/CF and UART1.
For UART1, it is transmit data output UART_TXD1.
H3
G1
I/O/Z
I/O/Z
DVDD18
DMARQ/
UART_RXD1
IPD
DVDD18
This pin is multiplexed between ATA/CF and UART1.
For UART1, it is receive data input UART_RXD1.
UART0
UART_RXD0/
GPIO35
This pin is multiplexed between UART0 and GPIO.
For UART0, it is receive data input UART_RXD0.
D5
C5
I/O/Z
I/O/Z
DVDD18
DVDD18
UART_TXD0/
GPIO36
This pin is multiplexed between UART0 and GPIO. .
For UART0, it is transmit data output UART_TXD0.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-23. PWM0, PWM1, PWM2 Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2)
DESCRIPTION
NO.
PWM2
PWM2/
B2/
GPIO47
This pin is multiplexed between PWM2, VPBE, and GPIO.
For PWM2, it is output PWM2.
A15
I/O/Z
DVDD18
PWM1
PWM1/
R2/
GPIO46
This pin is multiplexed between PWM1, VPBE, and GPIO.
For PWM1, it is output PWM1.
B15
C15
I/O/Z
I/O/Z
DVDD18
PWM0
PWM0/
GPIO45
This pin is multiplexed between PWM0 and GPIO.
For PWM0, it is output PWM0.
DVDD18
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
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Table 2-24. ATA/CF Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
ATA/CF
SPI_EN1/
HDDIR/
GPIO42
This pin is multiplexed between SPI, ATA, and GPIO.
For ATA, it is buffer direction control output HDDIR.
B2
I/O/Z
DVDD18
GPIO50/
ATA_CS0
This pin is multiplexed between GPIO and ATA/CF.
In ATA mode, it is ATA/CF chip select output ATA_CS0.
J5
O
O
DVDD18
DVDD18
GPIO51/
ATA_CS1
This pin is multiplexed between GPIO and ATA/CF.
In ATA mode, it is ATA/CF chip select output ATA_CS1.
H1
EM_R/W/
INTRQ/
H/W
This pin is multiplexed between EMIFA, ATA/CF, and HPI.
For ATA/CF, it is interrupt request input INTRQ.
G3
F1
I
I
DVDD18
EM_WAIT/
(RDY/BSY)/
IORDY/
IPU
DVDD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For ATA/CF, it is IO Ready input IORDY.
HRDY
EM_OE/
(RE)/
(IORD)/
DIOR/
HDS1
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For CF, it is read strobe output (IORD).
For ATA, it is read strobe output DIOR.
H4
G2
O
O
DVDD18
EM_WE
(WE)
(IOWR)/
DIOW/
HDS2
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For CF, it is write strobe output (IOWR).
For ATA, it is write strobe output DIOW.
DVDD18
DMACK/
UART_TXD1
This pin is multiplexed between ATA/CF and UART1.
For ATA/CF, it is DMA acknowledge output DMACK.
H3
G1
O
O
DVDD18
DMARQ/
UART_RXD1
IPD
DVDD18
This pin is multiplexed between ATA/CF and UART1.
For ATA/CF, it is DMA request DMARQ input.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-24. ATA/CF Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
EM_D15/
DD15/
E1
HD15
EM_D14/
DD14/
HD14
H5
F2
D1
G4
G5
E2
F3
C1
F4
D2
E4
E3
F5
D3
E5
EM_D13/
DD13/
HD13
EM_D12/
DD12/
HD12
EM_D11/
DD11/
HD11
EM_D10/
DD10/
HD10
EM_D9/
DD9/
HD9
EM_D8/
DD8/
HD8
These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases
they are used as a 16 bit bi-directional data bus.
I/O/Z
DVDD18
EM_D7/
DD7/
HD7
For ATA/CF, these are DD[15:0].
EM_D6/
DD6/
HD6
EM_D5/
DD5/
HD5
EM_D4/
DD4/
HD4
EM_D3/
DD3/
HD3
EM_D2/
DD2/
HD2
EM_D1/
DD1/
HD1
EM_D0/
DD0/
HD0
EM_A[0]/
DA2/
HCNTL1/
GPIO53
This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.
For ATA/CF, it is Device address bit 2 output DA2.
J4
I/O/Z
DVDD18
EM_BA[1]/
DA1/
GPIO52
This pin is multiplexed between EMIFA, ATA/CF, and GPIO.
For ATA/CF, it is Device address bit 1 output DA1.
H2
J3
I/O/Z
I/O/Z
DVDD18
EM_BA[0]/
DA0/
HINT
This pin is multiplexed between EMIFA, ATA/CF, HPI.
For ATA/CF, it is Device address bit 0 output DA0.
DVDD18
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Table 2-25. MMC/SD/SDIO Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2)
DESCRIPTION
NO.
MMC/SD/SDIO
SD_CLK
SD_CMD
A9
B9
C9
D9
E9
D8
O
DVDD33
DVDD33
Data clock output SD_CLK
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Bi-directional command IO SD_CMD
SD_DATA3
SD_DATA2
SD_DATA1
SD_DATA0
DVDD33
These pins are the nibble wide bi-directional data bus SD_DATA[3:0].
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
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Table 2-26. HPI Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NO.
Host-Port Interface (HPI)
For EMIFA, this pin is Chip Select 3 output.
In HPI mode this pin must be pulled high via an external 10-kΩ resistor.
EM_CS3
B1
J3
I/O/Z
I/O/Z
DVDD18
DVDD18
EM_BA[0]/
DA0/
HINT
This pin is multiplexed between EMIFA, ATA/CF, and HPI.
In HPI mode, it is the host interrupt output HINT.
EM_A[0]/
DA2/
HCNTL1/
GPIO53
This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.
For HPI, it is control input HCNTL1. The state of HCNTL1 and HCNTL0 determine
if address, data, or control information is being transmitted between an external
host and DM644X.
J4
I/O/Z
DVDD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI.
In HPI mode, it is control input HCNTL0. The state of HCNTL1 and HCNTL0
determine if address, data, or control information is being transmitted between an
external host and DM644X.
EM_A[2]/
(CLE)/
HCNTL0
J1
J2
I/O/Z
I/O/Z
DVDD18
EM_A[1]/
(ALE)/
HHWIL
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI.
In HPI mode, it is Half-word identification input HHWIL.
DVDD18
EM_R/W/
INTRQ/
HR/W
This pin is multiplexed between EMIFA, ATA/CF, and HPI.
For HPI, it is the Host Read Write input HR/W. This signal is active high for reads
and low for writes.
G3
C2
I/O/Z
I/O/Z
DVDD18
DVDD18
EM_CS2/
HCS
This pin is multiplexed between EMIFA and HPI.
In HPI mode, this pin is HPI Active Low Chip Select input HCS.
EM_WE
(WE)
(IOWR)/
DIOW/
HDS2
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For HPI, it is data strobe 2 input HDS2.
G2
I/O/Z
DVDD18
EM_OE/
(RE)/
(IORD)/
DIOR/
HDS1
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For HPI, it is data strobe 1 input HDS1.
H4
F1
I/O/Z
I/O/Z
DVDD18
EM_WAIT/
(RDY/BSY)/
IORDY/
IPU
DVDD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For HPI, it is ready output HRDY.
HRDY
(1) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-26. HPI Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NO.
EM_D15/
DD15/
E1
HD15
EM_D14/
DD14/
HD14
H5
F2
D1
G4
G5
E2
F3
C1
F4
D2
E4
E3
F5
D3
E5
EM_D13/
DD13/
HD13
EM_D12/
DD12/
HD12
EM_D11/
DD11/
HD11
EM_D10/
DD10/
HD10
EM_D9/
DD9/
HD9
EM_D8/
DD8/
HD8
These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI.
I/O/Z
DVDD18
In HPI mode, these are HD[15:0] and are multiplexed internally with the HPI
address lines.
EM_D7/
DD7/
HD7
EM_D6/
DD6/
HD6
EM_D5/
DD5/
HD5
EM_D4/
DD4/
HD4
EM_D3/
DD3/
HD3
EM_D2/
DD2/
HD2
EM_D1/
DD1/
HD1
EM_D0/
DD0/
HD0
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Table 2-27. Timer 0, Timer 1, and Timer 2 Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2)
DESCRIPTION
NO.
Timer 2 and Timer 1
No external pins. The Timer 2 and Timer 1 peripheral pins are not pinned out as external pins.
Timer 0
CLK_OUT1/
TIM_IN/
GPIO49
This pin is multiplexed between the USB clock generator, timer, and GPIO.
For Timer0, it is the timer event capture input TIM_IN.
E19
I/O/Z
DVDD18
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
Table 2-28. Reserved Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
RESERVED
RSV1
RSV2
RSV3
RSV4
A1
A19
W1
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
W19
IPD
VSS
RSV5
D4
I
Reserved. This pin must be tied directly to VSS for normal device operation.
RSV6
RSV7
L3
R8
M3
A O
A
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
RSV24
S
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal
Table 2-29. Supply Terminal Functions
SIGNAL
TYPE(1)
OTHER
DESCRIPTION
NAME
NO.
SUPPLY VOLTAGE PINS
F10
F11
F12
F13
3.3 V I/O supply voltage
(see the Power-Supply Decoupling section of this data manual)
DVDD33
S
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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Table 2-29. Supply Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER
DESCRIPTION
NAME
NO.
N5
G15
F14
J15
H14
K14
M14
L13
G9
1.8 V I/O supply voltage
(see the Power-Supply Decoupling section of this data manual)
DVDD18
S
F8
E7
G7
J7
L7
F6
H6
K6
M6
T5
P6
N7
P8
N9
R9
P10
N11
R11
P12
N13
R13
P14
R15
F15
K12
M12
L11
M10
L10
K10
L9
1.8 V DDR2 I/O supply voltage
(see the Power-Supply Decoupling section of this data manual)
DVDDR2
S
1.20 V core supply voltage
(see the Power-Supply Decoupling section of this data manual)
CVDD
S
L8
M8
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Table 2-29. Supply Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
OTHER
DESCRIPTION
NO.
J13
H12
H11
J11
K11
J10
H10
J9
1.20 V DSPSS supply voltage (A-513, -594 devices)
(see the Power-Supply Decoupling section of this data manual)
CVDDDSP
S
K9
K8
H8
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Table 2-30. Ground Terminal Functions
SIGNAL
TYPE(1)
OTHER
DESCRIPTION
NAME
NO.
GROUND PINS
K5
M5
G6
J6
L6
N6
R6
F7
H7
K7
M7
P7
R7
E8
G8
J8
N8
F9
H9
VSS
M9
P9
GND
Ground pins
G10
N10
R10
G11
M11
P11
G12
J12
N12
L12
R12
G13
H13
K13
M13
P13
G14
J14
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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Table 2-30. Ground Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
OTHER
DESCRIPTION
NO.
L14
N14
R14
H15
K15
P15
VSS
GND
Ground pins
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2.8 Device Support
2.8.1 Development Support
TI offers an extensive line of development tools for the SM320DM644x SoC platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tool's support documentation is electronically
available within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of SM320DM644x SoC-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any SoC application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the SM320DM644x SoC platform, visit the
Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator
(URL). For information on pricing and availability, contact the nearest TI field sales office or authorized
distributor.
2.8.2 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMX320DM6446ZWT). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications.
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, "Blank" is the default
[594-MHz DSP, 297-MHz ARM9]).
Figure 2-6 provides a legend for reading the complete device name for any TMS320DM644x SoC platform
member.
SM 320 DM6446 ( ) ZWT
(
)
( )
PREFIX
DEVICE SPEED RANGE
TMX = Experimental device
TMS = Qualified device
SM = HiRel Qualified device
Blank = 594-MHz DSP, 297-MHz ARM9
[commercial temperature]
TEMPERATURE RANGE (DEFAULT: 0°C TO 85°C)
DEVICE FAMILY
320 = TMS320 DSP family
Blank = 0°C to 85°C, commercial temperature
A = -40°C to 105°C, extended temperature
(A)
PACKAGE TYPE
ZWT = 361-pin plastic BGA, with Pb-free soldered balls
(B)
DEVICE
DM644x DMSoC:
DM6443
DM6446
SILICON REVISION
Blank = Silicon 1.3
A = Silicon 2.1
A. BGA = Ball Grid Array
B.
.ti.com).
Figure 2-6. Device Nomenclature
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2.8.3 Documentation Support
2.8.3.1 Related Documentation From Texas Instruments
The following documents describe the TMS320DM644x Digital Media System-on-Chip (DMSoC). Copies
of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the
search box provided at www.ti.com.
The current documentation that describes the DM644x DMSoC, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRUE14 TMS320DM644x DMSoC ARM Subsystem Reference Guide. Describes the ARM
subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ARM
subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In
general, the ARM is responsible for configuration and control of the device; including the
DSP subsystem, the video processing subsystem, and a majority of the peripherals and
external memories.
SPRUE15 TMS320DM644x DMSoC DSP Subsystem Reference Guide. Describes the digital signal
processor (DSP) subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC).
SPRUE19 TMS320DM644x DMSoC Peripherals Overview Reference Guide. Provides an overview
and briefly describes the peripherals available on the TMS320DM644x Digital Media
System-on-Chip (DMSoC).
SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas
Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in
the devices that is identical is not included.
SPRU732
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+
digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP
generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an
enhancement of the C64x DSP with added functionality and an expanded instruction set.
SPRU871
TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
SPRAAA6 EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migrating
from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct
memory access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC)
EDMA3. This document summarizes the key differences between the EDMA3 and the
EDMA2 and provides guidance for migrating from EDMA2 to EDMA3.
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3 Device Configurations
3.1 System Module Registers
The system module includes status and control registers required for configuration of the device. Brief
descriptions of the various registers are shown in Table 3-1. System Module registers required for device
configurations are discussed in the following sections.
Table 3-1. System Module Register Memory Map
HEX ADDRESS RANGE
REGISTER ACRONYM
DESCRIPTION
0x01C4 0000
PINMUX0
Pin multiplexing control 0. For details, see Section 3.5.4, PINMUX0 Register
Description.
0x01C4 0004
0x01C4 0008
PINMUX1
Pin multiplexing control 1. For details, see Section 3.5.5, PINMUX1 Register
Description.
DSPBOOTADDR
Boot address of DSP. For details, see Section 3.3.1.2, DSPBOOTADDR
Register Description.
0x01C4 000C
0x01C4 0010
SUSPSRC
INTGEN
Emulator Suspend Source. For details, see Section 3.6, Emulation Control.
ARM/DSP Interrupt Status and Control. For details, see Section 6.7.3,
ARM/DSP Communications Interrupts.
0x01C4 0014
BOOTCFG
Device boot configuration. For details, see Section 3.3.1.1, BOOTCFG
Register Description.
0x01C4 0018 - 0x01C4 0027
0x01C4 0028
–
Reserved.
JTAGID
JTAGID/Device ID number. For details, see Section 6.25.1, JTAG ID Register
Description.
0x01C4 002C
0x01C4 0030
–
Reserved.
HPI_CTL
HPI control. For details, see Section 3.5.6.10, HPI and EMIFA/ATA Pin
Multiplexing.
0x01C4 0034
0x01C4 0038
0x01C4 003C
0x01C4 0040
USBPHY_CTL
CHP_SHRTSW
MSTPRI0
USB PHY control. For details, see Section 6.15.1, USBPHY_CTL Register
Description.
Chip shorting switch control. For details, see Section 3.2.1, Power
Configurations at Reset.
Bus master priority control 0. For details, see Section 3.5.1, Switched Central
Resource (SCR) Bus Priorities.
MSTPRI1
Bus master priority control 1. For details, see Section 3.5.1, Switched Central
Resource (SCR) Bus Priorities.
0x01C4 0044
0x01C4 0048
VPSS_CLKCTL
VPSS clock control.
VDD3P3V_PWDN
VDD 3.3V I/O powerdown control. For details, see Section 3.2.2, Power
Configurations after Reset.
0x01C4 004C
DRRVTPER
–
Enables access to the DDR2 VTP Register.
Reserved.
0x01C4 0050 - 0x01C4 006F
3.2 Power Considerations
Global device power domains are controlled by the Power and Sleep Controller, except as shown in the
following sections.
3.2.1 Power Configurations at Reset
As described in the DM6446 Power and Clock Domains section, the DM6446 has two power domains:
Always On and DSP. There is a shorting switch between the two power domains that must be opened
when the DSP domain is powered off and closed when the DSP domain is powered on.
The CHP_SHRTSW register, shown in Figure 3-1, controls the shorting switch between the device
always-on and DSP power domains. This switch should be enabled after powering-up the DSP domain.
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Setting the DSPPWRON bit to '1’ closes (enables) the switch and enables the DSP power domain. The
default switch value is determined by the DSP_BT configuration input. If DSP self boot is selected
(DSP_BT=1), the DSP will be powered-up and DSPPWRON will be set to a value of '1'. For ARM boot
operation (DSP_BT=0), DSPPWRON will be set to the disable value of '0' and must be set by the ARM
before the DSP domain power is turned on.
Note: Once the DSP power domain is enabled (powered up), it cannot be disabled (powered down).
Dynamic power down of the DSP is not supported on this device.
Figure 3-1. CHP_SHRTSW Register
31
1
0
RESERVED
DSPPWRON
R/W-L
R-0000 0000 0000 0000 0000 0000 0000 000
LEGEND: R = Read, W = Write, n = value at reset, L = pin state latched at reset rising
Table 3-2. CHP_SHRTSW Register Description
NAME
DESCRIPTION
DSPPWRON
DSP power domain enable.
0 = Shorting switch open
1 = Shorting switch closed
3.2.2 Power Configurations after Reset
The VDD3P3V_PWDN register controls power to the 3.3V I/O buffers for MMC/SD/SDIO and GPIOV33.
The 3.3V I/Os are separated into two groups for independent control as shown in Figure 3-2 and
described in Table 3-3. By default, these pins are all disabled at reset.
Figure 3-2. VDD3P3V_PWDN Register
31
2
1
0
RESERVED
IOPWDN1 IOPWDN0
R/W-1 R/W-1
R-0000 0000 0000 0000 0000 0000 0000 00
LEGEND: R = Read, W = Write, n = value at reset
Table 3-3. VDD3P3V_PWDN Register Description
NAME
IOPWDN0
DESCRIPTION
GIOV33 I/O Powerdown controls GIOV33[16:0] pins.
0 = I/O buffers powered up
1 = I/O buffers powered down
IOPWDN1
MMC/SD/SDIO I/O Powerdown controls SD_CLK, SD_CMD, SD_DATA[3:0] pins.
0 = I/O buffers powered up
1 = I/O buffers powered down
3.3 Bootmode
The device is booted through multiple means: pin states captured at reset, primary bootloaders within
internal ROM or EMIFA, and secondary user bootloaders from peripherals or external memories. Boot
modes, pin configurations, and register configurations required for booting the device, are described in the
following sections.
3.3.1 Bootmode Registers
The BOOTCFG and DSPBOOTADDR registers are described in the following sections. At reset, the status
of various pins required for proper boot are stored within these registers.
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3.3.1.1 BOOTCFG Register Description
The BOOTCFG register (located at address 0x01C4 000A) contains the status values of the BTSEL1,
BTSEL0, DSP_BT, EM_WIDTH, and AEAW[4:0] pins captured at the rising edge of RESET. The register
format is shown in Figure 3-3 and bit field descriptions are shown in Table 3-4. The captured bits are
software readable after reset.
Figure 3-3. BOOTCFG Register
31
9
8
7
6
5
4
3
2
1
0
RESERVED
DSP_BT
R-L
BTSEL
R-LL
EM_WIDTH
R-L
DAEAW
R-0000 0000 0000 0000 0000 000
R-LLLLL
LEGEND: R = Read; W = Write; L = pin state latched at reset rising; -n = value after reset
Table 3-4. BOOTCFG Register Description
NAME
DESCRIPTION
BTSEL
ARM Boot mode selection pin states (BTSEL1, BTSEL0) captured at the rising edge of RESET.
‘00’ indicates ARM boots from ROM (NAND Flash).
‘01’ indicates that ARM boots from EMIFA (NOR Flash).
‘10’ indicates that ARM boots from ROM (HPI).
‘11’ indicates that ARM boots from ROM (UART0).
DSP_BT
DSP Boot mode selection pin state captured at the rising edge of RESET.
‘0’ sets ARM boot of C64x+.
‘1’ sets C64x+ self boot.
EM_WIDTH
DAEAW
EMIFA data bus width selection pin state captured at the rising edge of RESET.
‘0’ sets EMIFA to 8 bit data bus width
‘1’ sets EMIFA to 16 bit data bus width.
EMIFA address bus width selection pin states (AEAW[4:0]) captured at the rising edge of RESET. This configures
EMIFA address pins multiplexed with GPIO. See Table 3-9,Table 3-10, and Table 3-11
3.3.1.2 DSPBOOTADDR Register Description
The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register
format is shown in Figure 3-4 and bit field descriptions are shown in Table 3-5. DSPBOOTADDR is
readable and writable by software after reset.
Figure 3-4. DSPBOOTADDR Registers
31
10
9
0
BOOTADDR[21:0]
RESERVED
R- 0100 0010 0010 0000 0000 00
R-00 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-5. DSPBOOTADDR Register Description
NAME
DESCRIPTION
BOOTADDR[21:0]
Upper 22 bits of the C64x+ DSP boot address.
3.3.2 ARM Boot
The DM6446 ARM can boot from EMIFA, internal ROM (NAND), UART0, or HPI, as determined by the
setting of the BTSEL[1:0] pins. The BTSEL[1:0] pins are read by the ARM ROM Boot Loader (RBL) to
further define the ROM boot mode. The ARM boot modes are summarized in Table 3-6.
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Table 3-6. ARM Boot Modes
BTSEL1 BTSEL0
BOOT MODE
ARM RESET
VECTOR
BRIEF DESCRIPTION
0
0
ARM NAND RBL
0x0000 4000
Up to 14 K-bytes secondary boot loader through NAND with up
to 2 K-bytes page sizes.
0
1
1
0
ARM EMIFA External Boot
ARM HPI RBL
0x0200 0000
0x0000 4000
EMIFA EM_CS2 external memory space.
Up to 14 K-btyes secondary boot loader through an external
host.
1
1
ARM UART RBL
0x0000 4000
Up to 14 K-bytes secondary boot loader through UART0.
When the BTSEL[1:0] pins are set to the ARM EMIFA External Boot ("01"), the ARM immediately begins
executing code from the EMIFA EM_CS2 memory space (0x0200 0000). When the BTSEL[1:0] pins
indicate a condition other than the ARM EMIFA External Boot (!01), the RBL begins execution.
ARM NAND Boot mode has the following features:
•
Loads a secondary User Boot Loader (UBL) from NAND flash to ARM Internal RAM (AIM) and
transfers control to the user software.
•
•
•
•
Support for NAND with page sizes up to 2048 bytes.
Support for error correction when loading UBL
Support for up to 14KB UBL
Optional, user selectable, support for use of DMA, I-cache, and PLL enable while loading UBL
ARM UART Boot mode has the following features:
•
•
Loads a secondary UBL via UART0 to AIM and transfers control to the user software.
Support for up to 14KB UBL
ARM HPI Boot Mode has the following features:
•
No support for a full firmware boot. Instead, waits for external host to load a secondary UBL via HPI to
AIM and transfers control to the user software.
•
Support for up to 14KB UBL.
For further details on the ROM Bootloader, refer to the ARM Subsystem Users Guide.
3.3.3 DSP Boot
For C64x+ booting, the state of the DSP_BT pin is sampled at reset. If DSP_BT is low, the ARM will be
the master of C64x+ and control booting (Host Boot mode). If DSP_BT is high, the C64x+ will boot itself
coming out of device reset (Self-Boot mode). Table 3-7 shows a summary of the DSP boot modes.
Table 3-7. DSP Boot Modes
DSP_BT
DSP
ARM
DSPBOOTADDR
BRIEF DESCRIPTION
BOOT MODE
BOOT MODE
REGISTER VALUE
0
Host Boot
Internal Boot
Programmable
ARM sets an internal DSP memory location in DSPBOOTADDR
register where valid DSP code resides and loads code to this
internal DSP memory through DMA prior to releasing DSP reset.
0
Host Boot
External Boot
Programmable
ARM sets an external DSP memory location in DSPBOOTADDR
register (EMIFA or DDR2) where valid DSP code resides prior to
releasing DSP reset.
1
1
Self Boot
Host Boot
Any, except HPI
HPI
0x4220 0000
Default EMIFA Base Address
Programmable
ARM sets a DSP memory location in the DSPBOOTADDR
register. HPI loads code into the DM6446 memory map with the
entry point set to the memory location specified in the
DSPBOOTADDR register. Once the HPI completes loading the
code, the ARM should release the DSP from reset.
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3.3.3.1 Self-Boot Mode
In self-boot mode, the C64x+ power domain is turned on and the C64x+ DSP is released from reset
without ARM intervention. The C64x+ begins execution from the default EMIFA address (0x4220 0000)
contained within the DSPBOOTADDR register. The C64x+ begins execution with instruction (L1P) cache
enabled.
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3.4 Configurations at Reset
The following sections give information on configuration settings for the device at reset.
3.4.1 Device Configuration at Device Reset
Table 3-8 shows a summary of device inputs required for booting the ARM and DSP, and configuring
EMIFA data and address bus widths for proper operation of the device at the rising edge of the RESET
input.
Table 3-8. Device Configurations (Input Pins Sampled at Reset)
DEVICE SIGNALS
DEVICE SIGNAL NAME
AFTER RESET
SAMPLED
AT RESET
DESCRIPTION
BTSEL[1:0]
COUT[1:0]
ARM Boot mode selection pins.
‘00’ indicates ARM boots from ROM (NAND Flash).
‘01’ indicates that ARM boots from EMIFA (NOR Flash).
‘10’ indicates that the ARM boots from the HPI (ROM)
‘11’ indicates that ARM boots from ROM (UART0).
DSP_BT
EM_WIDTH
AEAW[4:0]
COUT3
COUT2
DSP Boot mode selection pin.
‘0’ sets ARM boot of C64x+.
‘1’ sets C64x+ self boot.
EMIFA data bus width selection pin.
‘0’ sets EMIFA to 8-bit data bus width
‘1’ sets EMIFA to 16-bit data bus width.
YOUT[4:0]
EMIFA address bus width selection pins for EMIFA address pins multiplexed with GPIO.
See Table 3-9, Table 3-10, and Table 3-11 for details.
3.4.2 Peripheral Selection at Device Reset
As briefly mentioned in Table 3-8, the state of the AEAW[4:0] pins captured at reset configures the
number of EMIFA address pins required for device boot. These values are stored in the AEAW field of the
PINMUX0 register. At reset, this provides proper addressing for external boot. Unused address pins are
available for use as GPIO. The register settings are software programmable after reset. Table 3-9,
Table 3-10, and Table 3-11 show the AEAW[4:0] bit settings and the corresponding multiplexing for
EMIFA address and GPIO pins.
The number of EMIFA address bits enabled is configurable from 0 to 23. EM_BA[1] and EM_A[21:0] pins
that are not assigned to another peripheral and not enabled as address signals become GPIO pins. The
enabled address pins are always contiguous from EM_BA[1] upwards and address bits cannot be skipped.
The exception to this are the EM_A[2:1] pins. EM_A[2:1] are usable as the ALE and CLE signals for the
NAND Flash mode of EMIFA and are always enabled as EMIFA pins. If an address width of 0 is selected,
this still allows a NAND Flash to be accessed. Also, selecting an address width of 2, 3, or 4 (AEAW[4:0] =
00010, 00011, or 00100) always results in 4 address outputs. For these and other address bit enable
settings, see Table 3-9, Table 3-10, and Table 3-11.
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Table 3-9. GPIO and EMIFA Multiplexing (Part 1)
Pin Mux Register AEAW[4:0] Bit Settings
00000
00001
00010
00011
00100
00101
00110
00111
(default)
GPIO[52]
GPIO[53]
EM_A[1]
EM_A[2]
GPIO[28]
GPIO[27]
GPIO[26]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
GPIO[53]
EM_A[1]
EM_A[2]
GPIO[28]
GPIO[27]
GPIO[26]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
GPIO[28]
GPIO[27]
GPIO[26]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
GPIO[28]
GPIO[27]
GPIO[26]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
GPIO[28]
GPIO[27]
GPIO[26]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
GPIO[27]
GPIO[26]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
GPIO[26]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
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Table 3-10. GPIO and EMIFA Multiplexing (Part 2)
Pin Mux Register AEAW[4:0] Bit Settings
01000
01001
01010
01011
01100
01101
01110
01111
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
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Table 3-11. GPIO and EMIFA Multiplexing (Part 3)
Pin Mux Register AEAW[4:0] Bit Settings
10000
10001
10010
10011
10100
10101
10110
Others
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
GPIO[12]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
GPIO[11]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
EM_A[20]
GPIO[10]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
EM_A[20]
EM_A[21]
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3.5 Configurations After Reset
The following sections give the details on configuring the device after reset.
3.5.1 Switched Central Resource (SCR) Bus Priorities
Prioritization within the switched central resource (SCR) is programmable for each master. The register bit
fields and default priority levels for DM6446 bus masters are shown in Table 3-12. The priority levels
should be tuned to obtain the best system performance for a particular application. Lower values indicate
higher priority. For most masters, their priority values are programmed at the system level by configuring
the MSTPRI0 and MSTPRI1 registers. Details on the MSTPRI0/1 registers are shown in Figure 3-5 and
Figure 3-6. The C64x+, VPSS, and EDMA masters contain registers that control their own priority values.
Table 3-12. DM6446 Default Bus Master Priorities
BUS
PRIORITY BIT FIELD
VPSSP
MASTER
DEFAULT PRIORITY LEVEL
0 (VPSS PCR Register)
VPSS
EDMATC0P
EDMATC1P
ARM_DMAP
ARM_CFGP
C64X+_DMAP
EDMATC0 0 (EDMACC QUEPRI Register)
EDMATC1 0 (EDMACC QUEPRI Register)
ARM (DMA) 1 (MSTPRI0 Register)
ARM (CFG) 1 (MSTPRI0 Register)
C64X+
(DMA)
7 (C64x+ MDMAARBE.PRI Register bit field)
C64X+_CFGP
C64X+
(CFG)
1 (MSTPRI0 Register)
EMACP
USBP
EMAC
USB
4 (MSTPRI1 Register)
4 (MSTPRI1 Register)
4 (MSTPRI1 Register)
4 (MSTPRI1 Register)
4 (MSTPRI1 Register)
ATAP
ATA/CF
VLYNQ
HPI
VLYNQP
HPIP
Figure 3-5. MSTPRI0 Register
31
15
19
18
2
16
0
RESERVED
R-0000 0000 0000 0
VICPP(1)
R/W-101
11
10
8
7
6
4
3
RESERVED
R-0000 0
C64X+_CFGP
R/W-001
RSV
R-0
ARM_CFGP
R/W-001
RSV
R-0
ARM_DMAP
R/W-001
LEGEND: R = Read; W = Write; -n = value after reset
(1) The VICPP bit field is configured by the third-party software. When modifying the MSTPRI0 register a read/modify/write must be
performed to preserve the configuration set by the third-party software.
Figure 3-6. MSTPRI1 Register
31
23
22
20
4
19
18
2
16
0
RESERVED
HPIP
RSV
R-0
VLYNQP
R/W-100
R-0000 0000 0
R-100
15
14
12
11
10
8
7
6
3
RSV
R-0
ATAP
RSV
R-0
USBP
RSV
R-0
RESERVED
R-100
RSV
R-0
EMACP
R/W-100
R/W-100
R/W-100
LEGEND: R = Read; W = Write; -n = value after reset
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3.5.2 Multiplexed Pin Configurations
There are numerous multiplexed pins that are shared by more than one peripheral. Some of these pins
are configured by external pullup/pulldown resistors only at reset, and others are configured by software.
As described in detail in Section 3.4.1 and Section 3.4.2, hardware configurable multiplexed pins are
programmed by external pullup/pulldown resistors at reset to set the initial functionality of pins for use by a
single peripheral. After reset, software configurable multiplexed pins are programmable through Memory
Mapped Registers (MMR) to allow the switching of pin functionalities during run-time. See Section 3.5.3
for more details on the register settings.
A summary of the pin multiplexing is shown in Table 3-13. The EMAC peripheral shares pins with the 3.3V
GPIO pins. The VLYNQ pins overlap upper EMIFA address pins resulting in a reduced EMIFA address
range as the VLYNQ width is increased. The ATA peripheral shares data lines and some control signals
with EMIFA. The ATA DMA pins are multiplexed with UART1. The ASP, UART0/1/2, SPI, I2C, and
PWM0/1/2 all default to GPIO pins when not enabled. The VPBE function of the VPSS requires additional
pins to implement the RGB888 mode. These are multiplexed with GPIOs.
Table 3-13. DM6446 Multiplexed Peripheral Pins and Multiplexing Controls
PRIMARY
(DEFAULT)
FUNCTION
SECONDARY
REGISTER/PIN(3)
CONTROL
TERTIARY
REGISTER/PIN(3)
CONTROL
MULTIPLEXED
PERIPHERALS
SECONDARY(1)
FUNCTION
TERTIARY(2)
FUNCTION
EMIFA (NAND), HPI EMIFA (NAND):
EM_A[1] (ALE),
HPI:
HHWIL, HCNTL0,
HCS
PinMux0:HPIEN,
Pins:BTSEL[1:0] = 10
EM_A[2] (CLE),
EM_CS2, EM_CS3
EMIFA, HPI, ATA
(CF)
EMIFA:
EM_D[0:15],
EM_BA[0]
ATA (CF):
DD[0:15], DA0
HPI:
HD[0:15], HINT
PinMux0:ATAEN
PinMux0:ATAEN
PinMux0:HPIEN,
Pins:BTSEL[1:0] = 10
EMIFA (NAND),
HPI, ATA (CF)
EMIFA (NAND):
R/W, EM_WAIT
(RDY/BSY),
EM_OE (RE),
EM_WE (WE)
ATA (CF):
HPI:
PinMux0:HPIEN,
Pins:BTSEL[1:0] = 10
INTRQ, IORDY,
DIOR(IORD) ,
DIOW (IOWR)
HR/W, HRDY, HDS1,
HDS2
VPBE LCD, GPIO
VPFE CCD, GPIO
GPIO:GPIO[0]
GPIO:GPIO[1]
GPIO:GPIO[2]
VPBE: LCD_OE
VPFE: C_WE
PinMux0:LOEEN
PinMux0:CWE
VPBE RGB888,
GPIO
VPBE:
RGB888 G0
PinMux0:RGB888
VPBE
LCD/RGB888, GPIO
GPIO:GPIO[3]
GPIO:GPIO[4]
VPBE:
RGB888 B0
VPBE:
LCD_FIELD
PinMux0:RGB888
PinMux0:RGB888
PinMux0:RGB888
PinMux0:LFLDEN
PinMux0:CFLDEN
VPFE CCD, VPBE
RGB888, GPIO
VPBE:
RGB888 R0
VPFE:
CCD_FIELD
VPBE RGB888,
GPIO
GPIO:
GPIO[5:6, 38]
VPBE:
RGB888 G1, B1,
R1
EMIFA, VLYNQ,
GPIO
GPIO:GPIO[8]
GPIO:GPIO[9]
EMIFA:
EM_CS5
VLYNQ:
VLYNQ_CLOCK
PinMux0:AECS5
PinMux0:AECS4
PinMux0:VLYNQEN
PinMux0:VLSCREN
EMIFA, VLYNQ,
GPIO
EMIFA:
EM_CS4
VLYNQ:
VLYNQ_SCRUN
EMIFA, VLYNQ,
GPIO
GPIO:
GPIO[10:17]
EMIFA:
EM_A[21:14]
VLYNQ:
VLYNQ_TXD[0:3],
VLYNQ_RXD[0:3]
PinMux0:AEAW,
Pins:DAEAW[4:0]
PinMux0:VLYNQEN,
PinMux0:VLYNQWD[1:0]
EMIFA, GPIO
GPIO:
GPIO[18:28]
EMIFA:
EM_A[13:3]
PinMux0:AEAW,
Pins:DAEAW[4:0]
(1) When the Secondary function is enabled, to avoid potential contention, ensure that the Primary (if not GPIO) and Tertiary functions are
disabled.
(2) When the Tertiary function is enabled, to avoid potential contention, ensure that the Primary (if not GPIO), Secondary, and other Tertiary
functions are disabled.
(3) Pin states are sampled at power on reset and written into the register fields.
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Table 3-13. DM6446 Multiplexed Peripheral Pins and Multiplexing Controls (continued)
PRIMARY
(DEFAULT)
FUNCTION
SECONDARY
REGISTER/PIN(3)
CONTROL
TERTIARY
MULTIPLEXED
PERIPHERALS
SECONDARY(1)
FUNCTION
TERTIARY(2)
FUNCTION
REGISTER/PIN(3)
CONTROL
ASP, GPIO
UART0, GPIO
SPI, GPIO
GPIO:
GPIO[29:34]
ASP:
PinMux1:ASP
PinMux1:UART0
PinMux1:SPI
(all pins)(4)
GPIO:
GPIO[35:36]
UART0:
RXD, TXD
GPIO:
SPI:
GPIO[37, 39:41]
SPI_EN0,
SPI_CLK,
SPI_DI, SPI_DO
SPI, ATA, GPIO
I2C, GPIO
GPIO:GPIO[42]
SPI: SPI_EN1
I2C: SCL, SDA
ATA: HDDIR
PinMux1:SPI
PinMux1:I2C
PinMux0:HDIREN
GPIO:
GPIO[43:44]
PWM0, GPIO
GPIO:GPIO[45]
GPIO:GPIO[46]
PWM0
PinMux1:PWM0
PWM1, VPBE
(RGB666/RGB888),
GPIO
VPBE:
RGB666/RGB888 PWM1
R2
PWM1:
PinMux0:RGB666/
PinMux0:RGB888
PinMux1:PWM1
PinMux1:PWM2
PWM2, VPBE
(RGB666/RGB888),
GPIO
GPIO:GPIO[47]
GPIO:GPIO[48]
VPBE:
RGB666/RGB888 PWM2
B2
PWM2:
PinMux0:RGB666/
PinMux0:RGB888
ClockOut0, GPIO
CLK_OUT0
PinMux1:CLK0
PinMux1:CLK1
ClockOut1, TIMER0, GPIO:GPIO[49]
GPIO
CLK_OUT1
TIMER0:
TIM_IN
PinMux1:TIM_IN
PinMux0:ATAEN
ATA, GPIO
GPIO:
GPIO[50:51]
ATA:
ATA_CS0,
ATA_CS1
PinMux0:ATAEN
EMIFA, GPIO, ATA GPIO:GPIO[52]
(CF)
EMIFA:
EM_BA[1]
ATA (CF):
DA1
PinMux0:AEAW[4:0],
Pins:DAEAW[4:0]
EMIFA, HPI, ATA
(CF), GPIO
GPIO:GPIO[53]
EMIFA:
EM_A[0]
ATA (CF): DA2/
HPI: HCNTL1
PinMux0:AEAW[4:0],
Pins:DAEAW[4:0]
PinMux0:ATAEN,
PinMux0:HPIEN,
Pins:BTSEL[1:0] = 10
EMAC, GPIO3V
GPIO:
GPIO3V[0:13]
EMAC:
PinMux0:EMACEN
PinMux0:EMACEN
(all pins, except
CRS)(4)
EMAC, MDIO,
GPIO3V
GPIO:
GPIO3V[14:16]
EMAC:
CRS,
MDIO:
MDIO, MDCLK
UART1, ATA (CF)
UART2, VPFE
N/A
ATA (CF):
DMACK, DMARQ
UART1: TXD, RXD
PinMux0:ATAEN
PinMux1:UART2
PinMux1:UART1
VPFE:
UART2:
CI[7:6]/
UART_RXD2,
CCD_DATA[15:14] UART_TXD2
UART2, VPFE
VPFE:
CI[5:4]/
UART2:
UART_CTS2,
PinMux1:UART2,
PinMux1:U2FLO
CCD_DATA[13:12] UART_RTS2
(4) See the Terminal Functions section for pin details.
3.5.3 Peripheral Selection After Device Reset
After device reset, the PINMUX0 and PINMUX1 registers are software programmable to allow multiplexing
of shared device pins between peripherals, as given in the Terminal Functions section. Section 3.5.4,
Section 3.5.5, and Section 3.5.6 identify the register settings necessary to configure specific multiplexed
functions and show the primary (default) function after reset.
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3.5.4 PINMUX0 Register Description
The PINMUX0 pin multiplexing register controls which peripheral is given ownership over shared pins
among EMAC, CCD, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, HPI, and GPIO peripherals. The
register format is shown in Figure 3-7 and bit field descriptions are given in Table 3-14. More details on
the PINMUX0 pin muxing fields are given in Section 3.5.6. A value of '1' enables the secondary or tertiary
pin function.
Figure 3-7. PINMUX0 Register(1)
31
30
29
28
27
26
25
24
23
22
21
18
17
16
EMACEN
R/W-0
Rsvd
HPIEN Rsvd
CFLDEN
R/W-0
CWE
LFLDEN LOEEN RGB888
RGB666
R/W-0
Reserved
R-0000
ATAEN HDIREN
R/W-0 R/W-D R-0
R/W-0
R/W-0
9
R/W-0
R/W-0
R/W-0
R/W-0
0
15
14
13
12
11
10
5
4
VLYNQEN VLSCREN
VLYNQWD
R/W-00
AECS5
R/W-0
AECS4
R/W-0
Reserved
R-00000
AEAW
R/W-0
R/W-0
R/W-LLLL
LEGEND: R = Read; W = Write; L = pin state latched at reset rising edge; D = derived from pin states; -n = value after reset
(1) For proper DM6446 device operation, always write a value of '0' to RSV bits 30 and 29
Table 3-14. PINMUX0 Register Description
Name
Description
EMACEN
HPIEN
Enable EMAC and MDIO function on default GPIO3V[0:16] pins.
Enable HPI module pins. Default value is derived from BTSEL[1:0] configuration inputs.
HPIEN is 1 when the BTSEL[1:0] = 10 for non-secure devices only. HPIEN default state
is always 0 for secure divices.
CFLDEN
CWE
Enable CCD C_FIELD function on default GPIO[4] pin
Enable CCD C_WE function on default GPIO[1] pin
LFLDEN
LOEEN
Enable LCD_FIELD function on default GPIO[3] pin
Enable LCD_OE function on default GPIO[0] pin
RGB888
RGB666
ATAEN
Enable VPBE RGB888 function on default GPIO[2:6, 46:47] pins
Enable VPBE RGB666 function on default GPIO[46:47] pins
Enable ATA function on default EMIFA and GPIO[52:53] pins and shared UART1 pins
Enable HDDIR function on default GPIO[42] pin
HDIREN
VLYNQEN
VLSCREN
VLYNQWD
Enable VLYNQ function on default GPIO[9,10:17] pins
Enable VLYNQ SCRUN function on default GPIO[9] pin
VLYNQ data width selection. This expands the VLYNQ TXD[0:3] and RXD[0:3]
functions on default GPIO[10:17] pins.
AECS5
AECS4
AEAW
Enable EMIFA EM_CS5 function on GPIO[8]
Enable EMIFA EM_CS4 function on GPIO[9]
EMIFA address width selection. Default value is latched at reset from AEAW[4:0]
configuration input pins. This enables EMIF address function on default GPIO[10:28]
pins.
3.5.5 PINMUX1 Register Description
The PINMUX1 pin multiplexing register controls which peripheral is given ownership over shared pins
among Timer, PLL, ASP, SPI, I2C, PWM, and UART peripherals. The register format is shown in
Figure 3-8 and bit field descriptions are given in Table 3-15. More details on the PINMUX1 pin muxing
fields are given in Section 3.5.6. A value of "1" enables the secondary or tertiary pin function.
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Figure 3-8. PINMUX1 Register(1)
31
19
18
17
16
Reserved
TIMIN
CLK1
CLK0
R-0000 0000 0000 0
R/W-0 R/W-0 R/W-0
15
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
ASP
Rsvd
SPI
I2C
PWM2 PWM1 PWM0 U2FLO UART2 UART1 UART0
R-0000 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) For proper DM6446 device operation, always write a value of '0' to RSV bit 9.
Table 3-15. PINMUX1 Register Description
Name
TIMIN
CLK1
CLK0
ASP
Description
Enable TIM_IN function on default GPIO[49] pin
Enable CLK_OUT1 function on default GPIO[49] pin
Enable CLK_OUT0 function on default GPIO[48] pin
Enable ASP function on default GPIO[29:34] pins
Enable SPI function on default GPIO[37,39:42] pins
Enable I2C function on default GPIO[43:44] pins
Enable PWM2 function on default GPIO[47] pin
Enable PWM1 function on default GPIO[46] pin
Enable PWM0 function on default GPIO[45] pin
SPI
I2C
PWM2
PWM1
PWM0
U2FLO
Enable UART2 flow control function on default VPFE
CI[5:4]/CCD_DATA[13:12] pins
UART2
Enable UART2 function on default VPFE CI[7:6]/CCD_DATA[15:14]
pins
UART1
UART0
Enable UART1 function on shared ATA (CF) DMACK, DMARQ pins
Enable UART0 function on default GPIO[35:36] pins
3.5.6 Pin Multiplexing Register Field Details
The bit fields for various pin multiplexing options within the PINMUX0 and PINMUX1 registers are
described in the following sections.
3.5.6.1 EMAC and GPIO3V Pin Multiplexing
The EMAC pin functions are selected as shown in Table 3-16. The functionality for each of the individual
pins affected by the PINMUX0 field settings is given in Table 3-17.
Table 3-16. EMAC and GPIO3V Pin Multiplexing Control
EMACEN
PIN FUNCTIONALITY SELECTED
0
1
GPIO3V
EMAC
Table 3-17. EMAC and GPIO3V Multiplexed Pins
GPIO
EMAC
TXEN
TXCLK
COL
GPIO3V[0]
GPIO3V[1]
GPIO3V[2]
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GPIO3V[3]
GPIO3V[4]
GPIO3V[5]
GPIO3V[6]
GPIO3V[7]
GPIO3V[8]
GPIO3V[9]
GPIO3V[10]
GPIO3V[11]
GPIO3V[12]
GPIO3V[13]
GPIO3V[14]
GPIO3V[15]
GPIO3V[16]
TXD[0]
TXD[1]
TXD[2]
TXD[3]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXCLK
RXDV
RXER
CRS
MDIO
MDCLK
3.5.6.2 VPFE (CCD), VPBE (LCD), and GPIO Pin Multiplexing
The CCD and LCD controllers in the VPSS require multiplex control bit settings for certain modes of
operation. Bits within the PinMux0 register, which select between the CCD or LCD control signal function
and GPIO, are summarized in Table 3-18.
Table 3-18. VPFE (CCD), VPBE (LCD), and GPIO Pin Multiplexing
PINMUX0 REGISTER FIELDS
MULTIPLEXED PINS
C_FIELD/
R0/
LCD_FIELD/
C_WE/
GPIO[1]
LCD_OE/
GPIO[0]
CFLDEN
LFLDEN
CWE
LOEEN
B0/
GPIO[4]
GPIO[3]
-
-
-
-
-
-
0
1
-
-
-
-
GPIO[0]
-
-
-
LCD_OE
-
-
0
1
-
-
-
GPIO[1]
-
-
-
-
-
-
-
-
-
-
-
C_WE
-
0
1
-
-
-
B0/GPIO[3](1)
-
-
-
-
-
-
-
-
LCD_FIELD
0
1
-
-
R0/GPIO[4](1)
C_FIELD
-
-
-
-
-
(1) Depends on RGB888 bit setting, see Table 3-19
3.5.6.3 VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing
Use of the RGB666 and RGB888 modes of the VPBE requires enabling RGB pins as shown in Table 3-19
and Table 3-20. Enabling PWM2, PWM1, CCD, and LCD functionality overrides the RGB modes. RGB666
interface pin functionality requires setting the RGB666 PINMUX0 Register bit field to ‘1’ and PINMUX1
Register bit fields PWM2 and PWM1 to ‘0’. Proper RGB888 interface operation requires setting PINMUX0
Register bit field RGB888 to ‘1’ and bit fields PWM2, PWM1, CFLDEN, and LFLDEN must be set to ‘0’.
Table 3-19. VPBE (RGB666, RGB888, and LCD), VPFE (CCD), and GPIO Pin Multiplexing
PINMUX0 AND PINMUX1 REGISTER BIT FIELDS
MULTIPLEXED PINS
PWM2/
B2/
PWM1/
R2/
C_FIELD/
R0/
LCD_FIELD/
B0/
RGB888 RGB666
PWM2
PWM1
CFLDEN LFLDEN
GPIO[47]
GPIO[46]
GPIO[4]
GPIO[3]
0
-
0
-
0
-
0
-
0
-
0
1
-
GPIO[47]
GPIO[46]
GPIO[4]
GPIO[3]
-
-
-
LCD_FIELD
-
-
-
-
1
-
-
-
C_FIELD
-
-
-
-
-
-
1
-
-
-
PWM1
-
-
-
-
-
1
-
-
PWM2
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0
1
1
-
0
0
0
0
0
0
0
0
B2
B2
R2
R2
GPIO[4]
R0
GPIO[3]
B0
Table 3-20. VPBE (RGB666, RGB888, and LCD) and GPIO Pin Multiplexing
PINMUX0 AND PINMUX1 REGISTER BIT FIELDS
MULTIPLEXED PINS
R1/
GPIO[38]
B1/
GPIO[6]
G1/
G0/
RGB888
PWM2
PWM1
CFLDEN
LFLDEN
GPIO[5]
GPIO[5]
G1
GPIO[2]
GPIO[2]
G0
0
1
0
0
0
0
0
0
0
0
GPIO[38]
R1
GPIO[6]
B1
3.5.6.4 ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing
The ATA peripheral shares pins with the EMIFA and UART1 as seen in Table 3-21. If ATA pin
functionality is enabled by setting the ATAEN bit field, the ATA module will drive the EMIFA data and
control pins. Enabling UART1 disables the use of the ATA DMARQ and DMACK signals and thus only
allows the ATA module to use PIO mode. The ATA HDDIR buffer direction control bit field works in
conjunction with the HDIREN enable bit field to allow the ATA pins to still be used as a GPIO or SPI_EN1
if the buffer is not being used (i.e. for Compact Flash). This multiplexing is shown in Table 3-22. When
ATAEN=0 and HDIREN=1 it indicates that the ATA interface has been disabled so that the EMIFA can be
used, but the ATA buffers are still present. HDDIR is driven low in this situation to ensure that the ATA
buffers drive away from DM644X and don’t cause bus contention with the EMIFA. Note that switching
between EMIFA and ATA (clearing or setting ATAEN) must be carefully performed to prevent bus
contention. Since the ATA device can be a bus master, software must ensure that all outstanding DMA
requests have completed before clearing the ATAEN bit.
Table 3-21. ATA, EMIFA, and GPIO Pin Multiplexing Control(1)
PINMUX0
REGISTER
BIT FIELD
MULTIPLEXED PINS
EM_BA[1]/
GPIO[52]/
ATA1
EM_A[0]/
GPIO[53]/
ATA2
EM_D[15:0]/
DD[15:0]
GPIO[50]/
ATA_CS0
GPIO[51]/
ATA_CS1
EM_R/W
INTRQ
EM_BA[0]/ EM_WAIT/
DIOR/
EM_OE
DIOW/
EM_WE
ATAEN
ATA0
IORDY
GPIO[50]
ATA_CS0
GPIO[51]
ATA_CS1
EM_R/W
INTRQ
EM_BA[0]
EM_WAIT
EM_OE
DIOR
EM_WE
DIOW
EM_BA[1]/
EM_A[0]/
EM_D[15:0]
DD[15:0]
0
1
GPIO[52](2) GPIO[53](2)
ATA0
IORDY
ATA1
ATA2
(1) This table assumes that the HPIEN bit in the PINMUX0 register is "0".
(2) This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9.
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Table 3-22. ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing
PINMUX0 AND PINMUX1 REGISTER BIT FIELDS
MULTIPLEXED PINS
SPI_EN1/
HDDIR/
GPIO[42]
UART_TXD1/
DMACK
UART_RXD1/
DMARQ
ATAEN
UART1
HDIREN
SPI
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
-
DMACK
DMACK
DMARQ
DMARQ
GPIO[42]
SPI_EN1
Driven Low
GPIO[42]
SPI_EN1
Driven Low
GPIO[42]x
SPI_EN1x
HDDIR
DMACK
DMARQ
0
1
-
UART_TXD1
UART_TXD1
UART_TXD1
DMACK
UART_RXD1
UART_RXD1
UART_RXD1
DMARQ
0
1
-
DMACK
DMARQ
DMACK
DMARQ
0
1
-
UART_TXD1
UART_TXD1
UART_TXD1
UART_RXD1
UART_RXD1
UART_RXD1
GPIO[42]x
SPI_EN1x
HDDIR
3.5.6.5 VLYNQ, EMIFA, and GPIO Pin Multiplexing
Table 3-23 and Table 3-24 show the VLYNQ pin control and multiplexing. If VLYNQ is disabled
(VLYNQEN=0), the AECS5 and AECS4 bits select between the GPIO[8] / EMIFA EM_CS5 and GPIO[9] /
EMIFA EM_CS4 functions, and the AEAW field determines the partitioning between GPIO and the upper
EMIFA address pins. If VLYNQ is enabled (VLYNQEN=1), VLYNQ_CLOCK, VLYNQ_TXD0, and
VLYNQ_RXD0 are always selected. The VLYNQ_SCRUN function is only enabled if VLYNQEN=1 and
VLSCREN=1 (VLSCREN overrides AECS4). The remaining VLYNQ TX/RX pins are selected based on
the VLYNQWD value. Unselected VLYNQ TX/RX pins will function as either GPIO or EMIFA address
based on the AEAW value.
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Table 3-23. VLYNQ Control, EMIFA, and GPIO Pin Multiplexing
PINMUX0 REGISTER BIT FIELDS
MULTIPLEXED PINS
EM_CS5/ EM_CS4/
VLYNQEN
VLSCREN
AECS5
AECS4
GPIO[8]/
GPIO[9]/
VLYNQ_CLOCK
VLYNQ_SCRUN
0
0
0
0
1
1
1
-
-
0
0
1
1
-
0
1
0
1
0
1
-
GPIO[8]
GPIO[8]
GPIO[9]
EM_CS4
-
EM_CS5
GPIO[9]
-
EM_CS5
EM_CS4
0
0
1
VLYNQ_CLOCK
VLYNQ_CLOCK
VLYNQ_CLOCK
GPIO[9]
-
EM_CS4
-
VLYNQ_SCRUN
Table 3-24. VLYNQ Data, EMIFA, and GPIO Pin Multiplexing
PINMUX0
REGISTER
BIT FIELDS
MULTIPLEXED PINS
EM_A[21]/
GPIO[10]/
VL_TXD0
EM_A[20]/
GPIO[11]/
VL_RXD0
EM_A[19]/
GPIO[12]/
VL_TXD1
EM_A[18]/
GPIO[13]/
VL_RXD1
EM_A[17]/
GPIO[14]/
VL_TXD2
EM_A[16]/
GPIO[15]/
VL_RXD2
EM_A[15]/
GPIO[16]/
VL_TXD3
EM_A[14]/
GPIO[17]/
VL_RXD3
VLYNQEN
VLYNQWD
EM_A[21]/
GPIO[10](1)
EM_A[20]/
GPIO[11](1)
EM_A[19]/
GPIO[12](1)
EM_A[18]/
GPIO[13](1)
EM_A[17]/
GPIO[14](1)
EM_A[16]/
GPIO[15](1)
EM_A[15]/
GPIO[16](1)
EM_A[14]/
GPIO[17](1)
0
1
1
-
VL_TXD0
VL_TXD0
VL_TXD0
VL_TXD0
VLRXD0
VLRXD0
VLRXD0
VLRXD0
EM_A[19]/
GPIO[12](1)
EM_A[18]/
GPIO[13](1)
EM_A[17]/
GPIO[14](1)
EM_A[16]/
GPIO[15](1)
EM_A[15]/
GPIO[16](1)
EM_A[14]/
GPIO[17](1)
00
01
VL_TXD1
VL_TXD1
VL_TXD1
VLRXD1
VLRXD1
VLRXD1
EM_A[17]/
GPIO[14](1)
EM_A[16]/
GPIO[15](1)
EM_A[15]/
GPIO[16](1)
EM_A[14]/
GPIO[17](1)
VL_TXD2
VLRXD2
EM_A[15]/
GPIO[16](1)
EM_A[14]/
GPIO[17](1)
1
1
10
11
VL_TXD2
VLRXD2
VL_TXD3
VLRXD3
(1) This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9.
3.5.6.6 Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing
The multiplexing of the CLK_OUT1 and Timer0 Input (Timer 0 only) functions is shown in Table 3-25.
Table 3-25. Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing
PINMUX1 REGISTER BIT FIELDS
MULTIPLEXED PINS
CLK_OUT1/
TIM_IN/
TIMIN
CLK1
GPIO[49]
0
0
1
0
1
-
GPIO[49]
CLK_OUT1
TIM_IN
3.5.6.7 ASP, SPI, I2C, ATA, and GPIO Pin Multiplexing
When the ASP, SPI, or I2C serial port functions are not selected, their pins may be used as GPIOs as
seen in Table 3-26, Table 3-27, and Table 3-28. The SPI_EN1 pin can also function as the HDDIR buffer
control when ATAEN is selected and the HDIREN bit is set.
Table 3-26. ASP and GPIO Pin Multiplexing
PINMUX1 REGISTER BIT FIELD
ASP
MULTIPLEXED PINS
CLKX/
GPIO[29]
CLKR/
GPIO[30]
FSX/
FSR/
DX/
GPIO[33]
DR/
GPIO[34]
GPIO[31]
GPIO[32]
GPIO[32]
FSR
0
1
GPIO[29]
CLKX
GPIO[30]
CLKR
GPIO[31]
FSX
GPIO[33]
DX
GPIO[34]
DR
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Table 3-27. SPI and GPIO Pin Multiplexing
PINMUX0 AND PINMUX1 REGISTER BIT FIELDS
MULTIPLEXED PINS
SP_EN1/
HDDIR/
SPI_DO/ SPI_DI/
SPI_CLK/
GPIO[39]
SPI_EN0/
GPIO[37]
SPI
ATAEN
HDIREN
GPIO[41]
GPIO[40]
GPIO[42]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
GPIO[42]
Driven Low
GPIO[42]
HDDIR
GPIO[41]
GPIO[41]
GPIO[41]
GPIO[41]
SPI_DO
SPI_DO
SPI_DO
SPI_DO
GPIO[40]
GPIO[40]
GPIO[40]
GPIO[40]
SPI_DI
GPIO[39]
GPIO[39]
GPIO[39]
GPIO[39]
SPI_CLK
SPI_CLK
SPI_CLK
SPI_CLK
GPIO[37]
GPIO[37]
GPIO[37]
GPIO[37]
SPI_EN0
SPI_EN0
SPI_EN0
SPI_EN0
SP_EN1
Driven Low
SP_EN1
HDDIR
SPI_DI
SPI_DI
SPI_DI
Table 3-28. I2C and GPIO Pin Multiplexing
PINMUX1 REGISTER
MULTIPLEXED PINS
BIT FIELD
I2C_CLK/
GPIO[43]
I2C_DATA/
I2C
GPIO[44]
GPIO[44]
I2C_DATA
0
1
GPIO[43]
I2C_CLK
3.5.6.8 PWM, RGB888, and GPIO Pin Multiplexing
Table 3-29 shows the PWM0/1/2 pin multiplexing. Each PWM output is independently controlled by its
own enable bit. The PWM function has priority over RGB888 muxing (see Section 3.5.6.3).
Table 3-29. PWM0/1/2, RGB888, and GPIO Pin Multiplexing
PINMUX1 REGISTER BIT FIELDS
MULTIPLEXED PINS
PWM2/
B2/
PWM1/
R2/
PWM0/
GPIO[45]
PWM2
PWM1
PWM0
RGB888
GPIO[47]
GPIO[46]
0
0
-
0
0
-
0
0
1
-
0
1
-
GPIO[47]
GPIO[46]
GPIO[45]
B2
R2
GPIO[45]
-
-
PWM0
-
1
-
-
-
PWM1
-
-
-
1
-
-
PWM2
3.5.6.9 UART, VPFE, ATA, and GPIO Pin Multiplexing
Each UART has independent pin multiplexing control bits in the PINMUX1 register. The UART2 peripheral
may be used with or without the flow control signals. Table 3-30 shows how UART2 selection reduces the
width of the VPFE interface.
Setting the UART1 bit enables UART1 transmit and receive pin functionality. Since these are shared with
the ATA DMA handshake signals, enabling UART1 effectively disables the ATA DMA mode. However,
ATA PIO mode is still supported with UART1 enabled. This is shown in Table 3-31. If the ATA module is
not enabled, the pins are always configured for use by UART1.
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Table 3-30. UART2, VPFE, and GPIO Pin Multiplexing
PINMUX1 REGISTER
BIT FIELDS
MULTIPLEXED PINS
CCD[15]/
CI[7]/
CCD[14]/
CI[6]/
CCD[13]/
CI[5]/
CCD[12]/
CI[4]/
UART2
U2FLO
UART_RXD2
UART_TXD2
UART_CTS2
UART_RTS2
CCD[15]/
CI[7](1)
CCD[14]/
CI[6](1)
CCD[13]/
CI[5](1)
CCD[12]/
CI[4](1)
0
-
UART_RXD2
UART_TXD2
CCD[13]/
CI[5](1)
CCD[12]/
CI[4](1)
1
1
0
1
UART_RXD2
UART_TXD2
UART_CTS2
UART_RTS2
(1) Functionality set by VPFE operating mode.
Table 3-31. UART1 and ATA Pin Multiplexing
PINMUX0 AND PINMUX1 REGISTER
BIT FIELDS
MULTIPLEXED PINS
UART_TXD1/ UART_RXD1/
ATAEN
UART1
DMACK
UART_TXD1
DMACK
DMARQ
UART_RXD1
DMARQ
0
1
1
-
0
1
UART_TXD1
UART_RXD1
As Table 3-32 shows, the UART0 pins are configurable for either UART0 transmit and receive data
functions or for GPIO.
Table 3-32. UART0 and GPIO Pin Multiplexing
PINMUX1 REGISTER BIT
MULTIPLEXED PINS
FIELD
UART_TXD0/
GPIO[36]
UART_RXD0/
GPIO[35]
UART0
0
1
GPIO[36]
GPIO[35]
UART_TXD0
UART_RXD0
3.5.6.10 HPI and EMIFA/ATA Pin Multiplexing
When the HPIEN bit is set, the HPI module is given control of most of the EMIFA/ATA control pins as well
as the EMIFA/ATA data bus. Table 3-33 shows which pins the HPI controls. HPIEN is set to 1 when the
state of the BTSEL[1:0] pins = 10 is latched at the rising edge of reset. Also, this bit can be manipulated
after reset by software. When the ATAEN bit is set and HPIEN is 0, the ATA mode of operation for pins
shared with the HPI is available. EMIFA mode functionality for the shared HPI pins is set when both
HPIEN and ATAEN are '0'.
Table 3-33. HPI and EMIFA/ATA Pin Multiplexing
PINMUX0
REGISTER
BIT FIELDS
MULTIPLEXED PINS
HR/W/
INTRQ/
EM_R/W
HRDY/
EM_WAIT/
IORDY
HDS1/
DIOR/
EM_OE
HDS2/
DIOW/
EM_WE
HCNTLB/
ATA2/
EM_A[0]
HINT/
ATA0/
EM_BA[0]
HD[15:0]/
DD[15:0]/
EM_D[15:0]
HPI
EN
ATA
EN
HCS/
EM_CS2
HHWIL/
EM_A[1]
HCNTLA/
EM_A[2]
0
0
1
0
1
-
EM_CS2
EM_CS2
HCS
EM_A[1](1)
EM_A[1](1)
HHWIL
EM_R/W
INTRQ
HR/W
EM_WAIT
IORDY
EM_OE
DIOR
EM_WE
DIOW
EM_A[2](1)
EM_A[2](1)
HCNTLA
EM_A[0](1)
EM_A[0](1)
HCNTLB
EM_BA[0]
ATA0
EM_D[15:0]
DD[15:0]
HRDY
HDS1
HDS2
HINT
HD[15:0]
(1) This pin shares GPIO functionality and is set by AEAW[4:0] as shown in Table 3-12, Table 3-13, and Table 3-14.
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3.6 Emulation Control
The flexibility of the DM644x architecture allows either the ARM or DSP to control the various peripherals
(setup registers, service interrupts, etc.). While this assignment is purely a matter of software convention,
during an emulation halt it is necessary for the device to know which peripherals are associated with the
halting processor so that only those modules receive the suspend signal. This allows peripherals
associated with the other (unhalted) processor to continue normal operation. The SUSPSRC register
indicates the emulation suspend source for those peripherals which support emulation suspend. The
SUSPSRC register format is shown in Figure 3-9. Brief details on the peripherals which correspond to the
register bits is given in Table 3-34. When the associated SUSPSRC bit is ‘0’, the peripheral’s emulation
suspend signal is controlled by the ARM emulator and when set to ‘1’ it is controlled by the DSP emulator.
Figure 3-9. Emulation Suspend Source Register (SUSPSRC)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VICP
SRC
VICP
EN
TIMR2 TIMR1 TIMR0
SRC SRC SRC
GPIO
SRC
PWM2 PWM1 PWM0
SRC SRC SRC
SPI
SRC
UART2 UART1 UART0
SRC SRC SRC
I2C
SRC
ASP
SRC
Rsvd
R-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HPI
SRC
USB
SRC
EMAC
SRC
Rsvd
Rsvd
R-00
Rsvd
R-000
Reserved
R-0 0000
R-000
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Table 3-34. SUSPSRC Register Description
Name
Description
VICPSRC
Video Imaging Coprocessor emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
VICPEN
Video Imaging Coprocessor emulation suspend enable
0 = Emulation suspend ignored by VICP
1 = VICP emulation suspend enabled
TIMR2SRC
TIMR1SRC
TIMR0SRC
GPIOSRC
PWM2SRC
PWM1SRC
PWM0 SRC
SPISRC
Timer2 (WD Timer) emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
Timer1 emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
Timer0 emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
GPIO emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
PWM2 emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
PWM1 emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
PWM0 emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
SPI emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
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Table 3-34. SUSPSRC Register Description (continued)
Name
Description
UART2SRC
UART2 emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
UART1SRC
UART0SRC
I2CSRC
UART1 emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
UART0 emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
I2C emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
ASPSRC
HPISRC
ASP emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
HPI emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
USBSRC
EMACSRC
USB emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
Ethernet MAC emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
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4 System Interconnect
On the DM6446 device, the C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers,
and the system peripherals are interconnected through a switch fabric architecture (shown in Figure 4-1).
The switch fabric is composed of multiple switched central resources (SCRs) and multiple bridges. The
SCRs establish low-latency connectivity between master peripherals and slave peripherals. Additionally,
the SCRs provide priority-based arbitration and facilitate concurrent data movement between master and
slave peripherals. Through SCR, the ARM subsystem can send data to the DDR2 Memory Controller
without affecting a data transfer between the EMAC and L2 memory. Bridges are mainly used to perform
bus-width conversion as well as bus operating frequency conversion. For example, in Figure 4-1, Bridge 8
performs a frequency conversion between a bus operating at DSP/6 clock rate and a bus operating at
DSP/3 clock rate. Furthermore, Bridge 3 performs a bus-width conversion between a 64-bit bus and a
32-bit bus.
The C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, and the various system
peripherals can be classified into two categories: master peripherals and slave peripherals. Master
peripherals are typically capable of initiating read and write transfers in the system and do not rely on the
EDMA3 or on a CPU to perform transfers to and from them. The system master peripherals include the
C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, CF/ATA, VLYNQ, EMAC, USB,
and VPSS. Not all master peripherals may connect to all slave peripherals. The supported connections
are designated by an X in Table 4-1.
Table 4-1. System Connection Matrix
SLAVE
MASTER
C64x+
ARM
DDR2 MEMORY CONTROLLER
SCR3(1)
C64x+
ARM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VPSS
CF/ATA
VLYNQ
EMAC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
USB
X
EDMA3TC0
EDMA3TC1
HPI
X
X
X(2)
(1) The C64x+ megamodule has access to only the following peripherals connected to SCR3: EDMA3, ASP, and Timers. All other
peripherals/modules that support a connection to SCR3 have access to all peripherals/modules connected to SCR3.
(2) HPI's access to SCR3 is limited to the power and sleep controller registers, PLL1 and PLL2 registers, and HPI configuration registers.
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4.1 System Interconnect Block Diagram
Figure 4-1 displays the DM6446 system interconnect block diagram. The following is a list that helps
interpret this diagram:
•
•
•
The direction of the arrows indicates either bus master or bus slave.
The arrow originates at a bus master and terminates at a bus slave.
The direction of the arrows does not indicate the direction of data flow. Data flow is typically
bi-directional for each of the documented bus paths.
•
•
The pattern of each arrow's line indicates the clock rate at which it is operating, either DSP/2, DSP/3,
or DSP/6 clock rate.
Some peripherals may have multiple instances shown in the diagram. A peripheral may have multiple
instances shown for a variety of reasons, some of which are described below:
–
The peripheral/module has master port(s) for data transfers, as well as slave port(s) for register
access, data access, and/or memory access. Examples of these peripherals are C64x+
megamodule, EDMA3, CF/ATA, USB, EMAC, VPSS, VLYNQ, and HPI.
–
The peripheral/module has a master port as well as slave memories. Examples of these are the
C64x+ megamodule and the ARM subsystem.
32
DSP/2 Clock Rate
CF/ATA
VLYNQ
EMAC
USB 2.0
HPI
32
DSP/3 Clock Rate
64
DDR2 Ctrl
(Mem/Reg)
32
32
32
32
64
DSP/6 Clock Rate
MXI/CLKIN Rate
SCR5
Bridge2
64
64
VPSS
64
Read
EDMA3CC
EDMA3TC0
EDMA3TC1
C64x+
L2/L1
32
32
32
32
32
EDMA3TC0
EDMA3TC1
Write
Read
Write
64
64
64
Bridge8
Bridge9
SCR4
SCR1
32
32
64
32
32
ARM
TCM
UART0
UART1
UART2
I2C
Bridge3
32
32
L2 Cache
CF/ATA Reg
32
32
32
32
USB Reg
EMAC Reg
128
32
32
64
64
HPI
64
64
PWM0
PWM1
PWM2
Timer 0
Timer 1
Timer 2
Bridge5
Bridge6
32
32
32
SCR8
EMAC Ctrl Mod Reg
C64x+
32
32
EMAC Ctrl Mod RAM
MDIO
32
32
32
32
32
32
256
32
32
32
32
VPSS Reg
SPI 0/1
SCR6
32
32
GPIO
VICP
SCR3
32
32
AINTC
ASP
VLYNQ
System Reg
PSC
32
32
32
SCR7
Bridge1
Bridge7
32
32
32
32
PLLC 0
MMC/SD
EMIFA/NAND
ARM
SCR2
PLLC 1
32
32
32
Figure 4-1. System Interconnect Block Diagram
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Case Temperature Range
(1)
(Unless Otherwise Noted)
(3)
Core (CVDD, VDDA1P1V, USB_VDDA1P2LDO(2), CVDDDSP
)
-0.5 V to 1.5 V
-0.5 V to 4.2 V
-0.5 V to 2.5 V
(3)
I/O, 3.3V (DVDD33, USB_VDDA3P3
)
Supply voltage ranges
I/O, 1.8V (DVDD18, DVDDR2, DDR_VDDDLL, PLLVDD18, VDDA1P8V
,
(3)
USB_VDD1P8, MXVDD, M24VDD
)
VI I/O, 3.3V
-0.5 V to 4.2 V
-0.5 V to 2.5 V
-0.5 V to 4.2 V
-0.5 V to 2.5 V
-40°C to 105°C
-55°C to 150°C
Input voltage ranges
Output voltage ranges
VI I/O, 1.8V
VO I/O, 3.3V
VO I/O, 1.8V
Operating case temperature ranges, TC
Storage temperature range, Tstg
(default)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This pin is an internal LDO output and connected via 1 µF capacitor to USB_VSSA1P2LDO
(3) All voltage values are with respect to VSS.
.
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5.2 Recommended Operating Conditions
MIN
1.14
3.15
1.71
NOM
1.2
MAX UNIT
(1)
Supply voltage, Core (CVDD, VDDA1P1V, USB_VDDA1P2LDO
,
CVDD
1.26
3.45
1.89
V
V
V
(2)
CVDDDSP
)
Supply voltage, I/O, 3.3V (DVDD33, USB_DVDDA3P3
)
3.3
DVDD
Supply voltage, I/O, 1.8V (DVDD18, DVDDR2, DDR_VDDDLL
,
1.8
PLLVDD18, VDDA1P8V, USB_VDD1P8, MXVDD, M24VDD
)
Supply ground (VSS, VSSA1P8V, VSSA1P1V, DDR_VSSDLL
,
VSS
USB_VSSREF, USB_VSS1P8, USB_VSSA3P3, USB_VSSA1P2LDO
,
0
0
0
V
(3)
MXVSS(3), M24VSS
)
DDR_VREF
DDR_ZP
DDR2 reference voltage(4)
0.49DVDDR2
0.5DVDDR2
VSS
0.51DVDDR2
V
V
DDR2 impedance control, connected via 200 Ω resistor to VSS
DDR2 impedance control, connected via 200 Ω resistor to
DVDDR2
DDR_ZN
DVDDR2
V
DAC_VREF
DAC_RBIAS
USB_VBUS
DAC reference voltage input
0.475
0.5
VSSA_1P8V
5
0.525
5.25
V
V
DAC biasing, connected via 4 kΩ resistor to VSSA_1P8V
USB external charge pump input
4.75
2
V
High-level input voltage, I/O, 3.3V
V
VIH
VIL
High-level input voltage, non-DDR I/O, 1.8V
Low-level input voltage, I/O, 3.3V
0.65DVDD
V
0.8
0.35DVDD
105
V
Low-level input voltage, non-DDR I/O, 1.8V
Operating case temperature
V
TC
-40
20
°C
MHz
FSYSCLK1
DSP Operating Frequency (SYSCLK1)
594
(1) This pin is an internal LDO output and connected via 1 µF capacitor to USB_VSSA1P2LDO
.
(2) Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance
options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,
1.1 V, 1.14 V, 1.2, 1.26 V with ±3% tolerances) by implementing simple board changes such as reference resistor values or input pin
configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SOC
devices.
(3) Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground.
(4) DDR_VREF is expected to equal 0.5DVDDR2 of the transmitting device and to track variations in the DVDDR2
.
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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Low/full speed:
USB_DN and USB_DP
2.8
USB_VDDAP3
V
High speed:
USB_DN and USB_DP
360
440
mV
VOH
High-level output voltage (3.3V I/O)
High-level output voltage (1.8V I/O)
DVDD33 = MIN, IOH = MAX
DVDD18 = MIN, IOH = MAX
2.4
V
V
DVDD - 0.45
Low/full speed:
USB_DN and USB_DP
0.0
-10
0.3
10
V
High speed:
USB_DN and USB_DP
mV
VOL
Low-level output voltage (3.3V I/O)
Low-level output voltage (1.8V I/O)
DVDD33 = MIN, IOL = MAX
DVDD18 = MIN, IOL = MAX
0.4
V
V
0.45
VI = VSS to DVDD without opposing
internal resistor
±10
250
-50
µA
µA
µA
VI = VSS to DVDD with opposing internal
(2)
II
Input current
50
100
(3)
pullup resistor
VI = VSS to DVDD with opposing internal
-250
-100
(3)
pulldown resistor
IOH
IOL
High-level output current
Low-level output current
All peripherals
-4 mA
All peripherals
4
mA
µA
µA
VO = DVDD or VSS; internal pull disabled
VO = DVDD or VSS; internal pull enabled
±20
(4)
IOZ
I/O Off-state output current
±100
(5)
Core (CVDD, VDDA1P1V, VDDA1P2LDO
CVDDDSP) supply current(6)
,
ICDD
IDDD
CVDD = 1.2 V, DSP clock = 594 MHz
DVDD = 3.3 V, DSP clock = 594 MHz
767
mA
mA
3.3V I/O (DVDD33, USB_VDDA3P3) supply
current(6)
6
1.8V I/O (DVDD18, DVDDR2, DDR_VDDDLL
,
IDDD
PLLVDD18, VDDA1P8V, USB_VDD1P8, MXVDD, DVDD = 1.8 V, DSP clock = 594 MHz
102
mA
M24VDD) supply current(6)
CI
Input capacitance
Output capacitance
4
4
pF
pF
Co
(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(2) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(4) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(5) This pin is an internal LDO output and connected via 1 µF capacitor to USB_VSSA1P2LDO
.
(6) Measured under the following conditions: 60% DSP CPU utilization; ARM doing typical activity (peripheral configurations, other
housekeeping activities); DDR2 Memory Controller at 50% utilization (135 MHz), 50% writes, 32 bits, 50% bit switching; 2 MHz ASP at
100% utilization; Timer0 at 100% utilization. At room temperature (25 °C) for typical process devices. The actual current draw varies
across manufacturing processes and is highly application-dependent. For more details on core and I/O activity, as well as information
relevant to board power supply design, see the TMS320DM644x Power Consumption Summary application report (literature number
SPRAAD6).
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6 Peripheral and Electrical Specifications
6.1 Parameter Information
6.1.1 Parameter Information Device-Specific Information
Tester Pin Electronics
Data Manual Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data manual provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the
data manual timings.
Input requirements in this data manual are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1.1 Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.5 V. For 1.8 V I/O, Vref = 0.9 V.
V
ref
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
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6.1.1.2 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
For the DDR2 memory controller interface, it is not necessary to use the IBIS models to analyze timing
characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the
DDR2 memory controller interface timings are met. See the Implementing DDR2 PCB Layout on the
TMS320DM644x DMSoC Application Report (literature number SPRAAC5).
6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals should transition between VIH and VIL (or between VIL and VIH) in a
monotonic manner.
6.3 Power Supplies
For more information regarding TI's power management products and suggested devices to power TI
DSPs, visit www.ti.com/dsppower.
6.3.1 Power-Supply Sequencing
The DM6446 includes two core supplies — CVDD and CVDDDSP, as well as three I/O supplies — DVDD18
,
DVDDR2, and DVDD33. To ensure proper device operation, a specific power-up sequence must be followed.
The core supply power-up sequence is dependent on the DSP boot mode selected at reset. If the DSP
boot mode is configured as Self-Boot mode, then both core supplies must be powered up at the same
time.
If the DSP boot mode is configured as Host-Boot, where the ARM boots the DSP, the two core supplies
may be ramped simultaneously or powered up separately. When powered up separately, the CVDDDSP
supply must not be ramped prior to the CVDD supply. The CVDDDSP supply must be powered up before the
shorting switch is closed (enabled). Prior to powering up the CVDDDSP supply, it should be left floating and
not driven to ground. Table 6-1 and Figure 6-4 describe the power-on sequence timing requirements for
DSP Host-Boot mode.
To minimize the voltage difference between these two core supplies, a single regulator source must be
used to power the CVDD and CVDDDSP supplies.
For more information, see Section 3.2.1, Power Considerations at Reset.
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Table 6-1. Core Supply Power-On Timing Requirements for DSP Host-Boot Mode (see Figure 6-4)
NO.
MIN
MAX
UNIT
(1)
1
td(CVDD-CVDDDSP)
Delay time, CVDD supply ready to CVDDDSP supply ramp start
0
ns
(1) In Host-Boot mode, the CVDDDSP supply must be powered up prior to closing (enabling) the shorting switch between the ALWAYS ON
and DSP power domains.
CVDD
CVDDDSP
Figure 6-4. DSP Host-Boot Mode Core Supply Timings
Once the CVDD supply has been powered up, the I/O supplies may be powered up. Table 6-2 and
Figure 6-5 show the power-on sequence timing requirements for the Core vs. I/O power-up. DVDDXX is
used to denote all I/O supplies. Note: the DVDDXX supply power-up is specified relative to the CVDD supply
power-up, not the CVDDDSP supply.
Table 6-2. I/O Supply Power-On Timing Requirements (see Figure 6-5)
NO.
MIN
MAX
UNIT
1
td(CVDD-DVDD)
Delay time, CVDD supply ready to DVDDXX supply ramp start
0
100
ms
CVDD
(A)
DVDDXX
Note A: DVDDXX denotes all I/O supplies.
Figure 6-5. I/O Supply Timings
There is not a specific power-up sequence that must be followed with respect to the order of the power-up
of the DVDD18, DVDDR2, and DVDD33 supplies. Once the CVDD supply is powered up and the td(CVDD-DVDDXX)
specification is met, the DVDD18, DVDDR2, and DVDD33 supplies may be powered up in any order of
preference. All other supplies may also be powered up in any order of preference once the td(CVDD-DVDDXX)
specification has been met.
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6.3.1.1 Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the DM6446 device, the PC board should include separate power planes for core,
I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
6.3.1.2 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to DM6446. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for
the core supplies and 30 for the I/O supplies. These caps need to be close to the DM6446 power pins, no
more than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better
because of their lower parasitic inductance. Proper capacitance values are also important. Small bypass
caps (near 560 pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can
be obtained in a small package) should be next closest. TI recommends no less than 8 small and
8 medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space
and at least the corners of the "exterior".
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 100 µF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of
any component, verification of capacitor availability over the product’s production lifetime should be
considered.
6.3.1.3 DM6446 Power and Clock Domains
DM6446 includes two separate power domains: "Always On" and "DSP". The "Always On" power domain
is always on when the chip is on. The "Always On" domain is powered by the VDD pins of the DM6446.
The majority of the DM6446's modules lie within the "Always On" power domain. A separate domain called
the "DSP" domain houses the C64x+ and VICP. The "DSP" domain is not always on. The "DSP" power
domain is powered by the CVDDDSP pins of the DM6446. Table 6-3 provides a listing of the DM6446 power
and clock domains.
Two primary reference clocks are required for the DM6446 device. These can either be crystal input or
driven by external oscillators. A 27-MHz crystal is recommended for the system PLLs, which generate the
internal clocks for the ARM, DSP, coprocessors, peripherals (including imaging peripherals), and EDMA3.
The recommended 27-MHz input enables the use of the video DACs to drive NTSC/PAL television signals
at the proper frequencies. A 24-MHz crystal is also required if the USB peripheral is to be used. For
further description of the DM6446 clock domains, see Table 6-4 and Figure 6-6.
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Table 6-3. DM6446 Power and Clock Domains
POWER DOMAIN
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
DSP
CLOCK DOMAIN
CLKIN
PERIPHERAL/MODULE
UART0
UART1
UART2
I2C
CLKIN
CLKIN
CLKIN
CLKIN
Timer0
Timer1
Timer2
PWM0
PWM1
PWM2
ARM Subsystem
DDR2
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKDIV2
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV1
VPSS
EDMA
SCR
GPSC
LPSCs
Ice Pick
EMIFA
USB
HPI
VLYNQ
EMAC
ATA/CF
MMC/SD/SDIO
SPI
ASP
GPIO
C64x+ CPU
Table 6-4. DM6446 Clock Domains(1)
CLOCK MODES (FREQUENCY)
SUBSYSTEM
FIXED RATIO vs. PLL1
PLL BYPASS
27 MHz
PLL ENABLED
PLL1
DSP
ARM
–
594 MHz
594 MHz
297 MHz
198 MHz
99 MHz
1:1
1:2
1:3
1:6
27 MHz
13.5 MHz
9 MHz
EDMA3/VPSS
Peripherals
4.5 MHz
(1) These table values assume a MXI/CLKIN of 27 MHz and a PLL1 multiplier equal to 22.
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Bypass Clock
PLLDIV1 (/1)
27 MHz
UARTs (x3)
I2C
SYSCLK1
SYSCLK2
DSP Subsystem
ARM Subsystem
VICP
PWMs (x3)
Timers (x3)
PLLDIV2 (/2)
PLLDIV4 (/4)
SYSCLK5
SYSCLK3
PLLDIV5 (/6)
USB PHY
60 MHz
24 MHz
PLLDIV3 (/3)
SCR
USB 2.0
VLYNQ
EMAC
PLL Controller 1
EDMA
VPFE
VPBE
PCLK
ATA/CF
EMIF/NAND
MMC/SD
SPI
VPBECLK
DACs
PLLDIV1 (/1)
PLLDIV2 (/2)
ASP
DDR2 PHY
GPIO
BPDIV
DDR2 VTP
PLL Controller 2
DDR2 Mem Ctlr
HPI
ARM INTC
Figure 6-6. PLL1 and PLL2 Clock Domain Block Diagram
For further detail on PLL1 and PLL2, see the structure block diagrams Figure 6-7 and Figure 6-8,
respectively.
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CLKMODE
PLLDIV1 (/1)
PLLDIV2 (/2)
PLLDIV3 (/3)
PLLDIV4 (/4)
PLLDIV5 (/6)
SYSCLK1
PLLEN
CLKIN
OSCIN
1
0
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
PLL
Post−DIV
1
0
PLLM
AUXCLK
BPDIV
SYSCLKBP
Figure 6-7. PLL1 Structure Block Diagram
CLKMODE
PLLEN
CLKIN
OSCIN
1
0
PLL2_SYSCLK1
(VPSS−VPBE)
Post−Div
PLLDIV1
PLL
1
0
(/1)
PLL2_SYSCLK2
(DDR2 PHY)
PLLDIV2
PLLM
PLL2_SYSCLKBP
(DDR2 VTP)
BPDIV
Figure 6-8. PLL2 Structure Block Diagram
6.3.1.4 Power and Sleep Controller (PSC) Module
The Power and Sleep Controller (PSC) controls DM6446 device power by turning off unused power
domains or gating off clocks to individual peripherals/modules. The PSC consists of a Global PSC (GPSC)
and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, power domain control,
PSC interrupt control, and a state machine for each peripheral/module. An LPSC is associated with each
peripheral/module and provides clock and reset control. The GPSC controls all of DM6446’s LPSCs. The
ARM subsystem does not have an LPSC module. ARM sleep mode is accomplished through the wait for
interrupt instruction. The LPSCs for DM6446 are shown in Table 6-5. The PSC register memory map is
given in Table 6-6. For more details on the PSC, see the Documentation Support section of the
TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).
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Table 6-5. DM6446 LPSC Assignments
LPSC
PERIPHERAL/MODULE
LPSC
PERIPHERAL/MODULE
LPSC
PERIPHERAL/MODULE
NUMBER
NUMBER
NUMBER
0
1
VPSS DMA
VPSS MMR
EDMACC
14
15
16
17
18
19
20
21
22
23
24
25
26
27
EMIFA
MMC/SD/SDIO
Reserved
ASP
28
TIMER1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
C64x+ CPU
VICP
29
2
30
3
EDMATC0
EDMATC1
EMAC
31
4
I2C
32
5
UART0
UART1
UART2
SPI
33
6
EMAC Memory Controller
MDIO
34
7
35
8
Reserved
36
9
USB
PWM0
PWM1
PWM2
GPIO
37
10
11
12
13
ATA/CF
38
VLYNQ
39
HPI
40
DDR2 Memory Controller
TIMER0
Table 6-6. PSC Register Memory Map
REGISTER
ACRONYM
HEX ADDRESS RANGE
DESCRIPTION
0x01C4 1000
0x01C4 1003 - 0x01C4 101F
0x01C4 1010
PID
Peripheral Revision and Class Information Register
Reserved
-
GBLCTL
Global Control Register
Reserved
0x01C4 1014
-
0x01C4 1018
INTEVAL
Interrupt Evaluation Register
Reserved
0x01C4 101C - 0x01C4 103F
0x01C4 1040
-
MERRPR0
Module Error Pending 0 (mod 0 - 31) Register
Module Error Pending 1 (mod 32- 63) Register
Reserved
0x01C4 1044
MERRPR1
0x01C4 1048 - 0x01C4 104F
0x01C4 1050
-
MERRCR0
Module Error Clear 0 (mod 0 - 31) Register
Module Error Clear 1 (mod 32 - 63) Register
Reserved
0x01C4 1054
MERRCR1
0x01C4 1058 - 0x01C4 105F
0x01C4 1060
-
PERRPR
Power Error Pending Register
Reserved
0x01C4 1064 - 0x01C4 1067
0x01C4 1068
-
PERRCR
Power Error Clear Register
Reserved
0x01C4 106C - 0x01C4 106F
0x01C4 1070
-
EPCPR
External Power Error Pending Register
Reserved
0x01C4 1074 - 0x01C4 1077
0x01C4 1078
-
EPCCR
External Power Control Clear Register
Reserved
0x01C4 107C - 0x01C4 10FF
0x01C4 1100
-
RAILSTAT
Power Rail Status Register
Power Rail Control Register
Power Rail Counter Select Register
Reserved
0x01C4 1104
RAILCTL
0x01C4 1108
RAILSEL
0x01C4 110C - 0x01C4 111F
0x01C4 1120
-
PTCMD
Power Domain Transition Command Register
Reserved
0x01C4 1124 - 0x01C4 1127
0x01C4 1128
-
PTSTAT
-
Power Domain Transition Status Register
Reserved
0x01C4 112C - 0x01C4 11FF
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Table 6-6. PSC Register Memory Map (continued)
REGISTER
ACRONYM
HEX ADDRESS RANGE
DESCRIPTION
0x01C4 1200
0x01C4 1204
PDSTAT0
PDSTAT1
-
Power Domain Status 0 Register (Always On)
Power Domain Status 1 Register (DSP)
Reserved
0x01C4 1208 - 0x01C4 12FF
0x01C4 1300
PDCTL0
PDCTL1
-
Power Domain Control 0 Register (Always On)
Power Domain Control 1 Register (DSP)
Reserved
0x01C4 1304
0x01C4 1308 - 0x01C4 150F
0x01C4 1510
MCKOUT0
MCKOUT1
-
Module Clock Output Status (mod 0-31) Register
Module Clock Output Status (mod 32-63) Register
Reserved
0x01C4 1514
0x01C4 1518 - 0x01C4 15FF
0x01C4 1600
MDCFG0
MDCFG1
MDCFG2
MDCFG3
MDCFG4
MDCFG5
MDCFG6
MDCFG7
Module Configuration 0 Register (VPSS DMA)
Module Configuration 1 Register (VPSS MMR)
Module Configuration 2 Register (EDMACC)
Module Configuration 3 Register (EDMATC0)
Module Configuration 4 Register (EDMATC1)
Module Configuration 5 Register (EMAC)
Module Configuration 6 Register (EMAC Memory Controller)
Module Configuration 7 Register (MDIO)
Reserved
0x01C4 1604
0x01C4 1608
0x01C4 160C
0x01C4 1610
0x01C4 1614
0x01C4 1618
0x01C4 161C
0x01C4 1620
0x01C4 1624
MDCFG9
MDCFG10
MDCFG11
MDCFG12
MDCFG13
MDCFG14
MDCFG15
Module Configuration 9 Register (USB)
Module Configuration 10 Register (ATA/CF)
Module Configuration 11 Register (VLYNQ)
Module Configuration 12 Register (HPI)
Module Configuration 13 Register (DDR2)
Module Configuration 14 Register (EMIFA)
Module Configuration 15 Register (MMC/SD/SDIO)
Reserved
0x01C4 1628
0x01C4 162C
0x01C4 1630
0x01C4 1634
0x01C4 1638
0x01C4 163C
0x01C4 1640
0x01C4 1644
MDCFG17
MDCFG18
MDCFG19
MDCFG20
MDCFG21
MDCFG22
MDCFG23
MDCFG24
MDCFG25
MDCFG26
MDCFG27
MDCFG28
-
Module Configuration 17 Register (ASP)
Module Configuration 18 Register (I2C)
Module Configuration 19 Register (UART0)
Module Configuration 20 Register (UART1)
Module Configuration 21 Register (UART2)
Module Configuration 22 Register (SPI)
Module Configuration 23 Register (PWM0)
Module Configuration 24 Register (PWM1)
Module Configuration 25 Register (PWM2)
Module Configuration 26 Register (GPIO)
Module Configuration 27 Register (TIMER0)
Module Configuration 28 Register (TIMER1)
Reserved
0x01C4 1648
0x01C4 164C
0x01C4 1650
0x01C4 1654
0x01C4 1658
0x01C4 165C
0x01C4 1660
0x01C4 1664
0x01C4 1668
0x01C4 166C
0x01C4 1670
0x01C4 1674 - 0x01C4 169B
0x01C4 169C
MDCFG39
MDCFG40
-
Module Configuration 39 Register (C64x+ CPU)
Module Configuration 40 Register (VICP)
Reserved
0x01C4 16A0
0x01C4 16A4 - 0x01C4 17FF
0x01C4 1800
MDSTAT0
MDSTAT1
MDSTAT2
MDSTAT3
Module Status 0 Register (VPSS DMA)
Module Status 1 Register (VPSS MMR)
Module Status 2 Register (EDMACC)
Module Status 3 Register (EDMATC0)
0x01C4 1804
0x01C4 1808
0x01C4 180C
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Table 6-6. PSC Register Memory Map (continued)
REGISTER
ACRONYM
HEX ADDRESS RANGE
DESCRIPTION
0x01C4 1810
0x01C4 1814
0x01C4 1818
0x01C4 181C
0x01C4 1820
0x01C4 1824
0x01C4 1828
0x01C4 182C
0x01C4 1830
0x01C4 1834
0x01C4 1838
0x01C4 183C
0x01C4 1840
0x01C4 1844
0x01C4 1848
0x01C4 184C
0x01C4 1850
0x01C4 1854
0x01C4 1858
0x01C4 185C
0x01C4 1860
0x01C4 1864
0x01C4 1868
0x01C4 186C
0x01C4 1870
0x01C4 1874 - 0x01C4 189B
0x01C4 189C
0x01C4 18A0
0x01C4 18A4 - 0x01C4 19FF
0x01C4 1A00
0x01C4 1A04
0x01C4 1A08
0x01C4 1A0C
0x01C4 1A10
0x01C4 1A14
0x01C4 1A18
0x01C4 1A1C
0x01C4 1A20
0x01C4 1A24
0x01C4 1A28
0x01C4 1A2C
0x01C4 1A30
0x01C4 1A34
0x01C4 1A38
0x01C4 1A3C
0x01C4 1A40
MDSTAT4
MDSTAT5
MDSTAT6
MDSTAT7
Module Status 4 Register (EDMATC1)
Module Status 5 Register (EMAC)
Module Status 6 Register (EMAC Memory Controller)
Module Status 7 Register (MDIO)
Reserved
MDSTAT9
MDSTAT10
MDSTAT11
MDSTAT12
MDSTAT13
MDSTAT14
MDSTAT15
Module Status 9 Register (USB)
Module Status 10 Register (ATA/CF)
Module Status 11 Register (VLYNQ)
Module Status 12 Register (HPI)
Module Status 13 Register (DDR2)
Module Status 14 Register (EMIFA)
Module Status 15 Register (MMC/SD/SDIO)
Reserved
MDSTAT17
MDSTAT18
MDSTAT19
MDSTAT20
MDSTAT21
MDSTAT22
MDSTAT23
MDSTAT24
MDSTAT25
MDSTAT26
MDSTAT27
MDSTAT28
-
Module Status 17 Register (ASP)
Module Status 18 Register (I2C)
Module Status 19 Register (UART0)
Module Status 20 Register (UART1)
Module Status 21 Register (UART2)
Module Status 22 Register (SPI)
Module Status 23 Register (PWM0)
Module Status 24 Register (PWM1)
Module Status 25 Register (PWM2)
Module Status 26 Register (GPIO)
Module Status 27 Register (TIMER0)
Module Status 28 Register (TIMER1)
Reserved
MDSTAT39
MDSTAT40
-
Module Status 39 Register (C64x+ CPU)
Module Status 40 Register (VICP)
Reserved
MDCTL0
Module Control 0 Register (VPSS DMA)
Module Control 1 Register (VPSS MMR)
Module Control 2 Register (EDMACC)
Module Control 3 Register (EDMATC0)
Module Control 4 Register (EDMATC1)
Module Control 5 Register (EMAC)
Module Control 6 Register (EMAC Memory Controller)
Module Control 7 Register (MDIO)
Reserved
MDCTL1
MDCTL2
MDCTL3
MDCTL4
MDCTL5
MDCTL6
MDCTL7
MDCTL9
MDCTL10
MDCTL11
MDCTL12
MDCTL13
MDCTL14
MDCTL15
Module Control 9 Register (USB)
Module Control 10 Register (ATA/CF)
Module Control 11 Register (VLYNQ)
Module Control 12 Register (HPI)
Module Control 13 Register (DDR2)
Module Control 14 Register (EMIFA)
Module Control 15 Register (MMC/SD/SDIO)
Reserved
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Table 6-6. PSC Register Memory Map (continued)
REGISTER
ACRONYM
HEX ADDRESS RANGE
DESCRIPTION
0x01C4 1A44
0x01C4 1A48
MDCTL17
MDCTL18
MDCTL19
MDCTL20
MDCTL21
MDCTL22
MDCTL23
MDCTL24
MDCTL25
MDCTL26
MDCTL27
MDCTL28
-
Module Control 17 Register (ASP)
Module Control 18 Register (I2C)
Module Control 19 Register (UART0)
Module Control 20 Register (UART1)
Module Control 21 Register (UART2)
Module Control 22 Register (SPI)
Module Control 23 Register (PWM0)
Module Control 24 Register (PWM1)
Module Control 25 Register (PWM2)
Module Control 26 Register (GPIO)
Module Control 27 Register (TIMER0)
Module Control 28 Register (TIMER1)
Reserved
0x01C4 1A4C
0x01C4 1A50
0x01C4 1A54
0x01C4 1A58
0x01C4 1A5C
0x01C4 1A60
0x01C4 1A64
0x01C4 1A68
0x01C4 1A6C
0x01C4 1A70
0x01C4 1A74 - 0x01C4 1A9B
0x01C4 1A9C
MDCTL39
MDCTL40
-
Module Control 39 Register (C64x+ CPU)
Module Control 40 Register (VICP)
Reserved
0x01C4 1AA0
0x01C4 1AA4 - 0x01C4 1FFF
0x01C4 1000
MPFAR
MPFSR
MPFCR
MPAA
Memory Protection Fault Address Register
Memory Protection Fault Status Register
Memory Protection Fault Command Register
Memory Protection Page Attribute Register
Reserved
0x01C4 1004
0x01C4 1008
0x01C4 100C
0x01C4 1010 - 0x01C4 1FFF
-
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6.4 Reset
DM6446 supports various types of resets. Power-on-reset (POR), warm reset, max reset, system reset,
C64x+ local reset, and module reset are summarized in Table 6-7.
Table 6-7. DM6446 Resets
Type
Initiator
Description
Power-on-reset (POR)
RESET pin active low while TRST is low.
Global chip reset (Cold reset). Activates the POR signal
on chip, which is used to reset test and emulation logic.
Warm reset
RESET pin active low while TRST is high.
Resets everything except for test and emulation logic.
ARM emulator stays alive during warm reset, but the
C64x+ emulator does not.
Maximum reset
Emulator, WD Timer
Software (register bit)
Same as Warm reset, except for initiators.
C64x+ Local reset
MMR controls the C64x+ reset input. This is used for
control of C64x+ reset by the ARM. The C64x+ Slave
DMA port is still alive when in local reset.
Power-on-reset (POR) is the global chip reset and it affects test, emulation, and other circuitry. It is
invoked by driving the RESET pin active low while TRST is held low. A POR is required to place DM6446
into a known good initial state. POR can be asserted prior to ramping the core and I/O voltages or after
the core and I/O voltages have reached their proper operating conditions. As a best practice, RESET
should be asserted (held low) during power-up. Prior to deasserting RESET (low-to-high transition), the
core and I/O voltages should be at their proper operating conditions and if an external 27 MHz oscillator is
used on the MXI/CLKIN pin, the external clock should also be running at the correct frequency.
Warm reset is activated by driving the RESET pin active low, while TRST is inactive high. This does not
reset test or ARM emulation logic. An ARM emulator session will stay alive during warm reset, but a
C64x+ emulator session will not.
Maximum reset is initiated by the emulator or the watchdog timer and the reset effects are the same as a
warm reset. The emulator initiates a maximum reset via the ICEPICK module. When the watchdog timer
counter reaches zero, this will initiate a maximum reset to recover from a runaway condition. Both of the
maximum reset initiators can be masked by the ARM emulator.
System reset is initiated by the emulator and is a soft reset. Memory contents are maintained. Test,
emulation, clock, and power control logic are unaffected. The emulator initiates a system reset via the
C64x+ emulation logic, or through ICECRUSHER. Both of these reset initiators are non-maskable resets.
The C64x+ DSP has an internal reset input that allows a host to control it. This reset is configured through
a MMR bit (MDCTL[39].LRSTz) in the PSC module. When in C64x+ local reset, the slave DMA port on
C64x+ will remain active and the internal memory will be accessible, including access to the VICP memory
through the L2 port (UMAP port).
For details on reset control/status registers, see the TMS320DM644x DMSoC ARM Subsystem Reference
Guide (literature number SPRUE14)
For information on peripheral selection at the rising edge of RESET, see the Device Configuration section
of this data manual.
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6.4.1 Reset Electrical Data/Timing
Table 6-8. Timing Requirements for Reset (see Figure 6-9)
NO.
1
MIN
MAX
UNIT
ns
tw(RST)
Width of the RESET pulse
444
444
444
2
tsu(BOOT)
th(BOOT)
Setup time, boot configuration bits valid before RESET high
Hold time, boot configuration bits valid after RESET high
ns
3
ns
Table 6-9. Switching Characteristics Over Recommended Operating Conditions During Reset(1)
(see Figure 6-9)
NO.
MIN
MAX
2000P
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
26 td(PLL_LOCK)
Delay time, PLL1 lock time
4
5
6
td(RSTL-DDRZZ)
td(RSTL-DDRLL)
td(RSTL-DDRHH)
Delay time, RESET low to DDR2 Z Group high impedance
Delay time, RESET low to DDR2 Low Group low
Delay time, RESET low to DDR2 High Group high
Delay time, RESET low to DDR2 Z/High Group high impedance
Delay time, RESET low to DDR2 Low/High Group low
Delay time, RESET low to Z Group high impedance
Delay time, RESET low to Low Group low
0
0
0
0
0
0
0
0
0
0
0
2P + 20
20
20
16 td(RSTL-DDRZHZ)
17 td(RSTL-DDRLHL)
5P + 20
20
7
8
9
td(RSTL-ZZ)
20
td(RSTL-LOWL)
td(RSTL-HIGHH)
20
Delay time, RESET low to High Group high
20
18 td(RSTL-HIGHLOWH)
19 td(RSTL-LOWHIGHL)
24 td(RSTL-ZIZ)
Delay time, RESET low to High/Low Group high
Delay time, RESET low to Low/High Group low
Delay time, RESET low to Z/Invalid Group high impedance
Delay time, RESET high to DDR2 Z Group valid
Delay time, RESET high to DDR2 Low Group valid
Delay time, RESET high to DDR2 High Group valid
Delay time, RESET high to DDR2 Z/High Group valid high
Delay time, RESET high to DDR2 Low/High Group valid high
Delay time, RESET high to Z Group valid
20
20
20
(2)
10 td(RSTH-DDRZV)
11 td(RSTH-DDRLV)
12 td(RSTH-DDRHV)
20 td(RSTH-DDRZHV)
21 td(RSTH-DDRLHV)
13 td(RSTH-ZV)
(2)
(2)
4000P
4000P
(2)
(2)
(2)
14 td(RSTH-LOWV)
15 td(RSTH-HIGHV)
22 td(RSTH-HIGHLOWV)
23 td(RSTH-LOWHIGHV)
25 td(RSTH-ZIIV)
Delay time, RESET high to Low Group valid
Delay time, RESET high to High Group valid
Delay time, RESET high to High/Low Group valid low
Delay time, RESET high to Low/High Group valid high
Delay time, RESET high to Z/Invalid Group invalid
5100P
5100P
4000P
(1) P = MXI/CLKIN cycle time, in ns.
(2) Following RESET high, this signal group maintains the state the pins(s) achieved while RESET was driven low until the peripheral is
enabled via the PSC. For example, the DDR2 Z Group goes high impedance following RESET low and remains in the high-impedance
state following RESET high until the DDR2 controller is enabled via the PSC.
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1
RESET
2
3
Boot
Configuration Pins
4
5
10
11
12
20
21
13
14
15
(A)
DDR2 Z Group
(A)
DDR2 Low Group
6
(A)
(A)
DDR2 High Group
16
DDR2 Z/High Group
17
7
(A)
(A)
DDR2 Low/High Group
Z Group
8
9
(A)
(A)
(A)
Low Group
High Group
18
19
24
22
23
High/Low Group
Low/High Group
Z/Invalid Group
(A)
(A)
25
A. DDR2 Z Group: DDR_DQS[3:0], DDR_D[12:0]
DDR2 Low Group: DDR_CLK0, DDR_CKE, DDR_A[12:0]
DDR2 High Group: DDR_CLK0, DDR_CS, DDR_WE, DDR_RAS, DDR_CAS
DDR2 Z/High Group: DDR_DQM[3:0],
DDR2 Low/High Group: DDR_BS[2:0]
Low Group: DMARQ/UART_RXD1, VCLK, RTCK, TDO, VPBECLK, YOUT0/G5/AEAW0, YOUT1/G6/AEAW1,
YOUT2/G7/AEAW2, YOUT3/R3/AEAW3, YOUT4/R4/AEAW4, COUT3/B6/DSP_BT, COUT2/B5/EM_WIDTH,
COUT1/B4/BTSEL1, COUT0/B3/BTSEL0, TRST
High Group: DMACK/UART_TXD1, EM_A[2]/(CLE), EM_A[1]/(ALE), EM_CS3, EM_WE/(WE)(IOWR)/DIOW
Z Group: All other pins not listed above, with the exception of power and ground pins.
S
The following Z Group pins have an internal pullup (IPU): DMARQ/UART_RXD1, VPBECLK, HSYNC, VSYNC,
YOUT0/G5/AEAW0, YOUT1/G6/AEAW1, YOUT2/G7/AEAW2, YOUT3/R3/AEAW3, YOUT4/R4/AEAW4,
COUT3/B6/DSP_BT, COUT2/B5/EM_WIDTH, COUT1/B4/BTSEL1, COUT0/B3/BTSEL0, TRST, YI/CCD[7:0],
CI[3:0]/CCD[11:8], CI4/CCD12/UART_RTS2, CI5/CCD13/UART_CTS2, CI6/CCD14/UART_TXD2,
CI7/CCD15/UART_RXD2
S
The following Z Group pins have an internal pulldown (IPD): EM_WAIT/IORDY, TCK, TDI, TMS, EMU[1:0]
High/Low Group: EM_BA[0]/DA0, EM_CS2, EM_OE/(RE)/(IORD)/DIOR
Low/High Group: EM_R/W/INTRQ
Z/Invalid Group: EM_D[15:0]
Figure 6-9. Reset Timing
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6.5 External Clock Input From MXI/CLKIN Pin
The DM6446 device has two input pins for an external clock source, MXI/CLKIN and M24XI. The
MXI/CLKIN pin provides the clock source for PLL1 and PLL2 whose optimal frequency is 27 MHz. The
M24XI pin provides the clock source for the USB PLL whose optimal frequency is 24 MHz.
The DM6446 device includes two options to provide an external clock input:
1. Use an on-chip oscillator with external crystal or ceramic resonator circuit (only supporting
parallel-resonant mode; it does not provide overtone support). For more details, see Section 6.5.1.
2. Use an external 1.8-V LVCMOS-compatible clock input. For more details, see Section 6.5.2.
6.5.1 Clock Input Option 1 – Crystal
6.5.1.1 27-MHz Crystal for System Oscillator
In this option, a crystal is used as the external clock input to the DM6446 PLL1 and PLL2.
The 27-MHz oscillator provides the reference clock for all DM6446 subsystems and peripherals. The
on-chip oscillator requires an external 27-MHz crystal connected across the MXI and MXO pins, along
with two load capacitors, as shown in Figure 6-10. The external crystal load capacitors must be
connected only to the 27-MHz oscillator ground pin (MXVSS). Do not connect to board ground (VSS). The
MXVDD pin can be connected to the same 1.8 V power supply as DVDD18
.
MXI/CLKIN
MXO
MXV
MXV
DD
SS
RBIAS
(optional)
Crystal
27 MHz
C1
C2
1.8 V
Figure 6-10. 27-MHz System Oscillator
The RBIAS resistor is optional. If the RBIAS resistor is used, it should equal 1 MΩ ±5%. The load
capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 =
10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete components used
to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins
(MXI and MXO) and to the MXVSS pin.
C1C2
(C1 ) C2)
CL +
Table 6-10. Crystal Requirements for a 27-MHz System Oscillator
PARAMETER
MIN
TYP
MAX
UNIT
ms
Start-up time (from power up until oscillating at stable frequency of 27 MHz)
4
Oscillation frequency
ESR
27
MHz
Ω
60
Frequency stability
±50
ppm
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6.5.1.2 24-MHz Crystal for USB Oscillator
In this option, a crystal is used as the external clock input to the DM6446 USB PLL.
The 24-MHz oscillator provides the reference clock for the DM6446 USB peripheral. The on-chip oscillator
requires an external 24-MHz crystal connected across the M24XI and M24XO pins, along with two load
capacitors, as shown in Figure 6-11.The external crystal load capacitors must be connected only to the
24-MHz oscillator ground pin (M24VSS). Do not connect to board ground (VSS).
M24XI
M24XO
M24V
M24V
DD
SS
RBIAS
(optional)
Crystal
24 MHz
C1
C2
1.8 V
Figure 6-11. 24-MHz USB Oscillator
The RBIAS resistor is optional. If the RBIAS resistor is used, it should equal 1 MΩ ±5%. The load
capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 =
10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete components used
to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins
(M24XI and M24XO) and to the M24XVSS pin.
C1C2
(C1 ) C2)
CL +
Table 6-11. Crystal Requirements for a 24-MHz USB Oscillator
PARAMETER
MIN
TYP
MAX
UNIT
ms
Start-up time (from power up until oscillating at stable frequency of 24 MHz)
4
Oscillation frequency
ESR
24
MHz
Ω
60
Frequency stability
±50
ppm
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6.5.2 Clock Input Option 2 – 1.8-V LVCMOS-Compatible Clock Input
In this option, a 1.8-V LVCMOS-compatible clock input is used as the external clock input to the DM6446
device. The external connections are shown in Figure 6-12. The MXI/CLKIN pin is connected to the 1.8-V
LVCMOS-compatible clock source. The MXO pin is left unconnected. The MXVSS pin is connected to
board ground (VSS). The MXVDD pin can be connected to the same 1.8-V power supply as DVDD18. The
clock source must meet the MXI/CLKIN timing requirements shown in Table 6-16, Timing Requirements
for MXI/CLKIN.
MXI/CLKIN
MXO
NC
MXVSS
MXVDD
1.8 V
Figure 6-12. 1.8-V LVCMOS-Compatible Clock Input
Figure 6-12 also applies to the USB external clock input. When a 1.8-V LVCMOS-compatible clock input is
used as the external clock input, the M24XI pin is connected to the 1.8-V LVCMOS-compatible clock
source. The M24XO pin is left unconnected. The M24VSS pin is connected to board ground (VSS). The
M24VDD pin can be connected to the same 1.8-V power supply as DVDDR2. The clock source must meet
the MXI/CLKIN timing requirements shown in Table 6-17, Timing Requirements for M24XI.
6.6 Clock PLLs
There are two independently controlled PLLs on DM6446. PLL1 generates the frequencies required for the
DSP, ARM, VICP, DMA, VPFE, and other peripherals. PLL2 generates the frequencies required for the
DDR2 interface and the VPBE in certain modes. The recommended reference clock for both PLLs is the
27-MHz crystal input. The USB2.0 PHY contains a third PLL embedded within it and the 24-MHz oscillator
is its reference clock source. This particular PLL is only usable for USB operation, and is discussed further
in the TMS320DM644x DMSoC Univeral Serial Bus (USB) Controller User's Guide (literature number
SPRUE35).
A summary of the PLL controller registers is shown in Table 6-12. For more details, see the
TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).
Table 6-12. PLL and Reset Controller Registers Memory Map
HEX ADDRESS RANGE
REGISTER ACRONYM
PLL1 Controller Registers
DESCRIPTION
0x01C4 0800
0x01C4 08E4
0x01C4 0900
0x01C4 0910
0x01C4 0918
0x01C4 091C
0x01C4 0920
0x01C4 0928
0x01C4 092C
0x01C4 0938
PID
Peripheral Identification and Revision Information Register
Reset Type Register
RSTYPE
PLLC
PLL Controller 1 Operations Control Register
PLL Controller 1 Multiplier Control Register
PLLM
PLLDIV1
PLLDIV2
PLLDIV3
POSTDIV
BPDIV
PLL Controller 1 Control-Divider 1 Register (SYSCLK1)
PLL Controller 1 Control-Divider 2 Register (SYSCLK2)
PLL Controller 1 Control-Divider 3 Register (SYSCLK3)
PLL Controller 1 Post-Divider Control Register
PLL Controller 1 Bypass Control-Divider Register (SYSCLKBP)
PLL Controller 1 Command Register
PLLCMD
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Table 6-12. PLL and Reset Controller Registers Memory Map (continued)
HEX ADDRESS RANGE
REGISTER ACRONYM
DESCRIPTION
0x01C4 093C
PLLSTAT
PLL Controller 1 Status Register (Shows PLLCTRL Status)
PLL Controller 1 Alignment Control Register
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
0x01C4 0940
ALNCTL
PLL Controller 1 Divider Change Register
(Indicates if SYSCLK Divide Ratio has Been Modified)
0x01C4 0944
DCHANGE
0x01C4 0948
0x01C4 094C
0x01C4 0950
CKEN
PLL Controller 1 Clock Enable Register
CKSTAT
PLL Controller 1 Clock Status Register (For All Clocks Except SYSCLKx)
PLL Controller 1 System Clock Status 1 Register (Indicates SYSCLK on/off
Status)
SYSTAT
0x01C4 0960
0x01C4 0964
PLLDIV4
PLLDIV5
PID
PLL Controller 1 Control-Divider 4 Register (SYSCLK4)
PLL Controller 1 Control-Divider 5 Register (SYSCLK5)
Peripheral Identification and Revision Information Register
PLL Controller 2 Operations Control Register
0x01C4 0C00
0x01C4 0D00
PLLC
0x01C4 0D10
PLLM
PLL Controller 2 Multiplier Control Register
0x01C4 0D18
PLLDIV1
PLLDIV2
POSTDIV
BPDIV
PLL Controller 2 Control-Divider 1 Register (SYSCLK1)
PLL Controller 2 Control-Divider 2 Register (SYSCLK2)
PLL Controller 2 Post-Divider Control Register
0x01C4 0D1C
0x01C4 0D20 - 0x01C4 0D2B
0x01C4 0D2C
PLL Controller 2 Bypass Control-Divider Register (SYSCLKBP)
PLL Controller 2 Command Register
0x01C4 0D38
PLLCMD
PLLSTAT
0x01C4 0D3C
PLL Controller 2 Status Register (Shows PLLCTRL Status)
PLL Controller 2 Alignment Control Register
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
0x01C4 0D40
0x01C4 0D44
ALNCTL
PLL Controller 2 Divider Change Register
(Indicates if SYSCLK Divide Ratio has Been Modified)
DCHANGE
0x01C4 0D48
0x01C4 0D4C
0x01C4 0D50
CKEN
PLL Controller 2 Clock Enable Register
CKSTAT
SYSTAT
PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx)
PLL Controller 2 System Clock Status 1 Register (Indicates SYSCLK on/off
Status)
6.6.1 PLL1 and PLL2
Both PLL1 and PLL2 power is supplied externally via the 1.8 V PLL power-supply pin (PLLVDD18). It is
recommended that an external EMI filter circuit be added to PLLVDD18, as shown in Figure 6-13. The 1.8-V
supply of the EMI filter must be from the same 1.8-V power plane supplying the device’s 1.8-V I/O
power-supply pins (DVDD). TI recommends EMI filter manufacturer Murata, part number
NFM18CC222R1C3.
All PLL external components (C1, C2, and the EMI Filter) should be placed as close to the device as
possible. For the best performance, TI recommends that all the PLL external components be on a single
side of the board without jumpers, switches, or components other than the ones shown in Figure 6-13. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(C1, C2, and the EMI Filter).
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DM644x
PLL1
PLLVDD18
+1.8 V
C2
C1
EMI Filter
0.1 µF
0.01 µF
PLL2
Figure 6-13. PLL1 and PLL2 External Connection
The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements,
see Section 6.6.3, Clock PLL Electrical Data/Timing (Input and Output Clocks).
There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating
frequency for MXI/CLKIN, PLLOUT, and the device clocks (SYSCLKs). The PLL Controllers must be
configured not to exceed any of these constraints documented in this section (certain combinations of
external clock inputs, internal dividers, and PLL multiply ratios might not be supported).
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Table 6-13. PLLC1 Clock Frequency Ranges
CLOCK SIGNAL NAME
MIN
20
MAX
30
UNIT
MHz
MHz
MHz
MXI/CLKIN(1)
PLLOUT
At 1.2-V CVDD
400
594
594
SYSCLK1 (CLKDIV1 Domain)
(1) MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).
Table 6-14. PLLC2 Clock Frequency Ranges
CLOCK SIGNAL NAME
MIN
20
MAX
UNIT
MHz
MHz
MXI/CLKIN(1)
PLLOUT
30
At 1.2-V CVDD
400
900
(1) MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).
Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed.
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after the PLL is powered up (after PLLCTL.PLLPWRDN bit goes through a 1-to-0
transition). The PLL should not be operated until this stabilization time has expired. This stabilization step
must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the
PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabliziation time value, see Table 6-15.
The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 0)
before bringing the PLL out of reset (writing PLLRST = 1). For the PLL reset time value, see Table 6-15.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1
with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the
PLL lock time value, see Table 6-15.
Table 6-15. PLL1 and PLL2 Stabilization, Lock, and Reset Times
PLL STABILIZATION/LOCK/RESET TIME
PLL Stabilization Time
MIN
TYP
MAX
UNIT
µs
150
PLL Lock Time
2000C(1)
ns
PLL Reset Time
128C(1)
ns
(1) C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37.037 ns.
For details on the PLL initialization software sequence, see the TMS320DM6446 DMSoC ARM Subsystem
Reference Guide (literature number SPRUE14).
6.6.2 Clock PLL Considerations with External Clock Sources
If the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power
both the DM6446 device and the external clock oscillator circuit. The minimum CLKIN rise and fall times
should also be observed. For the input clock timing requirements, see Section 6.6.3, Clock PLL Electrical
Data/Timing (Input and Output Clocks).
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock
source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Case Temperature and Section 6.6.3,
Clock PLL Electrical Data/Timing (Input and Output Clocks).
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6.6.3 Clock PLL Electrical Data/Timing (Input and Output Clocks)
Table 6-16. Timing Requirements for MXI/CLKIN(1)(2)(3)(4) (see Figure 6-14)
NO.
1
MIN
33.3
MAX
UNIT
ns
tc(MXI)
tw(MXIH)
tw(MXIL)
tt(MXI)
Cycle time, MXI/CLKIN
50
2
Pulse duration, MXI/CLKIN high
Pulse duration, MXI/CLKIN low
Transition time, MXI/CLKIN
Period jitter, MXI/CLKIN
0.45C
0.45C
0.55C
0.55C
0.05C
0.02C
ns
3
ns
4
ns
5
tJ(MXI)
ns
(1) The MXI/CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range
for CPU operating frequency. For example, for a -594 speed device with a 27 MHz CLKIN frequency, the PLL multiply factor should be
≤ 22.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(3) For more details on the PLL multiplier factors, see the Documentation Support section for ARM Subsystem User's Guide.
(4) C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37.037 ns.
1
5
4
2
MXI/CLKIN
3
4
Figure 6-14. MXI/CLKIN Timing
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Table 6-17. Timing Requirements for M24XI(1)(2)(3) (see Figure 6-15)
NO.
UNIT
MIN
TYP
MAX
1
2
3
4
5
tc(M24XI)
Cycle time, M24XI
41.6
ns
tw(M24XIH)
tw(M24XIL)
tt(M24XI)
Pulse duration, M24XI high
Pulse duration, M24XI low
Transition time, M24XI
Period jitter, M24XI
0.45C
0.45C
0.55C ns
0.55C ns
0.05C ns
0.02C ns
tJ(M24XI)
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) For more details on the PLL, see the Documentation Support section for USB Peripheral Reference Guide.
(3) C = M24XI cycle time in ns. For example, when M24XI frequency is 24 MHz, use C = 41.6 ns.
1
5
4
2
MXI/CLKIN
3
4
Figure 6-15. M24XI Timing
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Table 6-18. Switching Characteristics Over Recommended Operating Conditions for CLK_OUT0(1)(2)
(see Figure 6-16)
NO.
1
PARAMETER
MIN
37.037
MAX
UNIT
tC
Cycle time, CLK_OUT0
74.074 ns
2
tw(CLKOUT0H)
tw(CLKOUT0L)
tt(CLKOUT0)
Pulse duration, CLK_OUT0 high
Pulse duration, CLK_OUT0 low
Transition time, CLK_OUT0
0.45P
0.45P
0.55P ns
0.55P ns
0.05P ns
3
4
Delay time, CLKIN/MXI high to CLK_OUT0 high
(divide-by-1 only)
5
6
7
8
td(CLKINH-CLKO0H)
td(CLKINL-CLKO0L)
td(CLKINH-CLKO0L)
td(CLKINH-CLKO0H)
1
1
1
1
8
8
8
8
ns
ns
ns
ns
Delay time, CLKIN/MXI low to CLK_OUT0 low
(divide-by-1 only)
Delay time, CLKIN/MXI high to CLK_OUT0 low
(divide-by-2 only)
Delay time, CLKIN/MXI high to CLK_OUT0 high
(divide-by-2 only)
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/CLK_OUT0 clock frequency in nanoseconds (ns). For example, when CLK_OUT0 frequency is 27 MHz, use P = 37.04 ns.
5
6
8
7
CLKIN/MXI
2
4
1
CLK_OUT0
(Divide-by-1)
3
4
CLK_OUT0
(Divide-by-2)
Figure 6-16. CLK_OUT0 Timing
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Table 6-19. Switching Characteristics Over Recommended Operating Conditions for CLK_OUT1(1)(2)
(see Figure 6-17)
NO.
1
PARAMETER
MIN
41.667
MAX
83.33
UNIT
tC
Cycle time, CLK_OUT1
2
tw(CLKOUT1H)
tw(CLKOUT1L)
tt(CLKOUT1)
Pulse duration, CLK_OUT1 high
Pulse duration, CLK_OUT1 low
Transition time, CLK_OUT1
0.45P
0.45P
0.55P ns
0.55P ns
0.05P ns
3
4
Delay time, CLKIN/MXI high to CLK_OUT1 high
(divide-by-1 only)
5
6
7
8
td(CLKINH-CLKO1H)
td(CLKINL-CLKO1L)
td(CLKINH-CLKO1L)
td(CLKINH-CLKO1H)
1
1
1
1
8
8
8
8
ns
ns
ns
ns
Delay time, CLKIN/MXI low to CLK_OUT1 low
(divide-by-1 only)
Delay time, CLKIN/MXI high to CLK_OUT1 low
(divide-by-2 only)
Delay time, CLKIN/MXI high to CLK_OUT1 high
(divide-by-2 only)
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/CLK_OUT1 clock frequency in nanoseconds (ns). For example, when CLK_OUT1 frequency is 24 MHz, use P = 41.6 ns.
5
6
8
7
CLKIN/MXI
2
4
1
CLK_OUT1
(Divide-by-1)
3
4
CLK_OUT1
(Divide-by-2)
Figure 6-17. CLK_OUT1 Timing
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6.7 Interrupts
The DM6446 device has a large number of interrupts to service the needs of its many peripherals and
subsystems. Both the ARM and C64x+ are capable of servicing these interrupts. All of the device
interrupts are routed to the ARM interrupt controller with only a limited set routed to the C64x+ interrupt
controller. The interrupts can be selectively enabled or disabled in either of the controllers. In typical
applications, the ARM handles most of the peripheral interrupts and grants control, to the C64x+, of
interrupts that are relevant to DSP algorithms. Also, the ARM and DSP can communicate with each other
through interrupts.
6.7.1 ARM CPU Interrupts
The ARM9 CPU core supports 2 direct interrupts: FIQ and IRQ. The DM6446 ARM interrupt controller
prioritizes up to 64 interrupt requests from various peripherals and subsystems, which are listed in
Table 6-20, and interrupts the ARM CPU. Each interrupt is programmable for up to 8 levels of priority.
There are 6 levels for IRQ and 2 levels for FIQ. Interrupts at the same priority level are serviced in order
by the ARM Interrupt Number, with the lowest number having the highest priority. Table 6-21 shows the
ARM interrupt controller registers and memory locations. For more details on ARM interrupt control, see
the Documentation Support section of the TMS320DM6446 DMSoC ARM Subsystem Reference Guide
(literature number SPRUE14).
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Table 6-20. DM6446 ARM Interrupts
ARM
ARM
INTERRUPT
NUMBER
ACRONYM
SOURCE
INTERRUPT
NUMBER
ACRONYM
SOURCE
Timer 0 – TINT12
0
VDINT0
VDINT1
VDINT2
HISTINT
H3AINT
PRVUINT
RSZINT
-
VPSS CCDC 0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
TINT0
TINT1
1
VPSS CCDC 1
VPSS CCDC 2
VPSS Histogram
VPSS AE/AWB/AF
VPSS Previewer
VPSS Resizer
Reserved
Timer 0 – TINT34
Timer 1 – TINT12
Timer 1 – TINT34
PWM 0
2
TINT2
3
TINT3
4
PWMINT0
PWMINT1
PWMINT2
I2CINT
5
PWM 1
6
PWM 2
7
I2C
8
VENCINT
ASQINT
IMXINT
VLCDINT
-
VPSS VPBE
UARTINT0
UARTINT1
UARTINT2
SPINT0
UART 0
9
VICP Sqr (ARM int)
VICP IMX
UART 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
UART 2
VICP VLCD
SPI
Reserved
SPINT1
SPI
EMACINT
-
EMAC Memory Controller
Reserved
-
Reserved
DSP Controller to ARM 0
DSP Controller to ARM 1
GPIO 0
DSP2ARM0
DSP2ARM1
GPIO0
-
Reserved
EDMA3CC_INT0
EDMA CC Region 0
EDMA3CC_ERRINT EDMA CC Error
EDMA3TC_ERRINT0 EDMA TC 0 Error
EDMA3TC_ERRINT1 EDMA TC 1 Error
GPIO1
GPIO 1
GPIO2
GPIO 2
GPIO3
GPIO 3
PSCINT
-
PSC ALLINT
Reserved
ATA / IDE
HPI
GPIO4
GPIO 4
GPIO5
GPIO 5
IDEINT
HPINT
GPIO6
GPIO 6
GPIO7
GPIO 7
ASPXINT
ASPRINT
MMCINT
SDIOINT
-
ASP Transmit
ASP Receive
MMC
GPIOBNK0
GPIOBNK1
GPIOBNK2
GPIOBNK3
GPIOBNK4
COMMTX
COMMRX
EMUINT
GPIO Bank 0
GPIO Bank 1
GPIO Bank 2
GPIO Bank 3
GPIO Bank 4
ARMSS
SD
Reserved
DDR2 Memory Controller
EMIFA
DDRINT
EMIFAINT
VLQINT
ARMSS
VLYNQ
E2ICE
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Table 6-21. ARM Interrupt Controller Registers
HEX ADDRESS
0x01C4 8000
ACRONYM
FIQ0
REGISTER DESCRIPTION
FIQ Interrupt Status 0 [Interrupt Status of INT[31:0] (If Mapped to FIQ)]
FIQ Interrupt Status 1 [Interrupt Status of INT[63:32] (If Mapped to FIQ)]
IRQ Interrupt Status 0 [Interrupt Status of INT[31:0] (If Mapped to IRQ)]
IRQ Interrupt Status 1 [Interrupt Status of INT[63:32] (If Mapped to IRQ)]
Entry Address [28:0] for Valid FIQ Interrupt
Entry Address [28:0] for Valid IRQ Interrupt
Interrupt Enable Register 0
0x01C4 8004
FIQ1
0x01C4 8008
IRQ0
0x01C4 800C
0x01C4 8010
IRQ1
FIQENTRY
IRQENTRY
EINT0
0x01C4 8014
0x01C4 8018
0x01C4 801C
0x01C4 8020
EINT1
Interrupt Enable Register 1
INCTL
Interrupt Operation Control Register
Interrupt Entry Table Base Address Register
Reserved
0x01C4 8024
EABASE
-
0x01C4 8028 - 0x01C4 802F
0x01C4 8030
INTPRI0
INTPRI1
INTPRI2
INTPRI3
INTPRI4
INTPRI5
INTPRI6
INTPRI7
-
Interrupt 0-7 Priority Select
0x01C4 8034
Interrupt 8-15 Priority Select
0x01C4 8038
Interrupt 16-23 Priority Select
0x01C4 803C
0x01C4 8040
Interrupt 24-31 Priority Select
Interrupt 32-39 Priority Select
0x01C4 8044
Interrupt 40-47 Priority Select
0x01C4 8048
Interrupt 48-55 Priority Select
0x01C4 804C
0x01C4 8050 - 0x01C4 83FF
Interrupt 56-63 Priority Select
Reserved
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6.7.2 DSP Interrupts
The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 6-22. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 6-23
summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP
interrupt control, see the Documentation Support section of the TMS320DM6446 DMSoC DSP Subsystem
Reference Guide (literature number SPRUE15).
Table 6-22. DM6446 DSP Interrupts
DSP
DSP
INTERRUPT
NUMBER
ACRONYM
SOURCE
INTERRUPT
NUMBER
ACRONYM
SOURCE
0
EVT0
EVT1
EVT2
EVT3
C64x+ Int Ctl 0
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
C64x+ Int Ctl 1
C64x+ Int Ctl 2
C64x+ Int Ctl 3
Timer 0 – TINT12
Timer 0 – TINT34
Timer 1 – TINT12
Timer 1 – TINT34
Reserved
2
3
4
TINT0
TINT1
TINT2
TINT3
5
6
7
8
9
EMU_DTDMA
C64x+ EMC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
EMU_RTDXRX
EMU_RTDXTX
IDMAINT0
C64x+ RTDX
C64x+ RTDX
C64x+ EMC 0
C64x+ EMC 1
Reserved
IDMAINT1
ARM2DSP0
ARM2DSP1
ARM2DSP2
ARM2DSP3
ARM to DSP Controller 0
ARM to DSP Controller 1
ARM to DSP Controller 2
ARM to DSP Controller 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INTERR
EMC_IDMAERR
C64x+ Interrupt Controller
Dropped CPU Interrupt Event
32
33
96
97
Reserved
C64x+ EMC Invalid IDMA
Parameters
34
35
36
Reserved
98
99
Reserved
Reserved
Reserved
Reserved
EDMA3CC_INT1
EDMACC Interrupt Region 1
100
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Table 6-22. DM6446 DSP Interrupts (continued)
DSP
DSP
INTERRUPT
NUMBER
ACRONYM
SOURCE
INTERRUPT
NUMBER
ACRONYM
SOURCE
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
EDMA3CC_ERRINT
EDMA CC Error
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EDMA3TC_ERRINT0 EDMA TC0 Error
EDMA3TC_ERRINT1 EDMA TC1 Error
PSCINT
PSC ALLINT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ASP Transmit
ASP Receive
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ASPXINT
ASPRINT
PMC_ED
C64x+ PMC
Reserved
Reserved
Reserved
UMCED1
C64x+ UMC 1
C64x+ UMC 2
C64x+ PDC
C64x+ PDC
C64x+ PMC
C64x+ PMC
C64x+ DMC
C64x+ DMC
C64x+ UMC
C64x+ UMC
C64x+ EMC
C64x+ EMC
UMCED2
PDCERR
PVCINT
PMCCMPA
PMCDMPA
DMCCMPA
DMCDMPA
UMCCMPA
UMCDMPA
EMCCMPA
EMCDMPA
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Table 6-23. C64x+ Interrupt Controller Registers
HEX ADDRESS
0x0180 0000
0x0180 0004
0x0180 0008
0x0180 000C
0x0180 0020
0x0180 0024
0x0180 0028
0x0180 002C
0x0180 0040
0x0180 0044
0x0180 0048
0x0180 004C
0x0180 0080
0x0180 0084
0x0180 0088
0x0180 008C
0x0180 00A0
0x0180 00A4
0x0180 00A8
0x0180 00AC
0x0180 00C0
0x0180 00C4
0x0180 00C8
0x0180 00CC
0x0180 00E0
0x0180 00E4
0x0180 00E8
0x0180 00EC
0x0180 0104
0x0180 0108
0x0180 010C
0x0180 0140 - 0x0180 0144
0x0180 0180
0x0180 0184
0x0180 0188
0x0180 01C0
ACRONYM
EVTFLAG0
EVTFLAG1
EVTFLAG2
EVTFLAG3
EVTSET0
REGISTER DESCRIPTION
Event flag register 0
Event flag register 1
Event flag register 2
Event flag register 3
Event set register 0
EVTSET1
Event set register 1
EVTSET2
Event set register 2
EVTSET3
Event set register 3
EVTCLR0
Event clear register 0
EVTCLR1
Event clear register 1
EVTCLR2
Event clear register 2
EVTCLR3
Event clear register 3
EVTMASK0
EVTMASK1
EVTMASK2
EVTMASK3
MEVTFLAG0
MEVTFLAG1
MEVTFLAG2
MEVTFLAG3
EXPMASK0
EXPMASK1
EXPMASK2
EXPMASK3
MEXPFLAG0
MEXPFLAG1
MEXPFLAG2
MEXPFLAG3
INTMUX1
Event mask register 0
Event mask register 1
Event mask register 2
Event mask register 3
Masked event flag register 0
Masked event flag register 1
Masked event flag register 2
Masked event flag register 3
Exception mask register 0
Exception mask register 1
Exception mask register 2
Exception mask register 3
Masked exception flag register 0
Masked exception flag register 1
Masked exception flag register 2
Masked exception flag register 3
Interrupt mux register 1
Interrupt mux register 2
Interrupt mux register 3
Reserved
INTMUX2
INTMUX3
-
INTXSTAT
INTXCLR
Interrupt exception status
Interrupt exception clear
Dropped interrupt mask register
Event assert register
INTDMASK
EVTASRT
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6.7.3 ARM/DSP Communications Interrupts
The INTGEN register is used for generating interrupts between the ARM and DSP. The INTGEN register
format is shown in Figure 6-18. Table 6-24 describes the register bit fields. The ARM may generate an
interrupt to the DSP by setting one of the four INTDSP[3:0] bits or the INTNMI bit. The interrupt bit
automatically self clears and the corresponding DSP[3:0]STAT or NMISTAT bit is automatically set to
indicate that the interrupt was generated. After servicing the interrupt, the DSP clears the status bit by
writing ‘0’. The ARM may poll the status bit to determine when the DSP has completed servicing the
interrupt. The DSP may generate an interrupt to the ARM in the same manner using the INTARM[1:0] bits
and monitor ARM interrupt servicing via the ARM[1:0]STAT bits.
Figure 6-18. INTGEN Register
31
Reserved
R-00
30
29
28
27
24
23
22
21
20
19
17
16
ARM1 ARM0
STAT STAT
DSP3 DSP2 DSP1 DSP0
STAT STAT STAT STAT
NMI
STAT
Reserved
R-0000
Reserved
R-000
R/W-0 R/W-0
R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
15
14
13
12
11
8
7
6
5
4
3
1
0
INT
INT
INT
INT
INT
INT
INT
NMI
Reserved
R-00
Reserved
R-0000
Reserved
R-000
ARM1 ARM0
DSP3 DSP2 DSP1 DSP0
R/W-0 R/W-0
R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Table 6-24. INTGEN Register Bit Fields Descriptions
Name
Description
ARM1STAT
ARM0STAT
DSP3STAT
DSP2STAT
DSP1STAT
DSP0STAT
NMISTAT
INTARM1
INTARM0
INTDSP3
INTDSP2
INTDSP1
INTDSP0
INTNMI
DSP to ARM Int1 Status/Clear(1)
DSP to ARM Int0 Status/Clear(1)
ARM to DSP Int3 Status/Clear(1)
ARM to DSP Int2 Status/Clear(1)
ARM to DSP Int1 Status/Clear(1)
ARM to DSP Int0 Status/Clear(1)
DSP NMI Status/Clear(1)
DSP to ARM Int1 Set(2)
DSP to ARM Int0 Set(2)
ARM to DSP Int3 Set(2)
ARM to DSP Int2 Set(2)
ARM to DSP Int1 Set(2)
ARM to DSP Int0 Set(2)
DSP NMI Set(2)
(1) Write '0' to clear. Writing '1' has no effect.
(2) Write '1' to generate the interrupt. The register bit automatically clears to a value of '0'. Writing a '0' has no effect.
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6.8 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
The DM6446 GPIO peripheral supports the following:
•
•
•
Up to 54 1.8v GPIO pins, GPIO[0:53]
Up to 17 3.3v GPIO pins, GPIO3V[0:16] (GPIO[54:70])
Interrupts:
–
–
–
Up to 8 unique GPIO[0:7] interrupts from Bank 0
5 GPIO bank (aggregated) interrupt signals from each of the 5 banks of GPIOs
Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO
signal
•
•
DMA events:
–
–
Up to 8 unique GPIO DMA events from Bank 0
5 GPIO bank (aggregated) DMA event signals from each of the 5 banks of GPIOs
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
•
•
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 6-25. For more detailed information on GPIOs,
see the Documentation Support section for the General-Purpose Input/Output (GPIO) Reference Guide.
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6.8.1 GPIO Peripheral Register Description(s)
Table 6-25. GPIO Registers
HEX ADDRESS RANGE
0x01C6 7000
ACRONYM
REGISTER NAME
PID
-
Peripheral Identification Register
Reserved
0x01C6 7004
0x01C6 7008
BINTEN
GPIO interrupt per-bank enable
GPIO Banks 0 and 1
0x01C6 700C
0x01C6 7010
0x01C6 7014
0x01C6 7018
0x01C6 701C
0x01C6 7020
0x01C6 7024
0x01C6 7028
0x01C6 702C
0x01C6 7030
0x01C6 7034
-
Reserved
DIR01
GPIO Banks 0 and 1 Direction Register (GPIO[0:31])
GPIO Banks 0 and 1 Output Data Register (GPIO[0:31])
GPIO Banks 0 and 1 Set Data Register (GPIO[0:31])
GPIO Banks 0 and 1 Clear data for banks 0 and 1 (GPIO[0:31])
GPIO Banks 0 and 1 Input Data Register (GPIO[0:31])
OUT_DATA01
SET_DATA01
CLR_DATA01
IN_DATA01
SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (GPIO[0:31])
CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (GPIO[0:31])
SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (GPIO[0:31])
CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (GPIO[0:31])
INSTAT01
GPIO Banks 0 and 1 Interrupt Status Register (GPIO[0:31])
GPIO Banks 2 and 3
0x01C6 7038
0x01C6 703C
0x01C6 7040
0x01C6 7044
0x01C6 7048
0x01C6 704C
0x01C6 7050
0x01C6 7054
0x01C6 7058
0x01C6 705C
DIR23
GPIO Banks 2 and 3 Direction Register (GPIO[32:63])
GPIO Banks 2 and 3 Output Data Register (GPIO[32:63])
GPIO Banks 2 and 3 Set Data Register (GPIO[32:63])
GPIO Banks 2 and 3 Clear Data Register (GPIO[32:63])
GPIO Banks 2 and 3 Input Data Register (GPIO[32:63])
OUT_DATA23
SET_DATA23
CLR_DATA23
IN_DATA23
SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register (GPIO[32:63])
CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register (GPIO[32:63])
SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register (GPIO[32:63])
CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register (GPIO[32:63])
INSTAT23
GPIO Banks 2 and 3 Interrupt Status Register (GPIO[32:63])
GPIO Bank 4
0x01C6 7060
0x01C6 7064
DIR4
GPIO Bank 4 Direction Register (GPIO[64:70])
GPIO Bank 4 Output Data Register (GPIO[64:70])
GPIO Bank 4 Set Data Register (GPIO[64:70])
GPIO Bank 4 Clear Data Register (GPIO[64:70])
GPIO Bank 4 Input Data Register (GPIO[64:70])
GPIO Bank 4 Set Rising Edge Interrupt Register (GPIO[64:70])
GPIO Bank 4 Clear Rising Edge Interrupt Register (GPIO[64:70])
GPIO Bank 4 Set Falling Edge Interrupt Register (GPIO[64:70])
OUT_DATA4
SET_DATA4
0x01C6 7068
0x01C6 706C
CLR_DATA4
IN_DATA4
0x01C6 7070
0x01C6 7074
SET_RIS_TRIG4
CLR_RIS_TRIG4
SET_FAL_TRIG4
0x01C6 7078
0x01C6 707C
0x01C6 7080
CLR_FAL_TRIG4 GPIO Bank 4 Clear Falling Edge Interrupt Register (GPIO[64:70])
0x01C6 7084
INSTAT4
-
GPIO Bank 4 Interrupt Status Register (GPIO[64:70])
Reserved
0x01C6 7088 - 0x01C6 7FFF
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6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-26. Timing Requirements for GPIO Inputs(1) (see Figure 6-19)
NO.
1
MIN
52
52
MAX
UNIT
ns
tw(GPIH)
tw(GPIL)
Pulse duration, GPIx high
Pulse duration, GPIx low
2
ns
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have DM6446 recognize
the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow DM6446 enough time to
access the GPIO register through the internal bus.
Table 6-27. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-19)
NO.
3
PARAMETER
Pulse duration, GPOx high
Pulse duration, GPOx low
MIN
26(1)
26(1)
MAX
UNIT
ns
tw(GPOH)
tw(GPOL)
4
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
2
1
GPIx
4
3
GPOx
Figure 6-19. GPIO Port Timing
6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-28. Timing Requirements for External Interrupts(1) (see Figure 6-20)
NO.
1
MIN
MAX
UNIT
ns
tw(ILOW)
tw(IHIGH)
Width of the external interrupt pulse low
Width of the external interrupt pulse high
52
52
2
ns
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have DM6446recognize the
GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow DM6446 enough time to
access the GPIO register through the internal bus.
2
1
EXT_INTx
Figure 6-20. GPIO External Interrupt Timing
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6.9 Enhanced Direct Memory Access (EDMA) Controller
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the DM6446 device. These data transfers include cache servicing, non-cacheable memory accesses,
user-programmed data transfers, and host accesses. These are summarized as follows:
•
Transfer to/from on-chip memories
–
–
–
–
Coprocessor shared memory
DSP L1D memory
DSP L2 memory
ARM program/data RAM
•
Transfer to/from external storage
–
–
–
–
–
DDR2 SDRAM
NAND flash
Asynchronous EMIF
Smart Media, SD, MMC, xD media storage
ATA/CF
•
Transfer to/from peripherals/hosts
–
–
–
–
–
VLYNQ
ASP
SPI
PWM
UART
The EDMA controller supports two addressing modes: constant addressing mode and increment
addressing mode. On the DM6446 device, constant addressing mode is not supported by any peripheral
or internal memory. For more information on these two addressing modes, see the TMS320DM644x
DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide (literature number SPRUE23).
6.9.1 EDMA Channel Synchronization Events
The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 6-29 lists the source of EDMA synchronization events associated with each of the programmable
EDMA channels. For the DM6446 device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the
EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers
(EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled,
captured, processed, linked, chained, and cleared, etc., see the Document Support section of the
TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide (literature
number SPRUE23).
Table 6-29. DM6446 EDMA Channel Synchronization Events(1)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
0-1
2
Reserved
XEVT
REVT
ASP Transmit Event
ASP Receive Event
VPSS Histogram Event
VPSS H3A Event
3
4
HISTEVT
H3AEVT
PRVUEVT
RSZEVT
5
6
VPSS Previewer Event
VPSS Resizer Event
7
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate
transfer completion events. For more detailed information on EDMA event-transfer chaining, see the Document Support section of the
TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide (literature number SPRUE23).
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Table 6-29. DM6446 EDMA Channel Synchronization Events (continued)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
8
9
IMXINT
VLCDINT
ASQINT
DSQINT
VICP Interrupt
VICP VLCD Interrupt
VICP ASQ Interrupt
VICP DSQ Interrupt
Reserved
10
11
12-15
16
SPIXEVT
SPIREVT
URXEVT0
UTXEVT0
URXEVT1
UTXEVT1
URXEVT2
UTXEVT2
SPI Transmit Event
SPI Receive Event
UART 0 Receive Event
UART 0 Transmit Event
UART 1 Receive Event
UART 1 Transmit Event
UART 2 Receive Event
UART 2 Transmit Event
Reserved
17
18
19
20
21
22
23
24
25
Reserved
26
MMCRXEVT
MMCTXEVT
I2CREVT
MMC Receive Event
MMC Transmit Event
I2C Receive Event
I2C Transmit Event
Reserved
27
28
29
I2CXEVT
30-31
32
GPINT0
GPINT1
GPIO 0 Interrupt
GPIO 1 Interrupt
GPIO 2 Interrupt
GPIO 3 Interrupt
GPIO 4 Interrupt
GPIO 5 Interrupt
GPIO 6 Interrupt
GPIO 7 Interrupt
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
GPIO Bank 4 Interrupt
Reserved
33
34
GPINT2
35
GPINT3
36
GPINT4
37
GPINT5
38
GPINT6
39
GPINT7
40
GPBNKINT0
GPBNKINT1
GPBNKINT2
GPBNKINT3
GPBNKINT4
41
42
43
44
45-47
48
TINT0
TINT1
TINT2
TINT3
PWM0
PWM1
PWM2
Timer 0 Interrupt
Timer 1 Interrupt
Timer 2 Interrupt
Timer 3 Interrupt
PWM 0 Event
49
50
51
52
53
PWM 1 Event
54
PWM 2 Event
55-63
Reserved
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6.9.2 EDMA Peripheral Register Descriptions
Table 6-30 lists the EDMA registers, their corresponding acronyms, and DM6446 device memory
locations.
Table 6-30. DM6446 EDMA Registers
HEX ADDRESS
ACRONYM
Channel Controller Registers
Reserved
REGISTER NAME
0x01c0 0000 - 0x01c0 0003
0x01c0 0004
CCCFG
EDMA3CC Configuration Register
Reserved
0x01c0 0008 - 0x01c0 01FF
Global Registers
0x01c0 0200
0x01c0 0204
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
QCHMAP4
QCHMAP5
QCHMAP6
QCHMAP7
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
DMAQNUM4
DMAQNUM5
DMAQNUM6
DMAQNUM7
QDMAQNUM
–
QDMA Channel 0 Mapping to PaRAM Register
QDMA Channel 1 Mapping to PaRAM Register
QDMA Channel 2 Mapping to PaRAM Register
QDMA Channel 3 Mapping to PaRAM Register
QDMA Channel 4 Mapping to PaRAM Register
QDMA Channel 5 Mapping to PaRAM Register
QDMA Channel 6 Mapping to PaRAM Register
QDMA Channel 7 Mapping to PaRAM Register
DMA Queue Number Register 0 (Channels 00 to 07)
DMA Queue Number Register 1 (Channels 08 to 15)
DMA Queue Number Register 2 (Channels 16 to 23)
DMA Queue Number Register 3 (Channels 24 to 31)
DMA Queue Number Register 4 (Channels 32 to 39)
DMA Queue Number Register 5 (Channels 40 to 47)
DMA Queue Number Register 6 (Channels 48 to 55)
DMA Queue Number Register 7 (Channels 56 to 63)
CC QDMA Queue Number
0x01c0 0208
0x01c0 020C
0x01c0 0210
0x01c0 0214
0x01c0 0218
0x01c0 021C
0x01c0 0240
0x01c0 0244
0x01c0 0248
0x01c0 024C
0x01c0 0250
0x01c0 0254
0x01c0 0258
0x01c0 025C
0x01c0 0260
0x01c0 0264 - 0x01c0 0283
0x01c0 0284
Reserved
QUEPRI
–
Queue Priority Register
0x01c0 0288 - 0x01c0 02FF
0x01c0 0300
Reserved
EMR
Event Missed Register
0x01c0 0304
EMRH
Event Missed Register High
0x01c0 0308
EMCR
Event Missed Clear Register
0x01c0 030C
0x01c0 0310
EMCRH
Event Missed Clear Register High
QEMR
QDMA Event Missed Register
0x01c0 0314
QEMCR
QDMA Event Missed Clear Register
0x01c0 0318
CCERR
EDMA3CC Error Register
0x01c0 031C
0x01c0 0320
CCERRCLR
EEVAL
EDMA3CC Error Clear Register
Error Evaluate Register
0x01c0 0340
DRAE0
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register High for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register High for Region 1
DMA Region Access Enable Register for Region 2
DMA Region Access Enable Register High for Region 2
DMA Region Access Enable Register for Region 3
DMA Region Access Enable Register High for Region 3
Reserved
0x01c0 0344
DRAEH0
DRAE1
0x01c0 0348
0x01c0 034C
0x01c0 0350
DRAEH1
DRAE2
0x01c0 0354
DRAEH2
DRAE3
0x01c0 0358
0x01c0 035C
0x01c0 0360 - 0x01c0 037C
DRAEH3
–
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Table 6-30. DM6446 EDMA Registers (continued)
HEX ADDRESS
0x01c0 0380
0x01c0 0384
0x01c0 0388
0x01c0 038C
ACRONYM
QRAE0
QRAE1
QRAE2
QRAE3
–
REGISTER NAME
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
Reserved
0x01c0 0390 - 0x01c0 039C
0x01c0 0400
Q0E0
Event Q0 Entry 0 Register
Event Q0 Entry 1 Register
Event Q0 Entry 2 Register
Event Q0 Entry 3 Register
Event Q0 Entry 4 Register
Event Q0 Entry 5 Register
Event Q0 Entry 6 Register
Event Q0 Entry 7 Register
Event Q0 Entry 8 Register
Event Q0 Entry 9 Register
Event Q0 Entry 10 Register
Event Q0 Entry 11 Register
Event Q0 Entry 12 Register
Event Q0 Entry 13 Register
Event Q0 Entry 14 Register
Event Q0 Entry 15 Register
Event Q1 Entry 0 Register
Event Q1 Entry 1 Register
Event Q1 Entry 2 Register
Event Q1 Entry 3 Register
Event Q1 Entry 4 Register
Event Q1 Entry 5 Register
Event Q1 Entry 6 Register
Event Q1 Entry 7 Register
Event Q1 Entry 8 Register
Event Q1 Entry 9 Register
Event Q1 Entry 10 Register
Event Q1 Entry 11 Register
Event Q1 Entry 12 Register
Event Q1 Entry 13 Register
Event Q1 Entry 14 Register
Event Q1 Entry 15 Register
Reserved
0x01c0 0404
Q0E1
0x01c0 0408
Q0E2
0x01c0 040C
0x01c0 0410
Q0E3
Q0E4
0x01c0 0414
Q0E5
0x01c0 0418
Q0E6
0x01c0 041C
0x01c0 0420
Q0E7
Q0E8
0x01c0 0424
Q0E9
0x01c0 0428
Q0E10
Q0E11
Q0E12
Q0E13
Q0E14
Q0E15
Q1E0
0x01c0 042C
0x01c0 0430
0x01c0 0434
0x01c0 0438
0x01c0 043C
0x01c0 0440
0x01c0 0444
Q1E1
0x01c0 0448
Q1E2
0x01c0 044C
0x01c0 0450
Q1E3
Q1E4
0x01c0 0454
Q1E5
0x01c0 0458
Q1E6
0x01c0 045C
0x01c0 0460
Q1E7
Q1E8
0x01c0 0464
Q1E9
0x01c0 0468
Q1E10
Q1E11
Q1E12
Q1E13
Q1E14
Q1E15
0x01c0 046C
0x01c0 0470
0x01c0 0474
0x01c0 0478
0x01c0 047C
0x01c0 0480 - 0x01c0 05FF
0x01c0 0600
QSTAT0
QSTAT1
Queue 0 Status Register
0x01c0 0604
Queue 1 Status Register
0x01c0 0608 - 0x01c0 061F
0x01c0 0620
Reserved
QWMTHRA
–
Queue Watermark Threshold A Register for Q[3:0]
Reserved
0x01c0 0624
0x01c0 0640
CCSTAT
EDMA3CC Status Register
Reserved
0x01c0 0644 - 0x01c0 0FFF
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Table 6-30. DM6446 EDMA Registers (continued)
HEX ADDRESS
ACRONYM
Global Channel Registers
REGISTER NAME
0x01c0 1000
0x01c0 1004
0x01c0 1008
0x01c0 100C
0x01c0 1010
0x01c0 1014
0x01c0 1018
0x01c0 101C
0x01c0 1020
0x01c0 1024
0x01c0 1028
0x01c0 102C
0x01c0 1030
0x01c0 1034
0x01c0 1038
0x01c0 103C
0x01c0 1040
0x01c0 1044
0x01c0 1048 - 0x01c0 104F
0x01c0 1050
0x01c0 1054
0x01c0 1058
0x01c0 105C
0x01c0 1060
0x01c0 1064
0x01c0 1068
0x01c0 106C
0x01c0 1070
0x01c0 1074
0x01c0 1078
0x01c0 1080
0x01c0 1084
0x01c0 1088
0x01c0 108C
0x01c0 1090
0x01c0 1094
0x01c0 1098 - 0x01c0 1FFF
ER
ERH
Event Register
Event Register High
Event Clear Register
Event Clear Register High
Event Set Register
ECR
ECRH
ESR
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register High
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
SERH
SECR
SECRH
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
IER
IERH
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
IECR
IECRH
IESR
IESRH
IPR
IPRH
ICR
ICRH
IEVAL
QER
Interrupt Clear Register High
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
Shadow Region 0 Channel Registers
0x01c0 2000
0x01c0 2004
0x01c0 2008
0x01c0 200C
0x01c0 2010
0x01c0 2014
0x01c0 2018
0x01c0 201C
ER
Event Register
ERH
Event Register High
ECR
Event Clear Register
Event Clear Register High
Event Set Register
ECRH
ESR
ESRH
CER
Event Set Register High
Chained Event Register
Chained Event Register High
CERH
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Table 6-30. DM6446 EDMA Registers (continued)
HEX ADDRESS
0x01c0 2020
0x01c0 2024
0x01c0 2028
0x01c0 202C
0x01c0 2030
0x01c0 2034
0x01c0 2038
0x01c0 203C
0x01c0 2040
0x01c0 2044
ACRONYM
EER
REGISTER NAME
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
-
0x01c0 2048 - 0x01c0 204C
0x01c0 2050
IER
Interrupt Enable Register
0x01c0 2054
IERH
IECR
IECRH
IESR
IESRH
IPR
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
0x01c0 2058
0x01c0 205C
0x01c0 2060
0x01c0 2064
0x01c0 2068
0x01c0 206C
0x01c0 2070
IPRH
ICR
0x01c0 2074
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
0x01c0 2078
0x01c0 207C
0x01c0 2080
QER
QDMA Event Register
0x01c0 2084
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01c0 2088
0x01c0 208C
0x01c0 2090
0x01c0 2094
0x01c0 2098 - 0x01c0 21FC
Shadow Region 1 Channel Registers
0x01c0 2200
0x01c0 2204
0x01c0 2208
0x01c0 220C
0x01c0 2210
0x01c0 2214
0x01c0 2218
0x01c0 221C
0x01c0 2220
0x01c0 2224
0x01c0 2228
0x01c0 222C
0x01c0 2230
0x01c0 2234
0x01c0 2238
0x01c0 223C
ER
ERH
Event Register
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
Chained Event Register High
Event Enable Register
CERH
EER
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
SERH
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Table 6-30. DM6446 EDMA Registers (continued)
HEX ADDRESS
0x01c0 2240
ACRONYM
SECR
SECRH
-
REGISTER NAME
Secondary Event Clear Register
0x01c0 2244
Secondary Event Clear Register High
Reserved
0x01c0 2248 - 0x01c0 224C
0x01c0 2250
IER
Interrupt Enable Register
0x01c0 2254
IERH
IECR
IECRH
IESR
IESRH
IPR
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
0x01c0 2258
0x01c0 225C
0x01c0 2260
0x01c0 2264
0x01c0 2268
0x01c0 226C
IPRH
ICR
0x01c0 2270
0x01c0 2274
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
0x01c0 2278
0x01c0 227C
0x01c0 2280
QER
QDMA Event Register
0x01c0 2284
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01c0 2288
0x01c0 228C
0x01c0 2290
0x01c0 2294
0x01c0 2298 - 0x01c0 23FC
Shadow Region 2 Channel Registers
0x01c0 2400
0x01c0 2404
0x01c0 2408
0x01c0 240C
0x01c0 2410
0x01c0 2414
0x01c0 2418
0x01c0 241C
0x01c0 2420
0x01c0 2424
0x01c0 2428
0x01c0 242C
0x01c0 2430
0x01c0 2434
0x01c0 2438
0x01c0 243C
0x01c0 2440
0x01c0 2444
0x01c0 2448 - 0x01c0 244C
0x01c0 2450
0x01c0 2454
0x01c0 2458
0x01c0 245C
0x01c0 2460
ER
ERH
Event Register
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register High
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
-
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
IERH
IECR
IECRH
IESR
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Table 6-30. DM6446 EDMA Registers (continued)
HEX ADDRESS
0x01c0 2464
0x01c0 2468
0x01c0 246C
0x01c0 2470
0x01c0 2474
0x01c0 2478
0x01c0 247C
0x01c0 2480
0x01c0 2484
0x01c0 2488
0x01c0 248C
0x01c0 2490
0x01c0 2494
ACRONYM
IESRH
IPR
REGISTER NAME
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
IPRH
ICR
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
QER
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01c0 2498 - 0x01c0 25FC
Shadow Region 3 Channel Registers
0x01c0 2600
0x01c0 2604
0x01c0 2608
0x01c0 260C
0x01c0 2610
0x01c0 2614
0x01c0 2618
0x01c0 261C
0x01c0 2620
0x01c0 2624
0x01c0 2628
0x01c0 262C
0x01c0 2630
0x01c0 2634
0x01c0 2638
0x01c0 263C
0x01c0 2640
0x01c0 2644
0x01c0 2648 - 0x01c0 264C
0x01c0 2650
0x01c0 2654
0x01c0 2658
0x01c0 265C
0x01c0 2660
0x01c0 2664
0x01c0 2668
0x01c0 266C
0x01c0 2670
0x01c0 2674
0x01c0 2678
0x01c0 267C
0x01c0 2680
ER
ERH
Event Register
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register High
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
-
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
IERH
IECR
IECRH
IESR
IESRH
IPR
IPRH
ICR
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
QER
QDMA Event Register
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Table 6-30. DM6446 EDMA Registers (continued)
HEX ADDRESS
0x01c0 2684
ACRONYM
REGISTER NAME
QDMA Event Enable Register
QEER
0x01c0 2688
QEECR
QDMA Event Enable Clear Register
0x01c0 268C
QEESR
QDMA Event Enable Set Register
0x01c0 2690
QSER
QDMA Secondary Event Register
0x01c0 2694
QSECR
QDMA Secondary Event Clear Register
0x01c0 2698 - 0x01c0 27FC
0x01c0 2800 - 0x01c0 29FC
0x01c0 2A00 - 0x01c0 2BFC
0x01c0 2C00 - 0x01c0 2DFC
0x01c0 2E00 - 0x01c0 2FFC
0x01c0 2FFD - 0x01c0 3FFF
0x01c0 4000 - 0x01c0 4FFF
0x01c0 5000 - 0x01c0 7FFF
0x01c0 8000 - 0x01c0 FFFF
-
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Parameter Set RAM (see Table 6-31)
Reserved
Reserved
Transfer Controller 0 Registers
0x01c1 0000
0x01c1 0004
-
TCCFG
-
Reserved
EDMA3 TC0 Configuration Register
Reserved
0x01c1 0008 - 0x01c1 00FF
0x01c1 0100
TCSTAT
-
EDMA3 TC0 Channel Status Register
Reserved
0x01c1 0104 - 0x01c1 0110
0x01c1 0114 - 0x01c1 011F
0x01c1 0120
-
Reserved
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
EDMA3 TC0 Error Status Register
EDMA3 TC0 Error Enable Register
EDMA3 TC0 Error Clear Register
EDMA3 TC0 Error Details Register
EDMA3 TC0 Error Interrupt Command Register
Reserved
0x01c1 0124
0x01c1 0128
0x01c1 012C
0x01c1 0130
0x01c1 0134 - 0x01c1 013F
0x01c1 0140
RDRATE
-
EDMA3 TC0 Read Rate Register
Reserved
0x01c1 0144 - 0x01c1 01FF
0x01c1 0200 - 0x01c1 023F
0x01c1 0240
-
Reserved
SAOPT
SASRC
SACNT
SADST
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
EDMA3 TC0 Source Active Options Register
EDMA3 TC0 Source Active Source Address Register
EDMA3 TC0 Source Active Count Register
EDMA3 TC0 Source Active Destination Address Register
EDMA3 TC0 Source Active Source B-Index Register
EDMA3 TC0 Source Active Memory Protection Proxy Register
EDMA3 TC0 Source Active Count Reload Register
0x01c1 0244
0x01c1 0248
0x01c1 024C
0x01c1 0250
0x01c1 0254
0x01c1 0258
0x01c1 025C
EDMA3 TC0 Source Active Source Address B-Reference Register
EDMA3 TC0 Source Active Destination Address B-Reference Register
Reserved
0x01c1 0260
0x01c1 0264 - 0x01c1 027F
0x01c1 0280
DFCNTRLD
DFSRCBREF
EDMA3 TC0 Destination FIFO Set Count Reload Register
EDMA3 TC0 Destination FIFO Set Source Address B-Reference Register
0x01c1 0284
EDMA3 TC0 Destination FIFO Set Destination Address B-Reference
Register
0x01c1 0288
DFDSTBREF
0x01c1 028C - 0x01c1 02FF
0x01c1 0300
-
Reserved
DFOPT0
DFSRC0
EDMA3 TC0 Destination FIFO Options Register 0
EDMA3 TC0 Destination FIFO Source Address Register 0
0x01c1 0304
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Table 6-30. DM6446 EDMA Registers (continued)
HEX ADDRESS
0x01c1 0308
0x01c1 030C
0x01c1 0310
0x01c1 0314
ACRONYM
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
REGISTER NAME
EDMA3 TC0 Destination FIFO Count Register 0
EDMA3 TC0 Destination FIFO Destination Address Register 0
EDMA3 TC0 Destination FIFO BIDX Register 0
EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 0
Reserved
0x01c1 0318 - 0x01c1 033F
0x01c1 0340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
EDMA3 TC0 Destination FIFO Options Register 1
EDMA3 TC0 Destination FIFO Source Address Register 1
EDMA3 TC0 Destination FIFO Count Register 1
EDMA3 TC0 Destination FIFO Destination Address Register 1
EDMA3 TC0 Destination FIFO BIDX Register 1
EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 1
Reserved
0x01c1 0344
0x01c1 0348
0x01c1 034C
0x01c1 0350
0x01c1 0354
0x01c1 0358 - 0x01c1 037F
0x01c1 0380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
EDMA3 TC0 Destination FIFO Options Register 2
EDMA3 TC0 Destination FIFO Source Address Register 2
EDMA3 TC0 Destination FIFO Count Register 2
EDMA3 TC0 Destination FIFO Destination Address Register 2
EDMA3 TC0 Destination FIFO BIDX Register 2
EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 2
Reserved
0x01c1 0384
0x01c1 0388
0x01c1 038C
0x01c1 0390
0x01c1 0394
0x01c1 0398 - 0x01c1 03BF
0x01c1 03C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
EDMA3 TC0 Destination FIFO Options Register 3
EDMA3 TC0 Destination FIFO Source Address Register 3
EDMA3 TC0 Destination FIFO Count Register 3
EDMA3 TC0 Destination FIFO Destination Address Register 3
EDMA3 TC0 Destination FIFO BIDX Register 3
EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 3
Reserved
0x01c1 03C4
0x01c1 03C8
0x01c1 03CC
0x01c1 03D0
0x01c1 03D4
0x01c1 03D8 - 0x01c1 03FF
Transfer Controller 1 Registers
0x01c1 0400
0x01c1 0404
-
TCCFG
-
Reserved
EDMA3 TC1 Configuration Register
Reserved
0x01c1 0408 - 0x01c1 04FF
0x01c1 0500
TCSTAT
-
EDMA3 TC1 Channel Status Register
Reserved
0x01c1 0504 - 0x01c1 0510
0x01c1 0514 - 0x01c1 051F
0x01c1 0520
-
Reserved
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
EDMA3 TC1 Error Status Register
EDMA3 TC1 Error Enable Register
EDMA3 TC1 Error Clear Register
EDMA3 TC1 Error Details Register
EDMA3 TC1 Error Interrupt Command Register
Reserved
0x01c1 0524
0x01c1 0528
0x01c1 052C
0x01c1 0530
0x01c1 0534 - 0x01c1 053F
0x01c1 0540
RDRATE
-
EDMA3 TC1 Read Rate Register
Reserved
0x01c1 0544 - 0x01c1 05FF
0x01c1 0600 - 0x01c1 063F
0x01c1 0640
-
Reserved
SAOPT
SASRC
SACNT
SADST
SABIDX
EDMA3 TC1 Source Active Options Register
EDMA3 TC1 Source Active Source Address Register
EDMA3 TC1 Source Active Count Register
EDMA3 TC1 Source Active Destination Address Register
EDMA3 TC1 Source Active Source B-Index Register
0x01c1 0644
0x01c1 0648
0x01c1 064C
0x01c1 0650
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Table 6-30. DM6446 EDMA Registers (continued)
HEX ADDRESS
0x01c1 0654
ACRONYM
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
REGISTER NAME
EDMA3 TC1 Source Active Memory Protection Proxy Register
EDMA3 TC1 Source Active Count Reload Register
0x01c1 0658
0x01c1 065C
EDMA3 TC1 Source Active Source Address B-Reference Register
EDMA3 TC1 Source Active Destination Address B-Reference Register
Reserved
0x01c1 0660
0x01c1 0664 - 0x01c1 067F
0x01c1 0680
DFCNTRLD
DFSRCBREF
EDMA3 TC1 Destination FIFO Set Count Reload Register
EDMA3 TC1 Destination FIFO Set Source Address B-Reference Register
0x01c1 0684
EDMA3 TC1 Destination FIFO Set Destination Address B-Reference
Register
0x01c1 0688
DFDSTBREF
0x01c1 068C - 0x01c1 06FF
0x01c1 0700
-
Reserved
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
EDMA3 TC1 Destination FIFO Options Register 0
EDMA3 TC1 Destination FIFO Source Address Register 0
EDMA3 TC1 Destination FIFO Count Register 0
EDMA3 TC1 Destination FIFO Destination Address Register 0
EDMA3 TC1 Destination FIFO BIDX Register 0
EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 0
Reserved
0x01c1 0704
0x01c1 0708
0x01c1 070C
0x01c1 0710
0x01c1 0714
0x01c1 0718 - 0x01c1 073F
0x01c1 0740
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
EDMA3 TC1 Destination FIFO Options Register 1
EDMA3 TC1 Destination FIFO Source Address Register 1
EDMA3 TC1 Destination FIFO Count Register 1
EDMA3 TC1 Destination FIFO Destination Address Register 1
EDMA3 TC1 Destination FIFO BIDX Register 1
EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 1
Reserved
0x01c1 0744
0x01c1 0748
0x01c1 074C
0x01c1 0750
0x01c1 0754
0x01c1 0758 - 0x01c1 077F
0x01c1 0780
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
EDMA3 TC1 Destination FIFO Options Register 2
EDMA3 TC1 Destination FIFO Source Address Register 2
EDMA3 TC1 Destination FIFO Count Register 2
EDMA3 TC1 Destination FIFO Destination Address Register 2
EDMA3 TC1 Destination FIFO BIDX Register 2
EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 2
Reserved
0x01c1 0784
0x01c1 0788
0x01c1 078C
0x01c1 0790
0x01c1 0794
0x01c1 0798 - 0x01c1 07BF
0x01c1 07C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
EDMA3 TC1 Destination FIFO Options Register 3
EDMA3 TC1 Destination FIFO Source Address Register 3
EDMA3 TC1 Destination FIFO Count Register 3
EDMA3 TC1 Destination FIFO Destination Address Register 3
EDMA3 TC1 Destination FIFO BIDX Register 3
EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 3
Reserved
0x01c1 07C4
0x01c1 07C8
0x01c1 07CC
0x01c1 07D0
0x01c1 07D4
0x01c1 07D8 - 0x01c1 07FF
Table 6-31 shows an abbreviation of the set of registers which make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-32 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
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Table 6-31. EDMA Parameter Set RAM
HEX ADDRESS RANGE
DESCRIPTION
0x01c0 4000 - 0x01c0 401F
0x01c0 4020 - 0x01c0 403F
0x01c0 4040 - 0x01c0 405F
0x01c0 4060 - 0x01c0 407F
0x01c0 4080 - 0x01c0 409F
0x01c0 40A0 - 0x01c0 40BF
...
Parameters Set 0 (8 32-bit words)
Parameters Set 1 (8 32-bit words)
Parameters Set 2 (8 32-bit words)
Parameters Set 3 (8 32-bit words)
Parameters Set 4 (8 32-bit words)
Parameters Set 5 (8 32-bit words)
...
0x01c0 4FC0 - 0x01c0 4FDF
0x01c0 4FE0 - 0x01c0 4FFF
Parameters Set 126 (8 32-bit words)
Parameters Set 127 (8 32-bit words)
Table 6-32. Parameter Set Entries
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
PARAMETER ENTRY
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
OPT
SRC
Option
Source Address
A_B_CNT
DST
A Count, B Count
Destination Address
SRC_DST_BIDX
LINK_BCNTRLD
SRC_DST_CIDX
CCNT
Source B Index, Destination B Index
Link Address, B Count Reload
Source C Index, Destination C Index
C Count
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6.10 External Memory Interface (EMIF)
DM6446 supports several memory and external device interfaces, including:
•
•
•
Asynchronous EMIF (EMIFA) for interfacing to NOR Flash, SRAM, etc.
NAND Flash
ATA/CF
6.10.1 Asynchronous EMIF (EMIFA)
The DM6446 Asynchronous EMIF (EMIFA) provides an 8-bit or 16-bit data bus, an address bus width up
to 24-bits, and 4 dedicated chip selects, along with memory control signals. These signals are multiplexed
between three peripherals:
•
•
•
EMIFA and NAND interfaces
ATA/CF
Host Port Interface
6.10.1.1 NAND (NAND, SmartMedia, xD)
The EMIFA interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are
provided and each are individually configurable to provide either EMIFA or NAND support. The NAND
features supported are as follows.
•
•
•
•
•
NAND flash on up to 4 asynchronous chip selects.
8 and 16-bit data bus widths.
Programmable cycle timings.
Performs ECC calculation.
NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory
cards
•
ARM ROM supports booting of the DM6446 ARM processor from NAND flash located at CS2
The memory map for EMIFA and NAND registers is shown in Table 6-33. For more details on the EMIFA
and NAND interfaces, see the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature
number SPRUE19) and the TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF)
User's Guide (literature number SPRUE20).
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Table 6-33. EMIFA/NAND Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x01E0 0000 - 0x01E0 0003
0x01E0 0004
Reserved
AWCCR
Asynchronous Wait Cycle Configuration Register
Reserved
0x01E0 0008 - 0x01E0 000F
0x01E0 0010
A1CR
A2CR
Asynchronous 1 Configuration Register (CS2 Space)
Asynchronous 2 Configuration Register (CS3 Space)
Asynchronous 3 Configuration Register (CS4 Space)
Asynchronous 4 Configuration Register (CS5 Space)
Reserved
0x01E0 0014
0x01E0 0018
A3CR
0x01E0 001C
A4CR
0x01E0 0020 - 0x01E0 003F
0x01E0 0040
-
EIRR
EMIF Interrupt Raw Register
0x01E0 0044
EIMR
EMIF Interrupt Mask Register
0x01E0 0048
EIMSR
EIMCR
-
EMIF Interrupt Mask Set Register
EMIF Interrupt Mask Clear Register
Reserved
0x01E0 004C
0x01E0 0050 - 0x01E0 005F
0x01E0 0060
NANDFCR
NANDFSR
NANDF1ECC
NANDF2ECC
NANDF3ECC
NANDF4ECC
-
NAND Flash Control Register
0x01E0 0064
NAND Flash Status Register
0x01E0 0070
NAND Flash 1 ECC Register (CS2 Space)
NAND Flash 2 ECC Register (CS3 Space)
NAND Flash 3 ECC Register (CS4 Space)
NAND Flash 4 ECC Register (CS5 Space)
Reserved
0x01E0 0074
0x01E0 0078
0x01E0 007C
0x01E0 0080 - 0x01E0 0FFF
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6.10.1.2 EMIFA Electrical Data/Timing
Table 6-34. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)
(see Figure 6-21 and Figure 6-22)
NO.
MIN
MAX
UNIT
READS and WRITES
Pulse duration, EM_WAIT assertion and deassertion
READS
2
tw(EM_WAIT)
2E
ns
12 tsu(EMDV-EMOEH)
13 th(EMOEH-EMDIV)
14 tsu(EMWAIT-EMOEH)
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
Setup time, EM_WAIT asserted before EM_OE high(2)
WRITES
10.5
0
ns
ns
ns
4E + 10.4
28 tsu(EMWAIT-EMWEH)
Setup time, EM_WAIT asserted before EM_WE high(2)
4E + 10.4
ns
(1) E = SYSCLK5 period in ns for EMIFA. For example, when running the DSP CPU at 594 MHz, use E = 10.1 ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-23 and Figure 6-24 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Table 6-35. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module(1)(2) (see Figure 6-21 and Figure 6-22)
NO.
PARAMETER
MIN
MAX
UNIT
READS and WRITES
READS
1
td(TURNAROUND)
Turn around time
(TA + 1) * E - 2
(TA + 1) * E + 2 ns
(RS + RST + RH + (RS + RST + RH + TA +
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
ns
TA + 4) * E - 0.5
4) * E + 0.5
3
4
5
tc(EMRCYCLE)
(RS + RST + RH +
TA + 4) * E - 0.5
4184 * E + 0.5 ns
Output setup time, EM_CS[5:2] low to EM_OE low (SS
= 0)
(RS + 1) * E - 1
(RS + 1) * E + 1.4 ns
tsu(EMCSL-EMOEL)
Output setup time, EM_CS[5:2] low to EM_OE low (SS
= 1)
-1
(RH + 1) * E - 2.1
-2.2
ns
(RH + 1) * E + 1.4 ns
ns
Output hold time, EM_OE high to EM_CS[5:2] high
(SS = 0)
th(EMOEH-EMCSH)
Output hold time, EM_OE high to EM_CS[5:2] high
(SS = 1)
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMAV-EMOEL)
th(EMOEH-EMAIV)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[21:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[21:0] invalid
EM_OE active low width (EW = 0)
(RS + 1) * E - 1.8
(RH + 1) * E - 2.3
(RS + 1) * E - 1.9
(RH + 1) * E - 2.6
(RST + 1) * E - 2
(RST + 1) * E - 2
(RS + 1) * E + 1.3 ns
(RH + 1) * E + 1.1 ns
(RS + 1) * E + 1.5 ns
(RH + 1) * E + 1.2 ns
(RST + 1) * E + 2 ns
(RST + 4097) * E + 2 ns
4E + 10.4 ns
10 tw(EMOEL)
EM_OE active low width (EW = 1)
11 td(EMWAITH-EMOEH)
Delay time from EM_WAIT deasserted to EM_OE high
WRITES
(WS + WST + WH (WS + WST + WH + TA
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
ns
+ TA + 4) * E - 0.5
+ 4) * E + 0.5
15 tc(EMWCYCLE)
(WS + WST + WH
+ TA + 4) * E -0.5
4184 * E + 0.5 ns
Output setup time, EM_CS[5:2] low to EM_WE low
(SS = 0)
(WS + 1) * E - 0.9
(WS + 1) * E + 1.4 ns
16 tsu(EMCSL-EMWEL)
Output setup time, EM_CS[5:2] low to EM_WE low
(SS = 1)
-1
(WH + 1) * E - 2.1
-2.1
ns
(WH + 1) * E + 1.1 ns
ns
Output hold time, EM_WE high to EM_CS[5:2] high
(SS = 0)
17 th(EMWEH-EMCSH)
Output hold time, EM_WE high to EM_CS[5:2] high
(SS = 1)
18 tsu(EMRNW-EMWEL)
19 th(EMWEH-EMRNW)
20 tsu(EMBAV-EMWEL)
21 th(EMWEH-EMBAIV)
22 tsu(EMAV-EMWEL)
23 th(EMWEH-EMAIV)
Output setup time, EM_R/W valid to EM_WE low
Output hold time, EM_WE high to EM_R/W invalid
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[21:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[21:0] invalid
EM_WE active low width (EW = 0)
(WS + 1) * E - 0.7
(WH + 1) * E - 0.9
(WS + 1) * E - 1.7
(WH + 1) * E - 2.3
(WS + 1) * E - 1.8
(WH + 1) * E - 2.6
(WST + 1) * E - 2
(WST + 1) * E - 2
(WS + 1) * E + 0.9 ns
(WH + 1) * E + 0.9 ns
(WS + 1) * E + 1.5 ns
(WH + 1) * E + 0.9 ns
(WS + 1) * E + 1.7 ns
(WH + 1) * E + 1 ns
(WST + 1) * E + 2 ns
(WST + 4097) * E + 2
4E + 10.4 ns
24 tw(EMWEL)
EM_WE active low width (EW = 1)
25 td(EMWAITH-EMWEH)
26 tsu(EMDV-EMWEL)
27 th(EMWEH-EMDIV)
Delay time from EM_WAIT deasserted to EM_WE high
Output setup time, EM_D[15:0] valid to EM_WE low
Output hold time, EM_WE high to EM_D[15:0] invalid
(WS + 1) * E - 2.2
(WH + 1) * E - 2.2
(WS + 1) * E + 1.4 ns
(WH + 1) * E + 1.4 ns
(1) RS = Read setup, RST = Read STrobe, RH = Read Hold, WS = Write Setup, WST = Write STrobe, WH = Write Hold, TA = Turn
Around, EW = Extend Wait mode, SS = Select Strobe mode. These parameters are programmed via the Asynchronous Bank and
Asynchronous Wait Cycle Configuration Registers and support the following range of values: TA[3:0], RS[15:0], RST[63:0], RH[7:0],
WS[15:0], WST[63:0], WH[7:0], and EW[255:0]. For more information, see the TMS320DM644x DMSoC Asynchronous External Memory
Interface (EMIF) User's Guide (literature number SPRUE20).
(2) E = SYSCLK5 period in ns for EMIFA. For example, when running the DSP CPU at 594 MHz, use E = 10.1 ns.
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SETUP
STROBE
HOLD
3
1
EM_CS[5:2]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
4
8
5
9
7
6
10
EM_OE
13
12
EM_D[15:0]
EM_WE
Figure 6-21. Asynchronous Memory Read Timing for EMIF
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SETUP
STROBE
HOLD
15
1
EM_CS[5:2]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
16
18
20
22
17
19
21
23
24
EM_WE
27
26
EM_D[15:0]
EM_OE
Figure 6-22. Asynchronous Memory Write Timing for EMIF
SETUP
STROBE
Extended Due to EM_WAIT
STROBE HOLD
EM_CS[5:2]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
14
11
EM_OE
2
2
Asserted
Deasserted
EM_WAIT
Figure 6-23. EM_WAIT Read Timing Requirements
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SETUP
STROBE
Extended Due to EM_WAIT
STROBE HOLD
EM_CS[5:2]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
28
25
EM_WE
2
2
Asserted
Deasserted
EM_WAIT
Figure 6-24. EM_WAIT Write Timing Requirements
6.10.2 DDR2 Memory Controller
The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A
standard compliant DDR2 SDRAM Devices and can interface to either 16-bit or 32-bit DDR2 SDRAM
devices. For details on the DDR2 Memory Controller, see Section 2.8.3, Document Support for the link to
the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature number SPRUE19) for the
TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (literature number SPRUE22).
DDR2 SDRAM plays a key role in a DaVinci-based system. Such a system is expected to require a
significant amount of high-speed external memory for:
•
•
•
•
Buffering of input image data from sensors or video sources
Intermediate buffering for processing/resizing of image data in the VPFE
Numerous OSD display buffers
Intermediate buffering for large raw Bayer data image files while performing image processing
functions
•
•
Buffering for intermediate data while performing video encode and decode functions
Storage of executable code for both the ARM and DSP
A memory map of the DDR2 Memory Controller registers is shown in Table 6-36.
Table 6-36. DDR2 Memory Controller Registers
HEX ADDRESS RANGE
0x01C4 004C
ACRONYM
DDRVTPER
DDRVTPR
-
REGISTER NAME
DDR2 VTP Enable Register
DDR2 VTP Register
Reserved
0x01C4 2030
0x2000 0000 - 0x2000 0003
0x2000 0004
SDRSTAT
SDBCR
SDRCR
SDTIMR
SDTIMR2
PBBPR
-
SDRAM Status Register
0x2000 0008
SDRAM Bank Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register
0x2000 000C
0x2000 0010
0x2000 0014
SDRAM Timing Register 2
Peripheral Bus Burst Priority Register
Reserved
0x2000 0020
0x2000 0024 - 0x2000 00BF
0x2000 00C0
IRR
Interrupt Raw Register
0x2000 00C4
IMR
Interrupt Masked Register
Interrupt Mask Set Register
0x2000 00C8
IMSR
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Table 6-36. DDR2 Memory Controller Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x2000 00CC
IMCR
Interrupt Mask Clear Register
Reserved
0x2000 00D0 - 0x2000 00E3
0x2000 00E4
-
DDRPHYCR
DDR PHY Control Register
Reserved
0x2000 00E8 - 0x2000 00EF
0x2000 00F0
-
VTPIOCR
-
VTP IO Control Register
Reserved
0x2000 00F4 - 0x2000 7FFF
6.10.2.1 DDR2 Memory Controller Electrical Data/Timing
The Implementing DDR2 PCB Layout on the DM644x DMSoC application report (literature number
SPRAAC5) specifies a complete DDR2 interface solution for the DM6446 as well as a list of compatible
DDR2 devices. TI has performed the simulation and system characterization to ensure all DDR2 interface
timings in this solution are met.
TI only supports board designs that follow the guidelines outlined in the Implementing DDR2 PCB Layout
on the DM644x DMSoC application report (literature number SPRAAC5).
Table 6-37. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller(1)(2)(see Figure 6-25)
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(DDR_CLK0)
Cycle time, DDR_CLK0
6
8
ns
(1) DDR_CLK0 cycle time = 2 x PLL2 - SYSCLK2 cycle time.
(2) The PLL2 Controller must be programmed such that the resulting DDR_CLK0 clock frequency is within the specified range.
1
DDR_CLK0
Figure 6-25. DDR2 Memory Controller Clock Timing
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6.11 ATA/CF
The ATA/CF peripheral supports the following features:
•
•
•
•
•
•
PIO, multiword DMA, and Ultra ATA 33/66
Up to mode 4 timings on PIO mode
Up to mode 2 timings on multiword DMA
Up to mode 4 timings on Ultra ATA
Programmable timing parameters
Supports TrueIDE mode for Compact Flash
In addition, the Host IDE Controller supports multiword DMA transfers between external IDE/ATAPI
devices and a system memory bus interface.
6.11.1 ATA/CF Peripheral Register Description(s)
The ATA registers are shown in Table 6-38.
Table 6-38. ATA Register Memory Map
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
ATA Bus Master Interface DMA Engine Registers
Primary IDE Channel DMA Control Register
Primary IDE Channel DMA Status Register
0x01C6 6000
0x01C6 6002
0x01C6 6004
0x01C6 6008
0x01C6 600A
0x01C6 600C
BMICP
BMISP
BMIDTP
Primary IDE Channel DMA Descriptor Table Pointer Register
-
-
-
Reserved
ATA Configuration Registers
0x01C6 6040
0x01C6 6042
0x01C6 6044
0x01C6 6045
0x01C6 6047
0x01C6 6048
0x01C6 604A
0x01C6 6050
0x01C6 6054
0x01C6 6058
0x01C6 605C
0x01C6 6060
0x01C6 6064
0x01C6 6068
0x01C6 606C
0x01C6 6070
0x01C6 6074
0x01C6 6078
0x01C6 607C - 0x01C6 67FF
IDETIMP
-
Primary IDE Channel Timing Register
-
Reserved
-
IDESTAT
UDMACTL
-
IDE Controller Status Register
Ultra-DMA Control Register
Reserved
MISCCTL
REGSTB
REGRCVR
DATSTB
DATRCVR
DMASTB
DMARCVR
UDMASTB
UDMATRP
Miscellaneous Control Register
Task File Register Strobe Timing Register
Task File Register Recovery Timing Register
Data Register Access PIO Strobe Timing Register
Data Register Access PIO Recovery Timing Register
Multiword DMA Strobe Timing Register
Multiword DMA Recovery Timing Register
Ultra-DMA Strobe Timing Register
Ultra-DMA Ready-to-Pause Timing Register
UDMATENV Ultra-DMA Timing Envelope Register
IORDYTMP
-
Primary IO Ready Timer Configuration Register
Reserved
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6.11.2 ATA/CF Electrical Data/Timing
All ATA/CF AC timing data described in Section 6.11.2.1 – Section 6.11.2.3 is provided at the DM6446
device pins. For more details, see Section 6.1, Parameter Information.
The AC timing specifications described in Section 6.11.2.1 – Section 6.11.2.3 assume correct
configuration of the ATA/CF memory-mapped control registers for the selected ATA/CF frequency of
operation.
6.11.2.1 ATA/CF PIO Data Transfer AC Timing
Table 6-39. Timings for ATA/CF Module — PIO Data Transfer(1)(2) (see Figure 6-26)
NO.
1
MODE
0-4(3)
0-4(3)
0-4(3)
0-2
MIN
(DATSTB + DATRCVR + 2)P -0.5
12P - 1.6
MAX
UNIT
ns
t0
t1
t2
Cycle time
2
Address valid to DIOW/ DIOR setup
DIOW/ DIOR pulse duration low
ns
3
(DATSTB + 1)P - 1
–
ns
ns
4
t2i
DIOW/DIOR recovery time, pulse duration high
3-4(3)
(DATRCVR + 1)P - 1
ns
DIOW data setup time, DD[15:0] valid before
DIOW rising edge
5
6
t3
t4
0-4(3)
0-4(3)
(DATSTB + 1)P
ns
DIOW data hold time, DD[15:0] valid after DIOW
rising edge
(HWNHLD + 1)P + 1
ns
0
1
50
35
20
ns
ns
ns
DIOR data setup time, DD[15:0] valid before DIOR
rising edge
7
t5
2-4(3)
DIOR data hold time, DD[15:0] valid after DIOR
rising edge
8
9
t6
0-4(3)
5
ns
Output data 3-state, DD[15:0] 3-state after DIOR
rising edge
t6Z
0-4(3)
0-4(3)
0-4(3)
30
ns
ns
ns
10 t9
DIOW/DIOR to address valid hold
(HWNHLD + 1)P - 2.1
0
Read data setup time, DD[15:0] valid before
IORDY active
11 tRD
12 tA
13 tB
14 tC
IORDY setup
0-4(3)(4)
0-4(3)
0-4(3)
35
1250
5
ns
ns
ns
IORDY pulse width
IORDY assertion to release
(1) P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 594 MHz, use P = 10.1 ns.
(2) DATSTB equals the value programmed in the DATSTBxP bit field in the DATSTB register. DATRCVR equals the value programmed in
the DATRCVRxP bit field in the DATRCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the
MISCCTL register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number
SPRUE21).
(3) The sustained throughput for PIO modes 3 and 4 is limited to the throughput equivalent of PIO mode 2. For more detailed information,
see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number SPRUE21).
(4) The tA parameter must be met only when the IORDY timer is enabled to allow a device to insert wait states during a transaction. In order
to meet the tA parameter, a minimum frequency for SYSCLK5 is specified for each PIO as follows:
•
•
•
•
•
PIO mode 0, MIN frequency = 15 MHz
PIO mode 1, MIN frequency = 22 MHz
PIO mode 2, MIN frequency = 31 MHz
PIO mode 3, MIN frequency = 45 MHz
PIO mode 4, MIN frequency = 57 MHz
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t
0
DA[2:0],
ATA_CS0,
ATA_CS1
t
1
t
2
t
9
DIOW/DIOR
t
2i
t
3
t
4
DD[15:0](OUT)
t
6
t
5
DD[15:0] (IN)
t
6Z
(A)
IORDY
t
A
t
RD
t
C
(B)
IORDY
t
C
t
B
(C)
IORDY
A. IORDY is not negated for transfer (no wait generated)
B. IORDY is negative but is re-asserted before t (no wait is generated)
A
C. IORDY is negative before t and remains asserted until t ; data is driven valid at t (wait is generated)
A
B
RD
Figure 6-26. ATA/CF PIO Data Transfer Timing
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6.11.2.2 ATA/CF Multiword DMA Timing
Table 6-40. Timings for ATA/CF Module — Multiword DMA AC Timing(1)(2) (see Figure 6-27)
NO.
1
MODE
MIN
MAX
UNIT
ns
t0
Cycle time
0-2
0-2
0
(DMASTB + DMARCVR + 2)P - 0.5
(DMASTB + 1)P - 1
2
tD
DIOW/DIOR active low pulse duration
ns
150
ns
DIOR data access, DIOR falling edge to DD[15:0]
valid
3
4
tE
1
60
50
ns
2
ns
DIOR data hold time, DD[15:0] valid after DIOR
rising edge
tF
0-2
0-2
5
ns
ns
DIOW/DIOR data setup time, DD[15:0] (OUT) valid
before DIOW/DIOR rising edge
(DMASTB)P
0
1
2
100
30
ns
ns
ns
5
6
tG
DIOW/DIOR data setup time, DD[15:0] (IN) valid
before DIOW/DIOR rising edge
20
DIOW data hold time, DD[15:0] valid after DIOW
rising edge
tH
0-2
(HWNHLD + 1)P + 1
ns
7
8
9
tI
DMACK to DIOW/DIOR setup
DIOW/DIOR to DMACK hold
DIOR negated pulse width
DIOW negated pulse width
0-2
0-2
0-2
0-2
0
(DMARCVR + 1)P - 1.7
5P - 5.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJ
tKR
(DMARCVR + 1)P - 1
(DMARCVR + 1)P - 1
10 tKW
120
45
35
40
35
11 tLR
DIOR to DMARQ delay
1
2
0-1
2
12 tLW
DIOW to DMARQ delay
13 tM
14 tN
ATA_CSx valid to DIOW/DIOR setup
0-2
0-2
0
(DATRCVR)P - 1.7
5P - 1.7
ATA_CSx valid after DIOW/DIOR rising edge hold
20
25
15 tZ
DMACK to read data (DD[15:0]) released
1-2
(1) P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 594 MHz, use P = 10.1 ns.
(2) DMASTB equals the value programmed in the DMASTBxP bit field in the DMASTB register. DMARCVR equals the value programmed
in the DMARCVRxP bit field in the DMARCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the
MISCCTL register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number
SPRUE21).
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DA[2:0],
ATA_CS0,
ATA_CS1
t
0
t
M
t
N
DMARQ
DMACK
t
L
t
I
t
J
t
D
t
K
DIOW/DIOR
t
H
t
G
DD[15:0](OUT)
t
G
t
Z
t
F
t
E
DD[15:0] (IN)
Figure 6-27. ATA/CF Multiword DMA Timing
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6.11.2.3 ATA/CF Ultra DMA Timing
Table 6-41. Timings for ATA/CF Module — Ultra DMA AC Timing(1)(2)
(see Figure 6-28 through Figure 6-37)
NO.
MODE
MIN
MAX
UNIT
MHz
ns
28 f(SYSCLK5)
Operating frequency, SYSCLK5
0-4
0
25
240
1
160
ns
1
t2CYCTYP
Typical sustained average two cycle time
2
120
ns
3
90
60
ns
4
ns
2
3
tCYC
Cycle time, Strobe edge to Strobe edge
0-4
(UDMASTB + 1)P
ns
Two cycle time, rising to rising edge or falling to
falling edge
t2CYC
0-4
2(UDMASTB + 1)P
ns
0
1
15
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
5
tDS
Data setup, data valid before STROBE edge
Data hold, data valid after STROBE edge
2-3
4
5
tDH
0-4
0
5
70
48
31
20
6.7
1
Data valid INPUT setup time, data valid before
STROBE
2
6
tDVS
3
4
Data valid OUTPUT setup time, data valid before
STROBE
0-4
0-4
0-4
0-4
0-4
0-4
(UDMASTB)P - 3.1
ns
ns
ns
ns
ns
ns
Data valid INPUT hold time, data valid after
STROBE
6.2
7
tDVH
Data valid OUTPUT hold time, data valid after
STROBE
1P - 2
CRC word valid setup time at host, CRC valid
before DMACK negation
10 tCVS
11 tCVH
12 tZFS
(UDMASTB)P
CRC word valid hold time at sender, CRC valid
after DMACK negation
2P
0
Time from STROBE output released-to-driving
until the first transition of critical timing
0
1
70
48
31
20
6.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Time from data output released-to-driving until
the first transition of critical timing
13 tDZFS
2
3
4
0
230
200
170
130
120
150
1
14 tFS
First STROBE time
2
3
4
15 tLI
Limited interlock time
0-4
0-4
0
16 tMLI
Interlock time with minimum
20
(1) P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 594 MHz, use P = 10.1 ns.
(2) UDMASTB equals the value programmed in the UDMSTBxP bit field in the UDMASTB register. UDMATRP equals the value
programmed in the UDMTRPxP bit field in the UDMATRP register. TENV equals the value programmed in the UDMATNVxP bit field in
the UDMATENV register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature
number SPRUE21).
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Table 6-41. Timings for ATA/CF Module — Ultra DMA AC Timing
(see Figure 6-28 through Figure 6-37) (continued)
NO.
MODE
MIN
MAX
UNIT
17 tUI
Unlimited interlock time
0-4
0
ns
Maximum time allowed for output drivers to
release
18 tAZ
19 tZAH
20 tZAD
0-4
0-4
0-4
10
ns
ns
ns
Minimum delay time required for output
20
0
Minimum delay time for driver to assert or negate
(from released)
Envelope time, DMACK to STOP and DMACK to
HDMARDY during in-burst initiation and from
DMACK to STOP during data out burst initiation
21 tENV
0-4
(TENV + 1)P - 0.5
(TENV + 1)P + 1.4
ns
0
1
75
70
60
ns
ns
ns
22 tRFS
Ready-to-final-STROBE time
2-4
Ready to pause time, (HDMARDY (DIOR) to
STOP (DIOW))
0-4
(UDMATRP + 1)P - 0.8
ns
0
160
125
100
ns
ns
ns
ns
ns
23 tRP
Ready to pause time, (DDMARDY (IORDY) to
DMARQ)
1
2-4
0-4
0-4
24 tIORDYZ
25 tZIORDY
Maximum time before releasing IORDY
Minimum time before driving IORDY
20
0
Setup and hold time for DMACK (before
assertion or negation)
26 tACK
0-4
20
ns
STROBE edge to negation of DMARQ or
assertion of STOP (when sender terminates a
burst)
27 tSS
0-4
50
ns
DMARQ
t
UI
t
FS
DMACK
t
ACK
t
ENV
t
ZAD
(A)
STOP (DIOW)
t
ACK
t
ENV
t
FS
(A)
(A)
HDMARDY (DIOR)
t
ZIORDY
t
ZAD
t
ZFS
DSTROBE (IORDY)
t
DZFS
t
t
DVH
t
AZ
DVS
DD[15:0]
t
ACK
DA[2:0],
ATA_CS0,
ATA_CS1
A. The definitions for the DIOW:STOP, DIOR:HDMARDY, and IORDY:DSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
Figure 6-28. ATA/CF Initiating an Ultra DMA Data-In Burst Timing
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t
2CYC
(A)
CYC
t
(A)
CYC
t
DSTROBE
(IORDY)
t
DS
t
DH
t
DS
t
DH
t
DH
DD[15:0]
A. While DSTROBE (IORDY) timing is tCYC at the device, it may be different at the host due to propagation delay
differences on the cable.
Figure 6-29. ATA/CF Sustained Ultra DMA Data-In Data Transfer Timing
DMARQ
DMACK
STOP (DIOW)
t
RP
HDMARDY
(DIOR)
t
RFS
DSTROBE
(IORDY)
DD[15:0]
Figure 6-30. ATA/CF Host Pausing an Ultra DMA Data-In Burst Timing
DMARQ
DMACK
t
MLI
t
LI
t
ACK
t
LI
STOP (DIOW)
t
LI
t
ACK
HDMARDY
(DIOR)
t
SS
t
IORDYZ
DSTROBE
(IORDY)
t
t
ZAH
CVH
t
t
AZ
CVS
CRC
DD[15:0]
t
ACK
DA[2:0],
ATA_CS0,
ATA_CS1
Figure 6-31. ATA/CF Device Terminating an Ultra DMA Data-In Burst Timing
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DMARQ
t
LI
t
MLI
DMACK
t
ACK
t
RP
STOP (DIOW)
t
ZAH
t
ACK
t
AZ
HDMARDY
t
LI
(DIOR)
t
t
MLI
RFS
t
IORDYZ
DSTROBE
(IORDY)
t
CVS
t
CVH
CRC
DD[15:0]
t
ACK
DA[2:0],
ATA_CS0,
ATA_CS1
Figure 6-32. ATA/CF Host Terminating an Ultra DMA Data-In Burst Timing
DMARQ
t
UI
DMACK
t
ACK
t
ENV
(A)
STOP (DIOW)
t
LI
t
t
UI
ZIORDY
(A)
(A)
DDMARDY (IORDY)
HSTROBE (DIOR)
t
ACK
t
DZFS
t
DVH
t
DVS
DD[15:0]
t
ACK
DA[2:0],
ATA_CS0,
ATA_CS1
A. The definitions for the DIOW:STOP, IORDY:DDMARDY, and DIOR:HSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
Figure 6-33. ATA/CF Initiating an Ultra DMA Data-Out Burst Timing
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t
2CYC
t
2CYC
(A)
CYC
t
(A)
CYC
t
HSTROBE (DIOR)
t
DVS
t
DVH
t
DVH
t
t
DVS
DVH
DD[15:0] (OUT)
A. While HSTROBE (DIOR) timing is tCYC at the host, it may be different at the device due to propagation delay
differences on the cable.
Figure 6-34. ATA/CF Sustained Ultra DMA Data-Out Transfer Timing
DMARQ
t
RP
DMACK
STOP (DIOW)
DDMARDY (IORDY)
t
RFS
HSTROBE
(DIOR)
DD[15:0]
Figure 6-35. ATA/CF Device Pausing an Ultra DMA Data-Out Burst Timing
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t
LI
DMARQ
DMACK
t
MLI
t
LI
t
ACK
t
SS
STOP (DIOW)
t
LI
t
IORDYZ
DDMARDY (IORDY)
HSTROBE (DIOR)
t
ACK
t
CVS
t
CVH
DD[15:0]
CRC
t
ACK
DA[2:0],
ATA_CS0, ATA_CS1
Figure 6-36. ATA/CF Host Terminating an Ultra DMA Data-Out Burst Timing
DMARQ
DMACK
t
t
LI
ACK
t
MLI
STOP (DIOW)
t
RP
t
IORDYZ
DDMARDY
(IORDY)
t
RFS
t
ACK
t
LI
t
MLI
HSTROBE
(DIOR)
t
CVS
t
CVH
DD[15:0]
CRC
t
ACK
DA[2:0],
ATA_CS0,
ATA_CS1
Figure 6-37. ATA/CF Device Terminating an Ultra DMA Data-Out Burst Timing
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6.11.2.4 ATA/CF HDDIR Timing
Figure 6-38 through Figure 6-41 show the behavior of HDDIR for the different types of transfers.
Table 6-42. Timing Requirements for HDDIR(1)
NO.
MIN
E - 3.1
MAX
UNIT
1
tc
Cycle time, ATA_CS[1:0] to HDDIR low
2.1
ns
(1) E = ATA clock cycle
DA[2:0],
ATA_CS0,
ATA_CS1
(A)
t
C
(A)
t
C
HDDIR
DIOW
DD[15:0] (OUT)
A.
t
C
≥ one cycle
Figure 6-38. ATA/CF HDDIR Taskfile Write/Single PIO Write Timing
DA[2:0],
ATA_CS0,
ATA_CS1
(A)
t
C
(A)
t
C
HDDIR
DIOW
DD[15:0] (OUT)
A.
t ≥ one cycle
C
Figure 6-39. ATA/CF HDDIR PIO Postwrite Start Timing
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DA[2:0],
ATA_CS0,
ATA_CS1
DMACK
HDDIR
(A)
(A)
t
C
t
C
DIOW
DD[15:0] (OUT)
A.
t
C
≥ one cycle
Figure 6-40. ATA/CF HDDIR Multiword DMA Write Transfer Timing
DA[2:0],
ATA_CS0,
ATA_CS1
DMACK
HDDIR
(A)
t
C
DIOW
DD[15:0] (OUT)
A. ≥ one cycle
CRC
t
C
Figure 6-41. ATA/CF HDDIR Ultra DMA Write Transfer Timing
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6.12 MMC/SD/SDIO
The DM6446 MMC/SD/SDIO Controller has following features:
•
•
•
•
•
•
MultiMediaCard (MMC).
Secure Digital (SD) memory card with Secure Data I/O (SDIO).
MMC/SD/SDIO protocol support.
Programmable clock frequency.
256 bit Read/Write FIFO to lower system overhead.
Slave DMA transfer capability.
SDIO is only supported for WLAN operation through TI third parties. For more information about
third-party WLAN products, go to http://www.ti.com.davinciwlan.
The MMC/SD/SDIO register memory mapping is shown in Table 6-43.
6.12.1 MMC/SD/SDIO Peripheral Description(s)
Table 6-43. MMC/SD/SDIO Register Descriptions
HEX ADDRESS RANGE
0x01E1 0000
ACRONYM
MMCCTL
REGISTER NAME
MMC Control Register
0x01E1 0004
MMCCLK
MMCST0
MMCST1
MMCIM
MMC Memory Clock Control Register
MMC Status Register 0
0x01E1 0008
0x01E1 000C
MMC Status Register 1
0x01E1 0010
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive Register
MMC Data Transmit Register
MMC Command Register
0x01E1 0014
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRR
MMCDXR
MMCCMD
MMCARGHL
MMCRSP01
MMCRSP23
MMCRSP45
MMCRSP67
MMCDRSP
-
0x01E1 0018
0x01E1 001C
0x01E1 0020
0x01E1 0024
0x01E1 0028
0x01E1 002C
0x01E1 0030
0x01E1 0034
MMC Argument Register
0x01E1 0038
MMC Response Register 0 and 1
MMC Response Register 2 and 3
MMC Response Register 4 and 5
MMC Response Register 6 and 7
MMC Data Response Register
Reserved
0x01E1 003C
0x01E1 0040
0x01E1 0044
0x01E1 0048
0x01E1 004C - 0x01E1 004F
0x01E1 0050
MMCCIDX
-
MMC Command Index Register
Reserved
0x01E1 0054 - 0x01E1 0063
0x01E1 0064 - 0x01E1 006C
0x01E1 0070
SDIO
-
Reserved
0x01E1 0074
MMCFIFOCTL
-
MMC FIFO Control Register
Reserved
0x01E1 0078 - 0x01E1 FFFF
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6.12.2 MMC/SD/SDIO Electrical Data/Timing
Table 6-44. Timing Requirements for MMC/SD/SDIO Module
(see Figure 6-43 and Figure 6-45)
STANDARD MODE
NO.
UNIT
MIN
5
MAX
1
2
3
4
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
Setup time, SD_CMD valid before SD_CLK high
ns
ns
ns
ns
Hold time, SD_CMD valid after SD_CLK high
Setup time, SD_DATx valid before SD_CLK high
Hold time, SD_DATx valid after SD_CLK high
5
5
5
Table 6-45. Switching Characteristics Over Recommended Operating Conditions for MMC/SD/SDIO
Module(1) (see Figure 6-42 through Figure 6-45)
STANDARD MODE
NO.
PARAMETER
UNIT
MIN
0
MAX
25
7
f(CLK)
Operating frequency, SD_CLK
MHz
KHz
ns
8
f(CLK_ID)
tW(CLKL)
tW(CLKH)
tr(CLK)
Identification mode frequency, SD_CLK
Pulse width, SD_CLK low
0
400
9
10
10
10
11
12
13
14
Pulse width, SD_CLK high
ns
Rise time, SD_CLK
10
10
13
13
ns
tf(CLK)
Fall time, SD_CLK
ns
td(CLKLL-CMD)
tdis(CLKL-DAT)
Delay time, SD_CLK low to SD_CMD transition
Disable time, SD_CLK low to SD_DATx transition
-7.5
-7.5
ns
ns
(1) P = Period of SD_CLK (SYSCLK5), in nanoseconds (ns).
9
10
7
SD_CLK
13
13
13
13
START
XMIT
Valid
Valid
Valid
END
SD_CMD
Figure 6-42. MMC/SD/SDIO Host Command Timing
9
10
7
SD_CLK
SD_CMD
1
2
Valid
START
XMIT
Valid
Valid
END
Figure 6-43. MMC/SD/SDIO Card Response Timing
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9
10
7
SD_CLK
14
14
14
Dx
14
SD_DATx
START
D0
D1
END
Figure 6-44. MMC/SD/SDIO Host Write Timing
9
10
7
SD_CLK
4
4
3
Start
3
SD_DATx
D0
D1
Dx
End
Figure 6-45. MMC/SD/SDIO Host Read and Card CRC Status Timing
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6.13 Video Processing Sub-System (VPSS) Overview
The DM6446 Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input
interface for external imaging peripherals (i.e., image sensors, video decoders, etc.) and a Video
Processing Back End (VPBE) output interface for display devices, such as analog SDTV displays, digital
LCD panels, HDTV video encoders, etc.
Note: The VPSS module is supported with Linux Application Peripheral Interfaces (APIs) commonly used
by video application developers. Video for Linux 2 or V4L2 uses APIs commonly used for video capture.
The typical use cases of the VPSS Video Front-End (VPFE) have been ported to this Linux API structure.
V4L2 supports standard video interfaces such as: BT.656 and Y/C mode. Other modules within the VPSS
VPFE for example, the Preview Engine, H3A, and Histogram are not currently supported within the
software APIs. The VPSS Back-End (VPBE) uses FBDev/DirectFB as the APIs. Certain functionalities
within the VPBE have not been implemented in the FBDev/DirectFB APIs. For modes/functions not
implemented in software, it is the user's responsibility to modify the software drivers/APIs.
The VPSS register memory mapping is shown in Table 6-46.
Table 6-46. VPSS Register Descriptions
HEX ADDRESS
REGISTER ACRONYM
DESCRIPTION
RANGE
0x01C7 3400
0x01C7 3404
0x01C7 3408
0x01C7 3508
PID
Peripheral Revision and Class Information
VPSS Control Register
PCR
-
Reserved
SDR_REG_EXP
-
SDRAM Non Real-Time Read Request Expand
Reserved
0x01C7 350C -
0x01C7 3FFF
To ensure NTSC- and PAL-compliant output video, the stability of the input clock source is very important.
TI recommends a 27-MHz, 50-ppm crystal. Ceramic oscillators are not recommended. The NTSC/PAL
color sub-carrier frequency is derived from the 27-MHz clock. Therefore, if the 27-MHz clock drifts, then
the color sub-carrier frequency will drift as well. Assuming no 27-MHz frequency drift, the color sub-carrier
frequency is generated as follows:
35
æ
ç
è
ö
÷
ø
fsc-ntsc = 27 MHz
= 3.5795454545 MHz
264
167
æ
ö
fsc-pal = 27 MHz
= 4.4332628318 MHz
ç
÷
1017
è
ø
To ensure the color sub-carrier frequency will not drift out of spec, the user must follow the crystal
requirements discussed in Section 6.5.1, Clock Input Option 1 – Crystal or Ceramic Resonator.
Alternatively, if the VPBE input clock is sourced from the VPBECLK or VPFE clock inputs, these clocks
must have a frequency stability of ± 50 ppm to ensure the NTSC and PAL compliant output video.
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6.13.1 Video Processing Front-End (VPFE)
The Video Processing Front-End (VPFE) consists of the CCD Controller (CCDC), Preview Engine,
Resizer, Hardware 3A (H3A) Statistic Generator, and Histogram blocks. Together, these modules provide
DM6446 with a powerful and flexible front-end interface. These modules are briefly described below:
•
•
The CCDC provides an interface to image sensors and digital video sources.
The Preview Engine is a parameterized hardwired image processing block which is used for converting
RAW color data from a Bayer pattern to YUV 4:2:2.
•
•
The Resizer module re-sizes the input image data to the desired display or video encoding resolution
The H3A module provides control loops for Auto Focus (AF), Auto White Balance (AWB) and Auto
Exposure (AE).
•
The Histogram module bins input color pixels, depending on the amplitude, and provides statistics
required to implement various 3A (AE/AF/AWB) algorithms and tune the final image/video output.
The VPFE register memory mapping is shown in Table 6-47.
Table 6-47. VPFE Register Address Range Descriptions
HEX ADDRESS RANGE
0x01C7 0400 – 0x01C7 07FF
0x01C7 0800 – 0x01C7 0BFF
0x01C7 0C00 – 0x01C7 09FF
0x01C7 1000 – 0x01C7 13FF
0x01C7 1400 – 0x01C7 17FF
0x01C7 3400 – 0x01C7 3FFF
ACRONYM
CCDC
REGISTER NAME
VPFE – CCD Controller
PREV
RESZ
HIST
H3A
VPFE – Preview Engine/Image Signal Processor
VPFE – Resizer
VPFE – Histogram
VPFE – Hardware 3A (Auto-Focus/WB/Exposure)
VPSS Shared Buffer Logic Registers
VPSS
6.13.1.1 CCD Controller (CCDC)
The CCDC receives raw image/video data from sensors (CMOS or CCD) or YUV video data in numerous
formats from video decoder devices. The following features are supported by the CCDC module.
•
•
Conventional Bayer pattern formats.
Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to an
external timing generator.
•
•
•
•
•
•
•
•
•
Interface to progressive and interlaced sensors.
REC656/CCIR-656 standard (YCbCr 4:2:2 format, either 8- or 16-bit).
YCbCr 4:2:2 format, either 8- or 16-bit with discrete H and VSYNC signals.
Up to 16-bit input.
Optical black clamping signal generation.
Shutter signal control.
Digital clamping and black level compensation.
10-bit to 8-bit A-law compression.
Low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left and right
edges of each line are cropped from the output.
•
•
•
•
Output range from 16-bits to 8-bits wide (8-bits wide allows for 50% saving in storage area).
Downsampling via programmable culling patterns.
Control output to the DDR2 via an external write enable signal.
Up to 16K pixels (image size) in both the horizontal and vertical direction.
The CCDC register memory mapping is shown in Table 6-48.
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Table 6-48. CCDC Register Descriptions
HEX ADDRESS RANGE
0x01C7 0400
0x01C7 0404
0x01C7 0408
0x01C7 040C
0x01C7 0410
0x01C7 0414
0x01C7 0418
0x01C7 041C
0x01C7 0420
0x01C7 0424
0x01C7 0428
0x01C7 042C
0x01C7 0430
0x01C7 0434
0x01C7 0438
0x01C7 043C
0x01C7 0440
0x01C7 0444
0x01C7 0448
0x01C7 044C
0x01C7 0450
0x01C7 0454
0x01C7 0458
0x01C7 045C
0x01C7 0460
0x01C7 0464
0x01C7 0468
0x01C7 046C
0x01C7 0470
0x01C7 0474
0x01C7 0478
0x01C7 047C
0x01C7 0480
0x01C7 0484
0x01C7 0488
0x01C7 048C
0x01C7 0490
0x01C7 0494
REGISTER ACRONYM
DESCRIPTION
PID
Peripheral Revision and Class Information
Peripheral Control Register
PCR
SYN_MODE
HD_VD_WID
PIX_LINES
HORZ_INFO
VERT_START
VERT_LINES
CULLING
HSIZE_OFF
SDOFST
SYNC and Mode Set Register
HD and VD Signal Width
Number of Pixels in a Horizontal Line and Number of Lines in a Frame
Horizontal Pixel Information
Vertical Line - Settings for the Starting Pixel
Number of Vertical Lines
Culling Information in Horizontal and Vertical Directions
Horizontal Size
SDRAM/DDRAM Line Offset
SDRAM Address
SDR_ADDR
CLAMP
Optical Black Clamping Settings
DC Clamp
DCSUB
COLPTN
CCD Color Pattern
BLKCMP
Black Compensation
-
Reserved
-
Reserved
VDINT
VD Interrupt Timing
ALAW
A-Law Setting
REC656IF
CCDCFG
REC656 Interface
CCD Configuration
FMTCFG
Data Reformatter/Video Port Configuration
Data Reformatter/Video Input Interface Horizontal Information
Data Reformatter/Video Input Interface Vertical Information
Address Pointer 0 Setup
FMT_HORZ
FMT_VERT
FMT_ADDR0
FMT_ADDR1
FMT_ADDR2
FMT_ADDR3
FMT_ADDR4
FMT_ADDR5
FMT_ADDR6
FMT_ADDR7
PRGEVEN_0
RRGEVEN_1
PRGGODD_0
PRGGODD_1
VP_OUT
Address Pointer 1 Setup
Address Pointer 2 Setup
Address Pointer 3 Setup
Address Pointer 4 Setup
Address Pointer 5 Setup
Address Pointer 6 Setup
Address Pointer 7 Setup
Program Entries 0-7 for Even Line
Program Entries 8-15 for Even Line
Program Entries 0-7 for Odd Line
Program Entries 8-15 for Odd Line
Video Port Output Settings
6.13.1.2 Preview Engine
The preview engine transforms raw unprocessed image/video data from a sensor (CMOS or CCD) into
YCbCr 4:2:2 data. The output of the preview engine is used for both video compression and external
display devices such as a NTSC/PAL analog encoder or a digital LCD. The following features are
supported by the preview engine.
•
•
•
Accepts conventional Bayer pattern formats.
Input image/video data from either the CCD/CMOS controller or the DDR2 memory.
Output width up to 1280 pixels wide.
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•
Automatic/mandatory cropping of pixels/lines when edge processing is performed. If all the
corresponding modules are enabled, a total of 14 pixels per line (7 left most and 7 right most) and 8
lines (4 top most and 4 bottom most) will not be output.
•
Simple horizontal averaging (by factors of 2, 4, or 8) to handle input widths that are greater than 1280
(plus the cropped number) pixels wide.
•
•
Dark frame capture to DDR2.
Dark frame subtraction for every input raw data frame, fetched from DDR2, pixel-by-pixel to improve
video quality.
•
•
Lens shading compensation. Each input pixel is multiplied with a corresponding 8-bit gain value and
the result is right shifted by a programmable parameter (0-7 bits).
A-law decompression to transform non-linear 8-bit data to 10-bit linear data. This feature allows data in
DDR2 to be 8-bits, which saves 50% of the area if the input to the preview engine is from the DDR2.
•
•
Horizontal median filter for reducing temperature induced noise in pixels.
Programmable noise filter that operates on a 3x3 grid of the same color (effectively, this is a five line
storage requirement).
•
•
•
•
Digital gain and white balance (color separate gain for white balance).
Programmable CFA interpolation that operates on a 5x5 grid.
Conventional Bayer pattern RGB and complementary color sensors.
Support for an image that is downsampled by 2x in the horizontal direction (with and without phase
correction). In this case, the image is 2/3 populated instead of the conventional 1/3 colors.
•
Support for an image that is downsampled by 2x in both the horizontal and vertical direction. In this
case, the image is fully populated instead of the conventional 1/3 colors.
•
•
•
•
Programmable RGB-to-RGB blending matrix (9 coefficients for the 3x3 matrix).
Fully programmable gamma correction (1024 entries for each color held in an on-chip RAM).
Programmable color conversion (RGB to YUV) coefficients (9 coefficients for the 3x3 matrix).
Luminance enhancement (non-linear) and chrominance suppression & offset.
The Preview Engine register memory mapping is shown in Table 6-49.
Table 6-49. Preview Engine Register Descriptions
HEX ADDRESS RANGE
REGISTER ACRONYM
DESCRIPTION
0x01C7 0800
0x01C7 0804
0x01C7 0808
0x01C7 080C
0x01C7 0810
0x01C7 0814
0x01C7 0818
0x01C7 081C
0x01C7 0820
0x01C7 0824
0x01C7 0828
0x01C7 082C
0x01C7 0830
0x01C7 0834
0x01C7 0838
0x01C7 083C
0x01C7 0840
0x01C7 0844
PID
Peripheral Revision and Class Information
Peripheral Control Register
Horizontal Information/Setup
Vertical Information/Setup
Read Address From SDRAM
Line Offset for the Read Data
Dark Frame Address From SDRAM
Line Offset for the Dark Frame Data
Write Address to the SDRAM
Line Offset for the Write Data
Input Formatter/Averager
PCR
HORZ_INFO
VERT_INFO
RSDR_ADDR
RADR_OFFSET
DSDR_ADDR
DRKF_OFFSET
WSDR_ADDR
WADD_OFFSET
AVE
HMED
Horizontal Median Filter
NF
Noise Filter
WB_DGAIN
WBGAIN
White Balance Digital Gain
White Balance Coefficients
White Balance Coefficients Selection
CFA Register
WBSEL
CFA
BLKADJOFF
Black Adjustment Offset
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Table 6-49. Preview Engine Register Descriptions (continued)
HEX ADDRESS RANGE
0x01C7 0848
0x01C7 084C
0x01C7 0850
0x01C7 0854
0x01C7 0858
0x01C7 085C
0x01C7 0860
0x01C7 0864
0x01C7 0868
0x01C7 086C
0x01C7 0870
0x01C7 0874
0x01C7 0878
0x01C7 087C
0x01C7 0880
0x01C7 0884
REGISTER ACRONYM
RGB_MAT1
DESCRIPTION
RGB2RGB Blending Matrix Coefficients
RGB_MAT2
RGB_MAT3
RGB_MAT4
RGB_MAT5
RGB_OFF1
RGB_OFF2
CSC0
RGB2RGB Blending Matrix Coefficients
RGB2RGB Blending Matrix Coefficients
RGB2RGB Blending Matrix Coefficients
RGB2RGB Blending Matrix Coefficients
RGB2RGB Blending Matrix Offsets
RGB2RGB Blending Matrix Offsets
Color Space Conversion Coefficients
Color Space Conversion Coefficients
Color Space Conversion Coefficients
Color Space Conversion Offsets
Contrast and Brightness Settings
Chrominance Suppression Settings
Maximum/Minimum Y and C Settings
Setup Table Addresses
CSC1
CSC2
CSC_OFFSET
CNT_BRT
CSUP
SETUP_YC
SET_TBL_ADDRESS
SET_TBL_DATA
Setup Table Data
6.13.1.3 Resizer
The resizer module can accept input image/video data from either the preview engine or DDR2. The
output of the resizer module is sent to DDR2. The following features are supported by the resizer module.
•
•
•
•
An output width up to 1280 horizontal pixels.
Input from external DDR2.
Up to 4x upsampling (digital zoom).
Bi-cubic interpolation (4-tap horizontal, 4-tap vertical) can be implemented with the programmable filter
coefficients.
•
•
•
•
•
•
8 phases of filter coefficients.
Optional bi-linear interpolation for the chrominance components.
Up to 1/4x downsampling
4-tap horizontal and 4-tap vertical filter coefficients (with 8-phases) for 1x to 1/2x downsampling
1/2x to 1/4x downsampling, for 7-tap mode with 4-phases.
Resizing either YUV 4:2:2 packed data (16-bits) or color separate data (8-bit data within DDR) that is
contiguous.
•
•
•
Separate/independent resizing factor for the horizontal and vertical directions.
Upsampling and downsampling ratios that are available are: 256/N, with N ranging from 64 to 1024.
Programmable luminance sharpening after the horizontal resizing and before the vertical resizing step.
The Resizer register memory mapping is shown in Table 6-50.
Table 6-50. Resizer Register Descriptions
HEX ADDRESS RANGE
REGISTER ACRONYM
DESCRIPTION
0x01C7 0C00
0x01C7 0C04
0x01C7 0C08
0x01C7 0C0C
0x01C7 0C10
0x01C7 0C14
0x01C7 0C18
PID
Peripheral Revision and Class Information
Peripheral Control Register
PCR
RSZ_CNT
OUT_SIZE
IN_START
IN_SIZE
Resizer Control Bits
Output Width and Height After Resizing
Input Starting Information
Input Width and Height Before Resizing
Input SDRAM Address
SDR_INADD
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Table 6-50. Resizer Register Descriptions (continued)
HEX ADDRESS RANGE
0x01C7 0C1C
0x01C7 0C20
0x01C7 0C24
0x01C7 0C28
0x01C7 0C2C
0x01C7 0C30
0x01C7 0C34
0x01C7 0C38
0x01C7 0C3C
0x01C7 0C40
0x01C7 0C44
0x01C7 0C48
0x01C7 0C4C
0x01C7 0C50
0x01C7 0C54
0x01C7 0C58
0x01C7 0C5C
0x01C7 0C60
0x01C7 0C64
0x01C7 0C68
0x01C7 0C6C
0x01C7 0C70
0x01C7 0C74
0x01C7 0C78
0x01C7 0C7C
0x01C7 0C80
0x01C7 0C84
0x01C7 0C88
0x01C7 0C8C
0x01C7 0C90
0x01C7 0C94
0x01C7 0C98
0x01C7 0C9C
0x01C7 0CA0
0x01C7 0CA4
0x01C7 0CA8
REGISTER ACRONYM
SDR_INOFF
DESCRIPTION
SDRAM Offset for the Input Line
SDR_OUTADD
SDR_OUTOFF
HFILT10
Output SDRAM Address
SDRAM Offset for the Output Line
Horizontal Filter Coefficients 1 and 0
Horizontal Filter Coefficients 3 and 2
Horizontal Filter Coefficients 5 and 4
Horizontal Filter Coefficients 7 and 6
Horizontal Filter Coefficients 9 and 8
Horizontal Filter Coefficients 11 and 10
Horizontal Filter Coefficients 13 and 12
Horizontal Filter Coefficients 15 and 14
Horizontal Filter Coefficients 17 and 16
Horizontal Filter Coefficients 19 and 18
Horizontal Filter Coefficients 21 and 20
Horizontal Filter Coefficients 23 and 22
Horizontal Filter Coefficients 25 and 24
Horizontal Filter Coefficients 27 and 26
Horizontal Filter Coefficients 29 and 28
Horizontal Filter Coefficients 31 and 30
Vertical Filter Coefficients 1 and 0
Vertical Filter Coefficients 3 and 2
Vertical Filter Coefficients 5 and 4
Vertical Filter Coefficients 7 and 6
Vertical Filter Coefficients 9 and 8
Vertical Filter Coefficients 11 and 10
Vertical Filter Coefficients 13 and 12
Vertical Filter Coefficients 15 and 14
Vertical Filter Coefficients 17 and 16
Vertical Filter Coefficients 19 and 18
Vertical Filter Coefficients 21 and 20
Vertical Filter Coefficients 23 and 22
Vertical Filter Coefficients 25 and 24
Vertical Filter Coefficients 27 and 26
Vertical Filter Coefficients 29 and 28
Vertical Filter Coefficients 31 and 30
Luminance Enhancer
HFILT32
HFILT54
HFILT76
HFILT98
HFILT1110
HFILT1312
HFILT1514
HFILT1716
HFILT1918
HFILT2120
HFILT2322
HFILT2524
HFILT2726
HFILT2928
HFILT3130
VFILT10
VFILT32
VFILT54
VFILT76
VFILT98
VFILT1110
VFILT1312
VFILT1514
VFILT1716
VFILT1918
VFILT2120
VFILT2322
VFILT2524
VFILT2726
VFILT2928
VFILT3130
YENH
6.13.1.4 Hardware 3A (H3A)
The Hardware 3A (H3A) module provides control loops for Auto Focus, Auto White Balance and Auto
Exposure. There are 2 main components of the H3A module:
•
•
Auto Focus (AF) Engine
Auto Exposure (AE) & Auto White Balance (AWB) Engine
The AF engine extracts and filters the red, green, and blue data from the input image/video data and
provides either the accumulation or peaks of the data in a specified region. The specified region is a two
dimensional block of data and is referred to as a “paxel” for the case of AF.
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The AE/AWB Engine accumulates the values and checks for saturated values in a sub sampling of the
video data. In the case of the AE/AWB, the two-dimensional block of data is referred to as a “window”.
The number, dimensions, and starting position of the AF paxels and the AE/AWB windows are separately
programmable.
The H3A register memory mapping is shown in Table 6-51.
Table 6-51. H3A Register Descriptions
HEX ADDRESS RANGE
0x01C7 1400
0x01C7 1404
0x01C7 1408
0x01C7 140C
0x01C7 1410
0x01C7 1414
0x01C7 1418
0x01C7 141C
0x01C7 1420
0x01C7 1424
0x01C7 1428
0x01C7 142C
0x01C7 1430
0x01C7 1434
0x01C7 1438
0x01C7 143C
0x01C7 1440
0x01C7 1444
0x01C7 1448
0x01C7 144C
0x01C7 1450
0x01C7 1454
0x01C7 1458
0x01C7 145C
REGISTER ACRONYM
DESCRIPTION
Peripheral Revision and Class Information
Peripheral Control Register
PID
PCR
AFPAX1
Setup for the AF Engine Paxel Configuration
Setup for the AF Engine Paxel Configuration
Start Position for AF Engine Paxels
AFPAX2
AFPAXSTART
AFIIRSH
Start Position for IIRSH
AFBUFST
SDRAM/DDRAM Start Address for AF Engine
IIR Filter Coefficient Data for SET 0
IIR Filter Coefficient Data for SET 0
IIR Filter Coefficient Data for SET 0
IIR Filter Coefficient Data for SET 0
IIR Filter Coefficient Data for SET 0
IIR Filter Coefficient Data for SET 0
IIR Filter Coefficient Data for SET 1
IIR Filter Coefficient Data for SET 1
IIR Filter Coefficient Data for SET 1
IIR Filter Coefficient Data for SET 1
IIR Filter Coefficient Data for SET 1
IIR Filter Coefficient Data for SET 1
Configuration for AE/AWB Windows
Start Position for AE/AWB Windows
Start Position and Height for Black Line of AE/AWB Windows
Configuration for Subsample Data in AE/AWB Window
SDRAM/DDRAM Start Address for AE/AWB Engine
AFCOEF010
AFCOEF032
AFCOEFF054
AFCOEFF076
AFCOEFF098
AFCOEFF0010
AFCOEF110
AFCOEF132
AFCOEFF154
AFCOEFF176
AFCOEFF198
AFCOEFF1010
AEWWIN1
AEWINSTART
AEWINBLK
AEWSUBWIN
AEWBUFST
6.13.1.4.1 Auto Focus (AF) Engine
The following features are supported by the Auto Focus (AF) Engine.
•
•
•
•
•
•
•
•
•
•
Peak Mode in a Paxel (a Paxel is defined as a two dimensional block of pixels).
Accumulate the maximum Focus Value of each line in a Paxel
Accumulation/Sum Mode (instead of Peak mode).
Accumulate Focus Value in a Paxel.
Up to 36 Paxels in the horizontal direction and up to 128 Paxels in the vertical direction.
Programmable width and height for the Paxel. All paxels in the frame will be of same size.
Programmable red, green, and blue position within a 2x2 matrix.
Separate horizontal start for paxel and filtering.
Programmable vertical line increments within a paxel.
Parallel IIR filters configured in a dual-biquad configuration with individual coefficients (2 filters with 11
coefficients each). The filters are intended to compute the sharpness/peaks in the frame to focus on.
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6.13.1.4.2 Auto Exposure (AE) and Auto White Balance (AWB) Engine
The following features are supported by the Auto Exposure (AE) and Auto White Balance (AWB) Engine.
•
•
•
•
•
Accumulate clipped pixels along with all non-saturated pixels.
Up to 36 horizontal windows.
Up to 128 vertical windows.
Programmable width and height for the windows. All windows in the frame will be of same size.
Separate vertical start coordinate and height for a black row of paxels that is different than the
remaining color paxels.
•
•
Programmable Horizontal Sampling Points in a window.
Programmable Vertical Sampling Points in a window.
6.13.1.5 Histogram
The histogram module accepts raw image/video data and bins the pixels on a value (and color separate)
basis. The value of the pixel itself is not stored, but each bin contains the number of pixels that are within
the appropriate set range. The source of the raw data for the histogram is typically a CCD/CMOS sensor
(via the CCDC module) or optionally from DDR2. The following features are supported by the histogram
module.
•
•
•
Up to four regions/areas.
Separate horizontal/vertical start and end position for each region.
Pixels from overlapping regions are accumulated into the highest priority region. The priority is: region0
> region1 > region2 > region3.
•
•
•
•
•
•
Interface to conventional Bayer pattern. Each region can accumulate either 3 or 4 colors.
32, 64, 128, or 256 bins per color per region.
32, 64, or 128 bins per color for 2 regions.
32 or 64 bins per color for 3 or 4 regions.
Automatic clear of histogram RAM after an ARM read.
Saturation of the pixel count if the count exceeds the maximum value (each memory location is 20-bit
wide).
•
•
Downshift ranging from 0 to 7 bits (maximum bin range 128).
The last bin (highest range of values) will accumulate any value that is higher than the lower bound.
The Histogram register memory mapping is shown in Table 6-52.
Table 6-52. Histogram Register Descriptions
HEX ADDRESS RANGE
REGISTER ACRONYM
DESCRIPTION
0x01C7 1000
0x01C7 1004
0x01C7 1008
0x01C7 100C
0x01C7 1010
0x01C7 1014
0x01C7 1018
0x01C7 101C
0x01C7 1020
0x01C7 1024
0x01C7 1028
0x01C7 102C
0x01C7 1030
0x01C7 1034
PID
Peripheral Revision and Class Information Register
Peripheral Control Register
PCR
HIST_CNT
WB_GAIN
R0_HORZ
R0_VERT
R1_HORZ
R1_VERT
R2_HORZ
R2_VERT
R3_HORZ
R3_VERT
HIST_ADDR
HIST_DATA
Histogram Control Bits Register
White/Channel Balance Settings Register
Region 0 Horizontal Information Register
Region 0 Vertical Information Register
Region 1 Horizontal Information Register
Region 1 Vertical Information Register
Region 2 Horizontal Information Register
Region 2 Vertical Information Register
Region 3 Horizontal Information Register
Region 3 Vertical Information Register
Histogram Address for Data to be Read Register
Histogram Data That is Read From the Memory Register
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Table 6-52. Histogram Register Descriptions (continued)
HEX ADDRESS RANGE
0x01C7 1038
REGISTER ACRONYM
DESCRIPTION
RADD
Read Address From DDR2 Memory Register
0x01C7 103C
RADD_OFF
H_V_INFO
Read Address Offset for Each Line in the DDR2 Memory Register
0x01C7 1040
Horizontal/Vertical Information Register (Horizontal/Vertical Number of
Pixels When Data is Read From DDR2 Memory Information Register)
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6.13.1.6 VPFE Electrical Data/Timing
Table 6-53. Timing Requirements for VPFE PCLK Master/Slave Mode (see Figure 6-46)
NO.
1
MIN
MAX
UNIT
ns
tc(PCLK)
tw(PCLKH)
tw(PCLKL)
tt(PCLK)
Cycle time, PCLK
10.204 or 13.33(1)
160
2
Pulse duration, PCLK high
Pulse duration, PCLK low
Transition time, PCLK
4.4
4.4
ns
3
ns
4
3
ns
(1) When PCLK sources the clock for both the VPFE and VPBE, the minimum cycle time of 13.33 ns (specified in Table 6-60, Timing
Requirements for VPBE CLK Inputs for VPBE) must be met. When PCLK sources the clock for only the VPFE, a minimum cycle time of
10.2 ns may be used.
2
3
1
PCLK
4
4
Figure 6-46. VPFE PCLK Timing
Table 6-54. Timing Requirements for VPFE (CCD) Slave Mode(1) (see Figure 6-47)
NO.
5
MIN
MAX
UNIT
ns
tsu(CCDV-PCLK)
th(PCLK-CCDV)
tsu(HDV-PCLK)
th(PCLK-HDV)
Setup time, CCD valid before PCLK edge
Hold time, CCD valid after PCLK edge
Setup time, HD valid before PCLK edge
Hold time, HD valid after PCLK edge
Setup time, VD valid before PCLK edge
Hold time, VD valid after PCLK edge
Setup time, C_WE valid before PCLK edge
Hold time, C_WE valid after PCLK edge
3
2
3
2
3
2
3
2
3
2
6
ns
7
ns
8
ns
9
tsu(VDV-PCLK)
th(PCLK-VDV)
tsu(C_WEV-PCLK)
th(PCLK-C_WEV)
ns
10
11
12
13
14
ns
ns
ns
tsu(C_FIELDV-PCLK) Setup time, C_FIELD valid before PCLK edge
th(PCLK-C_FIELDV) Hold time, C_FIELD valid after PCLK edge
ns
ns
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
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PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
8, 10
7, 9
HD/VD
11, 13
12, 14
C_WE/C_FIELD
CCD[15:0]
5
6
Figure 6-47. VPFE (CCD) Slave Mode Input Data Timing
Table 6-55. Timing Requirements for VPFE (CCD) Master Mode(1) (see Figure 6-48)
NO.
15
MIN
MAX
UNIT
ns
tsu(CCDV-PCLK)
th(PCLK-CCDV)
tsu(CWEV-PCLK)
th(PCLK-CWEV)
Setup time, CCD valid before PCLK edge
Hold time, CCD valid after PCLK edge
Setup time, C_WE valid before PCLK edge
Hold time, C_WE valid after PCLK edge
3
2
3
2
16
ns
23
ns
24
ns
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
15
16
CCD[15:0]
23
24
C_WE
Figure 6-48. VPFE (CCD) Master Mode Input Data Timing
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Table 6-56. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master
Mode(1) (see Figure 6-49)
NO.
18
PARAMETER
Delay time, PCLK edge to HD valid
Delay time, PCLK edge to VD valid
Delay time, PCLK edge to C_FIELD valid
MIN
MAX
UNIT
ns
td(PCLK-HDV)
0.5
0.5
0.5
8
8
20
td(PCLK-VDV)
ns
22
td(PCLK-C_FIELDV)
8.3
ns
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
18
HD
20
VD
22
C_FIELD
Figure 6-49. VPFE (CCD) Master Mode Control Output Data Timing
6.13.2 Video Processing Back-End (VPBE)
The Video Processing Back-End (VPBE) consists of the On-Screen Display (OSD) module, the Video
Encoder (VENC) including the Digital LCD (DLCD) and Analog (i.e., DAC) interfaces. The video encoder
generates analog video output. The DLCD controller generates digital RGB/YCbCr data output and timing
signals.
The VPBE register memory mapping is shown in Table 6-57.
Table 6-57. VPBE Register Descriptions
Address
Register
PID
Description
Peripheral Revision and Class Information Register
Peripheral Control Register
0x01C7 2780
0x01C7 2784
PCR
6.13.2.1 On-Screen Display (OSD)
The major function of the OSD module is to gather and blend video data and display/bitmap data before
feeding it to the Video Encoder (VENC) in YCbCr format. The video and display data is read from an
external memory, typically DDR2. The OSD is programmed via control and parameter registers. The
following are the primary features that are supported by the OSD.
•
Simultaneous display of two video windows and two OSD windows (VIDWIN0/VIDWIN1 and
OSDWIN0/OSDWIN1).
–
–
–
–
–
–
–
Separate enable for each window
Programmable width, height, and base starting coordinates for each window
External memory address and offset registers for each window
Support for x2 and x4 zoom in both the horizontal and vertical direction
OSDWIN1 can be used as an attribute window for OSDWIN0
Attribute window blinking intervals
Field/frame mode for the windows (interlaced/progressive)
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–
–
Eight step blending process between the OSD and video windows
Transparency support for the OSD and video data (when a bitmap pixel is zero, there will be no
blending for that corresponding video pixel)
–
–
Resize from VGA to NTSC/PAL (640x480 to 720x576) for both the OSD and video windows
Reads in YCbCr data in 4:2:2 format from external memory, with the capability for swapping the
order of the CbCr component in the 32-bit word (this is relevant to the two video windows)
–
–
Support for a ping-pong buffer scheme that can be used for VIDWIN0 (allows for video data to be
accessed from two different locations in DDR2)
Each OSD window (either one, but not both at the same time) is capable of reading in RGB data
(16-bit data with six bits for the green and five bits each for the red and blue colors) instead of
bitmap data in YCbCr format restricted to a maximum of 8-bits
–
–
The OSD bitmap data width is selectable between 1, 2, 4, or 8-bits.
Each OSD window supports 16 entries for the bitmap (to index into a 256 entry RAM/ROM CLUT
table).
–
Indirect support for 24-bit RGB input data (which will be transformed into 16-bit YCbCr video
window data) via the wrapper interface in the VPBE.
•
•
Support for a rectangular cursor window and a programmable background color selection.
–
Programmable color palette with the ability to select between a RAM/ROM table with support for
256 colors.
–
–
The width, height, and color of the cursor is programmable.
The display priority is: Rectangular-Cursor > OSDWIN1 > OSDWIN0 > VIDWIN1 > VIDWIN0 >
background color
Support for attenuation of the YCbCr values for the REC601 standard.
The following restrictions exist in the OSD module.
•
•
•
Both the OSD windows and VIDWIN1 should be fully contained inside VIDWIN0.
When one of the OSD windows is set in RGB mode, it cannot overlap with VIDWIN1.
The OSD cannot support more than 256 color entries in the CLUT RAM/ROM. Some applications
require higher number of entries, and one workaround is to use VIDWIN1 as an overlay mimicking the
OSD window. Another option is to use the RGB mode for one of the OSD windows which allows for a
total of 16-bits for the R, G, and B colors (64K colors).
•
•
•
•
The OSD can only read YCbCr in 4:2:2 interleaved format for the video windows. Other formats, either
color separate storage or 4:4:4/4:2:0 interleaved data is not supported.
If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window
dimension cannot be greater than 720 currently.
It is not possible to use both of the CLUT ROMs at the same time. However, one window can use
RAM while another uses ROM.
The 24-bit RGB input mode is only valid for one of the two video windows (programmable) and does
not apply to the OSD windows.
The OSD register memory mapping is shown in Table 6-58.
Table 6-58. OSD Register Descriptions
Address
Register
Description
0x01C7 2600
0x01C7 2604
0x01C7 2608
0x01C7 260C
0x01C7 260C
0x01C7 2610
MODE
OSD Mode Register
VIDWINMD
OSDWIN0MD
OSDWIN1MD
OSDATRMD
RECTCUR
Video Window Mode Setup
OSD Window Mode Setup
OSD Window 1 Mode Setup (when used as a second OSD window)
OSD Attribute Window Mode Setup (when used as an attribute window)
Rectangular Cursor Setup
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Table 6-58. OSD Register Descriptions (continued)
0x01C7 2614
RSV0
Reserved
0x01C7 2618
0x01C7 261C
0x01C7 2620
0x01C7 2624
0x01C7 2628
0x01C7 262C
0x01C7 2630
0x01C7 2634
0x01C7 2638
0x01C7 263C
0x01C7 2640
0x01C7 2644
0x01C7 2648
0x01C7 264C
0x01C7 2650
0x01C7 2654
0x01C7 2658
0x01C7 265C
0x01C7 2660
0x01C7 2664
0x01C7 2668
0x01C7 266C
0x01C7 2670
0x01C7 2674
0x01C7 2678
0x01C7 267C
0x01C7 2680
0x01C7 2684
0x01C7 2688
0x01C7 268C
0x01C7 2690
0x01C7 2694
0x01C7 2698
0x01C7 269C
0x01C7 26A0
0x01C7 26A4
0x01C7 26A8
0x01C7 26AC
0x01C7 26B0
0x01C7 26B4
0x01C7 26B8
0x01C7 26BC
0x01C7 26C0
0x01C7 26C4
0x01C7 26C8
0x01C7 26CC
0x01C7 26D0
VIDWIN0OFST
VIDWIN1OFST
OSDWIN0OFST
OSDWIN1OFST
RSV1
Video Window 0 Offset
Video Window 1 Offset
OSD Window 0 Offset
OSD Window 1 Offset
Reserved
VIDWIN0ADR
VIDWIN1ADR
RSV2
Video Window 0 Address
Video Window 1 Address
Reserved
OSDWIN0ADR
OSDWIN1ADR
BASEPX
OSD Window 0 Address
OSD Window 1 Address
Base Pixel X
BASEPY
Base Pixel Y
VIDWIN0XP
VIDWIN0YP
VIDWIN0XL
VIDWIN0YL
VIDWIN1XP
VIDWIN1YP
VIDWIN1XL
VIDWIN1YL
OSDWIN0XP
OSDWIN0YP
OSDWIN0XL
OSDWIN0YL
OSDWIN1XP
OSDWIN1YP
OSDWIN1XL
OSDWIN1YL
CURXP
Video Window 0 X-Position
Video Window 0 Y-Position
Video Window 0 X-Size
Video Window 0 Y-Size
Video Window 1 X-Position
Video Window 1 Y-Position
Video Window 1 X-Size
Video Window 1 Y-Size
OSD Bitmap Window 0 X-Position
OSD Bitmap Window 0 Y-Position
OSD Bitmap Window 0 X-Size
OSD Bitmap Window 0 Y-Size
OSD Bitmap Window 1 X-Position
OSD Bitmap Window 1 Y-Position
OSD Bitmap Window 1 X-Size
OSD Bitmap Window 1 Y-Size
Rectangular Cursor Window X-Position
Rectangular Cursor Window Y-Position
Rectangular Cursor Window X-Size
Rectangular Cursor Window Y-Size
Reserved
CURYP
CURXL
CURYL
RSV3
RSV4
Reserved
W0BMP01
W0BMP23
W0BMP45
W0BMP67
W0BMP89
W0BMPAB
W0BMPCD
W0BMPEF
W1BMP01
W1BMP23
W1BMP45
W1BMP67
W1BMP89
Window 0 Bitmap Value to Palette Map 0/1
Window 0 Bitmap Value to Palette Map 2/3
Window 0 Bitmap Value to Palette Map 4/5
Window 0 Bitmap Value to Palette Map 6/7
Window 0 Bitmap Value to Palette Map 8/9
Window 0 Bitmap Value to Palette Map A/B
Window 0 Bitmap Value to Palette Map C/D
Window 0 Bitmap Value to Palette Map E/F
Window 1 Bitmap Value to Palette Map 0/1
Window 1 Bitmap Value to Palette Map 2/3
Window 1 Bitmap Value to Palette Map 4/5
Window 1 Bitmap Value to Palette Map 6/7
Window 1 Bitmap Value to Palette Map 8/9
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Table 6-58. OSD Register Descriptions (continued)
0x01C7 26D4
0x01C7 26D8
0x01C7 26DC
0x01C7 26E0
0x01C7 26E4
0x01C7 26E8
0x01C7 26EC
0x01C7 26F0
0x01C7 26F4
0x01C7 26F8
0x01C7 26FC
W1BMPAB
W1BMPCD
W1BMPEF
-
Window 1 Bitmap Value to Palette Map A/B
Window 1 Bitmap Value to Palette Map C/D
Window 1 Bitmap Value to Palette Map E/F
Reserved
RSV5
Reserved
MISCCTL
CLUTRAMYCB
CLUTRAMCR
TRANSPVAL
RSV6
Miscellaneous Control
CLUT RAMYCB Setup
CLUT RAM Setup
CLUT RAM Setup
Reserved
PPVWIN0ADR
Ping-Pong Video Window 0 Address
6.13.2.2 Video Encoder (VENC)
Analog/DACs interface of the Video Encoder (VENC) supports the following features.
•
•
Master Clock Input - 27MHz (x2 Upsampling)
SDTV Support
–
–
–
–
–
–
–
–
–
Composite NTSC-M, PAL-B/D/G/H/I
S-Video (Y/C)
Component YPbPr (SMPTE/EBU N10, Betacam, MII)
RGB
Non-Interlace
CGMS/WSS
Line 21 Closed Caption Data Encoding
Chroma Low Pass Filter 1.5MHz/3MHz
Programmable SC-H phase
•
HDTV Support
–
–
–
–
Progressive Output (525p/625p)
Component YPbPr
RGB
CGMS/WSS
•
•
•
•
•
•
4 10-bit Over-Sampling D/A Converters
Optional 7.5% Pedestal
16-235/0-255 Input Amplitude Selectable
Programmable Luma Delay
Master/Slave Operation
Internal Color Bar Generation (100%/75%)
The Digital LCD Controller (DLCD) of the VENC supports the following features.
•
•
Programmable DCLK
Various Output Formats
–
–
–
–
YCbCr 16bit
YCbCr 8bit
ITU-R BT. 656
Parallel RGB 24bit
•
•
•
Low Pass Filter for Digital RGB Output
Programmable Timing Generator
Master/Slave Operation
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•
Internal Color Bar Generation (100%/75%)
The VENC register memory mapping including the Digital LCD and DACs is shown in Table 6-59.
Table 6-59. VENC (Including Digital LCD and DACs) Register Descriptions
Address
Register
Description
0x01C7 2400
0x01C7 2404
0x01C7 2408
0x01C7 240C
0x01C7 2410
0x01C7 2414
0x01C7 2418
0x01C7 241C
0x01C7 2420
0x01C7 2424
0x01C7 2428
0x01C7 242C
0x01C7 2430
0x01C7 2434
0x01C7 2438
0x01C7 243C
0x01C7 2440
0x01C7 2444
0x01C7 2448
0x01C7 244C
0x01C7 2450
0x01C7 2454
0x01C7 2458
0x01C7 245C
0x01C7 2460
0x01C7 2464
0x01C7 2468
0x01C7 246C
0x01C7 2470
0x01C7 2474
0x01C7 2478
0x01C7 247C
0x01C7 2480
0x01C7 2484
0x01C7 2488
0x01C7 248C
0x01C7 2490
0x01C7 2494
0x01C7 2498
0x01C7 249C
0x01C7 24A0
0x01C7 24A4
0x01C7 24A8
0x01C7 24AC
VMOD
Video Mode
VIDCTL
VDPRO
Video Interface I/O Control
Video Data Processing
Sync Control
SYNCCTL
HSPLS
Horizontal Sync Pulse Width
Vertical Sync Pulse Width
Horizontal Interval
VSPLS
HINT
HSTART
HVALID
Horizontal Valid Data Start Position
Horizontal Data Valid Range
Vertical Interval
VINT
VSTART
VVALID
Vertical Valid Data Start Position
Vertical Data Valid Range
Horizontal Sync Delay
Vertical Sync Delay
HSDLY
VSDLY
YCCTL
YCbCr Control
RGBCTL
RGBCLP
LINECTL
CULLLINE
LCDOUT
BRTS
RGB Control
RGB Level Clipping
Line ID Control
Culling Line Control
LCD Output Signal Control
Brightness Start Position Signal Control
Brightness Width Signal Control
LCD_AC Signal Control
PWM Start Position Signal Control
PWM Width Signal Control
DCLK Control
BRTW
ACCTL
PWMP
PWMW
DCLKCTL
DCLKPTN0
DCLKPTN1
DCLKPTN2
DCLKPTN3
DCLKPTN0A
DCLKPTN1A
DCLKPTN2A
DCLKPTN3A
DCLKHS
DCLKHSA
DCLKHR
DCLKVS
DCLKVR
CAPCTL
CAPDO
DCLK Pattern 0
DCLK Pattern 1
DCLK Pattern 2
DCLK Pattern 3
DCLK Auxiliary Pattern 0
DCLK Auxiliary Pattern 1
DCLK Auxiliary Pattern 2
DCLK Auxiliary Pattern 3
Horizontal DCLK Mask Start
Horizontal Auxiliary DCLK Mask Start
Horizontal DCLK Mask Range
Vertical DCLK Mask Start
Vertical DCLK Mask Range
Caption Control
Caption Data Odd Field
Caption Data Even Field
Video Attribute Data # 0
Video Attribute Data # 1
CAPDE
ATR0
ATR1
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Table 6-59. VENC (Including Digital LCD and DACs) Register Descriptions (continued)
0x01C7 24B0
0x01C7 24B4
0x01C7 24B4
0x01C7 24B4
0x01C7 24B4
0x01C7 24B8
0x01C7 24BC
0x01C7 24C0
0x01C7 24C4
0x01C7 24C8
0x01C7 24CC
0x01C7 24D0
0x01C7 24D4
0x01C7 24D8
0x01C7 24DC
0x01C7 24E0
0x01C7 24E4
0x01C7 24E8
0x01C7 24EC
0x01C7 24F0
0x01C7 24F4
0x01C7 24F8
0x01C7 24FC
0x01C7 2500
0x01C7 2504
0x01C7 2508
0x01C7 250C
0x01C7 2510
0x01C7 2514
0x01C7 2518
0x01C7 251C
0x01C7 2520
0x01C7 2524
0x01C7 2528
0x01C7 252C
0x01C7 2530
0x01C7 2534
0x01C7 2538
0x01C7 253C
ATR2
Video Attribute Data # 2
Reserved
VSTAT
Video Status
Reserved
DACTST
YCOLVL
SCPROG
DAC Test
YOUT and COUT Levels
Sub-Carrier Programming
Reserved
CVBS
Composite Mode
CMPNT
ETMG0
ETMG1
ETMG2
ETMG3
DACSEL
Component Mode
CVBS Timing Control 0
CVBS Timing Control 1
Component Timing Control 0
Component Timing Control 1
DAC Output Select
Reserved
ARGBX0
ARGBX1
ARGBX2
ARGBX3
ARGBX4
DRGBX0
DRGBX1
DRGBX2
DRGBX3
DRGBX4
VSTARTA
OSDCLK0
OSDCLK1
HVLDCL0
HVLDCL1
OSDHADV
Analog RGB Matrix 0
Analog RGB Matrix 1
Analog RGB Matrix 2
Analog RGB Matrix 3
Analog RGB Matrix 4
Digital RGB Matrix 0
Digital RGB Matrix 1
Digital RGB Matrix 2
Digital RGB Matrix 3
Digital RGB Matrix 4
Vertical Data Valid Start Position for Even Field
OSD Clock Control 0
OSD Clock Control 1
Horizontal Valid Culling Control 0
Horizontal Valid Culling Control 1
OSD Horizontal Sync Advance
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6.13.2.3 VPBE Electrical Data/Timing
Table 6-60. Timing Requirements for VPBE CLK Inputs (see Figure 6-50)
NO.
1
MIN
13.33
MAX
UNIT
ns
tc(PCLK)
Cycle time, PCLK
160
2
tw(PCLKH)
tw(PCLKL)
Pulse duration, PCLK high
Pulse duration, PCLK low
Transition time, PCLK
5.7
5.7
ns
3
ns
4
tt(PCLK)
3
ns
5
tc(VPBECLK)
tw(VPBECLKH)
tw(VPBECLKL)
tt(VPBECLK)
Cycle time, VPBECLK
13.33
5.7
160
ns
6
Pulse duration, VPBECLK high
Pulse duration, VPBECLK low
Transition time, VPBECLK
ns
7
5.7
ns
8
3
ns
3
7
1
5
2
6
PCLK
4
4
8
VPBECLK
8
Figure 6-50. VPBE PCLK and VPBECLK Timing
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Table 6-61. Timing Requirements for VPBE Control Input With Respect to PCLK and VPBECLK(1) (see
Figure 6-51)
NO.
9
MIN
MAX
UNIT
ns
tsu(VCTLV-PCLK)
th(PCLK-VCTLV)
Setup time, VCTL valid before PCLK edge
2
0.5
2
10
27
28
33
34
35
36
Hold time, VCTL valid after PCLK edge
ns
tsu(VCTLV-VPBECLK)
th(VPBECLK-VCTLV)
tsu(FIELD-PCLK)
Setup time, VCTL valid before VPBECLK rising edge
Hold time, VCTL valid after VPBECLK rising edge
Setup time, LCD_FIELD valid before PCLK edge
Hold time, LCD_FIELD valid after PCLK edge
Setup time, LCD_FIELD valid before VPBECLK edge
Hold time, LCD_FIELD valid after VPBECLK edge
ns
0.5
ns
5P(2)
5P(2)
5P(2)
5P(2)
ns
th(PCLK-FIELD)
ns
tsu(FIELD-VPBECLK)
th(VPBECLK-FIELD)
ns
ns
(1) PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising
edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.
(2) P = 1/(VCLKIN clock frequency) in ns. VCLKIN is either PCLK or VPBECLK, whichever is used.
VPBECLK
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
10
34
28
36
9
27
35
(A)
VCTL
33
LCD_FIELD
A. VCTL = HSYNC and VSYNC
Figure 6-51. VPBE Input Timing With Respect to PCLK and VPBECLK
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Table 6-62. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to PCLK and VPBECLK(1) (see Figure 6-52)
NO.
11
12
13
14
29
30
31
32
PARAMETER
MIN
MAX
UNIT
ns
td(PCLK-VCTLV)
Delay time, PCLK edge to VCTL valid
13.3
13.6
13.3
13.6
td(PCLK-VCTLIV)
Delay time, PCLK edge to VCTL invalid
Delay time, PCLK edge to VDATA valid
Delay time, PCLK edge to VDATA invalid
Delay time, VPBECLK rising edge to VCTL valid
Delay time, VPBECLK rising edge to VCTL invalid
Delay time, VPBECLK rising edge to VDATA valid
2
2
2
2
ns
td(PCLK-VDATAV)
td(PCLK-VDATAIV)
td(VPBECLK-VCTLV)
td(VPBECLK-VCTLIV)
td(VPBECLK-VDATAV)
ns
ns
ns
ns
ns
td(VPBECLK-VDATAIV) Delay time, VPBECLK rising edge to VDATA invalid
ns
(1) PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising
edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.
VPBECLK
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
11, 29
13, 31
12, 30
14, 32
(A)
VCTL
(B)
VDATA
A. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE
B. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]
Figure 6-52. VPBE Output Timing With Respect to PCLK and VPBECLK
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Table 6-63. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to VCLK(1)(2) (see Figure 6-53)
NO.
PARAMETER
MODE(3)
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
tc(VCLK)
Cycle time, VCLK
13.33
160
Pulse duration, VCLK high (positive-edge clocking)
Pulse duration, VCLK high (negative-edge clocking)
Pulse duration, VCLK low (positive-edge clocking)
Pulse duration, VCLK low (negative-edge clocking)
Transition time, VCLK
H - 1.3(4) H - 0.3(4)
L - 1.3(4) L - 0.3(4)
L + 0.3(4) L + 1.3(4)
H + 0.3(4) H + 1.3(4)
3
18
19
tw(VCLKH)
tw(VCLKL)
tt(VCLK)
20
21
22
td(VCLKINH-VCLKH) Delay time, VCLKIN high to VCLK high
td(VCLKINL-VCLKL) Delay time, VCLKIN low to VCTL low
2
2
12
12
Delay time, VCLK negative edge to VCTL valid
td(VCLK-VCTLV)
7.5
6.9
23
24
25
Delay time, VCLK positive edge to VCTL valid
Delay time, VCLK negative edge to VCTL invalid
td(VCLKL-VCTLIV)
2
Delay time, VCLK positive edge to VCTL invalid
1.5
Delay time, VCLK negative edge to VDATA valid
td(VCLK-VDATAV)
6.8
6.3
Delay time, VCLK positive edge to VDATA valid
RGB
YCC
RGB
YCC
2.1
2.5
1.9
2.1
Delay time, VCLK negative edge to VDATA invalid
td(VCLKL-VDATAIV)
26
Delay time, VCLK positive edge to VDATA invalid
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.
(2) VCLKIN = PCLK or VPBECLK
(3) RGB and YCC modes utilize different data pins. RGB mode uses data pins: R[7:0], G[7:0], and B[7:0]. YCC mode uses data pins:
COUT[7:0] and YOUT[7:0].
(4) H and L are the high and low pulse widths of the input clock to the VPBE, respectively. For example, if VPBECLK is used as the input
clock and it has a high pulse duration of 6.67 ns, the resulting high pulse duration of VCLK, if positive-edge clocking is selected, will be a
MAX of 6.37 ns and a MIN of 5.27 ns.
(A)
VCLKIN
18
21
17
22
19
VCLK
(Positive Edge
Clocking)
VCLK
(Negative Edge
Clocking)
20
23
25
20
24
26
(B)
VCTL
(C)
VDATA
A. VCLKIN = PCLK or VPBECLK
B. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE
C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]
Figure 6-53. VPBE Control and Data Output Timing With Respect to VCLK
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6.13.2.4 DAC Electrical Data/Timing
Table 6-64. Switching Characteristics Over Recommended Operating Conditions for DAC Static
Specifications
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Accuracy
Integral Non-Linearity (INL)
Differential Non-Linearity (DNL)
-1.0
-0.5
1.0
0.5
LSB
LSB
Analog Output
Offset Error
Gain Error
0.5
5
500
LSB
%FS
mVPP
Full-Scale Output Voltage
RLOAD = 500 Ω
Output Capacitance
200
pF
Reference
Reference Voltage Range (VREF
Full-Scale Current Adjust Resistor (RBIAS)
0.475
3.8
0.5
4.0
0.525
4.2
V
kΩ
)
Table 6-65. Switching Characteristics Over Recommended Operating Conditions for DAC Dynamic
Specifications
NO.
PARAMETER
Output Update Rate (FCLK
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
MHz
)
27
6
60
Signal Bandwidth
FCLK = 27 MHz
FOUT = 2.0 MHz
FCLK = 60 MHz
FOUT = 2.0 MHz
FCLK = 27 MHz
FOUT = 2.0 MHz
FCLK = 60 MHz
FOUT = 2.0 MHz
60
60
60
60
dB
dB
db
SFDR to Nyquist
SFDR within Bandwidth
dB
dB
PSRR Over Temp vs Power Supply
50
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The DM6446's analog video DAC outputs are designed to drive a 500-Ω load. Figure 6-54 describes a
typical circuit that will permit connecting the analog video output from the DM6446 device to standard
75-Ω impedance video systems. Another solution is to use a Video Amplifier, such as the Texas
Instruments' OPA361, which provides a complete solution to the typical output circuit shown in
Figure 6-54.
Low-Pass Filter
75 Ω
fc = 6.5 MHz
IOUT
Amplifier
Gain = 5.6 V/V
DAC
~RLOAD = 500 Ω
75 Ω
Figure 6-54. Typical Output Circuit for NTSC/PAL Video From DACs
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6.14 Host-Port Interface (HPI)
The Host Port Interface (HPI) provides a parallel port through which an external host processor can
access the DM6446 memory space. The host device is asynchronous to the DM6446 clocks and functions
as a master to the HPI interface. The HPI enables a host device and DM6446 to exchange information via
internal or external memory. Both the host and DM6446 can access the HPI control register (HPIC) and
the HPI address registers (HPIAR, HPIAW). The host can access the HPI data register (HPID) and the
HPIC by using the external data and interface control signals.
The HPI interface shares the DaVinci EMIFA 16-bit data bus pins for multiplexed address/data and
supports the following modes:
•
•
16 Bit Multiplexed mode / dual half-word cycles (16 bit host data bus/32 bit memory width)
ARM ROM supports booting of DM6446 ARM processor from an external processor
The HPI registers are summarized in Table 6-66. For more detailed information on the HPI peripheral, see
the Documentation Support section for the Host Port Interface (HPI) Reference Guide.
Table 6-66. Host-Port Interface (HPI) Register Descriptions
HEX ADDRESS RANGE
0x01C4 0030
ACRONYM
HPI_CTL
HPI_PID
HPIPWREMU
–
REGISTER NAME
Host-Port Interface Configuration Register
0x01C6 7800
0x01C6 7804
HPI Power and Emulation Management Register
Reserved
0x01C6 7808 - 0x01C6 782F
0x01C6 7830
HPIC
Host-Port Interface Control Register
Host-Port Interface Write Address Register
Host-Port Interface Read Address Register
Reserved
0x01C6 7834
HPIAW
HPIAR
–
0x01C6 7838
0x01C6 783C - 0x01C6 7FFF
The HPI_CTL register sets the owner of HPIA(R/W) and HPIC registers for HPI address and control. The
details for HPI_CTL are shown in Figure 6-55 and Table 6-67.
Figure 6-55. HPI_CTL Register
31
15
30
14
29
28
27
11
26
10
25
24
Reserved
R-0000000000000000
23
22
21
20
19
18
2
17
1
16
0
13
12
9
8
7
6
5
4
3
CTL
MODE MODE
ADD
Reserved
TIMOUT
R/W-10000000
R-0
LEGEND: R = Read, W = Write, n = value at reset
R/W-0 R/W-0
Table 6-67. HPI_CTL Register Description
Name
Description
CTLMODE
HPIC register write access
0 = External Host
1 = DM6446 (if ADDMODE = 1)
ADDMODE
TIMOUT
HPIA register write access
0 = External Host
1 = DM6446
Host burst write timeout value
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6.14.1 Host-Port Interface (HPI) Electrical Data/Timing
Table 6-68. Timing Requirements for Host-Port Interface Cycles(1)(2) (see Figure 6-56 through Figure 6-57)
NO.
1
MIN
5
MAX
UNIT
ns
tsu(SELV-HSTBL)
th(HSTBL-SELV)
tw(HSTBL)
Setup time, select signals(3) valid before HSTROBE low
Hold time, select signals(3) valid after HSTROBE low
Pulse duration, HSTROBE low
2
2
ns
3
15
2P
5
ns
4
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
ns
12
13
tsu(HDV-HSTBH)
th(HSTBH-HDV)
ns
0
ns
Hold time, HSTROBE high after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
14
th(HRDYL-HSTBH)
2
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 594 MHz, use P = 1.68 ns.
(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Table 6-69. Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles(1) (see Figure 6-56 through Figure 6-57)
NO.
6
PARAMETER
MIN
MAX
UNIT
ns
td(HSTBL-HRDYH)
td(HSTBL-HDLZ)
td(HDV-HRDYL)
toh(HSTBH-HDV)
td(HSTBH-HDHZ)
Delay time, HSTROBE low to HRDY high(2)
Delay time, HSTROBE low to HD low impedance for an HPI read
Delay time, HD valid to HRDY low
0
0
12
7
ns
8
0
ns
9
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
1.5
ns
15
7
15
12
ns
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word
only)
16
20
td(HSTBL-HDV)
ns
ns
td(HCSL-HRDYH)
Delay time, HCS low to HRDY high
0
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) This parameter is used during HPID reads and writes. For reads, at the beginning of the first half-word transfer (HPI16) on the falling
edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the
EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer
is full.
1
1
1
1
2
2
2
2
2
HCNTL[1:0]
HR/W
1
1
2
HHWIL
4
3
3
(A)
HSTROBE
HCS
15
9
15
9
7
16
HD[15:0] (output)
HRDY
1st half-word
2nd half-word
6
8
20
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 6-56. HPI16 Read Timing
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1
1
2
2
2
2
2
2
3
HCNTL[1:0]
HR/W
1
1
1
1
HHWIL
3
4
(A)
HSTROBE
HCS
12
12
13
2nd half-word
13
HD[15:0] (input)
1st half-word
6
14
20
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 6-57. HPI16 Write Timing
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6.15 USB 2.0
The DM6446 USB2.0 peripheral supports the following features:
•
•
•
•
•
USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous)
4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
FIFO RAM
–
–
4K endpoint
Programmable size
•
•
•
Connects to a standard UTMI+ PHY with a 60 MHz, 8-bit interface
Connects to a standard Charge Pump for VBUS 5 V generation
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
6.15.1 USBPHY_CTL Register Description
The USB physical interface control register USBPHY_CTL is described in Figure 6-58 and Table 6-70.
Figure 6-58. USBPHY_CTL Register
31
9
8
7
6
5
4
3
2
1
0
Reserved
R-0000 0000 0000 0000 0000 000
PHYCLKGD SESNDEN VBDTCTEN RSV PHYPLLON CLKO1SEL OSCPDWN
R-0 R/W-1 R/W-1 R-0 R/W-0 R/W-0 R/W-1
RSV
PHYPDWN
R/W-1
R/W-1
LEGEND: R = Read, W = Write, n = value at reset
Table 6-70. USBPHY_CTL Register Descriptions
Name
Description
PHYCLKGD
USB PHY Power and Clock Good
0 = Phy power not ramped or PLL not locked
1 = Phy power is good and PLL is locked
SESNDEN
VBDTCTEN
PHYPLLON
CLKO1SEL
OSCPDWN
PHYPDWN
Session End Comparator enable
0 = comparator disabled
1 = comparator enabled
vbus comparator enable
0 = comparators (except session end) disabled
1 = comparators (except session end) enabled
USB PHY PLL suspend override
0 = Normal PLL operation
1 = Override PLL suspend state
CLK_OUT1 frequency select
0 = 24 MHz
1 = 12 MHz
USB PHY oscillator power down control
0 = PHY oscillator powered
1 = PHY oscillator power off
USB PHY power down control
0 = PHY powered
1 = PHY power off
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6.15.2 USB2.0 Peripheral Register Description(s)
The USB register memory mapping is shown in Table 6-71.
Table 6-71. USB 2.0 Register Descriptions
Address
Acronym
Register Description
0x01C6 4000
0x01C6 4004
0x01C6 4008
0x01C6 4010
0x01C6 4014
0x01C6 4020
0x01C6 4024
0x01C6 4028
0x01C6 402C
0x01C6 4030
0x01C6 4034
0x01C6 4038
0x01C6 403C
0x01C6 4040
0x01C6 4080
0x01C6 4084
0x01C6 4088
0x01C6 408C
0x01C6 4090
0x01C6 4094
0x01C6 4098
0x01C6 409C
0x01C6 40C0
0x01C6 40D0
0x01C6 40D4
0x01C6 40D8
0x01C6 40DC
0x01C6 40E0
0x01C6 40E4
0x01C6 40E8
0x01C6 40EC
REVR
Revision Register
CTRLR
Control Register
STATR
Status Register
RNDISR
RNDIS Register
AUTOREQ
INTSRCR
Auto Request Register
USB Interrupt Source Register
USB Interrupt Source Set Register
USB Interrupt Source Clear Register
USB Interrupt Mask Register
USB Interrupt Mask Set Register
USB Interrupt Mask Clear Register
USB Interrupt Source Masked Register
USB End of Interrupt Register
USB Interrupt Vector Register
TX CPPI Control Register
TX CPPI Teardown Register
INTSETR
INTCLRR
INTMSKR
INTMSKSETR
INTMSKCLRR
INTMASKEDR
EOIR
INTVECTR
TCPPICR
TCPPITDR
TCPPIEOIR
TCPPIIVECTR
TCPPIMSKSR
TCPPIRAWSR
TCPPIIENSETR
TCPPIIENCLRR
RCPPICR
TX CPPI DMA Controller End of Interrupt Register
TX CPPI DMA Controller Interrupt Vector Register
TX CPPI Masked Status Register
TX CPPI Raw Status Register
TX CPPI Interrupt Enable Set Register
TX CPPI Interrupt Enable Clear Register
RX CPPI Control Register
RCPPIMSKSR
RCPPIRAWSR
RCPPIENSETR
RCPPIIENCLRR
RBUFCNT0
RBUFCNT1
RBUFCNT2
RBUFCNT3
RX CPPI Masked Status Register
RX CPPI Raw Status Register
RX CPPI Interrupt Enable Set Register
RX CPPI Interrupt Enable Clear Register
RX Buffer Count 0 Register
RX Buffer Count 1 Register
RX Buffer Count 2 Register
RX Buffer Count 3 Register
TX/RX CCPI Channel 0 State Block
TX CPPI DMA State Word 0
0x01C6 4100
0x01C6 4104
0x01C6 4108
0x01C6 410C
0x01C6 4110
0x01C6 4114
0x01C6 4118
0x01C6 411C
0x01C6 4120
0x01C6 4124
0x01C6 4128
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
TCPPIDMASTATEW6
TCPPICOMPPTR
TX CPPI DMA State Word 1
TX CPPI DMA State Word 2
TX CPPI DMA State Word 3
TX CPPI DMA State Word 4
TX CPPI DMA State Word 5
TX CPPI DMA State Word 6
TX CPPI Completion Pointer
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RX CPPI DMA State Word 0
RX CPPI DMA State Word 1
RX CPPI DMA State Word 2
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Table 6-71. USB 2.0 Register Descriptions (continued)
Address
Acronym
Register Description
RX CPPI DMA State Word 3
RX CPPI DMA State Word 4
RX CPPI DMA State Word 5
RX CPPI DMA State Word 6
RX CPPI Completion Pointer
TX/RX CCPI Channel 1 State Block
TX CPPI DMA State Word 0
TX CPPI DMA State Word 1
TX CPPI DMA State Word 2
TX CPPI DMA State Word 3
TX CPPI DMA State Word 4
TX CPPI DMA State Word 5
TX CPPI DMA State Word 6
TX CPPI Completion Pointer
RX CPPI DMA State Word 0
RX CPPI DMA State Word 1
RX CPPI DMA State Word 2
RX CPPI DMA State Word 3
RX CPPI DMA State Word 4
RX CPPI DMA State Word 5
RX CPPI DMA State Word 6
RX CPPI Completion Pointer
TX/RX CCPI Channel 2 State Block
TX CPPI DMA State Word 0
TX CPPI DMA State Word 1
TX CPPI DMA State Word 2
TX CPPI DMA State Word 3
TX CPPI DMA State Word 4
TX CPPI DMA State Word 5
TX CPPI DMA State Word 6
TX CPPI Completion Pointer
RX CPPI DMA State Word 0
RX CPPI DMA State Word 1
RX CPPI DMA State Word 2
RX CPPI DMA State Word 3
RX CPPI DMA State Word 4
RX CPPI DMA State Word 5
RX CPPI DMA State Word 6
RX CPPI Completion Pointer
TX/RX CCPI Channel 3 State Block
TX CPPI DMA State Word 0
TX CPPI DMA State Word 1
TX CPPI DMA State Word 2
TX CPPI DMA State Word 3
TX CPPI DMA State Word 4
TX CPPI DMA State Word 5
TX CPPI DMA State Word 6
0x01C6 412C
0x01C6 4130
0x01C6 4134
0x01C6 4138
0x01C6 413C
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
0x01C6 4140
0x01C6 4144
0x01C6 4148
0x01C6 414C
0x01C6 4150
0x01C6 4154
0x01C6 4158
0x01C6 415C
0x01C6 4160
0x01C6 4164
0x01C6 4168
0x01C6 416C
0x01C6 4170
0x01C6 4174
0x01C6 4178
0x01C6 417C
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
TCPPIDMASTATEW6
TCPPICOMPPTR
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
0x01C6 4180
0x01C6 4184
0x01C6 4188
0x01C6 418C
0x01C6 4190
0x01C6 4194
0x01C6 4198
0x01C6 419C
0x01C6 41A0
0x01C6 41A4
0x01C6 41A8
0x01C6 41AC
0x01C6 41BA
0x01C6 41B4
0x01C6 41B8
0x01C6 41BC
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
TCPPIDMASTATEW6
TCPPICOMPPTR
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
0x01C6 41C0
0x01C6 41C4
0x01C6 41C8
0x01C6 41CC
0x01C6 41D0
0x01C6 41D4
0x01C6 41D8
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
TCPPIDMASTATEW6
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Table 6-71. USB 2.0 Register Descriptions (continued)
Address
Acronym
Register Description
0x01C6 41DC
0x01C6 41E0
0x01C6 41E4
0x01C6 41E8
0x01C6 41EC
0x01C6 41F0
0x01C6 41F4
0x01C6 41F8
0x01C6 41FC
TCPPICOMPPTR
TX CPPI Completion Pointer
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
RX CPPI DMA State Word 0
RX CPPI DMA State Word 1
RX CPPI DMA State Word 2
RX CPPI DMA State Word 3
RX CPPI DMA State Word 4
RX CPPI DMA State Word 5
RX CPPI DMA State Word 6
RX CPPI Completion Pointer
Core Registers
0x01C6 4400
0x01C6 4401
0x01C6 4402
0x01C6 4404
0x01C6 4406
0x01C6 4408
0x01C6 440A
0x01C6 440B
0x01C6 440C
0x01C6 440E
0x01C6 440F
0x01C6 4410
FADDR
Function Address Register
POWER
INTRTX
Power Management Register
Interrupt Register for Endpoint 0 plus TX Endpoints 1 to 4
Interrupt Register for RX Endpoints 1 to 4
Interrupt Enable Register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts
Interrupt Enable Register for INTRUSB
Frame Number Register
INTRRX
INTRTXE
INTRRXE
INTRUSB
INTRUSBE
FRAME
INDEX
Index register for selecting the endpoint status and control registers
Register to enable the USB 2.0 test modes
TESTMODE
TXMAXP
Maximum packet size for peripheral/host TX endpoint (Index register set to select
Endpoints 1 - 4 only)
PERI_CSR0
HOST_CSR0
PERI_TXCSR
HOST_TXCSR
RXMAXP
Control Status register for Endpoint 0 in Peripheral mode. (Index register set to
select Endpoint 0)
Control Status register for Endpoint 0 in Host mode. (Index register set to select
Endpoint 0)
0x01C6 4412
Control Status register for peripheral TX endpoint. (Index register set to select
Endpoints 1 - 4)
Control Status register for host TX endpoint. (Index register set to select
Endpoints 1 - 4)
0x01C6 4414
0x01C6 4416
Maximum packet size for peripheral/host RX endpoint (Index register set to select
Endpoints 1 - 4 only)
PERI_RXCSR
HOST_RXCSR
COUNT0
Control Status register for peripheral RX endpoint. (Index register set to select
Endpoints 1 - 4)
Control Status register for host RX endpoint. (Index register set to select
Endpoints 1 - 4)
Number of received bytes in Endpoint 0 FIFO. (Index register set to select
Endpoint 0)
0x01C6 4418
RXCOUNT
Number of bytes in host RX endpoint FIFO. (Index register set to select
Endpoints 1 - 4)
0x01C6 441A
0x01C6 441A
HOST_TYPE0
Defines the speed of Endpoint 0
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint. (Index register set to select Endpoints 1 - 4 only)
0x01C6 441B
0x01C6 441B
HOST_NAKLIMIT0
Sets the NAK response timeout on Endpoint 0. (Index register set to select
Endpoint 0)
HOST_TXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint. (Index register set to select
Endpoints 1 - 4 only)
0x01C6 441C
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint. (Index register set to select Endpoints 1 - 4 only)
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Table 6-71. USB 2.0 Register Descriptions (continued)
Address
Acronym
Register Description
0x01C6 441D
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint. (Index register set to select
Endpoints 1 - 4 only)
0x01C6 441F
0x01C6 4420
0x01C6 4424
0x01C6 4428
0x01C6 442C
0x01C6 4430
0x01C6 4462
0x01C6 4463
0x01C6 4464
0x01C6 4466
CONFIGDATA
FIFO0
Returns details of core configuration (Index register set to select Endpoint 0)
TX and RX FIFO Register for Endpoint 0
FIFO1
TX and RX FIFO Register for Endpoint 1
FIFO2
TX and RX FIFO Register for Endpoint 2
FIFO3
TX and RX FIFO Register for Endpoint 3
FIFO4
TX and RX FIFO Register for Endpoint 4
TXFIFOSZ
RXFIFOSZ
TXFIFOADDR
RXFIFOADDR
TX Endpoint FIFO Size (Index register set to select Endpoints 0 - 4 only)
RX Endpoint FIFO Size (Index register set to select Endpoints 0 - 4 only)
TX Endpoint FIFO Address (Index register set to select Endpoints 0 - 4 only)
RX Endpoint FIFO Address (Index register set to select Endpoints 0 - 4 only)
Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG0
0x01C6 4480
0x01C6 4482
TXFUNCADDR
Address of the target function that has to be accessed through the associated TX
Endpoint
TXHUBADDR
Address of the hub that has to be accessed through the associated TX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 4483
TXHUBPORT
Port of the hub that has to be accessed through the associated TX Endpoint. This
is used only when full speed or low speed device is connected via a USB2.0 high
speed hub
0x01C6 4484
0x01C6 4486
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the associated RX
Endpoint
Address of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 4487
RXHUBPORT
Port of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG1
0x01C6 4488
0x01C6 448A
TXFUNCADDR
Address of the target function that has to be accessed through the associated TX
Endpoint
TXHUBADDR
Address of the hub that has to be accessed through the associated TX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 448B
TXHUBPORT
Port of the hub that has to be accessed through the associated TX Endpoint. This
is used only when full speed or low speed device is connected via a USB2.0 high
speed hub
0x01C6 448C
0x01C6 448E
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the associated RX
Endpoint
Address of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 448F
RXHUBPORT
Port of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG2
0x01C6 4490
0x01C6 4492
TXFUNCADDR
Address of the target function that has to be accessed through the associated TX
Endpoint
TXHUBADDR
Address of the hub that has to be accessed through the associated TX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 4493
TXHUBPORT
Port of the hub that has to be accessed through the associated TX Endpoint. This
is used only when full speed or low speed device is connected via a USB2.0 high
speed hub
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Table 6-71. USB 2.0 Register Descriptions (continued)
Address
Acronym
Register Description
0x01C6 4494
RXFUNCADDR
Address of the target function that has to be accessed through the associated RX
Endpoint
0x01C6 4496
RXHUBADDR
RXHUBPORT
Address of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 4497
Port of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG3
0x01C6 4498
0x01C6 449A
TXFUNCADDR
Address of the target function that has to be accessed through the associated TX
Endpoint
TXHUBADDR
Address of the hub that has to be accessed through the associated TX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 449B
TXHUBPORT
Port of the hub that has to be accessed through the associated TX Endpoint. This
is used only when full speed or low speed device is connected via a USB2.0 high
speed hub
0x01C6 449C
0x01C6 449E
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the associated RX
Endpoint
Address of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 449F
RXHUBPORT
Port of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG4
0x01C6 44A0
0x01C6 44A2
TXFUNCADDR
Address of the target function that has to be accessed through the associated TX
Endpoint
TXHUBADDR
Address of the hub that has to be accessed through the associated TX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 44A3
TXHUBPORT
Port of the hub that has to be accessed through the associated TX Endpoint. This
is used only when full speed or low speed device is connected via a USB2.0 high
speed hub
0x01C6 44A4
0x01C6 44A6
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the associated RX
Endpoint
Address of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 44A7
RXHUBPORT
Port of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
Control and Status Register for Endpoint 0 - EOCSR0
0x01C6 4502
PERI_CSR0
Control Status Register for Endpoint 0 in Peripheral mode
Control Status Register for Endpoint 0 in Host mode
Number of Received Bytes in Endpoint 0 FIFO
Defines the Speed of Endpoint 0
HOST_CSR0
COUNT0
0x01C6 4508
0x01C6 450A
0x01C6 450B
0x01C6 450F
HOST_TYPE0
HOST_NAKLIMIT0
CONFIGDATA
Sets the NAK response timeout on Endpoint 0.
Returns details of core configuration
Control and Status Register for Endpoint 1 - EOCSR1
0x01C6 4510
0x01C6 4512
TXMAXP
Maximum Packet size for Peripheral/Host TX Endpoint
Control Status Register for Peripheral TX Endpoint
Control Status Register for Host TX Endpoint
PERI_TXCSR
HOST_TXCSR
RXMAXP
0x01C6 4514
Maximum Packet Size for Peripheral/Host RX Endpoint
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Table 6-71. USB 2.0 Register Descriptions (continued)
Address
Acronym
Register Description
0x01C6 4516
PERI_RXCSR
HOST_RXCSR
RXCOUNT
Control Status Register for Peripheral RX Endpoint
Control Status Register for Host RX Endpoint
Number of Bytes in Host RX Endpoint FIFO
0x01C6 4518
0x01C6 451A
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint.
0x01C6 451B
0x01C6 451C
0x01C6 451D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint.
Control and Status Register for Endpoint 2 - EOCSR2
0x01C6 4520
0x01C6 4522
TXMAXP
Maximum Packet Size for Peripheral/Host TX Endpoint
Control Status Register for Peripheral TX Endpoint
Control Status Register for Host TX Endpoint
Maximum Packet Size for Peripheral/Host RX Endpoint
Control Status Register for Peripheral RX Endpoint
Control Status Register for Host RX Endpoint
Number of Bytes in Host RX Endpoint FIFO
PERI_TXCSR
HOST_TXCSR
RXMAXP
0x01C6 4524
0x01C6 4526
PERI_RXCSR
HOST_RXCSR
RXCOUNT
0x01C6 4528
0x01C6 452A
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint.
0x01C6 452B
0x01C6 452C
0x01C6 452D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint.
Control and Status Register for Endpoint 3 - EOCSR3
0x01C6 4530
0x01C6 4532
TXMAXP
Maximum Packet Size for Peripheral/Host TX Endpoint
Control Status Register for Peripheral TX Endpoint
Control Status Register for Host TX Endpoint
Maximum Packet Size for Peripheral/Host RX Endpoint
Control Status Register for Peripheral RX Endpoint
Control Status Register for Host RX Endpoint
Number of Bytes in Host RX Endpoint FIFO
PERI_TXCSR
HOST_TXCSR
RXMAXP
0x01C6 4534
0x01C6 4536
PERI_RXCSR
HOST_RXCSR
RXCOUNT
0x01C6 4538
0x01C6 453A
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint.
0x01C6 453B
0x01C6 453C
0x01C6 453D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint.
Control and Status Register for Endpoint 4 - EOCSR4
0x01C6 4540
0x01C6 4542
TXMAXP
Maximum Packet Size for Peripheral/Host TX Endpoint
Control Status Register for Peripheral TX Endpoint
Control Status Register for Host TX Endpoint
Maximum Packet Size for Peripheral/Host RX Endpoint
Control Status Register for Peripheral RX Endpoint
Control Status Register for Host RX Endpoint
Number of Bytes in Host RX Endpoint FIFO
PERI_TXCSR
HOST_TXCSR
RXMAXP
0x01C6 4544
0x01C6 4546
PERI_RXCSR
HOST_RXCSR
RXCOUNT
0x01C6 4548
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Table 6-71. USB 2.0 Register Descriptions (continued)
Address
Acronym
Register Description
0x01C6 454A
0x01C6 454B
0x01C6 454C
0x01C6 454D
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint.
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint.
6.15.3 USB2.0 Electrical Data/Timing
Table 6-72. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see
Figure 6-59)
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps
NO.
PARAMETER
UNIT
MIN
75
MAX
MIN
4
MAX
MIN
0.5
0.5
–
MAX
1
2
3
4
5
tr(D)
Rise time, USB_DP and USB_DM signals(1)
Fall time, USB_DP and USB_DM signals(1)
Rise/Fall time, matching(2)
Output signal cross-over voltage(1)
Source (Host) Driver jitter, next transition
Function Driver jitter, next transition
Source (Host) Driver jitter, paired transition(4)
Function Driver jitter, paired transition
Pulse duration, EOP transmitter
Pulse duration, EOP receiver
300
300
125
2
20
20
ns
ns
%
tf(D)
75
4
trfM
80
90 111.11
–
–
VCRS
1.3
1.3
2
2
–
V
tjr(source)NT
tjr(FUNC)NT
tjr(source)PT
tjr(FUNC)PT
tw(EOPT)
tw(EOPR)
t(DRATE)
2
(3)ns
ns
ns
ns
ns
ns
(3)
(3)
(3)
25
2
6
1
1
10
1
7
8
9
1250
670
1500
160
82
175
–
–
–
Data Rate
1.5
–
12
49.5
10.1
480 Mb/s
49.5
10.1 kΩ
10 ZDRV
Driver Output Resistance
–
28
40.5
9.9
Ω
11 USB_R1
USB reference resistor
9.9
10.1
9.9
(1) Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
(2) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(4) tjr = tpx(1) - tpx(0)
t
t
per − jr
USB_DM
90% V
OH
V
CRS
10% V
OL
USB_DP
t
f
t
r
Figure 6-59. USB2.0 Integrated Transceiver Interface Timing
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USB
USB_VSSREF
USB_R1
10 K Ω 1ꢀ(A)
A. Place the 10 K Ω 1ꢀ aꢁ clꢂꢁe tꢂ the ꢃeꢄvce aꢁ ꢅꢂꢁꢁvile.
Figure 6-60. USB Reference Resistor Routing
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6.16 Universal Asynchronous Receiver/Transmitter (UART)
DM6446 has 3 UART peripherals. Each UART has the following features:
•
•
•
•
•
•
•
16-byte storage space for both the transmitter and receiver FIFOs
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
Programmable auto-rts and auto-cts for autoflow control
Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
Prioritized interrupts
Programmable serial data formats
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, or no parity bit generation and detection
1, 1.5, or 2 stop bit generation
•
•
•
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
–
–
Loopback controls for communications link fault isolation
Break, parity, overrun, and framing error simulation
•
Modem control functions (CTS, RTS) on UART2 only.
The UART0/1/2 registers are listed in Table 6-73, Table 6-74, and Table 6-75.
6.16.1 UART Peripheral Register Description(s)
Table 6-73. UART0 Register Descriptions
HEX ADDRESS RANGE
0x01C2 0000
ACRONYM
REGISTER NAME
RBR
UART0 Receiver Buffer Register (Read Only)
UART0 Transmitter Holding Register (Write Only)
UART0 Interrupt Enable Register
UART0 Interrupt Identification Register (Read Only)
UART0 FIFO Control Register (Write Only)
UART0 Line Control Register
UART0 Modem Control Register
UART0 Line Status Register
0x01C2 0000
THR
0x01C2 0004
IER
0x01C2 0008
IIR
0x01C2 0008
FCR
0x01C2 000C
0x01C2 0010
LCR
MCR
0x01C2 0014
LSR
0x01C2 0018
-
Reserved
0x01C2 001C
0x01C2 0020
-
Reserved
DLL
UART0 Divisor Latch (LSB)
0x01C2 0024
DLH
UART0 Divisor Latch (MSB)
0x01C2 0028
PID1
Peripheral Identification Register 1
Peripheral Identification Register 2
UART0 Power and Emulation Management Register
Reserved
0x01C2 002C
0x01C2 0030
PID2
PWREMU_MGMT
-
0x01C2 0034 - 0x01C2 03FF
Table 6-74. UART1 Register Descriptions
HEX ADDRESS RANGE
0x01C2 0400
ACRONYM
RBR
REGISTER NAME
UART1 Receiver Buffer Register (Read Only)
UART1 Transmitter Holding Register (Write Only)
UART1 Interrupt Enable Register
0x01C2 0400
THR
0x01C2 0404
IER
0x01C2 0408
IIR
UART1 Interrupt Identification Register (Read Only)
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Table 6-74. UART1 Register Descriptions (continued)
HEX ADDRESS RANGE
0x01C2 0408
ACRONYM
REGISTER NAME
FCR
UART1 FIFO Control Register (Write Only)
UART1 Line Control Register
UART1 Modem Control Register
UART1 Line Status Register
Reserved
0x01C2 040C
LCR
0x01C2 0410
MCR
0x01C2 0414
LSR
0x01C2 0418
-
0x01C2 041C
-
Reserved
0x01C2 0420
DLL
UART1 Divisor Latch (LSB)
UART1 Divisor Latch (MSB)
Peripheral Identification Register 1
Peripheral Identification Register 2
UART1 Power and Emulation Management Register
Reserved
0x01C2 0424
DLH
0x01C2 0428
PID1
0x01C2 042C
PID2
0x01C2 0430
PWREMU_MGMT
-
0x01C2 0434 - 0x01C2 07FF
Table 6-75. UART2 Register Descriptions
HEX ADDRESS RANGE
0x01C2 0800
ACRONYM
REGISTER NAME
RBR
UART2 Receiver Buffer Register (Read Only)
UART2 Transmitter Holding Register (Write Only)
UART2 Interrupt Enable Register
UART2 Interrupt Identification Register (Read Only)
UART2 FIFO Control Register (Write Only)
UART2 Line Control Register
UART2 Modem Control Register
UART2 Line Status Register
0x01C2 0800
THR
0x01C2 0804
IER
0x01C2 0808
IIR
0x01C2 0808
FCR
0x01C2 080C
0x01C2 0810
LCR
MCR
0x01C2 0814
LSR
0x01C2 0818
-
Reserved
0x01C2 081C
0x01C2 0820
-
Reserved
DLL
UART2 Divisor Latch (LSB)
0x01C2 0824
DLH
UART2 Divisor Latch (MSB)
0x01C2 0828
PID1
Peripheral Identification Register 1
Peripheral Identification Register 2
UART2 Power and Emulation Management Register
Reserved
0x01C2 082C
0x01C2 0830
PID2
PWREMU_MGMT
-
0x01C2 0834 - 0x01C2 0BFF
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6.16.2 UART Electrical Data/Timing
Table 6-76. Timing Requirements for UARTx Receive(1) (see Figure 6-61)
NO.
4
MIN
0.96U
0.96U
MAX
1.05U
1.05U
UNIT
ns
tw(URXDB)
tw(URXSB)
Pulse duration, receive data bit (RXDn) [15/30/100 pF]
Pulse duration, receive start bit [15/30/100 pF]
5
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 6-77. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
(see Figure 6-61)
NO.
1
PARAMETER
MIN
MAX
128
UNIT
kHz
ns
f(baud)
Maximum programmable baud rate
2
tw(UTXDB)
tw(UTXSB)
Pulse duration, transmit data bit (TXDn) [15/30/100 pF]
Pulse duration, transmit start bit [15/30/100 pF]
U - 2
U - 2
U + 2
U + 2
3
ns
(1) U = UART baud time = 1/programmed baud rate.
3
5
2
Start
Bit
UART_TXDn
Data Bits
4
Start
Bit
UART_RXDn
Data Bits
Figure 6-61. UART Transmit/Receive Timing
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6.17 Serial Peripheral Interface (SPI)
The DM6446 SPI peripheral provides a programmable length shift register which allows serial
communication with other SPI devices through a 3 or 4 wire interface. The SPI supports the following
features:
•
•
•
Master mode operation
2 chip selects for interfacing to multiple slave SPI devices.
3 or 4 wire interface
The SPI registers are shown in Table 6-78.
6.17.1 SPI Peripheral Register Description(s)
Table 6-78. SPI Register Descriptions
HEX ADDRESS RANGE
0x01C6 6800
ACRONYM
REGISTER NAME
SPIGCR0
SPIGCR1
SPIINT
SPI Global Control Register 0
SPI Global Control Register 1
SPI Interrupt Register
0x01C6 6804
0x01C6 6808
0x01C6 680C
0x01C6 6810
SPILVL
SPIFLG
SPIPC0
–
SPI Interrupt Level Register
SPI Flag Status Register
SPI Pin Control Register 0
Reserved
0x01C6 6814
0x01C6 6818
0x01C6 681C
0x01C6 6820 - 0x01C6 6838
0x01C6 683C
0x01C6 6840
SPIPC2
–
SPI Pin Control Register 2
Reserved
SPIDAT1
SPIBUF
SPIEMU
SPIDELAY
SPIDEF
SPIFMT0
SPIFMT1
SPIFMT2
SPIFMT3
INTVEC0
INTVEC1
SPI Shift Register 1
SPI Buffer Register
0x01C6 6844
SPI Emulation Register
SPI Delay Register
0x01C6 6848
0x01C6 684C
0x01C6 6850
SPI Default Chip Select Register
SPI Data Format Register 0
SPI Data Format Register 1
SPI Data Format Register 2
SPI Data Format Register 3
SPI Interrupt Vector Register 0
SPI Interrupt Vector Register 1
Reserved
0x01C6 6854
0x01C6 6858
0x01C6 685C
0x01C6 6860
0x01C6 6864
0x01C6 6868 - 0x01C6 6FFF
6.17.2 SPI Electrical Data/Timing
Table 6-79. Timing Requirements for SPI (All Modes)(1) (see Figure 6-62)
NO.
1
MIN
30.3
MAX
UNIT
ns
tc(CLK)
Cycle time, SPI_CLK
56888.89
0.55*T
2
tw(CLKH)
tw(CLKL)
Pulse duration, SPI_CLK high (All Master Modes)
Pulse duration, SPI_CLK low (All Master Modes
0.45*T
0.45*T
ns
3
0.55*T
ns
(1) T = tc(CLK) [SPI_CLK period is equal to the SPI module clock divided by a configurable divider.]
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1
2
3
SPIx_CLK
(Clock Polarity = 0)
SPIx_CLK
(Clock Polarity = 1)
Figure 6-62. SPI_CLK Timing
6.17.2.1 SPI Master Mode Timings (Clock Phase = 0)
Table 6-80. Timing Requirements for SPI Master Mode [Clock Phase = 0] (1)(see Figure 6-63)
NO.
MIN
MAX
UNIT
Setup time, SPI_DI (input) valid before SPI_CLK (output)
falling edge
4
tsu(DIV-CLKL)
tsu(DIV-CLKH)
th(CLKL-DIV)
th(CLKH-DIV)
Clock Polarity = 0
Clock Polarity = 1
Clock Polarity = 0
Clock Polarity = 1
0.5P + 9.4
ns
Setup time, SPI_DI (in put) valid before SPI_CLK (output)
rising edge
5
6
7
0.5P + 9.4
0.5P - 4.5
0.5P - 4.5
ns
ns
ns
Hold time, SPI_DI (input) valid after SPI_CLK (output) falling
edge
Hold time, SPI_DI (input) valid after SPI_CLK (output) rising
edge
(1) P = Period of the SPI module clock in nanoseconds (SYSCLK5).
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Table 6-81. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode
[Clock Phase = 0] (see Figure 6-63)
NO.
PARAMETER
MIN
MAX UNIT
Delay time, SPI_CLK (output) rising edge to SPI_DO
(output) transition
8
td(CLKH-DOV)
td(CLKL-DOV)
Clock Polarity = 0
Clock Polarity = 1
-4
-4
5
5
ns
ns
ns
ns
Delay time, SPI_CLK (output) falling edge to SPI_DO
(output) transition
9
Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or
falling edge(1)(2)
10 td(ENL-CLKH/L)
11 td(CLKH/L-ENH)
2P - 2.3
Delay time, SPI_CLK (output) rising or falling edge to SPI_EN[1:0] (output)
rising edge(1)(2)(3)
1P + 0.5C - 0.2
(1) P = Period of the SPI module clock in nanoseconds (SYSCLK5).
(2) This delay can be increased under software control by the C2TDELAY register bit field in the SPIDELAY register.
(3) C = Period of SPI_CLK signal in ns.
11
SPI_EN
SPI_CLK
(Clock Polarity = 0)
10
SPI_CLK
(Clock Polarity = 1)
7
6
4
5
SPI_DI
(Input)
MSB IN
DATA
LSB IN
8
9
SPI_DO
(Output)
MSB OUT
DATA
LSB OUT
Figure 6-63. SPI Master Mode External Timing (Clock Phase = 0)
6.17.2.2 SPI Master Mode Timings (Clock Phase = 1)
Table 6-82. Timing Requirements for SPI Master Mode [Clock Phase = 1](1) (see Figure 6-64)
NO.
MIN
MAX
UNIT
Setup time, SPI_DI (input) valid before SPI_CLK
(output) rising edge
13 tsu(DIV-CLKL)
Clock Polarity = 0
Clock Polarity = 1
Clock Polarity = 0
Clock Polarity = 1
0.5P + 9.4
ns
Setup time, SPI_DI (in put) valid before SPI_CLK
(output) falling edge
14 tsu(DIV-CLKH)
15 th(CLKL-DIV)
16 th(CLKH-DIV)
0.5P + 9.4
0.5P - 4.5
0.5P - 4.5
ns
ns
ns
Hold time, SPI_DI (input) valid after SPI_CLK (output)
rising edge
Hold time, SPI_DI (input) valid after SPI_CLK (output)
falling edge
(1) P = Period of the SPI module clock in nanoseconds (SYSCLK5).
Table 6-83. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode
[Clock Phase = 1] (see Figure 6-64)
NO.
PARAMETER
MIN
MAX UNIT
Delay time, SPI_CLK (output) falling edge to SPI_DO
(output) transition
17 td(CLKL-DOV)
Clock Polarity = 0
-4
5
ns
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Table 6-83. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode
[Clock Phase = 1] (see Figure 6-64) (continued)
NO.
PARAMETER
MIN
MAX UNIT
Delay time, SPI_CLK (output) rising edge to SPI_DO
(output) transition
18 td(CLKH-DOV)
Clock Polarity = 1
-4
5
ns
ns
ns
Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or
falling edge(1)(2)(3)
19 td(ENL-CLKH/L)
20 td(CLKH/L-ENH)
2P + 0.5C - 2.3
1P - 0.2
Delay time, SPI_CLK (output) rising or falling edge to SPI_EN[1:0] (output)
rising edge(1)(2)
(1) P = Period of the SPI module clock in nanoseconds (SYSCLK5).
(2) This delay can be increased under software control by the C2TDELAY register bit field in the SPIDELAY register.
(3) C = Period of SPI_CLK signal in ns.
20
SPI_EN
SPI_CLK
(Clock Polarity = 0)
19
SPI_CLK
(Clock Polarity = 1)
15
16
13
14
SPI_DI
MSB IN
DATA
DATA
LSB IN
18
(Input)
17
SPI_DO
(Output)
MSB OUT
LSB OUT
Figure 6-64. SPI Master Mode External Timing (Clock Phase = 1)
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6.18 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between DM6446 and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP
through the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
Slew-Rate Limited Open-Drain Output Buffers
For more detailed information on the I2C peripheral, see the TMS320DM644x DMSoC Peripherals
Overview Reference Guide (literature number SPRUE19).
CAUTION
The DM6446 I2C pins use a standard ±4-mA LVCMOS buffer, not the slow I/O buffer
defined in the I2C specification. Series resistors may be necessary to reduce noise at
the system level.
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6.18.1 I2C Peripheral Register Description(s)
Table 6-84. I2C Registers
HEX ADDRESS RANGE
0x1c2 1000
0x1c2 1004
0x1c2 1008
0x1c2 100C
0x1c2 1010
0x1c2 1014
0x1c2 1018
0x1c2 101C
0x1c2 1020
0x1c2 1024
0x1c2 1028
0x1c2 102C
0x1c2 1030
0x1c2 1034
0x1c2 1038
ACRONYM
ICOAR
ICIMR
REGISTER NAME
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
I2C Clock Divider Low Register
I2C Clock Divider High Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
ICPID1
ICPID2
I2C Peripheral Identification Register 1
I2C Peripheral Identification Register 2
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6.18.2 I2C Electrical Data/Timing
6.18.2.1 Inter-Integrated Circuits (I2C) Timing
Table 6-85. Timing Requirements for I2C Timings(1) (see Figure 6-65)
STANDARD
MODE
FAST MODE
NO.
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
3
th(SCLL-SDAL)
µs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SDA-SCLL)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(3)
0(3) 0.9(4)
µs
Pulse duration, SDA high between STOP and START
conditions
8
tw(SDAH)
4.7
1.3
µs
(5)
9
tr(SDA)
Rise time, SDA
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
µs
ns
pF
(5)
(5)
(5)
10
11
12
13
14
15
tr(SCL)
Rise time, SCL
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4
0.6
0
50
(5)
Cb
400
400
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
SCL
6
8
14
4
13
5
10
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-65. I2C Receive Timings
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Table 6-86. Switching Characteristics for I2C Timings (see Figure 6-66)
STANDARD
MODE
FAST MODE
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
16
17
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Delay time, SCL high to SDA low (for a repeated START
condition)
td(SCLH-SDAL)
4.7
4
0.6
0.6
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
18
td(SDAL-SCLL)
µs
19
20
21
22
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
µs
µs
ns
µs
tw(SCLH)
Pulse duration, SCL high
td(SDAV-SCLH)
tv(SCLL-SDAV)
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low
250
0
0.9
10
Pulse duration, SDA high between STOP and START
conditions
23
tw(SDAH)
4.7
4
1.3
0.6
µs
28
29
td(SCLH-SDAH)
Cp
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
µs
pF
10
SDA
21
23
19
28
20
SCL
16
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 6-66. I2C Transmit Timings
CAUTION
The DM6446 I2C pins use a standard ±4-mA LVCMOS buffer, not the slow I/O buffer
defined in the I2C specification. Series resistors may be necessary to reduce noise at
the system level.
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6.19 Audio Serial Port (ASP)
The ASP provides these functions:
•
•
•
•
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
•
External shift clock or an internal, programmable frequency shift clock for data transfer
For more detailed information on the ASP peripheral, see the Documentation Support section for the
Audio Serial Port (ASP) Reference Guide.
6.19.1 ASP Peripheral Register Description(s)
Table 6-87. ASP Register Descriptions
HEX ADDRESS RANGE
0x01E0 2000
ACRONYM
DRR
REGISTER NAME
ASP Data Receive Register
ASP Data Transmit Register
0x01E0 2004
DXR
0x01E0 2008
SPCR
RCR
ASP Serial Port Control Register
ASP Receive Control Register
ASP Transmit Control Register
ASP Sample Rate Generator Register
ASP Pin Control Register
0x01E0 200C
0x01E0 2010
XCR
0x01E0 2014
SRGR
PCR
0x01E0 2024
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6.19.2 ASP Electrical Data/Timing
6.19.2.1 Audio Serial Port (ASP) Timing
Table 6-88. Timing Requirements for ASP(1) (see Figure 6-67)
NO.
2
MIN
38.5 or 2P(2)(3)
19.25 or P(2)(3)(4)
MAX
UNIT
ns
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
3
Pulse duration, CLKR/X high or CLKR/X low
ns
11.8
1.3
6
5
6
tsu(FRH-CKRL)
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
3
10.7
0.9
3
7
8
Hold time, DR valid after CLKR low
3.1
12.2
1.4
6
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = 1/SYSCLK5 clock frequency in ns. For example, when running parts at DSP frequency of 594 MHz, use P = 10.1 ns.
(3) Use whichever value is greater.
(4) The ASP does not require a duty cycle specification, just ensure the minimum pulse duration specification is met.
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Table 6-89. Switching Characteristics Over Recommended Operating Conditions for ASP(1)(2)
(see Figure 6-67)
NO.
2
PARAMETER
Cycle time, CLKR/X
MIN
MAX
UNIT
ns
tc(CKRX)
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
38.5(3)
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
C - 1(4)
C + 1(4)
ns
4
td(CKRH-FRV)
-2.1
3
ns
-1.7
3
14.4
9
td(CKXH-FXV)
tdis(CKXH-DXHZ)
td(CKXH-DXV)
Delay time, CLKX high to internal FSX valid
ns
ns
1.7
-3.9
4
Disable time, DX high impedance following last data
bit from CLKX high
12
13
2.1
13
-3.9 + D1(5)
4 + D2(5)
ns
ns
Delay time, CLKX high to DX valid
2.1 + D1(5) 14.5 + D2(5)
-2.3 + D1(6) 4 + D2(6)
1.9 + D1(6) 12.1 + D2(6)
Delay time, FSX high to DX valid
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
14
td(FXH-DXV)
ns
FSX ext
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) C = H or L
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency [SYSCLK1])
S = sample rate generator input clock = Not Supported if CLKSM = 0 (no CLKS pin on DM6446)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the ASP bit rate does not exceed the maximum limit [see footnote (3) above].
(5) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
(6) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
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2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
DR
7
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX
(XDATDLY=00b)
(A)
13
14
13
(A)
12
DX
Bit 0
Bit(n-1)
(n-2)
(n-3)
A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.
Figure 6-67. ASP Timing
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6.20 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between DM6446 and the
network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and
100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS)
support.
The EMAC controls the flow of packet data from the DM6446 device to the PHY. The MDIO module
controls PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the DM6446 device through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
For the DM6446 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Module Reference Guide which describes the DM6446 EMAC peripheral in detail, see the Documentation
Support section . For a list of supported registers and register fields, see Table 6-90 [Ethernet MAC
(EMAC) Control Registers] and Table 6-91 [EMAC Statistics Registers] in this data manual.
6.20.1 EMAC Peripheral Register Description(s)
Table 6-90. Ethernet MAC (EMAC) Control Registers
HEX ADDRESS RANGE
01C8 0000
01C8 0004
01C8 0008
01C8 0010
01C8 0014
01C8 0018
01C8 0080
01C8 0084
01C8 0088
01C8 008C
01C8 0090
01C8 00A0
01C8 00A4
01C8 00A8
01C8 00AC
01C8 00B0
01C8 00B4
01C8 00B8
01C8 00BC
01C8 0100
01C8 0104
01C8 0108
01C8 010C
01C8 0110
01C8 0114
01C8 0120
01C8 0124
01C8 0128
01C8 012C
ACRONYM
TXIDVER
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
TXCONTROL
TXTEARDOWN
Transmit Teardown Register
RXIDVER
Receive Identification and Version Register
Receive Control Register
RXCONTROL
RXTEARDOWN
Receive Teardown Register
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
Receive Unicast Clear Register
Receive Maximum Length Register
RXBUFFEROFFSET
RXFILTERLOWTHRESH
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
Receive Buffer Offset Register
Receive Filter Low Priority Frame Threshold Register
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
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Table 6-90. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
REGISTER NAME
01C8 0130
01C8 0134
01C8 0138
01C8 013C
01C8 0140
01C8 0144
01C8 0148
01C8 014C
01C8 0150
01C8 0154
01C8 0158
01C8 015C
01C8 0160
01C8 0164
01C8 0168
01C8 016C
01C8 0170
01C8 0174
01C8 01D0
01C8 01D4
01C8 01D8
01C8 01DC
01C8 01E0
01C8 01E4
01C8 01E8
01C8 01EC
01C8 0200 - 01C8 02FC
01C8 0500
01C8 0504
01C8 0508
01C8 0600
01C8 0604
01C8 0608
01C8 060C
01C8 0610
01C8 0614
01C8 0618
01C8 061C
01C8 0620
01C8 0624
01C8 0628
01C8 062C
01C8 0630
01C8 0634
01C8 0638
01C8 063C
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Receive Channel 7 Flow Control Threshold Register
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
MAC Status Register
Emulation Control Register
FIFO Control Register (Transmit and Receive)
MAC Configuration Register
Soft Reset Register
MAC Source Address Low Bytes Register (Lower 16-bits)
MAC Source Address High Bytes Register (Upper 32-bits)
MAC Hash Address Register 1
MACHASH2
MAC Hash Address Register 2
BOFFTEST
Back Off Test Register
TPACETEST
RXPAUSE
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
TXPAUSE
Transmit Pause Timer Register
(see Table 6-91)
MACADDRLO
MACADDRHI
MACINDEX
EMAC Statistics Registers
MAC Address Low Bytes Register
MAC Address High Bytes Register
MAC Index Register
TX0HDP
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive Channel 7 DMA Head Descriptor Pointer Register
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
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Table 6-90. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Transmit Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0640
TX0CP
Transmit Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0644
01C8 0648
01C8 064C
01C8 0650
01C8 0654
01C8 0658
01C8 065C
01C8 0660
01C8 0664
01C8 0668
01C8 066C
01C8 0670
01C8 0674
01C8 0678
01C8 067C
TX1CP
TX2CP
TX3CP
TX4CP
TX5CP
TX6CP
TX7CP
RX0CP
RX1CP
RX2CP
RX3CP
RX4CP
RX5CP
RX6CP
RX7CP
Transmit Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
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Table 6-91. EMAC Statistics Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
01C8 0200
RXGOODFRAMES
Good Receive Frames Register
Broadcast Receive Frames Register
(Total number of good broadcast frames received)
01C8 0204
RXBCASTFRAMES
Multicast Receive Frames Register
(Total number of good multicast frames received)
01C8 0208
01C8 020C
01C8 0210
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
Pause Receive Frames Register
Receive CRC Errors Register (Total number of frames received with
CRC errors)
Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
01C8 0214
01C8 0218
01C8 021C
01C8 0220
RXALIGNCODEERRORS
RXOVERSIZED
Receive Oversized Frames Register
(Total number of oversized frames received)
Receive Jabber Frames Register
(Total number of jabber frames received)
RXJABBER
Receive Undersized Frames Register
(Total number of undersized frames received)
RXUNDERSIZED
01C8 0224
01C8 0228
01C8 022C
RXFRAGMENTS
RXFILTERED
Receive Frame Fragments Register
Filtered Receive Frames Register
Received QOS Filtered Frames Register
RXQOSFILTERED
Receive Octet Frames Register
(Total number of received bytes in good frames)
01C8 0230
01C8 0234
RXOCTETS
Good Transmit Frames Register
(Total number of good frames transmitted)
TXGOODFRAMES
01C8 0238
01C8 023C
01C8 0240
01C8 0244
01C8 0248
01C8 024C
01C8 0250
01C8 0254
01C8 0258
01C8 025C
01C8 0260
01C8 0264
01C8 0268
01C8 026C
01C8 0270
01C8 0274
01C8 0278
01C8 027C
01C8 0280
01C8 0284
01C8 0288
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
TXCOLLISION
Transmit Collision Frames Register
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit Underrun Error Register
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
FRAME64
Transmit and Receive 64 Octet Frames Register
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns
Register
01C8 028C
RXDMAOVERRUNS
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Table 6-92. EMAC Control Module Registers
HEX ADDRESS RANGE
0x01C8 1004
ACRONYM
EWCTL
REGISTER NAME
Interrupt control register
Interrupt timer count
0x01C8 1008
EWINTTCNT
Table 6-93. EMAC Control Module RAM
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
EMAC Control Module Descriptor Memory
0x01C8 2000 - 0x01C8 3FFF
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6.20.2 EMAC Electrical Data/Timing
Table 6-94. Timing Requirements for MRCLK (see Figure 6-68)
NO.
1
MIN
40
MAX
UNIT
ns
tc(MRCLK)
Cycle time, MRCLK
2
tw(MRCLKH)
tw(MRCLKL)
Pulse duration, MRCLK high
Pulse duration, MRCLK low
14
14
ns
3
ns
1
2
3
MRCLK
Figure 6-68. MRCLK Timing (EMAC - Receive)
Table 6-95. Timing Requirements for MTCLK (see Figure 6-68)
NO.
1
MIN
MAX
UNIT
ns
tc(MTCLK)
Cycle time, MTCLK
40
14
14
2
tw(MTCLKH)
tw(MTCLKL)
Pulse duration, MTCLK high
Pulse duration, MTCLK low
ns
3
ns
1
2
3
MTCLK
Figure 6-69. MTCLK Timing (EMAC - Transmit)
Table 6-96. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 6-70)
NO.
1
MIN
MAX
UNIT
ns
tsu(MRXD-MRCLKH)
th(MRCLKH-MRXD)
Setup time, receive selected signals valid before MRCLK high
Hold time, receive selected signals valid after MRCLK high
8
8
2
ns
(1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.
1
2
MRCLK (Input)
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 6-70. EMAC Receive Interface Timing
Table 6-97. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
10/100 Mbit/s(1) (see Figure 6-71)
NO.
MIN
MAX
25
UNIT
1
td(MTCLKH-MTXD)
Delay time, MTCLK high to transmit selected signals valid
5
ns
(1) Transmit selected signals include: MTXD3-MTXD0, and MTXEN.
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1
MTCLK (Input)
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 6-71. EMAC Transmit Interface Timing
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6.21 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
For more detailed information on the MDIO peripheral, see the Documentation Support section for the
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module Reference
Guide. For a list of supported registers and register fields, see Table 6-98 [MDIO Registers] in this data
manual.
6.21.1 Peripheral Register Description(s)
Table 6-98. MDIO Registers
HEX ADDRESS RANGE
0x01C8 4000
ACRONYM
–
REGISTER NAME
Reserved
0x01C8 4004
CONTROL
ALIVE
MDIO Control Register
0x01C8 4008
MDIO PHY Alive Status Register
0x01C8 400C
LINK
MDIO PHY Link Status Register
0x01C8 4010
LINKINTRAW
LINKINTMASKED
–
MDIO Link Status Change Interrupt (Unmasked) Register
MDIO Link Status Change Interrupt (Masked) Register
Reserved
0x01C8 4014
0x01C8 4018
0x01C8 4020
USERINTRAW
USERINTMASKED
USERINTMASKSET
MDIO User Command Complete Interrupt (Unmasked) Register
MDIO User Command Complete Interrupt (Masked) Register
MDIO User Command Complete Interrupt Mask Set Register
0x01C8 4024
0x01C8 4028
0x01C8 402C
USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register
0x01C8 4030 - 0x01C8 407C
0x01C8 4080
–
Reserved
USERACCESS0
USERPHYSEL0
USERACCESS1
USERPHYSEL1
–
MDIO User Access Register 0
MDIO User PHY Select Register 0
MDIO User Access Register 1
MDIO User PHY Select Register 1
Reserved
0x01C8 4084
0x01C8 4088
0x01C8 408C
0x01C8 4090 - 0x01C8 47FF
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6.21.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-99. Timing Requirements for MDIO Input (see Figure 6-72 and Figure 6-73)
NO.
1
MIN
400
MAX
UNIT
ns
tc(MDCLK)
Cycle time, MDCLK
2
tw(MDCLK)
Pulse duration, MDCLK high/low
180
ns
3
tt(MDCLK)
Transition time, MDCLK
5
ns
ns
ns
4
tsu(MDIO-MDCLKH)
th(MDCLKH-MDIO)
Setup time, MDIO data input valid before MDCLK high
Hold time, MDIO data input valid after MDCLK high
15
0
5
1
3
3
MDCLK
4
5
MDIO
(input)
Figure 6-72. MDIO Input Timing
Table 6-100. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-73)
NO.
MIN
-0.6
MAX
UNIT
7
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
100
ns
1
MDCLK
7
MDIO
(output)
Figure 6-73. MDIO Output Timing
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6.22 Timer
The DM6446 device has 3 64-bit general-purpose timers which have the following features:
•
•
64-bit count-up counter
Timer modes:
–
–
–
64-bit general-purpose timer mode
Dual 32-bit general-purpose timer mode (Timer 0 and 1)
Watchdog timer mode (Timer 2)
•
•
2 possible clock sources:
–
–
Internal clock
External clock input via timer input pin TIM_IN (Timer 0 only)
2 operation modes:
–
–
One-time operation (timer runs for one period then stops)
Continuous operation (timer automatically resets after each period)
•
•
Generates interrupts to both the DSP and the ARM CPUs
Generates sync event to EDMA
For more detailed information, see the Documentation Support section for the Timer Reference Guide.
6.22.1 Timer Peripheral Register Description(s)
Table 6-101. Timer 0 Registers
HEX ADDRESS RANGE
0x01C2 1400
ACRONYM
DESCRIPTION
-
Reserved
0x01C2 1404
EMUMGT_CLKSPD
Timer 0 Emulation Management/Clock Speed Register
Timer 0 Counter Register 12
Timer 0 Counter Register 34
Timer 0 Period Register 12
Timer 0 Period Register 34
Timer 0 Control Register
0x01C2 1410
TIM12
TIM34
PRD12
PRD34
TCR
0x01C2 1414
0x01C2 1418
0x01C2 141C
0x01C2 1420
0x01C2 1424
TGCR
-
Timer 0 Global Control Register
Reserved
0x01C2 1428 - 0x01C2 17FF
Table 6-102. Timer 1 Registers
HEX ADDRESS RANGE
0x01C2 1800
ACRONYM
DESCRIPTION
-
Reserved
0x01C2 1804
EMUMGT_CLKSPD
Timer 1 Emulation Management/Clock Speed Register
Timer 1 Counter Register 12
Timer 1 Counter Register 34
Timer 1 Period Register 12
Timer 1 Period Register 34
Timer 1 Control Register
0x01C2 1810
TIM12
TIM34
PRD12
PRD34
TCR
0x01C2 1814
0x01C2 1818
0x01C2 181C
0x01C2 1820
0x01C2 1824
TGCR
-
Timer 1 Global Control Register
Reserved
0x01C2 1828 - 0x01C2 1BFF
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Table 6-103. Timer 2 (Watchdog) Registers
HEX ADDRESS RANGE
0x01C2 1C00
ACRONYM
DESCRIPTION
-
EMUMGT_CLKSPD
TIM12
Reserved
0x01C2 1C04
Timer 2 Emulation Management/Clock Speed Register
Timer 2 Counter Register 12
Timer 2 Counter Register 34
Timer 2 Period Register 12
0x01C2 1C10
0x01C2 1C14
TIM34
0x01C2 1C18
PRD12
PRD34
TCR
0x01C2 1C1C
Timer 2 Period Register 34
0x01C2 1C20
Timer 2 Control Register
0x01C2 1C24
TGCR
Timer 2 Global Control Register
Timer 2 Watchdog Timer Control Register
Reserved
0x01C2 1C28
WDTCR
-
0x01C2 1C2C - 0x01C2 1FFF
6.22.2 Timer Electrical Data/Timing
Table 6-104. Timing Requirements for Timer Input(1)(2) (see Figure 6-74)
NO.
1
MIN
MAX
UNIT
ns
tc(TIN)
Cycle time, TIM_IN
4P
0.45C
0.45C
2
tw(TINPH)
tw(TINPL)
tt(TIN)
Pulse duration, TIM_IN high
Pulse duration, TIM_IN low
Transition time, TIM_IN
0.55C
0.55C
0.05C
ns
3
ns
4
ns
(1) P = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use P = 37.037 ns.
(2) C = TIM_IN cycle time in ns. For example, when TIM_IN frequency is 27 MHz, use C = 37.037 ns
1
2
3
4
4
TIM_IN
Figure 6-74. Timer Timing
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6.23 Pulse Width Modulator (PWM)
The 3 DM6446 Pulse Width Modulator (PWM) peripherals support the following features:
•
•
•
•
•
•
Period counter
First-phase duration counter
Repeat count for one-shot operation
Configurable to operate in either one-shot or continuous mode
Buffered period and first-phase duration registers
One-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or
high-to-low).
•
•
One-shot operation generates N+1 periods of waveform, N being the repeat count register value
Emulation support
The register memory maps for PWM0/1/2 are shown in Table 6-105, Table 6-106, and Table 6-107.
Table 6-105. PWM0 Register Memory Map
HEX ADDRESS RANGE
0x01C2 2000
ACRONYM
REGISTER NAME
Reserved
0x01C2 2004
PCR
CFG
START
RPT
PER
PH1D
-
PWM0 Peripheral Control Register
PWM0 Configuration Register
PWM0 Start Register
0x01C2 2008
0x01C2 200C
0x01C2 2010
PWM0 Repeat Count Register
PWM0 Period Register
0x01C2 2014
0x01C2 2018
PWM0 First-Phase Duration Register
Reserved
0x01C2 201C - 0x01C2 23FF
Table 6-106. PWM1 Register Memory Map
HEX ADDRESS RANGE
0x01C2 2400
ACRONYM
REGISTER NAME
Reserved
0x01C2 2404
PCR
CFG
START
RPT
PER
PH1D
-
PWM1 Peripheral Control Register
0x01C2 2408
PWM1 Configuration Register
PWM1 Start Register
0x01C2 240C
0x01C2 2410
PWM1 Repeat Count Register
PWM1 Period Register
PWM1 First-Phase Duration Register
Reserved
0x01C2 2414
0x01C2 2418
0x01C2 241C -0x01C2 27FF
Table 6-107. PWM2 Register Memory Map
HEX ADDRESS RANGE
0x01C2 2800
ACRONYM
REGISTER NAME
Reserved
0x01C2 2804
PCR
CFG
START
RPT
PER
PH1D
-
PWM2 Peripheral Control Register
PWM2 Configuration Register
PWM2 Start Register
0x01C2 2808
0x01C2 280C
0x01C2 2810
PWM2 Repeat Count Register
PWM2 Period Register
0x01C2 2814
0x01C2 2818
PWM2 First-Phase Duration Register
Reserved
0x01C2 281C - 0x01C2 2BFF
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6.23.1 PWM0/1/2 Electrical/Timing Data
Table 6-108. Switching Characteristics Over Recommended Operating Conditions for PWM0/1/2 Outputs
(see Figure 6-75 and Figure 6-76)
NO.
1
PARAMETER
Pulse duration, PWMx high
MIN
37
MAX
UNIT
ns
tw(PWMH)
tw(PWML)
2
Pulse duration, PWMx low
37
ns
3
tt(PWM)
Transition time, PWMx
5
ns
4
td(CCDC-PWMV)
Delay time, CCDC(VD) trigger event to PWMx valid
2
10
ns
1
2
PWM0/1/2
3
3
Figure 6-75. PWM Output Timing
VD(CCDC)
4
INVALID
VALID
PWM0
PWM1
4
INVALID
VALID
4
INVALID
VALID
PWM2
Figure 6-76. PWM Output Delay Timing
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6.24 VLYNQ
The DM6446 VLYNQ peripheral provides a high speed serial communications interface with the following
features.
•
•
•
Low Pin Count
Scalable Performance / Support
Simple Packet Based Transfer Protocol for Memory Mapped Access
–
–
–
–
Write Request / Data Packet
Read Request Packet
Read Response Data Packet
Interrupt Request Packet
•
Supports both Symmetric and Asymmetric Operation
–
–
–
Tx pins on first device connect to Rx pins on second device and vice versa
Data pin widths are automatically detected after reset
Request packets, response packets, and flow control information are all multiplexed and sent
across the same physical pins
–
Supports both Host/Peripheral and Peer to Peer communication
•
•
Simple Block Code Packet Formatting (8b/10b)
In Band Flow Control
–
–
–
No extra pins needed
Allows receiver to momentarily throttle back transmitter when overflow is about to occur
Uses built in special code capability of block code to seamlessly interleave flow control information
with user data
–
Allows system designer to balance cost of data buffering versus performance
•
•
•
Multiple outstanding transactions
Automatic packet formatting optimizations
Internal loop-back mode
6.24.1 VLYNQ Peripheral Register Description(s)
Table 6-109. VLYNQ Registers
HEX ADDRESS RANGE
0x01E0 1000
0x01E0 1004
0x01E0 1008
0x01E0 100C
0x01E0 1010
0x01E0 1014
0x01E0 1018
0x01E0 101C
0x01E0 1020
0x01E0 1024
0x01E0 1028
0x01E0 102C
0x01E0 1030
0x01E0 1034
0x01E0 1038
0x01E0 103C
0x01E0 1040
ACRONYM
REGISTER NAME
-
Reserved
CTRL
STAT
VLYNQ Local Control Register
VLYNQ Local Status Register
INTPRI
VLYNQ Local Interrupt Priority Vector Status/Clear Register
VLYNQ Local Unmasked Interrupt Status/Clear Register
VLYNQ Local Interrupt Pending/Set Register
INTSTATCLR
INTPENDSET
INTPTR
XAM
VLYNQ Local Interrupt Pointer Register
VLYNQ Local Transmit Address Map Register
VLYNQ Local Receive Address Map Size 1 Register
VLYNQ Local Receive Address Map Offset 1 Register
VLYNQ Local Receive Address Map Size 2 Register
VLYNQ Local Receive Address Map Offset 2 Register
VLYNQ Local Receive Address Map Size 3 Register
VLYNQ Local Receive Address Map Offset 3 Register
VLYNQ Local Receive Address Map Size 4 Register
VLYNQ Local Receive Address Map Offset 4 Register
VLYNQ Local Chip Version Register
RAMS1
RAMO1
RAMS2
RAMO2
RAMS3
RAMO3
RAMS4
RAMO4
CHIPVER
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Table 6-109. VLYNQ Registers (continued)
HEX ADDRESS RANGE
0x01E0 1044
ACRONYM
REGISTER NAME
AUTNGO
VLYNQ Local Auto Negotiation Register
0x01E0 1048
-
Reserved
0x01E0 104C
-
Reserved
0x01E0 1050 - 0x01E0 105C
0x01E0 1060
-
Reserved
-
Reserved
0x01E0 1064
-
Reserved
0x01E0 1068 - 0x01E0 107C
0x01E0 1080
-
Reserved for future use
RREVID
RCTRL
RSTAT
RINTPRI
VLYNQ Remote Revision Register
VLYNQ Remote Control Register
VLYNQ Remote Status Register
VLYNQ Remote Interrupt Priority Vector Status/Clear Register
0x01E0 1084
0x01E0 1088
0x01E0 108C
0x01E0 1090
RINTSTATCLR VLYNQ Remote Unmasked Interrupt Status/Clear Register
RINTPENDSET VLYNQ Remote Interrupt Pending/Set Register
0x01E0 1094
0x01E0 1098
RINTPTR
RXAM
VLYNQ Remote Interrupt Pointer Register
0x01E0 109C
VLYNQ Remote Transmit Address Map Register
0x01E0 10A0
RRAMS1
RRAMO1
RRAMS2
RRAMO2
RRAMS3
RRAMO3
RRAMS4
RRAMO4
VLYNQ Remote Receive Address Map Size 1 Register
VLYNQ Remote Receive Address Map Offset 1 Register
VLYNQ Remote Receive Address Map Size 2 Register
VLYNQ Remote Receive Address Map Offset 2 Register
VLYNQ Remote Receive Address Map Size 3 Register
VLYNQ Remote Receive Address Map Offset 3 Register
VLYNQ Remote Receive Address Map Size 4 Register
VLYNQ Remote Receive Address Map Offset 4 Register
0x01E0 10A4
0x01E0 10A8
0x01E0 10AC
0x01E0 10B0
0x01E0 10B4
0x01E0 10B8
0x01E0 10BC
VLYNQ Remote Chip Version Register (values on the device_id and
device_rev pins of remote VLYNQ)
0x01E0 10C0
RCHIPVER
0x01E0 10C4
0x01E0 10C8
RAUTNGO
RMANNGO
RNGOSTAT
-
VLYNQ Remote Auto Negotiation Register
VLYNQ Remote Manual Negotiation Register
VLYNQ Remote Negotiation Status Register
Reserved
0x01E0 10CC
0x01E0 10D0 - 0x01E0 10DC
VLYNQ Remote Interrupt Vectors 3 - 0 (sourced from vlynq_int_i[3:0] port of
remote VLYNQ)
0x01E0 10E0
0x01E0 10E4
RINTVEC0
RINTVEC1
VLYNQ Remote Interrupt Vectors 7 - 4 (sourced from vlynq_int_i[7:4] port of
remote VLYNQ)
0x01E0 10E8 - 0x01E0 10FC
0x01E0 1100 - 0x01E0 1FFF
-
-
Reserved for future use
Reserved
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6.24.2 VLYNQ Electrical Data/Timing
Table 6-110. Timing Requirements for VLYNQ_CLK for VLYNQ (see Figure 6-77)
NO.
MIN
MAX
UNIT
ns
1
tc(VCLK)
Cycle time, VLYNQ_CLK
10
3
Pulse duration, VLYNQ_CLK high [CLK External]
Pulse duration, VLYNQ_CLK high [CLK Internal]
Pulse duration, VLYNQ_CLK low [CLK External]
Pulse duration, VLYNQ_CLK low [CLK Internal]
Transition time, VLYNQ_CLK
ns
2
tw(VCLKH)
4
ns
3
ns
3
4
tw(VCLKL)
tt(VCLK)
4
ns
3
ns
1
4
2
VLYNQ_CLK
4
3
Figure 6-77. VLYNQ_CLK Timing for VLYNQ
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Table 6-111. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for
the VLYNQ Module (see Figure 6-78)
NO.
PARAMETER
MIN
MAX
UNIT
ns
Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] invalid [SLOW Mode]
Delay time, VLYNQ_CLK high to VLYNQ_ TXD[3:0] invalid [FAST Mode]
1
td(VCLKH-
TXDI)
1
0.5
ns
td(VCLKH-
TXDV)
2
Delay time, VLYNQ_CLK to VLYNQ_TXD[3:0] valid
9.75
ns
Table 6-112. Timing Requirements for Receive Data for the VLYNQ Module (see Figure 6-78)
NO.
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RTM disabled, RTM sample = 3
RTM enabled, RXD Flop = 0
RTM enabled, RXD Flop = 1
RTM enabled, RXD Flop = 2
RTM enabled, RXD Flop = 3
RTM enabled, RXD Flop = 4
RTM enabled, RXD Flop = 5
RTM enabled, RXD Flop = 6
RTM enabled, RXD Flop = 7
RTM disabled, RTM sample = 3
RTM enabled, RXD Flop = 0
RTM enabled, RXD Flop = 1
RTM enabled, RXD Flop = 2
RTM enabled, RXD Flop = 3
RTM enabled, RXD Flop = 4
RTM enabled, RXD Flop = 5
RTM enabled, RXD Flop = 6
RTM enabled, RXD Flop = 7
0.8
2.2
1.9
1.4
0.8
0.4
0.1
Setup time, VLYNQ_RXD[3:0] valid before
VLYNQ_CLK high
3
tsu(RXDV-VCLKH)
-0.2
-0.4
2
0.6
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Hold time, VLYNQ_RXD[3:0] valid after
VLYNQ_CLK high
4
th(VCLKH-RXDV)
1
VLYNQ_CLK
2
Data
VLYNQ_TXD[3:0]
VLYNQ_RXD[3:0]
4
3
Data
Figure 6-78. VLYNQ Transmit/Receive Timing
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6.25 IEEE 1149.1 JTAG
The JTAG(1) interface is used for BSDL testing and emulation of the DM6446 device.
The DM6446 device requires that both TRST and RESET be asserted upon power up to be properly
initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets
are required for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
For maximum reliability, DM6446 includes an internal pulldown (IPD) on the TRST pin to ensure that
TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
6.25.1 JTAG Peripheral Register Description(s) – JTAG ID Register
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Table 6-113. JTAG ID Register
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
0x01C4 0028
JTAGID
JTAG Identification Register
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
DM6446 device, the JTAG ID register resides at address location 0x01C4 0028. The register hex value for
DM6446 is: 0x0B70 002F for silicon revisions 1.3 and earlier, and 0x1B70 002F for silicon revision
2.1. For the actual register bit names and their associated bit field descriptions, see Figure 6-79 and
Table 6-114.
31-28
27-12
11-1
0
VARIANT
(4-Bit)(A)
PART NUMBER (16-Bit)
MANUFACTURER (11-Bit)
LSB
R-000x
R-1011 0111 0000 0000
R-0000 0010 111
R-1
LEGEND: R = Read, W = Write, n = value at reset
(A) For silicon revisions 1.3 and earlier, VARIANT = 0000. For silicon revision 2.1, VARIANT = 0001.
Figure 6-79. JTAG ID Register Description - DM6446 Register Value - 0xXB70 002F
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Table 6-114. JTAG ID Register Selection Bit Descriptions
BIT
NAME
VARIANT
DESCRIPTION
Variant (4-Bit) value. DM6446 value: 0000 for silicon revisions 1.3 and earlier, and 0001 for
silicon revision 2.1.
31:28
27:12
11-1
0
PART NUMBER
Part Number (16-Bit) value. DM6446 value: 1011 0111 0000 0000.
MANUFACTURER Manufacturer (11-Bit) value. DM6446 value: 0000 0010 111.
LSB LSB. This bit is read as a "1" for DM6446.
6.25.2 JTAG Test-Port Electrical Data/Timing
Table 6-115. Timing Requirements for JTAG Test Port (see Figure 6-80)
NO.
1
MIN
20
MAX
UNIT
ns
tc(TCK)
Cycle time, TCK
2
tw(TCKH)
Pulse duration, TCK high
8
8
ns
3
tw(TCKL)
Pulse duration, TCK low
ns
4
tc(RTCK)
Cycle time, RTCK
20
10
10
10
1
ns
5
tw(RTCKH)
tw(RTCKL)
tsu(TDIV-RTCKH)
th(RTCKH-TDIV)
Pulse duration, RTCK high
Pulse duration, RTCK low
Setup time, TDI/TMS valid before RTCK high
Hold time, TDI/TMS valid after RTCK high
ns
6
ns
7
ns
8
ns
Table 6-116. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 6-80)
NO.
PARAMETER
Delay time, RTCK low to TDO valid
MIN
MAX
15
UNIT
9
td(RTCKL-TDOV)
ns
1
2
3
TCK
4
5
6
RTCK
9
TDO
8
7
TDI/TMS
Figure 6-80. JTAG Test-Port Timing
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7 Mechanical Packaging and Orderable Information
The following table(s) show the thermal resistance characteristics for the PBGA–ZWT mechanical
package.
7.1 Thermal Data for ZWT
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZWT]
NO.
1
＝C/W(1)
AIR FLOW (m/s)(2)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
6.54
N/A
N/A
0.00
1.0
2
15.62
29.75
26.78
26.20
25.80
0.11
3
4
RΘJA
PsiJT
PsiJB
Junction-to-free air
Junction-to-package top
Junction-to-board
5
2.00
3.00
0.00
1.0
6
7
8
0.15
9
0.16
2.00
3.00
0.00
1.0
10
11
12
13
14
0.16
14.79
14.66
14.66
14.66
2.00
3.00
(1) These measurements were conducted in a JEDEC defined 1S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages.
(2) m/s = meters per second
7.1.1 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
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PACKAGE OPTION ADDENDUM
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30-Jun-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SM320DM6446AZWTA
ACTIVE
NFBGA
ZWT
361
90
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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