SM320F28335-EP_16 [TI]
Digital Signal Controller (DSC);
| 型号： | SM320F28335-EP_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Digital Signal Controller (DSC) |
| 文件： | 总169页 (文件大小：1805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM320F28335-EP
Digital Signal Controller (DSC)
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS581C
June 2009–Revised January 2010
SM320F28335-EP
SPRS581C–JUNE 2009–REVISED JANUARY 2010
www.ti.com
Contents
1
2
3
SM320F28335 DSC ............................................................................................................. 11
1.1
Features .................................................................................................................... 11
SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS ........................................ 12
1.2
Introduction ...................................................................................................................... 13
2.1
Pin Assignments ........................................................................................................... 14
Signal Descriptions ........................................................................................................ 23
2.2
Functional Overview .......................................................................................................... 33
3.1
Memory Maps .............................................................................................................. 34
Brief Descriptions .......................................................................................................... 38
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
C28x CPU ....................................................................................................... 38
Memory Bus (Harvard Bus Architecture) .................................................................... 38
Peripheral Bus .................................................................................................. 38
Real-Time JTAG and Analysis ................................................................................ 38
External Interface (XINTF) .................................................................................... 39
Flash ............................................................................................................. 39
M0, M1 SARAMs ............................................................................................... 39
L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 39
Boot ROM ....................................................................................................... 39
3.2.10 Security .......................................................................................................... 40
3.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 41
3.2.12 External Interrupts (XINT1-XINT7, XNMI) ................................................................... 41
3.2.13 Oscillator and PLL .............................................................................................. 42
3.2.14 Watchdog ........................................................................................................ 42
3.2.15 Peripheral Clocking ............................................................................................. 42
3.2.16 Low-Power Modes .............................................................................................. 42
3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 43
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 43
3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 43
3.2.20 Control Peripherals ............................................................................................. 44
3.2.21 Serial Port Peripherals ......................................................................................... 44
Register Map ............................................................................................................... 45
3.3
3.4
3.5
Device Emulation Registers .............................................................................................. 46
Interrupts .................................................................................................................... 47
3.5.1
External Interrupts .............................................................................................. 50
3.6
System Control ............................................................................................................ 51
3.6.1
OSC and PLL Block ............................................................................................ 53
3.6.1.1 External Reference Oscillator Clock Option .................................................... 54
3.6.1.2 PLL-Based Clock Module ......................................................................... 54
3.6.1.3 Loss of Input Clock ................................................................................ 56
Watchdog Block ................................................................................................. 56
3.6.2
3.7
Low-Power Modes Block ................................................................................................. 57
4
Peripherals ....................................................................................................................... 58
4.1
4.2
4.3
DMA Overview ............................................................................................................. 58
32-Bit CPU-Timers 0/1/2 ................................................................................................. 60
Enhanced PWM Modules (ePWM1/2/3/4/5/6) ......................................................................... 62
2
Contents
Copyright © 2009–2010, Texas Instruments Incorporated
SM320F28335-EP
www.ti.com
SPRS581C–JUNE 2009–REVISED JANUARY 2010
4.4
4.5
High-Resolution PWM (HRPWM) ....................................................................................... 65
Enhanced CAP Modules (eCAP1/2/3/4/5/6) ........................................................................... 67
4.6
4.7
Enhanced QEP Modules (eQEP1/2) .................................................................................... 70
Analog-to-Digital Converter (ADC) Module ............................................................................ 72
4.7.1
4.7.2
4.7.3
ADC Connections if the ADC Is Not Used .................................................................. 75
ADC Registers .................................................................................................. 75
ADC Calibration ................................................................................................. 76
4.8
4.9
Multichannel Buffered Serial Port (McBSP) Module .................................................................. 77
Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 80
4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) .......................................... 85
4.11 Serial Peripheral Interface (SPI) Module (SPI-A) ..................................................................... 88
4.12 Inter-Integrated Circuit (I2C) ............................................................................................. 91
4.13 GPIO MUX ................................................................................................................. 92
4.14 External Interface (XINTF) ............................................................................................... 99
5
6
Device Support ................................................................................................................ 101
Electrical Specifications ................................................................................................... 101
6.1
Absolute Maximum Ratings ............................................................................................. 101
Recommended Operating Conditions ................................................................................. 103
6.2
6.3
6.4
Electrical Characteristics ................................................................................................ 103
Current Consumption .................................................................................................... 104
6.4.1
6.4.2
6.4.3
Reducing Current Consumption ............................................................................. 105
Current Consumption Graphs ............................................................................... 106
Thermal Design Considerations ............................................................................. 107
6.5
6.6
Emulator Connection Without Signal Buffering for the DSP ....................................................... 107
Timing Parameter Symbology .......................................................................................... 109
6.6.1
6.6.2
6.6.3
General Notes on Timing Parameters ...................................................................... 109
Test Load Circuit .............................................................................................. 109
Device Clock Table ........................................................................................... 109
6.7
6.8
Clock Requirements and Characteristics ............................................................................. 111
Power Sequencing ....................................................................................................... 112
6.8.1
Power Management and Supervisory Circuit Solutions .................................................. 112
6.9
General-Purpose Input/Output (GPIO) ................................................................................ 115
6.9.1
6.9.2
6.9.3
6.9.4
GPIO - Output Timing ........................................................................................ 115
GPIO - Input Timing .......................................................................................... 116
Sampling Window Width for Input Signals ................................................................. 117
Low-Power Mode Wakeup Timing .......................................................................... 118
6.10 Enhanced Control Peripherals ......................................................................................... 122
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 122
6.10.2 Trip-Zone Input Timing ....................................................................................... 122
6.11 External Interrupt Timing ................................................................................................ 124
6.12 I2C Electrical Specification and Timing ............................................................................... 125
6.13 Serial Peripheral Interface (SPI) Timing .............................................................................. 125
6.13.1 Master Mode Timing .......................................................................................... 125
6.13.2 SPI Slave Mode Timing ...................................................................................... 129
6.14 External Interface (XINTF) Timing ..................................................................................... 132
6.14.1 USEREADY = 0 ............................................................................................... 132
6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) ............................................. 133
Copyright © 2009–2010, Texas Instruments Incorporated
Contents
3
SM320F28335-EP
SPRS581C–JUNE 2009–REVISED JANUARY 2010
www.ti.com
6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................ 133
6.14.4 XINTF Signal Alignment to XCLKOUT ..................................................................... 135
6.14.5 External Interface Read Timing ............................................................................. 136
6.14.6 External Interface Write Timing ............................................................................. 137
6.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................ 139
6.14.8 External Interface Ready-on-Write Timing With One External Wait State ............................. 142
6.14.9 XHOLD and XHOLDA Timing ............................................................................... 145
6.15 On-Chip Analog-to-Digital Converter .................................................................................. 148
6.15.1 ADC Power-Up Control Bit Timing .......................................................................... 149
6.15.2 Definitions ...................................................................................................... 150
6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................ 151
6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 152
6.15.5 Detailed Descriptions ......................................................................................... 153
6.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 154
6.16.1 McBSP Transmit and Receive Timing ...................................................................... 154
6.16.2 McBSP as SPI Master or Slave Timing .................................................................... 156
6.17 Flash Timing .............................................................................................................. 160
Thermal/Mechanical Data .................................................................................................. 162
7
4
Contents
Copyright © 2009–2010, Texas Instruments Incorporated
SM320F28335-EP
www.ti.com
SPRS581C–JUNE 2009–REVISED JANUARY 2010
List of Figures
2-1
176-Pin PGF/PTP LQFP (Top View) .......................................................................................... 15
179-Ball GHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View) .................................................. 16
179-Ball GHH MicroStar BGA™ (Upper Right Quadrant) (Bottom View)................................................. 17
179-Ball GHH MicroStar BGA™ (Lower Left Quadrant) (Bottom View) .................................................. 18
179-Ball GHH MicroStar BGA ™(Lower Right Quadrant) (Bottom View)................................................. 19
176-Ball GJZ Plastic BGA (Upper Left Quadrant) (Bottom View).......................................................... 20
176-Ball GJZ Plastic BGA (Upper Right Quadrant) (Bottom View)........................................................ 21
176-Ball GJZ Plastic BGA (Lower Left Quadrant) (Bottom View).......................................................... 22
176-Ball GJZ Plastic BGA (Lower Right Quadrant) (Bottom View)........................................................ 22
Functional Block Diagram ...................................................................................................... 33
Memory Map ...................................................................................................................... 35
External and PIE Interrupt Sources............................................................................................ 48
External Interrupts................................................................................................................ 48
Multiplexing of Interrupts Using the PIE Block ............................................................................... 49
Clock and Reset Domains ...................................................................................................... 52
OSC and PLL Block Diagram................................................................................................... 53
Using a 3.3-V External Oscillator............................................................................................... 54
Using a 1.9-V External Oscillator............................................................................................... 54
Using the Internal Oscillator .................................................................................................... 54
Watchdog Module ................................................................................................................ 56
DMA Functional Block Diagram ................................................................................................ 59
CPU-Timers ....................................................................................................................... 60
CPU-Timer Interrupt Signals and Output Signal ............................................................................. 60
Multiple PWM Modules .......................................................................................................... 62
ePWM Submodules Showing Critical Internal Signal Interconnections ................................................... 65
eCAP Functional Block Diagram ............................................................................................... 69
eQEP Functional Block Diagram ............................................................................................... 70
Block Diagram of the ADC Module ............................................................................................ 73
ADC Pin Connections With Internal Reference .............................................................................. 74
ADC Pin Connections With External Reference ............................................................................. 75
McBSP Module .................................................................................................................. 78
eCAN Block Diagram and Interface Circuit ................................................................................... 81
eCAN-A Memory Map ........................................................................................................... 82
eCAN-B Memory Map ........................................................................................................... 83
Serial Communications Interface (SCI) Module Block Diagram............................................................ 87
SPI Module Block Diagram (Slave Mode) .................................................................................... 90
I2C Peripheral Module Interfaces .............................................................................................. 91
GPIO MUX Block Diagram...................................................................................................... 93
Qualification Using Sampling Window......................................................................................... 98
External Interface Block Diagram .............................................................................................. 99
Typical 16-bit Data Bus XINTF Connections................................................................................ 100
Typical 32-bit Data Bus XINTF Connections................................................................................ 100
SM320F28335 Operating Life Derating Chart .............................................................................. 102
Typical Operational Current Versus Frequency ............................................................................ 107
Typical Operational Power Versus Frequency ............................................................................. 107
Emulator Connection Without Signal Buffering for the DSP .............................................................. 108
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
6-1
6-2
6-3
6-4
Copyright © 2009–2010, Texas Instruments Incorporated
List of Figures
5
SM320F28335-EP
SPRS581C–JUNE 2009–REVISED JANUARY 2010
www.ti.com
6-5
3.3-V Test Load Circuit......................................................................................................... 109
6-6
Clock Timing..................................................................................................................... 112
Power-on Reset................................................................................................................. 113
Warm Reset ..................................................................................................................... 114
Example of Effect of Writing Into PLLCR Register ......................................................................... 115
General-Purpose Output Timing .............................................................................................. 116
Sampling Mode ................................................................................................................. 116
General-Purpose Input Timing ................................................................................................ 117
IDLE Entry and Exit Timing.................................................................................................... 118
STANDBY Entry and Exit Timing Diagram .................................................................................. 119
HALT Wake-Up Using GPIOn................................................................................................. 121
PWM Hi-Z Characteristics ..................................................................................................... 122
ADCSOCAO or ADCSOCBO Timing ........................................................................................ 124
External Interrupt Timing....................................................................................................... 124
SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 127
SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 129
SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 131
SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 132
Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 135
Example Read Access ......................................................................................................... 137
Example Write Access ......................................................................................................... 138
Example Read With Synchronous XREADY Access ...................................................................... 140
Example Read With Asynchronous XREADY Access ..................................................................... 141
Write With Synchronous XREADY Access.................................................................................. 143
Write With Asynchronous XREADY Access ................................................................................ 144
External Interface Hold Waveform............................................................................................ 146
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 147
ADC Power-Up Control Bit Timing ........................................................................................... 149
ADC Analog Input Impedance Model ........................................................................................ 150
Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 151
Simultaneous Sampling Mode Timing ....................................................................................... 152
McBSP Receive Timing........................................................................................................ 156
McBSP Transmit Timing ....................................................................................................... 156
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 157
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 158
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 159
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 160
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6
List of Figures
Copyright © 2009–2010, Texas Instruments Incorporated
SM320F28335-EP
www.ti.com
SPRS581C–JUNE 2009–REVISED JANUARY 2010
List of Tables
2-1
Hardware Features .............................................................................................................. 13
Signal Descriptions............................................................................................................... 23
Addresses of Flash Sectors .................................................................................................... 36
Handling Security Code Locations ............................................................................................. 36
Wait-states ........................................................................................................................ 37
Boot Mode Selection............................................................................................................. 40
Peripheral Frame 0 Registers .................................................................................................. 45
Peripheral Frame 1 Registers .................................................................................................. 45
Peripheral Frame 2 Registers .................................................................................................. 46
Peripheral Frame 3 Registers .................................................................................................. 46
Device Emulation Registers..................................................................................................... 46
PIE Peripheral Interrupts ....................................................................................................... 49
PIE Configuration and Control Registers...................................................................................... 50
External Interrupt Registers..................................................................................................... 50
PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 53
PLLCR Bit Descriptions ......................................................................................................... 55
CLKIN Divide Options ........................................................................................................... 55
Possible PLL Configuration Modes ............................................................................................ 55
Low-Power Modes ............................................................................................................... 57
CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 61
ePWM Control and Status Registers (default configuration in PF1)....................................................... 63
ePWM Control and Status Registers (remapped configuration in PF3 - DMA accessible)............................. 64
eCAP Control and Status Registers ........................................................................................... 69
eQEP Control and Status Registers ........................................................................................... 71
ADC Registers ................................................................................................................... 75
McBSP Register Summary...................................................................................................... 79
3.3-V eCAN Transceivers ...................................................................................................... 81
CAN Register Map .............................................................................................................. 84
SCI-A Registers .................................................................................................................. 86
SCI-B Registers .................................................................................................................. 86
SCI-C Registers ................................................................................................................. 86
SPI-A Registers................................................................................................................... 89
I2C-A Registers................................................................................................................... 92
GPIO Registers .................................................................................................................. 94
GPIO-A Mux Peripheral Selection Matrix .................................................................................... 95
GPIO-B Mux Peripheral Selection Matrix .................................................................................... 96
GPIO-C Mux Peripheral Selection Matrix .................................................................................... 97
XINTF Configuration and Control Register Mapping....................................................................... 100
Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT ............................................... 104
Typical Current Consumption by Various Peripherals (at 150 MHz) .................................................... 105
Clocking and Nomenclature (150-MHz devices)............................................................................ 110
Clocking and Nomenclature (100-MHz devices)............................................................................ 110
Input Clock Frequency ......................................................................................................... 111
XCLKIN Timing Requirements - PLL Enabled ............................................................................. 111
XCLKIN Timing Requirements - PLL Disabled ............................................................................. 111
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 111
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
Copyright © 2009–2010, Texas Instruments Incorporated
List of Tables
7
SM320F28335-EP
SPRS581C–JUNE 2009–REVISED JANUARY 2010
www.ti.com
6-9
Power Management and Supervisory Circuit Solutions ................................................................... 112
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-47
6-48
6-49
6-50
6-51
6-52
6-53
6-54
6-55
6-56
Reset (XRS) Timing Requirements .......................................................................................... 114
General-Purpose Output Switching Characteristics........................................................................ 115
General-Purpose Input Timing Requirements .............................................................................. 116
IDLE Mode Timing Requirements ........................................................................................... 118
IDLE Mode Switching Characteristics ....................................................................................... 118
STANDBY Mode Timing Requirements ..................................................................................... 118
STANDBY Mode Switching Characteristics ................................................................................ 119
HALT Mode Timing Requirements ........................................................................................... 120
HALT Mode Switching Characteristics ...................................................................................... 120
ePWM Timing Requirements ................................................................................................. 122
ePWM Switching Characteristics ............................................................................................ 122
Trip-Zone input Timing Requirements ....................................................................................... 122
High Resolution PWM Characteristics at SYSCLKOUT = (60 - 150 MHz).............................................. 123
Enhanced Capture (eCAP) Timing Requirement .......................................................................... 123
eCAP Switching Characteristics ............................................................................................. 123
Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 123
eQEP Switching Characteristics ............................................................................................. 123
External ADC Start-of-Conversion Switching Characteristics............................................................. 123
External Interrupt Timing Requirements .................................................................................... 124
External Interrupt Switching Characteristics ................................................................................ 124
I2C Timing ...................................................................................................................... 125
SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 126
SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 128
SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 129
SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 131
Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 132
XINTF Clock Configurations................................................................................................... 135
External Interface Read Timing Requirements ............................................................................. 136
External Interface Read Switching Characteristics......................................................................... 136
External Interface Write Switching Characteristics ......................................................................... 137
External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)................................... 139
External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 139
Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 139
Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)....................................... 139
External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ................................... 142
Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 142
Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 142
XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 145
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 146
ADC Electrical Characteristics (over recommended operating conditions) ............................................ 148
ADC Power-Up Delays......................................................................................................... 149
Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .............................. 149
Sequential Sampling Mode Timing ........................................................................................... 151
Simultaneous Sampling Mode Timing ....................................................................................... 152
McBSP Timing Requirements ................................................................................................ 154
McBSP Switching Characteristics ........................................................................................... 154
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................ 156
8
List of Tables
Copyright © 2009–2010, Texas Instruments Incorporated
SM320F28335-EP
www.ti.com
SPRS581C–JUNE 2009–REVISED JANUARY 2010
6-57
6-58
6-59
6-60
6-61
6-62
6-63
6-64
6-65
6-66
6-67
6-68
7-1
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)............................ 156
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................ 157
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)............................ 157
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................ 158
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)............................ 158
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................ 159
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 159
Flash Endurance for A and S Temperature Material ...................................................................... 160
Flash Endurance for Q Temperature Material .............................................................................. 160
Flash Parameters at 150-MHz SYSCLKOUT ............................................................................... 160
Flash/OTP Access Timing ..................................................................................................... 160
Minimum Required Flash/OTP Wait-States at Different Frequencies ................................................... 161
Thermal Model 176-pin PGF Results ........................................................................................ 162
Thermal Model 179-pin GHH Results........................................................................................ 162
Thermal Model 176-pin GJZ Results ........................................................................................ 162
Thermal Model 176-pin PTP Results......................................................................................... 163
7-2
7-3
7-4
Copyright © 2009–2010, Texas Instruments Incorporated
List of Tables
9
SM320F28335-EP
SPRS581C–JUNE 2009–REVISED JANUARY 2010
www.ti.com
10
List of Tables
Copyright © 2009–2010, Texas Instruments Incorporated
SM320F28335-EP
www.ti.com
SPRS581C–JUNE 2009–REVISED JANUARY 2010
Digital Signal Controller (DSC)
Check for Samples: SM320F28335-EP
1
SM320F28335 DSC
• Three 32-Bit CPU Timers
• Serial Port Peripherals
– Up to 2 CAN Modules
1.1 Features
12
• High-Performance Static CMOS Technology
– Up to 150 MHz (6.67-ns Cycle Time)
– 1.9-V/1.8-V Core, 3.3-V I/O Design
• High-Performance 32-Bit CPU
– Up to 3 SCI (UART) Modules
– Up to 2 McBSP Modules (Configurable as
SPI)
– IEEE-754 Single-Precision Floating-Point
Unit (FPU) )
– 16 x 16 and 32 x 32 MAC Operations
– 16 x 16 Dual MAC
– One SPI Module
– One Inter-Integrated-Circuit (I2C) Bus
• 12-Bit ADC, 16 Channels
– 80-ns Conversion Rate
– 2 x 8 Channel Input Multiplexer
– Two Sample-and-Hold
– Single/Simultaneous Conversions
– Internal or External Reference
– Harvard Bus Architecture
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– Code-Efficient (in C/C++ and Assembly)
• Six Channel DMA Controller (for ADC, McBSP,
ePWM, XINTF, and SARAM)
• 16-bit or 32-bit External Interface (XINTF)
– Over 2M x 16 Address Reach
• On-Chip Memory
– 256K x 16 Flash, 34K x 16 SARAM
– 1K x 16 OTP ROM
• Boot ROM (8K x 16)
– With Software Boot Modes (via SCI, SPI,
CAN, I2C, McBSP, XINTF, and Parallel I/O)
– Standard Math Tables
• Clock and System Control
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Watchdog Timer Module
• GPIO0 to GPIO63 Pins Can Be Connected to
One of the Eight External Core Interrupts
• Peripheral Interrupt Expansion (PIE) Block That
Supports All 58 Peripheral Interrupts
• 128-Bit Security Key/Lock
– Protects Flash/OTP/RAM Blocks
– Prevents Firmware Reverse Engineering
• Enhanced Control Peripherals
– Up to 18 PWM Outputs
• Up to 88 Individually Programmable,
Multiplexed GPIO Pins With Input Filtering
• JTAG Boundary Scan Support
(1)
• Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware
• Development Support Includes
– ANSI C/C++ Compiler/Assembler/Linker
– Code Composer Studio™ IDE
– DSP/BIOS™
– Digital Motor Control and Digital Power
Software Libraries
• Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks
• Package Options
– Quad Flatpack With Power-Pad (PTP)
– Thin Quad Flatpack (PGF, Preview Only)
– MicroStar BGA™ (GHH)
– Plastic BGA (GJZ)
• Temperature Options:
– A: –40°C to 85°C (GHH) (PGF, GJZ, Preview
Only)
– S: –40°C to 125°C (GJZ, Preview Only)
– Q: –40°C to 125°C (GJZ, Preview Only)
– M: –55°C to 125°C (PTP, GJZ)
– Up to 6 HRPWM Outputs With 150 ps MEP
Resolution
– Up to 6 Event Capture Inputs
– Up to 2 Quadrature Encoder Interfaces
– Up to 8 32-bit/Nine 16-bit Timers
(1) IEEE Standard 1149.1-1990 Standard Test Access Port and
Boundary Scan Architecture
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
MicroStar BGA, Code Composer Studio, DSP/BIOS are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
SM320F28335-EP
SPRS581C–JUNE 2009–REVISED JANUARY 2010
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1.2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C) Temperature Range(2)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
(2) Additional temperature ranges are available - contact factory
12
SM320F28335 DSC
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2
Introduction
The SM320F28335 is a highly integrated, high-performance solution for demanding control applications.
Throughout this document, the device is abbreviated as F28335. Table 2-1 provides a summary of
features.
Table 2-1. Hardware Features
FEATURE
TYPE(1)
F28335 (150 MHz)
Instruction cycle
Floating-point Unit
–
–
–
–
6.67 ns
Yes
3.3-V on-chip flash (16-bit word)
256K
34K
Single-access RAM (SARAM) (16-bit word)
One-time programmable (OTP) ROM
(16-bit word)
–
1K
Code security for on-chip flash/SARAM/OTP blocks
Boot ROM (8K X16)
–
–
1
0
0
0
0
0
–
Yes
Yes
16/32-bit External Interface (XINTF)
6-channel Direct Memory Access (DMA)
PWM outputs
Yes
Yes
ePWM1/2/3/4/5/6
HRPWM channels
ePWM1A/2A/3A/4A/5A/6A
32-bit Capture inputs or auxiliary PWM outputs
32-bit QEP channels (four inputs/channel)
Watchdog timer
6
2
Yes
No. of channels
16
12-Bit ADC
MSPS
2
12.5
Conversion time
80 ns
32-Bit CPU timers
–
1
0
0
0
0
–
–
–
–
–
–
–
–
–
3
Multichannel Buffered Serial Port (McBSP)/SPI
Serial Peripheral Interface (SPI)
Serial Communications Interface (SCI)
Enhanced Controller Area Network (eCAN)
Inter-Integrated Circuit (I2C)
2
1
3
2
1
General Purpose I/O pins (shared)
External interrupts
88
8
Yes
176-Pin PTP
Packaging
179-Ball GHH
Yes
176-Ball GJZ
Yes
A: –40°C to 85°C
S: –40°C to 125°C
Q: –40°C to 125°C
M: –55°C to 125°C
(PGF, GHH, GJZ)
(GJZ)
Temperature options
(GJZ)
(PTP, GJZ)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module.
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2.1 Pin Assignments
The 176-pin PZ low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-1. The 179-ball
GHH ball grid array (BGA) terminal assignments are shown in Figure 2-2 through Figure 2-5. The 176-ball
GJZ plastic ball grid array (PBGA) terminal assignments are shown in Figure 2-6 through
Figure 2-9.Table 2-2 describes the function(s) of each pin.
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
GPIO76/XD3
GPIO77/XD2
GPIO78/XD1
GPIO79/XD0
88 GPIO48/ECAP5/XD31
87 TCK
86 EMU1
85
84
83
EMU0
V
DD3VFL
GPIO38/XWE0
XCLKOUT
V
SS
V
V
82 TEST2
81 TEST1
80
79 TMS
78
DD
GPIO28/SCIRXDA/XZCS6
SS
XRS
GPIO28/SCIRXDA/XZCS6
GPIO34/ECAP1/XREADY
V
TRST
DDIO
V
77 TDO
76 TDI
SS
GPIO36/SCIRXDA/XZCS0
V
75 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
74 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
73 GPIO27/ECAP4/EQEP2S/MFSXB
72 GPIO26/ECAP3/EQEP2I/MCLKXB
DD
V
SS
GPIO35/SCITXDA/XR/W
XRD
GPIO37/ECAP2/XZCS7
GPIO40/XA0/XWE1
V
71
70
DDIO
V
SS
GPIO41/XA1
GPIO42/XA2
69 GPIO25/ECAP2/EQEP2B/MDRB
68 GPIO24/ECAP1/EQEP2A/MDXB
67 GPIO23/EQEP1I/MFSXA/SCIRXDB
66 GPIO22/EQEP1S/MCLKXA/SCITXDB
65 GPIO21/EQEP1B/MDRA/CANRXB
64 GPIO20/EQEP1A/MDXA/CANTXB
63 GPIO19/SPISTEA/SCIRXDB/CANTXA
62 GPIO18/SPICLKA/SCITXDB/CANRXA
V
V
V
DD
SS
GPIO43/XA3
GPIO44/XA4
GPIO45/XA5
V
DDIO
V
61
60
59
58
SS
GPIO46/XA6
GPIO47/XA7
DD
V
V
V
SS
DD2A18
SS2AGND
GPIO80/XA8 163
164
165
166
167
168
169
170
171
GPIO81/XA9
GPIO82/XA10
57 ADCRESEXT
56 ADCREFP
55 ADCREFM
54 ADCREFIN
53 ADCINB7
V
SS
V
DD
GPIO83/XA11
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
GPIO84/XA12
V
52
51
50
49
48
47
46
45
DDIO
V
SS
GPIO85/XA13 172
GPIO86/XA14
GPIO87/XA15
173
174
175
176
GPIO39/XA16
GPIO31/CANTXA/XA17
V
DDAIO
Figure 2-1. 176-Pin PGF/PTP LQFP (Top View)
14
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SPRS581C–JUNE 2009–REVISED JANUARY 2010
1
2
3
4
5
6
7
GPIO21/
EQEP1B/
MDRA/
VSSAIO
VSS
P
N
ADCINB0
ADCINB2
ADCINB6
ADCREFP
P
N
CANRXB
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
VDDAIO
VDD
ADCINA1
ADCINB1
ADCINB5
ADCREFM
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
VDD2A18
M
ADCINA2
ADCINA5
VSS1AGND
ADCLO
ADCINA4
VDDA2
ADCINA0
ADCINA3
VSSA2
ADCINB4
ADCINB3
ADCINA7
ADCRESEXT
ADCREFIN
ADCINB7
M
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
GPIO20/
EQEP1A/
MDXA/
L
L
CANTXB
GPIO19/
SPISTEA/
SCIRXDB/
CANTXA
VSS2AGND
K
K
6
7
GPIO17/
SPISOMIA/
CANRXB/
TZ6
VDD
VSS
VDD1A18
J
ADCINA6
GPIO16/
J
GPIO14/
TZ3/XHOLD/
SCITXDB/
MCLKXB
GPIO13/
TZ2/
GPIO15/
TZ4/XHOLDA/ SPISIMOA/
VDD
H
H
CANRXB/
MDRB
SCIRXDB/
MFSXB
CANTXB/
TZ5
1
2
3
4
5
Figure 2-2. 179-Ball GHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View)
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8
9
10
11
12
13
14
GPIO33/
SCLA/
GPIO48/
ECAP5/
XD31
GPIO50/
EQEP1A/
XD29
VSS
P
N
TMS
TEST2
EMU1
P
N
EPWMSYNCO/
ADCSOCBO
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO32/
SDAA/
GPIO49/
ECAP6/
XD30
VSS
VSS
VDDIO
TCK
EPWMSYNCI/
ADCSOCAO
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO51/
EQEP1B/
XD28
GPIO52/
EQEP1S/
XD27
VDD3VFL
VSS
M
TDI
M
TRST
GPIO27/
ECAP4/
EQEP2S/
MFSXB
GPIO53/
EQEP1I/
XD26
GPIO54/
SPISIMOA/
XD25
GPIO55/
SPISOMIA/
XD24
VDDIO
L
EMU0
L
XRS
TEST1
VSS
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
GPIO56/
SPICLKA/
XD23
GPIO58/
MCLKRA/
XD21
GPIO57/
SPISTEA/
XD22
VDD
K
TDO
K
8
9
VSS
J
X2
X1
XCLKIN
J
GPIO59/
MFSRA/
XD20
VSS
VDDIO
VDD
VSS
H
H
10
11
12
13
14
Figure 2-3. 179-Ball GHH MicroStar BGA™ (Upper Right Quadrant) (Bottom View)
16
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SPRS581C–JUNE 2009–REVISED JANUARY 2010
1
2
3
4
5
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
GPIO12/
TZ1/
GPIO10/
EPWM6A/
CANRXB/
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
VSS
G
F
G
CANTXB/
MDXB
ADCSOCBO
GPIO8/
EPWM5A/
CANTXB/
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
VDD
VSS
VDDIO
F
ADCSOCAO
6
7
GPIO6/
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO3/
EPWM2B/
ECAP5/
EPWM4A/
GPIO4/
GPIO84/
XA12
GPIO81/
XA9
VDDIO
E
D
E
EPWMSYNCI/
EPWMSYNCO
EPWM3A
MCLKRB
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO2/
GPIO86/
XA14
GPIO83/
XA11
GPIO45/
XA5
VSS
VSS
D
EPWM2A
GPIO29/
SCITXDA/
XA19
GPIO0/
GPIO85/
XA13
GPIO82/
XA10
GPIO80/
XA8
VSS
VSS
C
B
C
B
EPWM1A
GPIO30/
CANRXA/
XA18
GPIO39/
XA16
GPIO46/
XA6
GPIO43/
XA3
VDD
VSS
VDD
GPIO31/
CANTXA/
XA17
GPIO87/
XA15
GPIO47/
XA7
GPIO44/
XA4
VDDIO
VSS
A
A
1
2
3
4
5
6
7
Figure 2-4. 179-Ball GHH MicroStar BGA™ (Lower Left Quadrant) (Bottom View)
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10
11
12
13
14
GPIO63/
SCITXDC/
XD16
GPIO61/
MFSRB/
XD18
GPIO62/
SCIRXDC
XD17
GPIO60/
MCLKRB/
XD19
GPIO64/
XD15
G
G
GPIO69/
XD10
GPIO66/
XD13
GPIO65/
XD14
VSS
VDD
F
F
8
9
GPIO28/
SCIRXDA/
XZCS6
GPIO68/
XD11
GPIO67/
XD12
VSS
VDD
VDDIO
VSS
E
D
C
B
A
E
D
C
B
A
GPIO40/
XA0/
GPIO37/
ECAP2/
XZCS7
GPIO34/
ECAP1/
XREADY
GPIO38/
XWE0
GPIO70/
XD9
VDD
VSS
XWE1
GPIO36/
SCIRXDA/
XZCS0
GPIO73/
XD6
GPIO74/
XD5
GPIO71/
XD8
VDD
VSS
XCLKOUT
GPIO42/
XA2
GPIO78/
XD1
GPIO76/
XD3
GPIO72/
XD7
VDD
VDDIO
XRD
GPIO35/
GPIO41/
XA1
GPIO79/
XD0
GPIO77/
XD2
GPIO75/
XD4
VSS
VSS
SCITXDA/
XR/W
8
9
10
11
12
13
14
Figure 2-5. 179-Ball GHH MicroStar BGA ™(Lower Right Quadrant) (Bottom View)
18
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SPRS581C–JUNE 2009–REVISED JANUARY 2010
1
2
3
4
5
6
7
VSSA2
VSS2AGND
P
N
ADCINB0
ADCREFM
ADCREFP ADCRESEXT ADCREFIN
VSSAIO
ADCLO
ADCINB1
ADCINA0
ADCINB3
ADCINB5
ADCINB7
EMU0
M
ADCINA2
ADCINA5
ADCINA1
ADCINA4
ADCINB2
VSS1AGND
VDDA2
ADCINB4
ADCINB6
TEST1
TEST2
VDDAIO
VDD2A18
L
ADCINA3
VDD1A18
ADCINA7
GPIO15/
ADCINA6
GPIO16/
K
GPIO17/
SPISOMIA/
CANRXB/
TZ6
TZ4/XHOLDA/ SPISIMOA/
VDD
VSS
VSS
J
SCIRXDB/
MFSXB
CANTXB/
TZ5
GPIO12/
TZ1/
GPIO13/
TZ2/
GPIO14/
TZ3/XHOLD/
SCITXDB/
MCLKXB
VDD
VSS
VSS
H
CANTXB/
MDXB
CANRXB/
MDRB
Figure 2-6. 176-Ball GJZ Plastic BGA (Upper Left Quadrant) (Bottom View)
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8
9
10
11
12
13
14
GPIO20/
EQEP1A/
MDXA/
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
GPIO33/
SCLA/
VSS
VSS
EMU1
P
N
M
L
EPWMSYNCO/
ADCSOCBO
CANTXB
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
GPIO21/
EQEP1B/
MDRA/
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
VDDIO
TDI
TDO
XRS
CANRXB
GPIO19/
SPISTEA/
SCIRXDB/
CANTXA
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO32/
SDAA/
TMS
TCK
EPWMSYNCI/
ADSOCAO
GPIO50/
EQEP1A/
XD29
GPIO49/
ECAP6/
XD30
GPIO48/
ECAP5/
XD31
VDD
VDD3VFL
VDDIO
TRST
GPIO53
EQEP1I/
XD26
GPIO52/
EQEP1S/
XD27
GPIO51/
EQEP1B/
XD28
VDD
K
GPIO56/
SPICLKA/
XD23
GPIO55/
SPISOMIA/
XD24
GPIO54/
SPISIMOA/
XD25
VSS
VSS
VDD
J
GPIO59/
MFSRA/
XD20
GPIO58/
MCLKRA/
XD21
GPIO57/
SPISTEA/
XD22
VSS
VSS
X2
H
Figure 2-7. 176-Ball GJZ Plastic BGA (Upper Right Quadrant) (Bottom View)
20
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GPIO9/
EPWM5B/
SCITXDB/
ECAP3
GPIO10/
EPWM6A/
CANRXB/
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
VDDIO
VSS
VSS
G
ADCSOCBO
GPIO6/
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO8/
EPWM5A/
CANTXB/
EPWM4A/
VDD
VSS
VSS
F
EPWMSYNCI/
EPWMSYNCO
ADCSOCAO
GPIO3/
EPWM2B/
ECAP5/
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO4/
VDDIO
E
D
C
B
A
EPWM3A
MCLKRB
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO0/
GPIO2/
GPIO47/
XA7
VDD
VDD
VDDIO
EPWM1A
EPWM2A
GPIO29/
SCITXDA/
XA19
GPIO30/
CANRXA/
XA18
GPIO39/
XA16
GPIO85/
XA13
GPIO82/
XA10
GPIO46/
XA6
GPIO43/
XA3
GPIO31/
CANTXA/
XA17
GPIO87/
XA15
GPIO84/
XA12
GPIO81/
XA9
GPIO45/
XA5
GPIO42/
XA2
VDDIO
GPIO86/
XA14
GPIO83/
XA11
GPIO80/
XA8
GPIO44/
XA4
GPIO41/
XA1
VSS
VSS
1
2
3
4
5
6
7
Figure 2-8. 176-Ball GJZ Plastic BGA (Lower Left Quadrant) (Bottom View)
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GPIO60/
MCLKRB/
XD19
VSS
VSS
VDDIO
XCLKIN
X1
G
GPIO63/
SCITXDC/
XD16
GPIO62/
SCIRXDC/
XD17
GPIO61/
MFSRB/
XD18
VSS
VSS
VDD
F
GPIO66/
XD13
GPIO65/
XD14
GPIO64/
XD15
VDD
E
D
C
B
A
GPIO28/
SCIRXDA/
XZCS6
GPIO69/
XD10
GPIO68/
XD11
GPIO67/
XD12
VDD
VDD
VDDIO
GPIO36/
SCIRXDA/
XZCS0
GPIO40/
GPIO38/
XWE0
GPIO78/
XD1
GPIO75/
XD4
GPIO71/
XD8
GPIO70/
XD9
XA0/XWE1
GPIO37/
ECAP2/
XZCS7
GPIO35/
SCITXDA/
XR/W
GPIO79/
XD0
GPIO77/
XD2
GPIO74/
XD5
GPIO72
XD7
VSS
GPIO34/
ECAP1/
XREADY
GPIO76/
XD3
GPIO73/
XD6
VDDIO
VSS
XCLKOUT
XRD
8
9
10
11
12
13
14
Figure 2-9. 176-Ball GJZ Plastic BGA (Lower Right Quadrant) (Bottom View)
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SPRS581C–JUNE 2009–REVISED JANUARY 2010
2.2 Signal Descriptions
Table 2-2 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral
signals that are listed under them are alternate functions. Some peripheral functions may not be available
in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant. All pins capable of producing an
XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin is not configured
for XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unless otherwise
indicated). All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled
on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0-GPIO11 pins are not
enabled at reset. The pullups on GPIO12-GPIO34 are enabled upon reset.
Table 2-2. Signal Descriptions
PIN NO.
(1)
PGF/P
TP
PIN #
NAME
DESCRIPTION
GHH
BALL # BALL #
GJZ
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system
control of the operations of the device. If this signal is not connected or driven low, the
device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during
normal device operation. An external pulldown resistor is recommended on this pin. The
value of this resistor should be based on drive strength of the debugger pods applicable to
the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board be validated for proper
operation of the debugger and the application. (I, ↓)
TRST
78
M10
L11
TCK
TMS
87
79
N12
P10
M14
M12
JTAG test clock with internal pullup (I, ↑)
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK. (I, ↑)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK. (I, ↑)
TDI
76
77
M9
K9
N12
N13
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
TDO
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the
emulator system and is defined as input/output through the JTAG scan. This pin is also
used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state
and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the
device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor
should be based on the drive strength of the debugger pods applicable to the design. A
2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is
recommended that each target board be validated for proper operation of the debugger
and the application.
EMU0
85
L11
N7
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the
emulator system and is defined as input/output through the JTAG scan. This pin is also
used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state
and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the
device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor
should be based on the drive strength of the debugger pods applicable to the design. A
2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is
recommended that each target board be validated for proper operation of the debugger
and the application.
EMU1
86
P12
P8
FLASH
VDD3VFL
TEST1
TEST2
84
81
82
M11
K10
P11
L9
M7
L7
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
Copyright © 2009–2010, Texas Instruments Incorporated
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Introduction
23
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www.ti.com
Table 2-2. Signal Descriptions (continued)
PIN NO.
GHH
(1)
PGF/P
TP
PIN #
NAME
DESCRIPTION
GJZ
BALL # BALL #
CLOCK
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half
the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16
(XTIMCLK) and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF] to
1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during
a reset. (O/Z, 8 mA drive).
XCLKOUT
XCLKIN
138
105
C11
J14
A10
G13
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this
case, the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-V
oscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I)
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a
ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the
1.9-V core digital power supply. A 1.9-V external oscillator may be connected to the X1 pin.
In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator is
used with the XCLKIN pin, X1 must be tied to GND. (I)
X1
X2
104
102
J13
J11
G14
H14
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected
across X1 and X2. If X2 is not used it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the
address contained at the location 0x3FFFC0. When XRS is brought to a high level,
execution begins at the location pointed to by the PC. This pin is driven low by the DSC
when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
XRS
80
L10
M13
The output buffer of this pin is an open-drain with an internal pullup. It is recommended
that this pin be driven by an open-drain device.
ADC SIGNALS
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCLO
35
36
37
38
39
40
41
42
53
52
51
50
49
48
47
46
43
57
54
K4
J5
K1
K2
L1
ADC Group A, Channel 7 input (I)
ADC Group A, Channel 6 input (I)
ADC Group A, Channel 5 input (I)
ADC Group A, Channel 4 input (I)
ADC Group A, Channel 3 input (I)
ADC Group A, Channel 2 input (I)
ADC Group A, Channel 1 input (I)
ADC Group A, Channel 0 input (I)
ADC Group B, Channel 7 input (I)
ADC Group B, Channel 6 input (I)
ADC Group B, Channel 5 input (I)
ADC Group B, Channel 4 input (I)
ADC Group B, Channel 3 input (I)
ADC Group B, Channel 2 input (I)
ADC Group B, Channel 1 input (I)
ADC Group B, Channel 0 input (I)
Low Reference (connect to analog ground) (I)
ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
External reference input (I)
L1
L2
L2
L3
L3
M1
N1
M3
K5
P4
N4
M4
L4
M1
M2
M3
N6
M6
N5
M5
N4
M4
N3
P3
N2
P6
P7
P3
N3
P2
M2
M5
L5
ADCRESEXT
ADCREFIN
Internal Reference Positive Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass
capacitor of 2.2 mF to analog ground. (O)
ADCREFP
ADCREFM
56
55
P5
N5
P5
P4
Internal Reference Medium Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass
capacitor of 2.2 mF to analog ground. (O)
24
Introduction
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SPRS581C–JUNE 2009–REVISED JANUARY 2010
Table 2-2. Signal Descriptions (continued)
PIN NO.
GHH
(1)
PGF/P
TP
PIN #
NAME
DESCRIPTION
GJZ
BALL # BALL #
CPU AND I/O POWER PINS
ADC Analog Power Pin
VDDA2
VSSA2
VDDAIO
VSSAIO
VDD1A18
VSS1AGND
VDD2A18
VSS2AGND
VDD
34
33
K2
K3
K4
P1
L5
ADC Analog Ground Pin
ADC Analog I/O Power Pin
ADC Analog I/O Ground Pin
ADC Analog Power Pin
ADC Analog Ground Pin
ADC Analog Power Pin
ADC Analog Ground Pin
45
N2
44
P1
N1
K3
L4
31
J4
32
K1
59
M6
K6
L6
58
P2
D4
D5
D8
D9
E11
F4
4
B1
VDD
15
B5
VDD
23
B11
C8
VDD
29
VDD
61
D13
E9
VDD
101
109
117
126
139
146
154
167
9
VDD
F3
F11
H4
J4
CPU and Logic Digital Power Pins
VDD
F13
H1
VDD
VDD
H12
J2
J11
K11
L8
VDD
VDD
K14
N6
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
A4
A13
B1
71
B10
E7
93
D7
107
121
143
159
170
E12
F5
D11
E4
Digital I/O Power Pin
L8
G4
H11
N14
G11
L10
N14
Copyright © 2009–2010, Texas Instruments Incorporated
Introduction
25
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Table 2-2. Signal Descriptions (continued)
PIN NO.
GHH
(1)
PGF/P
TP
PIN #
NAME
DESCRIPTION
GJZ
BALL # BALL #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
A5
A10
A11
B4
A1
A2
A14
B14
F6
8
14
22
30
C3
60
C7
F7
70
C9
F8
83
D1
F9
Digital Ground Pins
92
D6
G6
G7
G8
G9
H6
H7
H8
H9
J6
103
106
108
118
120
125
140
144
147
155
160
166
171
D14
E8
E14
F4
F12
G1
H10
H13
J3
J7
J10
J12
M12
N10
N11
P6
J8
J9
P13
P14
Digital Ground Pins
P8
GPIOA AND PERIPHERAL SIGNALS
GPIO0
General purpose input/output 0 (I/O/Z)
EPWM1A
-
-
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
5
6
C1
D3
D2
E4
E2
E3
D1
D2
D3
E1
E2
E3
GPIO1
General purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
EPWM1B
ECAP6
MFSRB
GPIO2
EPWM2A
-
-
General purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
7
GPIO3
EPWM2B
ECAP5
General purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
10
11
12
MCLKRB
GPIO4
EPWM3A
-
-
General purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
GPIO5
General purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
EPWM3B
MFSRA
ECAP1
26
Introduction
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SPRS581C–JUNE 2009–REVISED JANUARY 2010
Table 2-2. Signal Descriptions (continued)
PIN NO.
GHH
(1)
PGF/P
TP
PIN #
NAME
DESCRIPTION
GJZ
BALL # BALL #
GPIO6
General purpose input/output 6 (I/O/Z)
EPWM4A
EPWMSYNCI
EPWMSYNCO
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
13
16
17
18
19
20
21
24
E1
F2
F1
G5
G4
G2
G3
H3
F1
F2
F3
G1
G2
G3
H1
H2
GPIO7
General purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
EPWM4B
MCLKRA
ECAP2
Enhanced capture input/output 2 (I/O)
GPIO8
General Purpose Input/Output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
EPWM5A
CANTXB
ADCSOCAO
ADC start-of-conversion A (O)
GPIO9
General purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
EPWM5B
SCITXDB
ECAP3
Enhanced capture input/output 3 (I/O)
GPIO10
General purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
EPWM6A
CANRXB
ADCSOCBO
ADC start-of-conversion B (O)
GPIO11
EPWM6B
SCIRXDB
ECAP4
General purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB
General purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB
General purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14
General purpose input/output 14 (I/O/Z)
Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external
interface (XINTF) to release the external bus and place all buses and strobes into a
high-impedance state. To prevent this from happening when TZ3 signal goes active,
disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus
will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are
ignored by default, unless they are enabled by the code. The XINTF will release the bus
when any current access is complete and there are no pending accesses on the XINTF. (I)
TZ3/XHOLD
25
H2
H3
SCITXDB
MCLKXB
SCI-B Transmit (I)
McBSP-B transmit clock (I/O)
GPIO15
General purpose input/output 15 (I/O/Z)
Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on
the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4
function is chosen. If the pin is configured as an output, then XHOLDA function is chosen.
XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF
buses and strobe signals will be in a high-impedance state. XHOLDA is released when the
XHOLD signal is released. External devices should only drive the external bus when
XHOLDA is active (low). (I/0)
TZ4/XHOLDA
26
27
H4
H5
J1
J2
SCIRXDB
MFSXB
SCI-B receive (I)
McBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5
General purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
Copyright © 2009–2010, Texas Instruments Incorporated
Introduction
27
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SM320F28335-EP
SPRS581C–JUNE 2009–REVISED JANUARY 2010
www.ti.com
Table 2-2. Signal Descriptions (continued)
PIN NO.
GHH
(1)
PGF/P
TP
PIN #
NAME
DESCRIPTION
GJZ
BALL # BALL #
GPIO17
General purpose input/output 17 (I/O/Z)
SPISOMIA
CANRXB
TZ6
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
28
62
63
64
65
66
67
68
69
72
73
J1
L6
J3
N8
GPIO18
General purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
SPICLKA
SCITXDB
CANRXA
Enhanced CAN-A receive (I)
GPIO19
General purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
SPISTEA
SCIRXDB
CANTXA
K7
L7
M8
Enhanced CAN-A transmit (O)
GPIO20
EQEP1A
MDXA
General purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
P9
CANTXB
GPIO21
EQEP1B
MDRA
General purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
P7
N7
M7
M8
N8
K8
L9
N9
CANRXB
GPIO22
General purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
EQEP1S
MCLKXA
SCITXDB
M9
GPIO23
EQEP1I
MFSXA
SCIRXDB
General purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
P10
N10
M10
P11
N11
GPIO24
ECAP1
EQEP2A
MDXB
General purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB
General purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB
General purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
GPIO27
ECAP4
EQEP2S
MFSXB
General purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6
General purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
141
2
E10
C2
B2
D10
C1
C2
B2
GPIO29
SCITXDA
XA19
General purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18
General purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
1
GPIO31
CANTXA
XA17
General purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
176
A2
28
Introduction
Copyright © 2009–2010, Texas Instruments Incorporated
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Product Folder Link(s): SM320F28335-EP
SM320F28335-EP
www.ti.com
SPRS581C–JUNE 2009–REVISED JANUARY 2010
Table 2-2. Signal Descriptions (continued)
PIN NO.
GHH
(1)
PGF/P
TP
PIN #
NAME
DESCRIPTION
GJZ
BALL # BALL #
GPIO32
General purpose input/output 32 (I/O/Z)
SDAA
EPWMSYNCI
ADCSOCAO
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
74
75
N9
P9
M11
P12
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
General-Purpose Input/Output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY
General-Purpose Input/Output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal
142
148
145
150
137
175
151
152
153
156
157
158
161
162
88
D10
A9
A9
B9
GPIO35
SCITXDA
XR/W
General-Purpose Input/Output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
GPIO36
SCIRXDA
XZCS0
General-Purpose Input/Output 36 (I/O/Z)
SCI receive data (I)
External Interface zone 0 chip select (O)
C10
D9
C9
B8
GPIO37
ECAP2
XZCS7
General-Purpose Input/Output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
GPIO38
-
XWE0
General-Purpose Input/Output 38 (I/O/Z)
-
External Interface Write Enable 0 (O)
D11
B3
C10
C3
C8
A7
GPIO39
-
XA16
General-Purpose Input/Output 39 (I/O/Z)
-
External Interface Address Line 16 (O)
GPIO40
-
XA0/XWE1
General-Purpose Input/Output 40 (I/O/Z)
-
External Interface Address Line 0/External Interface Write Enable 1 (O)
D8
GPIO41
-
XA1
General-Purpose Input/Output 41 (I/O/Z)
-
External Interface Address Line 1 (O)
A8
GPIO42
-
XA2
General-Purpose Input/Output 42 (I/O/Z)
-
External Interface Address Line 2 (O)
B8
B7
GPIO43
-
XA3
General-Purpose Input/Output 43 (I/O/Z)
-
External Interface Address Line 3 (O)
B7
C7
A6
GPIO44
-
XA4
General-Purpose Input/Output 44 (I/O/Z)
-
External Interface Address Line 4 (O)
A7
GPIO45
-
XA5
General-Purpose Input/Output 45 (I/O/Z)
-
External Interface Address Line 5 (O)
D7
B6
GPIO46
-
XA6
General-Purpose Input/Output 46 (I/O/Z)
-
External Interface Address Line 6 (O)
B6
C6
D6
L14
L13
GPIO47
-
XA7
General-Purpose Input/Output 47 (I/O/Z)
-
External Interface Address Line 7 (O)
A6
GPIO48
ECAP5
XD31
General-Purpose Input/Output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (O)
P13
N13
GPIO49
ECAP6
XD30
General-Purpose Input/Output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (O)
89
Copyright © 2009–2010, Texas Instruments Incorporated
Introduction
29
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Product Folder Link(s): SM320F28335-EP
SM320F28335-EP
SPRS581C–JUNE 2009–REVISED JANUARY 2010
www.ti.com
Table 2-2. Signal Descriptions (continued)
PIN NO.
GHH
(1)
PGF/P
TP
PIN #
NAME
DESCRIPTION
GJZ
BALL # BALL #
GPIO50
General-Purpose Input/Output 50 (I/O/Z)
EQEP1A
XD29
90
91
P14
M13
M14
L12
L13
L14
K11
K13
K12
H14
G14
G12
G13
G11
G10
F14
F11
E13
E11
L12
K14
K13
K12
J14
J13
J12
H13
H12
H11
G12
F14
F13
F12
E14
E13
E12
D14
D13
Enhanced QEP 1input A (I)
External Interface Data Line 29 (O)
GPIO51
EQEP1B
XD28
General-Purpose Input/Output 51 (I/O/Z)
Enhanced QEP 1input B (I)
External Interface Data Line 28 (O)
GPIO52
EQEP1S
XD27
General-Purpose Input/Output 52 (I/O/Z)
Enhanced QEP 1Strobe (I/O)
External Interface Data Line 27 (O)
94
GPIO53
EQEP1I
XD26
General-Purpose Input/Output 53 (I/O/Z)
Enhanced CAP1 lndex (I/O)
External Interface Data Line 26 (O)
95
GPIO54
SPISIMOA
XD25
General-Purpose Input/Output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (O)
96
GPIO55
SPISOMIA
XD24
General-Purpose Input/Output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (O)
97
GPIO56
SPICLKA
XD23
General-Purpose Input/Output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (O)
98
GPIO57
SPISTEA
XD22
General-Purpose Input/Output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (O)
99
GPIO58
MCLKRA
XD21
General-Purpose Input/Output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (O)
100
110
111
112
113
114
115
116
119
122
123
GPIO59
MFSRA
XD20
General-Purpose Input/Output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (O)
GPIO60
MCLKRB
XD19
General-Purpose Input/Output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (O)
GPIO61
MFSRB
XD18
General-Purpose Input/Output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (O)
GPIO62
SCIRXDC
XD17
General-Purpose Input/Output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (O)
GPIO63
SCITXDC
XD16
General-Purpose Input/Output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (O)
GPIO64
-
XD15
General-Purpose Input/Output 64 (I/O/Z)
-
External Interface Data Line 15 (O)
GPIO65
-
XD14
General-Purpose Input/Output 65 (I/O/Z)
-
External Interface Data Line 14 (O)
GPIO66
-
XD13
General-Purpose Input/Output 66 (I/O/Z)
-
External Interface Data Line 13 (O)
GPIO67
-
XD12
General-Purpose Input/Output 67 (I/O/Z)
-
External Interface Data Line 12 (O)
GPIO68
-
General-Purpose Input/Output 68 (I/O/Z)
-
XD11
External Interface Data Line 11 (O)
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Table 2-2. Signal Descriptions (continued)
PIN NO.
GHH
(1)
PGF/P
TP
PIN #
NAME
DESCRIPTION
GJZ
BALL # BALL #
GPIO69
-
XD10
General-Purpose Input/Output 69 (I/O/Z)
-
External Interface Data Line 10 (O)
124
127
128
129
130
131
132
133
134
135
136
163
164
165
168
169
172
173
174
F10
D12
C14
B14
C12
C13
A14
B13
A13
B12
A12
C6
D12
C14
C13
B13
A12
B12
C12
A11
B11
C11
B10
A5
GPIO70
-
XD9
General-Purpose Input/Output 70 (I/O/Z)
-
External Interface Data Line 9 (O)
GPIO71
-
XD8
General-Purpose Input/Output 71 (I/O/Z)
-
External Interface Data Line 8 (O)
GPIO72
-
XD7
General-Purpose Input/Output 72 (I/O/Z)
-
External Interface Data Line 7 (O)
GPIO73
-
XD6
General-Purpose Input/Output 73 (I/O/Z)
-
External Interface Data Line 6 (O)
GPIO74
-
XD5
General-Purpose Input/Output 74 (I/O/Z)
-
External Interface Data Line 5 (O)
GPIO75
-
XD4
General-Purpose Input/Output 75 (I/O/Z)
-
External Interface Data Line 4 (O)
GPIO76
-
XD3
General-Purpose Input/Output 76 (I/O/Z)
-
External Interface Data Line 3 (O)
GPIO77
-
XD2
General-Purpose Input/Output 77 (I/O/Z)
-
External Interface Data Line 2 (O)
GPIO78
-
XD1
General-Purpose Input/Output 78 (I/O/Z)
-
External Interface Data Line 1 (O)
GPIO79
-
XD0
General-Purpose Input/Output 79 (I/O/Z)
-
External Interface Data Line 0 (O)
GPIO80
-
XA8
General-Purpose Input/Output 80 (I/O/Z)
-
External Interface Address Line 8 (O)
GPIO81
-
XA9
General-Purpose Input/Output 81 (I/O/Z)
-
External Interface Address Line 9 (O)
E6
B5
GPIO82
-
XA10
General-Purpose Input/Output 82 (I/O/Z)
-
External Interface Address Line 10 (O)
C5
C5
GPIO83
-
XA11
General-Purpose Input/Output 83 (I/O/Z)
-
External Interface Address Line 11 (O)
D5
A4
GPIO84
-
XA12
General-Purpose Input/Output 84 (I/O/Z)
External Interface Address Line 12 (O)
E5
B4
GPIO85
-
XA13
General-Purpose Input/Output 85 (I/O/Z)
-
External Interface Address Line 13 (O)
C4
C4
GPIO86
-
XA14
General-Purpose Input/Output 86 (I/O/Z)
-
External Interface Address Line 14 (O)
D4
A3
GPIO87
-
General-Purpose Input/Output 87 (I/O/Z)
-
A3
B3
XA15
External Interface Address Line 15 (O)
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Table 2-2. Signal Descriptions (continued)
PIN NO.
GHH
(1)
PGF/P
TP
PIN #
NAME
DESCRIPTION
GJZ
BALL # BALL #
XRD
149
B9 A8
External Interface Read Enable
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3
Functional Overview
M0 SARAM 1Kx16
(0-Wait)
L0 SARAM 4K x 16
(0-Wait, Dual Map)
OTP 1K x 16
M1 SARAM 1Kx16
(0-Wait)
L1 SARAM 4K x 16
(0-Wait, Dual Map)
Flash
256K x 16
8 Sectors
L2 SARAM 4K x 16
(0-Wait, Dual Map)
Code
Security
Module
L3 SARAM 4K x 16
(0-Wait, Dual Map)
TEST2
L4 SARAM 4K x 16
(0-W Data, 1-W Prog)
Pump
TEST1
PSWD
L5 SARAM 4K x 16
(0-W Data, 1-W Prog)
Boot ROM
8K x 16
Flash
Wrapper
L6 SARAM 4K x 16
(0-W Data, 1-W Prog)
L7 SARAM 4K x 16
(0-W Data, 1-W Prog)
Memory Bus
XD31:0
FPU
TCK
XHOLDA
XHOLD
XREADY
XR/W
TDI
TMS
32-bit CPU
TDO
(150 MHZ @ 1.9 V)
(100 MHz @ 1.8 V)
GPIO
MUX
88 GPIOs
TRST
EMU0
EMU1
XZCS0
XZCS7
XZCS6
XWE0
XCLKIN
X1
CPU Timer 0
XA0/XWE1
XA19:1
OSC,
DMA
6 Ch
PLL,
LPM,
WD
CPU Timer 1
CPU Timer 2
X2
XRS
XCLKOUT
XRD
PIE
(Interrupts)
88 GPIOs
A7:0
8 External Interrupts
GPIO
MUX
XINTF
Memory Bus
12-Bit
ADC
2-S/H
B7:0
DMA Bus
REFIN
32-bit peripheral bus
(DMA accessible)
32-bit peripheral bus
16-bit peripheral bus
FIFO
(16 Levels)
FIFO
(16 Levels)
FIFO
(16 Levels)
EPWM-1/../6
CAN-A/B
(32-mbox)
EQEP-1/2
McBSP-A/B
ECAP-1/../6
SCI-A/B/C
SPI-A
I2C
HRPWM-1/../6
GPIO MUX
88 GPIOs
Secure zone
Figure 3-1. Functional Block Diagram
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3.1 Memory Maps
In Figure 3-2 the following applies:
•
•
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps
are restricted to data memory only. A user program cannot access these memory maps in program
space.
•
Protected means the order of "Write followed by Read" operations is preserved rather than the pipeline
order.
•
•
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Locations 0x38 0080 - 0x38 008F contain the ADC calibration routine. It is not programmable by the
user.
•
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for
this.
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Block
Start Address
On-Chip Memory
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
0x00 0040
0x00 0400
0x00 0800
M0 SARAM (1K x 16)
M1 SARAM (1K x 16)
Peripheral Frame 0
Reserved
PIE Vector - RAM
(256 x16)
(Enabled if
VMAP = 1,
ENPIE =1)
0x00 0D00
Reserved
0x00 0E00
0x00 2000
Peripheral Frame 0
0x00 4000
0x00 5000
XINTF Zone 0 (4K x 16,XZCS0)
(Protected) DMA Accessible
Reserved
0x00 5000
0x00 6000
0x00 7000
Peripheral Frame 3
(Protected) DMA Accessible
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
L0 SARAM (4K x16, Secure Zone Dual Mapped)
L1 SARAM (4K x 16, Secure Zone Dual Mapped)
L2 SARAM (4Kx16, Secure Zone, Dual Mapped)
L3 SARAM (4Kx16, Secure Zone, Dual Mapped)
L4 SARAM (4Kx16, DMA Accessible)
0x00 9000
0x00 A000
0x00 B000
0x00 C000
Reserved
0x00 D000
0x00 E000
0x00 F000
0x01 0000
L5 SARAM (4Kx16, DMA Accessible)
L6 SARAM (4Kx16, DMA Accessible)
L7 SARAM (4Kx16, DMA Accessible)
0x10 0000
0x20 0000
0x30 0000
Reserved
XINTF Zone 6 (1 M x 16, XZCS6)(DMA Accessible)
XINTF Zone 7 (1 M x 16, XZCS7)(DMA Accessible)
0x30 0000
0x33 FFF8
FLASH (256 K x 16, Secure Zone)
128-bit Password
0x34 0000
0x38 0080
Reserved
ADC Calibration Data
0x38 0090
Reserved
0x38 0400
0x38 0800
User OTP (1K x 16, Secure Zone)
Reserved
0x3F 8000
L0 SARAM (4K x 16, Secure Zone Dual Mapped)
L1 SARAM (4K x 16, Secure Zone Dual Mapped)
L2 SARAM (4K x 16, Secure Zone Dual Mapped)
L3 SARAM (4K x 16, Secure Zone Dual Mapped)
0x3F 9000
0x3F A000
0x3F B000
0x3F C000
Reserved
Reserved
0x3F E000
0x3F FFC0
Boot ROM (8K x 16)
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector- should be enabled at a time.
Figure 3-2. Memory Map
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Table 3-1. Addresses of Flash Sectors
ADDRESS RANGE
PROGRAM AND DATA SPACE
Sector H (32K x 16)
Sector G (32K x 16)
Sector F (32K x 16)
Sector E (32K x 16)
Sector D (32K x 16)
Sector C (32K x 16)
Sector B (32K x 16)
Sector A (32K x 16)
0x30 0000 - 0x30 7FFF
0x30 8000 - 0x30 FFFF
0x31 0000 - 0x31 7FFF
0x31 8000 - 0x31 FFFF
0x32 0000 - 0x32 7FFF
0x32 8000 - 0x32 FFFF
0x33 0000 - 0x33 7FFF
0x33 8000 - 0x33 FF7F
Program to 0x0000 when using the
Code Security Module
0x33 FF80 - 0x33 FFF5
0x33 FFF6 - 0x33 FFF7
0x33 FFF8 - 0x33 FFFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password
(128-Bit) (Do Not Program to all zeros)
NOTE
•
•
When the code-security passwords are programmed, all addresses between
0x33FF80 and 0x33FFF5 cannot be used as program code or data. These locations
must be programmed to 0x0000.
If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may
be used for code or data. Addresses 0x33FFF0 – 0x33FFF5 are reserved for data and
should not contain program code. .
Table 3-2 shows how to handle these memory locations.
Table 3-2. Handling Security Code Locations
ADDRESS
FLASH
Code security enabled
Code security disabled
Application code and data
Reserved for data only
0x33FF80 - 0x33FFEF
0x33FFF0 - 0x33FFF5
Fill with 0x0000
Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these
blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected so as to
make sure that operations occur as written (the penalty is extra cycles are added to align the operations).
This mode is programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 3-3.
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Table 3-3. Wait-states
Area
Wait-States (CPU)
0-wait
Wait-States (DMA)(1)
Comments
Fixed
M0 and M1 SARAMs
Peripheral Frame 0
0-wait (writes)
1-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait (reads)
Peripheral Frame 3
Peripheral Frame 1
0-wait (writes)
1-wait (reads)
Assumes no conflicts between CPU and DMA.
Cycles can be extended by peripheral generated ready.
Consecutive writes to the CAN will experience a 1-cycle
pipeline hit.
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
Fixed. Cycles cannot be extended by the peripheral.
L0 SARAM
L1 SARAM
L2 SARAM
L3 SARAM
L4 SARAM
L5 SARAM
L6 SARAM
L7 SARAM
XINTF
0-wait data and
program
Assumes no CPU conflicts
0-wait data (read)
0-wait data (write)
1-wait program (read)
1-wait program (write)
Programmable
0-wait data (write)
0-wait data (read)
Assumes no conflicts between CPU and DMA.
Programmable
Programmed via the XTIMING registers or extendable via
external XREADY signal to meet system timing requirements.
1-wait is minimum wait states allowed on external waveforms
for both reads and writes on XINTF.
0-wait minimum writes 0-wait minimum writes 0-wait minimum for writes assumes write buffer enabled and
with write buffer
enabled
with write buffer enabled not full.
Assumes no conflicts between CPU and DMA. When DMA and
CPU attempt simultaneous conflict, 1-cycle delay is added for
arbitration.
OTP
Programmable
1-wait minimum
Programmed via the Flash registers.
1-wait is minimum number of wait states allowed. 1-wait-state
operation is possible at a reduced CPU frequency.
FLASH
Programmable
Programmed via the Flash registers.
1-wait Paged min
0-wait minimum for paged access is not allowed
1-wait Random min
Random ≥ Paged
FLASH Password
Boot-ROM
16-wait fixed
1-wait
Wait states of password locations are fixed.
0-wait speed is not possible.
(1) The DMA has a base of 4 cycles/word.
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3.2 Brief Descriptions
3.2.1 C28x CPU
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The C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x
DSCs, but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient
C/C++ engine, enabling users to develop their system control software in a high-level language. It also
enables math algorithms to be developed using C/C++. The device is as efficient in DSP math tasks as it
is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the
need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable
the controller to handle higher numerical resolution problems efficiently. Add to this the fast interrupt
response with automatic context save of critical registers, resulting in a device that is capable of servicing
many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with
pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to
expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for
conditional discontinuities. Special store conditional operations further improve performance.
3.2.2 Memory Bus (Harvard Bus Architecture)
As with many DSC type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the memory
bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory
bus.)
Data Reads
Program
Reads
(Simultaneous program reads and fetches cannot occur on the memory
bus.)
Lowest:
Fetches
(Simultaneous program reads and fetches cannot occur on the memory
bus.)
3.2.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSC family of devices, the
F28335 adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16
address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus
are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version
supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports DMA access
and both 16- and 32-bit accesses (called peripheral frame 3).
3.2.4 Real-Time JTAG and Analysis
The F28335 implements the standard IEEE 1149.1 JTAG interface. Additionally, the device supports
real-time mode of operation whereby the contents of memory, peripheral and register locations can be
modified while the processor is running and executing code and servicing interrupts. The user can also
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single step through non-time critical code while enabling time-critical interrupts to be serviced without
interference. The device implements the real-time mode in hardware within the CPU. This is a feature
unique to the F28335, requiring no software monitor. Additionally, special analysis hardware is provided
that allows setting of hardware breakpoint or data/address watch-points and generate various
user-selectable break events when a match occurs.
3.2.5 External Interface (XINTF)
This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The
chip-select lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be
programmed with a different number of wait states, strobe signal setup and hold timing and each zone can
be programmed for extending wait states externally or not. The programmable wait-state, chip-select and
programmable strobe timing enables glueless interface to external memories and peripherals.
3.2.6 Flash
The F28335 contains 256K × 16 of embedded flash memory, segregated into eight 32K × 16 sectors and
a single 1K × 16 of OTP memory at address range 0x380400 – 0x3807FF. The user can individually
erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not
possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other
sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance.
The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or
store data information. Note that addresses 0x33FFF0 – 0x33FFF5 are reserved for data variables and
should not contain program code.
NOTE
The Flash and OTP wait-states can be configured by the application. This allows
applications running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
3.2.7 M0, M1 SARAMs
The F28335 contains these two blocks of single access memory, each 1K × 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute
code or for data variables. The partitioning is performed within the linker. The C28x device presents a
unified memory map to the programmer. This makes for easier programming in high-level languages.
3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
The F28335 contains an additional 32K × 16 of single-access RAM, divided into 8 blocks (L0-L7 with 4K
each). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is mapped
to both program and data space. L4, L5, L6, and L7 are DMA accessible.
3.2.9 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math related algorithms.
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Table 3-4. Boot Mode Selection
MODE
GPIO87/XA15
GPIO86/XA14
GPIO85/XA13
GPIO84/XA12
MODE(1)
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Jump to Flash
SCI-A boot
SPI-A boot
I2C-A boot
eCAN-A boot
McBSP-A boot
Jump to XINTF x16
Jump to XINTF x32
Jump to OTP
Parallel GPIO I/O boot
Parallel XINTF boot
Jump to SARAM
Branch to check boot mode
Branch to Flash, skip ADC calibration
Branch to SARAM, skip ADC
calibration
0
0
0
0
0
Branch to SCI, skip ADC calibration
(1) All four GPIO pins have an internal pullup.
NOTE
Modes 0, 1, and 2 in Table 3-4 are for TI debug only. Skipping the ADC calibration
function in an application will cause the ADC to operate outside of the stated
specifications
3.2.10 Security
The devices support high levels of security to protect the user firmware from being reverse engineered.
The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the
flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1/L2/L3 SARAM
blocks. The security feature prevents unauthorized users from examining the memory contents via the
JTAG port, executing code from external memory or trying to boot-load some undesirable software that
would export the secure memory contents. To enable access to the secure blocks, the user must write the
correct 128-bit KEY value, which matches the value stored in the password locations within the Flash.
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent
unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, L0,
L1, L2 or L3 memory while the emulator is connected will trip the ECSL and break the emulation
connection. To allow emulation of secure code, while maintaining the CSM protection against secure
memory reads, the user must write the correct value into the lower 64 bits of the KEY register, which
matches the value stored in the lower 64 bits of the password locations within the flash. Note that dummy
reads of all 128 bits of the password in the flash must still be performed. If the lower 64 bits of the
password locations are all ones (unprogrammed), then the KEY value does not need to match.
When initially debugging a device with the password locations in flash programmed (i.e., secured), the
emulator takes some time to take control of the CPU. During this time, the CPU will start running and may
execute an instruction that performs an access to a protected ECSL area. If this happens, the ECSL will
trip and cause the emulator connection to be cut. Two solutions to this problem exist:
1. The first is to use the Wait-In-Reset emulation mode, which will hold the device in reset until the
emulator takes control. The emulator must support this mode for this option.
2. The second option is to use the “Branch to check boot mode” boot option. This will sit in a loop and
continuously poll the boot mode select pins. The user can select this boot mode and then exit this
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mode once the emulator is connected by re-mapping the PC to another address or by changing the
boot mode selection pin to the desired boot mode.
NOTE
•
•
When the code-security passwords are programmed, all addresses between
0x33FF80 and 0x33FFF5 cannot be used as program code or data. These locations
must be programmed to 0x0000.
If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may
be used for code or data. Addresses 0x33FFF0 – 0x33FFF5 are reserved for data and
should not contain program code. .
The 128-bit password (at 0x33 FFF8 – 0x33 FFFF) must not be programmed to zeros.
Doing so would permanently lock the device.
disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS
DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED
MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS
INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND
CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE
WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER,
EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN
ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
3.2.11 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F28335, 58 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12
CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
3.2.12 External Interrupts (XINT1-XINT7, XNMI)
The devices support eight masked external interrupts (XINT1-XINT7, XNMI). XNMI can be connected to
the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or
both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). XINT1,
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XINT2, and XNMI also contain a 16-bit free running up counter, which is reset to zero when a valid
interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the
281x devices, there are no dedicated pins for the external interrupts. XINT1 XINT2, and XNMI interrupts
can accept inputs from GPIO0 – GPIO31 pins. XINT3 – XINT7 interrupts can accept inputs from GPIO32
– GPIO63 pins.
3.2.13 Oscillator and PLL
The device can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.14 Watchdog
The devices contain a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog
can be disabled if necessary.
3.2.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN)
and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be
decoupled from increasing CPU clock speeds.
3.2.16 Low-Power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and
only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake the
processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT:
Turns off the internal oscillator. This mode basically shuts down the device and
places it in the lowest possible power consumption mode. A reset or external signal
can wake the device from this mode.
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3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0: PIE:
Flash:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Waitstate Registers
XINTF:
DMA
External Interface Registers
DMA Registers
Timers:
CSM:
CPU-Timers 0, 1, 2 Registers
Code Security Module KEY Registers
ADC:
ADC Result Registers (dual-mapped)
PF1: eCAN:
GPIO:
eCAN Mailbox and Control Registers
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers (dual mapped)
Enhanced Capture Module and Registers
Enhanced Quadrature Encoder Pulse Module and Registers
System Control Registers
ePWM:
eCAP:
eQEP:
PF2: SYS:
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
ADC Status, Control, and Result Register
Inter-Integrated Circuit Module and Registers
External Interrupt Registers
SPI:
ADC:
I2C:
XINT
PF3: McBSP
ePWM:
Multichannel Buffered Serial Port Registers
Enhanced Pulse Width Modulator Module and Registers (dual mapped)
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
3.2.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for Real-Time OS (RTOS)/BIOS applications. It is connected to INT14 of the CPU. If DSP/BIOS
is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be
connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.
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3.2.20 Control Peripherals
The F28335 supports the following peripherals which are used for embedded control and communication:
ePWM:
The enhanced PWM peripheral supports independent/complementary PWM
generation, adjustable dead-band generation for leading/trailing edges,
latched/cycle-by-cycle trip mechanism. Some of the PWM pins support HRPWM
features. The ePWM registers are supported by the DMA to reduce the overhead
for servicing this peripheral.
eCAP:
eQEP:
The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit
timer.
This peripheral has a watchdog timer to detect motor stall and input error detection
logic to identify simultaneous edge transition in QEP signals.
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling. The ADC registers are supported
by the DMA to reduce the overhead for servicing this peripheral.
3.2.21 Serial Port Peripherals
The devices support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
McBSP: The multichannel buffered serial port (McBSP) connects to E1/T1 lines,
phone-quality codecs for modem applications or high-quality stereo audio DAC
devices. The McBSP receive and transmit registers are supported by the DMA to
significantly reduce the overhead for servicing this peripheral. Each McBSP module
can be configured as an SPI as required.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications
between the DSC and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multi-device communications are
supported by the master/slave operation of the SPI. On the F28335, the SPI
contains a 16-level receive and transmit FIFO for reducing interrupt servicing
overhead.
SCI:
I2C:
The serial communications interface is a two-wire asynchronous serial port,
commonly known as UART. The SCI contains a 16-level receive and transmit FIFO
for reducing interrupt servicing overhead.
The inter-integrated circuit (I2C) module provides an interface between a DSC and
other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus)
specification version 2.1 and connected by way of an I2C-bus. External components
attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the
DSC through the I2C module. On the F28335, the I2C contains a 16-level receive
and transmit FIFO for reducing interrupt servicing overhead.
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3.3 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-5.
Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 3-6.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 3-7.
Peripheral Frame 3: These are peripherals that are mapped to the 32-bit DMA-accessible
peripheral bus. See Table 3-8.
Table 3-5. Peripheral Frame 0 Registers(1)
NAME
ADDRESS RANGE
0x00 0880 - 0x00 09FF
0x00 0A80 - 0x00 0ADF
0x00 0AE0 - 0x00 0AEF
0x00 0B00 - 0x00 0B0F
SIZE (×16)
ACCESS TYPE(2)
Device Emulation Registers
FLASH Registers(3)
Code Security Module Registers
384
96
EALLOW protected
EALLOW protected
EALLOW protected
Not EALLOW protected
16
ADC registers (dual-mapped)
16
0 wait (DMA), 1 wait (CPU), read only
XINTF Registers
CPU–TIMER0/1/2 Registers
PIE Registers
0x00 0B20 - 0x00 0B3F
0x00 0C00 - 0x00 0C3F
0x00 0CE0 - 0x00 0CFF
0x00 0D00 - 0x00 0DFF
0x00 1000 - 0x00 11FF
32
64
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
EALLOW protected
32
PIE Vector Table
DMA Registers
256
512
EALLOW protected
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-6. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
0x00 6000 - 0x00 61FF
0x00 6200 - 0x00 63FF
0x00 6800 - 0x00 683F
0x00 6840 - 0x00 687F
0x00 6880 - 0x00 68BF
0x00 68C0 - 0x00 68FF
0x00 6900 - 0x00 693F
0x00 6940 - 0x00 697F
0x00 6A00 - 0x00 6A1F
0x00 6A20 - 0x00 6A3F
0x00 6A40 - 0x00 6A5F
0x00 6A60 - 0x00 6A7F
0x00 6A80 - 0x00 6A9F
0x00 6AA0 - 0x00 6ABF
0x00 6B00 - 0x00 6B3F
0x00 6B40 - 0x00 6B7F
0x00 6F80 - 0x00 6FFF
SIZE (×16)
512
512
64
ECAN-A Registers
ECAN-B Registers
EPWM1 + HRPWM1 registers
EPWM2 + HRPWM2 registers
EPWM3 + HRPWM3 registers
EPWM4 + HRPWM4 registers
EPWM5 + HRPWM5 registers
EPWM6 + HRPWM6 registers
ECAP1 registers
64
64
64
64
64
32
ECAP2 registers
32
ECAP3 registers
32
ECAP4 registers
32
ECAP5 registers
32
ECAP6 registers
32
EQEP1 registers
64
EQEP2 registers
64
GPIO registers
128
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Table 3-7. Peripheral Frame 2 Registers
NAME
ADDRESS RANGE
0x00 7010 - 0x00 702F
0x00 7040 - 0x00 704F
0x00 7050 - 0x00 705F
0x00 7070 - 0x00 707F
0x00 7100 - 0x00 711F
0x00 7750 - 0x00 775F
0x00 7770 - 0x00 777F
0x00 7900 - 0x00 793F
SIZE (×16)
System Control Registers
SPI-A Registers
SCI-A Registers
External Interrupt Registers
ADC Registers
32
16
16
16
32
16
16
64
SCI-B Registers
SCI-C Registers
I2C-A Registers
Table 3-8. Peripheral Frame 3 Registers
NAME
ADDRESS RANGE
0x5000 – 0x503F
0x5040 - 0x507F
0x5800 – 0x583F
0x5840 - 0x587F
0x5880 - 0x58BF
0x58C0 - 0x58FF
0x5900 - 0x593F
0x5940 - 0x597F
SIZE (×16)
McBSP-A Registers (DMA)
McBSP-B Registers (DMA)
EPWM1 + HRPWM1 (DMA)(1)
EPWM2 + HRPWM2 (DMA)
EPWM3 + HRPWM3 (DMA)
EPWM4 + HRPWM4 (DMA)
EPWM5 + HRPWM5 (DMA)
EPWM6 + HRPWM6 (DMA)
64
64
64
64
64
64
64
64
(1) The ePWM/HRPWM modules can be re-mapped to Peripheral Frame 3 where they can be accessed by the DMA module. To achieve
this, bit 0 (MAPEPWM) of MAPCNF register (address 0x702E) must be set to 1. This register is EALLOW protected. When this bit is 0,
the ePWM/HRPWM modules are mapped to Peripheral Frame 1.
3.4 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 3-9.
Table 3-9. Device Emulation Registers
ADDRESS
RANGE
NAME
SIZE (x16)
DESCRIPTION
0x0880
0x0881
DEVICECNF
2
Device Configuration Register
PARTID
CLASSID
REVID
0x380090
0x0882
1
1
1
Part ID Register
0x00EF
0x00EF
0x0883
Revision ID
Register
0x0000 - Silicon Rev. 0 - TMX
0x0001 – Silicon Rev. A – TMS
PROTSTART
PROTRANGE
0x0884
0x0885
1
1
Block Protection Start Address Register
Block Protection Range Address Register
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3.5 Interrupts
Figure 3-3 shows how the various interrupt sources are multiplexed.
Peripherals
(SPI, SCI, I2C, CAN, McBSP(A),
EPWM(A), ECAP, EQEP, ADC(A))
Clear
DMA
WDINT
Watchdog
Low Power Models
WAKEINT
DMA
Sync
LPMINT
SYSCLKOUT
XINT1
XINT1
Latch
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
INT1
to
INT12
GPIOXINT1SEL(4:0)
XINT2SOC
C28
Core
XINT2
DMA
XINT2
ADC
Latch
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
GPIOXINT2SEL(4:0)
DMA
TINT0
CPU Timer 0
DMA
TINT2
CPU Timer 2
CPU Timer 1
INT14
INT13
TOUT1
TINT1
Flash Wrapper
GPIO0.int
XNMI_
XINT13
GPIO
Mux
Latch
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
NMI
GPIO31.int
1
GPIOXNMISEL(4:0)
DMA
A. DMA-accessible
Figure 3-3. External and PIE Interrupt Sources
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DMA
XINT3
Interrupt Control
XINT3CR(15:0)
Latch
GPIOXINT3SEL(4:0)
DMA
XINT4
Interrupt Control
XINT4CR(15:0)
Latch
GPIOXINT4SEL(4:0)
DMA
XINT5
INT1
to
INT12
PIE
Latch
Interrupt Control
XINT5CR(15:0)
C28
Core
GPIOXINT5SEL(4:0)
DMA
XINT6
Interrupt Control
XINT6CR(15:0)
Latch
GPIOXINT6SEL(4:0)
DMA
XINT7
GPIO32.int
GPIO63.int
GPIO
Mux
Interrupt Control
XINT7CR(15:0)
Latch
GPIOXINT7SEL(4:0)
Figure 3-4. External Interrupts
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the F28335, 58 of these are used by peripherals as
shown in Table 3-10.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.
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IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals or
External
INTx
MUX
INTx.6
INTx.7
INTx.8
Interrupts
PIEACKx
(Enable)
(Flag)
(Enable/Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
Figure 3-5. Multiplexing of Interrupts Using the PIE Block
Table 3-10. PIE Peripheral Interrupts(1)
PIE INTERRUPTS
CPU INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
SEQ2INT
(ADC)
SEQ1INT
(ADC)
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
XINT2
XINT1
Reserved
EPWM6_TZINT
(ePWM6)
EPWM5_TZINT
(ePWM5)
EPWM4_TZINT
(ePWM4)
EPWM3_TZINT
(ePWM3)
EPWM2_TZINT
(ePWM2)
EPWM1_TZINT
(ePWM1)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EPWM6_INT
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
ECAP6_INT
(ECAP6)
ECAP5_INT
(ECAP5)
ECAP4_INT
(eCAP4)
ECAP3_INT
(eCAP3)
ECAP2_INT
(eCAP2)
ECAP1_INT
(eCAP1)
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
Reserved
Reserved
Reserved
Reserved
MXINTA
(McBSP-A)
MRINTA
(McBSP-A)
MXINTB
(McBSP-B)
MRINTB
(McBSP-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
DINTCH6
(DMA)
DINTCH5
(DMA)
DINTCH4
(DMA)
DINTCH3
(DMA)
DINTCH2
(DMA)
DINTCH1
(DMA)
SCITXINTC
(SCI-C)
SCIRXINTC
(SCI-C)
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
Reserved
Reserved
ECAN1_INTB
(CAN-B)
ECAN0_INTB
(CAN-B)
ECAN1_INTA
(CAN-A)
ECAN0_INTA
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT10
INT11
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LUF
(FPU)
LVF
(FPU)
INT12
Reserved
XINT7
XINT6
XINT5
XINT4
XINT3
(1) Out of the 96 possible interrupts, 58 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
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Table 3-11. PIE Configuration and Control Registers
NAME
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
ADDRESS
0x0CE0
0x0CE1
0x0CE2
0x0CE3
0x0CE4
0x0CE5
0x0CE6
0x0CE7
0x0CE8
0x0CE9
0x0CEA
0x0CEB
0x0CEC
0x0CED
0x0CEE
0x0CEF
0x0CF0
0x0CF1
0x0CF2
0x0CF3
0x0CF4
0x0CF5
0x0CF6
0x0CF7
0x0CF8
0x0CF9
SIZE (X16)
DESCRIPTION(1)
PIE, Control Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
0x0CFA
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.
3.5.1 External Interrupts
Table 3-12. External Interrupt Registers
Name
Address
0x00 7070
0x00 7071
0x00 7072
0x00 7073
0x00 7074
0x00 7075
0x00 7076
0x00 7077
0x00 7078
0x00 7079
0x707A - 0x707E
Size (x16) Description
XINT1CR
XINT2CR
XINT3CR
XINT4CR
XINT5CR
XINT6CR
XINT7CR
XNMICR
XINT1CTR
XINT2CTR
Reserved
1
1
1
1
1
1
1
1
1
1
5
XINT1 configuration register
XINT2 configuration register
XINT3 configuration register
XINT4 configuration register
XINT5 configuration register
XINT6 configuration register
XINT7 configuration register
XNMI configuration register
XINT1 counter register
XINT2 counter register
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Table 3-12. External Interrupt Registers (continued)
Name
Address
Size (x16) Description
XNMI counter register
XNMICTR
0x00 707F
1
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge.
3.6 System Control
This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. Figure 3-6 shows the various clock and reset domains that will be discussed.
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C28x Core
SYSCLKOUT
CLKIN
System
Control
Register
Clock Enables
LSPCLK
LOSPCP
Bridge
I/O
Peripheral
Registers
SPI-A, SCI-A/B/C
Clock Enables
I2C-A
Clock Enables
/2
Bridge
Bridge
Bridge
I/O
I/O
I/O
Peripheral
Registers
eCAN-A/B
GPIO
Mux
Clock Enables
Peripheral
Registers
EPWM1/../6, HRPWM1/../6,
ECAP1/../6, EQEP1/2
Clock Enables
LSPCLK
LOSPCP
Peripheral
Registers
McBSP-A/B
Clock Enables
HSPCLK
HISPCP
16 Channels
ADC
Registers
12-Bit ADC
Result
Registers
DMA
Clock Enables
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT). See Figure 3-7 for an illustration of how CLKIN is derived.
Figure 3-6. Clock and Reset Domains
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to PCLKCR0/1/2 registers
(enables peripheral clocks) occurs to when the action is valid. This delay must be taken
into account before attempting to access the peripheral configuration registers.
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-13.
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Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers
Name
Address
0x00 7011
Size (x16) Description
PLL Status Register
Reserved
PLLSTS
Reserved
HISPCP
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
Reserved
PCLKCR3
PLLCR
1
7
1
1
1
1
1
1
1
1
1
1
1
1
3
1
6
1
0x00 7012 - 0x00 7018
0x00 701A
High-Speed Peripheral Clock Pre-Scaler Register
Low-Speed Peripheral Clock Pre-Scaler Register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low Power Mode Control Register 0
Low Power Mode Control Register 1
Peripheral Clock Control Register 3
PLL Control Register
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
0x00 7021
SCSR
0x00 7022
System Control and Status Register
Watchdog Counter Register
Reserved
WDCNTR
Reserved
WDKEY
Reserved
WDCR
0x00 7023
0x00 7024
0x00 7025
Watchdog Reset Key Register
Reserved
0x00 7026 - 0x00 7028
0x00 7029
Watchdog Control Register
Reserved
MAPCNF
0x00 702A - 0x00 702D
0x00 702E
Reserved
ePWM/HRPWM Re-map Register
3.6.1 OSC and PLL Block
Figure 3-7 shows the OSC and PLL block.
OSCCLK
OSCCLK
/1
XCLKIN
(3.3-V clock input
from external
oscillator)
0
n
OSCCLK or
VCOCLK
CLKIN
/2
/4
To
CPU
PLLSTS[OSCOFF]
PLLSTS[PLLOFF]
VCOCLK
PLL
n ≠ 0
PLLSTS[DIVSEL]
4-bit Multiplier PLLCR[DIV]
X1
External
Crystal or
Resonator
On-chip
oscillator
X2
Figure 3-7. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the F28335 using the X1 and X2
pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following
configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO
.
2. A 1.9-V (1.8-V for 100 MHz devices) external oscillator can be directly connected to the X1 pin. The X2
pin should be left unconnected and the XCLKIN pin tied low. The logic-high level in this case should
not exceed VDD
.
The three possible input-clock configurations are shown in Figure 3-8 through Figure 3-10.
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XCLKIN
X1
X2
NC
External Clock Signal
(Toggling 0−V
)
DDIO
Figure 3-8. Using a 3.3-V External Oscillator
X2
X1
XCLKIN
External Clock Signal
NC
(Toggling 0−V
)
DD
Figure 3-9. Using a 1.9-V External Oscillator
XCLKIN
X1
X2
C
L2
C
L1
Crystal
Figure 3-10. Using the Internal Oscillator
3.6.1.1 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
•
•
•
•
•
Fundamental mode, parallel resonant
CL (load capacitance) = 12 pF
CL1 = CL2 = 24 pF
Cshunt = 6 pF
ESR range = 25 to 40 Ω
TI recommends that customers have the resonator/crystal vendor characterize the operation of their
device with the DSC chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
circuit. The vendor can also advise the customer regarding the proper tank component values that will
produce proper start up and stability over the entire operating range.
3.6.1.2 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
131072 OSCCLK cycles. The input clock and PLLCR[DIV] bits should be chosen in such a way that the
output frequency of the PLL (VCOCLK) does not exceed 300 MHz.
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Table 3-14. PLLCR(1) Bit Descriptions
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE(2) (3)
PLLSTS[DIVSEL] = 0 or 1
PLLSTS[DIVSEL] = 2
PLLSTS[DIVSEL] = 3
0000 (PLL bypass)
0001
OSCCLK/4 (Default)
(OSCCLK * 1)/4
(OSCCLK * 2)/4
(OSCCLK * 3)/4
(OSCCLK * 4)/4
(OSCCLK * 5)/4
(OSCCLK * 6)/4
(OSCCLK * 7)/4
(OSCCLK * 8)/4
(OSCCLK * 9)/4
(OSCCLK * 10)/4
Reserved
OSCCLK/2
(OSCCLK * 1)/2
(OSCCLK * 2)/2
(OSCCLK * 3)/2
(OSCCLK * 4)/2
(OSCCLK * 5)/2
(OSCCLK * 6)/2
(OSCCLK * 7)/2
(OSCCLK * 8)/2
(OSCCLK * 9)/2
(OSCCLK * 10)/2
Reserved
OSCCLK
–
0010
–
0011
–
0100
–
0101
–
0110
–
0111
–
1000
–
1001
–
–
1010
1011 - 1111
Reserved
(1) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /2.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic have no effect.
(3) This register is EALLOW protected.
Table 3-15. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
1
2
3
/4
/4
/2
/1(1)
(1) This mode can be used only when the PLL is bypassed or off.
The PLL-based clock module provides two modes of operation:
•
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
•
External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 3-16. Possible PLL Configuration Modes
CLKIN AND
SYSCLKOUT
PLL MODE
REMARKS
PLLSTS[DIVSEL]
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Off
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
PLL Enable
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0, 1
2
OSCCLK*n/4
OSCCLK*n/2
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3.6.1.3 Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have
been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog
reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops
decrementing (i.e., the watchdog counter does not change with the limp-mode clock). In addition to this,
the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could
be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the DSC will be held in reset, should the input clocks
ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSC,
should the capacitor ever get fully charged. An I/O pin may be used to discharge the
capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would
also help in detecting failure of the flash memory and the VDD3VFL rail.
3.6.2 Watchdog Block
The watchdog block on the F28335 is similar to the one used on the 240x and 281x devices. The
watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the
software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset
the watchdog counter. Figure 3-11 shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
WDCLK
8-Bit
Watchdog
Counter
CLR
Watchdog
Prescaler
/512
Clear Counter
Internal
Pullup
WDKEY(7:0)
WDRST
WDINT
Generate
Watchdog
55 + AA
Key Detector
Output Pulse
(512 OSCCLKs)
Good Key
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK[2:0])
1
0
1
(A)
WDRST
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-11. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
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In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the
LPM block so that it can wake the device from STANDBY (if enabled). See Section Section 3.7,
Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so
is the WATCHDOG.
3.7 Low-Power Modes Block
The low-power modes on the F28335 are similar to the 240x devices. Table 3-17 summarizes the various
modes.
Table 3-17. Low-Power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
XRS, Watchdog interrupt, any enabled
interrupt, XNMI
IDLE
00
On
On
On(2)
On
XRS, Watchdog interrupt, GPIO Port A
signal, debugger(3), XNMI
STANDBY
HALT
01
1X
Off
Off
Off
Off
(watchdog still running)
Off
XRS, GPIO Port A signal, XNMI,
debugger(3)
(oscillator and PLL turned off,
watchdog not functional)
(1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will
exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.
(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized
by the processor. The LPM block performs no tasks during this mode as
long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the
OSCCLK before waking the device. The number of OSCCLKs is specified in
the LPMCR0 register.
HALT Mode:
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the
device from HALT mode. The user selects the signal in the GPIOLPMSEL
register.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included).
They will be in whatever state the code left them in when the IDLE instruction was
executed.
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4
Peripherals
The integrated peripherals of the F28335 are described in the following subsections:
•
•
•
•
•
•
•
•
•
•
•
•
•
6-channel Direct Memory Access (DMA)
Three 32-bit CPU-Timers
Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)
Up to six enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, eCAP6)
Up to two enhanced QEP modules (eQEP1, eQEP2)
Enhanced analog-to-digital converter (ADC) module
Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)
Up to three serial communications interface modules (SCI-A, SCI-B, SCI-C)
One serial peripheral interface (SPI) module (SPI-A)
Inter-integrated circuit module (I2C)
Up to two multichannel buffered serial port (McBSP-A, McBSP-B) modules
Digital I/O and shared pin functions
External Interface (XINTF)
4.1 DMA Overview
Features:
•
•
6 Channels with independent PIE interrupts
Trigger Sources:
–
–
–
–
–
–
ePWM SOCA/SOCB
ADC Sequencer 1 and Sequencer 2
McBSP-A and McBSP-B transmit and receive logic
XINT1-7 and XINT13
CPU Timers
Software
•
Data Sources/Destinations:
–
–
–
–
–
L4-L7 16K × 16 SARAM
All XINTF zones
ADC Memory Bus mapped RESULT registers
McBSP-A and McBSP-B transmit and receive buffers
ePWM registers
•
•
Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit)
Throughput: 4 cycles/word (5 cycles/word for McBSP reads)
58
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CPU bus
INT7
ADC
CPU
PF0
I/F
External
interrupts
CPU
ADC
control
and
timers
PIE
ADC
RESULT
ADC
PF2
I/F
ADC
DMA
PF0
I/F
registers RESULT
registers
L4
L4
I/F
SARAM
(4Kx16)
CPU
L5
McBSP A
L5
I/F
Event
triggers
SARAM
(4Kx16)
DMA
6-ch
McBSP B
ePWM/
PF3
I/F
(A)
L6
HRPWM
registers
L6
I/F
SARAM
(4Kx16)
L7
L7
I/F
SARAM
(4Kx16)
DMA bus
A. The ePWM/HRPWM registers must be remapped to PF3 (through bit 0 of the MAPCNF register) before they can be
accessed by the DMA. The ePWM/HRPWM connection to DMA is not present in silicon revision 0.
Figure 4-1. DMA Functional Block Diagram
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4.2 32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the devices (CPU-TIMER0/1/2).
Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0 and CPU-Timer 1 can be used in user applications.
These timers are different from the timers that are present in the ePWM modules.
NOTE
NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
32-Bit Timer Period
TDDRH:TDDR
PRDH:PRD
16-Bit Prescale Counter
SYSCLKOUT
PSCH:PSC
TCR.4
32-Bit Counter
TIMH:TIM
(Timer Start Status)
Borrow
Borrow
TINT
Figure 4-2. CPU-Timers
The timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-3.
INT1
TINT0
PIE
CPU-TIMER 0
to
INT12
28x
CPU
TINT1
CPU-TIMER 1
INT13
INT14
XINT13
TINT2
CPU-TIMER 2
(Reserved for DSP/BIOS)
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4-3. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the
value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers.
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Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
0x0C00
0x0C01
0x0C02
0x0C03
0x0C04
0x0C05
0x0C06
0x0C07
0x0C08
0x0C09
0x0C0A
0x0C0B
0x0C0C
0x0C0D
0x0C0E
0x0C0F
0x0C10
0x0C11
0x0C12
0x0C13
0x0C14
0x0C15
0x0C16
0x0C17
SIZE (x16)
DESCRIPTION
TIMER0TIM
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
Reserved
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU-Timer 0, Counter Register
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
Reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
Reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
TIMER2TPR
TIMER2TPRH
CPU-Timer 2, Prescale Register
CPU-Timer 2, Prescale Register High
0x0C18
0x0C3F
Reserved
40
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4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6)
The F28335 contains up to six enhanced PWM Modules (ePWM). Figure 4-4 shows a block diagram of
multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM.
Table 4-2 shows the complete ePWM register set per module and Table 4-3 shows the remapped register
configuration.
EPWM1SYNCI
EPWM1SYNCI
EPWM1INT
EPWM1A
EPWM1SOC
ePWM1 module
EPWM1B
TZ1 to TZ6
to eCAP1
and ePWM4
module
EPWM1SYNCO
.
EPWM1SYNCO
(sync in)
EPWM2SYNCI
ePWM2 module
EPWM2SYNCO
EPWM2INT
EPWM2A
EPWM2B
TZ1 to TZ6
EPWM2SOC
PIE
GPIO
MUX
EPWMxSYNCI
ePWMx module
EPWMxINT
EPWMxA
EPWMxB
EPWMxSOC
TZ1 to TZ6
EPWMxSYNCO
ADCSOCxO(A)
Peripheral Bus
ADC
A. ADCSOCxO is sent to the DMA as well when the ePWM registers are remapped to PF3 (through bit 0 of the
MAPCNF register).
B. By default, ePWM/HRPWM registers are mapped to Peripheral Frame 1 (PF1). Table 4-2 shows this configuration. To
re-map the registers to Peripheral Frame 3 (PF3) to enable DMA access, bit 0 (MAPEPWM) of MAPCNF register
(address 0x702E) must be set to 1. Table 4-3 shows the remapped configuration.
Figure 4-4. Multiple PWM Modules
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NAME
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Table 4-2. ePWM Control and Status Registers (default configuration in PF1)
SIZE (x16) /
EPWM1
EPWM2
EPWM3
EPWM4
EPWM5
EPWM6
DESCRIPTION
#SHADOW
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
TBCTL
0x6800
0x6801
0x6802
0x6803
0x6804
0x6805
0x6807
0x6808
0x6809
0x680A
0x680B
0x680C
0x680D
0x680E
0x680F
0x6810
0x6811
0x6812
0x6814
0x6815
0x6816
0x6817
0x6818
0x6819
0x681A
0x681B
0x681C
0x681D
0x681E
0x6820
0x6840
0x6841
0x6842
0x6843
0x6844
0x6845
0x6847
0x6848
0x6849
0x684A
0x684B
0x684C
0x684D
0x684E
0x684F
0x6850
0x6851
0x6852
0x6854
0x6855
0x6856
0x6857
0x6858
0x6859
0x685A
0x685B
0x685C
0x685D
0x685E
0x6860
0x6880
0x6881
0x6882
0x6883
0x6884
0x6885
0x6887
0x6888
0x6889
0x688A
0x688B
0x688C
0x688D
0x688E
0x688F
0x6890
0x6891
0x6892
0x6894
0x6895
0x6896
0x6897
0x6898
0x6899
0x689A
0x689B
0x689C
0x689D
0x689E
0x68A0
0x68C0
0x68C1
0x68C2
0x68C3
0x68C4
0x68C5
0x68C7
0x68C8
0x68C9
0x68CA
0x68CB
0x68CC
0x68CD
0x68CE
0x68CF
0x68D0
0x68D1
0x68D2
0x68D4
0x68D5
0x68D6
0x68D7
0x68D8
0x68D9
0x68DA
0x68DB
0x68DC
0x68DD
0x68DE
0x68E0
0x6900
0x6901
0x6902
0x6903
0x6904
0x6905
0x6907
0x6908
0x6909
0x690A
0x690B
0x690C
0x690D
0x690E
0x690F
0x6910
0x6911
0x6912
0x6914
0x6915
0x6916
0x6917
0x6918
0x6919
0x691A
0x691B
0x691C
0x691D
0x691E
0x6920
0x6940
0x6941
0x6942
0x6943
0x6944
0x6945
0x6947
0x6948
0x6949
0x694A
0x694B
0x694C
0x694D
0x694E
0x694F
0x6950
0x6951
0x6952
0x6954
0x6955
0x6956
0x6957
0x6958
0x6959
0x695A
0x695B
0x695C
0x695D
0x695E
0x6960
Time Base Control Register
TBSTS
TBPHSHR
TBPHS
TBCTR
TBPRD
CMPCTL
CMPAHR
CMPA
Time Base Status Register
Time Base Phase HRPWM Register
Time Base Phase Register
Time Base Counter Register
Time Base Period Register Set
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
Counter Compare B Register Set
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay Count Register
Dead-Band Generator Falling Edge Delay Count Register
Trip Zone Select Register(1)
CMPB
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
DBCTL
DBRED
DBFED
TZSEL
TZCTL
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
TZEINT
TZFLG
Trip Zone Flag Register
Trip Zone Clear Register(1)
Trip Zone Force Register(1)
TZCLR
TZFRC
ETSEL
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
ETPS
ETFLG
ETCLR
ETFRC
PCCTL
HRCNFG
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.
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Table 4-3. ePWM Control and Status Registers (remapped configuration in PF3 - DMA accessible)
SIZE (x16) /
#SHADOW
NAME
TBCTL
EPWM1
EPWM2
EPWM3
EPWM4
EPWM5
EPWM6
DESCRIPTION
Time Base Control Register
0x5800
0x5801
0x5802
0x5803
0x5804
0x5805
0x5807
0x5808
0x5809
0x580A
0x580B
0x580C
0x580D
0x580E
0x580F
0x5810
0x5811
0x5812
0x5814
0x5815
0x5816
0x5817
0x5818
0x5819
0x581A
0x581B
0x581C
0x581D
0x581E
0x5820
0x5840
0x5841
0x5842
0x5843
0x5844
0x5845
0x5847
0x5848
0x5849
0x584A
0x584B
0x584C
0x584D
0x584E
0x584F
0x5850
0x5851
0x5852
0x5854
0x5855
0x5856
0x5857
0x5858
0x5859
0x585A
0x585B
0x585C
0x585D
0x585E
0x5860
0x5880
0x5881
0x5882
0x5883
0x5884
0x5885
0x5887
0x5888
0x5889
0x588A
0x588B
0x588C
0x588D
0x588E
0x588F
0x5890
0x5891
0x5892
0x5894
0x5895
0x5896
0x5897
0x5898
0x5899
0x589A
0x589B
0x589C
0x589D
0x589E
0x58A0
0x58C0
0x58C1
0x58C2
0x58C3
0x58C4
0x58C5
0x58C7
0x58C8
0x58C9
0x58CA
0x58CB
0x58CC
0x58CD
0x58CE
0x58CF
0x58D0
0x58D1
0x58D2
0x58D4
0x58D5
0x58D6
0x58D7
0x58D8
0x58D9
0x58DA
0x58DB
0x58DC
0x58DD
0x58DE
058E0
0x5900
0x5901
0x5902
0x5903
0x5904
0x5905
0x5907
0x5908
0x5909
0x590A
0x590B
0x590C
0x590D
0x590E
0x590F
0x5910
0x5911
0x5912
0x5914
0x5915
0x5916
0x5917
0x5918
0x5919
0x591A
0x591B
0x591C
0x591D
0x591E
0x5920
0x5940
0x5941
0x5942
0x5943
0x5944
0x5945
0x5947
0x5948
0x5949
0x594A
0x594B
0x594C
0x594D
0x594E
0x594F
0x5950
0x5951
0x5952
0x5954
0x5955
0x5956
0x5957
0x5958
0x5959
0x595A
0x595B
0x595C
0x595D
0x595E
0x5960
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
TBSTS
TBPHSHR
TBPHS
TBCTR
TBPRD
CMPCTL
CMPAHR
CMPA
Time Base Status Register
Time Base Phase HRPWM Register
Time Base Phase Register
Time Base Counter Register
Time Base Period Register Set
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
Counter Compare B Register Set
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
CMPB
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
DBCTL
DBRED
DBFED
TZSEL
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay Count Register
Dead-Band Generator Falling Edge Delay Count Register
Trip Zone Select Register(1)
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
TZCTL
TZEINT
TZFLG
Trip Zone Flag Register
Trip Zone Clear Register(1)
Trip Zone Force Register(1)
TZCLR
TZFRC
ETSEL
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
ETPS
ETFLG
ETCLR
ETFRC
PCCTL
HRCNFG
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.
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Time−base (TB)
Sync
in/out
select
Mux
CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
EPWMxSYNCO
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMxSYNCI
Counter
up/down
(16 bit)
TBCTL[SWFSYNC]
(software forced sync)
CTR=ZERO
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
Phase
control
Event
trigger
and
interrupt
(ET)
EPWMxINT
TBPHS active (24)
CTR = CMPA
CTR = CMPB
CTR_Dir
EPWMxSOCA
EPWMxSOCB
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
Action
qualifier
(AQ)
16
8
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMB
EPWMxAO
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
16
EPWMxBO
EPWMxTZINT
TZ1 to TZ6
CMPB active (16)
CMPB shadow (16)
CTR = ZERO
Figure 4-5. ePWM Submodules Showing Critical Internal Signal Interconnections
4.4 High-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived
digital PWM methods. The key points for the HRPWM module are:
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
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•
Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies greater than ~200 kHz when using a
CPU/System clock of 100 MHz.
•
•
•
This capability can be utilized in both duty cycle and phase-shift control methods.
Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase registers of the ePWM module.
HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA output). EPWMxB output has
conventional PWM capabilities.
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4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6)
The F28335 contains up to six enhanced capture (eCAP) modules. Figure 4-6 shows a functional block diagram of a module.
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CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Pre-scale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
control
Figure 4-6. eCAP Functional Block Diagram
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The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1/2/3/4/5/6ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power
operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, and ECAP6ENCLK are set to low,
indicating that the peripheral clock is off.
Table 4-4. eCAP Control and Status Registers
NAME
TSCTR
CTRPHS
CAP1
ECAP1
0x6A00
0x6A02
0x6A04
0x6A06
0x6A08
0x6A0A
ECAP2
0x6A20
0x6A22
0x6A24
0x6A26
0x6A28
0x6A2A
ECAP3
0x6A40
0x6A42
0x6A44
0x6A46
0x6A48
0x6A4A
ECAP4
0x6A60
0x6A62
0x6A64
0x6A66
0x6A68
0x6A6A
ECAP5
0x6A80
0x6A82
0x6A84
0x6A86
0x6A88
0x6A8A
ECAP6
0x6AA0
0x6AA2
0x6AA4
0x6AA6
0x6AA8
0x6AAA
SIZE (x16)
DESCRIPTION
Time-Stamp Counter
2
2
2
2
2
2
8
Counter Phase Offset Value Register
Capture 1 Register
Capture 2 Register
Capture 3 Register
Capture 4 Register
Reserved
CAP2
CAP3
CAP4
Reserved
0x6A0C-
0x6A12
0x6A2C-0x6A32 0x6A4C- 0x6A52 0x6A6C- 0x6A72
0x6A8C-
0x6A92
0x6AAC-
0x6AB2
ECCTL1
ECCTL2
ECEINT
ECFLG
0x6A14
0x6A15
0x6A16
0x6A17
0x6A18
0x6A19
0x6A34
0x6A35
0x6A36
0x6A37
0x6A38
0x6A39
0x6A54
0x6A55
0x6A56
0x6A57
0x6A58
0x6A59
0x6A74
0x6A75
0x6A76
0x6A77
0x6A78
0x6A79
0x6A94
0x6A95
0x6A96
0x6A97
0x6A98
0x6A99
0x6AB4
0x6AB5
0x6AB6
0x6AB7
0x6AB8
0x6AB9
1
1
1
1
1
1
6
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
Reserved
ECCLR
ECFRC
Reserved
0x6A1A-
0x6A1F
0x6A3A- 0x6A3F 0x6A5A- 0x6A5F 0x6A7A- 0x6A7F
0x6A9A-
0x6A9F
0x6ABA-
0x6ABF
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4.6 Enhanced QEP Modules (eQEP1/2)
The device contains up to two enhanced quadrature encoder (eQEP) modules.
System
control registers
To CPU
EQEPxENCLK
SYSCLKOUT
QCPRD
QCAPCTL
16
QCTMR
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxINT
16
QCLK
QDIR
QI
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
PIE
Position counter/
control unit
(PCCU)
Quadrature
decoder
(QDU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
Enhanced QEP (eQEP) peripheral
Figure 4-7. eQEP Functional Block Diagram
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Table 4-5. eQEP Control and Status Registers
EQEP1
SIZE(x16)/
#SHADOW
EQEP1
ADDRESS
EQEP2
ADDRESS
NAME
REGISTER DESCRIPTION
eQEP Position Counter
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
0x6B00
0x6B02
0x6B04
0x6B06
0x6B08
0x6B0A
0x6B0C
0x6B0E
0x6B10
0x6B12
0x6B13
0x6B14
0x6B15
0x6B16
0x6B17
0x6B18
0x6B19
0x6B1A
0x6B1B
0x6B1C
0x6B1D
0x6B1E
0x6B1F
0x6B20
0x6B40
0x6B42
0x6B44
0x6B46
0x6B48
0x6B4A
0x6B4C
0x6B4E
0x6B50
0x6B52
0x6B53
0x6B54
0x6B55
0x6B56
0x6B57
0x6B58
0x6B59
0x6B5A
0x6B5B
0x6B5C
0x6B5D
0x6B5E
0x6B5F
0x6B60
2/0
2/0
2/0
2/1
2/0
2/0
2/0
2/0
2/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
31/0
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
QCAPCTL
QPOSCTL
QEINT
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
eQEP Capture Control Register
eQEP Position-compare Control Register
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
QCTMRLAT
QCPRDLAT
Reserved
0x6B21-
0x6B3F
0x6B61-
0x6B7F
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4.7 Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 4-8. The ADC module
consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module
include:
•
•
•
•
•
12-bit ADC core with built-in S/H
Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12.5 MSPS
16-channel, MUXed inputs
Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion
can be programmed to select any 1 of 16 input channels
•
•
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state
sequencer (i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
–
The digital value of the input analog voltage is derived by:
Digital Value + 0,
when input ≤ 0 V
Input Analog Voltage * ADCLO
when 0 V < input < 3 V
when input ≥ 3 V
Digital Value + 4096
3
Digital Value + 4095,
A. All fractional values are truncated.
•
Multiple triggers as sources for the start-of-conversion (SOC) sequence
–
–
–
S/W - software immediate start
ePWM start of conversion
XINT2 ADC start of conversion
•
•
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.
Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to
synchronize conversions.
•
•
SOCA and SOCB triggers can operate independently in dual-sequencer mode.
Sample-and-hold (S/H) acquisition time window has separate prescale control.
The ADC module in the F28335 has been enhanced to provide flexible interface to ePWM peripherals.
The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at
25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel
modules. The two independent 8-channel modules can be cascaded to form a 16-channel module.
Although there are multiple input channels and two sequencers, there is only one converter in the ADC
module. Figure 4-8 shows the block diagram of the ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module
has the choice of selecting any one of the respective eight channels available through an analog MUX. In
the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer,
once the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to
perform oversampling algorithms. This gives increased resolution over traditional single-sampled
conversion results.
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SYSCLKOUT
DSP
System
Control Block
High-Speed
Prescaler
HALT
HSPCLK
ADCENCLK
Analog
MUX
Result Registers
70A8h
Result Reg 0
Result Reg 1
ADCINA0
S/H
ADCINA7
ADCINB0
ADCINB7
12-Bit
ADC
Module
Result Reg 7
Result Reg 8
70AFh
70B0h
S/H
Result Reg 15
70B7h
ADC Control Registers
S/W
S/W
EPWMSOCB
EPWMSOCA
GPIO/
SOC
SOC
Sequencer 2
Sequencer 1
XINT2_ADCSOC
Figure 4-8. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( VDD1A18
,
VDD2A18 , VDDA2, VDDAIO) from the digital supply.Figure 4-9 shows the ADC pin connections for the devices.
NOTE
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the
ADC module is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT
signals is as follows:
–
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the
clock to the register will still function. This is necessary to make sure all registers
and modes go into their default reset state. The analog module, however, will be
in a low-power inactive state. As soon as reset goes high, then the clock to the
registers will be disabled. When the user sets the ADCENCLK signal high, then
the clocks to the registers will be enabled and the analog module will be enabled.
There will be a certain time delay (ms range) before the ADC is stable and can be
used.
–
HALT: This mode only affects the analog module. It does not affect the registers.
In this mode, the ADC module goes into low-power mode. This mode also will stop
the clock to the CPU, which will stop the HSPCLK; therefore, the ADC register
logic will be turned off indirectly.
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Figure 4-9 shows the ADC pin-biasing for internal reference and Figure 4-10 shows the ADC pin-biasing
for external reference.
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Analog input 0−3 V with respect to ADCLO
Connect to analog ground
Connect to analog ground if internal reference is used
ADCREFIN
22 k
ADC External Current Bias Resistor ADCRESEXT
(A)
2.2
2.2
F
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP
ADCREFM
ADCREFP and ADCREFM should not
be loaded by external circuitry
(A)
F
V
DD1A18
ADC Analog Power Pin (1.9 V)
ADC Analog Power Pin (1.9 V)
V
DD2A18
ADC Power
V
V
ADC Analog Ground Pin
ADC Analog Ground Pin
SS1AGND
SS2AGND
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
V
V
DDA2
SSA2
ADC Analog and Reference I/O Power
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
V
V
DDAIO
SSAIO
A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 4-9. ADC Pin Connections With Internal Reference
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
Connect to 1.500, 1.024, or 2.048-V precision source
(D)
ADCREFIN
22 kΩ
ADC External Current Bias Resistor ADCRESEXT
2.2 µF(A)
2.2 µF(A)
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP
ADCREFM
ADCREFP and ADCREFM should not
be loaded by external circuitry
V
ADC Analog Power Pin (1.9 V)
ADC Analog Power Pin (1.9 V)
DD1A18
V
DD2A18
ADC Analog Power
ADC Analog Ground Pin
ADC Analog Ground Pin
V
SS1AGND
V
SS2AGND
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
V
V
DDA2
SSA2
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
V
V
DDAIO
ADC Analog and Reference I/O Power
SSAIO
A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
D. External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on
the voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain
accuracy will be determined by accuracy of this voltage source.
Figure 4-10. ADC Pin Connections With External Reference
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NOTE
The temperature rating of any recommended component must match the rating of the end
product.
4.7.1 ADC Connections if the ADC Is Not Used
It is recommended to keep the connections for the analog power pins, even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:
•
•
•
•
•
•
•
•
VDD1A18/VDD2A18 – Connect to VDD
VDDA2, VDDAIO – Connect to VDDIO
VSS1AGND/VSS2AGND, VSSA2, VSSAIO – Connect to VSS
ADCLO – Connect to VSS
ADCREFIN – Connect to VSS
ADCREFP/ADCREFM – Connect a 100-nF cap to VSS
ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to VSS
ADCINAn, ADCINBn - Connect to VSS
.
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power
savings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (VSS1AGND/VSS2AGND
)
NOTE
ADC parameters for gain error and offset error are specified only if the ADC calibration
routine is executed from the Boot ROM. See Section 4.7.3 for more information.
4.7.2 ADC Registers
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-6.
Table 4-6. ADC Registers(1)
NAME
ADDRESS(1) ADDRESS(2) SIZE (x16)
DESCRIPTION
ADCTRL1
0x7100
0x7101
0x7102
0x7103
0x7104
0x7105
0x7106
0x7107
0x7108
0x7109
0x710A
0x710B
0x710C
0x710D
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADC Control Register 1
ADC Control Register 2
ADCTRL2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADCRESULT5
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto-Sequence Status Register
0x0B00
0x0B01
0x0B02
0x0B03
0x0B04
0x0B05
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
ADC Conversion Result Buffer Register 5
(1) The registers in this column are Peripheral Frame 2 Registers.
(2) The ADC result registers are dual mapped. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and left justified.
Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 1 wait-state for CPU accesses and 0 wait state for DMA accesses and right
justified. During high speed/continuous conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user
memory.
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(1)
Table 4-6. ADC Registers
(continued)
NAME
ADDRESS(1) ADDRESS(2) SIZE (x16)
DESCRIPTION
ADCRESULT6
ADCRESULT7
ADCRESULT8
ADCRESULT9
ADCRESULT10
ADCRESULT11
ADCRESULT12
ADCRESULT13
ADCRESULT14
ADCRESULT15
ADCTRL3
0x710E
0x710F
0x7110
0x7111
0x7112
0x7113
0x7114
0x7115
0x7116
0x7117
0x7118
0x7119
0x0B06
0x0B07
0x0B08
0x0B09
0x0B0A
0x0B0B
0x0B0C
0x0B0D
0x0B0E
0x0B0F
1
1
1
1
1
1
1
1
1
1
1
1
ADC Conversion Result Buffer Register 6
ADC Conversion Result Buffer Register 7
ADC Conversion Result Buffer Register 8
ADC Conversion Result Buffer Register 9
ADC Conversion Result Buffer Register 10
ADC Conversion Result Buffer Register 11
ADC Conversion Result Buffer Register 12
ADC Conversion Result Buffer Register 13
ADC Conversion Result Buffer Register 14
ADC Conversion Result Buffer Register 15
ADC Control Register 3
ADCST
ADC Status Register
0x711A
0x711B
Reserved
2
ADCREFSEL
ADCOFFTRIM
0x711C
0x711D
1
1
ADC Reference Select Register
ADC Offset Trim Register
0x711E
0x711F
Reserved
2
4.7.3 ADC Calibration
The ADC_cal() routine is programmed into TI reserved OTP memory by the factory. The boot ROM
automatically calls the ADC_cal() routine to initialize the ADCREFSEL and ADCOFFTRIM registers with
device specific calibration data. During normal operation, this process occurs automatically and no action
is required by the user.
If the boot ROM is bypassed by Code Composer Studio during the development process, then
ADCREFSEL and ADCOFFTRIM must be initialized by the application. For working examples, see the
ADC initialization in the C2833x, C2823x C/C++ Header Files and Peripheral Examples (SPRC530).
NOTE
FAILURE TO INITIALIZE THESE REGISTERS WILL CAUSE THE ADC TO FUNCTION
OUT OF SPECIFICATION.
If the system is reset or the ADC module is reset using Bit 14 (RESET) from the ADC
Control Register 1, the routine must be repeated.
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4.8 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
•
•
•
•
•
•
•
•
•
Full–duplex communication
Double–buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8–, 12–, 16–, 20–, 24–, or 32–bits
8–bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to industry–standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
•
•
Works with SPI–compatible devices
The following application interfaces can be supported on the McBSP:
–
–
–
–
–
T1/E1 framers
IOM–2 compliant devices
AC97–compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS–compliant devices
SPI
•
McBSP clock rate,
CLKSRG
CLKG =
1+ CLKGDV
(
)
(1)
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O
buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less
than the I/O buffer speed limit.
NOTE
See Section 6 for maximum I/O pin toggling speed.
Figure 4-11 shows the block diagram of the McBSP module.
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TX
Interrupt
MXINT
Peripheral Write Bus
CPU
TX Interrupt Logic
To CPU
16
16
McBSP Transmit
Interrupt Select Logic
DXR2 Transmit Buffer
16
DXR1 Transmit Buffer
16
LSPCLK
MFSXx
MCLKXx
Compand Logic
XSR2
XSR1
MDXx
MDRx
CPU
DMA Bus
RSR1
16
RSR2
16
MCLKRx
Expand Logic
MFSRx
RBR2 Register
16
RBR1 Register
16
DRR2 Receive Buffer
DRR1 Receive Buffer
McBSP Receive
16
16
Interrupt Select Logic
RX
RX Interrupt Logic
Interrupt
MRINT
CPU
Peripheral Read Bus
To CPU
Figure 4-11. McBSP Module
Table 4-7 provides a summary of the McBSP registers.
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Table 4-7. McBSP Register Summary
McBSP-A
ADDRESS
McBSP-B
ADDRESS
TYPE
RESET VALUE DESCRIPTION
DATA REGISTERS, RECEIVE, TRANSMIT
DRR2
DRR1
DXR2
DXR1
0x5000
0x5001
0x5002
0x5003
0x5040
0x5041
0x5042
0x5043
R
R
0x0000
0x0000
0x0000
0x0000
McBSP Data Receive Register 2
McBSP Data Receive Register 1
McBSP Data Transmit Register 2
McBSP Data Transmit Register 1
W
W
McBSP CONTROL REGISTERS
SPCR2
SPCR1
RCR2
0x5004
0x5005
0x5006
0x5007
0x5008
0x5009
0x500A
0x500B
0x5044
0x5045
0x5046
0x5047
0x5048
0x5049
0x504A
0x504B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Serial Port Control Register 2
McBSP Serial Port Control Register 1
McBSP Receive Control Register 2
McBSP Receive Control Register 1
McBSP Transmit Control Register 2
McBSP Transmit Control Register 1
McBSP Sample Rate Generator Register 2
McBSP Sample Rate Generator Register 1
RCR1
XCR2
XCR1
SRGR2
SRGR1
MULTICHANNEL CONTROL REGISTERS
MCR2
0x500C
0x500D
0x500E
0x500F
0x5010
0x5011
0x5012
0x5013
0x5014
0x5015
0x5016
0x5017
0x5018
0x5019
0x501A
0x501B
0x501C
0x501D
0x501E
0x5023
0x504C
0x504D
0x504E
0x504F
0x5050
0x5051
0x5052
0x5053
0x5054
0x5055
0x5056
0x5057
0x5058
0x5059
0x505A
0x505B
0x505C
0x505D
0x505E
0x5063
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Multichannel Register 2
MCR1
McBSP Multichannel Register 1
RCERA
RCERB
XCERA
XCERB
PCR
McBSP Receive Channel Enable Register Partition A
McBSP Receive Channel Enable Register Partition B
McBSP Transmit Channel Enable Register Partition A
McBSP Transmit Channel Enable Register Partition B
McBSP Pin Control Register
RCERC
RCERD
XCERC
XCERD
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
XCERH
MFFINT
McBSP Receive Channel Enable Register Partition C
McBSP Receive Channel Enable Register Partition D
McBSP Transmit Channel Enable Register Partition C
McBSP Transmit Channel Enable Register Partition D
McBSP Receive Channel Enable Register Partition E
McBSP Receive Channel Enable Register Partition F
McBSP Transmit Channel Enable Register Partition E
McBSP Transmit Channel Enable Register Partition F
McBSP Receive Channel Enable Register Partition G
McBSP Receive Channel Enable Register Partition H
McBSP Transmit Channel Enable Register Partition G
McBSP Transmit Channel Enable Register Partition H
McBSP Interrupt Enable Register
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4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
The CAN module has the following features:
•
•
•
Fully compliant with CAN protocol, version 2.0B
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
–
–
–
–
–
–
–
–
–
–
Configurable as receive or transmit
Configurable with standard or extended identifier
Has a programmable receive mask
Supports data and remote frame
Composed of 0 to 8 bytes of data
Uses a 32-bit time stamp on receive and transmit message
Protects against reception of new message
Holds the dynamically programmable priority of transmit message
Employs a programmable interrupt scheme with two interrupt levels
Employs a programmable alarm on transmission or reception time-out
•
•
•
•
•
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)
•
Self-test mode
–
Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE
For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.625 kbps.
For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.
The F28335 CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and
exceptions.
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Address
Controls
Data
32
eCAN0INT
eCAN1INT
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 × 32-Bit Words
32
32
32
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
eCAN Protocol Kernel
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 4-12. eCAN Block Diagram and Interface Circuit
Table 4-8. 3.3-V eCAN Transceivers
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
PART NUMBER
VREF
OTHER
TA
SN65HVD230
SN65HVD230Q
SN65HVD231
SN65HVD231Q
SN65HVD232
SN65HVD232Q
SN65HVD233
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Standby
Standby
Sleep
Adjustable
Adjustable
Adjustable
Adjustable
None
Yes
Yes
–
–
–
–
–
–
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 125°C
Yes
Sleep
Yes
None
None
None
None
None
None
Standby
Adjustable
Diagnostic
Loopback
SN65HVD234
SN65HVD235
3.3 V
3.3 V
Standby and Sleep
Standby
Adjustable
Adjustable
None
None
–
-40°C to 125°C
-40°C to 125°C
Autobaud
Loopback
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eCAN-A Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
eCAN-A Memory (512 Bytes)
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
6000h
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Control and Status Registers
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Message Object Time Stamps (MOTS)
Bit-Timing Configuration − CANBTC
Error and Status − CANES
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
(32 × 32-Bit RAM)
eCAN-A Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
6100h−6107h
6108h−610Fh
6110h−6117h
6118h−611Fh
6120h−6127h
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
61E0h−61E7h
61E8h−61EFh
61F0h−61F7h
61F8h−61FFh
Reserved
Message Mailbox (16 Bytes)
Message Identifier − MSGID
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
61E8h−61E9h
61EAh−61EBh
61ECh−61EDh
61EEh−61EFh
Figure 4-13. eCAN-A Memory Map
NOTE
If the eCAN module is not used in an application, the RAM available (LAM, MOTS,
MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock
should be enabled for this.
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eCAN-B Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
eCAN-B Memory (512 Bytes)
Control and Status Registers
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
6200h
623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Message Object Time Stamps (MOTS)
Bit-Timing Configuration − CANBTC
Error and Status − CANES
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
(32 × 32-Bit RAM)
eCAN-B Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
6300h−6307h
6308h−630Fh
6310h−6317h
6318h−631Fh
6320h−6327h
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
63E0h−63E7h
63E8h−63EFh
63F0h−63F7h
63F8h−63FFh
Reserved
Message Mailbox (16 Bytes)
Message Identifier − MSGID
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
63E8h−63E9h
63EAh−63EBh
63ECh−63EDh
63EEh−63EFh
Figure 4-14. eCAN-B Memory Map
The CAN registers listed in Table 4-9 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
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Table 4-9. CAN Register Map(1)
ECAN-A
REGISTER NAME
ECAN-B
ADDRESS
SIZE
(x32)
DESCRIPTION
ADDRESS
CANME
CANMD
0x6000
0x6002
0x6004
0x6006
0x6008
0x600A
0x600C
0x600E
0x6010
0x6012
0x6014
0x6016
0x6018
0x601A
0x601C
0x601E
0x6020
0x6022
0x6024
0x6026
0x6028
0x602A
0x602C
0x602E
0x6030
0x6032
0x6200
0x6202
0x6204
0x6206
0x6208
0x620A
0x620C
0x620E
0x6210
0x6212
0x6214
0x6216
0x6218
0x621A
0x621C
0x621E
0x6220
0x6222
0x6224
0x6226
0x6228
0x622A
0x622C
0x622E
0x6230
0x6232
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mailbox enable
Mailbox direction
CANTRS
CANTRR
CANTA
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
CANAA
CANRMP
CANRML
CANRFP
CANGAM
CANMC
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
CANBTC
CANES
Bit-timing configuration
Error and status
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
The devices include three serial communications interface (SCI) modules. The SCI modules support
digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its
own separate enable and interrupt bits. Both can be operated independently or simultaneously in the
full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,
overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit
baud-select register.
Features of each SCI module include:
•
Two external pins:
–
–
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
Baud rate programmable to 64K different rates:
–
LSPCLK
(BRR ) 1) * 8
Baud rate =
when BRR ≠ 0
when BRR = 0
LSPCLK
16
Baud rate =
NOTE
See Section 6 for maximum I/O pin toggling speed.
•
Data-word format
–
–
–
–
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (non-return-to-zero) format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
•
•
Auto baud-detect hardware logic
16-level transmit/receive FIFO
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The SCI port operation is configured and controlled by the registers listed in Table 4-10, Table 4-11, and
Table 4-12.
Table 4-10. SCI-A Registers(1)
NAME
ADDRESS
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
SIZE (x16)
DESCRIPTION
SCI-A Communications Control Register
SCI-A Control Register 1
SCICCRA
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(2)
SCIFFRXA(2)
SCIFFCTA(2)
SCIPRIA
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 4-11. SCI-B Registers(1) (2)
NAME
ADDRESS
0x7750
0x7751
0x7752
0x7753
0x7754
0x7755
0x7756
0x7757
0x7759
0x775A
0x775B
0x775C
0x775F
SIZE (x16)
DESCRIPTION
SCI-B Communications Control Register
SCI-B Control Register 1
SCICCRB
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB(2)
SCIFFRXB(2)
SCIFFCTB(2)
SCIPRIB
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 4-12. SCI-C Registers(1) (2)
NAME
ADDRESS
0x7770
0x7771
0x7772
0x7773
SIZE (x16)
DESCRIPTION
SCI-C Communications Control Register
SCI-C Control Register 1
SCICCRC
1
1
1
1
SCICTL1C
SCIHBAUDC
SCILBAUDC
SCI-C Baud Register, High Bits
SCI-C Baud Register, Low Bits
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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(1) (2)
Table 4-12. SCI-C Registers
(continued)
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICTL2C
SCIRXSTC
SCIRXEMUC
SCIRXBUFC
SCITXBUFC
SCIFFTXC(2)
SCIFFRXC(2)
SCIFFCTC(2)
SCIPRC
0x7774
0x7775
0x7776
0x7777
0x7779
0x777A
0x777B
0x777C
0x777F
1
1
1
1
1
1
1
1
1
SCI-C Control Register 2
SCI-C Receive Status Register
SCI-C Receive Emulation Data Buffer Register
SCI-C Receive Data Buffer Register
SCI-C Transmit Data Buffer Register
SCI-C FIFO Transmit Register
SCI-C FIFO Receive Register
SCI-C FIFO Control Register
SCI-C Priority Control Register
Figure 4-15 shows the SCI module block diagram.
SCICTL1.1
SCITXD
Frame Format and Mode
SCITXD
TXSHF
Register
TXENA
Parity
Even/Odd Enable
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY
TX INT ENA
SCICTL2.0
Transmitter-Data
Buffer Register
SCICTL2.7
TXWAKE
SCICTL1.3
1
8
TX FIFO _0
TX FIFO
Interrupts
TXINT
TX Interrupt
Logic
TX FIFO _1
-----
To CPU
TX FIFO _15
SCI TX Interrupt select logic
SCITXBUF.7-0
WUT
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 - 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7-0
RXRDY
RX/BK INT ENA
SCIRXST.6
8
RX FIFO _15
BRKDT
SCIRXST.5
-----
RX FIFO
Interrupts
RX FIFO_1
RX FIFO _0
RXINT
RX Interrupt
Logic
SCIRXBUF.7-0
RX FIFO registers
To CPU
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 4-15. Serial Communications Interface (SCI) Module Block Diagram
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4.11 Serial Peripheral Interface (SPI) Module (SPI-A)
The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is
available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable
bit-transfer rate. Normally, the SPI is used for communications between the DSC controller and external
peripherals or another processor. Typical applications include external I/O or peripheral expansion through
devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by
the master/slave operation of the SPI.
The SPI module features include:
•
Four external pins:
–
–
–
–
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
Baud rate =
when SPIBRR = 3 to 127
when SPIBRR = 0,1, 2
(SPIBRR ) 1)
LSPCLK
Baud rate =
4
NOTE
See Section 6 for maximum I/O pin toggling speed.
•
•
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
•
•
16-level transmit/receive FIFO
Delayed transmit control
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The SPI port operation is configured and controlled by the registers listed in Table 4-13.
Table 4-13. SPI-A Registers
NAME
SPICCR
SPICTL
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
SIZE (X16)
DESCRIPTION(1)
SPI-A Configuration Control Register
SPI-A Operation Control Register
1
1
1
1
1
1
1
1
1
1
1
1
SPISTS
SPI-A Status Register
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-A Baud Rate Register
SPI-A Receive Emulation Buffer Register
SPI-A Serial Input Buffer Register
SPI-A Serial Output Buffer Register
SPI-A Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-A FIFO Transmit Register
SPI-A FIFO Receive Register
SPI-A FIFO Control Register
SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Figure 4-16 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPIRXBUF
SPISTS.7
SPICTL.4
RX FIFO _0
RX FIFO _1
SPIINT/SPIRXINT
RX FIFO Interrupt
−−−−−
RX FIFO _15
RX Interrupt
Logic
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
−−−−−
TX FIFO _1
SPITXINT
TX FIFO _0
16
SPI INT
ENA
SPI INT FLAG
SPISTS.6
SPITXBUF
Buffer Register
16
SPICTL.0
16
M
S
M
SPIDAT
Data Register
S
SW1
SW2
SPISIMO
SPISOMI
M
S
M
SPIDAT.15 − 0
S
Talk
SPICTL.1
(A)
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 − 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
LSPCLK
SPICCR.6
SPICTL.3
SPICLK
SPIBRR.6 − 0
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
Figure 4-16. SPI Module Block Diagram (Slave Mode)
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4.12 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module interfaces
within the device.
System Control
C28X CPU
Block
I2CAENCLK
SYSCLKOUT
SYSRS
Control
Data[16]
SDAA
Data[16]
GPIO
MUX
2
I C−A
Addr[16]
I2CINT1A
I2CINT2A
SCLA
PIE
Block
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCR0 register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 4-17. I2C Peripheral Module Interfaces
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
–
–
–
–
–
–
–
–
Support for 1-bit to 8-bit format transfers
7-bit and 10-bit addressing modes
General call
START byte mode
Support for multiple master-transmitters and slave-receivers
Support for multiple slave-transmitters and master-receivers
Combined master transmit/receive and receive/transmit mode
Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)
•
•
One 16-word receive FIFO and one 16-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
–
–
–
–
Transmit-data ready
Receive-data ready
Register-access ready
No-acknowledgment received
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–
–
–
Arbitration lost
Stop condition detected
Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
The registers in Table 4-14 configure and control the I2C port operation.
Table 4-14. I2C-A Registers
NAME
I2COAR
I2CIER
ADDRESS
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
-
DESCRIPTION
I2C own address register
I2C interrupt enable register
I2C status register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
-
4.13 GPIO MUX
On the F28335, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in Figure 4-18. Because of the open drain capabilities of the I2C pins, the GPIO MUX block
diagram for these pins differ.
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and
GPxQSELn registers occurs to when the action is valid.
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GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLMPSEL
LPMCR0
GPIOXINT7SEL
GPIOXNMISEL
External Interrupt
MUX
Low Power
Modes Block
PIE
Asynchronous
path
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD
N/C
00
01
Peripheral 1 Input
Peripheral 2 Input
Input
Internal
Pullup
Qualification
10
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
01
GPxDAT (latch)
Peripheral 1 Output
10
11
Peripheral 2 Output
Peripheral 3 Output
High Impedance
Output Control
GPxDIR (latch)
00
01
Peripheral 1 Output Enable
Peripheral 2 Output Enable
0 = Input, 1 = Output
XRS
10
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins.
Figure 4-18. GPIO MUX Block Diagram
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The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame
1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO
register mapping.
Table 4-15. GPIO Registers
NAME
ADDRESS
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
0x6F80 GPIO A Control Register (GPIO0 to 31)
SIZE (x16)
DESCRIPTION
GPACTRL
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
2
2
2
2
18
0x6F82
0x6F84
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
0x6F86
0x6F88
GPIO A MUX 2 Register (GPIO16 to 31)
0x6F8A
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pull Up Disable Register (GPIO0 to 31)
GPAPUD
0x6F8C
Reserved
GPBCTRL
GPBQSEL1
GPBQSEL2
GPBMUX1
GPBMUX2
GPBDIR
0x6F8E – 0x6F8F
0x6F90
GPIO B Control Register (GPIO32 to 63)
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
GPIOB Qualifier Select 2 Register (GPIO48 to 63)
GPIO B MUX 1 Register (GPIO32 to 47)
0x6F92
0x6F94
0x6F96
0x6F98
GPIO B MUX 2 Register (GPIO48 to 63)
0x6F9A
GPIO B Direction Register (GPIO32 to 63)
GPIO B Pull Up Disable Register (GPIO32 to 63)
GPBPUD
0x6F9C
Reserved
GPCMUX1
GPCMUX2
GPCDIR
0x6F9E – 0x6FA5
0x6FA6
GPIO C MUX1 Register (GPIO64 to 79)
GPIO C MUX2 Register (GPIO80 to 87)
GPIO C Direction Register (GPIO64 to 87)
GPIO C Pull Up Disable Register (GPIO64 to 87)
0x6FA8
0x6FAA
GPCPUD
Reserved
0x6FAC
0x6FAE – 0x6FBF
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
GPASET
0x6FC0
0x6FC2
2
2
2
2
2
2
2
2
2
2
2
2
8
GPIO A Data Register (GPIO0 to 31)
GPIO A Data Set Register (GPIO0 to 31)
GPIO A Data Clear Register (GPIO0 to 31)
GPIO A Data Toggle Register (GPIO0 to 31)
GPIO B Data Register (GPIO32 to 63)
GPACLEAR
GPATOGGLE
GPBDAT
0x6FC4
0x6FC6
0x6FC8
GPBSET
0x6FCA
GPIO B Data Set Register (GPIO32 to 63)
GPIO B Data Clear Register (GPIO32 to 63)
GPIOB Data Toggle Register (GPIO32 to 63)
GPIO C Data Register (GPIO64 to 87)
GPBCLEAR
GPBTOGGLE
GPCDAT
0x6FCC
0x6FCE
0x6FD0
GPCSET
0x6FD2
GPIO C Data Set Register (GPIO64 to 87)
GPIO C Data Clear Register (GPIO64 to 87)
GPIO C Data Toggle Register (GPIO64 to 87)
GPCCLEAR
GPCTOGGLE
Reserved
0x6FD4
0x6FD6
0x6FD8 0x6FDF
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
GPIOXINT3SEL
GPIOXINT4SEL
GPIOXINT5SEL
0x6FE0
0x6FE1
0x6FE2
0x6FE3
0x6FE4
0x6FE5
1
1
1
1
1
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XNMI GPIO Input Select Register (GPIO0 to 31)
XINT3 GPIO Input Select Register (GPIO32 to 63)
XINT4 GPIO Input Select Register (GPIO32 to 63)
XINT5 GPIO Input Select Register (GPIO32 to 63)
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Table 4-15. GPIO Registers (continued)
NAME
ADDRESS
0x6FE6
SIZE (x16)
DESCRIPTION
XINT6 GPIO Input Select Register (GPIO32 to 63)
XINT7 GPIO Input Select Register (GPIO32 to 63)
LPM GPIO Select Register (GPIO0 to 31)
GPIOXINT6SEL
GPIOINT7SEL
GPIOLPMSEL
Reserved
1
1
0x6FE7
0x6FE8
2
0x6FEA – 0x6FFF
22
Table 4-16. GPIO-A Mux Peripheral Selection Matrix
REGISTER BITS
PERIPHERAL SELECTION
GPADIR
GPADAT
GPAMUX1
GPAQSEL1
GPIOx
GPAMUX1=0,0
PER1
GPAMUX1 = 0, 1
PER2
GPAMUX1 = 1, 0
PER3
GPAMUX1 = 1, 1
GPASET
GPACLR
GPATOGGLE
QUALPRD0
0
1
1, 0
GPIO0 (I/O)
GPIO1 (I/O)
GPIO2 (I/O)
GPIO3 (I/O)
GPIO4 (I/O)
GPIO5 (I/O)
GPIO6 (I/O)
GPIO7 (I/O)
GPIO8 (I/O)
GPIO9 (I/O)
GPIO10 (I/O)
GPIO11 (I/O)
GPIO12 (I/O)
GPIO13 (I/O)
GPIO14 (I/O)
GPIO15 (I/O)
GPAMUX2 =0, 0
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
TZ1 (I)
3, 2
ECAP6 (I/O)
ECAP5 (I/O)
MFSRB (I/O)
2
5, 4
3
7, 6
MCLKRB (I/O)
4
9, 8
5
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
MFSRA (I/O)
EPWMSYNCI (I)
MCLKRA (I/O)
CANTXB (O)
SCITXDB (O)
CANRXB (I)
ECAP1 (I/O)
EPWMSYNCO (O)
ECAP2 (I/O)
6
7
QUALPRD1
8
ADCSOCAO (O)
ECAP3 (I/O)
9
10
11
12
13
14
15
ADCSOCBO (O)
ECAP4 (I/O)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
MDXB (O)
TZ2 (I)
MDRB (I)
TZ3 (I)/XHOLD (I)
TZ4 (I)/XHOLDA (O)
GPAMUX2 = 0, 1
SCITXDB (O)
SCIRXDB (I)
GPAMUX2 = 1, 0
MCLKXB (I/O)
MFSXB (I/O)
GPAMUX2
GPAMUX2 = 1, 1
GPAQSEL2
QUALPRD2
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1, 0
GPIO16 (I/O)
GPIO17 (I/O)
GPIO18 (I/O)
GPIO19 (I/O)
GPIO20 (I/O)
GPIO21 (I/O)
GPIO22 (I/O)
GPIO23 (I/O)
GPIO24 (I/O)
GPIO25 (I/O)
GPIO26 (I/O)
GPIO27 (I/O)
GPIO28 (I/O)
GPIO29 (I/O)
GPIO30 (I/O)
GPIO31 (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
MDXA (O)
TZ5 (I)
3, 2
TZ6 (I)
5, 4
CANRXA (I)
CANTXA (O)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
MDXB (O)
7, 6
9, 8
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
EQEP1B (I)
MDRA (I)
EQEP1S (I/O)
EQEP1I (I/O)
ECAP1 (I/O)
ECAP2 (I/O)
ECAP3 (I/O)
ECAP4 (I/O)
SCIRXDA (I)
SCITXDA (O)
CANRXA (I)
MCLKXA (I/O)
MFSXA (I/O)
EQEP2A (I)
EQEP2B (I)
EQEP2I (I/O)
EQEP2S (I/O)
QUALPRD3
MDRB (I)
MCLKXB (I/O)
MFSXB (I/O)
XZCS6 (O)
XA19 (O)
XA18 (O)
XA17 (O)
CANTXA (O)
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Table 4-17. GPIO-B Mux Peripheral Selection Matrix
REGISTER BITS
PERIPHERAL SELECTION
GPBDIR
GPBMUX1
GPIOx
PER1
PER2
PER3
GPBDAT
GPBSET
GPBQSEL1
GPBMUX1=0, 0
GPBMUX1 = 0, 1
GPBMUX1 = 1, 0
GPBMUX1 = 1, 1
GPBCLR
GPBTOGGLE
QUALPRD0
0
1
1, 0
GPIO32 (I/O)
GPIO33 (I/O)
GPIO34 (I/O)
GPIO35 (I/O)
GPIO36 (I/O)
GPIO37 (I/O)
GPIO38 (I/O)
GPIO39 (I/O)
GPIO40 (I/O)
GPIO41 (I/O)
GPIO42 (I/O)
GPIO43 (I/O)
GPIO44 (I/O)
GPIO45 (I/O)
GPIO46 (I/O)
GPIO47 (I/O)
GPBMUX2 =0, 0
SDAA (I/OC)(1)
SCLA (I/OC)(1)
ECAP1 (I/O)
SCITXDA (O)
SCIRXDA (I)
ECAP2 (I/O)
EPWMSYNCI (I)
ADCSOCAO (O)
ADCSOCBO (O)
3, 2
EPWMSYNCO (O)
2
5, 4
XREADY (I)
3
7, 6
XR/W (O)
XZCS0 (O)
XZCS7 (O)
XWE0 (O)
XA16 (O)
XA0/XWE1 (O)
XA1 (O)
4
9, 8
5
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
6
7
QUALPRD1
8
9
10
11
12
13
14
15
XA2 (O)
Reserved
XA3 (O)
XA4 (O)
XA5 (O)
XA6 (O)
XA7 (O)
GPBMUX2
GPBMUX2 = 0, 1
GPBMUX2 = 1, 0
GPBMUX2 = 1, 1
GPBQSEL2
QUALPRD2
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1, 0
GPIO48 (I/O)
GPIO49 (I/O)
GPIO50 (I/O)
GPIO51 (I/O)
GPIO52 (I/O)
GPIO53 (I/O)
GPIO54 (I/O)
GPIO55 (I/O)
GPIO56 (I/O)
GPIO57 (I/O)
GPIO58 (I/O)
GPIO59 (I/O)
GPIO60 (I/O)
GPIO61 (I/O)
GPIO62 (I/O)
GPIO63 (I/O)
ECAP5 (I/O)
ECAP6 (I/O)
XD31 (I/O)
XD30 (I/O)
XD29 (I/O)
XD28 (I/O)
XD27 (I/O)
XD26 (I/O)
XD25 (I/O)
XD24 (I/O)
XD23 (I/O)
XD22 (I/O)
XD21 (I/O)
XD20 (I/O)
XD19 (I/O)
XD18 (I/O)
XD17 (I/O)
XD16 (I/O)
3, 2
5, 4
EQEP1A (I)
7, 6
EQEP1B (I)
9, 8
EQEP1S (I/O)
EQEP1I (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
MCLKRA (I/O)
MFSRA (I/O)
MCLKRB (I/O)
MFSRB (I/O)
SCIRXDC (I)
SCITXDC (O)
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
QUALPRD3
(1) Open drain
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Table 4-18. GPIO-C Mux Peripheral Selection Matrix
REGISTER BITS
PERIPHERAL SELECTION
GPCDIR
GPCDAT
GPCMUX1
GPIOx or PER1
GPCMUX1 = 0, 0 or 0, 1
PER2 or PER3
GPCMUX1 = 1, 0 or 1, 1
GPCSET
GPCCLR
GPCTOGGLE
no qual
0
1
1, 0
3, 2
GPIO64 (I/O)
GPIO65 (I/O)
GPIO66 (I/O)
GPIO67 (I/O)
GPIO68 (I/O)
GPIO69 (I/O)
GPIO70 (I/O)
GPIO71 (I/O)
GPIO72 (I/O)
GPIO73 (I/O)
GPIO74 (I/O)
GPIO75 (I/O)
GPIO76 (I/O)
GPIO77 (I/O)
GPIO78 (I/O)
GPIO79 (I/O)
GPCMUX2 = 0, 0 or 0, 1
GPIO80 (I/O)
GPIO81 (I/O)
GPIO82 (I/O)
GPIO83 (I/O)
GPIO84 (I/O)
GPIO85 (I/O)
GPIO86 (I/O)
GPIO87 (I/O)
XD15 (I/O)
XD14 (I/O)
XD13 (I/O)
XD12 (I/O)
XD11 (I/O)
XD10 (I/O)
XD9 (I/O)
2
5, 4
3
7, 6
4
9, 8
5
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
GPCMUX2
1, 0
6
7
XD8 (I/O)
no qual
8
XD7 (I/O)
9
XD6 (I/O)
10
11
12
13
14
15
XD5 (I/O)
XD4 (I/O)
XD3 (I/O)
XD2 (I/O)
XD1 (I/O)
XD0 (I/O)
GPCMUX2 = 1, 0 or 1, 1
XA8 (O)
no qual
16
17
18
19
20
21
22
23
3, 2
XA9 (O)
5, 4
XA10 (O)
7, 6
XA11 (O)
9, 8
XA12 (O)
11, 10
13, 12
15, 14
XA13 (O)
XA14 (O)
XA15 (O)
The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
•
Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0, 0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
•
Qualification Using Sampling Window (GPxQSEL1/2=0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before
the input is allowed to change.
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Time between samples
GPyCTRL Reg
Input Signal
Qualified By 3
or 6 Samples
Qualification
GPIOx
SYNC
GPxQSEL
SYSCLKOUT
Number of Samples
Figure 4-19. Qualification Using Sampling Window
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the
input signal will default to either a 0 or 1 state, depending on the peripheral.
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4.14 External Interface (XINTF)
This section gives a top-level view of the external interface (XINTF) that is implemented on the F28335.
The XINTF is a non-multiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into
three fixed zones shown in Figure 4-20.
Data Space
Prog Space
0x0000−0000
XD(31:0)
XA(19:0)
0x0000−4000
XINTF Zone 0
XZCS0
(8K x 16)
0x0000−5000
0x0010−0000
0x0020−0000
0x0030−0000
XZCS6
XINTF Zone 6
(1M x 16)
XZCS7
XINTF Zone 7
(1M x 16)
XA0/XWE1
XWE0
XRD
XR/W
XREADY
XHOLD
XHOLDA
XCLKOUT
A. Each zone can be programmed with different wait states, setup and hold timings, and is supported by zone chip
selects that toggle when an access to a particular zone is performed. These features enable glueless connection to
many external memories and peripherals.
B. Zones 1 – 5 are reserved for future expansion.
C. Zones 0, 6, and 7 are always enabled.
Figure 4-20. External Interface Block Diagram
Figure 4-21 and Figure 4-22 show typical 16-bit and 32-bit data bus XINTF connections, illustrating how
the functionality of the XA0 and XWE1 signals change, depending on the configuration. Table 4-19 defines
XINTF configuration and control registers.
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XINTF
XREADY
External
wait-state
generator
16-bits
XCLKOUT
CS
XZCS0/6/7
XA(19:1)
XA0/XWE1
XRD
A(19:1)
A(0)
OE
WE
XWE0
D(15:0)
XD(15:0)
Figure 4-21. Typical 16-bit Data Bus XINTF Connections
XINTF
External
XREADY
wait-state
Low 16-bits
XCLKOUT
generator
CS
A(18:0)
OE
XA(19:1)
XRD
WE
XWE0
D(15:0)
XD(15:0)
High 16-bits
A(18:0)
CS
OE
WE
XZCS0/6/7
XA0/XWE1
(select XWE1)
D(31:16)
XD(31:16)
Figure 4-22. Typical 32-bit Data Bus XINTF Connections
Table 4-19. XINTF Configuration and Control Register Mapping
NAME
ADDRESS
0x00−0B20
0x00−0B2C
0x00−0B2E
0x00−0B34
0x00−0B38
0x00−0B3A
0x00 083D
SIZE (x16)
DESCRIPTION
XTIMING0
XTIMING6(1)
XTIMING7
XINTCNF2(2)
XBANK
2
2
2
2
1
1
1
XINTF Timing Register, Zone 0
XINTF Timing Register, Zone 6
XINTF Timing Register, Zone 7
XINTF Configuration Register
XINTF Bank Control Register
XINTF Revision Register
XINTF Reset Register
XREVISION
XRESET
(1) XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
(2) XINTCNF1 is reserved and not currently used.
100
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5
Device Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSCs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of F28335-based applications:
Software Development Tools
•
Code Composer Studio™ Integrated Development Environment (IDE)
–
–
–
–
C/C++ Compiler
Code generation tools
Assembler/Linker
Cycle Accurate Simulator
•
•
Application algorithms
Sample applications code
Hardware Development Tools
•
•
•
•
•
Development board
Evaluation modules
JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510USB
Universal 5-V dc power supply
Documentation and cables
6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.
6.1 Absolute Maximum Ratings(1) (2)
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.
Supply voltage range, VDDIO, VDD3VFL
Supply voltage range, VDDA2, VDDAIO
Supply voltage range, VDD
with respect to VSS
with respect to VSSA
with respect to VSS
with respect to VSSA
with respect to VSS
– 0.3 V to 4.6 V
– 0.3 V to 4.6 V
– 0.3 V to 2.5 V
– 0.3 V to 2.5 V
– 0.3 V to 0.3 V
– 0.3 V to 4.6 V
– 0.3 V to 4.6 V
± 20 mA
Supply voltage range, VDD1A18, VDD2A18
Supply voltage range, VSSA2, VSSAIO, VSS1AGND, VSS2AGND
Input voltage range, VIN
Output voltage range, VO
(3)
Input clamp current, IIK (VIN < 0 or VIN > VDDIO
)
Output clamp current, IOK (VO < 0 or VO > VDDIO
Operating ambient temperature ranges,
)
± 20 mA
TA: A version
– 40°C to 85°C
– 40°C to 125°C
– 40°C to 125°C
– 55°C to 125°C
– 40°C to 150°C
– 65°C to 150°C
TA: S version(4)
TA: Q version(4)
TA: M version(4)
(4)
Junction temperature range, Tj
(4)
Storage temperature range, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ± 2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the
voltage to a diode drop above VDDA2 or below VSSA2
.
(4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device
life.
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1000
100
Wirebond Voiding
Fail Mode
10
Electromigration Fail Mode
1
0.1
100
110
120
130
140
150
160
170
Continuous TJ (°C)
A. See datasheet for absolute maximum and minimum recommended operating conditions.
B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
Figure 6-1. SM320F28335 Operating Life Derating Chart
102
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6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.135
1.805
1.71
NOM
3.3
1.9
1.8
0
MAX UNIT
Device supply voltage, I/O, VDDIO
3.465
1.995
1.89
V
Device operation @ 150 MHz
Device supply voltage CPU, VDD
V
Device operation @ 100 MHz
Supply ground, VSS, VSSIO, VSSAIO, VSSA2
VSS1AGND, VSS2AGND
,
V
ADC supply voltage (3.3 V), VDDA2, VDDAIO
ADC supply voltage, VDD1A18, VDD2A18
3.135
1.805
1.71
3.135
2
3.3
1.9
1.8
3.3
3.465
1.995
1.89
V
V
Device operation @ 150 MHz
Device operation @ 100 MHz
Flash supply voltage, VDD3VFL
3.465
150
V
Device clock frequency (system clock),
fSYSCLKOUT
MHz
High-level input voltage, VIH
Low-level input voltage, VIL
2
VDDIO
0.8
– 4
-8
V
All I/Os except Group 2
Group 2(1)
High-level output source current, VOH = 2.4 V,
IOH
mA
mA
All I/Os except Group 2
Group 2(1)
4
Low-level output sink current, VOL = VOL MAX,
IOL
8
A version
– 40
– 40
– 40
– 55
85
S version
125
125
125
Ambient temperature, TA
°C
Q version
M version
(1) Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, EMU1, XINTF pins, GPIO35-87, XRD.
6.3 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX UNIT
IOH = IOHMAX
IOH = 50 mA
VOH High-level output voltage
VOL Low-level output voltage
V
VDDIO – 0.2
IOL = IOLMAX
0.4
V
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIO
VDDIO = 3.3 V, VIN = VDDIO
VO = VDDIO or 0 V
All I/Os (including XRS)
– 80
– 140
– 190
Input current
(low level)
IIL
mA
Pin with pulldown
enabled
± 2
± 2
80
Pin with pullup
enabled
Input current
(high level)
IIH
mA
Pin with pulldown
enabled
28
50
2
Output current, pullup or
pulldown disabled
IOZ
CI
± 2
mA
Input capacitance
pF
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6.4 Current Consumption
Table 6-1. Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
(1)
(2)
(3)
(4)
IDD
IDDIO
TYP(5)
IDD3VFL
TYP
IDDA18
TYP(5)
IDDA33
TYP(5)
MODE
TEST CONDITIONS
TYP(5)
MAX
MAX
MAX
MAX
MAX
The following peripheral
clocks are enabled:
•
•
•
•
•
ePWM1/2/3/4/5/6
eCAP1/2/3/4/5/6
eQEP1/2
eCAN-A
SCI-A/B (FIFO
mode)
Operational
(Flash)(6)
290 mA
315 mA
30 mA
50 mA
35 mA
40 mA
30 mA
35 mA
1.5 mA
2 mA
•
•
•
•
SPI-A (FIFO mode)
ADC
I2C
CPU Timer 0/1/2
All PWM pins are toggled
at 150 kHz.
All I/O pins are left
unconnected.(7)
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
IDLE
100 mA
120 mA
15 mA
60 mA
120 mA
2 mA
10 mA
5 mA
60 mA
15 mA
20 mA
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT(8)
8 mA
60 mA
60 mA
120 mA
120 mA
2 mA
2 mA
10 mA
10 mA
5 mA
5 mA
60 mA
60 mA
15 mA
15 mA
20 mA
20 mA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(9)
150 mA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Table 6-66 . If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
(3) IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(4) IDDA33 includes current into VDDA2 and VDDAIO pins.
(5) The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and MAX voltage (VDD = 2.0
V; VDDIO, VDD3VFL, VDDA = 3.6 V).
(6) When the identical code is run off SARAM, IDD would increase as the code operates with zero wait states.
(7) The following is done in a loop:
•
•
•
•
•
•
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Multiplication/addition operations are performed.
Watchdog is reset.
ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.
32-bit read/write of the XINTF is performed.
GPIO19 is toggled.
(8) HALT mode IDD currents will increase with temperature in a non-linear fashion.
(9) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
NOTE
The peripheral - I/O multiplexing implemented in the device prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done,
the current drawn by the device will be more than the numbers specified in the current
consumption tables.
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6.4.1 Reducing Current Consumption
The F28335 DSC incorporates a method to reduce the device current consumption. Since each peripheral
unit has an individual clock-enable bit, reduction in current consumption can be achieved by turning off the
clock to any peripheral module that is not used in a given application. Furthermore, any one of the three
low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-2
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 6-2. Typical Current Consumption by Various
Peripherals (at 150 MHz)(1)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION/MODULE (mA)(2)
ADC
I2C
8(3)
2.5
5
eQEP
ePWM
eCAP
SCI
5
2
5
SPI
4
eCAN
McBSP
CPU - Timer
XINTF
DMA
8
7
2
10(4)
10
15
FPU
(1) All peripheral clocks are disabled upon reset. Writing to/reading from
peripheral registers is possible only after the peripheral clocks are
turned on.
(2) For peripherals with multiple instances, the current quoted is per
module. For example, the 5 mA number quoted for ePWM is for one
ePWM module.
(3) This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the ADC
(IDDA18) as well.
(4) Operating the XINTF bus has a significant effect on IDDIO current. It
will increase considerably based on the following:
•
•
•
•
How many address/data pins toggle from one cycle to another
How fast they toggle
Whether 16-bit or 32-bit interface is used and
The load on these pins.
Following are other methods to reduce power consumption further:
•
The Flash module may be powered down if code is run off SARAM. This results in a current reduction
of 35 mA (typical) in the VDD3VFL rail.
•
•
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
Significant savings in IDDIO may be realized by disabling the pullups on pins that assume an output
function and on XINTF pins. A savings of 35 mW (typical) can be achieved by this.
The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is
165 mA, (typical). To arrive at the IDD current for a given application, the current-drawn by the peripherals
(enabled by that application) must be added to the baseline IDD current.
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6.4.2 Current Consumption Graphs
Current Vs Frequency
350.00
300.00
250.00
200.00
150.00
100.00
50.00
0.00
10 20
30 40 50 60 70
80 90 100 110 120 130 140 150
SYSCLKOUT (MHz)
IDD
IDDIO
IDDA18
IDD3VFL
1.8-V Current
3.3-V Current
Figure 6-2. Typical Operational Current Versus Frequency
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Device Power Vs SYSCLKOUT
1000.0
900.0
800.0
700.0
600.0
500.0
400.0
300.0
200.0
100.0
0.0
SYSCLKOUT (MHz)
Figure 6-3. Typical Operational Power Versus Frequency
NOTE
Typical operational current for 100-MHz devices (28x32) can be estimated from
Figure 6-2. Compared to 150-MHz devices, the analog and flash module currents remain
unchanged. While a marginal decrease in IDDIO current can be expected due to the
reduced external activity of peripheral pins, current reduction is primarily in IDD
.
6.4.3 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary.
Systems with more than 1 Watt power dissipation may require a product level thermal design. Care should
be taken to keep Tj within specified limits. In the end applications, Tcase should be measured to estimate
the operating junction temperature Tj. Tcase is normally measured at the center of the package top side
surface.
6.5 Emulator Connection Without Signal Buffering for the DSP
Figure 6-4 shows the connection between the DSP and JTAG header for a single-processor configuration.
If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals
must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-4 shows
the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.
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6 inches or less
VDDIO
VDDIO
13
14
2
5
EMU0
EMU1
TRST
TMS
TDI
EMU0
EMU1
TRST
TMS
PD
4
GND
1
6
GND
GND
GND
GND
3
8
TDI
7
10
12
TDO
TDO
11
9
TCK
TCK
TCK_RET
DSP
JTAG Header
Figure 6-4. Emulator Connection Without Signal Buffering for the DSP
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6.6 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
access time
H
L
High
Low
cycle time (period)
delay time
V
Valid
Unknown, changing, or don't care
level
f
fall time
X
Z
h
r
hold time
High impedance
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
6.6.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.6.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
(Α)
Z0 = 50 Ω
(B)
Device Pin
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 6-5. 3.3-V Test Load Circuit
6.6.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available. Table 6-3 and Table 6-4 list the cycle times of various clocks.
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Table 6-3. Clocking and Nomenclature (150-MHz devices)
MIN
28.6
20
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
50
35
ns
MHz
ns
On-chip oscillator
clock
tc(CI), Cycle time
Frequency
6.67
4
250
150
500
150
2000
150
XCLKIN(1)
SYSCLKOUT
XCLKOUT
HSPCLK(2)
LSPCLK(2)
ADC clock
MHz
ns
tc(SCO), Cycle time
Frequency
6.67
2
MHz
ns
tc(XCO), Cycle time
Frequency
6.67
0.5
6.67
MHz
ns
tc(HCO), Cycle time
Frequency
13.3(3)
75(3)
26.7(3)
37.5(3)
150
75
MHz
ns
tc(LCO), Cycle time
Frequency
13.3
40
MHz
ns
tc(ADCCLK), Cycle time
Frequency
25
MHz
(1) This also applies to the X1 pin if a 1.9-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default reset value if SYSCLKOUT = 150 MHz.
Table 6-4. Clocking and Nomenclature (100-MHz devices)
MIN
NOM
MAX UNIT
tc(OSC), Cycle time
28.6
20
10
4
50
35
ns
MHz
ns
On-chip oscillator
clock
Frequency
tc(CI), Cycle time
Frequency
250
100
500
100
2000
100
XCLKIN(1)
SYSCLKOUT
XCLKOUT
HSPCLK(2)
LSPCLK(2)
ADC clock
MHz
ns
tc(SCO), Cycle time
Frequency
10
2
MHz
ns
tc(XCO), Cycle time
Frequency
10
0.5
10
MHz
ns
(3)
tc(HCO), Cycle time
Frequency
20
(3)
50
100
50
MHz
ns
(3)
tc(LCO), Cycle time
Frequency
20
40
40
(3)
25
MHz
ns
tc(ADCCLK), Cycle time
Frequency
25
MHz
(1) This also applies to the X1 pin if a 1.8-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default reset value if SYSCLKOUT = 100 MHz.
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6.7 Clock Requirements and Characteristics
Table 6-5. Input Clock Frequency
PARAMETER
Resonator (X1/X2)
MIN
20
20
4
TYP MAX UNIT
35
Crystal (X1/X2)
35
MHz
150
fx
Input clock frequency
150-MHz device
100-MHz device
External oscillator/clock
source (XCLKIN or X1 pin)
4
100
fl
Limp mode SYSCLKOUT frequency range (with /2 enabled)
1 - 5
MHz
Table 6-6. XCLKIN Timing Requirements - PLL Enabled
NO.
C8
MIN
MAX UNIT
tc(CI)
tf(CI)
Cycle time, XCLKIN
Fall time, XCLKIN(1)
Rise time, XCLKIN(1)
33.3
200
6
ns
ns
ns
%
C9
C10 tr(CI)
6
(1)
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45
45
55
55
(1)
%
(1) This applies to the X1 pin also.
Table 6-7. XCLKIN Timing Requirements - PLL Disabled
NO.
MIN
6.67
10
MAX UNIT
C8
tc(CI)
Cycle time, XCLKIN
150-MHz device
100-MHz device
Up to 30 MHz
250
250
6
ns
C9
tf(CI)
Fall time, XCLKIN(1)
Rise time, XCLKIN(1)
ns
ns
ns
ns
%
30 MHz to 150 MHz
Up to 30 MHz
2
C10 tr(CI)
6
30 MHz to 150 MHz
2
(1)
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45
45
55
55
(1)
%
(1) This applies to the X1 pin also.
The possible configuration modes are shown in Table 3-16.
Table 6-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1) (2)
NO.
PARAMETER
Cycle time, XCLKOUT
MIN
6.67
10
TYP
MAX
UNIT
150-MHz device
100-MHz device
C1
tc(XCO)
ns
C3
C4
C5
C6
tf(XCO)
tr(XCO)
tw(XCOL)
tw(XCOH)
tp
Fall time, XCLKOUT
2
2
ns
ns
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
H – 2
H – 2
H + 2
ns
H + 2
ns
(3)
131072tc(OSCCLK)
cycles
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
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C10
C9
C8
(A)
XCLKIN
C6
C3
C1
C4
C5
(B)
XCLKOUT
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-6. Clock Timing
6.8 Power Sequencing
No requirements are placed on the power up/down sequence of the various power pins to ensure the
correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers
of the I/O pins are powered prior to the 1.9-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or
simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins
reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (see
Table 6-10). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 ms prior to VDD reaching 1.5 V. This is to
enhance flash reliability.
Additionally it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any
pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal
P-N junctions in unintended ways and produce unpredictable results.
6.8.1 Power Management and Supervisory Circuit Solutions
Table 6-9 lists the power management and supervisory circuit solutions for 2833x/2823x devices. LDO
selection depends on the total power consumed in the end application. Go to www.ti.com and click on
Power Management for a complete list of TI power ICs or select the Power Management Selection Guide
link for specific power reference designs.
Table 6-9. Power Management and Supervisory Circuit Solutions
SUPPLIER
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
TYPE
LDO
PART
DESCRIPTION
TPS767D301 Dual 1-A low-dropout regulator (LDO) with supply voltage supervisor (SVS)
LDO
TPS70202
TPS766xx
TPS3808
TPS3803
TPS799xx
TPS736xx
TPS62110
TPS6230x
Dual 500/250-mA LDO with SVS
LDO
250-mA LDO with PG
SVS
Open Drain SVS with programmable delay
Low-cost Open-drain SVS with 5 mS delay
200-mA LDO in WCSP package
SVS
LDO
LDO
400-mA LDO with 40 mV of VDO
DC/DC
DC/DC
High Vin 1.2-A dc/dc converter in 4x4 QFN package
500-mA converter in WCSP package
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V , V
DDIO DD3VFL
V , V
DDA2 DDAIO
(3.3 V)
V , V
DD DD1A18,
V
DD2A18
(1.9 V/1.8 V)
XCLKIN
X1/X2
(A)
OSCCLK/8
OSCCLK/16
XCLKOUT
User-Code Dependent
t
OSCST
t
w(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
(Internal)
User-Code Execution Phase
User-Code Dependent
t
d(EX)
(B)
h(boot-mode)
t
Boot-Mode
Pins
GPIO Pins as Input
Boot-ROM Execution Starts
Peripheral/GPIO Function
Based on Boot Code
(C)
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
I/O Pins
A. Upon power up, SYSCLKOUT is OSCCLK/4. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register
come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains
why XCLKOUT = OSCCLK/16 during this phase. Subsequently, boot ROM changes SYSCLKOUT to OSCCLK/2.
Because the XTIMCLK register is unchanged by the boot ROM, XCLKOUT is OSCCLK/8 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
C. See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up.
Figure 6-7. Power-on Reset
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Table 6-10. Reset (XRS) Timing Requirements
MIN
32tc(OSCCLK)
32tc(OSCCLK)
NOM
MAX
UNIT
cycles
cycles
(1)
tw(RSL1)
tw(RSL2)
Pulse duration, stable input clock to XRS high
Pulse duration, XRS low
Warm reset
Pulse duration, reset pulse generated by
watchdog
tw(WDRS)
512tc(OSCCLK)
cycles
td(EX)
tOSCST
th(boot-mode)
Delay time, address/data valid after XRS high
Oscillator start-up time
32tc(OSCCLK)
10
cycles
ms
(2)
1
Hold time for boot-mode pins
200tc(OSCCLK)
cycles
(1) In addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
(2) Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
XRS
User-Code Dependent
OSCCLK * 5
t
w(RSL2)
User-Code Execution Phase
t
d(EX)
Address/Data/
Control
(Don’t Care)
User-Code Execution
(Internal)
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-8. Warm Reset
Figure 6-9 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.
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OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(Changed CPU Frequency)
(PLL Lock-up Time, t ) is
p
131072 OSCCLK Cycles Long.)
Figure 6-9. Example of Effect of Writing Into PLLCR Register
6.9 General-Purpose Input/Output (GPIO)
6.9.1 GPIO - Output Timing
Table 6-11. General-Purpose Output Switching Characteristics
PARAMETER
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
MIN
MAX
8
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
All GPIOs
All GPIOs
8
ns
25
MHz
GPIO
t
r(GPO)
t
f(GPO)
Figure 6-10. General-Purpose Output Timing
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6.9.2 GPIO - Input Timing
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
t
Sampling Period determined
by GPxCTRL[QUALPRD]
w(SP)
(B)
t
w(IQSW)
(C)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
)
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
Figure 6-11. Sampling Mode
Table 6-12. General-Purpose Input Timing Requirements
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
tw(SP)
Sampling period
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
tw(SP) * (n(1) – 1)
2tc(SCO)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
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6.9.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
XCLKOUT
GPIOxn
t
w(GPI)
Figure 6-12. General-Purpose Input Timing
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6.9.4 Low-Power Mode Wakeup Timing
Table 6-13 shows the timing requirements, Table 6-14 shows the switching characteristics, and
Figure 6-13 shows the timing diagram for IDLE mode.
Table 6-13. IDLE Mode Timing Requirements(1)
MIN NOM
MAX
UNIT
Without input qualifier
With input qualifier
2tc(SCO)
5tc(SCO) + tw(IQSW)
Pulse duration, external wake-up
signal
tw(WAKE-INT)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-12 .
Table 6-14. IDLE Mode Switching Characteristics(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, external wake signal to
(2)
program execution resume
Wake-up from Flash
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20tc(SCO)
20tc(SCO) + tw(IQSW)
1050tc(SCO)
cycles
cycles
cycles
•
Flash module in active state
td(WAKE-IDLE)
Wake-up from Flash
•
•
Flash module in sleep state
Wake-up from SARAM
1050tc(SCO) + tw(IQSW)
20tc(SCO)
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-12 .
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
(A)
WAKE INT
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-13. IDLE Entry and Exit Timing
Table 6-15. STANDBY Mode Timing Requirements
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Without input qualification
With input qualification(1)
3tc(OSCCLK)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
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Table 6-16. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT low
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO)
cycles
Delay time, external wake
signal to program execution
resume(1)
td(WAKE-STBY)
cycles
cycles
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
1125tc(SCO)
•
Wake up from flash
–
Flash module in active
state
•
Wake up from flash
cycles
cycles
–
Flash module in sleep
state
1125tc(SCO) + tw(WAKE-INT)
Without input qualifier
With input qualifier
100tc(SCO)
•
Wake up from SARAM
100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
(A)
(C)
(E)
(D)
(B)
(F)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake−up
Signal
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is
in progress and its access time is longer than this number then it will fail.＝ It is recommended to enter STANDBY
mode from SARAM without an XINTF access in progress.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-14. STANDBY Entry and Exit Timing Diagram
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Table 6-17. HALT Mode Timing Requirements
MIN NOM
MAX
UNIT
cycles
cycles
(1)
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wakeup signal
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
(1) See Table 6-10 for an explanation of toscst
.
Table 6-18. HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
45tc(SCO)
UNIT
cycles
cycles
Delay time, IDLE instruction executed to XCLKOUT
low
td(IDLE-XCOL)
tp
32tc(SCO)
PLL lock-up time
131072tc(OSCCLK)
Delay time, PLL lock to program execution resume
1125tc(SCO)
35tc(SCO)
cycles
cycles
•
•
Wake up from flash
Flash module in sleep state
td(WAKE-HALT)
–
Wake up from SARAM
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(G)
(A)
(C)
(E)
(B)
(D)
HALT
(F)
Device
Status
HALT
Flushing Pipeline
PLL Lock-up Time
Normal
Execution
Wake-up Latency
GPIOn
X1/X2
t
d(WAKE−HALT)
t
w(WAKE-GPIO)
t
p
or XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before
oscillator is turned off and the CLKIN to the core is stopped:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in
progress and its access time is longer than this number then it will fail.＝ It is recommended to enter HALT mode from
SARAM without an XINTF access in progress.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin
asynchronously begins the wakeup process, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
E. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles. Note that these 131,072 clock cycles are applicable even when the PLL is disabled (i.e., code
execution will be delayed by this duration even when the PLL is disabled).
F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the
interrupt (if enabled), after a latency.
G. Normal operation resumes.
Figure 6-15. HALT Wake-Up Using GPIOn
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6.10 Enhanced Control Peripherals
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1-6. Table 6-19 shows the PWM timing requirements and
Table 6-20, switching characteristics.
Table 6-19. ePWM Timing Requirements(1)
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
tw(SYCIN)
Sync input pulse width
Synchronous
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-12 .
Table 6-20. ePWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
td(PWM)tza
8tc(SCO)
cycles
ns
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
no pin load
25
20
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
ns
6.10.2 Trip-Zone Input Timing
(A)
XCLKOUT
t
w(TZ)
TZ
t
d(TZ-PWM)HZ
(B)
PWM
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-16. PWM Hi-Z Characteristics
Table 6-21. Trip-Zone input Timing Requirements(1)
MIN
1tc(SCO)
MAX UNIT
cycles
tw(TZ)
Pulse duration, TZx input low
Asynchronous
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-12 .
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Table 6-22 shows the high-resolution PWM switching characteristics.
Table 6-22. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 150 MHz)
MIN
TYP
MAX UNIT
310 ps
Micro Edge Positioning (MEP) step size(1)
150
(1) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
Table 6-23 shows the eCAP timing requirement and Table 6-24 shows the eCAP switching characteristics.
Table 6-23. Enhanced Capture (eCAP) Timing Requirement(1)
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX UNIT
cycles
tw(CAP)
Capture input pulse width
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-12 .
Table 6-24. eCAP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
Table 6-25 shows the eQEP timing requirement and Table 6-26 shows the eQEP switching
characteristics.
Table 6-25. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements(1)
TEST CONDITIONS
Asynchronous/synchronous
With input qualifier
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
tw(QEPP)
QEP input period
2tc(SCO)
2(1tc(SCO) + tw(IQSW)
)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
Asynchronous/synchronous
With input qualifier
2tc(SCO)
2tc(SCO) +tw(IQSW)
2tc(SCO)
Asynchronous/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
Asynchronous/synchronous
With input qualifier
Asynchronous/synchronous
With input qualifier
2tc(SCO) +tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-12 .
Table 6-26. eQEP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
4tc(SCO)
6tc(SCO)
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync
output
Table 6-27. External ADC Start-of-Conversion Switching Characteristics
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCAL)
Pulse duration, ADCSOCAO low
32tc(HCO )
cycles
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t
w(ADCSOCAL)
ADCSOCAO
or
ADCSOCBO
Figure 6-17. ADCSOCAO or ADCSOCBO Timing
6.11 External Interrupt Timing
t
w(INT)
XNMI, XINT1, XINT2
t
d(INT)
Address bus
(internal)
Interrupt Vector
Figure 6-18. External Interrupt Timing
Table 6-28. External Interrupt Timing Requirements(1)
TEST CONDITIONS
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
(2)
tw(INT)
Pulse duration, INT input low/high
Synchronous
With qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-12 .
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 6-29. External Interrupt Switching Characteristics(1)
PARAMETER
MIN
MAX
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
tw(IQSW) + 12tc(SCO)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-12 .
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6.12 I2C Electrical Specification and Timing
Table 6-30. I2C Timing
TEST CONDITIONS
MIN
MAX
UNIT
fSCL
SCL clock frequency
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
400
kHz
vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
Vih
0.7 VDDIO
Vhys
Vol
0.05 VDDIO
V
Low level output voltage
Low period of SCL clock
3-mA sink current
0
0.4
V
tLOW
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3
ms
tHIGH
High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
-10
ms
lI
Input current with an input voltage
10
mA
between 0.1 VDDIO and 0.9 VDDIO MAX
6.13 Serial Peripheral Interface (SPI) Timing
This section contains both Master Mode and Slave Mode timing data.
6.13.1 Master Mode Timing
Table 6-31 lists the master mode timing (clock phase = 0) and Table 6-32 lists the timing (clock
phase = 1). Figure 6-19 and Figure 6-20 show the timing waveforms.
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UNIT
Table 6-31. SPI Master Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
MIN
4tc(LCO)
MAX
MIN
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
128tc(LCO)
0.5tc(SPC)M
5tc(LCO)
127tc(LCO)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M + 0.5tc(LCO)-10
0.5tc(SPC)M + 0.5tc(LCO)- 10
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
10
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M
0.5tc(SPC)M
10
3
4
5
8
9
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
tv(SPCL-SOMI)M
tv(SPCH-SOMI)M
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
10
10
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
35
0.5tc(SPC)M + 0.5tc(LCO) -10
0.5tc(SPC)M + 0.5tc(LCO) -10
35
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
ns
ns
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
35
35
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25tc(SPC)M -10
0.25tc(SPC)M - 10
0.5tc(SPC)M- 0.5tc(LCO)- 10
0.5tc(SPC)M- 0.5tc(LCO)- 10
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
4
3
SPICLK
(clock polarity = 1)
5
SPISIMO
SPISOMI
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-19. SPI Master Mode External Timing (Clock Phase = 0)
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UNIT
Table 6-32. SPI Master Mode External Timing (Clock Phase = 1)(1) (2) (3) (4) (5)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPI WHEN (SPIBRR + 1) IS ODD
SPIBRR = 0
OR 2
AND SPIBRR > 3
MIN
4tc(LCO)
MAX
128tc(LCO)
0.5tc(SPC)M
MIN
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
5tc(LCO)
127tc(LCO)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 0.5tc
(LCO)-10
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M - 0.5tc(LCO
0.5tc(SPC)M + 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCL))M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
35
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc
(LCO)-10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
6
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) -
10
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO)
-10
tsu(SIMO-SPCH)M
tsu(SIMO-SPCL)M
tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
Setup time, SPISIMO data valid before
SPICLK high (clock polarity = 0)
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M -10
35
Setup time, SPISIMO data valid before
SPICLK low (clock polarity = 1)
7
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
10
11
Setup time, SPISOMI before SPICLK high
(clock polarity = 0)
Setup time, SPISOMI before SPICLK low
(clock polarity = 1)
35
35
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
0.25tc(SPC)M -10
0.25tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
SPISOMI
Master Out Data Is Valid
10
Data Valid
11
Master In Data Must
Be Valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-20. SPI Master Mode External Timing (Clock Phase = 1)
6.13.2 SPI Slave Mode Timing
Table 6-33 lists the slave mode external timing (clock phase = 0) and Table 6-34 (clock phase = 1). Figure 6-21 and Figure 6-22 show the timing
waveforms.
Table 6-33. SPI Slave Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5)
NO.
MIN
MAX
UNIT
12
tc(SPC)S
Cycle time, SPICLK
4tc(LCO)
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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(1) (2) (3) (4) (5)
Table 6-33. SPI Slave Mode External Timing (Clock Phase = 0)
(continued)
NO.
MIN
MAX
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
35
UNIT
ns
13
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
tw(SPCL)S
ns
14
15
16
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
ns
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
ns
td(SPCH-SOMI)S
td(SPCL-SOMI)S
tv(SPCL-SOMI)S
ns
35
ns
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
0.75tc(SPC)S
0.75tc(SPC)S
ns
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
ns
19
20
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
tv(SPCL-SIMO)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
35
35
ns
ns
ns
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5tc(SPC)S-10
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5tc(SPC)S-10
ns
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12
SPICLK
(clock polarity = 0)
13
15
14
SPICLK
(clock polarity = 1)
16
SPISOMI
SPISIMO
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
(A)
SPISTE
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-21. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-34. SPI Slave Mode External Timing (Clock Phase = 1)(1) (2) (3) (4)
NO.
MIN
8tc(LCO)
MAX UNIT
12 tc(SPC)S
13 tw(SPCH)S
tw(SPCL)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.125tc(SPC)S
0.125tc(SPC)S
0.75tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC) S
0.5tc(SPC) S
0.5tc(SPC)S
14 tw(SPCL)S
tw(SPCH)S
17 tsu(SOMI-SPCH)S
tsu(SOMI-SPCL)S
18 tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
0.75tc(SPC) S
ns
21 tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
35
35
ns
ns
ns
22 tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S-10
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)S-10
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
SPISIMO
SPISOMI Data Is Valid
21
Data Valid
22
SPISIMO Data
Must Be Valid
(A)
SPISTE
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-22. SPI Slave Mode External Timing (Clock Phase = 1)
6.14 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone. Table 6-35 shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-35. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DESCRIPTION
DURATION (ns)(1) (2)
X2TIMING = 0
X2TIMING = 1
LR
Lead period, read access
Active period, read access
Trail period, read access
Lead period, write access
Active period, write access
Trail period, write access
XRDLEAD × tc(XTIM)
(XRDLEAD × 2) × tc(XTIM)
AR
TR
LW
AW
TW
(XRDACTIVE + WS + 1) × tc(XTIM)
XRDTRAIL × tc(XTIM)
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
(XWRACTIVE + WS + 1) × tc(XTIM)
XWRTRAIL × tc(XTIM)
(XWRACTIVE × 2 + WS + 1) × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
(1)
tc(XTIM) − Cycle time, XTIMCLK
(2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No
internal device hardware is included to detect illegal settings.
6.14.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
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Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 0
≥ 0
≥ 1
≥ 0
≥ 0
0, 1
Examples of valid and invalid timing when not sampling XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid(1)
Valid
0
1
0
0
0
0
0
1
0
0
0
0
0, 1
(1) No hardware to detect illegal XTIMING configurations
6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1
Lead:
LR ≥ × tc(XTIM)
LW ≥ tc(XTIM)
2
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
NOTE
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 1
≥ 0
≥ 1
≥ 1
≥ 0
0, 1
Examples of valid and invalid timing when using synchronous XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid(1)
Invalid(1)
Valid
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0, 1
0, 1
(1) No hardware to detect illegal XTIMING configurations
6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1
2
3
Lead:
LR ≥ × tc(XTIM)
LW ≥ tc(XTIM)
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
Lead +
Active:
LR + AR ≥ 4 ×
tc(XTIM)
LW + AW ≥ 4 ×
tc(XTIM)
NOTE
Restrictions do not include external hardware wait states.
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These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 2
0
≥ 1
≥ 2
0
0, 1
or
XRDLEAD
≥ 2
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
0
≥ 2
≥ 1
0
0, 1
Examples of valid and invalid timing when using asynchronous XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid(1)
Invalid(1)
Invalid(1)
Valid
0
1
1
1
1
2
0
0
1
1
2
1
0
0
0
0
0
0
0
1
1
1
1
2
0
0
1
1
2
1
0
0
0
0
0
0
0, 1
0, 1
0
1
Valid
0, 1
0, 1
Valid
(1) No hardware to detect illegal XTIMING configurations
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-36.
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Table 6-36. XINTF Clock Configurations
MODE
SYSCLKOUT
150 MHz
XTIMCLK
SYSCLKOUT
150 MHz
XCLKOUT
SYSCLKOUT
150 MHz
1
Example:
2
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
Example:
3
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
Example:
4
150 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
Example:
150 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6-23 .
PCLKR3[XINTFENCLK]
XTIMING0
LEAD/ACTIVE/TRAIL
XTIMING6
XTIMING7
XBANK
0
0
1
SYSCLKOUT
C28x
CPU
XTIMCLK
/2
1
0
XCLKOUT
/2
1
0
XINTCNF2 (XTIMCLK)
XINTCNF2
(CLKMODE)
XINTCNF2
(CLKOFF)
Figure 6-23. Relationship Between XTIMCLK and SYSCLKOUT
6.14.4 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock
XTIMCLK. Strobes such as XRD, XWE0, XWE1, and zone chip-select (XZCS) change state in relationship
to the rising edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or
one-half the frequency of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the
rising edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes will change
state either on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables,
the notation XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising
edge (high) or XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of
XCLKOUT, the notation XCOH is used.
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be
aligned can be determined based on the number of XTIMCLK cycles from the start of the access to the
point at which the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with
respect to the rising edge of XCLKOUT. If this number is odd, then the signal will change with respect to
the falling edge of XCLKOUT. Examples include the following:
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•
•
Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
XZCSL
Zone chip-select active low
XR/W active low
XRNWL
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if
the total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK
cycles is odd, then the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
XRDL
XWEL
XRD active low
XWE1 or XWE0 active low
•
•
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the
total number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If
the number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment
will be with respect to the falling edge of XCLKOUT.
Examples:
XRDH
XWEH
XRD inactive high
XWE1 or XWE0 inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total
number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive high
XR/W inactive high
XRNWH
6.14.5 External Interface Read Timing
Table 6-37. External Interface Read Timing Requirements
MIN
Access time, read data from address valid
MAX
UNIT
ns
(1)
ta(A)
(LR + AR) –16
(1)
ta(XRD)
Access time, read data valid from XRD active low
AR –14
ns
tsu(XD)XRD
th(XD)XRD
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
14
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-35 .
Table 6-38. External Interface Read Switching Characteristics
PARAMETER
MIN
MAX
1
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
–1
0.5
1.5
0.5
0.5
ns
ns
td(XCOHL-XRDL)
td(XCOHL-XRDH
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
ns
–1.5
(1)
ns
ns
(1)
th(XA)XRD
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
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Trail
(A)(B)
(C)
Active
Lead
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0, XZCS6, XZCS7
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
XA[0:19]
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
XWE0, XWE1(D)
XR/W
t
su(XD)XRD
t
a(A)
t
h(XD)XRD
t
a(XRD)
XD[0:31], XD[0:15]
XREADY(E)
DIN
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-24. Example Read Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 1
≥ 0
≥ 0
0
0
N/A(1)
N/A(1)
N/A(1)
N/A(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
6.14.6 External Interface Write Timing
Table 6-39. External Interface Write Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1 (1) low
Delay time, XCLKOUT high/low to XWE0, XWE1 high
Delay time, XCLKOUT high to XR/W low
1
0.5
1.5
2
–1
ns
ns
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
ns
2
ns
1
ns
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE0, XWE1 low
Delay time, data valid after XWE0, XWE1 active low
Hold time, address valid after zone chip-select inactive high
- 1
0
0.5
ns
ns
td(XWEL-XD)
1
ns
(2)
(3)
th(XA)XZCSH
ns
th(XD)XWE
Hold time, write data valid after XWE0, XWE1 inactive high
TW-2
ns
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit mode, this signal is XA0.
(2) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.
This includes alignment cycles.
(3) TW = Trail period, write access. See Table 6-35 .
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Table 6-39. External Interface Write Switching Characteristics (continued)
PARAMETER
MIN
MAX
UNIT
tdis(XD)XRNW
Maximum time for DSP to release the data bus after XR/W inactive high
4
ns
Active
(A) (B)
(C)
Lead
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
d(XCOHL-XZCSH)
t
d(XCOH-XZCSL)
XZCS0, XZCS6, XZCS7
t
d(XCOH-XA)
XA[0:19]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE0, XWE1(D)
XR/W
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
t
t
dis(XD)XRNW
d(XWEL-XD)
t
t
en(XD)XWEL
h(XD)XWEH
XD[0:31], XD[0:15]
XREADY(E)
DOUT
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-25. Example Write Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
0
0
≥ 1
≥ 0
≥ 0
N/A(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
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6.14.7 External Interface Ready-on-Read Timing With One External Wait State
Table 6-40. External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MIN
MAX
1
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive
high
- 1
0.5
ns
td(XCOH-XA)
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
th(XA)XRD
Delay time, XCLKOUT high to address valid
1.5
0.5
0.5
ns
ns
ns
ns
ns
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
- 1.5
(1)
(1)
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus, except XA0, which remains high. This
includes alignment cycles.
Table 6-41. External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
ns
(1)
ta(A)
Access time, read data from address valid
(LR + AR) - 16
(1)
ta(XRD)
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
AR - 14
ns
tsu(XD)XRD
th(XD)XRD
14
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-35 .
Table 6-42. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)(1)
MIN
12
6
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
ns
te(XRDYsynchH)
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
3
ns
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
12
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-26 :
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will finish. If XREADY (synchronous) is found to be
low, it is sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-43. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
11
6
MAX
UNIT
ns
tsu(XRDYAsynchL)XCOHL
th(XRDYAsynchL)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
ns
te(XRDYAsynchH)
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
3
ns
tsu(XRDYAsynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
11
0
ns
ns
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WS (Synch)
(C)
(A) (B)
Active
Lead
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
XZCS0 XZCS6, XZCS7
t
d(XCOH-XA)
XA[0:19]
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
t
su(XD)XRD
(D)
XWE0, XWE1
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
XD[0:31], XD[0:15]
DIN
t
su(XRDYsynchL)XCOHL
t
e(XRDYsynchH)
t
h(XRDYsynchL)
t
h(XRDYsynchH)XZCSH
t
su(XRDHsynchH)XCOHL
XREADY(Synch)
Legend:
(E)
(F)
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For each sample, setup time from the beginning of the access (E) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n - 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
F. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE) tc(XTIM) where n is the
sample number: n = 1, 2, 3, and so forth.
Figure 6-26. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 1
3
≥ 1
1
0
N/A(1)
N/A(1)
N/A(1)
0 = XREADY
(Synch)
(1) N/A = “Don’t care” for this example
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WS (Async)
Active
(A) (B)
Lead
Trail
(C)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0, XZCS6, XZCS7
t
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
d(XCOH-XA)
XA[0:19]
XRD
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
t
su(XD)XRD
(D)
XWE0, XWE1
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
DIN
XD[0:31], XD[0:15]
t
su(XRDYasynchL)XCOHL
t
e(XRDYasynchH)
t
h(XRDYasynchH)XZCSH
t
h(XRDYasynchL)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For each sample, setup time from the beginning of the access can be calculated as:
E = (XRDLEAD + XRDACTIVE -3 +n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and
so forth.
F. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) tc(XTIM)
Figure 6-27. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 1
3
≥ 1
1
0
N/A(1)
N/A(1)
N/A(1)
1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
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6.14.8 External Interface Ready-on-Write Timing With One External Wait State
Table 6-44. External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
MIN
MAX
1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1 low(1)
Delay time, XCLKOUT high/low to XWE0, XWE1 high(1)
Delay time, XCLKOUT high to XR/W low
– 1
0.5
1.5
2
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
2
1
Delay time, XCLKOUT high/low to XR/W high
– 1
0
0.5
Enable time, data bus driven from XWE0, XWE1 low(1)
Delay time, data valid after XWE0, XWE1 active low(1)
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high(1)
Maximum time for DSP to release the data bus after XR/W inactive high
td(XWEL-XD)
1
(2)
(3)
th(XA)XZCSH
th(XD)XWE
TW-2
tdis(XD)XRNW
4
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
(3) TW = trail period, write access (see Table 6-35 )
Table 6-45. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1)
MIN
12
6
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
ns
te(XRDYsynchH)
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
3
ns
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
12
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-28 :
E =(XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is high, then the access will complete. If XREADY (synchronous) is low, it is sampled
again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE +n –1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-46. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1)
MIN
11
6
MAX UNIT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
ns
ns
te(XRDYasynchH)
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
3
ns
tsu(XRDYasynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
11
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-28 :
E = (XWRLEAD + XWRACTIVE –2) tc(XTIM). When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
XREADY (asynchronous) is low, it is sampled again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
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WS (Synch)
Active
(A) (B)
(C)
Trail
Lead 1
(D)
XCLKOUT = XTIMCLK
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
t
t
h(XRDYsynchH)XZCSH
d(XCOH-XA)
XA[0:18]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
)
t
h(XD)XWEH
t
en(XD)XWEL
XD[0:15]
DOUT
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
su(XRDHsynchH)XCOHL
XREADY(Synch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0
E. For each sample, setup time from the beginning of the access can be calculated as E = (XWRLEAD + XWRACTIVE +
n –1) tc(XTIM) – tsu(XRDYsynchL)XCOH where n is the sample number: n = 1, 2, 3, and so forth.
F. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 6-28. Write With Synchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
1
0
≥ 1
3
≥ 1
0 = XREADY
(Synch)
(1) N/A = "Don't care" for this example.
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WS (Async)
Active
(A) (B)
(C)
Trail
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
t
h(XRDYasynchH)XZCSH
t
d(XCOH-XA)
XA[0:19]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
(D)
XWE0, XWE1
t
t
d(XCOH-XRNWL)
d(XCOHL-XRNWH)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
)
t
h(XD)XWEH
t
en(XD)XWEL
XD[31:0], XD[15:0]
DOUT
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
e(XRDYasynchH)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
(D)
(E)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
E. For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE
-3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
F. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
Figure 6-29. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
1
0
≥ 1
3
≥ 1
1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
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6.14.9 XHOLD and XHOLDA Timing
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the
bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active
low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still
execute code from internal memory. If an access is made to the external interface, the CPU is stalled until
the XHOLD signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[19:0]
XZCS0
XD[31:0], XD[15:0] XZCS6
XWE0, XWE1,
XRD
XZCS7
XR/W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
(1) (2)
Table 6-47. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
MIN
MAX
UNIT
ns
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
td(HL-HAL)
Delay time, XHOLD low to Hi-Z on all address, data, and control
Delay time, XHOLD low to XHOLDA low
4tc(XTIM) + 30 ns
5tc(XTIM)+ 30 ns
ns
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to bus valid
3tc(XTIM)+ 30 ns
ns
4tc(XTIM)+ 30 ns
ns
Delay time, XHOLD low to XHOLDA low
4tc(XTIM + 2tc(XCO) + 30 ns
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
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XCLKOUT
(/1 Mode)
t
d(HL-Hiz)
XHOLD
t
d(HH-HAH)
XHOLDA
t
d(HL-HAL)
t
d(HH-BV)
XR/W
High-Impedance
XZCS0, XZCS6, XZCS7
Valid
XA[19:0]
Valid
High-Impedance
XD[31:0], XD[15:0]
Valid
(A)
(B)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-30. External Interface Hold Waveform
Table 6-48. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)(1) (2) (3)
MIN
MAX
UNIT
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all address, data, and
control
4tc(XTIM) + tc(XCO) + 30 ns
ns
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to bus valid
4tc(XTIM + 2tc(XCO) + 30 ns
4tc(XTIM) + 30 ns
ns
ns
ns
6tc(XTIM) + 30 ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT.
Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value
specified.
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XCLKOUT
(1/2 XTIMCLK)
XHOLD
t
d(HL-HAL)
t
d(HH-HAH)
XHOLDA
t
d(HL-HiZ)
t
d(HH-BV)
XR/W,
XZCS0,
XZCS6,
XZCS7
High-Impedance
High-Impedance
High-Impedance
Valid
XA[19:0]
Valid
XD[0:31]XD[15:0]
Valid
(B)
(A)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-31. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
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6.15 On-Chip Analog-to-Digital Converter
Table 6-49. ADC Electrical Characteristics (over recommended operating conditions)(1) (2)
PARAMETER
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS(3)
Resolution
12
Bits
ADC clock
0.001
25
MHz
ACCURACY
INL (Integral nonlinearity)
1-12.5 MHz ADC clock (6.25 MSPS)
±1.5
±2
LSB
LSB
12.5-25 MHz ADC clock
(12.5 MSPS)
DNL (Differential nonlinearity)(4)
±1
LSB
LSB
LSB
LSB
LSB
LSB
(5) (3)
Offset error
±15
±30
±30
±4
(6) (3)
(3)
Overall gain error with internal reference
Overall gain error with external reference
Channel-to-channel offset variation
Channel-to-channel gain variation
ANALOG INPUT
±4
(7)
Analog input voltage (ADCINx to ADCLO)
ADCLO
0
3
5
V
–5
0
mV
pF
mA
Input capacitance
10
Input leakage current
±5
(6)
INTERNAL VOLTAGE REFERENCE
VADCREFP - ADCREFP output voltage at the pin based on
internal reference
1.275
0.525
V
V
VADCREFM - ADCREFM output voltage at the pin based on
internal reference
Voltage difference, ADCREFP - ADCREFM
0.75
50
V
Temperature coefficient
PPM/°C
EXTERNAL VOLTAGE REFERENCE(6) (8)
ADCREFSEL[15:14] = 11b
ADCREFSEL[15:14] = 10b
ADCREFSEL[15:14] = 01b
1.024
1.500
2.048
V
V
V
VADCREFIN - External reference voltage input on ADCREFIN
pin 0.2% or better accurate reference recommended
AC SPECIFICATIONS
SINAD (100 kHz) Signal-to-noise ratio + distortion
SNR (100 kHz) Signal-to-noise ratio
THD (100 kHz) Total harmonic distortion
ENOB (100 kHz) Effective number of bits
SFDR (100 kHz) Spurious free dynamic range
67.5
68
dB
dB
–79
10.9
83
dB
Bits
dB
(1) Tested at 25 MHz ADCCLK.
(2) All voltages listed in this table are with respect to VSSA2
.
(3) ADC parameters for gain error and offset error are only specified if the ADC calibration routine is executed from the Boot ROM. See
Section 4.7.3 for more information.
(4) TI specifies that the ADC will have no missing codes.
(5) 1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
(6) A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal reference
is inclusive of the movement of the internal bandgap over temperature. Gain error over temperature for the external reference option will
depend on the temperature profile of the source used.
(7) Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
(8) TI recommends using high precision external reference TI part REF3020/3120 or equivalent for 2.048-V reference.
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6.15.1 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
PWDNADC
t
d(BGR)
t
d(PWD)
Request for
ADC
Conversion
Figure 6-32. ADC Power-Up Control Bit Timing
Table 6-50. ADC Power-Up Delays
PARAMETER(1)
MIN
TYP
MAX
UNIT
td(BGR)
td(PWD)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
5
ms
Delay time for power-down control to be stable. Bit delay time for band-gap
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
register (PWDNADC)must be set to 1 before any ADC conversions are initiated.
20
50
ms
1
ms
(1) Timings maintain compatibility to the 281x ADC module. The 2833x/2823x ADC also supports driving all 3 bits at the same time and
waiting td(BGR) ms before first conversion.
Table 6-51. Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)(1) (2)
ADC OPERATING MODE
CONDITIONS
BG and REF enabled
VDDA18
VDDA3.3
UNIT
Mode A (Operational Mode):
30
2
mA
•
•
PWD disabled
Mode B:
Mode C:
Mode D:
9
5
5
0.5
20
15
mA
mA
mA
•
•
•
ADC clock enabled
BG and REF enabled
PWD enabled
•
•
•
ADC clock enabled
BG and REF disabled
PWD enabled
•
•
•
ADC clock disabled
BG and REF disabled
PWD enabled
(1) Test Conditions:
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
(2) VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO
.
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R
1 kΩ
on
Switch
R
s
ADCIN0
C
10 pF
C
h
1.64 pF
p
Source
Signal
ac
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (R ):
1 kΩ
1.64 pF
on
Sampling Capacitor (C ):
h
Parasitic Capacitance (C ): 10 pF
p
Source Resistance (R ):
50 Ω
s
Figure 6-33. ADC Analog Input Impedance Model
6.15.2 Definitions
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at
a time. These inputs are software-selectable.
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with
low power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:
•
•
Sequential sampling mode (SMODE = 0)
Simultaneous sampling mode (SMODE = 1)
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6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an
external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on
every Sample/Hold pulse. The conversion time and latency of the Result register update are explained
below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The
selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Sample n
Channel Ax or Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschx_n+1
t
dschx_n
ADC Event Trigger from
ePWM or Other Sources
t
SH
Figure 6-34. Sequential Sampling Mode (Single-Channel) Timing
Table 6-52. Sequential Sampling Mode Timing
AT 25 MHz
SAMPLE n
SAMPLE n + 1
ADC CLOCK,
REMARKS
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event trigger to
2.5tc(ADCCLK)
sampling
tSH
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
40 ns with Acqps = 0 Acqps value = 0-15
ADCTRL1[8:11]
td(schx_n)
td(schx_n+1)
Delay time for first result to appear
in Result register
4tc(ADCCLK)
160 ns
Delay time for successive results to
appear in Result register
(2 + Acqps) *
tc(ADCCLK)
80 ns
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6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or
from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register
update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold
pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC
clocks wide (maximum).
NOTE
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, etc.).
Sample n
Sample n+2
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschA0_n+1
t
SH
ADC Event Trigger from
ePWM or Other Sources
t
t
dschA0_n
dschB0_n+1
t
dschB0_n
Figure 6-35. Simultaneous Sampling Mode Timing
Table 6-53. Simultaneous Sampling Mode Timing
AT 25 MHz
SAMPLE n
SAMPLE n + 1
ADC CLOCK,
REMARKS
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event trigger to
2.5tc(ADCCLK)
sampling
tSH
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
40 ns with Acqps = 0 Acqps value = 0-15
ADCTRL1[8:11]
td(schA0_n)
td(schB0_n )
Delay time for first result to
appear in Result register
4tc(ADCCLK)
160 ns
200 ns
120 ns
120 ns
Delay time for first result to
appear in Result register
5tc(ADCCLK)
td(schA0_n+1) Delay time for successive results
to appear in Result register
(3 + Acqps) * tc(ADCCLK)
(3 + Acqps) * tc(ADCCLK)
td(schB0_n+1 ) Delay time for successive results
to appear in Result register
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6.15.5 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is
defined as level one-half LSB beyond the last code transition. The deviation is measured from the center
of each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(
)
SINAD * 1.76
N +
6.02
it is possible to get a measure of performance expressed as N, the effective number
of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be
calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
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6.16 Multichannel Buffered Serial Port (McBSP) Timing
6.16.1 McBSP Transmit and Receive Timing
Table 6-54. McBSP Timing Requirements(1) (2)
NO.
MIN
MAX UNIT
McBSP module clock (CLKG, CLKX, CLKR) range
1
kHz
25(3)
MHz
ns
McBSP module cycle time (CLKG, CLKX, CLKR)
range
40
1
ms
ns
M11
M12
M13
M14
M15
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
2P
tw(CKRX)
tr(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
P – 7
ns
7
7
ns
tf(CKRX)
Fall time, CLKR/X
ns
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
18
2
ns
M16
M17
M18
M19
M20
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
0
ns
ns
ns
ns
ns
6
18
2
0
6
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
18
2
CLKX ext
CLKX int
0
CLKX ext
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
CLKSRG
(1 ) CLKGDV)
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =
CLKSRG can be LSPCLK, CLKX,
CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (25 MHz).
Table 6-55. McBSP Switching Characteristics(1) (2)
NO.
M1
M2
M3
M4
PARAMETER
Cycle time, CLKR/X
MIN
MAX UNIT
tc(CKRX)
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
2P
D-5(3)
C-5(3)
ns
tw(CKRXH)
tw(CKRXL)
td(CKRH-FRV)
Pulse duration, CLKR/X high
D+5(3)
C+5(3)
ns
ns
ns
Pulse duration, CLKR/X low
Delay time, CLKR high to internal FSR valid
0
3
0
3
4
27
4
M5
M6
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
ns
ns
CLKX ext
CLKX int
27
8
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
CLKX ext
14
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C=CLKRX low pulse width = P
D=CLKRX high pulse width = P
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(1) (2)
Table 6-55. McBSP Switching Characteristics
(continued)
PARAMETER
MIN
MAX UNIT
M7
td(CKXH-DXV)
Delay time, CLKX high to DX valid.
CLKX int
9
28
ns
This applies to all bits except the first bit transmitted.
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
Delay time, CLKX high to DX valid
DXENA = 0
8
14
Only applies to first bit transmitted when DXENA = 1
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
P + 8
P + 14
M8
ten(CKXH-DX)
Enable time, CLKX high to DX driven
DXENA = 0
CLKX int
CLKX ext
CLKX int
CLKX ext
0
6
ns
Only applies to first bit transmitted when DXENA = 1
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
P
P + 6
M9
td(FXH-DXV)
Delay time, FSX high to DX valid
DXENA = 0
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
8
14
ns
ns
Only applies to first bit transmitted when DXENA = 1
in Data Delay 0 (XDATDLY=00b) mode.
P + 8
P + 14
M10
ten(FXH-DX)
Enable time, FSX high to DX driven
DXENA = 0
0
6
Only applies to first bit transmitted when DXENA = 1
in Data Delay 0 (XDATDLY=00b) mode
P
P + 6
M1, M11
M2, M12
M3, M12
M13
CLKR
FSR (int)
FSR (ext)
M4
M4
M14
M15
M16
M18
M17
DR
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
(n−3)
(n−2)
(RDATDLY=00b)
M18
DR
Bit (n−1)
(RDATDLY=01b)
M17
M18
DR
Bit (n−1)
(RDATDLY=10b)
Figure 6-36. McBSP Receive Timing
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M1, M11
M2, M12
M13
M3, M12
CLKX
FSX (int)
FSX (ext)
M5
M5
M19
M20
M9
M7
M7
M10
Bit 0
DX
Bit (n−1)
(n−2)
(n−3)
(n−2)
(XDATDLY=00b)
M8
DX
Bit (n−1)
M8
Bit 0
M6
(XDATDLY=01b)
M7
DX
Bit 0
Bit (n−1)
(XDATDLY=10b)
Figure 6-37. McBSP Transmit Timing
6.16.2 McBSP as SPI Master or Slave Timing
Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
NO.
MASTER
SLAVE
MIN MAX
UNIT
MIN
30
1
MAX
M30
M31
M32
M33
tsu(DRV-CKXL)
th(CKXL-DRV)
tsu(BFXL-CKXH)
tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P –10
8P + 10
16P
2P(1)
(1) 2P = 1/CLKG
Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
NO.
PARAMETER
MASTER
SLAVE
MIN MAX
UNIT
MIN
2P(1)
P
MAX
M24
M25
M28
th(CKXL-FXL)
td(FXL-CKXH)
tdis(FXH-DXHZ)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
ns
ns
ns
Disable time, DX high impedance following last data bit from
FSX high
6
6P + 6
4P + 6
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
ns
(1) 2P = 1/CLKG
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For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by
setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will
be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
M33
M32
MSB
LSB
CLKX
FSX
M25
M24
M28
M29
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M30
M31
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6-38. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
NO.
MASTER
SLAVE
UNIT
MIN
30
1
MAX
MIN MAX
M39
M40
M41
M42
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXH)
tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(1)
(1) 2P = 1/CLKG
Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
NO.
PARAMETER
MASTER
MIN
SLAVE
MIN
UNIT
MAX
MAX
M34
M35
M37
th(CKXL-FXL)
td(FXL-CKXH)
tdis(CKXL-DXHZ)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
P
2P(1)
ns
ns
ns
Disable time, DX high impedance following last data bit
from CLKX low
P + 6
7P + 6
4P + 6
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
6
ns
(1) 2P = 1/CLKG
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For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With a maximum LSPCLK speed of 75 MHz, CLKX maximum
frequency is LSPCLK/16; that is, 4.6875 MHz and P =13.3 ns.
M42
MSB
LSB
M41
CLKX
FSX
DX
M35
M34
M37
M38
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
M39
M40
(n-2)
DR
Bit 0
(n-3)
(n-4)
Figure 6-39. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Table 6-60. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
NO.
MASTER
SLAVE
MIN
MIN
30
1
MAX
MAX UNIT
M49
M50
M51
M52
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXL)
tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P –10
ns
ns
ns
ns
8P –10
8P + 10
16P
2P(1)
(1) 2P = 1/CLKG
Table 6-61. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
NO.
PARAMETER
MASTER
SLAVE
MIN
MIN
2P(1)
P
MAX
MAX UNIT
M43
M44
M47
th(CKXH-FXL)
td(FXL-CKXL)
tdis(FXH-DXHZ)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
ns
Disable time, DX high impedance following last data bit from
FSX high
6
6P + 6
4P + 6
M48
td(FXL-DXV)
Delay time, FSX low to DX valid
6
ns
(1) 2P = 1/CLKG
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For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency
will be LSPCLK/16; that is, 4.6875 MHz and P = 13.3 ns.
M52
M51
MSB
LSB
CLKX
FSX
M43
M44
M48
M47
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
M50
(n-3)
(n-4)
M49
Bit 0
(n-2)
(n-3)
(n-4)
Figure 6-40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Table 6-62. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
NO.
MASTER
SLAVE
MIN MAX
UNIT
MIN
30
1
MAX
M58 tsu(DRV-CKXL)
M59 th(CKXL-DRV)
M60 tsu(FXL-CKXL)
M61 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(1)
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency
is LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-63. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1)
NO.
PARAMETER
MASTER(2)
SLAVE
MIN MAX
UNIT
MIN
P
MAX
M53
M54
M56
th(CKXH-FXL)
td(FXL-CKXL)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
ns
2P(1)
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
P + 6
7P + 6
4P + 6
M57
td(FXL-DXV)
Delay time, FSX low to DX valid
6
ns
(1) 2P = 1/CLKG
(2) C = CLKX low pulse width = P
D = CLKX high pulse width = P
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M61
M60
MSB
M54
LSB
CLKX
M53
FSX
M56
M55
M57
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M58
M59
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6-41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
6.17 Flash Timing
Table 6-64. Flash Endurance for A and S Temperature Material(1)
MIN
TYP
MAX
UNIT
cycles
write
Nf
Flash endurance for the array (write/erase cycles)
0°C to 85°C (ambient)
0°C to 85°C (ambient)
100
1000
NOTP OTP endurance for the array (write cycles)
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 6-65. Flash Endurance for Q Temperature Material(1)
MIN
TYP
MAX
UNIT
cycles
write
Nf
Flash endurance for the array (write/erase cycles)
– 40°C to 125°C (ambient)
– 40°C to 125°C (ambient)
100
1000
NOTP OTP endurance for the array (write cycles)
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 6-66. Flash Parameters at 150-MHz SYSCLKOUT
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
Program Time 16-Bit Word
32K Sector
50
1000
500
11
ms
ms
ms
s
16K Sector
Erase Time
32K Sector
16K Sector
11
s
(1)
IDD3VFLP
VDD3VFL current consumption during the Erase/Program Erase
cycle
75
mA
mA
mA
mA
Program
35
(1)
IDDP
VDD current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
180
20
(1)
IDDIOP
(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off.
Table 6-67. Flash/OTP Access Timing
PARAMETER
MIN
37
MAX
UNIT
ta(fp)
Paged Flash access time
Random Flash access time
OTP access time
ns
ns
ns
ta(fr)
37
ta(OTP)
60
160
Electrical Specifications
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Table 6-68. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
PAGE WAIT-STATE
RANDOM
OTP WAIT-STATE
WAIT-STATE(1)
150
120
100
75
6.67
8.33
10
5
4
3
2
1
1
1
1
1
5
4
3
2
1
1
1
1
1
8
7
5
4
2
1
1
1
1
13.33
20
50
30
33.33
40
25
15
66.67
250
4
(1) Page and random wait-state must be ≥ 1.
Equations to compute the Flash page wait-state and random wait-state in Table 6-68 are as follows:
é
ù
ú
æ
ö
÷
÷
÷
÷
ø
t
êç
êç
êç
a fp
( )
ú
Flash Page Wait State =
-1 round up to the next highest integer), or 1whichever is larger
t
ú
ç
ê
c SCO
(
ú
)
è
ë
û
é
ù
ú
æ
ö
÷
÷
÷
÷
ø
t
êç
êç
êç
a fr
( )
ú
Flash Random Wait State =
-1 round up to the next highest integer), or 1whichever is larger
t
ú
ç
ê
c SCO
(
ú
)
è
ë
û
Equation to compute the OTP wait-state in Table 6-68 is as follows:
é
ù
ú
æ
ö
÷
÷
÷
÷
ø
t
êç
êç
êç
a OTP
(
)
)
ú
OTP Wait State =
-1 round up to the next highest integer), or 1whichever is larger
t
ú
ç
ê
c SCO
(
ú
è
ë
û
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7
Thermal/Mechanical Data
Table 7-1, Table 7-2, and Table 7-3 show the thermal data. See Section 6.4.3 for more information on
thermal design considerations.
The mechanical package diagram(s) that follow the tables reflect the most current released mechanical
data available for the designated device(s).
Table 7-1. Thermal Model 176-pin PGF Results
AIR FLOW
PARAMETER
0 lfm
44
150 lfm
34.5
250 lfm
33
500 lfm
31
qJA[°C/W] High k PCB
ΨJT[°C/W]
ΨJB
0.12
28.1
8.2
0.48
0.57
25.9
0.74
25.2
26.3
qJC
qJB
28.1
Table 7-2. Thermal Model 179-pin GHH Results
AIR FLOW
PARAMETER
0 lfm
32.8
0.09
12.4
8.8
150 lfm
24.1
250 lfm
22.9
500 lfm
20.9
qJA[°C/W] High k PCB
ΨJT[°C/W]
ΨJB
0.3
0.36
0.48
11.8
11.7
11.5
qJC
qJB
12.5
Table 7-3. Thermal Model 176-pin GJZ Results
AIR FLOW
PARAMETER
0 lfm
29.6
0.2
150 lfm
20.9
250 lfm
19.7
500 lfm
18
qJA[°C/W] High k PCB
ΨJT[°C/W]
ΨJB
0.78
0.91
1.11
11.3
12.2
11.4
12
11.6
11.5
qJC
qJB
162
Thermal/Mechanical Data
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Table 7-4. Thermal Model 176-pin PTP Results
AIR FLOW
(m/s)(5)
NO.
°C/W(1)
°C/W(2)
°C/W(3) °C/W(4)
1
2
RqJC
Junction-to-case
Junction-to-board
Junction-to-free air
7.8
6.2
21.3
14.3
13.1
12.1
11.2
0.5
0.6
0.7
0.8
1
9.4
9.9
27.9
20.2
18.6
17.4
16.2
0.7
0.9
1
8.6
7.1
10.1
10.6
30.6
22.6
21
N/A
N/A
0
RqJB
RqJA
3
23.2
4
0.5
1
5
RqJMA
Junction-to-moving air
6
19.6
18.2
0.8
2
7
4
8
0
9
1
0.5
1
10
11
12
13
14
15
16
17
PsiJT
Junction-to-package top
1.1
1.1
1.3
9.5
8.8
8.7
8.6
8.5
1.3
2
1.5
4
6.3
5.9
5.9
5.8
5.8
10.8
9.9
0
0.5
1
PsiJB
Junction-to-board
9.8
9.7
2
9.6
4
(1) Simulation data, using a model of a JEDEC defined 2S2P system with a 12 x 12-mm copper pad on the top and bottom copper layers
connected with an 8 x 8 thermal via array and soldered to the package thermal pad. Power dissipation of 1 W assumed, 70°C Ambient
temp assumed. Signal layer copper coverage 20%, inner layer copper coverage 90%. Actual performance will change based on
environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal
Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for
Leaded Surface Mount Packages.
(2) Simulation data, using the same model but with 1 oz. (35 mm) top and bottom copper thickness and 0.5 oz. (18 mm) inner copper
thickness. Power dissipation of 1 W and ambient temp of 70°C assumed.
(3) Simulation data, 1S1P PCB model with 12 x 12-mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8 x 8 thermal via array. Power dissipation of 1 W and ambient temp of 70°C assumed.
Copper thickness 2 oz. (70 mm) top and bottom.
(4) Simulation data, 1S1P PCB model with 12 x 12-mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8 x 8 thermal via array. Power dissipation of 1 W and ambient temp of 70°C assumed.
Copper thickness 1 oz. (35 mm) top and bottom.
(5) m/s = meters per second
Copyright © 2009–2010, Texas Instruments Incorporated
Thermal/Mechanical Data
163
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