SM320LF2407A-EP [TI]
DSP CONTROLLERS;
| 型号： | SM320LF2407A-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DSP CONTROLLERS |
| 文件： | 总112页 (文件大小：1426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢍꢀꢌ ꢎꢏ ꢐꢑ ꢒ ꢏꢅ ꢅꢋ ꢒꢀ
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
Two Event-Manager (EV) Modules
(EVA and EVB), Each Includes:
− Two 16-Bit General-Purpose Timers
− Eight 16-Bit Pulse-Width Modulation
(PWM) Channels Which Enable:
− Three-Phase Inverter Control
− Center- or Edge-Alignment of PWM
Channels
− Emergency PWM Channel Shutdown
With External PDPINTx Pin
− Programmable Deadband (Deadtime)
Prevents Shoot-Through Faults
− Three Capture Units for Time-Stamping
of External Events
− Input Qualifier for Select Pins
− On-Chip Position Encoder Interface
Circuitry
− Synchronized A-to-D Conversion
− Designed for AC Induction, BLDC,
Switched Reluctance, and Stepper Motor
Control
D
D
D
D
D
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
†
Qualification Pedigree
High-Performance Static CMOS Technology
− 25-ns Instruction Cycle Time (40 MHz)
− 40-MIPS Performance
− Low-Power 3.3-V Design
D
D
Based on TMS320C2xx DSP CPU Core
− Code-Compatible With F243/F241/C242
− Instruction Set and Module Compatible
With F240/C240
On-Chip Memory
− 32K Words x 16 Bits of Flash EEPROM
(4 Sectors) or ROM
− Programmable “Code-Security” Feature
for the On-Chip Flash/ROM
− Up to 2.5K Words x 16 Bits of
Data/Program RAM
− Applicable for Multiple Motor and/or
Converter Control
D
D
D
D
Phase-Locked-Loop (PLL)-Based Clock
Generation
40 Individually Programmable, Multiplexed
General-Purpose Input/Output (GPIO) Pins
− 544 Words of Dual-Access RAM
− 2K Words of Single-Access RAM
Five External Interrupts (Power Drive
Protection, Reset, Two Maskable Interrupts)
D
D
Boot ROM
− SCI/SPI Bootloader
Power Management:
External Memory Interface
− 192K Words x 16 Bits of Total Memory:
64K Program, 64K Data, 64K I/O
− Three Power-Down Modes
− Ability to Power Down Each Peripheral
Independently
D
D
Watchdog (WD) Timer Module
D
D
Real-Time JTAG-Compliant Scan-Based
10-Bit Analog-to-Digital Converter (ADC)
− 8 or 16 Multiplexed Input Channels
− 375 ns or 500 ns MIN Conversion Time
− Selectable Twin 8-State Sequencers
Triggered by Two Event Managers
‡
Emulation, IEEE Standard 1149.1 (JTAG)
Development Tools Include:
− Texas Instruments (TI) ANSI C Compiler,
Assembler/Linker, and Code Composer
Studio Debugger
D
D
D
Controller Area Network (CAN) 2.0B Module
Serial Communications Interface (SCI)
16-Bit Serial Peripheral Interface (SPI)
− Evaluation Modules
− Scan-Based Self-Emulation (XDS510)
− Broad Third-Party Digital Motor Control
Support
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio and XDS510 are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
†
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
240xA Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Controller Area Network (CAN) Module . . . . . . . . . . 37
Serial Communications Interface (SCI) Module . . . . 39
Serial Peripheral Interface (SPI) Module . . . . . . . . . . 41
PLL-Based Clock Module . . . . . . . . . . . . . . . . . . . . . . 43
Digital I/O and Shared Pin Functions . . . . . . . . . . . . . 46
External Memory Interface (LF2407A) . . . . . . . . . . . . 49
Watchdog (WD) Timer Module . . . . . . . . . . . . . . . . . . 50
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . 56
Electrical Specifications Data . . . . . . . . . . . . . . . . . . . . 57
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 57
Device Operating Life . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Recommended Operating Conditions . . . . . . . . . . . . . 59
Parameter Measurement Information . . . . . . . . . . . . . . 63
Migrating From 240x Devices to 240xA Devices . . . . 95
Peripheral Register Description . . . . . . . . . . . . . . . . . . . 96
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Functional Block Diagram of the 2407A
DSP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Peripheral Memory Map of the 2407A/2406A . . . . . . . 15
Device Reset and Interrupts . . . . . . . . . . . . . . . . . . . . . 16
DSP CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
240xA Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Scan-Based Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional Block Diagram of the 2407A DSP CPU . . 21
Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Event Manager Modules (EVA, EVB) . . . . . . . . . . . . 31
Enhanced Analog-to-Digital Converter
(ADC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
description
The SM320LF2407A-EP is a member of the TMS320C24x generation of digital signal processor (DSP)
controllers, and is part of the TMS320C2000 platform of fixed-point DSPs. The 240xA devices offer the
enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and
high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and
motion control applications, have been integrated to provide a true single-chip DSP controller. While
code-compatible with the existing C24x DSP controller devices, the 2407A offers increased processing
performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary
section for device-specific features.
The 240xA generation offers an array of memory sizes and different peripherals tailored to meet the specific
price/performance points required by various applications. Flash devices of up to 32K words offer a
cost-effective reprogrammable solution for volume production. The 240xA devices offer a password-based
“code security” feature which is useful in preventing unauthorized duplication of proprietary code stored in
on-chip Flash/ROM. Note that Flash-based devices contain a 256-word boot ROM to facilitate in-circuit
programming. The 240xA family also includes ROM devices that are fully pin-to-pin compatible with their Flash
counterparts.
All 240xA devices offer at least one event manager module which has been optimized for digital motor control
and power conversion applications. Capabilities of this module include center- and/or edge-aligned PWM
generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital
conversion. Devices with dual event managers enable multiple motor and/or converter control with a single
240xA DSP controller. Select EV pins have been provided with an “input-qualifier” circuitry, which minimizes
inadvertent pin-triggering by glitches.
The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 375 ns and
offers up to 16 channels of analog input. The autosequencing capability of the ADC allows a maximum of
16 conversions to take place in a single conversion session without any CPU overhead.
A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication
to other devices in the system. For systems requiring additional communication interfaces, the 2407A offers a
16-bit synchronous serial peripheral interface (SPI). The 2407A offers a controller area network (CAN)
communications module that meets 2.0B specifications. To maximize device flexibility, functional pins are also
configurable as general-purpose inputs/outputs (GPIOs).
To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices.
This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite
of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger
supports this family. Numerous third-party developers not only offer device-level development tools, but also
system-level design and development support.
TMS320C24x, TMS320C2000, TMS320, and C24x are trademarks of Texas Instruments.
3
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
240xA device summary
Note that throughout this data sheet, 240xA is used as a generic name for the LF240xA/LC240xA generation
of devices.
Table 1. Hardware Features of 2407A Device
FEATURE
LF2407A
Yes
C2xx DSP Core
Instruction Cycle
MIPS (40 MHz)
25 ns
40 MIPS
544
Dual-Access RAM (DARAM)
Single-Access RAM (SARAM)
RAM (16-bit word)
2K
3.3-V On-chip Flash (16-bit word) (4 sectors: 4K, 12K, 12K, 4K)
On-chip ROM (16-bit word)
32K
—
Code Security for On-Chip Flash/ROM
Boot ROM
Yes
Yes
External Memory Interface
Yes
Event Managers A and B (EVA and EVB)
EVA, EVB
4
S
S
S
S
S
General-Purpose (GP) Timers
Compare (CMP)/PWM
12/16
6/4
Capture (CAP)/QEP
Input qualifier circuitry on PDPINTx, CAPn, XINT1/2, and ADCSOC pins
Status of PDPINTx pin reflected in COMCONx register
Yes
Yes
Watchdog Timer
10-Bit ADC
Yes
Yes
S
S
Channels
Conversion Time (minimum)
16
500 ns
Yes
SPI
SCI
CAN
Yes
Yes
Digital I/O Pins (Shared)
External Interrupts
Supply Voltage
41
5
3.3 V
144-pin PGE
Packaging
Product Status:
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
PD
Denotes features that are different/new compared to 240x devices.
4
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
functional block diagram of the 2407A DSP controller
PLLF
PLLV
CCA
DARAM (B0)
256 Words
PLLF2
XINT1/IOPA2
RS
PLL Clock
XTAL1/CLKIN
CLKOUT/IOPE0
TMS2
XTAL2
ADCIN00−ADCIN07
ADCIN08−ADCIN15
C2xx
DSP
Core
BIO/IOPC1
DARAM (B1)
256 Words
V
CCA
MP/MC
10-Bit ADC
(With Twin
Autosequencer)
V
V
SSA
BOOT_EN/XF
REFHI
V
(3.3 V)
DD
V
V
REFLO
SS
DARAM (B2)
32 Words
XINT2/ADCSOC/IOPD0
SCITXD/IOPA0
SCI
SPI
SCIRXD/IOPA1
SPISIMO/IOPC2
SPISOMI/IOPC3
SPICLK/IOPC4
SPISTE/IOPC5
SARAM (2K Words)
TP1
TP2
(5V)
CANTX/IOPC6
CANRX/IOPC7
Flash/ROM
(32K Words:
4K/12K/12K/4K)
CAN
WD
V
CCP
Port A(0−7) IOPA[0:7]
Port B(0−7) IOPB[0:7]
A0−A15
D0−D15
Port C(0−7) IOPC[0:7]
Port D(0) IOPD[0]
Digital I/O
(Shared With
Other Pins)
PS, DS, IS
R/W
Port E(0−7) IOPE[0:7]
Port F(0−6) IOPF[0:6]
TRST
RD
READY
STRB
External Memory
Interface
TDO
WE
TDI
ENA_144
TMS
JTAG Port
TCK
VIS_OE
EMU0
EMU1
W/R / IOPC0
PDPINTA
PDPINTB
CAP1/QEP1/IOPA3
CAP2/QEP2/IOPA4
CAP3/IOPA5
CAP4/QEP3/IOPE7
CAP5/QEP4/IOPF0
CAP6/IOPF1
PWM1/IOPA6
PWM2/IOPA7
PWM7/IOPE1
Event Manager A
Event Manager B
PWM8/IOPE2
PWM3/IOPB0
PWM4/IOPB1
PWM9/IOPE3
D 3 × Capture Input
D 6 × Compare/PWM
Output
D 3 × Capture Input
D 6 × Compare/PWM
Output
PWM10/IOPE4
PWM11/IOPE5
PWM12/IOPE6
T3PWM/T3CMP/IOPF2
PWM5/IOPB2
PWM6/IOPB3
D 2 × GP
D 2 × GP
Timers/PWM
Timers/PWM
T1PWM/T1CMP/IOPB4
T2PWM/T2CMP/IOPB5
T4PWM/T4CMP/IOPF3
TDIRB/IOPF4
TDIRA/IOPB6
TCLKINA/IOPB7
TCLKINB/IOPF5
Indicates optional modules.
The memory size and peripheral selection of these modules change for different 240xA devices.
See Table 1 for device-specific details.
5
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
pinouts
†
PGE PACKAGE
(TOP VIEW)
1
108
107
106
105
104
103
102
101
100
99
TRST
ADCIN11
ADCIN02
ADCIN12
ADCIN03
ADCIN13
ADCIN04
ADCIN05
ADCIN14
ADCIN06
ADCIN07
ADCIN15
VIS_OE
2
TDIRB/IOPF4
3
V
SSO
4
V
DDO
5
D7
T4PWM/T4CMP/IOPF3
PDPINTA
6
7
8
T3PWM/T3CMP/IOPF2
D8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PLLF2
PLLF
98
97
PLLV
CCA
D9
96
STRB
95
TDIRA/IOPB6
V
V
DDO
SSO
94
D10
T1PWM/T1CMP/IOPB4
D11
93
RD
92
R/W
SM320LF2407A PGE
91
T2PWM/T2CMP/IOPB5
W/R/IOPC0
EMU1/OFF
90
EMU0
89
D12
WE
88
XINT2/ADCSOC/IOPD0
D13
CAP4/QEP3/IOPE7
DS
87
V
86
XINT1/IOPA2
D14
DD
85
V
SS
84
SCITXD/IOPA0
SCIRXD/IOPA1
D15
PS
83
CAP1/QEP1/IOPA3
82
IS
81
V
CAP5/QEP4/IOPF0
SS
DD
80
V
A0
79
SPISIMO/IOPC2
A15
CAP2/QEP2/IOPA4
78
A1
77
SPISOMI/IOPC3
SPISTE/IOPC5
A14
V
V
DDO
76
SSO
75
CAP3/IOPA5
A2
74
SPICLK/IOPC4
TMS2
73
CLKOUT/IOPE0
†
‡
Bold, italicized pin names indicate pin function after reset.
BOOT_EN is available only on Flash devices.
6
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
pin functions
The SM320LF2407A device is the superset of all the 240xA devices. All signals are available on the 2407A
device. Table 2 lists the signals available in the 240xA generation of devices.
†‡
Table 2. LF240xA and LC240xA Pin List and Package Options
LF2407A
(144-PGE)
PIN NAME
DESCRIPTION
EVENT MANAGER A (EVA)
CAP1/QEP1/IOPA3
CAP2/QEP2/IOPA4
CAP3/IOPA5
83
79
75
56
54
52
47
44
40
16
18
Capture input #1/quadrature encoder pulse input #1 (EVA) or GPIO (↑)
Capture input #2/quadrature encoder pulse input #2 (EVA) or GPIO (↑)
Capture input #3 (EVA) or GPIO (↑)
PWM1/IOPA6
Compare/PWM output pin #1 (EVA) or GPIO (↑)
Compare/PWM output pin #2 (EVA) or GPIO (↑)
Compare/PWM output pin #3 (EVA) or GPIO (↑)
Compare/PWM output pin #4 (EVA) or GPIO (↑)
Compare/PWM output pin #5 (EVA) or GPIO (↑)
Compare/PWM output pin #6 (EVA) or GPIO (↑)
Timer 1 compare output (EVA) or GPIO (↑)
PWM2/IOPA7
PWM3/IOPB0
PWM4/IOPB1
PWM5/IOPB2
PWM6/IOPB3
T1PWM/T1CMP/IOPB4
T2PWM/T2CMP/IOPB5
Timer 2 compare output (EVA) or GPIO (↑)
Counting direction for general-purpose (GP) timer (EVA) or GPIO. If TDIRA = 1, upward counting is
selected. If TDIRA = 0, downward counting is selected. (↑)
TDIRA/IOPB6
14
37
External clock input for GP timer (EVA) or GPIO. Note that the timer can also use the internal
device clock. (↑)
TCLKINA/IOPB7
EVENT MANAGER B (EVB)
CAP4/QEP3/IOPE7
CAP5/QEP4/IOPF0
CAP6/IOPF1
88
81
69
65
62
59
55
46
38
8
Capture input #4/quadrature encoder pulse input #3 (EVB) or GPIO (↑)
Capture input #5/quadrature encoder pulse input #4 (EVB) or GPIO (↑)
Capture input #6 (EVB) or GPIO (↑)
PWM7/IOPE1
Compare/PWM output pin #7 (EVB) or GPIO (↑)
Compare/PWM output pin #8 (EVB) or GPIO (↑)
Compare/PWM output pin #9 (EVB) or GPIO (↑)
Compare/PWM output pin #10 (EVB) or GPIO (↑)
Compare/PWM output pin #11 (EVB) or GPIO (↑)
Compare/PWM output pin #12 (EVB) or GPIO (↑)
Timer 3 compare output (EVB) or GPIO (↑)
PWM8/IOPE2
PWM9/IOPE3
PWM10/IOPE4
PWM11/IOPE5
PWM12/IOPE6
T3PWM/T3CMP/IOPF2
T4PWM/T4CMP/IOPF3
6
Timer 4 compare output (EVB) or GPIO (↑)
Counting direction for general-purpose (GP) timer (EVB) or GPIO. If TDIRB = 1, upward counting is
selected. If TDIRB = 0, downward counting is selected. (↑)
TDIRB/IOPF4
2
External clock input for GP timer (EVB) or GPIO. Note that the timer can also use the internal
device clock. (↑)
TCLKINB/IOPF5
126
†
‡
§
Bold, italicized pin names indicate pin function after reset.
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
It is highly recommended that V
and improve the noise immunity of the ADC.
be isolated from the digital supply voltage (and V from digital ground) to maintain the specified accuracy
CCA
SSA
¶
#
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
No power supply pin (V , V , V , or V ) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
DD DDO SS SSO
LEGEND: ↑ − Internal pullup
↓ − Internal pulldown
(Typical active pullup/pulldown value is 16 µA.)
7
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
pin functions (continued)
†‡
Table 2. LF240xA and LC240xA Pin List and Package Options (Continued)
LF2407A
(144-PGE)
PIN NAME
DESCRIPTION
ANALOG-TO-DIGITAL CONVERTER (ADC)
ADCIN00
ADCIN01
ADCIN02
ADCIN03
ADCIN04
ADCIN05
ADCIN06
ADCIN07
ADCIN08
ADCIN09
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN14
ADCIN15
112
110
107
105
103
102
100
99
Analog input #0 to the ADC
Analog input #1 to the ADC
Analog input #2 to the ADC
Analog input #3 to the ADC
Analog input #4 to the ADC
Analog input #5 to the ADC
Analog input #6 to the ADC
Analog input #7 to the ADC
Analog input #8 to the ADC
Analog input #9 to the ADC
Analog input #10 to the ADC
Analog input #11 to the ADC
Analog input #12 to the ADC
Analog input #13 to the ADC
Analog input #14 to the ADC
Analog input #15 to the ADC
ADC analog high-voltage reference input
ADC analog low-voltage reference input
113
111
109
108
106
104
101
98
V
V
V
V
115
114
116
117
REFHI
REFLO
CCA
§
Analog supply voltage for ADC (3.3 V)
Analog ground reference for ADC
SSA
CONTROLLER AREA NETWORK (CAN), SERIAL COMMUNICATIONS INTERFACE (SCI), SERIAL PERIPHERAL INTERFACE (SPI)
CANRX
IOPC7
CANTX
IOPC6
70
70
72
72
25
26
35
35
30
30
32
32
33
33
CAN receive data or GPIO (LF2403A) (↑)
GPIO only (2402A) (↑)
CANRX/IOPC7
CANTX/IOPC6
CAN transmit data or GPIO (LF2403A) (↑)
GPIO only (2402A) (↑)
SCITXD/IOPA0
SCIRXD/IOPA1
SCI asynchronous serial port transmit data or GPIO (↑)
SCI asynchronous serial port receive data or or GPIO (↑)
SPI clock or GPIO (LF2403A) (↑)
GPIO only (2402A) (↑)
SPICLK
IOPC4
SPICLK/IOPC4
SPISIMO/IOPC2
SPISOMI/IOPC3
SPISTE/IOPC5
SPISIMO
IOPC2
SPI slave in, master out or GPIO (LF2403A) (↑)
GPIO only (2402A) (↑)
SPISOMI
IOPC3
SPI slave out, master in or GPIO (LF2403A) (↑)
GPIO only (2402A) (↑)
SPISTE
IOPC5
SPI slave transmit-enable (optional) or GPIO (↑)
†
‡
§
Bold, italicized pin names indicate pin function after reset.
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
It is highly recommended that V
and improve the noise immunity of the ADC.
be isolated from the digital supply voltage (and V from digital ground) to maintain the specified accuracy
CCA
SSA
¶
#
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
No power supply pin (V , V , V , or V ) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
DD DDO SS SSO
LEGEND: ↑ − Internal pullup
↓ − Internal pulldown
(Typical active pullup/pulldown value is 16 µA.)
8
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
pin functions (continued)
†‡
Table 2. LF240xA and LC240xA Pin List and Package Options (Continued)
LF2407A
(144-PGE)
PIN NAME
DESCRIPTION
EXTERNAL INTERRUPTS, CLOCK
Device reset. RS causes the 240xA to terminate execution and sets PC = 0. When RS is brought
to a high level, execution begins at location zero of program memory. RS affects (or sets to zero)
various registers and status bits. When the watchdog timer overflows, it initiates a system reset
pulse that is reflected on the RS pin. The RS pin is an open drain with a pullup. (↑)
RS
133
Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins
(EVA) in the high-impedance state should motor drive/power converter abnormalities, such as
overvoltage or overcurrent, etc., arise. PDPINTA is a falling-edge-sensitive interrupt. (↑)
PDPINTA
7
External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge-sensitive. The edge polarity
is programmable. (↑)
XINT1/IOPA2
23
21
External user interrupt 2 and ADC start of conversion or GPIO. External “start-of-conversion” input
for ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. The edge polarity is
programmable. (↑)
XINT2/ADCSOC/IOPD0
Clock output or GPIO. This pin outputs either the CPU clock (CLKOUT) or the watchdog clock
(WDCLK). The selection is made by the CLKSRC bit (bit 14) of the system control and status
register (SCSR). This pin can be used as a GPIO if not used as a clock output pin. (↑)
CLKOUT/IOPE0
73
Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins
(EVB) in the high-impedance state should motor drive/power converter abnormalities, such as
overvoltage or overcurrent, etc., arise. PDPINTB is a falling-edge-sensitive interrupt. (↑)
PDPINTB
137
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS
PLL oscillator input pin. Crystal input to PLL/clock source input to PLL. XTAL1/CLKIN is tied to
one side of a reference crystal.
XTAL1/CLKIN
XTAL2
123
Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a reference crystal. This pin
goes in the high-impedance state when EMU1/OFF is active low.
124
PLLV
CCA
12
PLL supply (3.3 V)
IOPF6
131
General-purpose I/O (↑)
Boot ROM enable, GPO, XF. This pin will be sampled as input (BOOT_EN) to update SCSR2.3
(BOOT_EN bit) during reset and then driven as an output signal for XF. After reset, XF is driven
high. ROM devices do not have boot ROM, hence, no BOOT_EN modes. The BOOT_EN pin must
be driven with a passive circuit only. (↑)
BOOT_EN
XF
121
121
BOOT_EN /
XF
PLLF
11
10
PLL loop filter input 1
PLL loop filter input 2
PLLF2
Flash programming voltage pin. This pin must be connected to a 5-V supply for Flash
programming. The Flash cannot be programmed if this pin is connected to GND. When not
programming the Flash (i.e., during normal device operation), this pin can either be left connected
to the 5-V supply or it can be tied to GND. This pin must not be left floating at any time. Do not use
any current-limiting resistor in series with the 5-V supply on this pin. This pin is a “no connect” (NC)
on ROM parts (i.e., this pin is not connected to any circuitry internal to the device). Connecting this
pin to 5 V or leaving it open makes no difference on ROM parts.
V
CCP
(5V)
58
TP1
TP2
60
63
Test pin 1. Do not connect.
Test pin 2. Do not connect.
†
‡
§
Bold, italicized pin names indicate pin function after reset.
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
It is highly recommended that V
and improve the noise immunity of the ADC.
be isolated from the digital supply voltage (and V from digital ground) to maintain the specified accuracy
CCA
SSA
¶
#
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
No power supply pin (V , V , V , or V ) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
DD DDO SS SSO
LEGEND: ↑ − Internal pullup
↓ − Internal pulldown
(Typical active pullup/pulldown value is 16 µA.)
9
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
pin functions (continued)
†‡
Table 2. LF240xA and LC240xA Pin List and Package Options (Continued)
LF2407A
PIN NAME
DESCRIPTION
(144-PGE)
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS (CONTINUED)
Branch control input. BIO is polled by the BCND pma,BIO instruction. If BIO is low, a branch is
BIO/IOPC1
119
90
executed. If BIO is not used, it should be pulled high. This pin is configured as a branch control input
by all device resets. It can be used as a GPIO, if not used as a branch control input. (↑)
EMULATION AND TEST
Emulator I/O #0 with internal pullup. When TRST is driven high, this pin is used as an interrupt to or
from the emulator system and is defined as input/output through the JTAG scan. (↑)
EMU0
Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1/OFF is used as
an interrupt to or from the emulator system and is defined as an input/output through the JTAG scan.
When TRST is driven low, this pin is configured as OFF. EMU1/OFF, when active low, puts all output
drivers in the high-impedance state. Note that OFF is used exclusively for testing and emulation
purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply:
TRST = 0
EMU1/OFF
91
EMU0 = 1
EMU1/OFF = 0 (↑)
TCK
TDI
135
139
JTAG test clock with internal pullup (↑)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or
data) on a rising edge of TCK. (↑)
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is
shifted out of TDO on the falling edge of TCK. (↓)
TDO
TMS
142
144
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (↑)
JTAG test-mode select 2 (TMS2) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. Used for test and emulation only. This pin can be left unconnected
in user applications. If the PLL bypass mode is desired, TMS2, TMS, and TRST should be held low
during reset. (↑)
TMS2
36
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the
operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored. (↓)
NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device. In a low-noise
environment, TRST can be left floating. In a high-noise environment, an additional pulldown resistor
may be needed. The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board is validated for proper operation of the
debugger and the application.
TRST
1
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS
Data space strobe. IS, DS, and PS are always high unless low-level asserted for access to the relevant
external memory space or I/O. They are placed in the high-impedance state.
DS
IS
87
82
¶
I/O space strobe. IS, DS, and PS are always high unless low-level asserted for access to the relevant
¶
external memory space or I/O. They are placed in the high-impedance state.
†
‡
§
Bold, italicized pin names indicate pin function after reset.
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
It is highly recommended that V
and improve the noise immunity of the ADC.
be isolated from the digital supply voltage (and V
from digital ground) to maintain the specified accuracy
CCA
SSA
¶
#
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
No power supply pin (V , V , V , or V ) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
DD DDO SS SSO
LEGEND: ↑ − Internal pullup
↓ − Internal pulldown
(Typical active pullup/pulldown value is 16 µA.)
10
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
pin functions (continued)
†‡
Table 2. LF240xA and LC240xA Pin List and Package Options (Continued)
LF2407A
(144-PGE)
PIN NAME
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
Program space strobe. IS, DS, and PS are always high unless low-level asserted for access to the
relevant external memory space or I/O. They are placed in the high-impedance state.
PS
84
¶
Read/write qualifier signal. R/W indicates transfer direction during communication to an external
device. It is normally in read mode (high), unless low level is asserted for performing a write operation.
R/W is placed in the high-impedance state.
R/W
92
¶
Write/Read qualifier or GPIO. This is an inverted R/W signal useful for zero-wait-state memory
interface. It is normally low, unless a memory write operation is performed. See Table 12, Port C
section, for reset note regarding LF2406A and LF2402A. (↑)
W/R
IOPC0
19
19
W/R /
IOPC0
Read-enable strobe. Read-select indicates an active, external read cycle. RD is active on all external
program, data, and I/O reads. RD is placed in the high-impedance state.
RD
93
89
96
¶
Write-enable strobe. The falling edge of WE indicates that the device is driving the external data bus
(D15−D0). WE is active on all external program, data, and I/O writes. WE is placed in the
WE
¶
high-impedance state.
External memory access strobe. STRB is always high unless asserted low to indicate an external bus
STRB
¶
cycle. STRB is active for all off-chip accesses. STRB is placed in the high-impedance state.
READY is pulled low to add wait states for external accesses. READY indicates that an external device
is prepared for a bus transaction to be completed. If the device is not ready, it pulls the READY pin low.
The processor waits one cycle and checks READY again. Note that the processor performs
READY-detection if at least one software wait state is programmed. To meet the external READY
timings, the wait-state generator control register (WSGR) should be programmed for at least one wait
state. (↑)
READY
MP/MC
120
118
Microprocessor/Microcomputer mode select. If this pin is low during reset, the device is put in
microcomputer mode and program execution begins at 0000h of internal program memory (Flash
EEPROM). A high value during reset puts the device in microprocessor mode and program execution
begins at 0000h of external program memory. This line sets the MP/MC bit (bit 2 in the SCSR2
register). (↓)
Active high to enable external interface signals. If pulled low, the 2407A behaves like the
2406A/2403A/2402A—i.e., it has no external memory and generates an illegal address if DS is
asserted. This pin has an internal pulldown. (↓)
ENA_144
VIS_OE
122
97
Visibility output enable (active when data bus is output). This pin is active (low) whenever the external
data bus is driving as an output during visibility mode. Can be used by external decode logic to prevent
data bus contention while running in visibility mode.
A0
A1
A2
A3
A4
A5
A6
A7
80
78
74
71
68
64
61
57
Bit 0 of the 16-bit address bus
Bit 1 of the 16-bit address bus
Bit 2 of the 16-bit address bus
Bit 3 of the 16-bit address bus
Bit 4 of the 16-bit address bus
Bit 5 of the 16-bit address bus
Bit 6 of the 16-bit address bus
Bit 7 of the 16-bit address bus
†
Bold, italicized pin names indicate pin function after reset.
‡
§
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
It is highly recommended that V
and improve the noise immunity of the ADC.
be isolated from the digital supply voltage (and V from digital ground) to maintain the specified accuracy
CCA
SSA
¶
#
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
No power supply pin (V , V , V , or V ) should be left unconnected. All power supply pins must be connected appropriately for proper
DD DDO SS SSO
device operation.
LEGEND: ↑ − Internal pullup
↓ − Internal pulldown
(Typical active pullup/pulldown value is 16 µA.)
11
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
pin functions (continued)
†‡
Table 2. LF240xA and LC240xA Pin List and Package Options (Continued)
LF2407A
PIN NAME
DESCRIPTION
(144-PGE)
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
A8
53
51
Bit 8 of the 16-bit address bus
Bit 9 of the 16-bit address bus
Bit 10 of the 16-bit address bus
Bit 11 of the 16-bit address bus
Bit 12 of the 16-bit address bus
Bit 13 of the 16-bit address bus
Bit 14 of the 16-bit address bus
Bit 15 of the 16-bit address bus
Bit 0 of 16-bit data bus (↑)
Bit 1 of 16-bit data bus (↑)
Bit 2 of 16-bit data bus (↑)
Bit 3 of 16-bit data bus (↑)
Bit 4 of 16-bit data bus (↑)
Bit 5 of 16-bit data bus (↑)
Bit 6 of 16-bit data bus (↑)
Bit 7 of 16-bit data bus (↑)
Bit 8 of 16-bit data bus (↑)
Bit 9 of 16-bit data bus (↑)
Bit 10 of 16-bit data bus (↑)
Bit 11 of 16-bit data bus (↑)
Bit 12 of 16-bit data bus (↑)
Bit 13 of 16-bit data bus (↑)
Bit 14 of 16-bit data bus (↑)
Bit 15 of 16-bit data bus (↑)
A9
A10
A11
A12
A13
A14
A15
D0
48
45
43
39
34
31
127
130
132
134
136
138
143
5
D1
D2
D3
D4
D5
D6
D7
D8
9
D9
13
D10
D11
D12
D13
D14
D15
15
17
20
22
24
27
POWER SUPPLY
29
50
86
129
4
#
V
V
Core supply +3.3 V. Digital logic supply voltage.
DD
42
67
77
95
141
#
I/O buffer supply +3.3 V. Digital logic and buffer supply voltage.
DDO
†
‡
§
Bold, italicized pin names indicate pin function after reset.
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
It is highly recommended that V
and improve the noise immunity of the ADC.
be isolated from the digital supply voltage (and V from digital ground) to maintain the specified accuracy
CCA
SSA
¶
#
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
No power supply pin (V , V , V , or V ) should be left unconnected. All power supply pins must be connected appropriately for proper
DD DDO SS SSO
device operation.
LEGEND: ↑ − Internal pullup
↓ − Internal pulldown
(Typical active pullup/pulldown value is 16 µA.)
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
pin functions (continued)
†‡
Table 2. LF240xA and LC240xA Pin List and Package Options (Continued)
LF2407A
(144-PGE)
PIN NAME
DESCRIPTION
POWER SUPPLY (CONTINUED)
28
49
#
V
V
Core ground. Digital logic ground reference.
SS
85
128
3
41
66
#
76
I/O buffer ground. Digital logic and buffer ground reference.
SSO
94
125
140
†
‡
§
Bold, italicized pin names indicate pin function after reset.
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
It is highly recommended that V
and improve the noise immunity of the ADC.
be isolated from the digital supply voltage (and V from digital ground) to maintain the specified accuracy
CCA
SSA
¶
#
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
No power supply pin (V , V , V , or V ) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
DD DDO SS SSO
LEGEND: ↑ − Internal pullup
↓ − Internal pulldown
(Typical active pullup/pulldown value is 16 µA.)
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
memory maps
Hex
0000
Data
Hex
0000
I/O
Hex
Program
0000
Memory-Mapped
Registers/Reserved Addresses
Flash Sector 0 (4K)
005F
0060
007F
0080
00FF
0100
01FF
Interrupt Vectors (0000−003Fh)
Reserved (0040−0043h)
User code begins at 0044h
On-Chip DARAM B2
Illegal
†
0FFF
1000
Reserved
0200
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
02FF
0300
03FF
Flash Sector 1 (12K)
¶
On-Chip DARAM (B1)
0400
Reserved
Illegal
04FF
0500
3FFF
4000
07FF
0800
External
SARAM (2K)
Internal (DON = 1)
Reserved (DON=0)
Flash Sector 2 (12K)
Flash Sector 3 (4K)
0FFF
1000
Illegal
6FFF
7000
6FFF
7000
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, SPI, CAN, I/O, Interrupts)
7FFF
8000
7FFF
8000
SARAM (2K)
Internal (PON = 1)
External (PON=0)
87FF
8800
FEFF
FF00
Reserved
Flash Control Mode Register
Reserved
External
FF0E
External
FF0F
FDFF
FE00
FF10
FFFE
‡
Reserved (CNF = 1)
External (CNF = 0)
FEFF
FF00
Wait-State Generator Control
Register (On-Chip)
‡
On-Chip DARAM (B0) (CNF = 1)
External (CNF = 0)
FFFF
FFFF
FFFF
SARAM (See Table 1 for details.)
On-Chip Flash Memory (Sectored) − if MP/MC = 0
External Program Memory − if MP/MC = 1
Reserved or Illegal
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.
†
‡
Addresses 0040h−0043h in on-chip program memory are reserved for code security passwords.
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved when
CNF = 1.
§
¶
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
Figure 1. SM320LF2407A Memory Map
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peripheral memory map of the 2407A
Hex
0000
0003
0004
Reserved
Interrupt-Mask Register
Reserved
0005
Interrupt Flag Register
0006
0007
Emulation Registers
and Reserved
005F
Hex
0000
Memory-Mapped Registers
Illegal
and Reserved
7000−700F
7010−701F
005F
0060
System Configuration and
Control Registers
On-Chip DARAM B2
007F
0080
Illegal
Watchdog Timer Registers
7020−702F
00FF
0100
Illegal
SPI
7030−703F
7040−704F
7050−705F
7060−706F
7070−707F
7080−708F
7090−709F
70A0−70BF
70C0−70FF
7100−710E
710F−71FF
7200−722F
7230−73FF
Reserved
01FF
0200
SCI
On-Chip DARAM B0
Illegal
02FF
0300
On-Chip DARAM B1
External-Interrupt Registers
Illegal
03FF
0400
Reserved
Digital I/O Control Registers
ADC Control Registers
Illegal
04FF
0500
Illegal
07FF
0800
SARAM (2K)
0FFF
1000
CAN Control Registers
Illegal
Illegal
6FFF
7000
CAN Mailbox
Illegal
Peripheral Frame 1 (PF1)
73FF
7400
Peripheral Frame 2 (PF2)
743F
7440
Event Manager − EVA
Illegal
General-Purpose
Timer Registers
Compare, PWM, and
Deadband Registers
74FF
7500
7400−7408
Peripheral Frame 3 (PF3)
753F
7540
7411−7419
7420−7429
Illegal
Capture and QEP Registers
77EF
77F0
77F3
77F4
77FF
7800
7FFF
Code Security Passwords
Interrupt Mask, Vector and
Flag Registers
742C−7431
7432−743F
Reserved
Illegal
Illegal
8000
FFFF
Event Manager − EVB
†
External
General-Purpose
Timer Registers
Compare, PWM, and
Deadband Registers
7500−7508
“Illegal” indicates that access to
these addresses causes a
nonmaskable interrupt (NMI).
Illegal
7511−7519
7520−7529
Capture and QEP Registers
“Reserved” indicates addresses that
are reserved for test.
Interrupt Mask, Vector, and
Flag Registers
Reserved
752C−7531
7532−753F
Reserved
†
Available in LF2407A only
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device reset and interrupts
The 240xA software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The LF240xA recognizes three types
of interrupt sources.
D
Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The LF240xA devices have two sources of reset: an external reset pin and a watchdog timer time-out
(reset).
D
Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types:
−
External interrupts are generated by one of four external pins corresponding to the interrupts XINT1,
XINT2, PDPINTA, and PDPINTB. These four can be masked both by dedicated enable bits and by the
CPU’s interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core.
−
Peripheral interrupts are initiated internally by these on-chip peripheral modules: event manager A,
event manager B, SPI, SCI, CAN, and ADC. They can be masked both by enable bits for each event in
each peripheral and by the CPU’s IMR, which can mask each maskable interrupt line at the DSP core.
D
Software-generated interrupts for the LF240xA devices include:
−
−
−
The INTR instruction. This instruction allows initialization of any LF240xA interrupt with software. Its
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
The NMI instruction. This instruction forces a branch to interrupt vector location 24h. This instruction
globally disables maskable interrupts. 240xA devices do not have the NMI hardware signal, only
software activation is provided.
The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
−
An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.
Six core interrupts (INT1−INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to
the F24x devices. The PIE manages all the peripheral interrupts from the 240xA peripherals and are grouped to
share the six core level interrupts. Figure 2 shows the PIE block diagram for hardware-generated interrupts.
The PIE block diagram (Figure 2) and the interrupt table (Table 3) explain the grouping and interrupt vector
maps. LF240xA devices have interrupts identical to those of the F24x devices and should be completely
code-compatible. 240xA devices also have peripheral interrupts identical to those of the F24x − plus additional
interrupts for new peripherals such as event manager B. Though the new interrupts share the 24x interrupt
grouping, they all have a unique vector to differentiate among the interrupts. See Table 3 for details.
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device reset and interrupts (continued)
PDPINTA
PDPINTB
ADCINT
PIE
IMR
IFR
XINT1
XINT2
Level 1
IRQ GEN
SPIINT
RXINT
TXINT
CANMBINT
CANERINT
INT1
INT2
CMP1INT
CMP2INT
CMP3INT
CMP4INT
CMP5INT
CMP6INT
T1PINT
T1CINT
T1UFINT
T1OFINT
T3PINT
Level 2
IRQ GEN
T3CINT
T3UFINT
T3OFINT
CPU
T2PINT
T2CINT
INT3
T2UFINT
T2OFINT
T4PINT
Level 3
IRQ GEN
T4CINT
T4UFINT
T4OFINT
CAP1INT
CAP2INT
INT4
Level 4
IRQ GEN
CAP3INT
CAP4INT
CAP5INT
CAP6INT
SPIINT
RXINT
TXINT
INT5
Level 5
IRQ GEN
CANMBINT
CANERINT
INT6
ADCINT
XINT1
Level 6
IRQ GEN
XINT2
IACK
PIVR & Logic
PIRQR#
PIACK#
Data Bus
Addr Bus
Indicates change with respect to the TMS320F243/F241/C242 data sheets.
Interrupts from external interrupt pins. The remaining interrupts are internal to the peripherals.
Figure 2. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts
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interrupt request structure
Table 3. LF240xA/LC240xA Interrupt Source Priority and Vectors
CPU
INTERRUPT
AND
VECTOR
ADDRESS
BIT
PERIPHERAL
INTERRUPT
VECTOR
SOURCE
PERIPHERAL
MODULE
INTERRUPT OVERALL
MASK-
ABLE?
POSITION IN
PIRQRx AND
PIACKRx
DESCRIPTION
NAME
PRIORITY
(PIV)
RSN
0000h
RS pin,
Watchdog
Reset from pin, watchdog
timeout
Reset
1
2
3
N/A
N/A
N/A
N
N
N
−
Reserved
NMI
CPU
Emulator trap
0026h
NMI
0024h
Nonmaskable Nonmaskable interrupt,
Interrupt
software interrupt only
PDPINTA
PDPINTB
4
5
0.0
2.0
0020h
0019h
Y
Y
EVA
Power device protection
interrupt pins
EVB
ADC interrupt in
high-priority mode
ADCINT
XINT1
6
7
0.1
0.2
0004h
0001h
Y
Y
ADC
External
Interrupt Logic
External interrupt pins in high
priority
External
Interrupt Logic
XINT2
SPIINT
RXINT
8
9
0.3
0.4
0.5
0011h
0005h
0006h
Y
Y
Y
INT1
0002h
SPI
SCI
SPI interrupt pins in high priority
SCI receiver interrupt in
high-priority mode
10
SCI transmitter interrupt in
high-priority mode
TXINT
11
12
13
0.6
0.7
0.8
0007h
0040
0041
Y
Y
Y
SCI
CAN
CAN
CAN mailbox in high-priority
mode
CANMBINT
CANERINT
CAN error interrupt in
high-priority mode
CMP1INT
CMP2INT
CMP3INT
T1PINT
14
15
16
17
18
19
20
21
22
23
24
25
26
27
0.9
0.10
0.11
0.12
0.13
0.14
0.15
2.1
0021h
0022h
0023h
0027h
0028h
0029h
002Ah
0024h
0025h
0026h
002Fh
0030h
0031h
0032h
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EVA
EVA
EVA
EVA
EVA
EVA
EVA
EVB
EVB
EVB
EVB
EVB
EVB
EVB
Compare 1 interrupt
Compare 2 interrupt
Compare 3 interrupt
Timer 1 period interrupt
Timer 1 compare interrupt
Timer 1 underflow interrupt
Timer 1 overflow interrupt
Compare 4 interrupt
INT2
0004h
T1CINT
T1UFINT
T1OFINT
CMP4INT
CMP5INT
CMP6INT
T3PINT
2.2
Compare 5 interrupt
2.3
Compare 6 interrupt
2.4
Timer 3 period interrupt
Timer 3 compare interrupt
Timer 3 underflow interrupt
Timer 3 overflow interrupt
T3CINT
2.5
T3UFINT
T3OFINT
2.6
2.7
†
Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.
NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.
New peripheral interrupts and vectors with respect to the F243/F241 devices.
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interrupt request structure (continued)
Table 3. LF240xA/LC240xA Interrupt Source Priority and Vectors (Continued)
CPU
INTERRUPT
AND
VECTOR
ADDRESS
BIT
PERIPHERAL
INTERRUPT
VECTOR
SOURCE
PERIPHERAL
MODULE
INTERRUPT OVERALL
MASK-
ABLE?
POSITION IN
PIRQRx AND
PIACKRx
DESCRIPTION
NAME
PRIORITY
(PIV)
T2PINT
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
1.0
1.1
002Bh
002Ch
002Dh
002Eh
0039h
003Ah
003Bh
003Ch
0033h
0034h
0035h
0036h
0037h
0038h
0005h
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EVA
EVA
EVA
EVA
EVB
EVB
EVB
EVB
EVA
EVA
EVA
EVB
EVB
EVB
SPI
Timer 2 period interrupt
Timer 2 compare interrupt
Timer 2 underflow interrupt
Timer 2 overflow interrupt
Timer 4 period interrupt
Timer 4 compare interrupt
Timer 4 underflow interrupt
Timer 4 overflow interrupt
Capture 1 interrupt
T2CINT
T2UFINT
T2OFINT
T4PINT
1.2
1.3
INT3
0006h
2.8
T4CINT
2.9
T4UFINT
T4OFINT
CAP1INT
CAP2INT
CAP3INT
CAP4INT
CAP5INT
CAP6INT
SPIINT
2.10
2.11
1.4
1.5
Capture 2 interrupt
1.6
Capture 3 interrupt
INT4
0008h
2.12
2.13
2.14
1.7
Capture 4 interrupt
Capture 5 interrupt
Capture 6 interrupt
SPI interrupt (low priority)
SCI receiver interrupt
(low-priority mode)
RXINT
43
44
45
46
47
48
49
1.8
1.9
0006h
0007h
0040h
0041h
0004h
0001h
0011h
Y
Y
Y
Y
Y
Y
Y
SCI
SCI
SCI transmitter interrupt
(low-priority mode)
TXINT
INT5
000Ah
CAN mailbox interrupt
(low-priority mode)
CANMBINT
CANERINT
ADCINT
XINT1
1.10
1.11
1.12
1.13
1.14
CAN
CAN
ADC
CAN error interrupt
(low-priority mode)
ADC interrupt
(low priority)
External
Interrupt Logic
INT6
000Ch
External interrupt pins
(low-priority mode)
External
Interrupt Logic
XINT2
Reserved
TRAP
000Eh
0022h
N/A
N/A
Y
CPU
CPU
Analysis interrupt
TRAP instruction
N/A
N/A
N/A
Phantom
Interrupt
Vector
N/A
0000h
N/A
CPU
Phantom interrupt vector
INT8−INT16
N/A
N/A
0010h−0020h
N/A
N/A
N/A
N/A
CPU
CPU
†
Software interrupt vectors
INT20−INT31
00028h−0003Fh
†
Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.
NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.
New peripheral interrupts and vectors with respect to the F243/F241 devices.
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DSP CPU core
The 240xA devices use an advanced Harvard-type architecture that maximizes processing power by
maintaining two separate memory bus structures — program and data — for full-speed execution. This multiple
bus structure allows data and instructions to be read simultaneously. Instructions support data transfers
between program memory and data memory. This architecture permits coefficients that are stored in program
memory to be read in RAM, thereby eliminating the need for a separate coefficient ROM. This, coupled with a
four-deep pipeline, allows the LF240xA/LC240xA devices to execute most instructions in a single cycle. See
the functional block diagram of the 240xA DSP CPU for more information.
240xA instruction set
The 240xA microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or
external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.
addressing modes
The 240xA instruction set provides four basic memory-addressing modes: direct, indirect, immediate, and
register.
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.
Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each
page containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0−AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
scan-based emulation
x2xx devices incorporate scan-based emulation logic for code-development and hardware-
development support. Scan-based emulation allows the emulator to control the processor in the system without
the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx
by way of the IEEE 1149.1-compatible (JTAG) interface. The 240xA DSPs do not include boundary scan. The
scan chain of these devices is useful for emulation function only.
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functional block diagram of the 2407A DSP CPU
Program Bus
IS
DS
PS
MUX
R/W
STRB
READY
XF
XTAL1
CLKOUT
XTAL2
NPAR
16
PC
PAR
MSTACK
MUX
RD
RS
WE
Stack 8 × 16
MP/MC
XINT[1−2]
2
FLASH EEPROM/
ROM
Program Control
(PCTRL)
16
16
A15−A0
16
16
16
16
D15−D0
16
16
Data Bus
16
16
16
16
16
3
9
7
16
16
LSB
from
IR
AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)
DP(9)
16
MUX
MUX
16
ARP(3)
3
3
9
TREG0(16)
ARB(3)
Multiplier
3
ISCALE (0−16)
PREG(32)
32
16
PSCALE (−6,ā 0,ā 1,ā 4)
32
32
16
MUX
ARAU(16)
MUX
32
CALU(32)
32
32
16
Memory Map
Register
MUX
MUX
IMR (16)
IFR (16)
Data/Prog
DARAM
Data
C
ACCH(16)
ACCL(16)
32
GREG (16)
DARAM
B0 (256 × 16)
B2 (32 × 16)
B1 (256 × 16)
OSCALE (0−7)
16
MUX
16
16
16
NOTES: A. See Table 4 for symbol descriptions.
B. For clarity, the data and program buses are shown as single buses although they include address and data bits.
C. Refer to the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU
instruction set information.
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240xA legend for the internal hardware
Table 4. Legend for the 240xA DSP CPU Internal Hardware
SYMBOL
NAME
DESCRIPTION
32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities
ACC
Accumulator
Auxiliary Register
Arithmetic Unit
An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
and outputs
ARAU
These 16-bit registers are used as pointers to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used
as an index value for AR updates of more than one and as a compare value to AR.
AUX
REGS
Auxiliary Registers
0−7
Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit
resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.
C
Carry
32-bit-wide main arithmetic logic unit for the C2xx core. The CALU executes 32-bit operations in a single
machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and provides
status results to PCTRL.
Central Arithmetic
Logic Unit
CALU
If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM
(DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2
are mapped to data memory space only, at addresses 0300−03FF and 0060−007F, respectively. Blocks 0
and 1 contain 256 words, while block 2 contains 32 words.
DARAM
Dual-Access RAM
Data Memory
Page Pointer
The 9-bit DP register is concatenated with the seven least significant bits (LSBs) of an instruction word to
form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions.
DP
Global Memory
Allocation
Register
GREG specifies the size of the global data memory space. Since the global memory space is not used in
the 240xA devices, this register is reserved.
GREG
IMR
Interrupt Mask
Register
IMR individually masks or enables the seven interrupts.
Interrupt Flag
Register
IFR
The 7-bit IFR indicates that the C2xx has latched an interrupt from one of the seven maskable interrupts.
A total of 32 interrupts by way of hardware and/or software are available.
INT#
Interrupt Traps
Input Data-Scaling 16- to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit
ISCALE
Shifter
output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.
16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
signed or unsigned 2s-complement arithmetic multiply.
MPY
Multiplier
MSTACK provides temporary storage for the address of the next instruction to be fetched when program
address-generation logic is used to generate sequential addresses in data space.
MSTACK
MUX
Micro Stack
Multiplexer
Multiplexes buses to a common input
Next Program
Address Register
NPAR
NPAR holds the program address to be driven out on the PAB in the next cycle.
Output
Data-Scaling
Shifter
16- to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization
management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data
bus (DWEB).
OSCALE
Program Address
Register
PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory
operations scheduled for the current bus cycle.
PAR
PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
data-transfer operations.
PC
Program Counter
Program
Controller
PCTRL
PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
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240xA legend for the internal hardware (continued)
Table 4. Legend for the 240xA DSP CPU Internal Hardware (Continued)
SYMBOL
NAME
DESCRIPTION
32-bit register holds results of 16 × 16 multiply
PREG
Product Register
0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
32-bit product shifter and from either the CALU or the data-write data bus (DWEB), and requires no cycle
overhead.
Product-Scaling
Shifter
PSCALE
STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
routines, or for storing data. The C2xx stack is 16 bits wide and 8 levels deep.
STACK
TREG
Stack
Temporary
Register
16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.
status and control registers
Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can
be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved
and restored for subroutines.
The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST)
instruction is used to read from ST0 and ST1 — except for the INTM bit, which is not affected by the LST
instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC
instructions. Figure 3 shows the organization of status registers ST0 and ST1, indicating all status bits contained
in each. Several bits in the status registers are reserved and are read as logic 1s. Table 5 lists status register
field definitions.
15
13
12
11
10
1
9
8
0
ST0
ST1
ARP
ARB
OV
OVM
INTM
DP
15
13
12
11
10
9
8
1
7
1
6
1
5
1
4
3
1
2
1
1
0
CNF
TC
SXM
C
XF
PM
Figure 3. Organization of Status Registers ST0 and ST1
Table 5. Status Register Field Definitions
FIELD
FUNCTION
Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST
instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP.
ARB
Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value
is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the
LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed.
ARP
Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow.
Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these
cases, ADD can only set and SUB can only reset the carry bit, but cannot affect it otherwise. The single-bit shift and rotate
instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch
on the status of C. C is set to 1 on a reset.
C
On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data
space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1
instructions. RS sets the CNF to 0.
CNF
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
status and control registers (continued)
Table 5. Status Register Field Definitions (Continued)
FIELD
DP
FUNCTION
Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory
address of 16 bits. DP can be modified by the LST and LDP instructions.
Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled.
INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS also sets INTM. INTM has no effect on the unmaskable
RS and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when
a maskable interrupt trap is taken.
INTM
Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an
overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV.
OV
Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator
is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset
this bit, respectively. LST can also be used to modify the OVM.
OVM
Product shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG
output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, the PREG output is left-shifted by 4 bits
and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of 6 bits, sign-extended. Note that the PREG
contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the
SPM and LST #1 instructions. PM is cleared by RS.
PM
Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter.
SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction
suppresses sign extension regardless of SXM. SXM is set by the SETC SXM instruction and reset by the CLRC SXM instruction
and can be loaded by the LST #1 instruction. SXM is set to 1 by reset.
SXM
Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT
or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the 2 most
significant bits (MSBs) of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return
instructions can execute based on the condition of TC.
TC
XF
XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF instruction and reset
by the CLRC XF instruction. XF is set to 1 by reset.
central processing unit
The 240xA central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel multiplier, a 32-bit
central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the outputs of both the
accumulator and the multiplier. This section describes the CPU components and their functions. The functional
block diagram shows the components of the CPU.
input scaling shifter
The 240xA provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output connected
to the CALU. This shifter operates as part of the path of data coming from program or data space to the CALU
and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit CALU. This
is necessary for scaling arithmetic as well as aligning masks for logical operations.
The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;
the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit
(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the
instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment
operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to
the system’s performance.
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multiplier
The x240xA devices use a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned
32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned)
instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as
2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated
with the multiplier, as follow:
D
D
16-bit temporary register (TREG) that holds one of the operands for the multiplier
32-bit product register (PREG) that holds the product
Four product-shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.
The PM field of status register ST1 specifies the PM shift mode, as shown in Table 6.
Table 6. PSCALE Product-Shift Modes
PM
00
SHIFT
No shift
Left 1
DESCRIPTION
Product feed to CALU or data bus with no shift
01
Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product
Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product when
using the multiply-by-a-13-bit constant
10
11
Left 4
Right 6
Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow
The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with
a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number
by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to
128 consecutive multiply/accumulates without the possibility of overflow.
The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY
(multiply) instruction provides the second operand (also from the data bus). A multiplication also can be
performed with a 13-bit immediate operand when using the MPY instruction. Then, a product is obtained every
two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining
of the TREG load operations with CALU operations using the previous product. The pipeline operations that
run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG
to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC
(LTS).
Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle
multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient
addresses are generated by program address generation (PAGEN) logic, while the data addresses are
generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values
from the coefficient table sequentially and step through the data in any of the indirect addressing modes.
The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the
sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to
throw away the oldest sample.
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multiplier (continued)
The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision
arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed
data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits
to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The
SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the
multiplier for squaring a data memory value.
After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register
(PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store
product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data
bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This
is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot
be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product
register can be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high
half, then, is loaded using the LPH instruction.
central arithmetic logic unit
The x240xA central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical functions,
the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate it from
a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU). Once
an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional
operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming
from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier.
The CALU is a general-purpose ALU that operates on 16-bit words taken from data memory or derived from
immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean
operations, facilitating the bit-manipulation ability required for a high-speed controller. One input to the CALU
is always provided from the accumulator, and the other input can be provided from the product register (PREG)
of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After
the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.
The x240xA devices support floating-point operations for applications requiring a large dynamic range. The
NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by
performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the
LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions. These
instructions are useful in floating-point arithmetic where a number needs to be denormalized — that is,
floating-point to fixed-point conversion. They are also useful in the execution of an automatic gain control (AGC)
going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based
on the value contained in the four LSBs of TREG.
The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When
the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator
is loaded with either the most positive or the most negative value representable in the accumulator, depending
on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or
080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the
overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result
in overflow.)
The CALU can execute a variety of branch instructions that depend on the status of the CALU and the
accumulator. These instructions can be executed conditionally based on any meaningful combination of these
status bits. For overflow management, these conditions include OV (branch on overflow) and EQ (branch on
accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the
ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and
BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
26
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central arithmetic logic unit (continued)
The CALU also has an associated carry bit that is set or reset depending on various operations within the device.
The carry bit allows more efficient computation of extended-precision products and additions or subtractions.
It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the
single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other
such non-arithmetic or control instructions.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use
the previous value of carry in their addition/subtraction operation.
The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high
accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the
ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset
the carry bit only if a borrow is generated; otherwise, neither instruction affects it.
Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing,
based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the
carry bit. The carry bit is set to one on a hardware reset.
accumulator
The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage
in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is
performed while the data is being transferred to the data bus for storage. The contents of the accumulator
remain unchanged. When the postscaling shifter is used on the high word of the accumulator (bits 16−31), the
MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0−15). When the postscaling
shifter is used on the low word, the LSBs are zero-filled.
The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the
left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The
SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an
arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift,
shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected
by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT)
instructions can be used with the shift and rotate instructions for multiple-bit shifts.
auxiliary registers and auxiliary-register arithmetic unit (ARAU)
The 240xA provides a register file containing eight auxiliary registers (AR0−AR7). The auxiliary registers are
used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register
addressing allows placement of the data memory address of an instruction operand into one of the auxiliary
registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value
from 0 through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded
from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The
contents of these registers also can be stored in data memory or used as inputs to the CALU.
The auxiliary register file (AR0−AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary
register while the data memory location is being addressed. Indexing either by 1 or by the contents of the AR0
register can be performed. As a result, accessing tables of information does not require the CALU for address
manipulation; therefore, the CALU is free for other operations in parallel.
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
internal memory
The 320x240xA devices are configured with the following memory modules:
D
D
D
D
D
Dual-access random-access memory (DARAM)
Single-access random-access memory (SARAM)
Flash
ROM
Boot ROM
dual-access RAM (DARAM)
There are 544 words × 16 bits of DARAM on the 240xA devices. The 240xA DARAM allows writes to and reads
from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and
block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in
data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program
memory space. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data
memory) instructions allow dynamic configuration of the memory maps through software.
When using on-chip RAM, the 240xA runs at full speed with no wait states. The ability of the DARAM to allow
two accesses to be performed in one cycle, coupled with the parallel nature of the 240xA architecture, enables
the device to perform three concurrent memory accesses in any given machine cycle. Externally, the READY
line or on-chip software wait-state generator can be used to interface the 2407A to slower, less expensive
external memory.
single-access RAM (SARAM)
†
There are 2K words × 16 bits of SARAM on the 2407A. The PON and DON bits select SARAM (2K) mapping
in program space, data space, or both. See Table 18 for details on the SCSR2 register and the PON and DON
bits. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program and data spaces. The
SARAM (starting at 8000h in program memory) is accessible in external memory space, if the on-chip SARAM
is not enabled.
flash EEPROM
Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, Flash is nonvolatile.
However, it has the advantage of “in-target” reprogrammability. The LF2407A incorporates one 32K ꢀ 16-bit
Flash EEPROM module in program space. The Flash module has multiple sectors that can be individually
protected while erasing or programming. The sector size is non-uniform and partitioned as 4K/12K/12K/4K
sectors.
Unlike most discrete Flash memory, the LF240xA Flash does not require a dedicated state machine, because
the algorithms for programming and erasing the Flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
‡
the IEEE Standard 1149.1 (JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and Flash code. This Flash requires 5 V for programming (at V
at zero wait state while the device is powered at 3.3 V.
pin only) the array. The Flash runs
CCP
†
‡
See Table 1 for device-specific features.
IEEE Standard 1149.1−1990, IEEE Standard Test Access Port.
28
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
boot ROM
Boot ROM is a 256-word ROM memory-mapped in program space 0000−00FF. This ROM will be enabled if the
BOOT_EN pin is low during reset. The BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if the BOOT_EN
pin is low at reset. Boot ROM can also be enabled by writing 0 to the SCSR2.3 bit and disabled by writing 1 to
this bit.
The boot ROM has a generic bootloader to transfer code through SCI or SPI ports. The incoming code should
disable the BOOT_ROM bit by writing 1 to bit 3 of the SCSR2 register, or else, the whole Flash array will not
be enabled.
The boot ROM code sets the PLL to x2 or x4 option based on the condition of the SCITXD pin during reset. The
SCITXD pin should be pulled high/low to select the PLL multiplication factor. The choices made are as follows:
D
D
D
If the SCITXD pin is pulled low, the PLL multiplier is set to 2.
If the SCITXD pin is pulled high, the PLL multiplier is set to 4. (Default)
If the SCITXD pin is not driven at reset, the internal pullup selects the default multiplier of 4.
Care should be taken such that a combination of CLKIN and the PLL multiplication factor should not result in
a CPU clock speed of greater than 40 MHz, the maximum rated speed.
Furthermore, when the bootloader is used, only specific values of CLKIN would result in a baud-lock for the SCI.
Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature
number SPRU357) for more details about the bootloader operation.
29
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
flash/ROM security
240xA devices incorporate a security feature that prevents external access to program memory. This feature
is useful in preventing unauthorized duplication of proprietary code.
If access to Flash/ROM contents are desired for debugging purposes, two actions need to be taken:
1. A “dummy” read of locations 40h, 41h, 42h and 43h (of program memory space) is necessary. The word
“dummy” indicates that the destination address of this read is insignificant.
NOTE: Step 2 is not required if 40h−43h contain 0000 0000 0000 0000h or FFFF FFFF FFFF FFFFh.
2. A 64-bit password (split as four 16-bit words) must be written to the data-memory locations 77F0h, 77F1h,
77F2h, and 77F3h. The four 16-bit words written to these locations must match the four words stored in 40h,
41h, 42h, and 43h (of program memory space), respectively. The device becomes “unsecured” one cycle
after the last instruction that unsecures the part.
Code Security Module Disclaimer
The Code Security Module (“CSM”) included on this device was designed to password
protect the data stored in the associated memory (either ROM or Flash) and is warranted
by Texas Instruments (TI), in accordance with its standard terms and conditions, to
conform to TI’s published specifications for the warranty period applicable for this device.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE
ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.
MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING
IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
30
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PERIPHERALS
The integrated peripherals of the 240xA are described in the following subsections:
D
D
D
D
D
D
D
D
D
Two event-manager modules (EVA, EVB)
Enhanced analog-to-digital converter (ADC) module
Controller area network (CAN) module
Serial communications interface (SCI) module
Serial peripheral interface (SPI) module
PLL-based clock module
Digital I/O and shared pin functions
External memory interfaces
Watchdog (WD) timer module
event manager modules (EVA, EVB)
The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and
quadrature-encoder pulse (QEP) circuits. EVA’s and EVB’s timers, compare units, and capture units function
identically. However, timer/unit names differ for EVA and EVB. Table 7 shows the module and signal names
used. Table 7 shows the features and functionality available for the event-manager modules and highlights EVA
nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting
at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and
QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however,
module/signal names would differ.
Table 7. Module and Signal Names for EVA and EVB
EVA
EVB
EVENT MANAGER MODULES
MODULE
SIGNAL
MODULE
SIGNAL
Timer 1
Timer 2
T1PWM/T1CMP
T2PWM/T2CMP
Timer 3
Timer 4
T3PWM/T3CMP
T4PWM/T4CMP
GP Timers
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare 4
Compare 5
Compare 6
PWM7/8
PWM9/10
PWM11/12
Compare Units
Capture Units
Capture 1
Capture 2
Capture 3
CAP1
CAP2
CAP3
Capture 4
Capture 5
Capture 6
CAP4
CAP5
CAP6
QEP1
QEP2
QEP1
QEP2
QEP3
QEP4
QEP3
QEP4
QEP
Direction
External Clock
TDIRA
TCLKINA
Direction
External Clock
TDIRB
TCLKINB
External Inputs
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event manager modules (EVA, EVB) (continued)
240xA DSP Core
Data Bus
ADDR Bus Reset
16
Clock
INT2,3,4
3
16
16
EV Control Registers
and Control Logic
ADC Start of
Conversion
Output
Logic
16
16
GP Timer 1
Compare
T1PWM/
T1CMP
TDIRA
TCLKINA
GP Timer 1
Prescaler
CLKOUT
(Internal)
16
16
T1CON[4,5]
T1CON[8,9,10]
PWM1
PWM6
SVPWM
State
3
3
3
Full-Compare
Units
Deadband
Units
Output
Logic
Machine
16
16
T2PWM/
T2CMP
Output
Logic
GP Timer 2
Compare
TCLKINA
Prescaler
GP Timer 2
CLKOUT
(Internal)
T2CON[8,9,10]
T2CON[4,5]
16
TDIRA
DIR
16
Clock
QEP
Circuit
CAPCONA[14,13]
MUX
2
2
CAP1/QEP1
CAP2/QEP2
2
16
Capture Units
CAP3
16
Figure 4. Event Manager A Block Diagram
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general-purpose (GP) timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
D
D
D
D
D
D
D
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-control register,TxCON, for reads or writes
Selectable internal or external input clocks
A programmable prescaler for internal or external clock inputs
Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
D
A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There are
three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or
external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time
base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1
for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare
registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as
needed.
full-compare units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time
base and generate six outputs for compare and PWM-waveform generation using programmable deadband
circuit. The state of each of the six outputs is configured independently. The compare registers of the compare
units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
programmable deadband generator
The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband
values (from 0 to 16 µs) can be programmed into the compare register for the outputs of the three compare units.
The deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output
signal. The output states of the deadband generator are configurable and changeable as needed by way of the
double-buffered ACTR register.
PWM waveform generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two
independent PWMs by the GP-timer compares.
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PWM characteristics
Characteristics of the PWMs are as follows:
D
D
D
D
D
D
D
16-bit registers
Programmable deadband for the PWM output pairs, from 0 to 12 µs
Minimum deadband width of 25 ns
Change of the PWM carrier frequency for PWM frequency wobbling as needed
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
D
Minimized CPU overhead using auto-reload of the compare and period registers
D
The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx
signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.
−
−
PDPINTA pin status is reflected in bit 8 of COMCONA register.
PDPINTB pin status is reflected in bit 8 of COMCONB register.
capture unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three
capture circuits.
Capture units include the following features:
D
D
D
D
D
One 16-bit capture control register, CAPCONx (R/W)
One 16-bit capture FIFO status register, CAPFIFOx
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All inputs
are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold
at its current level to meet two rising edges of the device clock. The input pins CAP1/2 and CAP4/5 can also
be used as QEP inputs to the QEP circuit.]
D
D
User-specified transition (rising edge, falling edge, or both edges) detection
Three maskable interrupt flags, one for each capture unit
quadrature-encoder pulse (QEP) circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.
Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented
by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
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input qualifier circuitry
An input-qualifier circuitry qualifies the input signal to the CAP1−6, XINT1/2, ADCSOC and PDPINTA/B pins
in the 240xA devices. (The I/O functions of these pins do not use the input-qualifier circuitry). The state of the
internal input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch
smaller than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin
high/low for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls
whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches. On the
LC2402A, input qualification is for the CAP1, CAP2, CAP3, PDPINTA, and XINT2/ADCSOC pins.
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 5. The ADC module consists of a
10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
D
D
D
10-bit ADC core with built-in S/H
16-channel, MUXed inputs
Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
D
D
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
−
The digital value of the input analog voltage is derived by:
Input Analog Voltage * VREFLO
Digital Value + 1023
VREFHI * VREFLO
D
Multiple triggers as sources for the start-of-conversion (SOC) sequence
−
−
−
−
S/W − software immediate start
EVA − Event manager A (multiple event sources within EVA)
EVB − Event manager B (multiple event sources within EVB)
Ext − External pin (ADCSOC)
D
D
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
D
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
D
NOTE: The calibration and self-test features are not present in 240xA devices.
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enhanced analog-to-digital converter (ADC) module (continued)
The ADC module in the 240xA has been enhanced to provide flexible interface to event managers A and B. The
ADC interface is built around a fast, 10-bit ADC module with a total minimum conversion time of 375 ns
(S/H + conversion). The ADC module has 16 channels, configurable as two independent 8-channel modules
to service event managers A and B. The two independent 8-channel modules can be cascaded to form a
16-channel module. Although there are multiple input channels and two sequencers, there is only one converter
in the ADC module. Figure 5 shows the block diagram of the 240xA ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has the
choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded
mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the
conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing
allows the system to convert the same channel multiple times, allowing the user to perform oversampling
algorithms. This gives increased resolution over traditional single-sampled conversion results.
Result Registers
Analog MUX
70A8h
Result Reg 0
Result Reg 1
ADCIN00
10-Bit
ADC
Module
ADCIN07
ADCIN08
Result Reg 7
Result Reg 8
70AFh
70B0h
(375 ns MIN)
ADCIN15
Result Reg 15
70B7h
ADC Control Registers
S/W
EVA
ADCSOC
S/W
EVB
SOC
SOC
Sequencer 1
Sequencer 2
Figure 5. Block Diagram of the 240xA ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCINn pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (such as V
digital supply.
, V
, and V
) from the
CCA REFHI
SSA
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controller area network (CAN) module
The CAN module is a full-CAN controller designed as a 16-bit peripheral module and supports the following
features:
D
CAN specification 2.0B (active)
−
−
Standard data and remote frames
Extended data and remote frames
D
Six mailboxes for objects of 0- to 8-byte data length
−
−
Two receive mailboxes, two transmit mailboxes
Two configurable transmit/receive mailboxes
D
D
D
D
D
D
Local acceptance mask registers for mailboxes 0 and 1 and mailboxes 2 and 3
Configurable standard or extended message identifier
Programmable bit rate
Programmable interrupt scheme
Readable error counters
Self-test mode
−
In this mode, the CAN module operates in a loop-back fashion, receiving its own transmitted message.
The CAN module is a 16-bit peripheral. The accesses are split into the control/status-registers accesses and
the mailbox-RAM accesses.
CAN peripheral registers: The CPU can access the CAN peripheral registers only using 16-bit write accesses.
The CAN peripheral always presents full 16-bit data to the CPU bus during read cycles.
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
controller area network (CAN) module (continued)
CAN controller architecture
Figure 6 shows the basic architecture of the CAN controller through this block diagram of the CAN Peripherals.
CAN Module
Transmit Buffer
Control/Status Registers
Interrupt Logic
CANTX
Control Bus
CAN
CAN
Core
CPU Interface/
Memory Management Unit
CPU
Transceiver
CANRX
Temporary Receive Buffer
mailbox 0
mailbox 1
mailbox 2
mailbox 3
mailbox 4
mailbox 5
R
Data
ID
R
T/R
T/R
T
T
Matchid
Acceptance Filter
Control Logic
RAM 48x16
Figure 6. CAN Module Block Diagram
The mailboxes are situated in one 48-word x 16-bit RAM. It can be written to or read by the CPU or the CAN.
The CAN write or read access, as well as the CPU read access, needs one clock cycle. The CPU write access
needs two clock cycles. In these two clock cycles, the CAN performs a read-modify-write cycle and, therefore,
inserts one wait state for the CPU.
Address bit 0 of the address bus used when accessing the RAM decides if the lower (0) or the higher (1)
16-bit word of the 32-bit word is taken. The RAM location is determined by the upper bits 5 to 1 of the address
bus.
Table 8. 3.3-V CAN Transceivers for the 320Lx240xA DSPs
INTEGRATED
SLOPE CON-
TROL
†
PART NUMBER
LOW-POWER MODE
V
ref
PIN
T
A
MARKED AS
SN65HVD230QDRQ1
SN65HVD231QDRQ1
370 µA standby mode
Yes
Yes
No
Yes
230Q1
231Q1
232Q1
40 nA sleep mode
Yes
No
−40°C to 125°C
SN65HVD232QDRQ1 No standby or sleep mode
†
This is the nomenclature printed on the device, since the footprint is too small to accommodate the entire part number.
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CAN interrupt logic
There are two interrupt requests from the CAN module to the peripheral interrupt expansion (PIE) controller:
the mailbox interrupt and the error interrupt. Both interrupts can assert either a high-priority request or a
low-priority request to the CPU. Since CAN mailboxes can generate multiple interrupts, the software should
read the CAN_IFR register for every interrupt and prioritize the interrupt service, or else, these multiple
interrupts will not be recognized by the CPU and PIE hardware logic. Each interrupt routine should service all
the interrupt bits that are set and clear them after service.
serial communications interface (SCI) module
The 240xA devices include a serial communications interface (SCI) module. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of the SCI module include:
D
Two external pins:
−
−
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
D
D
Baud rate programmable to 64K different rates
Up to 2500 Kbps at 40-MHz CPUCLK
Data-word format
−
−
−
−
−
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
D
D
D
D
D
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
−
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
−
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
D
D
D
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing to the upper byte has no effect.
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
serial communications interface (SCI) module (continued)
Figure 7 shows the SCI module block diagram.
SCI TX Interrupt
TXRDY
SCITXBUF.7−0
TXWAKE
TX INT ENA
TXINT
Transmitter-Data
Buffer Register
Frame Format and Mode
SCICTL1.3
External
SCICTL2.7
Connections
1
SCICTL2.0
Parity
TX EMPTY
8
Even/Odd Enable
SCICTL2.6
SCICCR.6 SCICCR.5
WUT
TXENA
TXSHF
Register
SCITXD
SCITXD
SCICTL1.1
SCIHBAUD. 15−8
SCI Priority Level
1
Baud Rate
MSbyte
Register
Level 5 Int.
0
Level 1 Int.
Internal
Clock
SCI TX
Priority
SCILBAUD. 7−0
SCIPRI.6
Baud Rate
LSbyte
Register
1
Level 5 Int.
0
Level 1 Int.
SCI RX
Priority
SCIPRI.5
SCIRXD
RXSHF
Register
SCIRXD
RXWAKE
SCIRXST.1
RXENA
RX ERR INT ENA
SCICTL1.0
SCICTL1.6
SCI RX Interrupt
8
RXRDY
RX/BK INT ENA
Receiver-Data
Buffer
SCIRXST.6
RX Error
Register
SCICTL2.1
BRKDT
SCIRXST.5
SCIRXBUF.7−0
SCIRXST.7
RX Error
SCIRXST.4−2
FE OE PE
Figure 7. Serial Communications Interface (SCI) Module Block Diagram
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serial peripheral interface (SPI) module
Some 240xA devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted
into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications
between the DSP controller and external peripherals or another processor. Typical applications include external
I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice
communications are supported by the master/slave operation of the SPI.
The SPI module features include:
D
Four external pins:
−
−
−
−
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
D
D
D
D
Two operational modes: master and slave
Baud rate: 125 different programmable rates/10 Mbps at 40-MHz CPUCLK
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
−
−
−
−
Falling edge without phase delay: SPICLK active high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
D
D
D
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE: All registers in this module are 16-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing to the upper byte has no effect.
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
serial peripheral interface (SPI) module (continued)
Figure 8 is a block diagram of the SPI in slave mode.
SPIRXBUF.15−0
Overrun
INT ENA
Receiver
Overrun Flag
SPIRXBUF
SPI Priority
Buffer Register
SPISTS.7
0
1
Level 1
INT
Level 5
INT
SPIPRI.6
To CPU
SPICTL.4
SPITXBUF.15−0
16
SPITXBUF
SPI INT
ENA
Buffer Register
External
Connections
SPI INT FLAG
SPISTS.6
16
SPICTL.0
SW1
M
M
SPIDAT
S
M
S
Data Register
S
SPISIMO
SPISOMI
M
SPIDAT.15−0
SW2
S
Talk
SPICTL.1
†
SPISTE
State Control
Master/Slave
SPICTL.2
SPICCR.3−0
SPI Char
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
Internal
Clock
SPICCR.6
SPICTL.3
SPICLK
SPIBRR.6−0
M
6
5
4
3
2
1
0
NOTE A: The diagram is shown in the slave mode.
†
The SPISTE pin is driven low externally. Note that SW1, SW2, and SW3 are closed in this configuration. Refer to the following erratas for
restrictions on using the SPISTE pin:
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A DSP Controllers Silicon Errata
(literature number SPRZ002)
Figure 8. Four-Pin Serial Peripheral Interface Module Block Diagram
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PLL-based clock module
The 240xA has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different
CPU clock rates. See Figure 9 for the PLL Clock Module Block Diagram, Table 9 for clock rates, and Table 10
for the loop filter component values.
The PLL-based clock module provides two modes of operation:
D
D
Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the
XTAL1/CLKIN pin.
XTAL1/CLKIN
C
C
b1
b2
RESONATOR/
CRYSTAL
XTAL2
PLLF
F
in
PLL
CLKOUT
R
1
XTAL
OSC
C
2
3-bit
C
1
PLL Select
(SCSR1.[11:9])
PLLF2
Figure 9. PLL Clock Module Block Diagram
Table 9. PLL Clock Selection Through Bits (11−9) in SCSR1 Register
CLK PS2
CLK PS1
CLK PS0
CLKOUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4 × F
2 × F
in
in
1.33 × F
in
1 × F
in
0.8 × F
in
0.66 × F
0.57 × F
in
in
0.5 × F
in
Default multiplication factor after reset is (1,1,1), i.e., 0.5 × F .
in
CAUTION:
The bootloader sets the PLL to x2 or x4 option. If the bootloader is used, the value of CLKIN
used should not force CLKOUT to exceed the maximum rated device speed. See the “Boot
ROM” section for more details.
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external reference crystal clock option
The internal oscillator is enabled by connecting a crystal across the XTAL1/CLKIN and XTAL2 pins as shown
in Figure 10a. The crystal should be in fundamental operation and parallel resonant, with an effective series
resistance of 30 Ω−150 Ω and a maximum power dissipation of 1 mW; it should be specified at a load
capacitance of 20 pF.
external reference oscillator clock option
The internal oscillator is disabled by connecting a clock signal to XTAL1/CLKIN and leaving the XTAL2 input
pin unconnected as shown in Figure 10b.
XTAL1/CLKIN
b1
XTAL2
XTAL1/CLKIN
XTAL2
External Clock Signal
(Toggling 0−3.3 V)
C
C
b2
(see Note A)
(see Note A)
Crystal
(a)
NC
(b)
NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The
resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding
the proper tank component values that will ensure start-up and stability over the entire operating range.
Figure 10. Recommended Crystal/Clock Connection
loop filter
The PLL module uses an external loop filter circuit for jitter minimization. The components for the loop filter
circuit are R1, C1, and C2. The capacitors (C1 and C2) must be non-polarized. This loop filter circuit is connected
between the PLLF and PLLF2 pins (see Figure 9). For examples of component values of R1, C1, and C2 at a
specified oscillator frequency (XTAL1), see Table 10.
Table 10. Loop Filter Component Values With Damping Factor = 2.0
XTAL1/CLKIN FREQUENCY
R1 (Ω) ( 5% TOLERANCE)
C1 (µF) ( 20% TOLERANCE)
C2 (µF) ( 20% TOLERANCE)
(MHz)
4
4.7
5.6
6.8
8.2
9.1
10
11
3.9
2.7
0.082
0.056
0.039
0.033
0.022
0.015
0.015
0.012
0.01
5
6
1.8
7
1.5
8
1
9
0.82
0.68
0.56
0.47
0.39
0.33
0.33
0.27
0.22
0.22
0.18
0.15
10
11
12
13
14
15
16
17
18
19
20
12
13
15
15
16
18
18
20
22
24
0.0082
0.0068
0.0068
0.0056
0.0047
0.0047
0.0039
0.0033
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low-power modes
The 240xA has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the
CPU, but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down
to save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if
it is reset, or, if it receives an interrupt request.
clock domains
All 240xA-based devices have two clock domains:
1. CPU clock domain − consists of the clock for most of the CPU logic
2. System clock domain − consists of the peripheral clock (which is derived from CLKOUT of the CPU) and
the clock for the interrupt logic in the CPU.
When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues
to run. This mode is also known as IDLE1 mode. The 240xA CPU also contains support for a second IDLE mode,
IDLE2. By asserting IDLE2 to the 240xA CPU, both the CPU clock domain and the system clock domain are
stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the
oscillator and WDCLK are also shut down when in IDLE2 mode.
Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the
IDLE instruction is executed (see Table 11). These bits are located in the System Control and Status
Register 1 (SCSR1), and they are described in the TMS320LF/LC240xA DSP Controllers Reference Guide:
System and Peripherals (literature number SPRU357).
Table 11. Low-Power Modes Summary
LPMx BITS
SCSR1
[13:12]
CPU
CLOCK
DOMAIN
SYSTEM
CLOCK
DOMAIN
WDCLK
STATUS
PLL
STATUS
OSC
STATUS
FLASH
POWER
EXIT
CONDITION
LOW-POWER MODE
CPU running normally
XX
On
Off
On
On
On
On
On
On
On
On
—
Peripheral
Interrupt,
External Interrupt,
Reset,
IDLE1 − (LPM0)
IDLE2 − (LPM1)
00
On
On
PDPINTA/B
Wakeup
Interrupts,
External Interrupt,
Reset,
01
1X
Off
Off
Off
Off
On
Off
On
Off
On
Off
On
PDPINTA/B
HALT − (LPM2)
[PLL/OSC power down]
Reset,
PDPINTA/B
†
Off
†
The Flash must be powered down by the user code prior to entering LPM2. For more details, see the TMS320LF/LC240xA DSP Controllers
Reference Guide: System and Peripherals (literature number SPRU357).
other power-down options
240xA devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, SPI, CAN, EVB, and EVA.
Clock to these peripherals are disabled after reset; thus, start-up power can be low for the device.
Depending on the application, these peripherals can be turned on/off to achieve low power.
Refer to the SCSR1 register for details on the peripheral clock enable bits.
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digital I/O and shared pin functions
The 240xA has up to 41 general-purpose, bidirectional, digital I/O (GPIO) pins—most of which are shared
between primary functions and I/O. Most I/O pins of the 240xA are shared with other functions. The digital I/O
ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and
shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:
D
D
Output Control Registers — used to control the multiplexer selection that chooses between the primary
function of a pin or the general-purpose I/O function.
Data and Control Registers — used to control the data and data direction of bidirectional I/O pins.
description of shared I/O pins
The control structure for shared I/O pins is shown in Figure 11, where each pin has three bits that define its
operation:
D
D
MUX control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.
I/O direction bit — if the I/O function is selected for the pin (MUX control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).
D
I/O data bit — if the I/O function is selected for the pin (MUX control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.
The MUX control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
IOP Data Bit
(Read/Write)
Primary
Function
Primary
Function
(Output Section)
(Input Section)
In
Out
IOP DIR Bit
0 = Input
1 = Output
MUX Control Bit
0 = I/O Function
0
1
1 = Primary Function
Pullup
or
Pulldown
(Internal)
Primary
Function
or I/O Pin
Pin
Figure 11. Shared Pin Configuration
A summary of shared pin configurations and associated bits is shown in Table 12.
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description of shared I/O pins (continued)
Table 12. Shared Pin Configurations
†
‡
MUX
PIN FUNCTION SELECTED
I/O PORT DATA AND DIRECTION
MUX CONTROL
VALUE AT RESET
(MCRx.n)
CONTROL
REGISTER
(name.bit #)
(MCRx.n = 1)
(MCRX.N = 0)
§
¶
REGISTER
DATA BIT NO.
DIR BIT NO.
Primary Function
I/O
PORT A
SCITXD
SCIRXD
XINT1
IOPA0
IOPA1
IOPA2
IOPA3
IOPA4
IOPA5
IOPA6
IOPA7
MCRA.0
MCRA.1
MCRA.2
MCRA.3
MCRA.4
MCRA.5
MCRA.6
MCRA.7
0
0
0
0
0
0
0
0
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PORT B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CAP1/QEP1
CAP2/QEP2
CAP3
PWM1
PWM2
PWM3
PWM4
IOPB0
IOPB1
IOPB2
IOPB3
IOPB4
IOPB5
IOPB6
IOPB7
MCRA.8
MCRA.9
0
0
0
0
0
0
0
0
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PORT C
0
1
2
3
4
5
6
7
8
9
PWM5
MCRA.10
MCRA.11
MCRA.12
MCRA.13
MCRA.14
MCRA.15
10
11
12
13
14
15
PWM6
T1PWM/T1CMP
T2PWM/T2CMP
TDIRA
TCLKINA
#
W/R
IOPC0
IOPC1
IOPC2
IOPC3
IOPC4
IOPC5
IOPC6
IOPC7
MCRB.0
MCRB.1
MCRB.2
MCRB.3
MCRB.4
MCRB.5
MCRB.6
MCRB.7
1
1
0
0
0
0
0
0
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PCDATDIR
PORT D
0
1
2
3
4
5
6
7
8
BIO
9
SPISIMO
SPISOMI
SPICLK
SPISTE
CANTX
CANRX
10
11
12
13
14
15
XINT2/ADCSOC
EMU0
EMU1
TCK
IOPD0
MCRB.8
||
MCRB.9
||
MCRB.10
0
1
1
1
1
1
1
1
PDDATDIR
PDDATDIR
PDDATDIR
PDDATDIR
PDDATDIR
PDDATDIR
PDDATDIR
PDDATDIR
0
1
2
3
4
5
6
7
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
9
10
11
12
13
14
15
||
MCRB.11
MCRB.12
MCRB.13
MCRB.14
MCRB.15
||
||
||
||
TDI
TDO
TMS
TMS2
†
‡
§
¶
#
||
Bold, italicized pin names indicate pin functions at reset.
Valid only if the I/O function is selected on the pin
If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.
If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode.
Note that bits 15 through 9 of the MCRB register must be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation
of the device.
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description of shared I/O pins (continued)
†
Table 12. Shared Pin Configurations (Continued)
‡
MUX
PIN FUNCTION SELECTED
I/O PORT DATA AND DIRECTION
MUX CONTROL
VALUE AT RESET
(MCRx.n)
CONTROL
REGISTER
(name.bit #)
(MCRx.n = 1)
(MCRX.N = 0)
§
¶
REGISTER
DATA BIT NO.
DIR BIT NO.
Primary Function
I/O
PORT E
CLKOUT
PWM7
IOPE0
IOPE1
IOPE2
IOPE3
IOPE4
IOPE5
IOPE6
IOPE7
MCRC.0
MCRC.1
MCRC.2
MCRC.3
MCRC.4
MCRC.5
MCRC.6
MCRC.7
1
0
0
0
0
0
0
0
PEDATDIR
PEDATDIR
PEDATDIR
PEDATDIR
PEDATDIR
PEDATDIR
PEDATDIR
PEDATDIR
PORT F
0
1
2
3
4
5
6
7
8
9
PWM8
10
11
12
13
14
15
PWM9
PWM10
PWM11
PWM12
CAP4/QEP3
CAP5/QEP4
CAP6
IOPF0
IOPF1
IOPF2
IOPF3
IOPF4
IOPF5
MCRC.8
MCRC.9
0
0
0
0
0
0
PFDATDIR
PFDATDIR
PFDATDIR
PFDATDIR
PFDATDIR
PFDATDIR
0
1
2
3
4
5
8
9
T3PWM/T3CMP
T4PWM/T4CMP
TDIRB
MCRC.10
MCRC.11
MCRC.12
MCRC.13
10
11
12
13
TCLKINB
†
‡
§
¶
#
||
Bold, italicized pin names indicate pin functions at reset.
Valid only if the I/O function is selected on the pin
If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.
If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode.
Note that bits 15 through 9 of the MCRB register must be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation
of the device.
digital I/O control registers
Table 13 lists the registers available in the digital I/O module. As with other 240xA peripherals, these registers
are memory-mapped to the data space.
Table 13. Addresses of Digital I/O Control Registers
ADDRESS
7090h
7092h
7094h
7095h
7096h
7098h
709Ah
709Ch
709Eh
REGISTER
MCRA
NAME
I/O MUX control register A
MCRB
I/O mux control register B
MCRC
I/O mux control register C
PEDATDIR
PFDATDIR
PADATDIR
PBDATDIR
PCDATDIR
PDDATDIR
I/O port E data and direction register
I/O port F data and direction register
I/O port A data and direction register
I/O port B data and direction register
I/O port C data and direction register
I/O port D data and direction register
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external memory interface (LF2407A)
The LF2407A can address up to 64K × 16 words of memory (or registers) in each of the program, data, and I/O
spaces. On-chip memory, when enabled, occupies some of this off-chip range.
The CPU of the LF2407A schedules a program fetch, data read, and data write on the same machine cycle.
This is because from on-chip memory, the CPU can execute all three of these operations in the same cycle.
However, the external interface multiplexes the internal buses to one address bus and one data bus. The
external interface sequences these operations to complete first the data write, then the data read, and finally
the program read.
The LF2407A supports a wide range of system interfacing requirements. Program, data, and I/O address
spaces provide interface to memory and I/O, thereby maximizing system throughput. The full 16-bit address
and data buses, along with the PS, DS, and IS space-select signals, allow addressing of 64K 16-bit words in
program, data, and I/O space. Since on-chip peripheral registers occupy positions of data-memory space
(7000−7FFF), the externally addressable data-memory space is 32K 16-bit words (8000−FFFF). Note that the
global memory space of the C2xx core is not used for 240xA DSP devices. Therefore, the global memory
allocation register (GREG) is reserved for all these devices.
Input/output (I/O) design is simplified by having I/O space treated the same way as memory. I/O devices are
accessed in the I/O address space using the processor’s external address and data buses in the same manner
as memory-mapped devices.
The LF2407A external parallel interface provides various control signals to facilitate interfacing to the device.
The R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output
signal provides a timing reference for all external cycles. For convenience, the device also provides the RD and
the WE output signals, which indicate a read cycle and a write cycle, respectively, along with timing information
for those cycles. The availability of these signals minimizes external gating necessary for interfacing external
devices to the LF2407A.
The 2407A provides RD and W/R signals to help the zero-wait-state external memory interface. At higher
CLKOUT speeds, RD may not meet the slow memory device’s timing. In such instances, the W/R signal could
be used as an alternative signal with some tradeoffs. See the timings for details.
The LF2407A supports zero-wait-state reads on the external interface. However, to avoid bus conflicts, writes
take two cycles. This allows the LF2407A to buffer the transition of the data bus from input to output (or from
output to input) by a half cycle. In most systems, the LF2407A ratio of reads to writes is significantly large to
minimize the overhead of the extra cycle on writes.
wait-state generation
Wait-state generation is incorporated in the LF2407A without any external hardware for interfacing the LF2407A
with slower off-chip memory and I/O devices. Adding wait states lengthens the time the CPU waits for external
memory or an external I/O port to respond when the CPU reads from or writes to that external memory or I/O
port. Specifically, the CPU waits one extra cycle (one CLKOUT cycle) for every wait state. The wait states
operate on CLKOUT cycle boundaries.
To avoid bus conflicts, writes from the LF2407A always take at least two CLKOUT cycles. The LF2407A offers
two options for generating wait states:
D
D
READY Signal. With the READY signal, you can externally generate any number of wait states. The READY
pin has no effect on accesses to internal memory.
On-Chip Wait-State Generator. With this generator, you can generate zero to seven wait states.
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generating wait states with the READY signal
When the READY signal is low, the LF2407A waits one CLKOUT cycle and then checks READY again. The
LF2407A does not continue executing until the READY signal is driven high; therefore, if the READY signal is
not used, it should be pulled high.
The READY pin can be used to generate any number of wait states. However, when the LF2407A operates at
full speed, it may not respond fast enough to provide a READY-based wait state for the first cycle. For extended
wait states using external READY logic, the on-chip wait-state generator should be programmed to generate
at least one wait state.
generating wait states with the LF2407A on-chip software wait-state generator
The software wait-state generator can be programmed to generate zero to seven wait states for a given off-chip
memory space (program, data, or I/O), regardless of the state of the READY signal. These zero to seven wait
states are controlled by the wait-state generator register (WSGR) (I/O FFFFh). For more detailed information
on the WSGR and associated bit functions, refer to the TMS320LF/LC240xA DSP Controllers Reference Guide:
System and Peripherals (literature number SPRU357).
watchdog (WD) timer module
The 240xA devices include a watchdog (WD) timer module. The WD function of this module monitors software
and hardware operation by generating a system reset if it is not periodically serviced by software by having the
correct key written. The WD timer operates independently of the CPU. It does not need any CPU initialization
to function. When a system reset occurs, the WD timer defaults to the fastest WD timer rate available (WDCLK
signal = CLKOUT/512). As soon as reset is released internally, the CPU starts executing code, and the WD timer
begins incrementing. This means that, to avoid a premature reset, WD setup should occur early in the power-up
sequence. See Figure 12 for a block diagram of the WD module. The WD module features include the following:
D
WD Timer
−
−
Seven different WD overflow rates
A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and
generates a system reset if an incorrect value is written to the register
−
WD check bits that initiate a system reset if an incorrect value is written to the WD control register
(WDCR)
D
Automatic activation of the WD timer, once system reset is released
Three WD control registers located in control register frame beginning at address 7020h.
−
NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte
is read as zeros. Writing to the upper byte has no effect.
Figure 12 shows the WD block diagram. Table 14 shows the different WD overflow (time-out) selections.
The watchdog can be disabled in software by writing ‘1’ to bit 6 of the WDCR register (WDCR.6) while bit 5 of
the SCSR2 register (SCSR2.5) is 1. If SCSR2.5 is 0, the watchdog will not be disabled. SCSR2.5 is equivalent
to the WDDIS pin of the F243/241 devices.
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watchdog (WD) timer module (continued)
CLKOUT
CLKIN
3-bit
Prescaler
÷ 512
PLL
6-Bit
Free-
Running
Counter
/64
On-Chip
/32
Oscillator or
External
Clock
/16
/8
WDCLK
/4
/2
System
Reset
CLR
000
001
010
011
100
101
WDPS
WDCR.2−0
2
1 0
110
111
WDCR.6
WDDIS
WDCNTR.7−0
WDFLAG
8-Bit Watchdog
Counter
WDCR.7
Reset Flag
One-Cycle
Delay
PS/257
CLR
WDKEY.7−0
System
Reset
Request
Bad Key
Watchdog
Reset Key
Register
55 + AA
Detector
Good Key
WDCHK2−0
†
WDCR.5−3
Bad WDCR Key
3
3
System Reset
1
0 1
(Constant
Value)
†
Writing to bits WDCR.5−3 with anything but the correct pattern (101) generates a system reset.
Figure 12. Block Diagram of the WD Module
51
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
watchdog (WD) timer module (continued)
Table 14. WD Overflow (Time-out) Selections
WATCHDOG
CLOCK RATE
WD PRESCALE SELECT BITS
†
WDCLK DIVIDER
WDPS2
WDPS1
WDPS0
FREQUENCY (Hz)
WDCLK/1
‡
X
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
2
0
WDCLK/2
1
0
1
0
1
4
WDCLK/4
8
WDCLK/8
16
32
64
WDCLK/16
WDCLK/32
WDCLK/64
†
‡
WDCLK = CLKOUT/512
X = Don’t care
52
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
development support
Texas Instruments (TI) offers an extensive line of development tools for the 240xA generation of DSPs, including
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and
fully integrate and debug software and hardware modules.
The following products support development of 240xA-based applications:
Software Development Tools:
Assembler/linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler
Hardware Development Tools:
Emulator XDS510 (supports x24x multiprocessor system debug)
TMS320LF2407 EVM (Evaluation module for 2407 DSP)
See Table 15 and Table 16 for complete listings of development support tools for the 240xA. For information
on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Table 15. Development Support Tools
DEVELOPMENT TOOL
PLATFORM
PART NUMBER
Software − Code Generation Tools
Assembler/Linker
PC, Windows 95
TMDS3242850-02
TMDS3242855-02
C Compiler/Assembler/Linker
PC, Windows 95
Software − Emulation Debug Tools
LF2407 eZdsp
PC
TMDS3P761119
TMDS324012xx
Code Composer 4.12, Code Generation 7.0
PC
Hardware − Emulation Debug Tools
XDS510XL Board (ISA card), w/JTAG cable
XDS510PP Pod (Parallel Port) w/JTAG cable
PC
PC
TMDS00510
TMDS00510PP
PC is a trademark of International Business Machines Corp.
Windows is a registered trademark of Microsoft Corporation.
eZdsp is a trademark of Spectrum Digital, Inc.
XDS510XL and XDS510PP are trademarks of Texas Instruments.
53
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
development support (continued)
Table 16. TMS320x24x-Specific Development Tools
DEVELOPMENT TOOL
PLATFORM
PART NUMBER
Hardware − Evaluation/Starter Kits
PC, Windows 95, Windows 98
TMS320LF2407A EVM
TMDX3P701016
The LF2407 Evaluation Module (EVM) provide designers of motor and motion control applications with a
complete and cost-effective way to take their designs from concept to production. These tools offer both a
hardware and software development environment and include:
D
D
D
D
D
D
D
D
D
D
D
Flash-based LF240xA evaluation board
Code Generation Tools
Assembler/Linker
C Compiler
Source code debugger
C24x Debugger
Code Composer IDE
XDS510PP JTAG-based emulator
Sample applications code
Universal 5-V DC power supply
Documentation and cables
device and development support tool nomenclature
To designate the stages in the product development cycle, Texas Instruments assigns prefixes to the part
numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This
development flow is defined below.
Support tool development evolutionary flow:
TMDX
TMDS
Development support product that has not completed TI’s internal qualification testing
Fully qualified development support product
TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development support tools have been fully characterized, and the quality and reliability
of the device have been fully demonstrated. TI’s standard warranty applies.
54
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
device and development support tool nomenclature (continued)
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PAG, PG, PGE, and PZ) and temperature range (for example, A). Figure 13 provides a legend
for reading the complete device name for any TMS320x240xA family member. Refer to the timing section for
specific options that are available on 240xA devices.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
M
EP
SM 320 LF 2407A PGE
PREFIX
SM
ENHANCED PLASTIC
DESIGNATOR
=
Commercial
processing
TEMPERATURE RANGE
A
S
M
=
=
=
−40°C to 85°C
−40°C to 125°C
−55°C to 125°C
DEVICE FAMILY
320 = TMS320 DSP Family
†
PACKAGE TYPE
PGE= 144-pin plastic LQFP
DEVICE
240xA DSP
2407A
TECHNOLOGY
LF = Flash EEPROM (3.3 V)
†
LQFP = Low-Profile Quad Flatpack
Figure 13. TMS320x240xA Device Nomenclature
55
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
documentation support
Extensive documentation supports all of the TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets,
such as this document, with design specifications; complete user’s guides for all devices and development
support tools; and hardware and software applications. Useful reference documentation includes:
D
User Guides
−
−
−
TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number
SPRU357)
Manual Update Sheet for TMS320LF/LC240xA DSP Controllers Reference Guide: System and
Peripherals (SPRU357B) [literature number SPRZ015]
TMS320C240 DSP Controllers CPU, System, and Instruction Set Reference Guide
(literature number SPRU160)
D
D
Data Sheets
−
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A, TMS320LC2406A,
TMS320LC2404A, TMS320LC2402A DSP Controllers (literature number SPRS145)
TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP Controllers (literature number SPRS094)
TMS320LF2401A DSP Controller (literature number SPRS161)
−
−
Application Reports
3.3V DSP for Digital Motor Control (literature number SPRA550)
−
To receive copies of TMS320 DSP literature, contact the Literature Response Center at 800-477-8924.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this TMS320x240xA data sheet (literature number SPRS145), use the
comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support,
contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
56
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
LF240xA ELECTRICAL SPECIFICATIONS DATA
absolute maximum ratings over operating case temperature ranges (unless otherwise noted)
†
Supply voltage range, V , PLLV
, V
, and V
(see Note 1) . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
DD
CCA DDO
CCA
V
range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 5.5 V
CCP
Input voltage range, V
Output voltage range, V
Input clamp current, I (V < 0 or V > V
Output clamp current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
IN
O
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK IN
IN
CC
CC
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O
O
Operating case temperature ranges, T : M version (see Notes 2 and 3) . . . . . . . . . . . . . − 55°C to 125°C
C
Junction temperature range, T (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 130°C
J
Storage temperature range, T (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
stg
†
Clamp current stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to V
.
SS
2. Long term high−temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction
of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
3. See the next section on device operating life for important information on temperature ranges.
device operating life
125°C case operating temperature denotes maximum test temperature only. Impact on estimated product life
from continuous operation of this device at elevated temperatures are shown in Figure 14 .
Bond (package) life is based on time-to-first failure due to intermetallic formation. After the first failure is
encountered, the failure rate approaches 100% in a very short time (a matter of months) due to the nature of
the failure mechanism.
Since the bond intermetallic life is a function of package components and temperature only, the 150°C point is
included to indicate the effect of extended high temperature storage.
Electromigration life is based on a FR50 of 50 FITS with an activation energy of 0.75 eV and follows a standard
wear-out curve.
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
Device Life Estimations
20
Est bond Intermetalic Life
Est Electromigration Life
15
10
5
0
90
100
110
120
130
140
150
160
Continuous Junction Temperature
Figure 14. Graphical Display of Impact From Elevated Temperature
58
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
‡§
recommended operating conditions
MIN
3
NOM
3.3
0
MAX
3.6
0
UNIT
V
V
V
/V
Supply voltage
V = V
DDO DD
0.3 V
DD DDO
Supply ground
0
V
SS
PLLV
PLL supply voltage
ADC supply voltage
Flash programming supply voltage
3
3.3
3.3
5
3.6
3.6
5.25
40
V
CCA
¶
V
V
3
V
CCA
4.75
2
V
CCP
f
Device clock frequency (system clock)
MHz
V
CLKOUT
XTAL1/CLKIN
RS
2.2
2.3
2
V
DD
V
DD
V
DD
+ 0.3
+ 0.3
+ 0.3
0.6
0.5
0.8
− 2
− 4
− 8
2
#
V
V
High-level input voltage
IH
IL
All other inputs
D[15:0]
V
V
TCK
V
V
Low-level input voltage
All other inputs
Output pins Group 1
Output pins Group 2
Output pins Group 3
Output pins Group 1
Output pins Group 2
Output pins Group 3
V
||
||
||
||
||
||
mA
mA
mA
mA
mA
mA
°C
°C
I
I
High-level output source current, V
= 2.4 V
OH
OL
OH
4
Low-level output sink current, V
= V
MAX
OL
OL
8
T
T
Case temperature
M version
−55
−40
125
130
C
Junction temperature
25
J
Flash endurance for the array (Write/erase
cycles)
N
−40°C to 85°C
10K
cycles
f
‡
§
¶
#
||
Refer to the mechanical data package page for thermal resistance values, Θ (junction-to-ambient) and Θ (junction-to-case).
The drive strength of the EVA PWM pins and the EVB PWM pins are not identical.
JA
JC
V
should not differ from V by more than 0.3 V.
CCA
DD
The input buffers used in 240x/240xA are not 5-V compatible.
Primary signals and their groupings:
Group 1: PWM1−PWM6, T1PWM, T2PWM, CAP1−CAP6, TCLKINA, IOPF6, IOPC1, TCK, TDI, TMS, XF, A0−A15
Group 2: PS/DS/IS, RD, W/R, STRB, R/W, VIS_OE, D0−D15, T3PWM, T4PWM, PWM7−PWM12, CANTX, CANRX, SPICLK,
SPISOMI, SPISIMO, SPISTE, EMU0, EMU1, TDO, TMS2
Group 3: TDIRA, TDIRB, SCIRXD, SCITXD, XINT1, XINT2, CLKOUT, TCLKINB
59
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
electrical characteristics over recommended operating case temperature ranges (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= 3.0 V, I
= I
MAX
All outputs
2.4
V
DDO
DD
OH OH
V
OH
High-level output voltage
V
All outputs at 50 µA
V
− 0.2
DDO
A[15:0], CLKOUT,
PWM1−PWM12,
SCIRXD, SCITXD,
SPISIMO, SPISOMI,
T1PWM, T2PWM,
TCLKINA, W/R,
0.7
V
OL
Low-level output voltage
I = I MAX
OL OL
V
XINT1, XINT2
All other outputs
With pullup
0.4
−40
2
−9
9
−16
16
I
Input current (low level)
Input current (high level)
V
= 3.3 V, V = 0 V
IN
µA
IL
DD
DD
With pulldown
With pullup
2
I
I
V
V
= 3.3 V, V = V
IN DD
µA
µA
IH
With pulldown
40
Output current, high-impedance
state (off-state)
= V
O DD
or 0 V
2
OZ
C
C
Input capacitance
Output capacitance
2
3
pF
pF
i
o
current consumption by power-supply pins over recommended operating case temperature
ranges at 40-MHz CLOCKOUT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
120
20
UNIT
A test code running in B0 RAM does the following:
1. Enables clock to all peripherals.
2. Toggles all PWM outputs at 20 kHz.
3. Performs a continuous conversion of all ADC channels.
4. An infinite loop which transmits a character out of SCI
and executes MACD instructions.
†
I
I
95
mA
Operational Current
ADC module current
DD
NOTE: All I/O pins are floating.
10
mA
CCA
†
I
is the current flowing into the V , V
DD DDO
, and PLLV pins.
CCA
DD
current consumption by power-supply pins over recommended operating case temperature
ranges during low-power modes at 40-MHz CLOCKOUT (320LF2407A)
PARAMETER
Operational Current
ADC module current
Operational Current
ADC module current
MODE
TEST CONDITIONS
MIN
TYP
70
MAX
80
UNIT
mA
mA
mA
µA
†
I
I
I
I
I
DD
Clock to all peripherals is enabled.
No I/O pins are switching.
LPM0
10
35
20
70
CCA
†
DD
Clock to all peripherals is disabled.
No I/O pins are switching.
LPM1
LPM2
2
10
CCA
†
Clock to all peripherals is disabled.
Flash is powered down.
Operational Current
ADC module current
200
400
µA
µA
DD
‡
I
2
10
Input clock is disabled.
CCA
†
‡
I
is the current flowing into the V , V
, and PLLV
pins.
DD
DD DDO
CCA
If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.
60
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
current consumption graphs
100
90
80
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
35
40
45
CLKOUT Frequency (MHz)
Figure 15. LF2407A Typical Current Consumption (With Peripheral Clocks Enabled)
reducing current consumption
240x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current
consumption can be achieved by turning off the clock to any peripheral module which is not used in a given
application. Table 17 indicates the typical reduction in current consumption achieved by turning off the clocks
to various peripherals. Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and
Peripherals (literature number SPRU357) for further information on how to turn off the clock to the peripherals.
Table 17. Typical Current Consumption by Various Peripherals (at 40 MHz)
PERIPHERAL MODULE
CURRENT REDUCTION (mA)
8.4
6.1
6.1
CAN
EVA
EVB
ADC
SCI
†
3.7
1.9
1.3
SPI
†
This number represents the current drawn by the digital portion of the ADC module.
Turning off the clock to the ADC module results in the elimination of the current drawn
by the analog portion of the ADC (I
) as well.
CCA
61
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
I
OL
Tester Pin
Electronics
Output
Under
Test
50 Ω
V
LOAD
C
T
I
OH
Where:
I
I
V
=
=
=
=
2 mA (all outputs)
300 µA (all outputs)
1.5 V
OL
OH
LOAD
T
C
50-pF typical load-circuit capacitance
Figure 16. Test Load Circuit
signal transition levels
The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference
voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high
level of 2.4 V and to a maximum logic-low level of 0.8 V.
Figure 17 shows output levels.
2.4 V (V
80%
)
OH
20%
0.4 V (V
)
OL
Figure 17. Output Levels
Output transition times are specified as follows:
D
For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
D
For alow-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage
range and higher and the level at which the output is said to be high is 80% of the total voltage range and
higher.
Figure 18 shows the input levels.
2.0 V (V
90%
)
IH
10%
0.8 V (V
)
IL
Figure 18. Input Levels
Input transition times are specified as follows:
D
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90%
of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage
range and lower.
D
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher and the level at which the input is said to be high is 90% of the total
voltage range and higher.
62
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
A
A[15:0]
MS
R
Memory strobe pins IS, DS, or PS
READY
Cl
XTAL1/CLKIN
CLKOUT
CO
D
RD
RS
W
Read cycle or RD
RESET pin RS
D[15:0]
INT
XINT1, XINT2
Write cycle or WE
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don’t care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
general notes on timing parameters
All output signals from the 240xA devices (including CLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, refer to the appropriate cycle description section of this data sheet.
63
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external reference crystal/clock with PLL circuit enabled
timings with the PLL circuit enabled
PARAMETER
MIN
MAX
13
UNIT
Resonator
Crystal
4
†
4
4
20
f
x
Input clock frequency
MHz
CLKIN
20
†
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
switching characteristics over recommended operating conditions [H = 0.5 t
] (see Figure 19)
c(CO)
PARAMETER
Cycle time, CLKOUT
PLL MODE
MIN
TYP
MAX
UNIT
ns
†
t
t
t
t
t
×4 mode
25
c(CO)
Fall time, CLKOUT
4
4
ns
f(CO)
Rise time, CLKOUT
ns
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H−3
H −3
H
H
H+3
H+3
ns
w(COL)
w(COH)
ns
t
t
4096t
c(Cl)
ns
Transition time, PLL synchronized after RS pin high
†
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
timing requirements (see Figure 19)
MIN
MAX
250
5
UNIT
ns
t
t
t
t
t
Cycle time, XTAL1/CLKIN
c(Cl)
Fall time, XTAL1/CLKIN
ns
f(Cl)
Rise time, XTAL1/CLKIN
5
ns
r(Cl)
Pulse duration, XTAL1/CLKIN low as a percentage of t
40
40
60
60
%
w(CIL)
w(CIH)
c(Cl)
Pulse duration, XTAL1/CLKIN high as a percentage of t
c(Cl)
%
t
c(CI)
t
w(CIH)
t
t
r(Cl)
f(Cl)
t
w(CIL)
XTAL1/CLKIN
CLKOUT
t
w(COH)
t
f(CO)
t
t
t
c(CO)
w(COL)
r(CO)
Figure 19. CLKIN-to-CLKOUT Timing with PLL and External Clock in ×4 Mode
64
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
RS timings
timing requirements for a reset [H = 0.5t
] (see Figure 20 and Figure 21)
c(CO)
MIN NOM
MAX
UNIT
t
t
8t
8t
cycles
Pulse duration, stable CLKIN to RS high
Pulse duration, RS low
w(RSL)
c(CI)
cycles
w(RSL2)
c(CI)
t
PLL lock-up time
4096t
ns
ns
p
c(CI)
t
36H
Delay time, reset vector executed after PLL lock time
d(EX)
V
/V
DD DDO
t
t
p
d(EX)
t
w(RSL)
RS
CLKIN
†
XTAL1
‡
t
OSCST
BOOT_EN
/XF
BOOT_EN
XF
CLKOUT
I/Os
Hi-Z
Code-Dependent
Address/
Data/
Address/Data/Control Valid
Control
†
‡
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
t
is the oscillator start-up time, which is dependent on crystal/resonator and board design.
OSCST
Figure 20. Power-on Reset
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
RS timings (continued)
t
d(EX)
t
p
t
w(RSL2)
RS
CLKIN
†
XTAL1
BOOT_EN
/XF
BOOT_EN
XF
CLKOUT
I/Os
Hi-Z
Code-Dependent
Address/
Data/
Address/Data/Control Valid
Control
†
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
Figure 21. Warm Reset
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
RS timings (continued)
switching characteristics over recommended operating conditions for a reset [H = 0.5t
(see Figure 22)
]
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
†
t
t
t
128t
Pulse duration, RS low
w(RSL1)
c(CI)
36H
ns
Delay time, reset vector executed after PLL lock time
PLL lock time (input cycles)
d(EX)
4096t
ns
p
c(CI)
†
The parameter t
refers to the time RS is an output.
w(RSL1)
t
d(EX)
t
p
t
w(RSL1)
RS
CLKIN
†
XTAL1
BOOT_EN
/XF
BOOT_EN
XF
CLKOUT
I/Os
Hi-Z
Code-Dependent
Address/
Data/
Address/Data/Control Valid
Control
†
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
Figure 22. Watchdog Initiated Reset
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
low-power mode timings
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 23, Figure 24, and Figure 25)
]
c(CO)
PARAMETER
LOW-POWER MODES
MIN
TYP
MAX
UNIT
IDLE1
LPM0
LPM1
12 × t
15 × t
c(CO)
Delay time, CLKOUT switching to
program execution resume
t
t
ns
d(WAKE-A)
IDLE2
c(CO)
Delay time, Idle instruction executed to
CLKOUT high
IDLE2
LPM1
4t
c(CO)
ns
d(IDLE-COH)
OSC start-up
and PLL lock
time
Delay time, wakeup interrupt
asserted to oscillator running
t
ms
d(WAKE-OSC)
HALT
LPM2
{PLL/OSC power down}
Delay time, Idle instruction executed to
oscillator power off
t
t
4t
c(CO)
ns
ns
d(IDLE-OSC)
36H
Delay time, reset vector executed after RS high
d(EX)
t
d(WAKE−A)
A0−A15
CLKOUT
†
WAKE INT
†
WAKE INT can be any valid interrupt or RESET.
Figure 23. IDLE1 Entry and Exit Timing − LPM0
t
d(IDLE−COH)
A0−A15
CLKOUT
†
WAKE INT
t
d(WAKE−A)
†
WAKE INT can be any valid interrupt or RESET.
Figure 24. IDLE2 Entry and Exit Timing − LPM1
t
d(EX)
A0−A15
t
d(IDLE−OSC)
t
t
d(IDLE−COH)
d(WAKE−OSC)
CLKOUT
RESET
Figure 25. HALT Mode − LPM2
68
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
LPM2 wakeup timings
switching characteristics over recommended operating conditions (see Figure 26)
PARAMETER
MIN
MAX
UNIT
†
12
t
t
ns
Delay time, PDPINTx low to PWM high-impedance state
Delay time, INT low/high to interrupt-vector fetch
d(PDP-PWM)HZ
10t
ns
d(INT)
c(CO)
†
Not verified; for informational purposes only.
timing requirements (see Figure 26)
MIN
c(CO)
c(CO)
MAX
UNIT
ns
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
6t
‡
t
t
Pulse duration, PDPINTx input low
PLL lock-up time
w(PDP-WAKE)
12t
4096t
ns
p
c(CI)
‡
This is different from 240x devices.
Oscillator Disabled
XTAL1
†
t
OSC
t
p
CLKIN
‡
CLKOUT
t
w(PDP−WAKE)
PDPINTx
t
d(PDP-PWM)HZ
PWM
t
d(INT)
§
Interrupt Vector or
CPU IDLE State (LPM2)
CPU Status
¶
Next Instruction
†
t
is the oscillator start-up time.
OSC
‡
§
¶
CLKOUT frequency after LPM2 wakeup will be the same as that upon entering LPM2 (x4 shown as an example).
PDPINTx interrupt vector, if PDPINTx interrupt is enabled.
If PDPINTx interrupt is disabled.
Figure 26. LPM2 Wakeup Using PDPINTx
69
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
XF, BIO, and MP/MC timings
switching characteristics over recommended operating conditions (see Figure 27)
PARAMETER
Delay time, CLKOUT high to XF high/low
MIN
MAX
UNIT
t
−7
7
ns
d(XF)
timing requirements (see Figure 27)
MIN
MAX
UNIT
ns
†
t
t
12
22
Setup time, BIO or MP/MC low before CLKOUT low
Hold time, BIO or MP/MC low after CLKOUT low
su(BIO)CO
ns
h(BIO)CO
†
Not verified; for informational purposes only.
CLKOUT
t
d(XF)
XF
t
t
h(BIO)CO
su(BIO)CO
BIO,
MP/MC
Figure 27. XF and BIO Timing
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
TIMING EVENT MANAGER INTERFACE
PWM timings
PWM refers to all PWM outputs on EVA and EVB.
switching characteristics over recommended operating conditions for PWM timing
[H = 0.5t ] (see Figure 28)
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
†
t
t
2H−2
Pulse duration, PWMx output high/low
w(PWM)
d(PWM)CO
18
ns
Delay time, CLKOUT low to PWMx output switching
†
PWM outputs may be 100%, 0%, or increments of t
with respect to the PWM period.
c(CO)
‡
timing requirements [H = 0.5t
] (see Figure 29)
c(CO)
MIN
MAX
UNIT
ns
t
t
t
t
4H+5
40
Pulse duration, TMRDIR low/high
w(TMRDIR)
w(TMRCLK)
wh(TMRCLK)
c(TMRCLK)
60
60
%
Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time
Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time
Cycle time, TMRCLK
40
%
4 ꢀ t
c(CO)
ns
‡
Parameter TMRDIR is equal to the pin TDIRx, and parameter TMRCLK is equal to the pin TCLKINx.
CLKOUT
t
d(PWM)CO
t
w(PWM)
PWMx
Figure 28. PWM Output Timing
CLKOUT
t
w(TMRDIR)
†
TMRDIR
†
Parameter TMRDIR is equal to the pin TDIRx.
Figure 29. TMRDIR Timing
71
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
capture and QEP timings
CAP refers to all QEP and capture input pins.
timing requirements (see Figure 30)
MIN
c(CO)
c(CO)
MAX
UNIT
6t
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
†
t
Pulse duration, CAPx input low/high
ns
w(CAP)
12t
†
This is different from 240x devices.
CLKOUT
t
w(CAP)
CAPx
Figure 30. Capture Input and QEP Timing
72
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
interrupt timings
INT refers to XINT1 and XINT2. PDP refers to PDPINTx.
switching characteristics over recommended operating conditions (see Figure 31)
PARAMETER
MIN
MAX
UNIT
†
12
t
t
ns
Delay time, PDPINTx low to PWM high-impedance state
Delay time, INT low/high to interrupt-vector fetch
d(PDP-PWM)HZ
10t
ns
d(INT)
c(CO)
†
Not verified; for informational purposes only.
timing requirements (see Figure 31)
MIN
c(CO)
c(CO)
c(CO)
c(CO)
MAX
UNIT
6t
12t
6t
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
‡
t
t
Pulse duration, INT input low/high
Pulse duration, PDPINTx input low
ns
w(INT)
‡
ns
w(PDP)
12t
‡
This is different from 240x devices.
CLKOUT
t
w(PDP)
PDPINTx
t
d(PDP-PWM)HZ
†
PWM
t
w(INT)
XINT1, XINT2
A0−A15
t
d(INT)
Interrupt Vector
†
PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTx is taken
high depends on the state of the FCOMPOE bit.
Figure 31. External Interrupts Timing
73
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
general-purpose input/output timings
switching characteristics over recommended operating conditions (see Figure 32)
PARAMETER
MIN
MAX
UNIT
t
t
t
Delay time, CLKOUT low to GPIO low/high
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
All GPIOs
All GPIOs
All GPIOs
9
8
6
ns
ns
ns
d(GPO)CO
r(GPO)
f(GPO)
timing requirements [H = 0.5t
] (see Figure 33)
c(CO)
MIN
MAX
UNIT
t
2H+15
ns
Pulse duration, GPI high/low
w(GPI)
CLKOUT
t
d(GPO)CO
GPIO
t
r(GPO)
t
f(GPO)
Figure 32. General-Purpose Output Timing
CLKOUT
GPIO
t
w(GPI)
Figure 33. General-Purpose Input Timing
74
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
•
75
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
1
SPICLK
(clock polarity = 0)
2
4
3
SPICLK
(clock polarity = 1)
5
SPISIMO
SPISOMI
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
†
SPISTE
†
The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active
until the SPI communication stream is complete.
Figure 34. SPI Master Mode External Timing (Clock Phase = 0)
76
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
•
77
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
SPISOMI
Master Out Data Is Valid
10
Data Valid
11
Master In Data
Must Be Valid
†
SPISTE
†
The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until
the SPI communication stream is complete.
Figure 35. SPI Master Mode External Timing (Clock Phase = 1)
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
SPI SLAVE MODE TIMING PARAMETERS
Slave mode timing information is listed in the following tables.
†‡
SPI slave mode external timing parameters (clock phase = 0) (see Figure 36)
NO.
MIN
MAX
UNIT
‡
12
t
t
t
t
t
Cycle time, SPICLK
4t
c(CO)
ns
c(SPC)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
0.5t
0.5t
0.5t
0.5t
−10 0.5t
−10 0.5t
−10 0.5t
−10 0.5t
w(SPCH)S
w(SPCL)S
w(SPCL)S
w(SPCH)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
§
13
ns
ns
§
14
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
t
t
t
0.375t
−10
−10
d(SPCH-SOMI)S
d(SPCL-SOMI)S
v(SPCL-SOMI)S
c(SPC)S
c(SPC)S
§
ns
15
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
0.375t
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
0.75t
c(SPC)S
§
16
ns
ns
ns
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
t
0.75t
v(SPCH-SOMI)S
c(SPC)S
t
t
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
0
su(SIMO-SPCL)S
§
19
su(SIMO-SPCH)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
t
0.5t
0.5t
v(SPCL-SIMO)S
v(SPCH-SIMO)S
c(SPC)S
§
20
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
t
c(SPC)S
†
‡
§
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
t = system clock cycle time = 1/CLKOUT = t
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
c
c(CO)
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISIMO
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
†
SPISTE
†
The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until
the SPI communication stream is complete.
Figure 36. SPI Slave Mode External Timing (Clock Phase = 0)
80
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
†‡
SPI slave mode external timing parameters (clock phase = 1) (see Figure 37)
NO.
MIN
MAX
UNIT
12
t
t
t
t
t
t
t
Cycle time, SPICLK
8t
ns
c(SPC)S
c(CO)
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
0.5t
0.5t
0.5t
0.5t
−10 0.5t
−10 0.5t
−10 0.5t
−10 0.5t
w(SPCH)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
§
13
ns
ns
ns
w(SPCL)S
w(SPCL)S
§
14
w(SPCH)S
0.125t
c(SPC)S
su(SOMI-SPCH)S
su(SOMI-SPCL)S
§
17
0.125t
c(SPC)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =0)
t
t
0.75t
v(SPCH-SOMI)S
v(SPCL-SOMI)S
c(SPC)S
§
ns
ns
ns
18
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =1)
0.75t
c(SPC)S
t
t
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
0
su(SIMO-SPCH)S
§
21
su(SIMO-SPCL)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
t
0.5t
0.5t
v(SPCH-SIMO)S
v(SPCL-SIMO)S
c(SPC)S
§
22
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
t
c(SPC)S
†
‡
§
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
t = system clock cycle time = 1/CLKOUT = t
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
c
c(CO)
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
SPISIMO
SPISOMI Data Is Valid
21
Data Valid
22
SPISIMO Data
Must Be Valid
†
SPISTE
†
The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until
the SPI communication stream is complete.
Figure 37. SPI Slave Mode External Timing (Clock Phase = 1)
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external memory interface read timings
switching characteristics over recommended operating conditions for an external memory
interface read at 40 MHz [H = 0.5t ] (see Figure 38)
c(CO)
PARAMETER
Delay time, CLKOUT low to control valid
MIN
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
4
ns
d(COL-CNTL)
d(COL-CNTH)
d(COL-A)RD
d(COH-RDL)
d(COL-RDH)
d(COL-SL)
d(COL-SH)
d(WRN)
5
8
5
1
5
6
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay time, CLKOUT low to control inactive
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to RD strobe active
Delay time, CLKOUT low to RD strobe inactive high
Delay time, CLKOUT low to STRB strobe active low
Delay time, CLKOUT low to STRB strobe inactive high
Delay time, W/R going low to R/W rising
−8
−1
H − 7
0
Hold time, address valid after CLKOUT low
h(A)COL
Setup time, address valid before RD strobe active low
Hold time, address valid after RD strobe inactive high
su(A)RD
h(A)RD
timing requirements [H = 0.5t
] (see Figure 38)
c(CO)
MIN
MAX
UNIT
t
2H −10
ns
Access time, read data from address valid
Access time, read data from RD low
a(A)
t
t
t
H − 7
ns
ns
ns
a(RD)
8
Setup time, read data before RD strobe inactive high
Hold time, read data after RD strobe inactive high
su(D)RD
h(D)RD
†
0
0
†
t
ns
Hold time, read data after address invalid
h(AIV-D)
†
Not verified; for informational purposes only.
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external memory interface read timings (continued)
CLKOUT
t
d(COL−CNTL)
t
d(COL−CNTH)
PS, DS,
IS
t
d(COL−A)RD
t
d(COL−A)RD
t
h(A)COL
t
h(A)COL
A[0:15]
t
d(COH−RDL)
t
d(COL−RDH)
t
t
a(A)
d(COH−RDL)
t
d(COL−RDH)
t
h(A)RD
RD
t
h(AIV−D)
t
su(A)RD
t
a(A)
t
su(D)RD
t
h(D)RD
t
a(RD)
t
su(D)RD
t
d(WRN)
t
h(D)RD
W/R
R/W
D[0:15]
t
d(COL−SL)
t
d(COL−SH)
STRB
Figure 38. Memory Interface Read/Read Timings
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external memory interface write timings
switching characteristics over recommended operating conditions for an external memory
interface write at 40 MHz [H = 0.5t ] (see Figure 39)
c(CO)
PARAMETER
Delay time, CLKOUT high to control valid
MIN MAX
UNIT
ns
t
t
t
t
4
d(COH-CNTL)
d(COH-CNTH)
d(COH-A)W
5
10
6
ns
Delay time, CLKOUT high to control inactive
Delay time, CLKOUT high to address valid
Delay time, CLKOUT high to R/W low
ns
ns
d(COH-RWL)
t
t
t
t
t
t
t
6
6
6
ns
ns
ns
ns
ns
ns
ns
Delay time, CLKOUT high to R/W high
d(COH-RWH)
d(COL-WL)
d(COL-WH)
en(D)COL
d(COL-SL)
d(COL-SH)
d(WRN)
Delay time, CLKOUT low to WE strobe active low
Delay time, CLKOUT low to WE strobe inactive high
Enable time, data bus driven from CLKOUT low
Delay time, CLKOUT low to STRB active low
Delay time, CLKOUT low to STRB inactive high
Delay time, W/R going low to R/W rising
−3
6
6
5
t
t
t
t
−5
H−9
ns
ns
ns
ns
Hold time, address valid after CLKOUT low
h(A)COLW
su(A)W
su(D)W
h(D)W
Setup time, address valid before WE strobe active low
Setup time, write data before WE strobe inactive high
Hold time, write data after WE strobe inactive high
2H−17
†
2
t
5
ns
Disable time, data bus high impedance from WE high
dis(W-D)
†
Not verified; for informational purposes only.
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external memory interface write timings (continued)
CLKOUT
t
d(COH−CNTL)
t
d(COH−CNTH)
t
d(COH−CNTL)
PS, DS, IS
A[0:15]
t
d(COH−A)W
t
h(A)COLW
t
d(COH−RWL)
t
d(COH−RWH)
t
su(A)W
R/W
W/R
t
d(WRN)
t
d(COL−WH)
t
d(COL−WH)
t
d(COL−WL)
t
d(COL−WL)
WE
t
dis(W-D)
t
en(D)COL
t
en(D)COL
t
su(D)W
t
su(D)W
t
h(D)W
t
h(D)W
D[0:15]
STRB
t
d(COL−SL)
t
d(COL−SL)
t
d(COL−SH)
t
d(COL−SH)
ENA_144
CLKOUT
2H
2H
VIS_OE
NOTE A: VIS_OE will be visible at pin 97 of LF2407A when ENA_144 is low along with BVIS bits (10,9 of WSGR register − FFFFh@I/O) set to
10 or 11. CLKOUT and VIS_OE indicate internal memory write cycles (program/data). During VIS_OE cycles, the external bus will be
driven. CLKOUT is to be used along with VIS_OE for trace capabilities.
Figure 39. Memory Interface Write/Write Timings
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external memory interface ready-on-read timings
switching characteristics over recommended operating conditions for an external memory
interface ready-on-read (see Figure 40)
PARAMETER
Delay time, CLKOUT low to address valid
MIN MAX
UNIT
t
8
ns
d(COL-A)RD
timing requirements for an external memory interface ready-on-read (see Figure 40)
MIN
MAX
UNIT
†
−3
t
ns
Hold time, READY after CLKOUT high
h(RDY)COH
t
t
t
8
ns
ns
ns
Setup time, read data before RD strobe inactive high
Valid time, READY after address valid on read
Setup time, READY before CLKOUT high
su(D)RD
†
−2
v(RDY)ARD
su(RDY)COH
22
†
Not verified; for informational purposes only.
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external memory interface ready-on-read timings (continued)
CLKOUT
Wait Cycle
PS, DS, IS
t
d(COL−A)RD
A[0:15]
RD
t
su(D)RD
D[0:15]
STRB
t
v(RDY)ARD
t
h(RDY)COH
†
READY
t
su(RDY)COH
†
The WSGR register must be programmed before the READY pin can be used. See the READY pin description for more details.
Figure 40. Ready-on-Read Timings
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external memory interface ready-on-read timings (continued)
timing requirements for an external memory interface ready-on-read with one software wait state
and one external wait state (see Figure 41)
MIN
MAX
UNIT
t
t
t
H − 2.5
ns
Hold time, READY after CLKOUT high
Setup time, READY before CLKOUT high
Delay time, CLKOUT low to address valid
h(RDY)COH
su(RDY)COH
d(COL-A)RD
H − 9.5
ns
ns
8
SW = 1 cycle
EXW = 1 cycle
Read Cycle
CLKOUT
PS, DS, IS
t
d(COL-A)RD
A[0:15]
W/R
R/W
D[0:15]
STRB
t
h(RDY)COH
t
su(RDY)COH
READY
RD
Figure 41. Ready-on-Read Timings With One Software Wait (SW) State and
One External Wait (EXW) State
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external memory interface ready-on-write timings
switching characteristics over recommended operating conditions for an external memory
interface ready-on-write (see Figure 42)
PARAMETER
Delay time, CLKOUT high to address valid
MIN
MAX
UNIT
t
10
ns
d(COH-A)W
timing requirements for an external memory interface ready-on-write [H = 0.5t
(see Figure 42)
]
c(CO)
MIN
MAX
UNIT
t
t
t
t
−3
ns
Hold time, READY after CLKOUT high
h(RDY)COH
2H−17
ns
ns
ns
Setup time, write data before WE strobe inactive high
Valid time, READY after address valid on write
Setup time, READY before CLKOUT high
su(D)W
†
−3
v(RDY)AW
su(RDY)COH
22
†
Not verified; for informational purposes only.
CLKOUT
Wait Cycle
PS, DS, IS
t
d(COH−A)W
A[0:15]
WE
t
su(D)W
D[0:15]
STRB
t
v(RDY)AW
t
su(RDY)COH
t
h(RDY)COH
READY
Figure 42. Ready-on-Write Timings
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external memory interface ready-on-write timings (continued)
timing requirements for an external memory interface ready-on-write with one software wait state
and one external wait state (see Figure 43)
MIN
MAX
UNIT
t
t
t
H − 2.5
ns
Hold time, READY after CLKOUT high
Setup time, READY before CLKOUT high
Delay time, CLKOUT high to address valid
h(RDY)COH
su(RDY)COH
d(COH-A)W
H − 9.5
ns
ns
10
SW = 1 cycle
EXW = 1 cycle
Write Cycle
CLKOUT
PS, DS, IS
A[0:15]
t
d(COH−A)W
t
su(RDY)COH
t
h(RDY)COH
READY
R/W
WE
D[0:15]
STRB
Figure 43. Ready-on-Write Timings With One Software Wait (SW) State and
One External Wait (EXW) State
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
10-bit analog-to-digital converter (ADC)
The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as V
and V
.
CCA
SSA
The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic
circuitry that can be present on V and V from coupling into the ADC analog stage. All ADC specifications
SS
CC
are given with respect to V
unless otherwise noted.
SSA
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-bit (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured
Output conversion mode . . . . . . . . . . . . . . . . . . . 000h to 3FFh (000h for V ≤ V
; 3FFh for V ≥ V
)
I
REFLO
I
REFHI
Minimum conversion time (including sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
recommended operating conditions
MIN
NOM
3.3
0
MAX
UNIT
V
V
V
V
Analog supply voltage
Analog ground
3.0
3.6
V
V
V
V
V
CCA
SSA
†
Analog supply reference source
V
V
REFHI
REFLO
REFLO
CCA
REFHI
REFHI
†
Analog ground reference source
Analog input voltage, ADCIN00−ADCIN07
and V must be stable, within 1/2 LSB of the required resolution, during the entire conversion time.
V
V
V
SSA
V
REFLO
V
AI
†
V
REFHI
REFLO
ADC operating frequency (LF240xA)
MIN
MAX
UNIT
ADC operating frequency
4
30
MHz
†
operating characteristics over recommended operating condition ranges
PARAMETER
DESCRIPTION
MIN
TYP
MAX UNIT
V
V
= 3.3 V
10
20
mA
CCA
I
Analog supply current
PLL or OSC power
down
CCA
= V
REFHI
= 3.3 V
1
mA
CCA
I
I
V
input current
0.75
1.5
1
mA
ADREFHI
REFHI
Analog input leakage
mA
ADCIN
Non-sampling
Sampling
10
30
Typical capacitive load on
analog input pin
C
ai
Analog input capacitance
pF
t
Delay time, power-up to ADC valid
Time to stabilize analog stage after power-up
10
10
ms
d(PU)
Analog input source impedance needed for
conversions to remain within specifications at min
Z
Analog input source impedance
Zero-offset error
53
Ω
AI
t
w(SH)
"2
LSB
†
Absolute resolution = 3.22 mV. At V
REFHI
= 3.3 V and V
REFLO
= 0 V, this is one LSB. As V
REFHI
decreases, V
REFLO
increases, or both, the LSB
size decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
92
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
E
and E
for LF2407A
DNL
INL
PARAMETER
DESCRIPTION
CLKOUT
MIN MAX UNIT
Difference between the actual step width
and the ideal value
‡
E
Differential nonlinearity error
Integral nonlinearity error
30 MHz
"3 LSB
DNL
Maximum deviation from the best straight
line through the ADC transfer
characteristics, excluding the quantization
error
‡
E
INL
30 MHz
"3 LSB
‡
Test conditions: V
REFHI
= V
, V
= V
SSA
CCA REFLO
†
internal ADC module timings (see Figure 44)
MIN
MAX
UNIT
ns
t
t
t
t
t
t
Cycle time, ADC prescaled clock
33.3
c(AD)
‡
Pulse duration, total sample/hold and conversion time
Pulse duration, sample and hold time
Pulse duration, total conversion time
500
§
ns
w(SHC)
w(SH)
2t
32t
ns
c(AD)
c(AD)
10t
ns
w(C)
c(AD)
c(CO)
c(CO)
c(CO)
Delay time, start of conversion to beginning of sample and hold
Delay time, end of conversion to data loaded into result register
Delay time, ADC flag to ADC interrupt
2t
2t
2t
ns
d(SOC-SH)
d(EOC)
ns
t
ns
d(ADCINT)
†
The ADC timing diagram represents a typical conversion sequence. Refer to the ADC chapter in the TMS320LF/LC240xA DSP Controllers
Reference Guide: System and Peripherals (literature number SPRU357) for more details.
‡
§
The total sample/hold and conversion time is determined by the summation of t
Can be varied by ACQ Prescaler bits in the ADCTRL1 register
, t
, t
, and t .
d(EOC)
d(SOC-SH) w(SH) w(C)
t
c(AD)
Bit Converted
ADC Clock
9
8
7
6
5
4
3
1
0
2
Analog Input
EOC/Convert
t
w(C)
t
w(SH)
Internal Start/
Sample Hold
t
d(SOC−SH)
Start of Convert
t
d(EOC)
t
w(SHC)
XFR to RESULTn
ADC Interrupt
t
d(ADCINT)
Figure 44. Analog-to-Digital Internal Module Timing
93
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
†
Flash parameters @40 MHz CLOCKOUT
PARAMETER
Time/Word (16-bit)
Time/4K Sector
MIN
TYP
30
MAX UNIT
µs
ms
ms
ms
s
‡
130
400
350
1
Clear/Programming time
Time/12K Sector
Time/4K Sector
‡
Erase time
Time/12K Sector
Indicates the typical/maximum current consumption during the
Clear-Erase-Program (C-E-P) cycle
I
(V
pin current)
5
15
mA
CCP CCP
†
‡
TI releases upgrades to the Flash algorithms for these devices; hence, these typical values are subject to change.
The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on-chip RAM. The values
specified are when V
DD
= 3.3 V and V
CCP
= 5 V, and any deviation from these values could affect the timing parameters. Aging and process variance
could also impact the timing parameters.
94
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
migrating from 240x devices to 240xA devices
This section highlights the new features/migration issues of the 240xA devices (as compared to the 240x family)
and describes the impact these features/issues have on user applications.
maximum clock speed
240xA devices can operate at a maximum speed of 40 MHz compared to the 30-MHz operation of 240x devices.
This change in clock speed warrants a change in the register contents of all the peripherals. For example, to
maintain the same baud rate, the divisor values that are loaded to the SPI, SCI, and CAN registers must be
recalculated.
code security module
240xA devices incorporate a “code security module” which protects the contents of program memory from
unauthorized duplication. Passwords stored in password locations (PWL) 0040h to 0043h are used for this
purpose. Even if the code is not secured with passwords (i.e., PWL contains FFFFFFFFFFFFFFFFh), the PWL
must still be read to gain access to the program memory contents. Note that locations 0040h to 0043h were
available for user code in the 240x devices, which lack the “code security module”. In 240xA devices, these
locations are reserved for the passwords and are not available for the user code. Even if code security feature
is not used, these locations must be written with all ones. This fact must be borne in mind while submitting ROM
codes to TI.
input-qualifier circuitry
An input-qualifier circuitry qualifies the input signal to the CAP1–6, XINT1/2, ADCSOC, and PDPINTA/B pins
in the x240xA devices. The state of the internal input signal will change only after these pins are high/low for
6 (12) clock edges. The user must hold the pin high/low for 6 (12) cycles to ensure that the device see the level
change. The increase in the pulse width of the signals used to excite these pins must be taken into account
while migrating from the 240x to the 240xA family.
Bit 6 of the SCSR2 register controls whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used
to block 5- or 11-cycle glitches. This bit is a “reserved” bit in 240x devices.
status of the PDPINTx pin
The current status of the PDPINTx pins is now reflected in bit 8 of the COMCONx registers. This bit is a
“reserved” bit in 240x devices.
operation of the IOPC0 pin
At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external
memory interface (e.g., LF2406A), W/R mode is not functional and MCRB.0 must be set to a 0 if the IOPC0
pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register) is reserved in these devices and must
be written with a zero.
external pulldown resistor for TRST pin
An external pulldown resistor may be needed for the TRST pin in boards that operate in noisy environments.
Refer to the TRST pin description for more details.
95
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description
Table 18 is a collection of all the programmable registers of the LF240xA and is provided as a quick reference.
Table 18. LF240xA DSP Peripheral Register Description
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
DATA MEMORY SPACE
CPU STATUS REGISTERS
ARP
DP(6)
ARB
1
OV
DP(4)
CNF
XF
OVM
DP(3)
TC
1
DP(2)
SXM
1
INTM
DP(1)
C
DP(8)
DP(0)
1
ST0
ST1
DP(7)
1
DP(5)
1
1
PM
GLOBAL MEMORY AND CPU INTERRUPT REGISTERS
—
—
—
—
—
—
—
—
—
—
00004h
00005h
00006h
IMR
INT6 MASK
INT5 MASK
INT4 MASK
INT3 MASK
INT2 MASK
INT1 MASK
Reserved
GREG
IFR
—
—
—
—
—
—
—
—
—
—
INT6 FLAG
INT5 FLAG
INT4 FLAG
INT3 FLAG
INT2 FLAG
INT1 FLAG
SYSTEM REGISTERS
IRQ0.15
IRQ0.7
IRQ1.15
IRQ1.7
IRQ2.15
IRQ2.7
IRQ0.14
IRQ0.6
IRQ1.14
IRQ1.6
IRQ2.14
IRQ2.6
IRQ0.13
IRQ0.5
IRQ1.13
IRQ1.5
IRQ2.13
IRQ2.5
IRQ0.12
IRQ0.11
IRQ0.3
IRQ1.11
IRQ1.3
IRQ2.11
IRQ2.3
IRQ0.10
IRQ0.2
IRQ1.10
IRQ1.2
IRQ2.10
IRQ2.2
IRQ0.9
IRQ0.1
IRQ1.9
IRQ1.1
IRQ2.9
IRQ2.1
IRQ0.8
IRQ0.0
IRQ1.8
IRQ1.0
IRQ2.8
IRQ2.0
07010h
07011h
PIRQR0
PIRQR1
PIRQR2
IRQ0.4
IRQ1.12
IRQ1.4
IRQ2.12
IRQ2.4
07012h
07013h
Illegal
IAK0.15
IAK0.7
IAK1.15
IAK1.7
IAK2.15
IAK2.7
IAK0.14
IAK0.6
IAK1.14
IAK1.6
IAK2.14
IAK2.6
IAK0.13
IAK0.5
IAK1.13
IAK1.5
IAK2.13
IAK2.5
IAK0.12
IAK0.4
IAK1.12
IAK1.4
IAK2.12
IAK2.4
IAK0.11
IAK0.3
IAK1.11
IAK1.3
IAK2.11
IAK2.3
IAK0.10
IAK0.2
IAK1.10
IAK1.2
IAK2.10
IAK2.2
IAK0.9
IAK0.1
IAK1.9
IAK1.1
IAK2.9
IAK2.1
IAK0.8
IAK0.0
IAK1.8
IAK1.0
IAK2.8
IAK2.0
07014h
07015h
PIACKR0
PIACKR1
PIACKR2
07016h
07017h
Illegal
—
ADC CLKEN
—
CLKSRC
SCI CLKEN
—
LPM1
SPI CLKEN
—
LPM0
CAN CLKEN
—
CLK PS2
EVB CLKEN
—
CLK PS1
EVA CLKEN
—
CLK PS0
—
ILLADR
—
07018h
SCSR1
SCSR2
—
—
I/P
07019h
WD
OVERRIDE
QUALIFIER
CLOCKS
—
XMIF HI Z
BOOT_EN
MP/MC
DON
PON
0701Ah
to
Illegal
0701Bh
DIN15
DIN7
DIN14
DIN6
DIN13
DIN5
DIN12
DIN4
DIN11
DIN3
DIN10
DIN2
DIN9
DIN1
DIN8
DIN0
0701Ch
0701Dh
DINR
PIVR
Illegal
Illegal
V15
V7
V14
V6
V13
V5
V12
V4
V11
V3
V10
V2
V9
V1
V8
V0
0701Eh
0701Fh
Indicates change with respect to the F243/F241, C242 device register maps.
96
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
WD CONTROL REGISTERS
07020h
to
Illegal
07022h
07023h
07024h
07025h
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
WDCNTR
WDKEY
Illegal
Illegal
07026h
to
07028h
07029h
WDFLAG
WDDIS
WDCHK2
WDCHK1
WDCHK0
Illegal
SERIAL PERIPHERAL INTERFACE (SPI) CONFIGURATION CONTROL REGISTERS
WDPS2
WDPS1
WDPS0
WDCR
0702Ah
to
0703Fh
SPI SW
RESET
CLOCK
POLARITY
SPI
CHAR3
SPI
CHAR2
SPI
CHAR1
SPI
CHAR0
07040h
07041h
—
—
—
SPICCR
SPICTL
OVERRUN
INT ENA
CLOCK
PHASE
MASTER/
SLAVE
SPI INT
ENA
—
—
TALK
—
RECEIVER
OVERRUN
FLAG
SPI INT
FLAG
TX BUF
FULL FLAG
07042h
—
—
—
—
SPISTS
SPIBRR
07043h
07044h
07045h
Illegal
SPI BIT
RATE 6
SPI BIT
RATE 5
SPI BIT
RATE 4
SPI BIT
RATE 3
SPI BIT
RATE 2
SPI BIT
RATE 1
SPI BIT
RATE 0
—
Illegal
ERXB15
ERXB7
RXB15
RXB7
ERXB14
ERXB6
RXB14
RXB6
ERXB13
ERXB5
RXB13
RXB5
ERXB12
ERXB4
RXB12
RXB4
ERXB11
ERXB3
RXB11
RXB3
ERXB10
ERXB2
RXB10
RXB2
ERXB9
ERXB1
RXB9
ERXB8
ERXB0
RXB8
07046h
07047h
07048h
07049h
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
RXB1
RXB0
TXB15
TXB7
TXB14
TXB6
TXB13
TXB5
TXB12
TXB4
TXB11
TXB3
TXB10
TXB2
TXB9
TXB8
TXB1
TXB0
SDAT15
SDAT7
SDAT14
SDAT6
SDAT13
SDAT5
SDAT12
SDAT4
SDAT11
SDAT3
SDAT10
SDAT2
SDAT9
SDAT1
SDAT8
SDAT0
0704Ah
to
Illegal
0704Eh
SPI
PRIORITY
SPI
SUSP SOFT
SPI
SUSP FREE
0704Fh
—
—
—
—
—
SPIPRI
Indicates change with respect to the F243/F241, C242 device register maps.
97
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS
STOP
BITS
EVEN/ODD
PARITY
PARITY
ENABLE
LOOP BACK
ENA
ADDR/IDLE
MODE
SCI
CHAR2
SCI
CHAR1
SCI
CHAR0
07050h
07051h
07052h
07053h
07054h
SCICCR
RX ERR
INT ENA
—
SW RESET
BAUD13
BAUD5
—
—
BAUD12
BAUD4
—
TXWAKE
BAUD11
BAUD3
—
SLEEP
BAUD10
BAUD2
—
TXENA
BAUD9
BAUD1
RXENA
BAUD8
SCICTL1
SCIHBAUD
SCILBAUD
SCICTL2
BAUD15
(MSB)
BAUD14
BAUD6
BAUD0
(LSB)
BAUD7
TXRDY
RX/BK
INT ENA
TX
INT ENA
TX EMPTY
07055h
07056h
07057h
07058h
07059h
RX ERROR
ERXDT7
RXDT7
RXRDY
ERXDT6
RXDT6
BRKDT
ERXDT5
RXDT5
FE
OE
PE
RXWAKE
ERXDT1
RXDT1
—
SCIRXST
ERXDT4
RXDT4
ERXDT3
RXDT3
ERXDT2
RXDT2
ERXDT0
RXDT0
SCIRXEMU
SCIRXBUF
Illegal
TXDT7
TXDT6
TXDT5
TXDT4
TXDT3
TXDT2
TXDT1
TXDT0
SCITXBUF
0705Ah
to
Illegal
0705Eh
SCITX
PRIORITY
SCIRX
PRIORITY
SCI
SOFT
SCI
FREE
0705Fh
—
—
—
—
SCIPRI
07060h
to
Illegal
0706Fh
EXTERNAL INTERRUPT CONTROL REGISTERS
XINT1
FLAG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
07070h
07071h
XINT1CR
XINT2CR
XINT1
POLARITY
XINT1
PRIORITY
XINT1
ENA
—
XINT2
FLAG
—
—
—
XINT2
POLARITY
XINT2
PRIORITY
XINT2
ENA
—
07072h
to
0708Fh
Illegal
DIGITAL I/O CONTROL REGISTERS
MCRA.15
MCRA.7
MCRA.14
MCRA.6
MCRA.13
MCRA.5
MCRA.12
MCRA.4
MCRA.11
MCRA.3
MCRA.10
MCRA.2
MCRA.9
MCRA.1
MCRA.8
MCRA.0
07090h
07091h
07092h
07093h
07094h
MCRA
MCRB
Illegal
MCRB.15
MCRB.7
MCRB.14
MCRB.6
MCRB.13
MCRB.5
MCRB.12
MCRB.4
MCRB.11
MCRB.3
MCRB.10
MCRB.2
MCRB.9
MCRB.1
MCRB.8
MCRB.0
Illegal
MCRC.15
MCRC.7
E7DIR
MCRC.14
MCRC.6
E6DIR
MCRC.13
MCRC.5
E5DIR
MCRC.12
MCRC.4
E4DIR
MCRC.11
MCRC.3
E3DIR
MCRC.10
MCRC.2
E2DIR
MCRC.9
MCRC.1
E1DIR
MCRC.8
MCRC.0
E0DIR
MCRC
07095h
PEDATDIR
IOPE7
IOPE6
IOPE5
IOPE4
IOPE3
IOPE2
IOPE1
IOPE0
Indicates change with respect to the F243/F241, C242 device register maps.
98
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ꢀꢁ ꢂ ꢃ ꢄ ꢅꢆ ꢃꢇꢄ ꢈꢉ ꢊꢋ ꢌ
ꢍꢀꢌ ꢎꢏ ꢐꢑ ꢒ ꢏꢅ ꢅꢋ ꢒꢀ
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
DIGITAL I/O CONTROL REGISTERS (CONTINUED)
—
F6DIR
IOPF6
A6DIR
IOPA6
F5DIR
IOPF5
A5DIR
IOPA5
F4DIR
IOPF4
A4DIR
IOPA4
F3DIR
IOPF3
A3DIR
IOPA3
F2DIR
IOPF2
A2DIR
IOPA2
F1DIR
IOPF1
A1DIR
IOPA1
F0DIR
IOPF0
A0DIR
IOPA0
07096h
PFDATDIR
PADATDIR
—
A7DIR
IOPA7
07098h
07099h
0709Ah
0709Bh
0709Ch
0709Dh
0709Eh
0709Fh
Illegal
Illegal
Illegal
Illegal
B7DIR
IOPB7
B6DIR
IOPB6
B5DIR
IOPB5
B4DIR
IOPB4
B3DIR
IOPB3
B2DIR
IOPB2
B1DIR
IOPB1
B0DIR
IOPB0
PBDATDIR
PCDATDIR
PDDATDIR
C7DIR
IOPC7
C6DIR
IOPC6
C5DIR
IOPC5
C4DIR
IOPC4
C3DIR
IOPC3
C2DIR
IOPC2
C1DIR
IOPC1
C0DIR
IOPC0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D0DIR
IOPD0
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS
ADC
S/W RESET
ACQ
ACQ
ACQ
ACQ
PRESCALE0
—
SOFT
FREE
PRESCALE3 PRESCALE2 PRESCALE1
070A0h
ADCTRL1
CONV PRE-
SCALE (CPS) UOUS RUN
CONTIN-
INT
PRIORITY
SEQ1/2
CASCADE
—
—
—
—
EVB SOC
EN SEQ1
RESET
SEQ1
INT ENA
INT ENA
INT FLAG
SEQ1
EVA SOC
EN SEQ1
SOC SEQ1
SEQ1 BUSY
SEQ1 Mode1 SEQ1 Mode0
INT ENA INT ENA
SEQ2 Mode1 SEQ2 Mode0
070A1h
070A2h
ADCTRL2
EXT SOC
EN SEQ1
INT FLAG
SEQ2
EVB SOC
EN SEQ2
Reset SEQ2
—
SOC SEQ2
—
SEQ2 BUSY
—
—
—
—
—
—
—
MAXCONV
MAXCONV2
2
MAXCONV2
1
MAXCONV2
0
MAXCONV1
3
MAXCONV1
2
MAXCONV1
1
MAXCONV1
0
CONV 3
CONV 1
CONV 7
CONV 5
CONV 11
CONV 9
CONV 15
CONV 13
—
CONV 3
CONV 1
CONV 7
CONV 5
CONV 11
CONV 9
CONV 15
CONV 13
—
CONV 3
CONV 1
CONV 7
CONV 5
CONV 11
CONV 9
CONV 15
CONV 13
—
CONV 3
CONV 1
CONV 7
CONV 5
CONV 11
CONV 9
CONV 15
CONV 13
—
CONV 2
CONV 0
CONV 2
CONV 0
CONV 2
CONV 0
CONV 2
CONV 0
070A3h
070A4h
070A5h
070A6h
CHSELSEQ1
CHSELSEQ2
CHSELSEQ3
CHSELSEQ4
CONV 6
CONV 6
CONV 6
CONV 6
CONV 4
CONV 4
CONV 4
CONV 4
CONV 10
CONV 8
CONV 10
CONV 8
CONV 10
CONV 8
CONV 10
CONV 8
CONV 14
CONV 12
SEQ CNTR3
CONV 14
CONV 12
SEQ CNTR2
CONV 14
CONV 12
SEQ CNTR1
CONV 14
CONV 12
SEQ CNTR0
070A7h
AUTO_SEQ_SR
SEQ2
SEQ2
SEQ2
SEQ2
SEQ1
SEQ1
SEQ1
SEQ1
STATE 3
STATE 2
STATE 1
STATE 0
STATE 3
STATE 2
STATE 1
STATE 0
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
070A8h
070A9h
070AAh
RESULT0
RESULT1
RESULT2
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
Indicates change with respect to the F243/F241, C242 device register maps.
99
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢃꢇꢄ ꢈꢉꢊꢋ ꢌ
ꢍ ꢀꢌ ꢎ ꢏꢐ ꢑ ꢒꢏꢅ ꢅ ꢋꢒ ꢀ
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS (CONTINUED)
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
070ABh
070ACh
070ADh
070AEh
070AFh
070B0h
070B1h
070B2h
070B3h
070B4h
070B5h
070B6h
RESULT3
RESULT4
RESULT5
RESULT6
RESULT7
RESULT8
RESULT9
RESULT10
RESULT11
RESULT12
RESULT13
RESULT14
RESULT15
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
00
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
070B7h
070B8h
Reserved
Illegal
070B9h
to
070FFh
CONTROLLER AREA NETWORK (CAN) CONFIGURATION CONTROL REGISTERS
—
MD3
TA5
—
MD2
TA4
—
—
ME4
TA2
—
—
—
ME1
—
ME0
07100h
07101h
07102h
07103h
07104h
MDER
TCR
ME5
TA3
ME3
AA5
TRR5
RML3
OPC3
PDR
—
ME2
AA4
TRR4
RML2
OPC2
DBO
—
AA3
AA2
TRS5
RFP3
RMP3
—
TRS4
RFP2
RMP2
—
TRS3
RFP1
RMP1
SUSP
—
TRS2
RFP0
RMP0
CCR
—
TRR3
RML1
OPC1
WUBA
MBNR1
—
TRR2
RML0
OPC0
CDR
MBNR0
—
RCR
MCR
BCR2
ABO
—
STM
—
—
—
—
—
BRP7
BRP6
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Indicates change with respect to the F243/F241, C242 device register maps.
100
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅꢆ ꢃꢇꢄ ꢈꢉ ꢊꢋ ꢌ
ꢍꢀꢌ ꢎꢏ ꢐꢑ ꢒ ꢏꢅ ꢅꢋ ꢒꢀ
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
CONTROLLER AREA NETWORK (CAN) CONFIGURATION CONTROL REGISTERS (CONTINUED)
—
SAM
—
TSEG1−3
—
—
TSEG1−2
—
—
—
SBG
TSEG2−2
—
SJW1
TSEG2−1
—
SJW0
TSEG2−0
FER
07105h
07106h
07107h
07108h
07109h
0710Ah
0710Bh
0710Ch
0710Dh
0710Eh
BCR1
TSEG1−1
—
TSEG1−0
—
—
ESR
BEF
SA1
CRCE
—
SER
ACKE
BO
EP
EW
—
—
—
—
—
—
—
GSR
—
—
SMA
CCE
PDA
—
RM
TM
TEC7
REC7
—
TEC6
REC6
—
TEC5
REC5
MIF5
TEC4
TEC3
TEC2
TEC1
TEC0
CEC
REC4
REC3
REC2
REC1
REC0
MIF4
MIF3
MIF2
MIF1
MIF0
CAN_IFR
CAN_IMR
LAM0_H
LAM0_L
LAM1_H
LAM1_L
—
RMLIF
—
AAIF
WDIF
WUIF
BOIF
EPIF
WLIF
MIL
MIM5
MIM4
MIM3
MIM2
MIM1
MIM0
EIL
RMLIM
—
AAIM
WDIM
WUIM
BOIM
EPIM
WLIM
LAMI
LAM0−23
LAM0−15
LAM0−7
LAMI
LAM1−23
LAM1−15
LAM1−7
—
LAM0−28
LAM0−20
LAM0−12
LAM0−4
LAM1−28
LAM1−20
LAM1−12
LAM1−4
LAM0−27
LAM0−19
LAM0−11
LAM0−3
LAM1−27
LAM1−19
LAM1−11
LAM1−3
LAM0−26
LAM0−18
LAM0−10
LAM0−2
LAM1−26
LAM1−18
LAM1−10
LAM1−2
LAM0−25
LAM0−17
LAM0−9
LAM0−1
LAM1−25
LAM1−17
LAM1−9
LAM1−1
LAM0−24
LAM0−16
LAM0−8
LAM0−0
LAM1−24
LAM1−16
LAM1−8
LAM1−0
LAM0−22
LAM0−14
LAM0−6
—
LAM0−21
LAM0−13
LAM0−5
—
LAM1−22
LAM1−14
LAM1−6
LAM1−21
LAM1−13
LAM1−5
0710Fh
to
Illegal
071FFh
Message Object #0
IDL−15
IDL−7
IDE
IDL−14
IDL−6
AME
IDH−22
—
IDL−13
IDL−5
AAM
IDH−21
—
IDL−12
IDL−11
IDL−3
IDH−27
IDH−19
—
IDL−10
IDL−2
IDH−26
IDH−18
—
IDL−9
IDL−1
IDH−25
IDH−17
—
IDL−8
IDL−0
IDH−24
IDH−16
—
07200h
07201h
MSGID0L
MSGID0H
MSGCTRL0
IDL−4
IDH−28
IDH−20
—
IDH−23
—
07202h
07203h
07204h
—
—
—
RTR
DLC3
DLC2
DLC1
DLC0
Reserved
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
D8
D0
MBX0A
MBX0B
MBX0C
MBX0D
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07205h
07206h
07207h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
Indicates change with respect to the F243/F241, C242 device register maps.
101
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢃꢇꢄ ꢈꢉꢊꢋ ꢌ
ꢍ ꢀꢌ ꢎ ꢏꢐ ꢑ ꢒꢏꢅ ꢅ ꢋꢒ ꢀ
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
CONTROLLER AREA NETWORK (CAN) CONFIGURATION CONTROL REGISTERS (CONTINUED)
Message Object #1
IDL−15
IDL−7
IDE
IDL−14
IDL−6
AME
IDH−22
—
IDL−13
IDL−5
AAM
IDH−21
—
IDL−12
IDL−4
IDH−28
IDH−20
—
IDL−11
IDL−3
IDH−27
IDH−19
—
IDL−10
IDL−2
IDH−26
IDH−18
—
IDL−9
IDL−1
IDH−25
IDH−17
—
IDL−8
IDL−0
IDH−24
IDH−16
—
07208h
07209h
MSGID1L
MSGID1H
MSGCTRL1
IDH−23
—
0720Ah
0720Bh
0720Ch
—
—
—
RTR
DLC3
DLC2
DLC1
DLC0
Reserved
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
D8
D0
MBX1A
MBX1B
MBX1C
MBX1D
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
0720Dh
0720Eh
0720Fh
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
Message Object #2
IDL−15
IDL−7
IDE
IDL−14
IDL−6
AME
IDH−22
—
IDL−13
IDL−5
AAM
IDH−21
—
IDL−12
IDL−11
IDL−3
IDH−27
IDH−19
—
IDL−10
IDL−2
IDH−26
IDH−18
—
IDL−9
IDL−1
IDH−25
IDH−17
—
IDL−8
IDL−0
IDH−24
IDH−16
—
07210h
07211h
MSGID2L
MSGID2H
MSGCTRL2
IDL−4
IDH−28
IDH−20
—
IDH−23
—
07212h
07213h
07214h
—
—
—
RTR
DLC3
DLC2
DLC1
DLC0
Reserved
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
D8
D0
MBX2A
MBX2B
MBX2C
MBX2D
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07215h
07216h
07217h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
Message Object #3
IDL−15
IDL−7
IDE
IDL−14
IDL−6
AME
IDH−22
—
IDL−13
IDL−5
AAM
IDH−21
—
IDL−12
IDL−11
IDL−3
IDH−27
IDH−19
—
IDL−10
IDL−2
IDH−26
IDH−18
—
IDL−9
IDL−1
IDH−25
IDH−17
—
IDL−8
IDL−0
IDH−24
IDH−16
—
07218h
07219h
MSGID3L
MSGID3H
MSGCTRL3
IDL−4
IDH−28
IDH−20
—
IDH−23
—
0721Ah
0721Bh
0721Ch
—
—
—
RTR
DLC3
DLC2
DLC1
DLC0
Reserved
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D8
D0
MBX3A
Indicates change with respect to the F243/F241, C242 device register maps.
102
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅꢆ ꢃꢇꢄ ꢈꢉ ꢊꢋ ꢌ
ꢍꢀꢌ ꢎꢏ ꢐꢑ ꢒ ꢏꢅ ꢅꢋ ꢒꢀ
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
CONTROLLER AREA NETWORK (CAN) CONFIGURATION CONTROL REGISTERS (CONTINUED)
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
0721Dh
0721Eh
0721Fh
MBX3B
MBX3C
MBX3D
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
Message Object #4
IDL−15
IDL−7
IDE
IDL−14
IDL−6
AME
IDH−22
—
IDL−13
IDL−5
AAM
IDH−21
—
IDL−12
IDL−11
IDL−3
IDH−27
IDH−19
—
IDL−10
IDL−2
IDH−26
IDH−18
—
IDL−9
IDL−1
IDH−25
IDH−17
—
IDL−8
IDL−0
IDH−24
IDH−16
—
07220h
07221h
MSGID4L
MSGID4H
MSGCTRL4
IDL−4
IDH−28
IDH−20
—
IDH−23
—
07222h
07223h
07224h
—
—
—
RTR
DLC3
DLC2
DLC1
DLC0
Reserved
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
D8
D0
MBX4A
MBX4B
MBX4C
MBX4D
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07225h
07226h
07227h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
Message Object #5
IDL−15
IDL−7
IDE
IDL−14
IDL−6
AME
IDH−22
—
IDL−13
IDL−5
AAM
IDH−21
—
IDL−12
IDL−11
IDL−3
IDH−27
IDH−19
—
IDL−10
IDL−2
IDH−26
IDH−18
—
IDL−9
IDL−1
IDH−25
IDH−17
—
IDL−8
IDL−0
IDH−24
IDH−16
—
07228h
07229h
MSGID5L
MSGID5H
MSGCTRL5
IDL−4
IDH−28
IDH−20
—
IDH−23
—
0722Ah
0722Bh
0722Ch
—
—
—
RTR
DLC3
DLC2
DLC1
DLC0
Reserved
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
D8
D0
MBX5A
MBX5B
MBX5C
MBX5D
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
0722Dh
0722Eh
0722Fh
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07230h
to
Illegal
073FFh
Indicates change with respect to the F243/F241, C242 device register maps.
103
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢃꢇꢄ ꢈꢉꢊꢋ ꢌ
ꢍ ꢀꢌ ꢎ ꢏꢐ ꢑ ꢒꢏꢅ ꢅ ꢋꢒ ꢀ
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS − EVA
—
T1TOADC(0)
D15
T2STAT
TCOMPOE
D14
T1STAT
—
T2TOADC
T1TOADC(1)
07400h
07401h
07402h
07403h
07404h
07405h
07406h
07407h
07408h
GPTCONA
T1CNT
T1CMPR
T1PR
—
T2PIN
T1PIN
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D8
D0
D7
D6
D15
D14
D13
D5
D12
D11
D10
D2
D9
D8
D7
D6
D4
D3
D1
D0
D15
D14
D13
D5
D12
D11
D10
D2
D9
D8
D7
D6
D4
D3
D1
D0
FREE
—
SOFT
TENABLE
D14
—
TMODE1
TCLKS0
D12
TMODE0
TCLD1
D11
TPS2
TPS1
TECMPR
D9
TPS0
—
T1CON
T2CNT
T2CMPR
T2PR
TCLKS1
D13
D5
TCLD0
D10
D15
D8
D7
D6
D4
D3
D2
D1
D0
D15
D14
D13
D5
D12
D11
D10
D9
D8
D7
D6
D4
D3
D2
D1
D0
D15
D14
D13
D5
D12
D11
D10
D9
D8
D7
D6
D4
D3
D2
D1
D0
FREE
T2SWT1
SOFT
TENABLE
—
TMODE1
TCLKS0
TMODE0
TCLD1
TPS2
TCLD0
TPS1
TECMPR
TPS0
SELT1PR
T2CON
TCLKS1
07409h
to
07410h
Illegal
FULL AND SIMPLE COMPARE UNIT REGISTERS − EVA
PDPINTA
STATUS
CENABLE
—
CLD1
—
CLD0
—
SVENABLE
—
ACTRLD1
—
ACTRLD0
—
FCOMPOE
—
07411h
COMCONA
—
07412h
07413h
07414h
07415h
07416h
07417h
Illegal
SVRDIR
D2
D1
D0
CMP6ACT1
CMP2ACT1
CMP6ACT0
CMP2ACT0
CMP5ACT1
CMP1ACT1
CMP5ACT0
CMP1ACT0
ACTRA
CMP4ACT1
CMP4ACT0
CMP3ACT1
CMP3ACT0
Illegal
—
—
—
—
DBT3
DBT2
DBT1
—
DBT0
—
DBTCONA
EDBT3
EDBT2
EDBT1
DBTPS2
DBTPS1
DBTPS0
Illegal
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
CMPR1
CMPR2
CMPR3
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07418h
07419h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
0741Ah
to
Illegal
0741Fh
Indicates change with respect to the F243/F241, C242 device register maps.
104
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅꢆ ꢃꢇꢄ ꢈꢉ ꢊꢋ ꢌ
ꢍꢀꢌ ꢎꢏ ꢐꢑ ꢒ ꢏꢅ ꢅꢋ ꢒꢀ
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
CAPTURE UNIT REGISTERS − EVA
CAPRES
CAPQEPN
CAP3EN
CAP2EDGE
—
CAP3TSEL
CAP3EDGE
CAP12TSEL
CAP3TOADC
07420h
07421h
07422h
CAPCONA
CAP1EDGE
—
Illegal
—
CAP3FIFO
CAP2FIFO
CAP1FIFO
CAPFIFOA
CAP1FIFO
CAP2FIFO
CAP3FIFO
—
D15
D7
—
D14
D6
—
D13
D5
—
D12
D4
—
D11
D3
—
D10
D2
—
—
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
07423h
07424h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07425h
07426h
07427h
Illegal
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
CAP1FBOT
CAP2FBOT
CAP3FBOT
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07428h
07429h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
0742Ah
to
Illegal
0742Bh
EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS
T1OFINT
ENA
T1UFINT
ENA
T1CINT
ENA
—
—
—
—
—
0742Ch
EVAIMRA
T1PINT
ENA
CMP3INT
ENA
CMP2INT
ENA
CMP1INT
ENA
PDPINTA
ENA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0742Dh
0742Eh
EVAIMRB
EVAIMRC
T2OFINT
ENA
T2UFINT
ENA
T2CINT
ENA
T2PINT
ENA
—
—
—
—
—
CAP3INT
ENA
CAP2INT
ENA
CAP1INT
ENA
T1OFINT
FLAG
T1UFINT
FLAG
T1CINT
FLAG
—
—
—
—
—
0742Fh
EVAIFRA
T1PINT
FLAG
CMP3INT
FLAG
CMP2INT
FLAG
CMP1INT
FLAG
PDPINTA
FLAG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
07430h
07431h
EVAIFRB
EVAIFRC
T2OFINT
FLAG
T2UFINT
FLAG
T2CINT
FLAG
T2PINT
FLAG
—
—
—
—
—
CAP3INT
FLAG
CAP2INT
FLAG
CAP1INT
FLAG
07432h
to
Illegal
074FFh
Indicates change with respect to the F243/F241, C242 device register maps.
105
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS − EVB
—
T3TOADC(0)
D15
T4STAT
TCOMPOEB
D14
T3STAT
—
T4TOADC
T3TOADC(1)
07500h
07501h
07502h
07503h
07504h
07505h
07506h
07507h
07508h
GPTCONB
T3CNT
T3CMPR
T3PR
—
T4PIN
T3PIN
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D8
D0
D7
D6
D15
D14
D13
D5
D12
D11
D10
D2
D9
D8
D7
D6
D4
D3
D1
D0
D15
D14
D13
D5
D12
D11
D10
D2
D9
D8
D7
D6
D4
D3
D1
D0
FREE
—
SOFT
TENABLE
D14
—
TMODE1
TCLKS0
D12
TMODE0
TCLD1
D11
TPS2
TPS1
TECMPR
D9
TPS0
—
T3CON
T4CNT
T4CMPR
T4PR
TCLKS1
D13
D5
TCLD0
D10
D15
D8
D7
D6
D4
D3
D2
D1
D0
D15
D14
D13
D5
D12
D11
D10
D9
D8
D7
D6
D4
D3
D2
D1
D0
D15
D14
D13
D5
D12
D11
D10
D9
D8
D7
D6
D4
D3
D2
D1
D0
FREE
T4SWT3
SOFT
TENABLE
—
TMODE1
TCLKS0
TMODE0
TCLD1
TPS2
TCLD0
TPS1
TECMPR
TPS0
SELT3PR
T4CON
TCLKS1
07509h
to
07510h
Reserved
FULL AND SIMPLE COMPARE UNIT REGISTERS− EVB
PDPINTB
STATUS
CENABLE
—
CLD1
—
CLD0
—
SVENABLE
—
ACTRLD1
—
ACTRLD0
—
FCOMPOEB
—
07511h
COMCONB
—
07512h
07513h
07514h
07515h
07516h
07517h
Reserved
SVRDIR
D2
D1
D0
CMP12ACT1
CMP8ACT1
CMP12ACT0
CMP8ACT0
CMP11ACT1
CMP7ACT1
CMP11ACT0
CMP7ACT0
ACTRB
CMP10ACT1 CMP10ACT0
CMP9ACT1
CMP9ACT0
Reserved
—
—
—
—
DBT3
DBT2
DBT1
—
DBT0
—
DBTCONB
EDBT3
EDBT2
EDBT1
DBTPS2
DBTPS1
DBTPS0
Reserved
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
CMPR4
CMPR5
CMPR6
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07518h
07519h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
0751Ah
to
Reserved
0751Fh
Indicates change with respect to the F243/F241, C242 device register maps.
106
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
CAPTURE UNIT REGISTERS− EVB
CAPRES
CAPQEPN
CAP6EN
CAP5EDGE
—
CAP6TSEL
CAP6EDGE
CAP45SEL
CAP6TOADC
07520h
07521h
07522h
CAPCONB
CAP4EDGE
—
Reserved
—
CAP6FIFO
CAP5FIFO
CAP4FIFO
CAPFIFOB
CAP4FIFO
CAP5FIFO
CAP6FIFO
—
D15
D7
—
D14
D6
—
D13
D5
—
D12
D4
—
—
D10
D2
—
—
D11
D3
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
07523h
07524h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07525h
07526h
07527h
Reserved
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
CAP4FBOT
CAP5FBOT
CAP6FBOT
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07528h
07529h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
0752Ah
to
Reserved
0752Bh
EVENT MANAGER (EVB) INTERRUPT CONTROL REGISTERS
T3OFINT
ENA
T3UFINT
ENA
T3CINT
ENA
—
—
—
—
—
0752Ch
EVBIMRA
T3PINT
ENA
CMP6INT
ENA
CMP5INT
ENA
CMP4INT
ENA
PDPINTB
ENA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0752Dh
0752Eh
EVBIMRB
EVBIMRC
T4OFINT
ENA
T4UFINT
ENA
T4CINT
ENA
T4PINT
ENA
—
—
—
—
—
CAP6INT
ENA
CAP5INT
ENA
CAP4INT
ENA
T3OFINT
FLAG
T3UFINT
FLAG
T3CINT
FLAG
—
—
—
—
—
0752Fh
EVBIFRA
T3PINT
FLAG
CMP6INT
FLAG
CMP5INT
FLAG
CMP4INT
FLAG
PDPINTB
FLAG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
07530h
07531h
EVBIFRB
EVBIFRC
T4OFINT
FLAG
T4UFINT
FLAG
T4CINT
FLAG
T4PINT
FLAG
—
—
—
—
—
CAP6INT
FLAG
CAP5INT
FLAG
CAP4INT
FLAG
07532h
to
Reserved
0753Fh
Indicates change with respect to the F243/F241, C242 device register maps.
107
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢃꢇꢄ ꢈꢉꢊꢋ ꢌ
ꢍ ꢀꢌ ꢎ ꢏꢐ ꢑ ꢒꢏꢅ ꢅ ꢋꢒ ꢀ
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
KEY REGISTERS
077F0h
077F1h
077F2h
077F3h
High Word of the 64-Bit KEY Register
Third Word of the 64-Bit KEY Register
Second Word of the 64-Bit KEY Register
Low Word of the 64-Bit KEY Register
KEY3
KEY2
KEY1
KEY0
PROGRAM MEMORY SPACE − FLASH REGISTERS
—
—
—
—
—
—
—
—
—
—
—
—
0xx00h
0xx01h
PMPC
PWR DWN
KEY1
KEY0
EXEC
PRECND
Mode1
—
—
—
—
—
—
WSVER EN
FCM1
†
CTRL
PRECND
Mode0
ENG/R
Mode2
ENG/R
Mode1
ENG/R
Mode0
FCM3
FCM2
FCM0
0xx02h
0xx03h
0xx04h
0xx05h
WADDR
WDATA
TCR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ENAB
0xx06h
SECT
SECT 4
ENABLE
SECT 3
ENABLE
SECT 2
ENABLE
SECT 1
ENABLE
—
—
—
—
I/O MEMORY SPACE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0FF0Fh
0FFFFh
FCMR
WSGR
WAIT-STATE GENERATOR CONTROL REGISTER
—
—
—
—
—
BVIS.1
BVIS.0
ISWS.2
ISWS.1
ISWS.0
DSWS.2
DSWS.1
DSWS.0
PSWS.2
PSWS.1
PSWS.0
Indicates change with respect to the F243/F241, C242 device register maps.
†
Register shown with bits set in register mode.
108
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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°−ā7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Typical Thermal Resistance Characteristics
PARAMETER
DESCRIPTION
°C/W
Θ
Junction-to-ambient
44
JA
JC
Θ
Junction-to-case
13
109
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
SM320LF2407APGEMEP
V62/04608-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PGE
144
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
LQFP
PGE
144
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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