SMJ320C50AHFGM40 [TI]
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| 型号： | SMJ320C50AHFGM40 |
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SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
HFG PACKAGE
(TOP VIEW)
• Military Operating Temperature Range:
– 55°C to 125°C
• Processed to MIL-STD-883, Class B
• Fast Instruction Cycle Times of 40 ns
and 50 ns
1
99
• Source-Code Compatible With All ’C1x
and ’C2x Devices
• RAM-Based Operation
– 9K × 16-Bit Single-Cycle On-Chip
Program/Data RAM
– 1056 × 16-Bit Dual-Access On-Chip
Data RAM
• 2K × 16-Bit On-Chip Boot ROM
33
67
• 224K × 16-Bit Maximum Addressable
External Memory Space (64K Program,
64K Data, 64K I/O, and 32K Global)
• 32-Bit Arithmetic Logic Unit (ALU)
– 32-bit Accumulator (ACC)
– 32-Bit Accumulator Buffer (ACCB)
GFA PACKAGE
(TOP VIEW)
• 16-Bit Parallel Logic Unit (PLU)
• 16 × 16-Bit Multiplier, 32-Bit Product
• 11 Context-Switch Registers
• 2 Buffers for Circular Addressing
• Full-Duplex Synchronous Serial Port
• Time-Division Multiplexed Serial Port (TDM)
• Timer With Control and Counter Registers
A
C
B
D
F
E
G
J
H
K
L
M
P
T
N
R
U
W
• 16 Software Programmable Wait-State
Generators
V
• Divide-by-One Clock Option
• JTAG Boundary Scan Logic (IEEE 1149.1)
• Operations Are Fully Static
2
4
6
8
10 12 14 16 18
9 11 13 15 17 19
1
3
5
7
• Texas Instruments EPIC 0.8-µm CMOS
Technology
• Packaging
– 141-Pin Ceramic Grid Array (GFA Suffix)
– 132-Lead Ceramic Quad Flat Package
(HFG Suffix)
description
The SMJ320C50A digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor
manufactured in 0.8-µm double-level metal CMOS technology. The SMJ320C50A is the first DSP from TI
designed as a fully static device. Full-static CMOS design contributes to low power consumption while
maintaining high performance, making it ideal for applications such as battery-operated communications
systems, satellite systems, and advanced control algorithms.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
description (continued)
A number of enhancements to the basic SMJ320C2x architecture give the ’C50A a minimum 2× performance
over the previous generation. A four-deep instruction pipeline, incorporating delayed branching, delayed call
to subroutine, and delayed return from subroutine, allows the ’C50A to perform instructions in fewer cycles. The
addition of a parallel logic unit (PLU) gives the ’C50A a method of manipulating bits in data memory without using
the accumulator and ALU. The ’C50A has additional shifting and scaling capability for proper alignment of
multiplicands or storage of values to data memory.
The ’C50A achieves its low power consumption through the IDLE2 instruction. IDLE2 removes the functional
clock from the internal hardware of the ’C50A, which puts it into a total-sleep mode that uses only 5 µA. A low
logic level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.
The ’C50A is available with two clock speeds. The clock frequencies are 40 MHz, giving a 50-ns cycle time, and
50 MHz, giving a 40-ns cycle time.
AVAILABLE OPTIONS
PART NUMBER
SPEED
SUPPLY VOLTAGE TOLERANCE
PACKAGE
Pin grid array
SMJ320C50AGFAM40
SMJ320C50AGFAM50
SMJ320C50AHFGM40
SMJ320C50AHFGM50
50-ns cycle time
40-ns cycle time
50-ns cycle time
40-ns cycle time
±10%
±10%
±10%
±10%
Pin grid array
Quad flat package
Quad flat package
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
functional block diagram
Program Bus (Address)
Program Bus (Data)
IPTR INT#
INTM
IMR
IFR
BMAR
MUX
PASR
BRAF
PC(16)
MP/MC
CNF
RAM
Compare
PAER
Program Memory
Stack
(8 × 16)
BRCR
Data Bus (Data)
TRM
MUX
TREG2
TREG1
TREG0
Multiplier
MUX
PREG(32)
PM
MUX
COUNT
Prescaler
P-Scaler
MUX
OVM
SXM
ALU(32)
ACC(32)
ACCB(32)
Post-Scaler
OV
TC
C
DBMR
MUX
BIM
PLU(16)
Data Bus (Data)
MUX
ARP
CBER
INDX
MUX
ARCR
NDX
CBSR
AUXREGS
(8 × 16)
DP(9)
dma(7)
CBCR
MUX
ARB
MUX
XF
ARAU(16)
Data Bus (Address)
Data Memory
GREG
BR
CNF
OVLY
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
PIN ASSIGNMENTS
NO.
PIN
PIN
PIN
PIN
NO.
HFG GFA
NO.
HFG GFA
NO.
HFG GFA
PKG. PKG.
NAME
NAME
NAME
NAME
HFG
GFA
PKG. PKG.
PKG. PKG.
PKG. PKG.
†
†
†
1
2
NC
NC
35
NC
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
P4
T4
V
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
T10
T12
C15
B16
A17
C13
B14
A15
C11
B12
A13
R7
V
V
SS
SS
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
H4
K2
V
V
V
SS
SS
SS
†
3
D8
V
NC
DS
IS
TOUT
TCLKX
CLKX
SS
SS
4
D10
V
U5
V4
A0 (LSB)
A1
R17
T18
U19
N17
P18
R19
L17
M18
N19
J5
SS
†
5
NC
D7
D6
D5
D4
D3
D2
D1
6
E3
D2
C1
G3
F2
W3
U7
V6
A2
PS
TFSR/TADD
TCLKR
RS
7
A3
R/W
8
A4
STRB
BR
9
W5
U9
V8
A5
READY
HOLD
BIO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
A6
CLKIN2
X2/CLKIN
X1
E1
J3
A7
W7
W9
E9
A8
V
V
DD
H2
G1
C3
D4
J1
D0 (LSB)
TMS
A9
V
V
R9
DD
DD
V
V
L5
A11
A9
IAQ
DD
DD
V
V
E11
V10
K4
L19
T6
TDO
TRST
DD
DD
TDI
V
V
B10
D6
V
V
DD
SS
SS
TCK
V
T8
SS
SS
SS
D12
F4
V
M4
V
K18
J19
G19
H18
J17
E19
F18
G17
CLKMD2
FSX
A7
MP/MC
D15 (MSB)
D14
SS
SS
†
V
NC
B8
SS
†
NC
W11
W13
V12
U11
W15
V14
U13
CLKMD1
A10
TFSX/TFRM
DX
C9
L1
N1
M2
L3
INT1
INT2
INT3
INT4
NMI
A5
D13
A11
TDX
B6
D12
A12
HOLDA
XF
C7
D11
A13
A3
D10
R1
P2
N3
T2
R3
E5
E7
A14
CLKOUT1
B4
D9
†
DR
A15
NC
IACK
C5
D8
†
†
TDR
FSR
CLKR
NC
NC
E17
N5
A1
V
DD
V
DD
B2
V
DD
†
†
E13
G5
V
V
R5
V
DD
NC
NC
DD
†
†
†
V
NC
NC
NC
DD
DD
V
V16
U15
RD
DD
†
†
†
NC
NC
NC
WE
†
NC
NC
B18
A19
EMU0
†
EMU1/OFF
†
NC = No connect.
GFA Package additional connections:
V
V
: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, W19
DD
: T14, U1, U3, V2, W1, C17, C19, D14, D16, D18, F16, H16, K16, M16, P16
SS
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
Terminal Functions
SIGNAL
TYPE
DESCRIPTION
ADDRESS AND DATA BUSES
A15 (MSB)
A14
A13
A12
A11
A10
A9
A8
A7
A6
Parallel address bus. Multiplexed to address external data, program memory, or I/O. A0–A15 are in
thehigh-impedance state in hold mode and when OFF is active (low). These signals are used as inputs
for external DMA access of the on-chip single-access RAM. They become inputs while HOLDA is
active (low) if BR is externally driven low.
I/O/Z
A5
A4
A3
A2
A1
A0 (LSB)
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
Parallel data bus. Multiplexed to transfer data between the core CPU and external data, program
memory, or I/O devices. D0–D15 are in the high-impedance state when not outputting data, when RS
or HOLD is asserted, or when OFF is active (low). These signals are also used in external DMA access
of the on-chip single-access RAM.
I/O/Z
D5
D4
D3
D2
D1
D0 (LSB)
MEMORY CONTROL SIGNALS
DS
PS
IS
Data, program, and I/O space select signals. Always high unless asserted for communicating to a
particular external space. DS, PS, and IS are in the high-impedance state in hold mode or when OFF
is active (low).
O/Z
I
Data ready input. Indicates that an external device is prepared for the bus transaction to be completed.
If the device is not ready (READY is low), the processor waits one cycle and checks READY again.
READY also indicates a bus grant to an external device after a BR (bus request) signal.
READY
Read/write. Indicates transfer direction during communication to an external device. Normally in read
mode (high) unless asserted for performing a write operation. R/W is in the high-impedance state in
holdmodeorwhenOFFisactive(low). UsedinexternalDMAaccessofthe9KRAMcell. WhileHOLDA
andIAQareactive(low), thissignalisusedtoindicatethedirectionofthedatabusforDMAreads(high)
and writes (low).
R/W
I/O/Z
NOTE: All input pins that are unused should be connected to V
DD
or an external pullup resistor. The BR pin has an internal pullup for performing
DMA to the on-chip RAM. For emulation, TRST has an internal pulldown, and TMS, TCK, and TDI have internal pullups. EMU0 and EMU1
require external pullups to support emulation.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
Terminal Functions (continued)
SIGNAL
TYPE
DESCRIPTION
MEMORY CONTROL SIGNALS (CONTINUED)
Strobe. Always high unless asserted to indicate an external bus cycle. STRB is in the high-impedance
state in the hold mode or when OFF is active (low). Used in external DMA access of the on-chip
single-access RAM. While HOLDA and IAQ are active (low), this signal is used to select the memory
access.
STRB
RD
I/O/Z
O/Z
Read select. Indicates an active external read cycle and can connect directly to the output enable (OE)
of external devices. This signal is active on all external program, data, and I/O reads. RD is in the
high-impedance state in hold mode or when OFF is active (low).
Writeenable. Thefallingedgeindicatesthatthedeviceisdrivingtheexternaldatabus(D15–D0). Data
can be latched by an external device on the rising edge of WE. This signal is active on all external
program, data, and I/O writes. WE is in the high-impedance state in hold mode or when OFF is active
(low).
WE
O/Z
MULTIPROCESSING SIGNALS
Hold. Asserted to request control of the address, data, and control lines. When acknowledged by the
’C50A, these lines go to the high-impedance state.
HOLD
I
Hold acknowledge. Indicates to the external circuitry that the processor is in a hold state and that the
address, data, and memory control lines are in the high-impedance state so that they are available to
the external circuitry for access of local memory. This signal also goes to the high-impedance state
when OFF is active (low).
HOLDA
BR
O/Z
Bus request. Asserted during access of external global data memory space. READY is asserted when
the global data memory is available for the bus transaction. BR can be used to extend the data memory
address space by up to 32K words. BR goes to the high-impedance state when OFF is active low. BR
is used in external DMA access of the on-chip single-access RAM. While HOLDA is active (low), BR
is externally driven (low) to request access to the on-chip single-access RAM.
I/O/Z
Instructionacquisition. Asserted(active)whenthereisaninstructionaddressontheaddressbus;goes
into the high-impedance state when OFF is active (low). IAQ is also used in external DMA access of
the on-chip single-access RAM. While HOLDA is active (low), IAQ acknowledges the BR request for
access of the on-chip single-access RAM and stops indicating instruction acquisition.
IAQ
BIO
XF
O/Z
I
Branch control. Samples as the BIO condition. If low, the device executes the conditional instruction.
BIO must be active during the fetch of the conditional instruction.
External flag (latched software-programmable signal). Set high or low by a specific instruction or by
loading status register 1 (ST1). Used for signaling other processors in multiprocessor configurations
or as a general-purpose output. XF goes to the high-impedance state when OFF is active (low) and
is set high at reset.
O/Z
Interrupt acknowledge. Indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15–A0. IACK goes to the high-impedance state when OFF
is active (low).
IACK
O/Z
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
INT4
INT3
INT2
INT1
External interrupts. Prioritized and maskable by the interrupt mask register (IMR) and interrupt mode
bit (INTM, bit 9 of status register 0). These signals can be polled and reset via the interrupt flag register.
I
Nonmaskable interrupt. External interrupt that cannot be masked via INTM or IMR. When NMI is
activated, the processor traps to the appropriate vector location.
NMI
RS
I
I
Reset. Causes the device to terminate execution and forces the program counter to zero. When RS
is brought to a high level, execution begins at location zero of program memory.
Microprocessor/microcomputer select. If active (low) at reset (microcomputer mode), the signal
causes the internal program ROM to be mapped into program memory space. In the microprocessor
mode, all program memory is mapped externally. This signal is sampled only during reset, and the
mode that is set at reset can be overridden via the software control bit MP/MC in the PMST register.
MP/MC
I
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
Terminal Functions (continued)
SIGNAL
TYPE
DESCRIPTION
OSCILLATOR/TIMER SIGNALS
Master clock (or CLKIN2 frequency). CLKOUT1 cycles at the machine-cycle rate of the CPU. The
internal machine cycle is bounded by the rising edges of this signal. This signal goes to the
high-impedance state when OFF is active (low).
CLKOUT1
O/Z
CLKMD1 CLKMD2
Clock mode
0
0
External clock with divide-by-two option. Input clock provided to
X2/CLKIN1. Internal oscillator and PLL disabled.
Reserved for test purposes
Externaldivide-by-one option. Input clock provided to CLKIN2. Internal
oscillator is disabled and internal PLL is enabled.
Internal or external divide-by-two option. Input clock provided to
X2/CLKIN1. Internal oscillator is enabled and internal PLL is disabled.
CLKMD1
CLKMD2
0
1
1
0
I
I
1
1
Input to the internal oscillator from the crystal. If the internal oscillator is not being used, a clock may
be input to the device on X2/CLKIN. The internal machine cycle is half this clock rate.
X2/CLKIN
Output from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. This signal does not go to the high-impedance state when OFF is active (low).
X1
O
I
CLKIN2
TOUT
Divide-by-one input clock for driving the internal machine rate.
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a
CLKOUT1 cycle wide.
O
SUPPLY PINS
V
DD1
V
DD2
V
DD3
V
DD4
S
Power supply for data bus
V
V
DD5
DD6
S
S
S
S
S
S
S
Power supply for address bus
V
DD7
V
DD8
Power supply for inputs and internal logic
Power supply for address bus
V
V
DD9
DD10
V
DD11
V
DD12
Power supply for memory control signals
Power supply for inputs and internal logic
Power supply for memory control signals
Ground for memory control signals
V
DD13
V
DD14
V
DD15
V
DD16
V
SS1
V
SS2
V
V
V
V
SS3
SS4
SS5
SS6
S
S
Ground for data bus
V
SS7
V
SS8
V
SS9
V
SS10
Ground for address bus
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
Terminal Functions (continued)
SIGNAL
TYPE
DESCRIPTION
SUPPLY PINS (CONTINUED)
V
V
SS11
SS12
S
Ground for memory control signals
V
SS13
V
SS14
V
SS15
V
SS16
S
Ground for inputs and internal logic
SERIAL PORT SIGNALS
Receive clock. External clock signal for clocking data from DR (data receive) or TDR (TDM data
receive) into the RSR (serial port receive shift register). Must be present during serial port transfers.
If the serial port is not being used, these signals can be sampled as an input via the IN0 bit of the serial
port control (SPC) or TDR serial port control (TSPC) registers.
CLKR
TCLKR
I
Transmit clock. Clock signal for clocking data from the DR or TDR to the DX (data transmit) or TDX
(TDM data transmit pins). CLKX can be an input if the MCM bit in the serial port control register is set
to 0. It can also be driven by the device at 1/4 the CLKOUT1 frequency when the MCM bit is set to 1.
Iftheserialportisnotbeingused, thispincanbesampledasaninputviatheIN1bitoftheSPCorTSPC
register. This signal goes into the high-impedance state when OFF is active (low).
CLKX
TCLKX
I/O/Z
DR
TDR
I
Serial data receive. Serial data is received in the RSR (serial port receive shift register) via DR or TDR.
DX
TDX
Serial port transmit. Serial data transmitted from XSR (serial port transmit shift register) via DX or TDX.
This signal is in the high-impedance state when not transmitting and when OFF is active (low).
O/Z
Frame synchronization pulse for receive. The falling edge of FSR or TFSR initiates the data receive
process, which begins the clocking of the RSR. TFSR becomes an input/output (TADD) pin when the
serial port is operating in the TDM mode (TDM bit = 1). In TDM mode, this pin is used to input/output
the address of the port. This signal goes into the high-impedance state when OFF is active (low).
FSR
TFSR/TADD
I
I/O/Z
Frame synchronization pulse for transmit. The falling edge of FSX/TFSX initiates the data transmit
process, which begins the clocking of the XSR. Following reset, the default operating condition of
FSX/TFSX is an input. This pin may be selected by software to be an output when the TXM bit in the
serialcontrol register is set to 1. This signal goes to the high-impedance state when OFF is active (low).
When operating in TDM mode (TDM bit = 1), TFSX becomes TFRM, the TDM frame synchronization
pulse.
FSX
TFSX/TFRM
I/O/Z
TEST SIGNALS
JTAG test clock. This is normally a free-running clock with a 50% duty cycle. The changes of TAP (test
access port) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or
selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
on the falling edge of TCK.
TCK
I
JTAG test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of
TCK.
TDI
I
JTAG test data output. The contents of the selected register (instruction or data) is shifted out of TDO
on the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is in
progress. This signal also goes to the high-impedance state when OFF is active (low).
TDO
TMS
TRST
O/Z
JTAG test mode select. This serial control input is clocked into the test access port (TAP) controller on
the rising edge of TCK.
I
I
JTAG test reset. Asserting this signal gives the JTAG scan system control of the operations of the
device. If this signal is not connected or is driven low, the device operates in its functional mode and
the JTAG signals are ignored.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
Terminal Functions (continued)
SIGNAL
TYPE
DESCRIPTION
TEST SIGNALS (CONTINUED)
Emulator 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition (see
EMU1/OFF). When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system
and is defined as input/output put via JTAG scan.
EMU0
I/O/Z
Emulator1/OFF. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator
system and is defined as input/output via JTAG scan. When TRST is driven low, EMU1/OFF is
configured as OFF. When the OFF signal is active (low), all output drivers are in the high-impedance
state. OFF is used exclusively for testing and emulation purposes (not for multiprocessing
applications). For the OFF condition, the following conditions apply:
EMU1/OFF
RESERVED
I/O/Z
N/C
•
•
•
TRST = Low
EMU0 = High
EMU1/OFF = Low
†
Reserved. This pin should be left unconnected.
†
Quad flat pack only
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
DD
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Maximum operating case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
Minimum operating free-air temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
Supply voltage
4.5
5
0
5.5
DD
V
SS
CLKIN, CLKIN2
3.0
2.5
V
V
V
V
DD + 0.3
V
IH
High-level input voltage
CLKX, CLKR, TCLKX, TCLKR
All others
V
DD + 0.3
2.2
V
DD + 0.3
0.6
V
IL
Low-level input voltage
– 0.3
V
I
I
High-level output current
Low-level output current
Operating case temperature
Operating free-air temperature
– 300
2
µA
mA
°C
°C
OH
OL
T
125
C
T
– 55
A
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
‡
§
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
High-level output
voltage
V
V
I
I
= MAX
= MAX
2.4
3
V
OH
OH
¶
§
Low-level output voltage
0.3
#
0.6
30
V
OL
OL
BR
All others
– 400
– 30
– 30
– 400
– 50
– 10
High-impedance output
I
µA
OZ
#
#
#
#
#
current (V
= MAX)
30
DD
TRST (with internal pulldown)
TMS, TCK, TDI (with internal pullups)
X2/CLKIN
800
30
µA
Input current
(V = V to V )
DD
I
I
50
I
SS
All other inputs
50
mA
mA
Supply current, core
CPU
I
I
Operating,
T
= 25°C,
V
= 5.25 V, f = 40.96 MHz
60
40
DDC
A
DD
x
Supply current, pins
Operating,
T
A
= 25°C,
V
V
= 5.25 V, f = 40.96 MHz
mA
mA
mA
pF
DDP
DD
x
IDLE instruction,
T
A
= – 55°C,
= 5.5 V,
f
= 50 MHz
x
30
7
DD
I
Supply current, standby
DD
IDLE2 instruction, Clocks shut off, T = – 55°C,
V
DD
= 5.5 V
A
C
C
Input capacitance
Output capacitance
15
15
i
pF
o
‡
§
¶
For conditions shown as MIN/MAX, use the appropriate value specified under “recommended operating conditions”.
All typical or nominal values are at V = 5 V, T = 25°C.
All input and output voltage levels are TTL-compatible. Figure 1 shows the tested load circuit; Figure 2 and Figure 3 show the voltage reference
DD
A
levels.
#
These values are not specified pending detailed characterization.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
PARAMETER MEASUREMENT INFORMATION
I
OL
Tester Pin
Electronics
Output
Under
Test
50 Ω
V
LOAD
C
T
I
OH
Where:
I
I
V
=
=
=
=
2.0 mA (all outputs)
300 µA (all outputs)
1.5 V
OL
OH
LOAD
T
C
80 pF typical load circuit capacitance
Figure 1. Test Load Circuit
signal transition levels
TTL-output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Figure 2 shows the TTL-level outputs.
2.4 V
2 V
1 V
0.6 V
Figure 2. TTL-Level Outputs
TTL-output transition times are specified as follows:
•
•
For a high-to-low transition, the level at which the output is said to be no longer high is 2 V, and the level
at which the output is said to be low is 1 V.
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V, and the level
at which the output is said to be high is 2 V.
Figure 3 shows the TTL-level inputs.
2.2 V
90%
10%
0.6 V
Figure 3. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
•
•
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high
is 2 V, and the level at which the input is said to be low is 0.8 V.
For a low to high transisiton on an input signal, the level at which the input is said to be no longer low is
0.8 V, and the level at which the input is said to be high is 2 V.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
CLOCK CHARACTERISTICS AND TIMING
The ’C50A can use either its internal oscillator or an external frequency source for a clock. The clock mode is
determined by the CLKMD1 and CLKMD2 pins. The following table outlines the selection of the clock mode by
these pins.
CLKMD1
CLKMD2
CLOCK SOURCE
External divide-by-one clock option
1
0
0
1
Reserved for test purposes
External divide-by-two option or internal divide-by-two clock option
with an external crystal
1
0
1
0
External divide-by-two option with the internal oscillator disabled
internal divide-by-two clock option with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT1
is one-half the crystal’s oscillating frequency. The crystal should be in either fundamental or overtone operation
and parallel resonant, with an effective series resistance of 30 Ω and a power dissipation of 1 mW; it should be
specified at a load capacitance of 20 pF. Overtone crystals require an additional tuned LC circuit. Figure 4 shows
an external crystal (fundamental frequency) connected to the on-chip oscillator.
recommended operating conditions for internal divide-by-two clock option
PARAMETER
Input clock frequency
C1, C2 Load capacitance
MIN NOM
MAX
40
UNIT
MHz
MHz
pF
†
SMJ320C50A-40
SMJ320C50A-50
0
0
f
x
‡
†
50
10
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz but is tested at a minimum of 3.3 MHz to meet device test time requirements.
Other timings for the ’C50A-50 device are the same as those for the ’C50A-40 device except where otherwise indicated.
approaching ∞. The device is characterized at frequencies
c(CI)
‡
X1
X2/CLKIN
Crystal
C1
C2
Figure 4. Internal Clock Option
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
external divide-by-two clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected, CLKMD1 set high, and CLKMD2 set high. The external frequency is divided by two to generate
the internal machine cycle. The external frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions [H = 0.5 t
]
c(CO)
PARAMETER
MIN
50 2t
TYP
MAX
UNIT
ns
†
’320C50-40
’320C50-50
c(CI)
t
Cycle time, CLKOUT1
c(CO)
‡
†
40 2t
ns
c(CI)
11
t
t
t
t
t
Delay time, CLKIN high to CLKOUT1 high/low
Fall time, CLKOUT1
6
20
ns
d(CIH-CO)
5
5
ns
f(CO)
Rise time, CLKOUT1
ns
r(CO)
Pulse duration, CLKOUT1 low
Pulse duration, CLKOUT1 high
H – 2
H – 2
H
H
H + 2
H + 2
ns
w(COL)
w(COH)
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
25
MAX
UNIT
ns
†
’320C50A-40
’320C50A-50
t
Cycle time, CLKIN
c(CI)
‡
†
5
20
ns
§
t
t
Fall time, CLKIN
ns
f(CI)
§
Rise time, CLKIN
5
†
ns
r(CI)
’320C50A-40
’320C50A-50
’320C50A-40
’320C50A-50
11
8
ns
t
Pulse duration, CLKIN low
Pulse duration, CLKIN high
w(CIL)
‡
‡
†
†
†
ns
11
8
ns
t
w(CIH)
ns
†
This device utilizes a fully static design and therefore can operate with t
c(CI)
approaching ∞. The device is characterized at frequencies
approaching 0 Hz, but is tested at a minimum of 6.7 MHz to meet device test time requirements.
Other timings for the ’C50A-50 device are the same as those for the ’C50A-40 device except where otherwise indicated.
Values derived from characterization data and not tested.
‡
§
t
r(CI)
t
t
f(CI)
w(CIH)
t
t
w(CIL)
c(CI)
CLKIN
t
f(CO)
t
c(CO)
t
r(CO)
t
d(CIH-CO)
t
w(COL)
t
w(COH)
CLKOUT1
Figure 5. External Divide-by-Two Clock Timing
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
external divide-by-one clock option
An external frequency source can be used by injecting the frequency directly into CLKIN2 with X1 left
unconnected and X2 connected to V . This external frequency is divided by one to generate the internal
DD
machine cycle. The divide-by-one option is used when CLKMD1 is strapped high and CLKMD2 is strapped low.
The external frequency injected must conform to specifications listed in the timing requirements table.
switching characteristics over recommended operating conditions [H = 0.5 t
]
c(CO)
PARAMETER
MIN
50
40
2
TYP
MAX
UNIT
ns
†
’320C50A-40
’320C50A-50
t
t
75
75
c(CI)
t
Cycle time, CLKOUT1
c(CO)
‡
†
ns
c(CI)
9
t
t
t
t
t
t
Delay time, CLKIN2 high to CLKOUT1 high
Fall time, CLKOUT1
16
ns
d(CIH-CO)
5
5
ns
f(CO)
Rise time, CLKOUT1
ns
r(CO)
Pulse duration, CLKOUT1 low
H – 2
H – 2
H
H
H + 2
H + 2
ns
w(COL)
w(COH)
p
Pulse duration, CLKOUT1 high
ns
§
256
¶
Transitory phase–PLL synchronized after CLKIN2 supplied
1000
cycles
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
50
MAX
UNIT
ns
†
’320C50A-40
’320C50A-50
75
75
t
Cycle time, CLKIN2
c(CI)
‡
†
40
ns
¶
t
t
Fall time, CLKIN2
5
5
ns
f(CI)
¶
Rise time, CLKIN2
ns
r(CI)
’320C50A-40
’320C50A-50
’320C50A-40
’320C50A-50
15
11
15
11
60
64
60
64
ns
t
Pulse duration, CLKIN2 low
Pulse duration, CLKIN2 high
w(CIL)
‡
ns
ns
t
w(CIH)
‡
ns
†
Clocks can be stopped only while the device executes IDLE2 when using the external divide-by-one clock option. Note that tp (the transitory
phase) will occur when restarting clock from IDLE2 in this mode.
‡
§
¶
Other timings for the ’C50A-50 device are the same as those for the ’C50A-40 device except where indicated otherwise.
Values are specified by design and not tested.
Values derived from characterization data and not tested.
t
w(CIL)
t
f(CI)
t
w(CIH)
t
r(CI)
t
c(CI)
CLKIN2
t
t
w(COH)
d(CIH-CO)
t
f(CO)
t
t
r(CO)
c(CO)
t
w(COL)
t
P
Unstable
CLKOUT1
Figure 6. External Divide-by-One Clock Timing
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
MEMORY AND PARALLEL I/O INTERFACE READ
switching characteristics over recommended operating conditions [H = 0.5t
]
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
†
‡
t
t
t
t
t
Setup time, address valid before RD low
H–10
0
su(A)R
h(A)R
w(RL)
w(RH)
d(RW)
†
‡
Hold time, address valid after RD high
§¶
ns
Pulse duration, RD low
H–8
H–8
ns
§¶
Pulse duration, RD high
ns
Delay time, RD high to WE low
2H–5
ns
†
A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
See Figure 8 for address bus timing variation with load capacitance.
STRB and RD timing is – 3/+5 ns from CLKOUT1 timing on read cycles, following the first cycle after reset, which is always a 7 wait-statecycle.
Values derived from characterization data and are not tested.
‡
§
¶
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t
]
c(CO)
MIN
MAX
UNIT
ns
‡
’320C50A-40
’320C50A-50
2H–15
2H–15
t
Access time, read data valid from address valid
a(A)
#
‡
ns
t
t
t
Access time, read data valid after RD low
Setup time, read data valid before RD high
Hold time, read data valid after RD high
H–10
ns
a(R)
10
0
ns
su(D)R
h(D)R
ns
‡
#
See Figure 8 for address bus timing variation with load capacitance.
Other timings for ’C50A-50 device are the same as for the ’C50A-40 device except where indicated otherwise.
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
MEMORY AND PARALLEL I/O INTERFACE WRITE
switching characteristics over recommended operating conditions [H = 0.5t
]
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
†
‡
t
t
t
t
t
t
t
t
Setup time, address valid before WE low
H – 5
su(A)W
h(A)W
w(WL)
w(WH)
d(WR)
su(D)W
h(D)W
en(D)W
†
‡
Hold time, address valid after WE high
H – 10
ns
§
Pulse duration, WE low
2H – 8
2H – 8
3H – 10
2H – 20
H – 5
ns
§
Pulse duration, WE high
Delay time, WE high to RD low
Setup time, write data valid before WE high
ns
ns
§
¶#
2H
ns
§
¶
Hold time, write data valid after WE high
Enable time, WE to data bus driven
H+10
ns
¶
–5
ns
†
‡
§
A15–A0,PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
See Figure 8 for address bus timing variation with load capacitance.
STRBandWEedgesare0–4nsfromCLKOUT1edgesonwrites. Risingandfallingedgesofthesesignalstrackeachother;toleranceofresulting
pulse durations is ± 2 ns, not ± 4 ns.
¶
#
Values derived from characterization data and are not tested.
This value holds true for zero or one wait state only.
ADDRESS
t
t
h(A)W
su(A)W
t
a(A)
R/W
t
h(D)R
t
a(R)
t
en(D)W
t
su(D)R
t
h(D)W
DATA
RD
t
t
su(D)W
t
t
su(A)R
h(A)R
t
d(WR)
t
d(RW)
t
w(RH)
t
w(WL)
w(RL)
WE
t
w(WH)
STRB
NOTE A: All timings are for 0 wait states. However, external writes always require two cycles to prevent external bus conflicts. The above diagram
illustrates a one-cycle read and a two-cycle write and is not drawn to scale. All external writes immediately preceded by an external read
or immediately followed by an external read require three machine cycles.
Figure 7. Memory and Parallel I/O Interface Read and Write Timing
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
2
1.75
1.50
1.25
1
0.75
0.50
0.25
10 15 20 25
30 35 40
45 50 55
60 65 70 75
80 85 90
95
Change in Load Capacitance – pF
Figure 8. Address Bus Timing Variation With Load Capacitance
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
READY TIMING FOR EXTERNALLY GENERATED WAIT STATES
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
10
MAX
UNIT
ns
t
t
t
t
t
t
Setup time, READY before CLKOUT1 rises
Hold time, READY after CLKOUT1 rises
Setup time, READY before RD falls
Hold time, READY after RD falls
su(R-CO)
h(CO-R)
su(R)R
h(R)R
0
ns
15
ns
5
ns
Valid time, READY after WE falls
Hold time, READY after WE falls
H – 15
H + 5
ns
v(R)W
ns
h(R)W
CLKOUT1
t
su(R-CO)
ADDRESS
t
h(CO-R)
READY
RD
Wait State
Generated
by READY
t
su(R)R
Wait State
Generated
Internally
t
h(R)R
Figure 9. Ready Timing for Externally Generated Wait States During an External Read Cycle
CLKOUT1
t
h(R-CO)
ADDRESS
READY
t
t
su(R-CO)
v(R)W
t
h(R)W
WE
Wait State Generated by READY
Figure 10. Ready Timing for Externally Generated Wait States During an External Write Cycle
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
RESET, INTERRUPT, AND BIO
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t
]
c(CO)
PARAMETER
MIN
15
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
†
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, INT1–INT4, NMI, before CLKOUT1 low
su(IN)
†
Hold time, INT1–INT4, NMI, after CLKOUT1 low
h(IN)
‡
4H+15
Pulse duration, INT1–INT4, NMI low, synchronous
Pulse duration, INT1–INT4, NMI high, synchronous
Pulse duration, INT1–INT4, NMI low, asynchronous
w(INL)s
w(INH)s
w(INL)a
w(INH)a
su(R)
‡¶
2H+15
6H+15
4H+15
§
‡
‡
§
Pulse duration, INT1–INT4, NMI high, asynchronous
Setup time, RS before X2/CLKIN low
Pulse duration, RS low
10
20H
34H
15
w(RSL)
d(EX)
Delay time, RS high to reset vector fetch
Pulse duration, BIO low, synchronous
w(BI)s
w(BI)a
su(BI)
h(BI)
§
Pulse duration, BIO low, asynchronous
Setup time, BIO before CLKOUT1 low
Hold time, BIO after CLKOUT1 low
H+15
15
0
†
These parameters must be met to use the synchronous timings. Both reset and the interrupts can operate asynchronously. The pulse durations
require an extra half-cycle to assure internal synchronization.
‡
§
¶
If in IDLE2, add 4H to these timings.
Values derived from characterization data and are not tested.
Values are specified by design and not tested.
X2/CLKIN
t
t
d(EX)
su(R)
t
W(RSL)
RS
t
t
su(BI)
su(IN)
CLKOUT1
t
w(BI)s
t
h(BI)
BIO
A15–A0
INT4–
INT1
t
t
h(IN)
su(IN)
t
su(IN)
t
w(INL)s
t
w(INH)s
Figure 11. Reset, Interrupt, and BIO Timings
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK),
EXTERNAL FLAG (XF), AND TOUT
switching characteristics over recommended operating conditions [H = 0.5t
]
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
†
‡
‡
‡
t
t
t
t
t
t
t
t
t
Setup time, address valid before IAQ low
Hold time, address valid after IAQ low
Pulse duration, IAQ low
H–14
su(A)IAQ
h(A)IAQ
w(IAQL)
d(TOUT)
su(A)IACK
h(A)IACK
w(IACKL)
w(TOUT)
d(XF)
H–8
ns
H–10
ns
Delay time, CLKOUT1 falling to TOUT
–6
6
ns
§
‡
‡
‡
Setup time, address valid before IACK low
H–14
H–8
ns
§
Hold time, address valid after IACK high
Pulse duration, IACK low
ns
H–10
ns
Pulse duration, TOUT
2H–12
0
ns
Delay time, XF valid after CLKOUT1
12
ns
†
IAQ goes low during an instruction acquisition. It goes low only on the first cycle of the read when wait states are used. The falling edge should
be used to latch the valid address. The AVIS bit in the PMST register must be set to zero for the address to be valid when the instruction being
addressed resides in on-chip memory.
‡
§
Valid only if the external address reflects the current instruction activity (that is, code is executing on chip with no external bus cycles and AVIS
is on, or code is executing off-chip).
IACK goes low during the fetch of the first word of the interrupt vector. It goes low only on the first cycle of the read when wait states are used.
Address pins A1 – A4 can be decoded at the falling edge to identify the interrupt being acknowledged. The AVIS bit in the PMST register must
be set to zero for the address to be valid when the vectors reside in on-chip memory.
t
h(A)IAQ
ADDRESS
t
su(A)IAQ
t
w(IAQL)
IAQ
t
h(A)IACK
t
su(A)IACK
IACK
t
w(IACKL)
STRB
CLKOUT1
t
d(XF)
t
d(TOUT)
t
d(TOUT)
XF
TOUT
t
w(TOUT)
NOTE: IAQ and IACK are not affected by wait states.
Figure 12. IAQ, IACK, and XF Timings Example With Two External Wait States
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
EXTERNAL DMA
switching characteristics over recommended operating conditions [H = 0.5t
] (see Note 2)
c(CO)
PARAMETER
Delay time, HOLD low to HOLDA low
MIN
4H
2H
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
‡
t
t
t
t
t
t
t
t
t
t
t
t
d(H-HA)
d(HH-HA)
dis(M-HA)
en(HA-M)
d(B-I)
Delay time, HOLD high before HOLDA high
Disable time, address in the high-impedance state before HOLDA low
Enable time, HOLDA high to address driven
Delay time, XBR low to IAQ low
§
†
†
†
†
H–15
H–5
4H
†
†
6H
Delay time, XBR high to IAQ high
2H
4H
d(BH-I)
Delay time, read data valid after XSTRB low
Hold time, read data after XSTRB high
40
d(D)XR
h(D)XR
en(I-D)
0
†
¶
†
†
†
†
Enable time, IAQ low to read data driven
0
0
2H
15
H
†
Disable time, XR/W low to data in the high-impedance state
Disable time, IAQ high to data in the high-impedance state
Enable time, data from XR/W going high
dis(W)
dis(I-D)
en(D)RW
4
†
Values derived from characterization data and are not tested.
HOLD is not acknowledged until current external access request is complete.
This parameter includes all memory control lines.
This parameter refers to the delay between the time the condition (IAQ = 0 and XR/W = 1) is satisfied and the time that the SMJ320C50A data
lines become valid.
‡
§
¶
NOTE 2: X preceding a name refers to the external drive of the signal.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
ns
#
#
t
t
t
t
t
t
t
t
t
t
Delay time, HOLDA low to XBR low
0
0
d(HA-B)
#
#
Delay time, IAQ low to XSTRB low
ns
d(I-XS)
Setup time, Xaddress valid before XSTRB low
Setup time, Xdata valid before XSTRB low
Hold time, Xdata hold after XSTRB low
Hold time, write Xaddress hold after XSTRB low
Pulse duration, XSTRB low
15
15
15
15
45
45
20
0
ns
su(XA)
ns
su(XD)W
h(WD)W
h(XA)W
w(XSL)
w(XSH)
su(XS)RW
h(XA)R
ns
ns
ns
Pulse duration, XSTRB high
ns
Setup time, R/W valid before XSTRB low
Hold time, read Xaddress after XSTRB high
ns
ns
#
XBR, XR/W, and XSTRB lines should be pulled up with a 10-kΩ resistor to assure that they are in an inactive (high) state during the transition
period between the SMJ320C50A driving them and the external circuit driving them.
NOTE 2. X preceding a name refers to the external drive of the signal.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
EXTERNAL DMA
HOLD
t
d(HH-HA)
t
d(H-HA)
HOLDA
t
en(HA-M)
t
dis(M-HA)
Address
Bus/
Control
†
Signals
t
en(I-B)
t
d(HA-B)
XBR
IAQ
t
d(B-I)
t
d(BH-I)
t
d(I-XS)
t
su(XS)RW
XSTRB
XR/W
t
w(XSH)
t
w(XSL)
t
dis(W)
t
su(XA)
t
h(D)XR
t
h(XA)R
t
en(I-D)
XADDRESS
t
d(D)XR
t
su(XA)
t
h(XA)W
t
dis(I-D)
DATA(RD)
t
en(I-D)
t
t
en(D)RW
h(WD)W
t
su(XD)W
XDATA(WR)
†
A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address bus/control signals.
Figure 13. External DMA Timing
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
SERIAL-PORT RECEIVE
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t
]
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
†
t
t
t
t
t
t
t
t
Cycle time, serial-port clock
Fall time, serial-port clock
Rise time, serial-port clock
5.2H
c(SCK)
f(SCK)
r(SCK)
w(SCK)
su(FS)
h(FS)
‡
‡
8
ns
8
ns
Pulse duration, serial-port clock low/high
Setup time, FSR before CLKR falling edge
Hold time, FSR after CLKR falling edge
Setup time, DR before CLKR falling edge
Hold time, DR after CLKR falling edge
2.1H
10
ns
ns
10
ns
10
ns
su(DR)
h(DR)
10
ns
†
The serial-port design is fully static and therefore can operate with t
0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and are not tested.
approaching ∞. It is characterized approaching an input frequency of
c(SCK)
‡
t
c(SCK)
t
f(SCK)
t
w(SCK)
CLKR
FSR
t
t
r(SCK)
h(FS)
t
w(SCK)
t
su(FS)
t
su(DR)
t
h(DR)
DR
Bit
1
2
7 or 15
(see Note A)
8 or 16
(see Note A)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet.
Figure 14. Serial-Port Receive Timing
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
SERIAL-PORT TRANSMIT, EXTERNAL CLOCKS AND EXTERNAL FRAMES
switching characteristics over recommended operating conditions (see Note 3)
PARAMETER
MIN
MAX
UNIT
ns
t
t
t
Delay time, DX valid after CLKX rising
Disable time, DX valid after CLKX rising
Hold time, DX valid after CLKX rising
25
d(DX)
dis(DX)
h(DX)
†
40
ns
–6
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t ] (see Note 3)
c(CO)
MIN
MAX
UNIT
ns
t
t
t
t
t
t
t
Cycle time, serial-port clock
Fall time, serial-port clock
Rise time, serial-port clock
5.2H
‡
c(SCK)
f(SCK)
r(SCK)
w(SCK)
d(FS)
†
8
8
ns
†
ns
Pulse duration, serial-port clock low/high
Delay time, FSX after CLKX rising edge
Hold time, FSX after CLKX falling edge
Hold time, FSX after CLKX rising edge
2.1H
10
ns
2H–8
ns
ns
h(FS)
†§
2H–8
ns
h(FS)H
†
‡
Values derived from characterization data and are not tested.
The serial-port design is fully static and therefore can operate with t
0 Hz but tested at a much higher frequency to minimize test time.
approaching ∞. It is characterized approaching an input frequency of
c(SCK)
§
If the FSX pulse does not meet this specification, the first bit of serial data will be driven on the DX pin until the falling edge of FSX. After the falling
edgeofFSX,datawillbeshiftedoutontheDXpin.Thetransmit-buffer-emptyinterruptwillbegeneratedwhenthet
is met.
t
specification
h(FS)and h(FS)H
NOTE 3: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX are always defined depending on
the source of FSX, and CLKX timings are always dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
t
c(SCK)
t
f(SCK)
t
w(SCK)
CLKX
t
t
r(SCK)
d(FS)
t
h(FS)H
t
h(FS)
t
w(SCK)
FSX
t
d(DX)
t
dis(DX)
t
h(DX)
DX Bit
1
2
7 or 15
(see Note A)
8 or 16
(see Note A)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet.
Figure 15. Serial-Port Transmit Timing of External Clocks and External Frames
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
SERIAL-PORT TRANSMIT, INTERNAL CLOCKS AND INTERNAL FRAMES
switching characteristics over recommended operating conditions [H = 0.5t ] (see Note 3)
c(CO)
PARAMETER
MIN
TYP
MAX
25
UNIT
ns
t
t
t
t
t
t
t
t
Delay time, CLKX rising to FSX
Delay time, CLKX rising to DX
Disable time, CLKX rising to DX
Cycle time, serial-port clock
Fall time, serial-port clock
d(FS)
25
ns
d(DX)
†
40
ns
dis(DX)
c(SCK)
f(SCK)
r(SCK)
w(SCK)
h(DX)
8H
5
ns
ns
Rise time, serial-port clock
5
ns
Pulse duration, serial-port clock low/high
Hold time, DX valid after CLKX rising
4H – 20
– 6
ns
ns
†
Values derived from characterization and not tested.
NOTE 3: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX are always defined depending on
the source of FSX, and CLKX timings are always dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
t
)
c(SCK
t
f(SCK)
t
w(SCK)
CLKX
FSX
t
t
d(FS)
w(SCK)
t
r(SCK)
t
d(FS)
t
d(DX)
t
dis(DX)
t
h(DX)
DX
Bit
1
2
7 or 15
(see Note A)
8 or 16
(see Note A)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet.
Figure 16. Serial-Port Transmit Timing of Internal Clocks and Internal Frames
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
SERIAL-PORT RECEIVE IN TDM MODE
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t
]
c(CO)
MIN
MAX
UNIT
ns
†
t
t
t
t
t
t
t
t
t
t
Cycle time, serial-port clock
5.2H
c(SCK)
f(SCK)
r(SCK)
w(SCK)
su(LB)
h(LB)
‡
‡
Fall time, serial-port clock
8
ns
Rise time, serial-port clock
8
ns
Pulse duration, serial-port clock low/high
Setup time, TDAT/TADD before TCLK rising
Hold time, TDAT/TADD after TCLK rising
Setup time, TDAT/TADD before TCLK rising
2.1H
30
–5
25
0
ns
ns
ns
§
ns
su(SB)
h(SB)
§
Hold time, TDAT/TADD after TCLK rising
ns
¶
Setup time, TRFM before TCLK rising edge
10
10
ns
su(FS)
h(FS)
¶
Hold time, TRFM after TCLK rising edge
ns
†
The serial-port design is fully static and therefore can operate with t
0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and are not tested.
These parameters apply only to the first bits in the serial bit string.
TFRM timing and waveforms shown in Figure 17 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 18.
approaching ∞. It is characterized approaching an input frequency of
c(SCK)
‡
§
¶
t
t
f(SCK)
w(SCK)
t
t
w(SCK)
r(SCK)
TCLK
TDAT
t
t
su(LB)
c(SCK)
t
h(LB)
B13
B15
B1
B0
B0
B14
B12
A3
B8
A7
B7
B2
t
t
h(SB)
t
su(SB)
h(SB)
t
su(FS)
TADD
TFRM
A0
A1
A2
t
h(FS)
Figure 17. Serial-Port Receive Timing in TDM Mode
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
SERIAL-PORT TRANSMIT IN TDM MODE
switching characteristics over recommended operating conditions [H = 0.5t
]
c(CO)
MIN
–2
PARAMETER
MAX
UNIT
ns
t
t
t
Hold time, TDAT/TADD valid after TCLK rising
h(AD)
d(FS)
d(AD)
†
Delay time, TFRM valid after TCLK rising
Delay time, TCLK to valid TDAT/TADD
H
3H+10
25
ns
ns
†
TFRM timing and waveforms shown in Figure 18 are for internal TFRM. TFRM can also be configured as external, and the TFRM external case
is illustrated in the receive timing diagram in Figure 17.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [(H = 0.5t
]
c(CO)
MIN
TYP
MAX
UNIT
ns
‡
8H
§
t
t
t
t
Cycle time, serial-port clock
Fall time, serial-port clock
Rise time, serial-port clock
5.2H
c(SCK)
f(SCK)
r(SCK)
w(SCK)
¶
8
8
ns
¶
ns
Pulse duration, serial-port clock low/high
2.1H
ns
‡
§
When SCK is generated internally.
The serial-port design is fully static and therefore can operate with t
0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and are not tested.
approaching ∞. It is characterized approaching an input frequency of
c(SCK)
¶
t
f(SCK)
t
w(SCK)
t
w(SCK)
t
r(SCK)
TCLK
t
t
c(SCK)
d(AD)
B14
h(AD)
B15
TDAT
TADD
B0
B13
A2
B12
A3
B8 B7
B2
B1
B0
t
t
h(SB)
t
d(AD)
A1
A7
t
d(FS)
A0
t
d(FS)
TFRM
Figure 18. Serial-Port Transmit Timing in TDM Mode
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
MECHANICAL DATA
SMJ320C50 132-lead non-conductive ceramic tie bar (HFG suffix)
51,44 (2.025) MAX
24, 38 (0.960)
24, 00 (0.945)
20, 45 (0.806)
0,13 (.005) TYP
20, 19 (0.795)
Pin 1 Indicator
51, 18 (2.015)
50, 56 (1.990)
30,73
(1.210)
TYP
Detail A
Detail B
0,64 (0.025) TYP
0,635
1,02 (0.040)
0,76 (0.030)
(0.025)
MAX
Thermal Resistance Characteristics
1, 77 (0.070)
1, 27 (0.050)
PARAMETER
°C/W
R
ΘJC
R
ΘJA
2.0
38.4
0, 406 (0.016)
0, 254 (0.010)
0, 228 (0.009)
0, 127 (0.005)
0, 330 (0.013)
0, 152 (0.006)
2, 31 (0.091)
1, 95 (0.077)
Detail A
0, 35 (0.014)
0, 05 (0.002)
(At Braze Pads)
Detail B
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50A
DIGITAL SIGNAL PROCESSOR
SGUS018 – JANUARY 1994
MECHANICAL DATA
GFA/S-CPGA1-P141
SMJ320C31 CERAMIC PIN GRID ARRAY, CAVITY UP
1.080 (27,43)
1.040 (26,42)
SQ
0.900 (22,86) TYP
V
U
S
P
M
K
H
F
Y
R
N
L
J
G
E
C
A
D
B
2
4
6
8
10 12 14 16 18
9 11 13 15 17 19
1
3
5
7
0.025 (0,64)
0.006 (0,15)
0.034 (0,86) TYP
0.145 (3,68)
0.110 (2,79)
0.140 (3,56)
0.120 (3,05)
0.048 (1,22) DIA TYP
4 Places
0.050 (1,27) TYP
0.0215 (0,55)
0.0160 (0,41)
DIA TYP
4040133/A–10/93
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Thermal Resistance Characteristics
PARAMETER
°C/W
R
R
1.0
ΘJC
39.0
ΘJA
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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