SMJ320VC33 [TI]
DIGITAL SIGNAL PROCESSOR; 数字信号处理器
| 型号： | SMJ320VC33 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL SIGNAL PROCESSOR |
| 文件： | 总54页 (文件大小：608K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
D High-Performance Floating-Point Digital
Signal Processor (DSP):
D On-Chip Memory-Mapped Peripherals:
- One Serial Port
- SM/SMJ320VC33-150
- Two 32-Bit Timers
- 13-ns Instruction Cycle Time
- 150 Million Floating-Point Operations
Per Second (MFLOPS)
- Direct Memory Access (DMA)
Coprocessor for Concurrent I/O and CPU
Operation
- 75 Million Instructions Per Second
(MIPS)
D 164-Pin Low-Profile Quad Flatpack (HFG
Suffix)
D 34K × 32-Bit (1.1-Mbit) On-Chip Words of
Dual-Access Static Random-Access
Memory (SRAM) Configured in 2 × 16K plus
2 × 1K Blocks to improve Internal
Performance
D 144-Pin Non-hermetic Ceramic Ball Grid
Array (CBGA) (GNM Suffix)
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D x5 Phase-Locked Loop (PLL) Clock
D Two Low-Power Modes
Generator
D Two- and Three-Operand Instructions
D Very Low Power: < 200 mW @ 150 MFLOPS
D 32-Bit High-Performance CPU
D Parallel Arithmetic/Logic Unit (ALU) and
Multiplier Execution in a Single Cycle
D 16-/32-Bit Integer and 32-/40-Bit
D Block-Repeat Capability
Floating-Point Operations
D Zero-Overhead Loops With Single-Cycle
D Four Internally Decoded Page Strobes to
Simplify Interface to I/O and Memory
Devices
Branches
D Conditional Calls and Returns
D Interlocked Instructions for
D Boot-Program Loader
Multiprocessing Support
D EDGEMODE Selectable External Interrupts
D 32-Bit Instruction Word, 24-Bit Addresses
D Eight Extended-Precision Registers
D Bus-Control Registers Configure
Strobe-Control Wait-State Generation
D 1.8-V (Core) and 3.3-V (I/O) Supply Voltages
D Fabricated Using the 0.18-µm (l -Effective
eff
Gate Length) TImeline Technology by
Texas Instruments (TI)
description
The SM/SMJ320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal
CMOS (TImeline) technology. The SM/SMJ320VC33 is part of the SM320C3x generation of DSPs from Texas
Instruments.
The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and
flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The SM/SMJ320VC33
optimizes speed by implementing functions in hardware that other processors implement through software or
microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TImeline and SM320C3x are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL−PRF−38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
description (continued)
The SM/SMJ320VC33 can perform parallel multiply and ALU operations on integer or floating-point data in a
single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated
ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short
machine-cycle time. High performance and ease of use are the results of these features.
General-purpose applications are greatly enhanced by the large address space, multiprocessor interface,
internally and externally generated wait states, one external interface port, two timers, one serial port, and
multiple-interrupt structure. The SM320C3x supports a wide variety of system applications from host processor
to dedicated coprocessor. High-level-language support is easily implemented through a register-based
architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported
floating-point arithmetic.
JTAG scan-based emulation logic
The 320VC33 contains a JTAG port for CPU emulation within a chain of any number of other JTAG devices.
The JTAG port on this device does not include a pin-by-pin boundary scan for point-to-point board level test.
The Boundary Scan tap input and output is internally connected with a single dummy register allowing loop back
tests to be performed through that JTAG domain.
The JTAG emulation port of this device also includes two additional pins, EMU0 and EMU1, for global control
of multiple processors conforming to the TI emulation standard. These pins are open collector-type outputs
which are wire ORed and tied high with a pullup. Non-TI emulation devices should not be connected to these
pins.
The VC33 instruction register is 8 bits long. Table 1 shows the instructions code. The uses of SAMPLE and
HIGHZ opcodes, though defined, have no meaning for the SM/SMJ320VC33, which has no boundary scan. For
example, HIGHZ will affect only the dummy cell (no meaning) and will not put the device pins in a
high-impedance state.
Table 1. Boundary-Scan Instruction Code
INSTRUCTION NAME
EXTEST
INSTRUCTION CODE
00000000
11111111
00000010
00000110
00000011
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
BYPASS
SAMPLE
Boundry is only one dummy cell
Boundry is only one dummy cell
HIGHZ
†
PRIVATE1
†
PRIVATE2
†
PRIVATE3
†
PRIVATE4
†
PRIVATE5
†
PRIVATE6
†
PRIVATE7
†
PRIVATE8
†
PRIVATE9
†
PRIVATE10
†
PRIVATE11
†
Use of Private opcodes could cause the device to operate in an unexpected manner.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
pinout
†‡
HFG PACKAGE
(TOP VIEW)
NC
NC
NC
1
2
3
4
5
6
7
8
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
NC
NC
NC
A20
DV
DD
V
SS
CLKR
FSR0
A19
A18
A17
V
SS
DR0
TRST
TMS
DV
DD
9
A16
A15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CV
DD
V
SS
TDI
TDO
TCK
V
SS
EMU0
EMU1
A14
A13
CV
DD
A12
A11
DV
DD
DV
D0
D1
D2
D3
DD
A10
A9
V
SS
A8
A7
A6
A5
V
SS
D4
D5
DV
D6
D7
CV
D8
D9
DV
DD
A4
98
97
96
95
DD
DD
V
SS
A3
A2
94
CV
DD
A1
93
92
91
90
89
88
87
86
85
84
83
V
SS
A0
D10
D11
DV
DD
PAGE3
PAGE2
DV
DD
D12
D13
D14
D15
NC
V
SS
PAGE1
PAGE0
NC
NC
41
NC
NC - No internal connection
†
DV is the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O
DD
DD
SS
pins and the core CPU.
‡
PLLV and PLLV are isolated PLL supply pins that should be externally connected to CV and V respectively.
SS,
DD
SS
DD
The SM/SMJ320VC33 device is packaged in 164-pin low-profile quad flatpacks (HFG Suffix) and in 144-ball
fine pitch ball grid arrays (GNL and GNM Suffix).
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
†
GNM Terminal Assignments (Sorted by Signal Name)
SIGNAL
NAME
PIN
NUMBER
SIGNAL
NAME
PIN
NUMBER
SIGNAL
NAME
PIN
NUMBER
SIGNAL
NAME
PIN
NUMBER
A0
A1
J2
K2
K1
J4
D0
D1
G12
G10
F13
G11
H10
H13
H12
J10
J11
J12
K13
K12
K10
M13
L11
L12
M12
L10
K9
M1
N1
R/W
RDY
L4
M5
B7
A2
D2
N4
RESET
RSV0
RSV1
SHZ
A3
D3
N7
B4
A4
H4
H3
H1
G4
G1
G2
F3
D4
M8
N12
L13
H11
F11
B12
A10
A6
D5
A5
D5
D7
A6
D6
STRB
TCK
M4
F10
C10
A11
E11
D13
E10
C13
B1
DV
DD
A7
D7
A8
D8
TCLK0
TCLK1
TDI
A9
D9
A10
A11
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
DR0
F4
TDO
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
CLKMD0
CLKMD1
CLKR0
CLKX0
F2
A1
TMS
E1
E2
E4
C1
C2
D3
C3
B2
D4
A2
B3
C5
B5
B13
B11
E3
J3
DX0
EDGEMODE
EMU0
EMU1
EXTCLK
FSR0
A12
A7
TRST
F12
E12
C6
D1
G3
J1
C12
D10
L3
L2
N11
M11
M10
K8
FSX
M3
M6
L7
H1
H3
N2
HOLD
HOLDA
IACK
N5
N10
N13
K11
G13
E13
A13
C11
C9
V
SS
N9
K5
M9
K4
L8
INT0
C8
N8
INT1
B9
M7
INT2
D8
K7
INT3
A9
L6
MCBL/MP
PAGE0
PAGE1
PAGE2
PAGE3
B8
L5
N6
M2
N3
C7
L9
K6
C4
CV
DD
J13
D12
A8
A3
D11
D2
L1
XF0
XF1
B10
D9
K3
‡
PLLV
DD
F1
A5
XIN
B6
DV
DD
‡
H2
PLLV
A4
XOUT
D6
SS
†
‡
DV is the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O pins and the core
CPU.
DD
DD
SS
PLLV and PLLV are isolated PLL supply pins that should be externally connected to CV and V respectively.
SS,
DD
SS
DD
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
†
GNM Terminal Assignments (Sorted by Pin Number)
PIN
NUMBER
SIGNAL
NAME
PIN
NUMBER
SIGNAL
NAME
PIN
NUMBER
SIGNAL
NAME
PIN
NUMBER
SIGNAL
NAME
A1
A2
DV
C11
C12
C13
D1
V
G10
G11
G12
G13
H1
D1
D3
D0
L4
L5
R/W
DD
SS
A22
FSR0
TRST
CV
DD
A3
CV
L6
D29
DD
A4
PLLV
PLLV
V
V
L7
V
SS
SS
SS
SS
A5
D2
DV
A6
DV
L8
D25
CV
DD
DD
A6
DV
D3
A18
H2
L9
DD
DD
DD
A7
EDGEMODE
CV
D4
A21
RSV1
XOUT
SHZ
H3
A5
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
D17
D14
D15
A8
D5
H4
A4
D4
DD
A9
INT3
DV
D6
H10
H11
H12
H13
J1
A10
A11
A12
A13
B1
D7
DV
DV
DD
DD
DD
DD
TCLK1
DX
D8
INT2
XF1
D6
D5
DV
D9
PAGE0
V
V
D10
D11
D12
D13
E1
FSX
V
V
SS
SS
SS
SS
DR0
J2
A0
CV
STRB
RDY
B2
A20
A23
CV
J3
DD
DD
B3
TDO
A13
A14
J4
A3
D7
D8
D9
V
SS
B4
RSV0
CLKMD1
XIN
J10
J11
J12
J13
K1
D27
DV
B5
E2
DD
B6
E3
CV
D24
D21
D20
D16
D13
DD
B7
RESET
MCBL/MP
INT1
E4
A15
CV
DD
B8
E10
E11
E12
E13
F1
TMS
TDI
A2
A1
B9
K2
B10
B11
B12
B13
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
XF0
EMU1
K3
PAGE3
IACK
HOLDA
D31
CLKX0
V
K4
DV
DD
SS
DV
DV
K5
N2
H3
DD
DD
CLKR
A16
F2
A12
K6
N3
PAGE1
F3
A10
A11
TCK
K7
D28
N4
DV
DD
A17
F4
K8
D22
N5
HOLD
D30
A19
F10
F11
F12
F13
G1
K9
D18
N6
V
DV
K10
K11
K12
K13
L1
D12
N7
DV
DD
SS
DD
CLKMD0
EXTCLK
EMU0
D2
V
N8
D26
D23
SS
D11
D10
N9
V
A8
N10
N11
N12
N13
V
SS
SS
INT0
G2
A9
PAGE2
D19
DV
V
G3
V
L2
V
SS
SS
SS
DD
TCLK0
G4
A7
L3
H1
V
SS
†
‡
DV is the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O pins and the core
CPU.
DD
DD
SS
PLLV and PLLV are isolated PLL supply pins that should be externally connected to CV and V respectively.
SS,
DD
SS
DD
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
Terminal Functions
CONDITIONS
WHEN
SIGNAL IS Z TYPE
TERMINAL
†
DESCRIPTION
TYPE
NAME
QTY
‡
PRIMARY-BUS INTERFACE
32-bit data port
S
S
S
H
R
D31- D0
32
24
1
I/O/Z
O/Z
O/Z
O/Z
O/Z
Data port bus keepers. (See Figure 9)
24-bit address port
A23- A0
R/W
H
H
H
H
R
R
Read/write. R/W is high when a read is performed and low when a write is performed
over the parallel interface.
S
S
S
STRB
1
Strobe. For all external-accesses
PAGE0 -
PAGE3
1
Page strobes. Four decoded page strobes for external access
R
Ready. RDY indicates that the external device is prepared for a transaction
completion.
RDY
1
1
I
I
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23- A0,
D31-D0, STRB, and R/W are placed in the high-impedance state and all
transactions over the primary-bus interface are held until HOLD becomes a logic high
or until the NOHOLD bit of the primary-bus-control register is set.
HOLD
Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD.
HOLDA indicates that A23-A0, D31-D0, STRB, and R/W are in the high-impedance
state and that all transactions over the bus are held. HOLDA is high in response to
a logic-high of HOLD or the NOHOLD bit of the primary-bus-control register is set.
HOLDA
1
O/Z
S
CONTROL SIGNALS
Reset. When RESET is a logic low, the device is in the reset condition. When RESET
RESET
1
I
becomes a logic high, execution begins from the location specified by the reset vec-
tor.
EDGEMODE
INT3- INT0
1
4
I
I
Edge mode. Enables interrupt edge mode detection.
External interrupts
Internal acknowledge. IACK is generated by the IACK instruction. IACK can be used
to indicate when a section of code is being executed.
IACK
1
1
O/Z
I
S
MCBL/MP
Microcomputer Bootloader/microprocessor mode-select
Shutdown high impedance. When active, SHZ places all pins in the high-impedance
state. SHZ can be used for board-level testing or to ensure that no dual-drive
conditions occur. CAUTION: A low on SHZ corrupts the device memory and register
contents. Reset the device with SHZ high to restore it to a known operating condition.
SHZ
1
2
I
External flags. XF1 and XF0 are used as general-purpose I/Os or to support
interlocked processor instruction.
XF1, XF0
I/O/Z
S
R
SERIAL PORT 0 SIGNALS
CLKR0
CLKX0
1
1
I/O/Z
I/O/Z
Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver.
S
S
R
R
Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter.
DR0
DX0
1
1
I/O/Z
I/O/Z
Data-receive. Serial port 0 receives serial data on DR0.
S
S
R
R
Data-transmit output. Serial port 0 transmits serial data on DX0.
Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive
process using DR0.
FSR0
FSX0
1
1
I/O/Z
I/O/Z
S
S
R
R
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit
process using DX0.
†
‡
§
I = input, O = output, Z = high-impedance state
S = SHZ active, H = HOLD active, R = RESET active
Recommended decoupling. Four 0.1 µF for CV and eight 0.1 µF for DV
.
DD
DD
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
Terminal Functions (Continued)
CONDITIONS
WHEN
SIGNAL IS Z TYPE
TERMINAL
NAME
†
DESCRIPTION
TYPE
QTY
‡
TIMER SIGNALS
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As
an output, TCLK0 outputs pulses generated by timer 0.
TCLK0
1
1
I/O/Z
I/O/Z
S
S
R
R
Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As
an output, TCLK1 outputs pulses generated by timer 1.
TCLK1
SUPPLY AND OSCILLATOR SIGNALS
External H1 clock
H1
H3
1
1
O/Z
O/Z
S
S
External H3 clock
+V . Dedicated 1.8-V power supply for the core CPU. All must be connected to
a common supply plane.
DD
CV
DV
8
I
I
DD
DD
§
+V . Dedicated 3.3-V power supply for the I/O pins. All must be connected to a
DD
16
§
common supply plane.
V
18
1
I
I
I
Ground. All grounds must be connected to a common ground plane.
SS
PLLV
PLLV
Internally isolated PLL supply. Connect to CV (1.8 V)
DD
DD
SS
1
Internally isolated PLL ground. Connect to V
SS
External clock. Logic level compatible clock input. If the XIN/XOUT oscillator is
used, tie this pin to ground.
EXTCLK
XOUT
XIN
1
1
1
I
O
I
Clock out. Output from the internal-crystal oscillator. If a crystal is not used, XOUT
should be left unconnected.
Clock in. Internal-oscillator input from a crystal. If EXTCLK is used, tie this pin to
ground.
CLKMD0,
CLKMD1
2
2
I
I
Clock mode select pins
RSV0 - RSV1
Reserved. Use individual pullups to DV
.
DD
JTAG EMULATION
EMU1- EMU0
TDI
2
1
1
1
1
1
I/O
Emulation pins 0 and 1, use individual pullups to DV
DD
I
O
I
Test data input
Test data output
Test clock
TDO
TCK
TMS
I
Test mode select
Test reset
TRST
I
†
‡
§
I = input, O = output, Z = high-impedance state
S = SHZ active, H = HOLD active, R = RESET active
Recommended decoupling. Four 0.1 µF for CV and eight 0.1 µF for DV
.
DD
DD
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
functional block diagram
RAM
RAM
RAM
RAM
Cache
(64 × 32)
Block 0
Block 1
Boot
Loader
Block 2
Block 3
(1K × 32)
(1K × 32)
(16K × 32)
(16K × 32)
24
32
24
32
24
32
32
32
24
32
24
24
PDATA Bus
PADDR Bus
PAGE0
PAGE1
PAGE2
PAGE3
RDY
DDATA Bus
DADDR1 Bus
DADDR2 Bus
HOLD
HOLDA
STRB
R/W
DMADATA Bus
DMAADDR Bus
D31- D0
A23- A0
32
24
24
32
32
24
24
Peripheral Data Bus
DMA Controller
Global-Control
Register
Serial Port 0
MUX
IR
PC
Serial-Port-Control
Register
Source-Address
Register
FSX0
RSV(0,1)
SHZ
EDGEMODE
CPU1
CPU2
REG1
REG2
DX0
Receive/Transmit
(R/X) Timer Register
CLKX0
FSR0
DR0
Destination-
Address
Register
RESET
INT(3- 0)
IACK
Data-Transmit
Register
CLKR0
Transfer-
Counter
Register
MCBL/MP
XF(1,0)
TDI
Data-Receive
Register
32
32
40
40
32-Bit
Barrel
Shifter
TDO
EMU0
Multiplier
Timer 0
EMU1
Global-Control
Register
ALU
TCK
TMS
TRST
40
40
Timer-Period
Register
40
40
TCLK0
40
Extended-
Precision
Registers
(R7-R0)
EXTCLK
XOUT
XIN
40
32
Timer-Counter
Register
H1
H3
Timer 1
CLKMD(0,1)
DISP0, IR0, IR1
Global-Control
Register
ARAU0
ARAU1
BK
Timer-Period
Register
TCLK1
24
24
Timer-Counter
Register
24
24
Auxiliary
Registers
(AR0- AR7)
32
32
Port Control
32
32
STRB-Control
Register
32
32
Other
Registers
(12)
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
memory map
0h
0h
Reset, Interrupt, Trap Vector, and
Reserved Locations (64)
(External STRB Active)
03Fh
040h
Reserved for Bootloader
Operations
FFFh
1000h
External
STRB Active
Boot 1
External
STRB
(8M Words - 64 Words)
Active
(8M Words -
4K Words)
400000h
Boot 2
7FFFFFh
800000h
7FFFFFh
800000h
RAM Block 2
(16K Words Internal)
RAM Block 2
(16K Words Internal)
803FFFh
804000h
803FFFh
804000h
RAM Block 3
(16K Words Internal)
RAM Block 3
(16K Words Internal)
807FFFh
808000h
807FFFh
808000h
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
8097FFh
809800h
8097FFh
809800h
RAM Block 0
(1K Words Internal)
RAM Block 0
(1K Words Internal)
809BFFh
809C00h
809BFFh
809C00h
RAM Block 1
(1K Words Internal)
RAM Block 1
(1K Words Internal)
User-Program Interrupt
and Trap Branch Table
809FC0h
809FC1h
809FFFh
80A000h
63 Words
External
809FFFh
80A000h
External
STRB Active
(8M Words - 40K Words)
STRB Active
(8M Words -
40K Words)
Boot 3
FFF000h
FFFFFFh
FFFFFFh
(b) Microcomputer/Bootloader Mode
(a) Microprocessor Mode
NOTE A: STRB is active over all external memory ranges. PAGE0 to PAGE3 are configured as external bus strobes. These are simple
decoded strobes that have no configuration registers and are active only during external bus activity over the following ranges:
Name
Active range
PAGE0
PAGE1
PAGE2
PAGE3
STRB
0000000h – 03FFFFFh
0400000h – 07FFFFFh
0800000h – 0BFFFFFh
0C00000h – 0FFFFFFh
0000000h – 0FFFFFFh
Figure 1. SM/SMJ320VC33 Memory Maps
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
memory map (continued)
00h
809FC1h
Reset
INT0
01h
02h
INT0
INT1
809FC2h
809FC3h
809FC4h
809FC5h
INT1
INT2
INT2
INT3
03h
04h
INT3
XINT0
05h
06h
XINT0
RINT0
809FC6h
RINT0
07h
08h
809FC7h
809FC8h
Reserved
TINT0
Reserved
09h
809FC9h
809FCAh
TINT0
TINT1
0Ah
0Bh
TINT1
DINT
809FCBh
DINT
0Ch
1Fh
809FCCh
809FDFh
Reserved
Reserved
TRAP 0
809FE0h
20h
TRAP 0
3Bh
TRAP 27
809FFBh
TRAP 27
Reserved
3Ch
3Fh
809FFCh
809FFFh
Reserved
(a) Microprocessor Mode
(b) Microcomputer/Bootloader Mode
Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
memory map (continued)
808000h
808004h
808006h
808008h
808020h
808024h
808028h
808030h
808034h
808038h
808040h
DMA Global Control
DMA Source Address
DMA Destination Address
DMA Transfer Counter
Timer 0 Global Control
Timer 0 Counter
Timer 0 Period Register
Timer 1 Global Control
Timer 1 Counter
Timer 1 Period Register
Serial Global Control
808042h
808043h
808044h
808045h
808046h
FSX/DX/CLKX Serial Port Control
FSR/DR/CLKR Serial Port Control
Serial R/X Timer Control
Serial R/X Timer Counter
Serial R/X Timer Period Register
808048h
80804Ch
808064h
Data-Transmit
Data-Receive
Primary-Bus Control
NOTE A: Shading denotes reserved address locations.
Figure 3. Peripheral Bus Memory-Mapped Registers
clock generator
The clock generator provides clocks to the VC33 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source. The PLL circuit
generates the device clock by multiplying the reference clock frequency by a x5 scale factor, allowing use of
a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once
synchronized, locks onto and tracks an input clock signal.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
PLL and clock oscillator control
The clock mode control pins are decoded into four operational modes as shown in Figure 4. These modes
control clock divide ratios, oscillator, and PLL power (see Table 2).
When an external clock input or crystal is connected, the opposite unused input is simply grounded. An XOR
gate then passes one of the two signal sources to the PLL stage. This allows the direct injection of a clock
reference into EXTCLK, or 1-20 MHz crystals and ceramic resonators with the oscillator circuit. The two clock
sources include:
D
D
A crystal oscillator circuit, where a crystal or ceramic resonator is connected across the XOUT and XIN pins
and EXTCLK is grounded.
An external clock input, where an external clock source is directly connected to the EXTCLK pin, and XOUT
is left unconnected and XIN is grounded.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. The PLL
is a simple x5 reference multiplier with bypass and power control.
The clock divider, under CPU control, reduces the clock reference by 1 (MAXSPEED), 1/16 (LOWPOWER), or
clock stop (IDLE2). Wake-up from the IDLE2 state is accomplished by a RESET or interrupt pin logic-low state.
A divide-by-two TMS320C31 equivalent mode of operation is also provided. In this case, the clock output
reference is further divided by two with clock synchronization being determined by the timing of RESET falling
relative to the present H1/H3 state.
Clock & Crystal OSC
PLL
Clock Divider
MAXSPEED/
LOWPOWER
EXTCLK
XOUT
IDLE2
M
U
X
XOR
X1, 1/16, Off
M
U
X
S1 RF
CPU CLOCK
X5 PLL
XIN
1/2
Oscillator Enable
PLL PWR and Bypass
CLKMD0
CLKMD1
SEL
C31 DIV2 Mode
Figure 4. Clock Generation
Table 2. Clock Mode Select Pins
CLKMD0
CLKMD1
FEEDBACK
PLLPWR
Off
RATIO
NOTES
0
0
1
1
0
1
0
1
Off
On
On
On
1
1/2
1
Fully static, very low power
Oscillator enabled
Off
Off
Oscillator enabled
On
5
2 mA @ 60 MHz, 1.8 V PLL power. Oscillator enabled
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
PLL and clock oscillator control (continued)
Typical crystals in the 8-30 MHz range have a series resistance of 25 Ω, which increases below 8 MHz. To
maintain proper filtering and phase relationships, R and Z of the oscillator circuit should be 10x-40x that of
d
out
the crystal. A series compensation resistor (Rd), shown in Figure 5, is recommended when using lower
frequency crystals. The XOUT output, the square wave inverse of XIN, is then filtered by the XOUT output
impedance, C1 load capacitor, and R (if present). The crystal and C2 input load capacitor then refilters this
d
signal, resulting in a XIN signal that is 75-85% of the oscillator supply voltage.
NOTE: Some ceramic resonators are available in a low-cost, three-terminal package that includes C1 and C2
internally. Typically, ceramic resonators do not provide the frequency accuracy of crystals.
NOTE: Better PLL stability can be achieved using the optional power supply isolation circuit shown in Figure 5.
A similar filter can be used to isolate the PLLVSS, as shown in Figure 6. PLLVDD can also be directly connected
to CVDD
.
Table 3. Typical Crystal Circuit Loading
†
†
FREQUENCY (MHz)
Rd (Ω)
4.7k
2.2k
470
0
C1 (pF)
C2 (pF)
CL (pF)
RL (Ω)
2
18
18
15
15
9
18
18
15
12
9
12
12
12
12
10
200
60
30
25
25
5
10
15
20
0
†
CL and RL are typical internal series load capacitance and resistance of the crystal.
XOUT
XIN
EXTCLK
PLLV
CV
PLLV
SS
DD
DD
Rd
C1
100 Ω
Crystal
C2
0.1 µF
0.01 µF
Figure 5. Self-Oscillation Mode
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
PLL isolation
The internal PLL supplies can be directly connected to CV and V (0 Ω case) or fully isolated as shown in
DD
SS
Figure 6. The RC network prevents the PLL supplies from turning high frequency noise in the CV and V
DD
SS
supplies into jitter.
CV
DD
0 -100 Ω
PLLV
PLLV
DD
SS
0.1 µF
0.01 µF
0 -100 Ω
V
SS
Figure 6. PLL Isolation Circuit Diagram
clock and PLL considerations on initialization
On power up, the CPU clock divide mode can be in MAXSPEED, LOPOWER or IDLE2, or the PLL could be
in an undefined mode. RESET falling in the presence of a valid CPU clock is used to clear this state, after which
the device will synchronously terminate any external activity.
The 5x Fclkin PLL of the 320VC33 contains an 8-bit PLL-LOCK counter that will cause the PLL to output a
frequency of Fclkin/2 during the initial ramp. This counter, however, does not increment while RESET is low or
in the absence of an input clock. A minimum of 256 input clocks are required before the first falling edge of reset
for the PLL to output to clear this counter. The setup and behavior that is seen is as follows.
Power is applied to the DSP with RESET low and the input clock high or low. A clock is applied (RESET is still
low) and the PLL appears to lock on to the input clock, producing the expected x5 output frequency. RESET
is driven high and the PLL output immediately drops to Fclkin/2 for up to 256 input cycles or 128 of the Fclkin/2
output cycles. The PLL/CPU clock then switches to x5 mode.
The switch over is synchronous and does not create a clock glitch, so the only effect is that the CPU will run
slow for up to the first 128 cycles after reset goes high. Once the PLL has stabilized, the counter will remain
cleared and subsequent resets will not exhibit this condition.
power sequencing considerations
Though an internal ESD and CMOS latchup protection diode exists between CV and DV , it should not be
DD
DD
considered a current-carrying device on power up. An external Schottky diode should be used to prevent CV
DD
from exceeding DV by more than 0.7 V. The effect of this diode during power up is that if CV is powered
DD
DD
up first, DV will follow by one diode drop even when the DV supply is not active.
DD
DD
Typical systems using LDOs of the same family type for both DV and CV will track each other during power
DD
DD
up. In most cases, this is acceptable; but if a high-impedance pin state is required on power up, the SHZ pin
can be used to asynchronously disable all outputs. RESET should not be used in this case since some signals
require an active clock for RESET to have an effect and the clock may not yet be active. The internal core logic
becomes functional at approximately 0.8 V while the external pin IO becomes active at about 1.5 V.
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
EDGEMODE
When EDGEMODE = 1, a sampled digital delay line is decoded to generate a pulse on the falling edge of the
interrupt pin. To ensure interrupt recognition, input signal logic-high and logic-low states must be held longer
than the synchronizer delay of one CPU clock cycle. Holding these inputs to no less than two cycles in both the
logic-low and logic-high states is sufficient.
When EDGEMODE = 0, a logic-low interrupt pin will continually set the corresponding interrupt flag. The CPU
or DMA can clear this flag within two cycles of it being set. This is the maximum interrupt width that can be applied
if only one interrupt is to be recognized. The CPU can manually clear IF bits within an interrupt service routine
(ISR), effectively lengthening the maximum ISR width.
After reset, EDGEMODE is temporarily disabled, allowing logic-low INT pins to be detected for bootload
operation.
Delay
RESET
EDGEMODE
S
R
INTn
D Q
D Q
D Q
D Q
D Q
Q
IF Bit
CPU Reset
CPU Set
H1
H3
Figure 7. EDGEMODE and Interrupt Flag CIrcuit
reset operation
When RESET is applied, the CPU attempts to safely exit any pending read or write operations that may be in
progress. This can take as much as 10 CPU cycles, after which, the address, data, and control pins will be in
an inactive or high-impedance state.
When both RESET and SHZ are applied, the device will immediately enter the reset state with the pins held in
high-impedance mode. SHZ should then be disabled at least 10 CPU cycles before RESET is set high. SHZ
can be used during power-up sequencing to prevent undefined address, data, and control pins, avoiding system
conflicts.
PAGE0 - PAGE3 select lines
To facilitate simpler and higher speed connection to external devices, the SM/SMJ320VC33 includes four
predecoded select pins that have the same timings as STRB. These pins are decoded from A22, A23, and STRB
and are active only during external accesses over the ranges shown in Table 4. All external bus accesses are
controlled by a single bus control register.
Table 4. PAGE0 - PAGE3 Ranges
START
END
PAGE0
PAGE1
PAGE2
PAGE3
0x000000
0x3FFFFF
0x400000
0x800000
0xC00000
0x7FFFFF
0xBFFFFF
0xFFFFFF
15
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
using external logic with the READY pin
The key to designing external wait-state logic is the internal bus control register and associated internal logic
that logically combines the external READY pin with the much faster on-chip bus control logic. This essentially
allows slow external logic to interact with the bus while easily meeting the READY input timings. It is also relevant
to mention that the combined ready signals are sampled on the rising edge of the internal H1 clock. Please refer
to Figure 8 for the following examples.
example 1
A simple 0 or WTCNT wait-state decoder can be created by simply tying an address line back to the READY
pin and selecting the AND option. When the tied back address is low, the bus will run with 0 wait states. When
the tied back address is high, the bus will be controlled by the internal wait-state counter.
By enabling the bank compare logic, proper operation is further ensured by inserting a null cycle before a read
on the next bank is performed (writes are not pre-extended). This extra time can also be used by external logic
to affect the feedback path.
example 2
An N-WTCNT minimum wait-state decoder can also be created by tying back an address line to READY and
logically ORing it with the internal bank compare and wait count signals. When the address pin is low, bus timing
is determined by the internal WTCNT and BNKCMP settings. When the address line is high, the bus can run
no faster than the WTCNT counter and will be extended as long as READY is held high.
PAGE_0
A23
A22
Device
Enable
Pins
PAGE_1
PAGE_2
PAGE_3
Decode
Bus_Enable_Strobe,
0 = Active
STRB Pin
0 = Bus Idle
To C31 Style
Decoder
(C31 Compatibility)
H3
Abus_old
Abus
D Q
R
H3
N-Bit
Bank
N_Wait
Compare
Counter
Q
D
1
BUS_READY
H1
2
3
0
READY Pin
R/W Pin
R/W
Figure 8. Internal Ready Logic, Simplified Diagram
16
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
example 2 (continued)
Table 5. MUX Select (Bus Control Register Bits 4 and 3)
BIT 4
BIT 3
RESULTS
0
0
1
1
0
1
0
1
Ignore internal wait counter and use only external READY
Use only internal wait counter and ignore ready pin
Logically AND internal wait counter with ready pin
Logically OR internal wait counter with ready pin (reset default)
posted writes
External writes are effectively “posted” to the bus, which then acts like an output latch until the write completes.
Therefore, if the application code is executing internally, it can perform a very slow external write with no penalty
since the bus acts like it has a one-level-deep write FIFO.
data bus I/O buffer
The circuit shown in Figure 9 is incorporated into each data pin to lightly “hold” the last driven value on the data
bus pins when the DSP or an external device is not actively driving the bus. Each bus keeper is built from a
three-state driver with nominal 15 kΩ output resistance which is fed back to the input in a positive feedback
configuration. The resistance isolated driver then pulls the output in one direction or the other keeping the last
driven value. This circuit is enabled in all functional modes and is only disabled when SHZ is pulled low.
R/W
30 Ω
External Data
Internal
Data Bus
Bus Pin
15 kΩ
SHZ
Bus keeper
Figure 9. Bus Keeper Circuit
For an external device to change the state of these pins, it must be able to drive a small dc current until the driver
threshold is crossed. At the crossover point, the driver changes state, agreeing with the external driver and
assisting the change. The voltage threshold of the bus keeper is approximately at 50% of the DV supply
DD
voltage. The typical output impedance of 30 Ω for all SM/SMJ320VC33 I/O pins is easily capable of meeting
this requirement.
17
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
bootloader operation
When MCBL/MP = 1, an internal ROM is decoded into the address range of 0x000000-0x000FFF. Therefore,
when reset occurs, execution begins within the internal ROM program and vector space. No external activity
will be evident until one of the boot options is enabled. These options are enabled by pulling an external interrupt
pin low, which the boot-load software then detects, causing a particular routine to be executed (see Table 6).
Table 6. INT0 - INT3 Sources
ADDRESS/SOURCE WHERE BOOT DATA IS
ACTIVE INTERRUPT
DATA FORMAT
READ FROM
INT0
INT1
INT2
INT3
0x001000
8, 16, or 32-bit width
8, 16, or 32-bit width
0x400000
0xFFF000
Serial Port
8, 16, or 32-bit width
32-bit, external clock, and frame synch
When MCBL/MP = 1, the reset and interrupt vectors are hard-coded within the internal ROM. Since this is a
read-only device, these vectors cannot be modified. To enable user-defined interrupt routines, the internal
vectors contain fixed values that point to an internal section of SRAM beginning at 0x809FC1. Code execution
begins at these locations so it is important to place branch instructions (to the interrupt routine) at these locations
and not vectors.
The bootloader program requires a small stack space for calls and returns. Two SRAM locations at 0x809800
and 0x809801 are used for this stack. Data should not be boot loaded into these locations as this will corrupt
the bootloader program run-time stack. After the boot-load operation is complete, a program can reclaim these
locations. The simplest solution is to begin a program stack or uninitialized data section at 0x809800.
For additional detail on bootloader operation including the bootloader source code, see the TMS320C3x User’s
Guide (literature number SPRU031).
A bit I/O line or external logic can be used to safely disable the MCBL mode after bootloading is complete.
However, to ensure proper operation, the CPU should not be currently executing code or using external data
as the change takes place. In the following example, the XF0 pin is 3-state on reset, which allows the pullup
resistor to place the DSP in MCBL mode. The following code, placed at the beginning of an application then
causes the XF0 pin to become an active-logic-low output, changing the DSP mode to MP. The cache-enable
and RPTS instructions are used since they cause the LDI instruction to be executed multiple times even though
it has been fetched only once (before the mode change). In other words, the RPTS instruction acts as a
one-level-deep program cache for externally executed code. If the application code is to be executed from
internal RAM, no special provisions are needed.
LDI
8000h,ST ; Enable the cache
RPTS
LDI
4
; RPTS will fetch the following opcode 1 time
2h, IOF
; Drive MCBL/MP=0 for several cycles allowing
; the pipeline to clear
RESET
RESET
SM/SMJ320VC33
DV
DD
R
PU
XF0
MCBL/MP
Figure 10. Changing Bootload Select Pin
18
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
JTAG emulation
Though the 320VC33 contains a JTAG debug port which allows multiple JTAG enabled chips to be
daisy-chained, boundary scan of the pins is not supported. If the pin scan path is selected, it will be routed
through a null register with a length of one. For additional information concerning the emulation interface, see
JTAG/MPSD Emulation Technical Reference (literature number SPDU079).
designing a target system emulator connector (14-pin header)
JTAG target devices support emulation through a dedicated emulation port. This port is a superset of the test
access port standard and is accessed by the emulator. To communicate with the emulator, the target system
must have a 14-pin header (two rows of seven pins) with the connections that are shown in Figure 11. Table 7
describes the emulation signals.
TMS
TDI
1
3
5
7
9
2
4
6
8
TRST
Header Dimensions:
GND
Pin-to-pin spacing, 0.100 in. (X,Y)
Pin width, 0.025-in. square post
Pin length, 0.235-in. nominal
PD (VCC
)
no pin (key)†
GND
TDO
TCK_RET
10 GND
12 GND
14 EMU1
TCK 11
EMU0 13
†
While the corresponding female position on the cable connector is plugged to prevent improper
connection, the cable lead for pin 6 is present in the cable and is grounded, as shown in the
schematics and wiring diagrams in this document.
Figure 11. 14-Pin Header Signals and Header Dimensions
Table 7. 14-Pin Header Signal Descriptions
†
†
EMULATOR
TARGET
STATE
SIGNAL
DESCRIPTION
STATE
‡
TMS
TDI
Test mode select
Test data input
Test data output
O
O
I
I
I
TDO
O
Test clock. TCK is a 10.368-MHz clock source from the emulation cable pod.
This signal can be used to drive the system test clock
TCK
O
I
§
TRST
Test reset
O
I
I
‡¶
‡¶
EMU0
EMU1
Emulation pin 0
I/O
I/O
Emulation pin 1
I
Presence detect. Indicates that the emulation cable is connected and that the
PD(V
)
I
I
O
O
CC
target is powered up. PD should be tied to V in the target system.
CC
Test clock return. Test clock input to the emulator. May be a buffered or unbuf-
fered version of TCK.
TCK_RET
GND
Ground
†
‡
§
I = input; O = output
Use 1-50K pullups for TMS, EMU0 and EMU1.
Use 1-50K pulldown for TRST. Do not use pullup resistors on TRST: it has an internal pulldown device. In a low-noise environment, TRST can
be left floating. In a high-noise environment, an additional pulldown resistor may be needed. (The size of this resistor should be based on electrical
current considerations.)
EMU0 and EMU1 are I/O drivers configured as open-drain (open-collector) drivers. They are used as bidirectional signals for emulation global
start and stop.
¶
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
designing a target system emulator connector (14-pin header) (continued)
Although other headers can be used, recommended parts include:
straight header, unshrouded
DuPont Connector Systems
part numbers:
65610-114
65611-114
67996-114
67997-114
JTAG emulator cable pod logic
Figure 12 shows a portion of the emulator cable pod. The functional features of the pod are as follows:
D
D
D
Signals TDO and TCK_RET can be parallel-terminated inside the pod if required by the application. By
default, these signals are not terminated.
Signal TCK is driven with a 74LVT240 device. Because of the high-current drive (32 mA I /I ), this signal
OL OH
can be parallel-terminated. If TCK is tied to TCK_RET, the parallel terminator in the pod can be used.
Signals TMS and TDI can be generated from the falling edge of TCK_RET, according to the bus slave device
timing rules.
D
D
Signals TMS and TDI are series-terminated to reduce signal reflections.
A 10.368-MHz test clock source is provided. Another test clock can be used for greater flexibility.
+5 V
74F175
180 Ω
270 Ω
Q
Q
JP1
D
TDO (Pin 7)
74LVT240
10.368 MHz
33 Ω
33 Ω
TMS (Pin 1)
Y
Y
GND (Pins 4,6,8,10,12)
Y
Y
A
TDI (Pin 3)
EMU0 (Pin 13)
EMU1 (Pin 14)
74AS1034
{
TCK (Pin 11)
+5 V
180 Ω
270 Ω
TRST (Pin 2)
74AS1004
RESIN
JP2
{
TCK_RET (Pin 9)
PD(V ) (Pin 5)
CC
100 Ω
TL7705A
†
The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system
test clock source.
Figure 12. JTAG Emulator Cable Pod Interface
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
device and development support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP family devices and support tools. Each TMS320 DSP member has one of three prefixes: TMX,
TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This development flow
is defined below.
Device development evolutionary flow:
SMX
Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
SM/SMJ
Fully-qualified production device
Support tool development evolutionary flow:
TMDX
Development support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development support product
TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development support tools have been characterized fully, and the quality and reliability
of the device has been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, HFG, GNM, or GNL) and temperature range (for example, M). Figure 13 provides a legend for
reading the complete device name for any TMS320 DSP family member.
TMS320 is a trademark of Texas Instruments.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
device and development support tool nomenclature (continued)
SMJ 320 VC 33 GNM
M
150
PREFIX
SMX = experimental device
TMP = prototype device
TMS = qualified device
SPEED
150 = 150 MFLOPS
SMJ = MIL-PRF-38535 (QML)
SMQ= QML Plastic device
SM
= Commericial processing
TEMPERATURE RANGE
DEVICE FAMILY
320 = TMS320 Family
M
= Military
†
TECHNOLOGY
PACKAGE TYPE
HFG = 164-pin ceramic QFP
GNL = 144-pin ceramic BGA, hermetic
GNM= 144-pin ceramic BGA, non-hermetic
C = CMOS
E
F
=
=
CMOS EPROM
CMOS Flash EEPROM
LC = Low-Voltage CMOS (3.3 V)
VC= Low-Voltage CMOS [3 V (2.5 V
or 1.8 V core)]
UC= Ultra Low-Voltage CMOS [1.8 V
(1.5 V core)]
DEVICE
3x DSP:
30
31
32
33
4x DSP:
40
44
6x DSP:
6201 6201
6701 6211
†
QFP = Quad Flat Package
LQFP = Low-Profile Quad Flat Package
BGA = Ball Grid Array
Figure 13. TMS320 DSP Device Nomenclature
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
absolute maximum ratings over specified temperature range (unless otherwise noted)†
‡
Supply voltage range, DV
Supply voltage range, CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 2.4 V
DD
‡
DD
Input voltage range, V § . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 V to 4.6 V
I
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V
O
Continuous power dissipation (worst case)¶ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 °C to 125°C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
§
All voltage values are with respect to V
.
SS
Absolute dc input level should not exceed the DV or V supply rails by more than 0.3 V. An instantaneous low current pulse of < 2 ns,
DD
SS
< 10 mA, and < 1 V amplitude is permissable.
Actual operating power is much lower. This value was obtained under specially produced worst-case test conditions for the SM/SMJ320VC33,
which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to the
¶
external data and address buses at the maximum possible rate with a capacitive load of 30 pF. See normal (I ) current specification in the
CC
electrical characteristics table and also read TMS320C3x General-Purpose Applications (literature number SPRU194).
recommended operating conditions‡#||
MIN
1.71
3.14
NOM
1.8
MAX
1.89
3.46
UNIT
V
k
CV
DV
Supply voltage for the core CPU
Supply voltage for the I/O pinsh
Supply ground
DD
DD
3.3
0
V
V
V
V
V
SS
§
High-level input voltage
Low-level input voltage
0.7 x DV
DV + 0.3
V
IH
IL
DD
DD
§
-0.3
0.3 x DV
V
DD
I
I
High-level output current
Low-level output current
Operating case temperature
Capacitive load per output pin
4
4
mA
mA
°C
pF
OH
OL
T
-55
125
30
C
C
L
‡
§
All voltage values are with respect to V
Absolute dc input level should not exceed the DV or V supply rails by more than 0.3 V. An instantaneous low current pulse of < 2 ns, < 10 mA,
.
SS
DD
SS
and < 1 V amplitude is permissable.
All inputs and I/O pins are configured as inputs.
All input and I/O pins use a Schmidt hysteresis inputs except SHZ and D0-D31. Hysteresis is approximately 10% of DV and is centered at
#
||
DD
0.5 x DV
.
DD
kCV should not exceed DV by more than 0.7 V. (Use a Schottky clamp diode between these supplies.)
DD
DD
hDV should not exceed CV by more than 2.5 V.
DD
DD
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)†
‡
§
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN TYP
MAX UNIT
V
V
DV = MIN,
I
I
= MAX
= MAX
2.4
V
OH
OL
DD
OH
OL
Low-level output voltage
DV = MIN,
0.4
+5
V
DD
I
I
I
I
I
I
High-impedance current
T
T
= 25°C, DV = MAX
-5
-5
µA
µA
µA
µA
µA
µA
Z
C
C
DD
Input current
= 25°C, V = V to DV
+5
I
I
SS
DD
¶
Input current (with internal pullup)
Input current (with internal pulldown)
Input current (with bus keeper) pullup
Inputs with internal pullups
-600
600
-600
600
10
IPU
IPD
BKU
BKD
¶
Inputs with internal pulldowns
-10
10
#
Bus keeper opposes until conditions match
#
Input current (with bus keeper) pulldown
-10
T
= 25°C, f = 75 MHz
x
C
||
I
I
Supply current, pins k
25
60
260
215
mA
DDD
DDC
DV = MAX
DD
T
= 25°C, f = 75 MHz
x
C
||
Supply current, core CPU k
mA
mA
CV = MAX
DD
PLL enabled, oscillator enabled
PLL disabled, oscillator enabled
PLL disabled, oscillator disabled, FCLK = 0
All inputs except XIN
2
500
50
I
IDLE2, Supply current, I
plus I
DDD DDC
DD
µA
10*
10*
10*
C
C
Input capacitance
Output capacitance
pF
pF
i
XIN
o
* Not production tested
†
All voltage values are with respect to V
.
SS
‡
§
¶
#
||
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
For VC33, all typical values are at DV = 3.3, CV = 1.8 V, T (case temperature) = 25°C.
Pins with internal pullup devices: TDI, TCK, and TMS. Pin with internal pulldown device: TRST.
Pins D0-D31 include internal bus keepers that maintain valid logic levels when the bus is not driven (see Figure 9).
Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which
are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern at the
maximum rate possible. See TMS320C3x General-Purpose Applications (literature number SPRU194).
DD
DD
C
kf is the PLL output clock frequency.
x
PARAMETER MEASUREMENT INFORMATION
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
= 4 mA (all outputs) for dc levels test.
and I are adjusted during ac timing analysis to achieve an ac termination of 50 Ω
OL
O
OH
V
= DV /2
LOAD
DD
C
T
= 40-pF typical load-circuit capacitance
Figure 14. Test Load Circuit
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows, unless
otherwise noted:
Lowercase subscripts and their meanings
Letters and symbols and their meanings
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High Impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
x
pulse duration (width)
unknown, changing, or don’t care level
Additional symbols and their meaning
A
Address lines (A23- A0)
H
H1 and H3
HOLD
Asynchronous reset signals (XF0, XF1, CLKX0, DX0,
FSX0, CLKR0, DR0, FSR0, TCLK0, and TCLK1)
ASYNCH
HOLD
CLKX
CLKR
CONTROL
D
CLKX0
HOLDA
IACK
INT
HOLDA
IACK
CLKR0
Control signals
INT3- INT0
PAGE0- PAGE3
RDY
Data lines (D31- D0)
PAGE
RDY
RW
DR
DR
DX
DX
R/W
EXTCLK
FS
EXTCLK
RW
R/W
FSX/R
RESET
S
RESET
STRB
FSX
FSX0
FSR
FSR0
SCK
SHZ
CLKX/R
SHZ
GPI
General-purpose input
General-purpose input/output; peripheral pin (CLKX0,
CLKR0, DX0, DR0, FSX0, FSR0, TCLK0, and TCLK1)
GPIO
TCLK
TCLK0, TCLK1, or TCLKx
GPO
H1
General-purpose output
XF
XF0, XF1, or XFx
H1
H3
XF0
XF1
XIN
XF0
XF1
XIN
H3
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
phase-locked loop (PLL) circuit timing
phase-locked loop characteristics using EXTCLK or on-chip crystal oscillator†
PARAMETER
MIN
5*
MAX
15*
75*
2*
UNIT
MHz
MHz
mA
F
F
Frequency range, PLL input
Frequency range, PLL output
pllin
25*
pllout
I
PLL current, CV supply
DD
pll
P
PLL power, CV supply
5*
mW
%
pll
DD
PLL
PLL output duty cycle at H1
45*
55*
400*
1000
dc
PLLJ
PLL
PLL output jitter, F
= 25 MHz
ps
pllout
PLL lock time in input cycles
cycles
LOCK
* Not production tested
†
Duty cycle is defined as 100*t /(t +t )%
1
1
2
To ensure clean internal clock references, the minimal low and high pulse durations must be maintained. At high
frequencies, this may require a fast rise and fall time as well as a tightly controlled duty cycle. At lower
frequencies, these requirements are less restrictive when in x1 and x0.5 modes. The PLL, however, must have
an input duty cycle of between 40% and 60% for proper operation.
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
clock circuit timing
The following table defines the timing parameters for the clock circuit signals.
circuit parameters for on-chip crystal oscillator† (see Figure 15)
PARAMETER
MIN
TYP
CV
MAX
UNIT
V
V
Oscillator internal supply voltage
Fundamental mode frequency range
DC bias point (input threshold)
Feedback resistance
O
DD
F
1*
20*
60*
MHz
O
V
40*
50
%V
O
bias
R
R
100*
250*
300
500
85
500*
1000*
kΩ
fbk
Small signal ac output impedance
The ac output voltage with test crystal
Ω
out
‡
V
V
V
V
V
V
V
%V
%V
V
xoutac
xinac
xoutl
xouth
inl
O
O
‡
The ac input voltage with test crystal
85
V
V
= V , I
= 0, F =0 (logic input)
V
- 0.1*
V
+ 0.3*
SS
xin
xin
xinh xout
O
SS
= V , I
= 0, F =0 (logic input)
CV
- 0.3*
CV + 0.1*
V
xinl xout
O
DD
DD
When used for logic level input, oscillator enabled
When used for logic level input, oscillator enabled
When used for logic level input, oscillator disabled
XOUT internal load capacitance
-0.3*
0.8 x V *
0.2 x V *
V
O
DV + 0.3*
V
inh
O
DD
0.7 x DV
DV + 0.3
V
xinh
DD
DD
C
C
2*
2*
2
3
3
5*
5*
pF
pF
ns
xout
XIN internal load capacitance
xin
t
I
I
Delay time, XIN to H1 x1 and x0.5 modes
5.5
8
d(XIN-H1)
inl
Input current, feedback enabled, V = 0
50*
-50*
µA
µA
il
Input current, feedback enabled, V = V
ih
inh
il
* Not production tested
†
This circuit is intended for series resonant fundamental mode operation.
Signal amplitude is dependent on the crystal and load used.
‡
XOUT
Rd
R
OUT
C
XOUT
C
1
R
fbk
Crystal
V
O
XIN
To internal
clock generator
C
XIN
C
2
NOTE A: See Table 3 for value of Rd.
Figure 15. On-Chip Oscillator Circuit
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
clock circuit timing (continued)
The following tables define the timing requirements and switching characteristics for EXTCLK.
timing requirements for EXTCLK, all modes (see Figure 16 and Figure 17)
MIN
MAX
1*
UNIT
F = F
F < F
F = F
F < F
, x0.5 and x1 modes
max
max
max
max
t
t
Rise time, EXTCLK
Fall time, EXTCLK
ns
r(EXTCLK)
f(EXTCLK)
4*
, x0.5 and x1 modes
1*
ns
ns
4*
x5 mode
x1 mode
21*
6*
t
t
t
t
Pulse duration, EXTCLK low
Pulse duration, EXTCLK high
w(EXTCLKL)
w(EXTCLKH)
dc(EXTCLK)
c(EXTCLK)
x0.5 mode
4*
x5 mode
21*
5*
x1 mode
ns
%
x0.5 mode
4*
x5 PLL mode
x1 and x0.5 modes, F = max
x1 and x0.5 modes, F = 0 Hz
x5 mode
40*
45
60*
55
Duty cycle, EXTCLK [t
Cycle time, EXTCLK
/ t
w(EXTCLKH) c(H)]
0*
100*
200*
66.7*
13.3
10*
5*
x1 mode
ns
x0.5 mode
x5 mode
15*
75
x1 mode
0
F
Frequency range, 1/t
MHz
ext
c(EXTCLK)
x0.5 mode
0*
100*
* Not production tested
switching characteristics for EXTCLK over recommended operating conditions, all modes
(see Figure 16 and Figure 17)
PARAMETER
MIN
TYP
0.5 x DV
4.5
MAX
UNIT
V
Mid-level, used to measure duty cycle
V
mid
DD
x1 mode
x0.5 mode
2*
2*
7*
7*
3*
3*
2*
Delay time, EXTCLK to H1 and
H3
t
ns
d(EXTCLK-H)
4.5
t
t
t
Rise time, H1 and H3
Fall time, H1 and H3
ns
ns
ns
r(H)
f(H)
Delay time, from H1 low to H3 high or from H3 low to H1 high
x5 PLL mode
-1.5*
d(HL-HH)
1/(5 x fext)
1/fext
x1 mode
t
Cycle time, H1 and H3
ns
c(H)
x0.5 mode
2/fext
* Not production tested
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
clock circuit timing (continued)
t
t
c(EXTCLK)
r(EXTCLK)
t
w(EXTCLKH)
EXTCLK
t
w(EXTCLKL)
f(EXTCLK)
t
t
c(H)
H3
H1
t
d(EXTCLK-H)
t
f(H)
t
d(EXTCLK-H)
t
r(H)
Figure 16. Divide-By-Two Mode
t
c(EXTCLK)
t
r(EXTCLK)
t
f(EXTCLK)
t
w(EXTCLKH)
EXTCLK
t
w(EXTCLKL)
t
d(EXTCLK-H)
t
d(EXTCLK-H)
H3
H1
t
c(H)
t
d(HL-HH)
NOTE A: EXTCLK is held low.
Figure 17. Divide-By-One Mode
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
memory read/write timing
The following tables define memory read/write timing parameters for STRB.
timing requirements for memory read/write† (see Figure 18, Figure 19, and Figure 20)
MIN
5*
MAX
UNIT
ns
t
t
t
t
t
Setup time, Data before H1 low (read)
Hold time, Data after H1 low (read)
Setup time, RDY before H1 high
Hold time, RDY after H1 high
su(D-H1L)R
h(H1L-D)R
su(RDY-H1H)
h(H1H-RDY)
d(A-RDY)
-1*
5
ns
ns
-1*
ns
‡
Delay time, Address valid to RDY
P - 6*
ns
0 wait state, C = 30 pF
6*
ns
L
t
Valid time, Data valid after address PAGEx, or STRB valid
v(A-D)
1 wait state
t
+ 6*
ns
c(H)
* Not production tested
†
These timings assume a similar loading of 30 pF on all pins.
‡
P = t
/2 (when duty cycle equals 50%).
c(H)
switching characteristics over recommended operating conditions for memory read/write†
(see Figure 18, Figure 19, and Figure 20)
PARAMETER
Delay time, H1 low to STRB low
MIN
-1*
MAX
UNIT
ns
t
t
t
t
t
t
t
t
3
3
d(H1L-SL)
Delay time, H1 low to STRB high
-1*
-1*
-1*
-1*
-1*
ns
d(H1L-SH)
Delay time, H1 high to R/W low (write)
Delay time, H1 low to address valid
3
ns
d(H1H-RWL)W
d(H1L-A)
3
ns
Delay time, H1 high to R/W high (write)
Delay time, H1 high to address valid on back-to-back write cycles (write)
Valid time, Data after H1 low (write)
3
ns
d(H1H-RWH)W
d(H1H-A)W
v(H1L-D)W
h(H1H-D)W
3*
5
ns
ns
Hold time, Data after H1 high (write)
0*
5
ns
* Not production tested
†
These timings assume a similar loading of 30 pF on all pins.
Output load characteristics for high-speed and low-speed (low-noise) output buffers are shown in Figure 18.
High-speed buffers are used on A0 - A23, PAGE0 - PAGE3, H1, H3, STRB, and R/W. All other outputs use the
low-speed, (low-noise) output buffer.
LOW
SPEED NOISE
HIGH
LOAD
0 pF
Low-Noise Buffer
0.05 ns/pF
5
4
2.0
2.8
15 pF
30 pF
50 pF
2.6
3.2
4.0
3.4
4.4
High-Speed Buffer
0.04 ns/pF
3
2
5.25
C
Lmax
= 30 pF
Output Delay (ns)
1
10
20
30
40
50
Load Capacitance (pF)
Figure 18. Output Load Characteristics, Buffer Only
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
memory read/write timing (continued)
H3
H1
t
d(H1L-SL)
t
d(H1L-SH)
PAGEx, STRB
R/W
t
d(H1L-A)
t
v(A-D)
t
d(H1H-RWL)W
A[23:0]
D[31:0]
t
su(D-H1L)R
t
t
t
h(H1L-D)R
d(A-RDY)
su(RDY-H1H)
t
h(H1H-RDY)
RDY
NOTE A: STRB remains low during back-to-back read operations.
Figure 19. Timing for Memory (STRB = 0 and PAGEx = 0) Read
H3
H1
t
d(H1L-SH)
t
d(H1L-SL)
PAGEx, STRB
R/W
t
t
d(H1H-RWL)W
d(H1H-RWH)W
t
d(H1L-A)
t
d(H1H-A)W
A[23:0]
D[31:0]
RDY
t
t
h(H1H-D)W
v(H1L-D)W
t
h(H1H-RDY)
t
su(RDY-H1H)
Figure 20. Timing for Memory (STRB = 0 and PAGEx = 0) Write
31
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
XF0 and XF1 timing when executing LDFI or LDII
The following tables define the timing parameters for XF0 and XF1 during execution of LDFI or LDII.
timing requirements for XF0 and XF1 when executing LDFI or LDII (see Figure 21)
MIN MAX
UNIT
ns
t
t
Setup time, XF1 before H1 low
Hold time, XF1 after H1 low
4*
0*
su(XF1-H1L)
h(H1L-XF1)
ns
* Not production tested
switching characteristics over recommended operating conditions for XF0 and XF1 when executing
LDFI or LDII (see Figure 21)
PARAMETER
MIN MAX
UNIT
t
Delay time, H3 high to XF0 low
3
ns
d(H3H-XF0L)
Fetch
LDFI or LDII
Decode
Read
Execute
H3
H1
PAGEx, STRB
R/W
A[23:0]
D[31:0]
RDY
t
d(H3H-XF0L)
XF0
XF1
t
su(XF1-H1L)
t
h(H1L-XF1)
Figure 21. Timing for XF0 and XF1 When Executing LDFI or LDII
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
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†
XF0 timing when executing STFI and STII
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.
switching characteristics over recommended operating conditions for XF0 when executing STFI
or STII (see Figure 22)
PARAMETER
MIN MAX
UNIT
†
t
Delay time, H3 high to XF0 high
3
ns
d(H3H-XF0H)
†
XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
Fetch
STFI or STII
Decode
Read
Execute
H3
H1
PAGEx, STRB
R/W
A[23:0]
D[31:0]
RDY
t
d(H3H-XF0H)
XF0
Figure 22. Timing for XF0 When Executing an STFI or STII
33
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DIGITAL SIGNAL PROCESSOR
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XF0 and XF1 timing when executing SIGI
The following tables define the timing parameters for the XF0 and XF1 pins during execution of SIGI.
timing requirements for XF0 and XF1 when executing SIGI (see Figure 23)
MIN MAX
UNIT
ns
t
t
Setup time, XF1 before H1 low
Hold time, XF1 after H1 low
4*
0*
su(XF1-H1L)
h(H1L-XF1)
ns
* Not production tested
switching characteristics over recommended operating conditions for XF0 and XF1 when executing
SIGI (see Figure 23)
PARAMETER
MIN MAX
UNIT
ns
t
t
Delay time, H3 high to XF0 low
Delay time, H3 high to XF0 high
3
3
d(H3H-XF0L)
d(H3H-XF0H)
ns
Fetch
SIGI
Decode
Read
Execute
H3
H1
t
t
t
su(XF1-H1L)
d(H3H-XF0L)
d(H3H-XF0H)
XF0
XF1
t
h(H1L-XF1)
Figure 23. Timing for XF0 and XF1 When Executing SIGI
34
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DIGITAL SIGNAL PROCESSOR
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loading when XF is configured as an output
The following table defines the timing parameter for loading the XF register when the XFx pin is configured as
an output.
switching characteristics over recommended operating conditions for loading the XF register when
configured as an output pin (see Figure 24)
PARAMETER
MIN MAX
UNIT
t
Valid time, XFx after H3 high
3
ns
v(H3H-XF)
Fetch Load
Instruction
Decode
Read
Execute
H3
H1
OUTXFx Bit
(see Note A)
1 or 0
t
v(H3H-XF)
XFx
NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register.
Figure 24. Timing for Loading XF Register When Configured as an Output Pin
35
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DIGITAL SIGNAL PROCESSOR
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changing XFx from an output to an input
The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin.
timing requirements for changing XFx from output to input mode (see Figure 25)
MIN
4
MAX
UNIT
ns
t
t
Setup time, XFx before H1 low
Hold time, XFx after H1 low
su(XF-H1L)
h(H1L-XF)
0
ns
switching characteristics over recommended operating conditions for changing XFx from output to
input mode (see Figure 25)
PARAMETER
MIN
MAX
UNIT
t
Disable time, XFx after H3 high
5*
ns
dis(H3H-XF)
* Not production tested
Buffers Go
From Output
to Output
Execute
Load of IOF
Synchronizer
Delay
Value on Pin
Seen in IOF
H3
H1
t
su(XF-H1L)
I/OxFx Bit
t
(see Note A)
h(H1L-XF)
t
dis(H3H-XF)
XFx
Output
Data
Sampled
INXFx Bit
(see Note A)
Data
Seen
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.
Figure 25. Timing for Changing XFx From Output to Input Mode
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
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changing XFx from an input to an output
The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.
switching characteristics over recommended operating conditions for changing XFx from input to
output mode (see Figure 26)
PARAMETER
MIN MAX
UNIT
t
Delay time, H3 high to XFx switching from input to output
3
ns
d(H3H-XF)
Execution of
Load of IOF
H3
H1
I/OxFx Bit
(see Note A)
t
d(H3H-XF)
XFx
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register.
Figure 26. Timing for Changing XFx From Input to Output Mode
37
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DIGITAL SIGNAL PROCESSOR
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reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is
possible.
The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
Resetting the device initializes the bus control register to seven software wait states and therefore results in slow
external accesses until these registers are initialized.
HOLD is a synchronous input that can be asserted during reset. It can take nine CPU cycles before HOLDA
is granted.
The following table defines the timing parameters for the RESET signal. The numbers shown in Figure 27
correspond with those in the NO. column of the following table.
timing requirements for RESET (see Figure 27)
MIN
5*
MAX
UNIT
ns
*†
t
t
Setup time, RESET before EXTCLK low
P - 7
su(RESET-EXTCLKL)
su(RESETH-H1L)
Setup time, RESET high before H1 low and after ten H1 clock cycles
5
ns
* Not production tested
†
P = t
c(EXTCLK)
switching characteristics over recommended operating conditions for RESET (see Figure 27)
PARAMETER
Delay time, EXTCLK high to H1 high
Delay time, EXTCLK high to H1 low
Delay time, EXTCLK high to H3 low
Delay time, EXTCLK high to H3 high
Disable time, Data (high impedance) from H1 high
MIN* MAX*
UNIT
ns
t
t
t
t
t
t
t
t
t
2
2
2
2
7
7
7
7
6
6
3
3
3
d(EXTCLKH-H1H)
d(EXTCLKH-H1L)
d(EXTCLKH-H3L)
d(EXTCLKH-H3H)
dis(H1H-DZ)
ns
ns
ns
‡
ns
Disable time, Address (high impedance) from H3 high
Delay time, H3 high to control signals high
ns
dis(H3H-AZ)
ns
d(H3H-CONTROLH)
d(H1H-RWH)
Delay time, H1 high to R/W high
ns
Delay time, H1 high to IACK high
ns
d(H1H-IACKH)
Disable time, Asynchronous reset signals disabled (high impedance) from RESET
low
t
6
ns
dis(RESETL-ASYNCH)
§
* Not production tested
‡
High impedance for Dbus is limited to nominal bus keeper Z
Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
= 15 kΩ.
OUT
§
38
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
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reset timing (continued)
EXTCLK
t
su(RESET-EXTCLKL)
RESET
(see Notes A and C)
t
d(EXTCLKH-H1H)
t
t
d(EXTCLKH-H1L)
su(RESETH-H1L)
H1
t
d(EXTCLKH-H3L)
H3
Ten H1 Clock Cycles
t
dis(H1H-DZ)
D[31:0]
t
t
d(EXTCLKH-H3H)
dis(H3H-AZ)
PAGEx, A[23:0]
STRB
t
d(H3H-CONTROLH)
t
d(H1H-RWH)
R/W
t
d(H1H-IACKH)
IACK
t
Asynchronous
Reset Signals
(see Note B)
dis(RESETL-ASYNCH)
NOTES: A. Clock circuit is configured in C31-compatible divide-by-2 mode. If configured for x1 mode, EXTCLK directly drives H3.
B. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
C. RESET is a synchronous input that can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.
D. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the
reset vector is fetched twice, with no software wait states.
E. The address and PAGE3-PAGE0 outputs are placed in a high-impedance state during reset requiring a nominal 10-22 kΩ pullup.
If not, undesirable spurious reads can occur when these outputs are not driven.
Figure 27. RESET Timing
39
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DIGITAL SIGNAL PROCESSOR
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interrupt response timing
The following table defines the timing parameters for the INTx signals.
timing requirements for INT3-INT0 response (see Figure 28)
MIN
4*
NOM
MAX
UNIT
ns
t
t
t
Setup time, INT3- INT0 before H1 low
Hold time, INT3- INT0 after H1 low
su(INT-H1L)
h(H1L-INT)
w(INT)
0
ns
†
†
Pulse duration, interrupt to ensure only one interrupt
P + 5*
1.5P
2P - 5*
ns
* Not production tested
†
P = t
c(H)
The interrupt (INTx) pins are synchronized inputs that can be asserted at any time during a clock cycle. The
TMS320C3x interrupts are selectable as level- or edge-sensitive. Interrupts are detected on the falling edge of
H1. Therefore, interrupts must be set up and held to the falling edge of the internal H1 for proper detection. The
CPU and DMA respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt when level mode is selected, an interrupt pulse must be set
up and held such that a logic-low condition occurs for:
D
D
D
A minimum of one H1 falling edge
No more than two H1 falling edges
Interrupt sources whose edges cannot be specified to meet the H1 falling edge setup and hold times must
be further restriced in pulse width as defined by t
(parameter 51) in the table above.
w(INT)
When EDGEMODE=1, the falling edge of the INT0-INT3 pins are detected using synchronous logic (see
Figure 7). The pulse low and high time should be two CPU clocks or greater.
The TMS320C3x can set the interrupt flag from the same source as quickly as two H1 clock cycles after it has
been cleared.
If the specified timings are met, the exact sequence shown in Figure 28 occurs; otherwise, an additional delay
of one clock cycle is possible.
40
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DIGITAL SIGNAL PROCESSOR
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interrupt response timing (continued)
Fetch First
Instruction of
Service
Reset or
Interrupt
Vector Read
Routine
H3
H1
‡
t
su(INT-H1L)
t
h(H1L-INT)
†
¶
t
su(INT-H1L)
t
su(INT-H1L)
INT3 - INT0 Pin
(EDGEMODE = 0)
§
t
w(INT)
INT3 - INT0 Pin
(EDGEMODE = 1)
INT3 - INT0
Flag
ADDR
Data
Vector Address
First Instruction Address
†
‡
§
¶
Falling edge of H1 just detects INTx falling edge.
Falling edge of H1 detects second INTx low, however flag clear takes precedence.
Nominal width.
Falling edge of H1 misses previous INTx low as INTx rises.
Figure 28. INT3-INT0 Response Timing
41
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DIGITAL SIGNAL PROCESSOR
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interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal. The numbers shown in Figure 29
correspond with those in the NO. column of the table below.
NOTE: The IACK instruction can be executed at anytime to signal an event. It is most often used within an
interrupt routine to signal which interrupt has occurred.
switching characteristics over recommended operating conditions for IACK (see Figure 29)
PARAMETER
Delay time, H1 high to IACK low
Delay time, H1 high to IACK high
MIN MAX
UNIT
ns
t
t
-1*
-1*
3
3
d(H1H-IACKL)
d(H1H-IACKH)
ns
* Not production tested
Decode IACK
Instruction
IACK Data
Read
Fetch IACK
Instruction
H3
H1
t
d(H1H-IACKL)
t
d(H1H-IACKH)
IACK
ADDR
Data
Figure 29. Interrupt Acknowledge (IACK) Timing
42
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DIGITAL SIGNAL PROCESSOR
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serial-port timing parameters
The following tables define the timing parameters for the serial port.
timing requirements (see Figure 30 and Figure 31)
MIN
MAX
UNIT
CLKX/R ext
t
x 2.6*
c(H)
t
t
Cycle time, CLKX/R
ns
c(SCK)
w(SCK)
†
16
CLKX/R int
CLKX/R ext
CLKX/R int
t
x 4*
t
x 2 *
c(H)
c(H)
t
+ 5
c(H)
Pulse duration, CLKX/R high/low
ns
[t
/2] - 4*
[t
/2] + 4*
c(SCK)
c(SCK)
t
t
Rise time, CLKX/R
Fall time, CLKX/R
3*
3*
ns
ns
r(SCK)
f(SCK)
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKX/R ext
CLKX/R int
CLKX ext
CLKX int
4*
t
t
t
t
t
Setup time, DR before CLKR low
Hold time, DR after CLKR low
ns
ns
ns
ns
ns
su(DR-CLKRL)
h(CLKRL-DR)
su(FSR-CLKRL)
h(SCKL-FS)
5*
3*
0*
4*
5*
3*
0*
Setup time, FSR before CLKR low
Hold time, FSX/R input after CLKX/R low
Setup time, external FSX before CLKX
-[t
- 6]
[t
/2] - 6*
c(SCK)
c(H)
su(FSX-CLKX)
-[t
- 10]*
t
/2*
c(SCK)
c(H)
* Not production tested
†
A cycle time of t
*2 is possible when the device is operated at lower CPU frequencies. See the TMS320VC33 Silicon Update (literature number
c(H)
SPRZ176) for further details.
switching characteristics over recommended operating conditions (see Figure 30 and Figure 31)
PARAMETER
MIN
MAX
4*
6
UNIT
t
t
Delay time, H1 high to internal CLKX/R
ns
d(H1H-SCK)
d(CLKX-DX)
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
Delay time, CLKX to DX valid
ns
ns
ns
5*
5
t
t
Delay time, CLKX to internal FSX high/low
d(CLKX-FSX)
d(CLKX-DX)V
4*
4
Delay time, CLKX to first DX bit, FSX precedes CLKX
high
5*
6
t
t
Delay time, FSX to first DX bit, CLKX precedes FSX
ns
ns
d(FSX-DX)V
Disable time, DX high impedance following last data bit from CLKX high
6
dis(CLKX-DXZ)
* Not production tested
43
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DIGITAL SIGNAL PROCESSOR
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data-rate timing modes
Unless otherwise indicated, the data-rate timings shown in Figure 30 and Figure 31 are valid for all serial-port
modes, including handshake. For a functional description of serial-port operation, see the TMS320C3x User’s
Guide (literature number SPRU031).
The serial-port timing parameters are defined in the preceding “serial-port timing parameters” tables. The
numbers shown in Figure 30 and Figure 31 correspond with those in the NO. column of each table.
t
c(SCK)
t
d(H1H-SCK)
H1
t
d(H1H-SCK)
t
w(SCK)
t
w(SCK)
CLKX/R
t
f(SCK)
t
t
d(CLKX- DX)
r(SCK)
t
d(CLKX- DX)V
t
t
dis(CLKX- DXZ)
h(CLKRL- DR)
Bit n-1
Bit n-2
Bit 0
DX
DR
t
su(DR- CLKRL)
Bit n-1
Bit n-2
FSR
t
su(FSR- CLKRL)
t
d(CLKX- FSX)
t
d(CLKX- FSX)
FSX(INT)
t
h(SCKL- FS)
FSX(EXT)
t
t
h(SCKL- FS)
su(FSX- CLKX)
NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
Figure 30. Fixed Data-Rate Mode Timing
CLKX/R
t
d(CLKX- FSX)
FSX(INT)
t
d(FSX- DX)V
t
su(FSX- CLKX)
FSX(EXT)
t
d(CLKX- DX)
t
dis(CLKX-DXZ)
t
d(CLKX-DX)V
Bit n-1
Bit n-2
Bit n-3
Bit 0
DX
t
h(SCKL-FS)
FSR
t
su(FSR-CLKRL)
Bit n-1
Bit n-2
Bit n-3
DR
t
su(DR- CLKRL)
t
h(CLKRL-DR)
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed
data-rate mode.
Figure 31. Variable Data-Rate Mode Timing
44
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HOLD timing
HOLD is a synchronous input that can be asserted at any time during a clock cycle. If the specified timings are
met, the exact sequence shown in Figure 32 and Figure 33 occurs; otherwise, an additional delay of one clock
cycle is possible.
The table, “timing parameters for HOLD/HOLDA”, defines the timing parameters for the HOLD and HOLDA
signals. The numbers shown in Figure 32 and Figure 33 correspond with those in the NO. column of the table.
The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device
comes out of hold and prevents future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus
allowing the processor to continue (internally) until a second external write is encountered.
Figure 32, Figure 33, and the accompaning timings are for a zero wait-state bus configuration. Since HOLD is
internally captured by the CPU on the H1 falling edge one cycle before the present cycle is terminated, the
minimum HOLD width for any bus configuration is, therefore, WTCNT+3. Also, HOLD should not be deasserted
before HOLDA has been active for at least one cycle.
timing requirements for HOLD/HOLDA (see Figure 32 and Figure 33)
MIN
MAX UNIT
t
t
Setup time, HOLD before H1 low
Pulse duration, HOLD low
3
ns
ns
su(HOLD-H1L)
w(HOLD)
3t
*
c(H)
*Not production tested.
switching characteristics over recommended operating conditions for HOLD/HOLDA
(see Figure 32 and Figure 33)
PARAMETER
Valid time, HOLDA after H1 low
MIN
MAX UNIT
t
t
t
t
t
t
t
t
t
t
-1*
3*
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
v(H1L-HOLDA)
w(HOLDA)
d(H1L-SH)H
dis(H1L-S)
en(H1L-S)
Pulse duration, HOLDA low
2t
- 4*
c(H)
Delay time, H1 low to STRB high for a HOLD
-1
3
4
Disable time, STRB to the high-impedance state from H1 low
Enable time, STRB enabled (active) from H1 low
Disable time, R/W to the high-impedance state from H1 low
Enable time, R/W enabled (active) from H1 low
Disable time, Address to the high-impedance state from H1 low
Enable time, Address enabled (valid) from H1 low
Disable time, Data to the high-impedance state from H1 high
4
5*
4
dis(H1L-RW)
en(H1L-RW)
dis(H1L-A)
en(H1L-A)
4*
5
4*
dis(H1H-D)
* Not production tested
45
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DIGITAL SIGNAL PROCESSOR
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HOLD timing (continued)
H3
H1
t
t
su(HOLD- H1L)
su(HOLD- H1L)
t
w(HOLD)
HOLD
t
t
v(H1L-HOLDA)
v(H1L- HOLDA)
t
w(HOLDA)
HOLDA
STRB, PAGEx
R/W
t
d(H1L-SH)H
t
t
en(H1L-S)
dis(H1L-S)
t
en(H1L-RW)
t
dis(H1L-RW)
t
t
en(H1L-A)
dis(H1L-A)
A[23:0]
t
dis(H1H-D)
D[31:0]
Write Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 32. Timing for HOLD/HOLDA (After Write)
H3
H1
t
t
su(HOLD- H1L)
su(HOLD- H1L)
t
w(HOLD)
HOLD
HOLDA
t
v(H1L- HOLDA)
t
v(H1L- HOLDA)
t
w(HOLDA)
t
d(H1L-SH)H
t
t
en(H1L-S)
dis(H1L-S)
STRB, PAGEx
R/W
t
en(H1L-RW)
en(H1L-A)
t
dis(H1L-RW)
t
t
dis(H1L-A)
A[23:0]
D[31:0]
Read Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 33. Timing for HOLD/HOLDA (After Read)
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
general-purpose I/O timing
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The contents of the internal
control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The following table shows the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and vice versa.
timing requirements for peripheral pin general-purpose I/O (see Note 1, Figure 34, and Figure 35)
MIN MAX
UNIT
ns
t
t
Setup time, general-purpose input before H1 low
Hold time, general-purpose input after H1 low
3*
0*
su(GPIO-H1L)
h(H1L-GPIO)
ns
* Not production tested
NOTE 1: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
switching characteristics over recommended operating conditions for peripheral pin
general-purpose I/O (see Note 1, Figure 34, and Figure 35)
PARAMETER
Delay time, H1 high to general-purpose output
Disable time, general-purpose output from H1 high
MIN MAX
UNIT
ns
t
t
4
5
d(H1H-GPIO)
dis(H1H)
ns
NOTE 1: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Execution
of Store of
Peripheral-
Control
Value on Pin
Seen in
Peripheral-
Control
Buffers Go
From
Output to
Input
Synchronizer Delay
Register
Register
H3
H1
t
su(GPIO-H1L)
I/O
t
h(H1L-GPIO)
Control Bit
t
dis(H1H)
Peripheral Pin
(see Note A)
Output
Data Bit
Data
Sampled
Data
Seen
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 34. Change of Peripheral Pin From General-Purpose Output to Input Mode Timing
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
peripheral pin I/O timing (continued)
Execution of Store
of Peripheral-
Control Register
H3
H1
I/O
Control
Bit
t
d(H1H-GPIO)
t
d(H1H-GPIO)
Peripheral Pin
(see Note A)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 35. Change of Peripheral Pin From General-Purpose Input to Output Mode Timing
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
timer pin timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers. The following
tables define the timing parameters for the timer pin.
timing requirements for timer pin (see Figure 36 and Figure 37)
MIN
3*
MAX
UNIT
†
t
t
Setup time, TCLK external before H1 low
Hold time, TCLK external after H1 low
ns
ns
su(TCLK-H1L)
†
0
h(H1L-TCLK)
* Not production tested
†
These requirements are applicable for a synchronous input clock.
switching characteristics over recommended operating conditions for timer pin (see Figure 36 and
Figure 37)
MIN
MAX
UNIT
PARAMETER
t
t
Delay time, H1 high to TCLK internal valid
3
ns
d(H1H-TCLK)
TCLK ext
TCLK int
TCLK ext
TCLK int
t
x 2.6*
c(H)
‡
Cycle time, TCLK
ns
ns
c(TCLK)
32
t
x 2*
t
x 2 *
c(H)
c(H)
c(H)
t
+ 5*
‡
t
Pulse duration, TCLK
w(TCLK)
[t
/2] - 4*
[t
/2] + 4*
c(TCLK)
c(TCLK)
* Not production tested
‡
These parameters are applicable for an asynchronous input clock.
H3
H1
t
t
h(H1L-TCLK)
h(H1L-TCLK)
su(TCLK-H1L)
t
su(TCLK-H1L)
t
TCLK as input
t
w(TCLK)
t
c(TCLK)
Figure 36. Timer Pin Timing, Input
H3
H1
t
d(H1H-TCLK)
t
d(H1H-TCLK)
TCLK as output
Figure 37. Timer Pin Timing, Output
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
SHZ pin timing
The following table defines the timing parameter for the SHZ pin.
switching characteristics over recommended operating conditions for SHZ (see Figure 38)
PARAMETER
MIN
MAX
UNIT
t
Disable time, SHZ low to all outputs, I/O pins disabled (high impedance)
0*
8*
ns
dis(SHZ)
* Not production tested
SHZ
t
dis(SHZ)
All I/O Pins
NOTE A: Enabling SHZ destroys SM/SMJ320VC33 register and memory contents.
Assert SHZ = 1 and reset the SM/SMJ320VC33 to restore it to a known
condition.
Figure 38. Timing for SHZ
test access port timing
The following table defines the timing parameter for the test access port.
timing for test access port (see Figure 39)
MIN
5*
MAX
UNIT
ns
t
t
t
t
Setup time, TMS/TDI to TCK high
Hold time, TMS/TDI from TCK high
Delay time, TCK low to TDO valid
Rise time, TCK
su(TMS-TCKH)
h(TCKH-TMS)
d(TCKL-TDOV)
5*
ns
0*
10*
3*
ns
ns
r (TCK)
f (TCK)
t
Fall time, TCK
3*
ns
* Not production tested
TCK
t
r(TCK)
t
f(TCK)
t
su(TMS-TCKH)
TMS/TDI
TDO
t
t
d(TCHL-TDOV)
h(TCHK-TMS)
Figure 39. IEEE-1149.1 Test Access Port Timings
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
MECHANICAL DATA
GNM (S-CBGA-N144)
CERAMIC BALL GRID ARRAY
12,15
11,85
SQ
9,60 TYP
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2 3 4 5 6 7 8 9 10 11 12 13
2,40 MAX
0,56
0,34
Seating Plane
0,12
0,55
0,45
M
∅ 0,10
0,50
0,35
4201017/B 05/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
MECHANICAL DATA
HFG (S-CQFP-F164)
CERAMIC QUAD FLATPACK WITH NCTB
1.140 (28,96)
SQ
1.120 (28,45)
0.325 (8,26)
1.000 (25,40)
BSC
Tie Bar Width
”A”
0.275 (6,99)
41
1
42
164
1.520 (38,61)
1.480 (37,59)
2.505 (63,63)
2.485 (63,12)
82
124
83
123
”C”
1.150 (29,21)
BSC 8 Places
”B”
0.061 (1,55)
DIA 4 Places
0.059 (1,50)
0.105 (2,67) MAX
0.018 (0,46) MAX
0.010 (0,25)
0.006 (0,15)
164 X
BRAZE
0.014 (0,36)
0.002 (0,05)
0.040 (1,02)
0.030 (0,76)
0.009 (0,23)
0.004 (0,10)
0.020 (0,51) MAX
DETAIL ”B”
0.130 (3,30) MAX
0,025 (0,64)
DETAIL ”A”
DETAIL ”C”
4040231-9/J 01/99
NOTES: C. All linear dimensions are in inches (millimeters).
D. This drawing is subject to change without notice.
E. Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier
F. This package is hermetically sealed with a metal lid.
G. The leads are gold-plated and can be solder-dipped.
H. Leads not shown for clarity purposes
I. Falls within JEDEC MO-113AA (REV D)
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-0053901QYA
5962-0053901QYC
5962-0053902QYA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CFP
HFG
164
164
164
164
144
164
1
1
1
4
1
1
None
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-1-235C-UNLIM
Level-NC-NC-NC
CFP
HFG
CFP
HFG
5962-0053902QYC
SM320VC33GNMM150
SMJ320VC33HFGM150
CFP
HFG
CBGA
CFP
GNM
HFG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Use of such information may require a license from a third party under the patents or other intellectual property
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
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Amplifiers
amplifier.ti.com
www.ti.com/audio
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dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
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Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
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Logic
interface.ti.com
logic.ti.com
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Microcontrollers
power.ti.com
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www.ti.com/opticalnetwork
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www.ti.com/video
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www.ti.com/wireless
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Copyright 2005, Texas Instruments Incorporated
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