SN100KT5540 [TI]

OCTAL ECL-TO-TTL TRANSLATOR WITH 3-STATE OUTPUTS;
SN100KT5540
型号: SN100KT5540
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

OCTAL ECL-TO-TTL TRANSLATOR WITH 3-STATE OUTPUTS

输出元件
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SN100KT5540  
OCTAL ECL-TO-TTL TRANSLATOR  
WITH 3-STATE OUTPUTS  
SDZS005 – DECEMBER 1989  
R NT PACKAGE  
100K Compatible  
(T0P VIEW)  
Inverting Outputs  
Y1  
Y2  
Y3  
Y4  
A1  
A2  
A3  
A4  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
ECL and TTL Control Inputs  
2
3
Flow-Through Architecture Optimizes PCB  
Layout  
4
V
OE2 (TTL)  
5
CC  
Center Pin V , V , and GND  
CC EE  
Configurations Minimize High-Speed  
Switching Noise  
GND  
GND  
GND  
Y5  
Y6  
Y7  
V
6
EE  
GND  
OE1 (ECL)  
A5  
A6  
A7  
A8  
7
8
9
Package Options Include “Small Outline”  
Packages and Standard Plastic 300-mil  
DIPs  
10  
11  
12  
Y8  
description  
This octal ECL-to-TTL translator is designed to  
logic symbol  
provide a efficient translation between a 100K  
ECL signal environment and a TTL signal  
environment. This device is designed specifically  
to improve the performance and density of  
ECL-to-TTL CPU/bus-oriented functions such as  
memory-address drivers, clock drivers, and  
bus-oriented receivers and transmitters.  
ECL/TTL  
&
17  
OE1  
EN  
20  
OE2  
24  
1
2
ECL/TTL  
A1  
Y1  
23  
A2  
Y2  
Y3  
Y4  
22  
3
4
9
A3  
Two output pins, OE1 and OE2, are provided.  
These control inputs are ANDed together with  
OE1 being ECL compatible and OE2 being TTL  
compatible. This offers the choice of controlling  
the outputs of the device from either a TTL or ECL  
signal environment.  
21  
A4  
16  
A5  
Y5  
Y6  
Y7  
Y8  
15  
10  
11  
12  
A6  
14  
A7  
13  
A8  
The SN100KT5540 is characterized for operation  
from 0°C to 85°C.  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
FUNCTION TABLE  
OUTPUT  
ENABLE  
DATA  
OUTPUT  
INPUT  
TTL  
Y
OE1  
OE2  
A
X
X
L
X
H
L
H
X
L
Z
Z
H
L
L
H
L
Copyright 1989, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN100KT5540  
OCTAL ECL-TO-TTL TRANSLATOR  
WITH 3-STATE OUTPUTS  
SDZS005 – DECEMBER 1989  
logic diagram (positive logic)  
24  
1
2
3
4
ECL/TTL  
ECL/TTL  
ECL/TTL  
ECL/TTL  
A1  
Y1  
Y2  
23  
A2  
22  
Y3  
Y4  
A3  
21  
A4  
17  
OE1  
ECL/TTL  
20  
OE2  
16  
9
ECL/TTL  
ECL/TTL  
ECL/TTL  
ECL/TTL  
Y5  
Y6  
A5  
15  
10  
A6  
14  
11  
12  
Y7  
Y8  
A7  
13  
A8  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V to 0 V  
CC  
EE  
Input voltage range: TTL (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 V to 7 V  
ECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to 0 V  
EE  
Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
CC  
Voltage applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V  
Input current range (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA to 5 mA  
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA  
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN100KT5540  
OCTAL ECL-TO-TTL TRANSLATOR  
WITH 3-STATE OUTPUTS  
SDZS005 – DECEMBER 1989  
recommended operating conditions  
MIN  
4.5  
4.2  
2
NOM  
5
MAX  
5.5  
UNIT  
V
V
V
V
V
V
V
TTL supply voltage  
CC  
EE  
IH  
IL  
ECL supply voltage  
4.5  
4.8  
V
TTL high-level input voltage  
TTL low-level input voltage  
ECL high-level input voltage  
V
0.8  
840  
1490  
18  
V
1150  
1810  
mV  
mV  
mA  
mA  
mA  
°C  
IH  
IL  
ECL low-level input voltage  
TTL input clamp current  
High-level output current  
Low-level output current  
I
I
I
IK  
15  
OH  
OL  
48  
T
A
Operating free-air temperature  
0
85  
The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only.  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
= 4.2 V,  
MIN TYP  
MAX  
UNIT  
V
IK  
OE2 only  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 4.5 V,  
= 4.5 V,  
= 4.5 V,  
= 4.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5 V,  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
V
EE  
I = 18 mA  
1.2  
V
I
= 4.5 V ± 0.3 V,  
= 4.5 V ± 0.3 V,  
= 4.5 V ± 0.3 V,  
= 4.8 V,  
I
I
I
= 3 mA  
= 15 mA  
= 48 mA  
2.4  
2
3.3  
3.1  
OH  
OH  
OL  
V
OH  
V
V
OL  
0.38  
0.55  
0.1  
V
I
I
I
I
I
I
I
I
I
I
I
I
OE2 only  
V = 7 V  
I
V = 2.7 V  
I
V = 0.5 V  
I
mA  
µA  
mA  
µA  
µA  
µA  
µA  
mA  
mA  
mA  
mA  
mA  
pF  
I
OE2 only  
= 4.8 V,  
20  
IH  
OE2 only  
= 4.8 V,  
0.5  
350  
IL  
Data inputs and OE1  
Data inputs and OE1  
= 4.8 V,  
V
IH  
V
IL  
V
O
V
O
V
O
= 840 mV  
= 1810 mV  
= 2.7 V  
IH  
= 4.8 V,  
0.50  
IL  
= 4.8 V,  
50  
50  
225  
97  
OZH  
OZL  
= 4.8 V,  
= 0.5 V  
§
= 4.8 V,  
= 0 V  
100  
OS  
= 4.8 V  
67  
84  
81  
22  
5
CCH  
CCL  
CCZ  
EE  
= 4.8 V  
120  
116  
= 4.8 V  
= 4.8 V  
33  
C
= 4.5 V  
i
C
= 5 V,  
= 4.5 V  
7
pF  
o
§
All typical values are at V  
= 5 V, V  
= 4.5 V, T = 25°C.  
CC  
EE A  
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN100KT5540  
OCTAL ECL-TO-TTL TRANSLATOR  
WITH 3-STATE OUTPUTS  
SDZS005 – DECEMBER 1989  
switching characteristics over recommended ranges of supply voltage and operating free-air  
temperature (see Figure 1)  
C
= 50 pF,  
L
FROM  
TO  
R1 = 500 ,  
R2 = 500 Ω  
PARAMETER  
UNIT  
(INPUT)  
(OUTPUT)  
MIN TYP  
MAX  
6.4  
6.4  
6.9  
8.7  
8.1  
8
t
t
t
t
t
t
t
t
t
t
1.6  
1.6  
2.4  
3.5  
2.8  
2.2  
1.4  
2.5  
1.6  
0.7  
3.9  
4.2  
4.5  
5.9  
5.2  
4.6  
3.3  
4.7  
4.1  
3.3  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
PZH  
PZL  
PHZ  
PLZ  
A
Y
ns  
OE1  
OE1  
Y
Y
ns  
ns  
6.1  
7.9  
6.5  
6.4  
OE2  
Y
Y
ns  
ns  
OE2  
All typical values are at V  
= 5 V, V  
= 4.5 V, T = 25°C.  
EE A  
CC  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN100KT5540  
OCTAL ECL-TO-TTL TRANSLATOR  
WITH 3-STATE OUTPUTS  
SDZS005 – DECEMBER 1989  
PARAMETER MEASUREMENT INFORMATION  
7 V  
SWITCH POSITION TABLE  
Open  
R1  
S1  
TEST  
S1  
t
t
t
t
t
t
Open  
Open  
Open  
Closed  
Open  
Closed  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
From Output  
Under Test  
Test  
Point  
C
L
R2  
(See Note A)  
LOAD CIRCUIT  
t
r
t
f
950 mV  
ECL Input  
(See Note C)  
80%  
50%  
80%  
50%  
20%  
20%  
1690 mV  
t
PHL  
t
PLH  
V
OH  
Out-of-Phase  
TTL Output  
1.5 V  
1.5 V  
V
OL  
ECL INPUT PROPAGATION DELAY TIMES  
–950 mV  
Output  
3 V  
Output  
Control  
Control  
50%  
50%  
1.5 V  
1.5 V  
(Low-level  
enabling)  
–1690 mV  
(Low-level  
enabling)  
0
t
t
PZL  
t
t
PZL  
t
t
PLZ  
PLZ  
3.5 V  
3.5 V  
Output  
Output  
Waveform 1  
(See Note D)  
Waveform 1  
(See Note D)  
1.5 V  
1.5 V  
V
0.3 V  
0.3 V  
0.3 V  
OL  
V
V
OL  
t
PZH  
PHZ  
t
PZH  
PHZ  
V
0
OH  
OH  
0.3 V  
Output  
Waveform 2  
(See Note D)  
Output  
Waveform 2  
(See Note D)  
1.5 V  
1.5 V  
0
VOLTAGE WAVEFORMS  
ECL ENABLE AND DISABLE TIMES  
VOLTAGE WAVEFORMS  
TTL ENABLE AND DISABLE TIMES  
NOTES: A.C includes probe and jig capacitance.  
L
B.For TTL inputs, input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns,  
o
r
t 2.5 ns.  
f
C.For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 0.7 ns,  
o
r
t 0.7 ns.  
f
D.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2  
is for an output with internal conditions such that the output is high except when disabled by the output control.  
E.The outputs are measured one at a time with one transition per measurement.  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN100KT5540  
OCTAL ECL-TO-TTL TRANSLATOR  
WITH 3-STATE OUTPUTS  
SDZS005 – DECEMBER 1989  
FIGURE 1. LOAD CIRCUIT AND VOLTAGE WAVEFORMS  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jun-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
SOIC  
PDIP  
Drawing  
SN100KT5540DW  
SN100KT5540NT  
OBSOLETE  
OBSOLETE  
DW  
24  
24  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
NT  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
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information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
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