SN10501DBVRG4 [TI]
Low-Distortion High-Speed Rail-to-Rail Output Operational Amplifiers 5-SOT-23 -40 to 85;
| 型号： | SN10501DBVRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Distortion High-Speed Rail-to-Rail Output Operational Amplifiers 5-SOT-23 -40 to 85 放大器 光电二极管 商用集成电路 |
| 文件： | 总32页 (文件大小：1267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN10501
SN10502
SN10503
D-14
DBV-5
DGK-8
DGN-8
PWP-14
D-8
www.ti.com .................................................................................................................................................. SLOS408B–MARCH 2003–REVISED JANUARY 2009
HIGH-SPEED RAIL-TO-RAIL OUTPUT VIDEO AMPLIFIERS
1
FEATURES
2
•
High Speed
VIDEO DRIVE CIRCUIT
–
–
100 MHz Bandwidth (–3 dB, G = 2)
900 V/s Slew Rate
V
S+
•
Excellent Video Performance
+
–
–
–
50 MHz Bandwidth (0.1 dB, G = 2)
0.007% Differential Gain
10 µF
0.1 µF
75 Ω
Video In
5
3
4
SN10501
1
+
V
O
0.007 Differential Phase
75 Ω
−
•
Rail-to-Rail Output Swing
VO = –4.5 / 4.5 (RL= 150 Ω)
2
–
75 Ω
•
•
High Output Drive, IO = 100 mA (typ)
Ultralow Distortion
+
10 µF
0.1 µF
V
S−
–
–
HD2 = –78 dBc (f = 5 MHz, RL = 150 Ω)
HD3 = –85 dBc (f = 5 MHz, RL = 150 Ω)
1.43 kΩ
1.43 kΩ
6.3
•
Wide Range of Power Supplies
VS = 3 V to 15 V
V
= 0.1 V
PP
O
6.2
−0.1 dB at 49 MHz
–
6.1
6.0
APPLICATIONS
5.9
5.8
5.7
V
= 2 V
PP
O
•
•
•
•
•
Video Line Driver
Imaging
DVD / CD ROM
Active Filtering
−0.1 dB at 51 MHz
5.6
5.5
Gain = 2
R
V
R
= 150 Ω to GND
= ±5 V
L
S
General Purpose Signal Chain Conditioning
5.4
5.3
= 1.43 kΩ
F
100 k
1 M
10 M
100 M
1 G
DESCRIPTION
f − Frequency − Hz
The SN1050x family is a set of rail-to-rail output
single, dual, and triple low-voltage, high-output swing,
low-distortion high-speed amplifiers ideal for driving
data converters, video switching, or low distortion
applications. This family of voltage-feedback
amplifiers can operate from a single 15-V power
supply down to a single 3-V power supply while
consuming only 14 mA of quiescent current per
channel. In addition, the family offers excellent ac
performance with 100-MHz bandwidth, 900-V/µs slew
rate and harmonic distortion (THD) at –78 dBc at
5 MHz.
DEVICE
SN10501
SN10502
SN10503
DESCRIPTION
Single
Dual
Triple
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
owerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2009, Texas Instruments Incorporated
SN10501
SN10502
SN10503
SLOS408B–MARCH 2003–REVISED JANUARY 2009 .................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
operating free-air temperature range unless otherwise
(1)
UNIT
Supply voltage, VS
16.5 V
±VS
Input voltage, VI
Output current, IO
150 mA
4 V
Differential input voltage, VID
Continuous power dissipation See Dissipation Rating Table
Maximum junction temperature, TJ
150°C
125°C
(2)
Maximum junction temperature, continuous operation, longterm reliability, TJ
Storage temperature range, Tstg
–65°C to 150°C
300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
PACKAGE DISSIPATION RATINGS
POWER RATING(2)
PACKAGE
θJC(°C/W)(1)
θJA(°C/W)
T
A ≤ 25°C
TA = 85°C
156 mW
410 mW
600 mW
154 mW
685 mW
1.07 W
DBV (5)
D (8)
55
255.4
97.5
66.6
260
391 mW
1.02 W
1.5 W
38.3
26.9
54.2
4.7
D (14)
DGK (8)
DGN (8)(3)
PWP (14)(3)
385 mW
1.71 W
2.67 W
58.4
37.5
2.07
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion
starts to substantially increase. Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and long term reliability.
(3) The SN10501, SN10502, and SN10503 may incorporate a PowerPAD™ on the underside of the chip.
This acts as a heatsink and must be connected to a thermally dissipating plane for proper power
dissipation. Failure to do so may result in exceeding the maximum junction temperature which could
permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing
the PowerPAD™ thermally enhanced package.
2
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Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): SN10501 SN10502 SN10503
SN10501
SN10502
SN10503
www.ti.com .................................................................................................................................................. SLOS408B–MARCH 2003–REVISED JANUARY 2009
RECOMMENDED OPERATING CONDITIONS
MIN
1.35
MAX
8
UNIT
V
Dual supply
Supply voltage,(VS+ and VS-
)
Single supply
2.7
16
Input common-mode voltage range
VS- + 1.1
VS+ - 1.1
V
PACKAGE ORDERING INFORMATION
PACKAGED DEVICES
PACKAGE TYPE
TRANSPORT MEDIA, QUANTITY
SINGLE
SN10501DBVT
SN10501DBVR
SN10501DGK
SN10501DGKR
SN10501DGN
SN10501DGNR
SN10501D
SN10501DR
—
DUAL
—
TRIPLE
—
SOT-23-5
SOT-23-5
MSOP-8
Tape and Reel, 250
Tape and Reel, 3000
Rails, 75
—
—
SN10502DGK
SN10502DGKR
SN10502DGN
SN10502DGNR
SN10502D
SN10502DR
—
—
—
MSOP-8
Tape and Reel, 2500
Rails, 75
—
MSOP-8-PP
MSOP-8-PP
SOIC
—
Tape and Reel, 2500
Rails, 75
SN10503D
SN10503DR
SN10503PWP
SN10503PWPR
SOIC
Tape and Reel, 2500
Rails, 75
TSSOP-14-PP
TSSOP-14-PP
—
—
Tape and Reel, 2000
PIN ASSIGNMENTS
PACKAGE DEVICES
SN10501
DBV PACKAGE
(TOP VIEW)
SN10501
D, DGK, DGN PACKAGE
(TOP VIEW)
SN10502
D, DGK, DGN PACKAGE
(TOP VIEW)
1
2
3
5
V
S+
V
NC
IN−
IN+
VS−
OUT
NC
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
VS−
VS+
1
2
3
4
8
7
6
5
VS+
VOUT
NC
2OUT
2IN−
2IN+
V
S−
4
IN−
IN+
NC − No internal connection
SN10503
D, PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
NC
NC
2OUT
2IN−
2IN+
VS−
3IN+
3IN−
3OUT
VS+
1IN+
1IN−
1OUT
8
NC − No internal connection
Copyright © 2003–2009, Texas Instruments Incorporated
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SN10501
SN10502
SN10503
SLOS408B–MARCH 2003–REVISED JANUARY 2009 .................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS
VS = 5 V, RL = 150 Ω, and G = 2 unless otherwise noted
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
–40°C to
85°C
25°C
25°C
UNITS
MIN/MAX
AC PERFORMANCE
G = 1, VO = 100 mVPP
170
100
MHz
MHz
Typ
Typ
G = 2, VO = 100 mVPP
Rf = 1 kΩ
,
Small signal bandwidth
G = 10, VO = 100 mVPP
Rf = 1 kΩ
,
12
50
MHz
MHz
Typ
Typ
G = 2, VO = 100 mVPP
,
0.1 dB flat bandwidth
Rf = 1.43 kΩ
Gain bandwidth product
G > 10, f = 1 MHz, Rf = 1 kΩ
G = 2, VO = ±2.5 VPP
120
57
MHz
MHz
V/µs
ns
Typ
Typ
Min
Typ
Typ
(
)
(1)
Full-power bandwidth
Slew rate
G = 2, VO = ±2.5 VPP
900
25
Settling time to 0.1%
G = -2, VO = ±2 VPP
Settling time to 0.01%
Harmonic distortion
52
ns
Second harmonic distortion
Third harmonic distortion
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
Input voltage noise
–78
–85
dBc
dBc
%
Typ
Typ
Typ
Typ
Typ
Typ
Typ
G = 2, VO = 2 VPP, f = 5 MHz,
RL = 150 Ω
0.007
0.007
13
G = 2, R = 150 Ω
°
nV/√Hz
pA/√Hz
dB
f = 1 MHz
Input current noise
0.8
Crosstalk (dual and triple only)
DC PERFORMANCE
f = 5 MHz Ch-to-Ch
–90
Open-loop voltage gain (AOL
Input offset voltage
Input bias current
)
VO = ±2 V
VCM = 0 V
100
12
80
25
3
75
30
5
75
30
5
dB
mV
µA
nA
Min
Max
Max
Max
0.9
100
Input offset current
500
700
700
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Input resistance
–4 / 4
94
–3.9 / 3.9
70
V
Min
Min
Typ
Max
VCM = 2 V
65
65
dB
MΩ
pF
33
Input capacitance
Common-mode / differential
1 / 0.5
OUTPUT CHARACTERISTICS
RL = 150 Ω
RL = 499 Ω
–4.5 / 4.5
V
V
Typ
Min
Min
Min
Typ
Output voltage swing
–4.7 / 4.7 –4.5 / 4.5 –4.4 / 4.4 -4.4 / 4.4
Output current (sourcing)
Output current (sinking)
Output impedance
100
-100
0.09
92
88
88
mA
mA
Ω
RL = 10 Ω
-92
-88
-88
f = 1 MHz
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Power supply rejection (±PSRR)
±5
14
75
±8
18
62
±8
20
60
±8
22
60
V
Max
Max
Min
Per channel
mA
dB
(1) Full-power bandwidth = SR / 2πVpp
4
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Product Folder Link(s): SN10501 SN10502 SN10503
SN10501
SN10502
SN10503
www.ti.com .................................................................................................................................................. SLOS408B–MARCH 2003–REVISED JANUARY 2009
ELECTRICAL CHARACTERISTICS
VS = 5 V, RL = 150 Ω, and G = 2 unless otherwise noted
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to -40°C to
UNITS
25°C
25°C
MIN/MAX
70C
85C
AC PERFORMANCE
G = 1, VO = 100 mVPP
170
100
12
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Min
Typ
Typ
Small signal bandwidth
G = 2, VO = 100 mVPP, Rf = 1.5 kΩ
G = 10, VO = 100 mVPP, Rf = 1.5 kΩ
G = 2, VO = 100 mVPP, Rf = 1.24 kΩ
G > 10, f = 1 MHz, Rf = 1.5 kΩ
0.1 dB flat bandwidth
50
Gain bandwidth product
120
60
(
)
(1)
Full-power bandwidth
Slew rate
G = 2, VO = 4 V step
G = -2, VO = 2 V
750
27
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
48
ns
Second harmonic distortion
Third harmonic distortion
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
Input voltage noise
–82
–88
dBc
dBc
%
Typ
Typ
Typ
Typ
Typ
Typ
Typ
G = 2, VO = 2 VPP, f = 5 MHz,
RL = 150 Ω
0.014
0.011
13
G = 2, R = 150 Ω
°
nV/√Hz
pA/√Hz
dB
f = 1 MHz
Input current noise
0.8
Crosstalk (dual and triple only)
DC PERFORMANCE
f = 5 MHz Ch-to-Ch
–90
Open-loop voltage gain (AOL
Input offset voltage
Input bias current
)
VO = 1.5 V to 3.5 V
VCM = 2.5 V
100
12
80
25
3
75
30
5
75
30
5
dB
mV
µA
nA
Min
Max
Max
Max
0.9
100
Input offset current
500
700
700
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Input resistance
1 / 4
96
1.1 / 3.9
70
V
Min
Min
Typ
Max
VCM = 1.5 V to 3.5 V
65
65
dB
MΩ
pF
33
Input capacitance
Common-mode / differential
1 / 0.5
OUTPUT CHARACTERISTICS
RL = 150 Ω
RL = 499 Ω
0.5 / 4.5
V
V
Typ
Min
Min
Min
Typ
Output voltage swing
0.2 / 4.8 0.3 / 4.7 0.4 / 4.6 0.4 / 4.6
Output current (sourcing)
Output current (sinking)
Output impedance
95
85
80
80
mA
mA
Ω
RL = 10 Ω
–95
0.09
-85
–80
–80
f = 1 MHz
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Power supply rejection (±PSRR)
5
16
15
62
16
17
60
16
19
60
V
Max
Max
Min
Per channel
12
70
mA
dB
(1) Full-power bandwidth = SR / 2πVpp
Copyright © 2003–2009, Texas Instruments Incorporated
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SN10501
SN10502
SN10503
SLOS408B–MARCH 2003–REVISED JANUARY 2009 .................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Frequency response
Small signal frequency response
Large signal frequency response
Slew rate
1– 8
9, 10
11
vs Output voltage step
vs Frequency
12, 13
14, 15
16
Harmonic distortion
Voltage and current noise
Differential gain
vs Frequency
vs Number of loads
vs Number of loads
vs Supply voltage
vs Load resistance
vs Frequency
17, 18
19, 20
21
Differential phase
Quiescent current
Output voltage
22
Open-loop gain and phase
Rejection ratio
23
vs Frequency
24
Rejection ratio
vs Case temperature
vs Input common-mode range
vs Frequency
25
Common-mode rejection ratio
Output impedance
26, 27
28, 29
30
Crosstalk
vs Frequency
Input bias and offset current
vs Case temperature
31, 32
FREQUENCY RESPONSE
FREQUENCY RESPONSE
FREQUENCY RESPONSE
8
6.3
6.2
8
7
V
= 2 V
PP
V
= 2 V
PP
O
V
= 0.1 V
PP
O
O
7
−3 dB at 99 MHz
−3 dB at 99 MHz
−0.1 dB at 49 MHz
6
5
6.1
6.0
6
5
V
= 0.1 V
PP
O
4
3
2
5.9
5.8
5.7
4
3
2
V
= 2 V
PP
−3 dB at 99 MHz
O
V
= 0.1 V
PP
O
−0.1 dB at 51 MHz
−3 dB at 99 MHz
1
0
5.6
5.5
1
0
Gain = 2
Gain = 2
Gain = 2
R
V
= 150 Ω to GND
= ±5 V
R
V
= 150 Ω to GND
= ±5 V
R
V
= 150 Ω to GND
= ±5 V
L
L
L
S
S
S
5.4
5.3
−1
−2
−1
−2
R
F
= 1.43 kΩ
R
F
= 1.43 kΩ
R
F
= 301 Ω
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
FREQUENCY RESPONSE
Figure 2.
FREQUENCY RESPONSE
Figure 3.
FREQUENCY RESPONSE
6.3
6.2
8
7
6.3
6.2
V
= 2 V
PP
O
V
= 2 V
PP
O
−3 dB at 99 MHz
V
= 2 V
PP
O
−0.1 dB at 14 MHz
−0.1 dB at 58 MHz
6.1
6.0
6
5
6.1
6.0
V
= 0.1 V
PP
O
−3 dB at 99 MHz
5.9
5.8
5.7
4
3
2
5.9
5.8
5.7
V
= 0.1 V
PP
O
V
= 0.1 V
PP
−0.1 dB at 14 MHz
O
−0.1 dB at 48 MHz
5.6
5.5
1
0
5.6
5.5
Gain = 2
Gain = 2
Gain = 2
R
= 150 Ω to GND
= ±5 V
R
L
= 150 Ω to V /2
R
L
= 150 Ω to V /2
L
S
S
V
V
= 5 V
V
= 5 V
S
S
S
5.4
5.3
5.4
5.3
−1
−2
R
F
= 301 Ω
R
F
= 1.24 kΩ
R = 1.24 kΩ
F
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 4.
Figure 5.
Figure 6.
6
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SN10501
SN10502
SN10503
www.ti.com .................................................................................................................................................. SLOS408B–MARCH 2003–REVISED JANUARY 2009
FREQUENCY RESPONSE
FREQUENCY RESPONSE
FREQUENCY RESPONSE
8
7
8
7
6.3
6.2
V
= 2 V
PP
O
−3 dB at 89 MHz
V
= 0.1 V
PP
Gain = 2
O
−0.1 dB at 16 MHz
6
5
6
5
6.1
6.0
R
R
V
V
= 150 Ω
= 1 kΩ
= 100 mV
= ±5 V
L
V
= 0.1 V
PP
O
4
3
4
3
2
5.9
5.8
5.7
F
O
S
−3 dB at 84 MHz
PP
V
= 2 V
PP
O
−0.1 dB at 16 MHz
2
1
0
5.6
5.5
1
Gain = 2
Gain = 2
0
R
L
= 150 Ω to V /2
R
L
= 150 Ω to V /2
S
S
Gain = 1
V
R
= 5 V
= 301Ω
V
R
= 5 V
= 301 Ω
S
S
5.4
5.3
−1
−2
−1
−2
F
F
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 7.
Figure 8.
Figure 9.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
FREQUENCY RESPONSE
FREQUENCY RESPONSE
8
8
7
6
5
4
3
2
1200
1000
800
Gain = 2
7
6
5
4
3
2
V
= 5 V
S
Gain = 2
R
R
V
= 150 Ω
= 1 kΩ
= ±5 V
L
F
S
Rise
R
L
= 499 Ω
V
= ±5 V
S
Fall
R
V
V
= 1.5 kΩ
= 100 mV
= 5 V
F
O
S
PP
600
Gain = 2
400
1
0
R
R
V
V
= 150 Ω
= 1 kΩ
= 2 V
PP
= ±5 V
L
F
O
S
200
0
Gain = 1
1
0
−1
−2
100 k
1 M
10 M
100 M
1 G
0
1
2
3
4
5
6
7
8
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
V
− Output Voltage Step − V
O
Figure 10.
Figure 11.
Figure 12.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
0
0
800
Gain = 2
−10
Gain = 2
−10
Gain = 2
700
600
500
400
300
200
100
0
R
R
= 150 Ω
= 1 kΩ
= 5 V
L
F
S
R
V
= 150 Ω
= 2 V
PP
R
V
= 150 Ω
= 2 V
PP
L
L
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
Fall
O
S
O
S
V
V
= ±5 V
V
= 5 V
Rise
HD2
HD3
HD2
HD3
10
0
0.5
1
1.5
2
2.5
3
3.5
4
100
0.1
1
100
0.1
1
10
V
− Output Voltage Step − V
f − Frequency − MHz
f − Frequency − MHz
O
Figure 13.
Figure 14.
Figure 15.
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VOLTAGE AND CURRENT NOISE
DIFFERENTIAL GAIN
vs
DIFFERENTIAL PHASE
vs
vs
FREQUENCY
10
NUMBER OF LOADS
NUMBER OF LOADS
0.4
0.35
0.3
100
0.20
0.18
0.16
Gain = 2
R = 1.5 kΩ
40 IRE − NTSC
Worst Case ±100
Gain = 2
R = 1.5 kΩ
40 IRE − NTSC
Worst Case ±100 IRE Ramp
f
f
0.14 IRE Ramp
0.25
0.2
V
n
0.12
0.10
0.08
0.06
0.04
V
= 5 V
S
10
1
V
= 5 V
S
0.15
0.1
I
n
V
= ±5 V
S
V
3
= ±5 V
S
0.05
0
0.02
0
0.1
10 M
1
0
1
2
4
5
1 k
10 k
100 k
1 M
0
1
2
3
4
5
Number of Loads − 150 Ω
f − Frequency − Hz
Number of Loads − 150 Ω
Figure 16.
Figure 17.
Figure 18.
DIFFERENTIAL GAIN
vs
DIFFERENTIAL PHASE
vs
QUIESCENT CURRENT
vs
NUMBER OF LOADS
NUMBER OF LOADS
SUPPLY VOLTAGE
22
0.4
0.35
0.3
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
Gain = 2
R = 1.5 kΩ
40 IRE − PAL
Worst Case ±100 IRE Ramp
Gain = 2
R = 1.5 kΩ
40 IRE − PAL
Worst Case ±100 IRE Ramp
20
18
16
14
12
10
f
T
A
= 85°C
f
T
A
= 25°C
0.25
0.2
V
= 5 V
S
V
= 5 V
S
0.15
0.1
T
A
= −40°C
8
6
4
2
0
V
= ±5 V
S
V
= ±5 V
S
0.05
0
0.02
0
0
1
2
3
4
5
1.5
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
Number of Loads − 150 Ω
V
− Supply Voltage − ±V
Number of Loads − 150 Ω
S
Figure 19.
Figure 20.
Figure 21.
OUTPUT VOLTAGE
vs
OPEN-LOOP GAIN AND PHASE
REJECTION RADIO
vs
vs
LOAD RESISTANCE
FREQUENCY
FREQUENCY
5
4
3
110
100
90
80
70
60
50
40
30
20
10
220
200
180
160
140
120
100
80
100
V
= ±5 V, 5 V, and 3.3 V
S
V
= ±5 V, 5 V,
S
90
80
70
60
50
40
30
and 3.3 V
2
1
CMMR
T
A
= −40 to 85°C
0
PSRR
−1
60
−2
−3
40
20
10
0
20
−4
−5
0
0
−10
−20
10
100
1 k
10 k
0.1
1
10
100
100 1 k 10 k 100 k 1 M 10 M 100 M 1 G
R
L
− Load Resistance − Ω
f − Frequency − MHz
f − Frequency − Hz
Figure 22.
Figure 23.
Figure 24.
8
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REJECTION RATIO
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
INPUT COMMON-MODE RANGE
100
90
100
100
V
= ±5 V, 5 V, and 3.3 V
S
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
CMMR
80
PSRR
70
60
50
40
V
= 5 V
S
V
T
A
= ±5 V
= 25°C
S
T
A
= 25°C
10
0
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
−6
−4
−2
0
2
4
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
V
− Input Common-Mode Voltage Range − V
T
C
− Case Temperature − °C
V
− Input Common-Mode Voltage Range − V
ICR
ICR
Figure 25.
Figure 26.
Figure 27.
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
CROSSTALK
vs
FREQUENCY
FREQUENCY
FREQUENCY
120
100
10
100
10
Gain = 2
= 150 Ω to GND
= 2 V
PP
= ±5 V
Gain = 2
Crosstalk all Channels
R
R
= 150 Ω to V /2
L
L
S
100
80
V
V
V
V
= 2 V
= 5 V
O
S
O
S
PP
R
F
= 301 Ω
R
F
= 301 Ω
60
40
1
1
0.1
V
= ±5 V, 5 V, and 3.3 V
S
Gain = 1
0.1
R
= 150 Ω
= −1 dB
= 25°C
L
20
0
V
T
IN
R
F
= 1.43 kΩ
R
F
= 1.24 kΩ
A
0.01
0.01
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 28.
Figure 29.
Figure 30.
INPUT BIAS AND OFFSET CURRENT
INPUT BIAS AND OFFSET CURRENT
vs
vs
CASE TEMPERATURE
CASE TEMPERATURE
0.84
0.82
0.9
0.88
0.86
10
5
V
= 5 V
V
= ±5 V
S
S
5
0
I
OS
I
OS
0
0.8
−5
−10
I
IB+
I
IB+
0.78
−5
−10
−15
0.84
0.82
I
IB−
0.76
0.74
−15
−20
0.8
0.78
0.76
I
IB−
0.72
0.7
−20
−25
−25
−30
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Case Temperature − °C
Figure 31.
Figure 32.
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APPLICATION INFORMATION
decrease the loading effect of the feedback network
on the output of the amplifier, but this enhancement
comes at the expense of additional noise and
potentially lower bandwidth. Feedback-resistor values
between 1 kΩ and 2 kΩ are recommended for most
situations.
HIGH-SPEED OPERATIONAL AMPLIFIERS
The SN1050x operational amplifiers are a family of
single, dual, and triple rail-to-rail output voltage
feedback amplifiers. The SN1050x family combines
both a high slew rate and a rail-to-rail output stage.
WIDEBAND, INVERTING OPERATION
Applications Section Contents
Since the SN1050x family are general-purpose,
wideband voltage-feedback amplifiers, several
familiar operational-amplifier applications circuits are
available to the designer. Figure 34 shows a typical
inverting configuration where the input and output
impedances and noise gain from Figure 33 are
retained in an inverting circuit configuration. Inverting
operation is one of the more common requirements
and offers several performance benefits. The
inverting configuration shows improved slew rates
and distortion due to the pseudo-static voltage
maintained on the inverting input.
•
•
•
•
•
Wideband, Noninverting Operation
Wideband, Inverting Gain Operation
Video Drive Circuits
Single Supply Operation
Power Supply Decoupling Techniques and
Recommendations
Active Filtering With the SN1050x
Driving Capacitive Loads
Board Layout
Thermal Analysis
Additional Reference Material
Mechanical Package Drawings
•
•
•
•
•
•
5 V
+V
S
+
WIDEBAND, NONINVERTING OPERATION
100 pF
0.1 µF
6.8 µF
The SN1050x is a family of unity gain stable
rail-to-rail output voltage feedback operational
amplifiers designed to operate from a single 3-V to
15-V power supply.
+
V
R
649 Ω
O
T
C
T
_
0.1 µF
499 Ω
50 Ω Source
Figure 33 is the noninverting gain configuration of
2V/V used to demonstrate the typical performance
curves.
R
R
f
g
V
I
1.3 kΩ
1.3 kΩ
R
M
0.1 µF
6.8 µF
52.3 Ω
5 V
+V
S
+
100 pF
+
−V
S
−5 V
100 pF
0.1 µF 6.8 µF
50 Ω Source
49.9 Ω
Figure 34. Wideband, Inverting Gain
Configuration
+
_
V
I
V
O
499 Ω
In the inverting configuration, some key design
considerations must be noted. One is that the gain
resistor (Rg) becomes part of the signal channel input
impedance. If input impedance matching is desired
(beneficial when the signal is coupled through a
cable, twisted pair, long PC-board trace, or other
transmission-line conductors), Rg may be set equal to
the required termination value and Rf adjusted to give
the desired gain. However, care must be taken when
dealing with low inverting gains, because the resulting
feedback-resistor value can present a significant load
to the amplifier output. For an inverting gain of 2,
setting Rg to 49.9 Ω for input matching eliminates the
need for RM but requires a 100-Ω feedback resistor.
This has the advantage that the noise gain becomes
equal to 2 for a 50-Ω source impedance—the same
R
f
1.3 kΩ
1.3 kΩ
R
g
0.1 µF 6.8 µF
+
100 pF
−V
S
−5 V
Figure 33. Wideband, Noninverting Gain
Configuration
Voltage-feedback amplifiers, unlike current-feedback
designs, can use a wide range of resistors values to
set their gain with minimal impact on their stability
and frequency response. Larger-valued resistors
10
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as the noninverting circuit in Figure 33. However, the
amplifier output now sees the 100-Ω feedback
resistor in parallel with the external load. To eliminate
this excessive loading, increase both Rg and Rf,
values, as shown in Figure 34, and then provide the
input-matching impedance with a third resistor (RM) to
ground. The total input impedance becomes the
parallel combination of Rg and RM.
Video Drive Circuits
Most video-distribution systems are designed with
75-Ω series resistors to drive a matched 75-Ω cable.
In order to deliver a net gain of 1 to the 75-Ω
matched load, the amplifier is typically set up for a
voltage gain of 2, compensating for the 6-dB
attenuation of the voltage divider formed by the series
and shunt 75-Ω resistors at either end of the cable.
The circuit shown in Figure 36 meets this
requirement. The SN1050x gain flatness and
The last major consideration to discuss in inverting
amplifier design is setting the bias-current
cancellation resistor on the noninverting input. If the
resistance is set equal to the total dc resistance
looking out of the inverting terminal, the output dc
error, due to the input bias currents, is reduced to the
input-offset current multiplied by Rf in Figure 34. The
dc source impedance looking out of the inverting
terminal is 1.3 kΩ || (1.3 kΩ + 25.6 Ω) = 649 Ω. To
reduce the additional high-frequency noise introduced
by the resistor at the noninverting input, and
differential
gain/phase
performance
provide
exceptional results in video distribution applications.
V
S+
+
10 µF
0.1 µF
Video In
5
3
4
+
75 Ω
1
power-supply feedback, RT is bypassed with
capacitor to ground.
a
75 Ω
−
V
O
2
75 Ω
SINGLE SUPPLY OPERATION
+
10 µF
V
S−
The SN1050x family is designed to operate from a
single 3-V to 15-V power supply. When operating
from a single power supply, care must be taken to
ensure that the input signal and amplifier are biased
appropriately to allow for the maximum output voltage
swing. The circuits shown in Figure 35 demonstrate
methods to configure an amplifier for single-supply
operation.
0.1 µF
1.43 kΩ
1.43 kΩ
Figure 36. Cable Drive Application
Differential gain and phase measure the change in
overall small-signal gain and phase for the color
subcarrier frequency (3.58 MHz in NTSC systems) vs
changes in the large-signal output level (which
represents luminance information in a composite
video signal). The SN1050x, with the typical 150-Ω
load of a single matched video cable, shows less
than 0.007% / 0.007° differential gain/phase errors
over the standard luminance range for a positive
video (negative sync) signal.
+V
S
50 Ω Source
+
V
I
V
O
R
T
49.9 Ω
_
499 Ω
+V
2
S
R
f
1.3 kΩ
V
S+
R
g
75 Ω
1.3 kΩ
0.1 µF
V
O
+
+V
2
S
10 µF
75 Ω
R
f
Video In
5
3
4
1.3 kΩ
+
75 Ω
75 Ω
V
1
S
50 Ω Source
−
V
O
R
g
_
+
2
75 Ω
V
I
1.3 kΩ
T
75 Ω
75 Ω
V
O
52.3 Ω
R
499 Ω
1.43 kΩ
1.43 kΩ
0.1 µF
+V
S
+V
2
S
V
O
2
V
S−
+
10 µF
Figure 35. DC-Coupled Single Supply Operation
Figure 37. Video Distribution
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Similar performance is observed for negative video
1.24 kΩ
1.24 kΩ
signals. In practice, similar performance is achieved
even with three video loads as shown in Figure 37
due to the linear high-frequency output impedance of
the SN1050x. This circuit is suitable for driving video
cables, provided that the length does not exceed a
few feet. If longer cables are driven, the gain of the
SN1050x can be increased to compensate for cable
loss.
Output Range
= 2 V to 4.5 V
5 V
V
Range
O
= 0 V to 1.25V
75 Ω
Input Range
= 1 V to 2.25 V
-
+
470 µF
75 Ω
R
T
Configuring the SN1050x for single-supply video
applications is easily done, but attention must be
given to input and output bias voltages to ensure
proper system operation. Unlike some video
amplifiers, the SN1050x input common-mode voltage
range does not include the negative power supply,
but rather it is about 1-V from each power supply. For
split supply configurations, this is very beneficial. For
single-supply systems, there are some design
constraints that must be observed.
Figure 39. AC-Coupled Output Single-Supply
Video Amplifier
In some systems, the physical size and/or cost of a
470-µF capacitor can be prohibitive. One way to
circumvent this issue is to use two smaller capacitors
in a feedback configuration as shown in Figure 40.
This is commonly known as SAG correction. This
circuit increases the gain of the amplifier up to 3 V/V
at low frequencies to counteract the increased
impedance of the capacitor placed at the amplifier
output. One issue that must be resolved is that the
gain at low frequencies is typically limited by the
power-supply voltage and the output swing of the
amplifier. Therefore, it is possible to saturate the
amplifier at these low frequencies if full analysis is not
done on this system which includes both input and
output requirements.
Figure 38 shows a single-supply video configuration
illustrating the dc bias voltages acceptable for the
SN1050x. The lower end of the input common-mode
range is specified as 1 V. The upper end is limited to
4 V with the 5-V supply shown, but the output range
and gain of 2 limit the highest acceptable input
voltage to 4.5 V / 2 = 2.25 V. The 4.5-V output is
what is typically expected with a 150-Ω load. It is
easily seen that the input and output voltage ranges
are limiting factors in the total system. Both
specifications must be taken into account when
designing a system.
1.24 kΩ
1.24 kΩ
22 µF
5 V
1.24 kΩ
1.24 kΩ
1.24
V
Range
O
kΩ
Output Range
= 2 V to 4.5 V
= 0 V to 1.25V
75 Ω
Input Range
= 1 V to 2.25 V
5 V
-
V
Range
O
+
= 1 V to 2.25 V
22 µF
75 Ω
Input Range
= 1 V to 2.25 V
−
+
75 Ω
R
T
Output Range
= 2 V to 4.5 V
75 Ω
R
T
Figure 40. AC-Coupled SAG Corrected Output
Single-Supply Video Amplifier
Figure 38. DC-Coupled Single-Supply Video
Amplifier
Many times the output of the video encoder or DAC
does not have the capability to output the 1-V to
2.25-V range, but rather a 0-V to 1.25-V range. In this
instance, the signal must be ac-coupled to the
amplifier input as shown in Figure 41. Note that it
does not matter what the voltage output of the DAC
is, but rather the voltage swing should be kept less
In most systems, this may be acceptable because
most receivers are ac-coupled and set the black level
to the desired system value, typically 0 V (0-IRE).
But, to ensure full compatibility with any system, it is
often desirable to place an ac coupling capacitor on
the output as shown in Figure 39. This removes the
dc-bias voltage appearing at the amplifier output. To
minimize field tilt, the size of this capacitor is typically
470 µF, although values as small as 220 µF have
been used with acceptable results.
than 1.25 VPP
.
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1.24 kΩ
1.24 kΩ
68 µF
1.24 kΩ
2.49 kΩ
Output Range
= 2 V to 4.5 V
Output Range
= 0.5 V to 4.5V
5 V
DAC Output
= 0 V to 2V
5 V
5 V
5 V
V
O
Range
V
Range
O
= 0 V to 1.25V
DAC Output
= 0 V to 1.25V
75 Ω
470 µF
-
= 0 V to 2V
75 Ω
4.64 kΩ
−
+
10 kΩ
+
470 µF
10 µF
10 kΩ
47 µF
75 Ω
75 Ω
2.26 kΩ
Input Range
= 1 V to 2.25V
Input = 2.5 V
Figure 41. AC-Coupled Input and Output
Single-Supply Video Amplifier
Figure 44. Inverting AC-Coupled Wide Output
Swing Single-Supply Video Amplifier
To further increase dynamic range at the output, the
output dc bias should be centered around 2.5 V for
the 5-V system shown. However, a wide output range
requires a wide input range, and should be centered
around 2.5 V. The best ways to accomplish this are
to ac-couple the gain resistor or bias it at 2.5 V with a
reference supply as shown in Figure 42 and
Figure 43.
APPLICATION CIRCUITS
Active Filtering With the SN1050x
High-frequency active filtering with the SN1050x is
achievable due to the amplifier's high slew rate, wide
bandwidth, and voltage feedback architecture.
Several options are available for high-pass, low-pass,
bandpass, and bandstop filters of varying orders. A
simple two-pole, low-pass filter is presented in
Figure 45 as an example, with two poles at 25 MHz.
68 µF
1.24 kΩ
1.24 kΩ
Output Range
= 0.5 V to 4.5V
5 V
5 V
4.7 pF
V
Range
O
DAC Output
= 0 V to 2V
= 0 V to 2V
75 Ω
-
3.01 kΩ
50 Ω Source
1.3 kΩ
+
470 µF
V
I
47 µF
1.3 kΩ
52.3 Ω
75 Ω
5 V
3.01 kΩ
Input Range
= 1.5 V to 3.5V
_
49.9 Ω
V
O
Figure 42. AC-Coupled Wide Output Swing
Single-Supply Video Amplifier
+
33 pF
−5 V
1.24 kΩ
1.24 kΩ
Figure 45. A Two-Pole Active Filter With Two
Poles Between 90 MHz and 100 MHz
2.5 V
Output Range
= 0.5 V to 4.5V
5 V
5 V
V
O
Range
= 0 V to 2V
Driving Capacitive Loads
DAC Output
= 0 V to 2V
75 Ω
470 µF
-
3.01 kΩ
+
A demanding, yet very common application for an op
amp is capacitive loading. Often, this load is the input
of an A/D converter, including additional external
capacitance, sometimes recommended to improve
A/D linearity. A high-speed, high open-loop gain
amplifier like the SN1050x can be very susceptible to
decreased stability and closed-loop response peaking
when a capacitive load is placed directly on the
output pin. When the amplifier's open-loop output
resistance is considered, the capacitance introduces
an additional pole in the signal path that can
decrease the phase margin. When the primary
considerations are frequency-response flatness,
pulse response fidelity, or distortion, the simplest and
most effective solution is to isolate the capacitive load
47 µF
75 Ω
3.01 kΩ
Input Range
= 1.5 V to 3.5V
Figure 43. AC-Coupled Wide Output Swing
Single-Supply Video Amplifier Using Voltage
Reference
Another beneficial configuration is to use the amplifier
in an inverting configuration as shown in Figure 44.
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from the feedback loop by inserting a series isolation
resistor between the amplifier output and the
capacitive load. This does not eliminate the pole from
the loop response, but rather shifts it and adds a zero
at a higher frequency. The additional zero cancels the
phase lag from the capacitive-load pole, thus
increasing the phase margin and improving stability.
ground- and power-plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors,
effective at lower frequency, should also be used
on the main supply pins. These may be placed
somewhat farther from the device and may be
shared among several devices in the same area
of the PC board.
Power Supply Decoupling Techniques and
Recommendations
Power-supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher-quality ac performance,
most notably improved distortion performance. The
following guidelines ensure the highest level of
performance.
3. Careful selection and placement of external
components preserves the high frequency
performance of the SN1050x. Choose
low-reactance resistors. Surface-mount resistors
work best, and allow a tighter overall layout.
Metal-film and carbon-composition axial-lead
resistors can also provide good high-frequency
performance. Again, keep component leads and
PC-board trace length as short as possible.
1. Place decoupling capacitors as close to the
power-supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply
Never use wirewound resistors in
a
high
2. Placement priority; locate the smallest-value
capacitors nearest to the device.
frequency application. Since the output pin and
inverting-input pin are the most sensitive to
parasitic capacitance, always position the
feedback and series-output resistor, if any, as
close as possible to the output pin. Other network
3. Solid
power
and
ground
planes
are
recommended to reduce the inductance along
power-supply return-current paths, with the
exception of the areas underneath the input and
output pins.
components,
such
as
noninverting-input
termination resistors, should also be placed close
to the package. Where double-sided component
mounting is allowed, place the feedback resistor
directly under the package on the other side of
the board between the output and inverting input
pins. Even with a low parasitic capacitance
shunting the external resistors, excessively high
resistor values can create significant time
constants that can degrade performance. Good
axial-lead metal-film or surface-mount resistors
have approximately 0.2 pF in shunt with the
resistor. For resistor values > 2.0 kΩ, this
parasitic capacitance can add a pole and/or a
zero below 400 MHz that can affect circuit
operation. Keep resistor values as low as
4. Recommended values for power supply
decoupling include a bulk decoupling capacitor
(6.8 to 22 µF), a mid-range decoupling capacitor
(0.1 µF) and
a high frequency decoupling
capacitor (1000 pF) for each supply. A 100 pF
capacitor can be used across the supplies as well
for extremely high-frequency return currents, but
often is not required.
BOARD LAYOUT
Achieving
optimum
performance
with
a
high-frequency amplifier like the SN1050x requires
careful attention to board layout parasitics and
external component types.
possible,
consistent
with
load-driving
Recommendations to optimize performance include:
considerations. A good starting point for design is
to set the Rf to 1.3 kΩ for low-gain, noninverting
applications. This automatically keeps the resistor
noise terms low, and minimizes the effect of their
parasitic capacitance.
1. Minimize parasitic capacitance to any ac
ground for all signal I/O pins. Parasitic
capacitance on the output and inverting-input pins
can cause instability: on the noninverting input, it
can react with the source impedance to cause
unintentional band limiting. To reduce unwanted
capacitance, open a window in all ground and
power planes around the signal I/O pins. Keep
ground and power planes unbroken elsewhere on
the board.
4. Connections to other wideband devices on
the board may be made with short, direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Use relatively wide traces (50 mils to 100
mils), preferably with ground and power planes
opened up around them. Low parasitic capacitive
loads (<4 pF) may not need an R(ISO), since the
SN1050x is nominally compensated to operate
2. Minimize the distance (< 0.25”) from the
power-supply pins to high frequency 0.1-µF
decoupling capacitors. At the device pins, the
14
Submit Documentation Feedback
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): SN10501 SN10502 SN10503
SN10501
SN10502
SN10503
www.ti.com .................................................................................................................................................. SLOS408B–MARCH 2003–REVISED JANUARY 2009
with a 2-pF parasitic load. Higher parasitic
capacitive loads without an R(ISO) are allowed as
the signal gain increases (increasing the
unloaded phase margin). If a long trace is
required, and the 6-dB signal loss intrinsic to a
THERMAL ANALYSIS
The SN1050x family of devices does not incorporate
automatic thermal shutoff protection, so the designer
must take care to ensure that the design does not
violate the absolute-maximum junction temperature of
doubly-terminated
acceptable, implement
transmission
line
is
the
device.
Failure
may
result
if
the
a
matched-impedance
absolute-maximum junction temperature of 150°C is
exceeded.
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A
50-Ω environment is normally not necessary
The thermal characteristics of the device are dictated
by the package and the PC board. Maximum power
dissipation for a given package can be calculated
using the following formula.
onboard, and in fact
a
higher-impedance
environment improves distortion as shown in the
distortion-versus-load plots. With a characteristic
board-trace impedance definition based on board
material and trace dimensions, a matching series
resistor in the trace from the output of the
SN1050x is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device:
this total effective impedance should be set to
match the trace impedance. If the 6-dB
attenuation of a doubly terminated transmission
Tmax–TA
+
qJA
PDmax
where:
P
is the maximum power dissipation in the amplifier (W).
Dmax
T
is the absolute maximum junction temperature (°C).
max
T is the ambient temperature (°C).
A
θ
θ
= θ + θ
JA
JC CA
is the thermal coefficient from the silicon junctions to the
JC
case (°C/W).
θ
is the thermal coefficient from the case to ambient air
CA
(°C/W).
line is unacceptable,
a long trace can be
1.5
series-terminated at the source end only. Treat
the trace as a capacitive load in this case and
add an R(ISO) resistor in series with the output to
isolate any capacitance to the amplifier. This
setting does not preserve the signal integrity of a
doubly-terminated line. If the input impedance of
the destination device is low, the signal is
attenuated due to the voltage divider formed by
the series output into the terminating impedance.
1.25
8-Pin D Package
1
0.75
5-Pin DBV Package
0.5
0.25
0
5. Socketing a high speed part like the SN1050x
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
−40
−20
0
20
40
60
80
T
A
− Ambient Temperature − °C
socket can create
a
troublesome parasitic
θ
θ
T
= 170°C/W for 8-Pin SOIC (D)
= 324.1°C/W for 5-Pin SOT−23 (DBV)
= 150°C, No Airflow
JA
network which can make it almost impossible to
achieve a smooth, stable frequency response.
Best results are obtained by soldering the
SN1050x onto the board.
JA
J
Figure 46. Maximum Power Dissipation
vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to consider not only quiescent power
dissipation, but also dynamic power dissipation. Often
maximum power dissipation is difficult to quantify
because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
Copyright © 2003–2009, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): SN10501 SN10502 SN10503
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
PACKAGING INFORMATION
Orderable Device
SN10501D
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
D
8
5
5
5
5
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
10501D
SN10501DBVR
SN10501DBVRG4
SN10501DBVT
SN10501DBVTG4
SN10501DG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
3000
3000
250
250
75
Green (RoHS
& no Sb/Br)
SBBI
SBBI
SBBI
SBBI
10501D
BHA
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN10501DGK
SN10501DGKG4
SN10501DGN
SN10501DGNG4
SN10501DR
VSSOP
VSSOP
DGK
DGK
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
BHA
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
AJU
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
AJU
SOIC
2500
Green (RoHS
& no Sb/Br)
10501D
SN10501DRG4
SN10502D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
TBD
Call TI
Call TI
-40 to 85
-40 to 85
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
10502D
10502D
AJT
SN10502DG4
SN10502DGK
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
D
8
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
80
Green (RoHS
& no Sb/Br)
SN10502DGKG4
SN10502DGKR
80
Green (RoHS
& no Sb/Br)
AJT
2500
Green (RoHS
& no Sb/Br)
AJT
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN10502DGKRG4
SN10502DGN
ACTIVE
VSSOP
DGK
8
8
TBD
Call TI
Call TI
-40 to 85
-40 to 85
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
DGN
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AJV
AJV
SN10502DGNG4
SN10502DGNR
SN10502DGNRG4
SN10502DR
MSOP-
PowerPAD
8
8
8
8
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
-40 to 85
OBSOLETE
OBSOLETE
ACTIVE
MSOP-
PowerPAD
MSOP-
PowerPAD
Call TI
Call TI
SOIC
2500
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
10502D
10503D
10503D
SN10503
SN10502DRG4
SN10503D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
TBD
Call TI
Call TI
-40 to 85
-40 to 85
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN10503DG4
SN10503DR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2500
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN10503DRG4
SN10503PWP
ACTIVE
ACTIVE
SOIC
D
14
14
TBD
Call TI
Call TI
-40 to 85
-40 to 85
HTSSOP
PWP
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN10503PWPG4
ACTIVE
HTSSOP
PWP
14
TBD
Call TI
Call TI
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN10501DBVR
SN10501DBVT
SN10501DR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
3000
250
180.0
180.0
330.0
330.0
330.0
330.0
9.0
9.0
3.15
3.15
6.4
3.2
3.2
5.2
3.4
5.2
9.0
1.4
1.4
2.1
1.4
2.1
2.1
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
Q1
Q1
8
2500
2500
2500
2500
12.4
12.4
12.4
16.4
12.0
12.0
12.0
16.0
SN10502DGKR
SN10502DR
VSSOP
SOIC
DGK
D
8
5.3
8
6.4
SN10503DR
SOIC
D
14
6.5
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN10501DBVR
SN10501DBVT
SN10501DR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
3000
250
182.0
182.0
367.0
358.0
367.0
367.0
182.0
182.0
367.0
335.0
367.0
367.0
20.0
20.0
35.0
35.0
35.0
38.0
8
2500
2500
2500
2500
SN10502DGKR
SN10502DR
VSSOP
SOIC
DGK
D
8
8
SN10503DR
SOIC
D
14
Pack Materials-Page 2
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相关型号：
SN10502DGKG4
Low-Distortion High-Speed Rail-to-Rail Output Operational Amplifiers 8-VSSOP -40 to 85
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