SN54ABTH32318_06 [TI]

18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS; 18位TRI -PORT通用总线交换器
SN54ABTH32318_06
型号: SN54ABTH32318_06
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
18位TRI -PORT通用总线交换器

文件: 总11页 (文件大小:190K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN54ABTH32318, SN74ABTH32318  
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS  
SCBS180E – JUNE 1992 – REVISED MAY 1997  
Members of the Texas Instruments  
Widebus+ Family  
High-Impedance State During Power Up  
and Power Down  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
UBE (Universal Bus Exchanger)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
High-Drive Outputs (–32-mA I , 64-mA I  
)
OL  
OH  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Package Options Include 80-Pin Plastic  
Thin Quad Flat (PN) Package With  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
12 × 12-mm Body Using 0.5-mm Lead Pitch  
and 84-Pin Ceramic Quad Flat (HT) Package  
OLP  
= 5 V, T = 25°C  
CC  
A
SN74ABTH32318 . . . PN PACKAGE  
(TOP VIEW)  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61  
A2  
A3  
A4  
GND  
A5  
A6  
A7  
A8  
A9  
C8  
C7  
C6  
GND  
C5  
C4  
C3  
C2  
C1  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
1
2
3
4
5
6
7
8
9
V
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
CC  
CC  
GND  
A10  
A11  
A12  
A13  
A14  
GND  
A15  
A16  
A17  
GND  
B18  
B17  
B16  
B15  
B14  
GND  
B13  
B12  
B11  
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+, EPIC-ΙΙB, and UBE are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54ABTH32318, SN74ABTH32318  
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS  
SCBS180E – JUNE 1992 – REVISED MAY 1997  
SN54ABTH32318 . . . HT PACKAGE  
(TOP VIEW)  
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64  
1
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
A2  
A3  
A4  
GND  
A5  
A6  
A7  
A8  
A9  
C8  
C7  
C6  
GND  
C5  
C4  
C3  
C2  
C1  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
V
V
CC  
CC  
NC  
GND  
A10  
A11  
A12  
A13  
A14  
GND  
A15  
A16  
A17  
NC  
GND  
B18  
B17  
B16  
B15  
B14  
GND  
B13  
B12  
B11  
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42  
NC – No internal connection  
description  
The ’ABTH32318 consist of three 18-bit registered input/output (I/O) ports. These registers combine D-type  
latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be  
exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations  
of real-time and stored data can be exchanged among the three ports.  
Data flow in each direction is controlled by the output-enable (OEA, OEB, and OEC), select-control (SELA,  
SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data  
register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held  
at a high or low logic level. If LEA is low, data is stored on the low-to-high transition of CLKA. Output data  
selection is accomplished by the select-control pins. All three ports have active-low output enables, so when  
the output-enable input is low, the outputs are active; when the output-enable input is high, the outputs are in  
the high-impedance state.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54ABTH32318, SN74ABTH32318  
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS  
SCBS180E – JUNE 1992 – REVISED MAY 1997  
description (continued)  
The SN54ABTH32318 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABTH32318 is characterized for operation from –40°C to 85°C.  
Function Tables  
STORAGE  
INPUTS  
OUTPUT  
CLKA  
LEA  
L
A
L
L
L
H
X
X
L
H
H
L
X
X
L
Q
Q
0
0
L
H
L
H
H
H
A-portregistershown. BandCportsare  
similar but use CLKB, CLKC, LEB, and  
LEC.  
Output level before the indicated  
steady-state input conditions were  
established  
A-PORT OUTPUT  
INPUTS  
OUTPUT A  
OEA SELA  
H
L
L
X
H
L
Z
Output of C register  
Output of B register  
B-PORT OUTPUT  
INPUTS  
OEB SELB  
OUTPUT B  
H
L
L
X
H
L
Z
Output of A register  
Output of C register  
C-PORT OUTPUT  
INPUTS  
OEC SELC  
OUTPUT C  
H
L
L
X
H
L
Z
Output of B register  
Output of A register  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54ABTH32318, SN74ABTH32318  
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS  
SCBS180E – JUNE 1992 – REVISED MAY 1997  
logic diagram (positive logic)  
77  
OEC  
76  
SELC  
Q
CLK  
74  
CLKC  
LEC  
75  
52  
LE  
D
C1  
24  
25  
OEB  
SELB  
Q
27  
26  
CLKB  
LEB  
CLK  
LE  
D
28  
B1  
78  
79  
OEA  
SELA  
Q
CLK  
22  
23  
CLKA  
LEA  
LE  
D
80  
A1  
1 of 18 Channels  
Pin numbers shown are for the PN package.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54ABTH32318, SN74ABTH32318  
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS  
SCBS180E – JUNE 1992 – REVISED MAY 1997  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
CC  
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
I
Voltage range applied to any output in the high or power-off state, V  
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V  
O
Current into any output in the low state, I : SN54ABTH32318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA  
O
SN74ABTH32318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA  
IK  
OK  
I
Output clamp current, I  
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA  
O
Package thermal impedance, θ (see Note 2): PN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W  
Storage temperature range, T  
JA  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.  
recommended operating conditions (see Note 3)  
SN54ABTH32318 SN74ABTH32318  
UNIT  
MIN  
4.5  
2
MAX  
MIN  
4.5  
2
MAX  
V
V
V
V
Supply voltage  
5.5  
5.5  
V
V
CC  
High-level input voltage  
Low-level input voltage  
Input voltage  
IH  
0.8  
0.8  
V
IL  
0
V
0
V
CC  
V
I
CC  
I
I
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Power-up ramp rate  
–24  
48  
–32  
64  
mA  
mA  
ns/V  
µs/V  
°C  
OH  
OL  
t/v  
t/V  
Outputs enabled  
10  
10  
200  
–55  
200  
–40  
CC  
T
Operating free-air temperature  
125  
85  
A
NOTE 3: Unused control pins must be held high or low to prevent them from floating.  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54ABTH32318, SN74ABTH32318  
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS  
SCBS180E – JUNE 1992 – REVISED MAY 1997  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
SN54ABTH32318  
SN74ABTH32318  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN TYP  
MAX  
MIN TYP  
MAX  
V
V
V
V
V
= 4.5 V,  
= 4.5 V,  
= 5 V,  
I = –18 mA  
–1.2  
–1.2  
V
IK  
CC  
CC  
CC  
I
I
I
I
I
I
I
= –3 mA  
= –3 mA  
= –24 mA  
= –32 mA  
= 48 mA  
= 64 mA  
2.5  
3
2.5  
3
OH  
OH  
OH  
OH  
OL  
OL  
V
OH  
2
V
= 4.5 V  
= 4.5 V  
CC  
CC  
2
0.55  
0.55  
0.55  
0.55  
V
V
V
V
OL  
100  
100  
mV  
µA  
hys  
Control inputs  
V
V
= 0 to 5.5 V,  
V = V  
or GND  
or GND  
±1  
±1  
CC  
I
CC  
CC  
I
I
A, B, or C ports  
= 2.1 V to 5.5 V,  
V = V  
I
±20  
±20  
CC  
V = 0.8 V  
100  
100  
I
I
A, B, or C ports  
V
CC  
= 4.5 V  
µA  
I(hold)  
V = 2 V  
I
–100  
–100  
I
I
I
I
I
V
V
V
V
V
= 0 to 2.1 V, V = 0.5 V to 2.7 V, OE = X  
±50  
±50  
±100  
50  
±50  
±50  
±100  
50  
µA  
µA  
µA  
µA  
mA  
OZPU  
OZPD  
off  
CC  
CC  
CC  
CC  
CC  
O
= 2.1 V to 0, V = 0.5 V to 2.7 V, OE = X  
O
= 0,  
V or V 4.5 V  
I O  
= 5.5 V, V = 5.5 V  
O
Outputs high  
= 2.5 V  
CEX  
§
= 5.5 V,  
V
–50  
–100  
–180  
2
–50  
–100  
–180  
2
O
O
Outputs high  
Outputs low  
V
I
= 5.5 V,  
= 0,  
CC  
O
I
45  
45  
mA  
CC  
V = V  
or GND  
I
CC  
Outputs disabled  
1
1
V
= 5.5 V, One input at 3.4 V,  
CC  
Other inputs at V  
0.5  
0.5  
mA  
I  
CC  
or GND  
CC  
V = 2.5 V or 0.5 V  
C
C
Control inputs  
3
3
pF  
pF  
i
I
A, B, or C ports  
V
O
= 2.5 V or 0.5 V  
11.5  
11.5  
io  
§
All typical values are at V  
= 5 V, T = 25°C.  
A
CC  
This parameter is specified by characterization.  
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.  
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.  
CC  
timing requirements over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted) (see Figure 1)  
SN54ABTH32318 SN74ABTH32318  
UNIT  
MIN  
MAX  
MIN  
MAX  
f
t
Clock frequency  
Pulse duration  
150  
150  
MHz  
ns  
clock  
LE high  
3.3  
3.3  
2.4  
2.1  
1.4  
2.1  
3.3  
3.3  
2.4  
2.1  
1.4  
2.1  
w
CLK high or low  
A, B, or C before CLK↑  
A, B, or C before LE↓  
A, B, or C after CLK↑  
A, B, or C after LE↓  
t
t
Setup time  
Hold time  
ns  
ns  
su  
h
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54ABTH32318, SN74ABTH32318  
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS  
SCBS180E – JUNE 1992 – REVISED MAY 1997  
switching characteristics over recommended ranges of supply voltage and operating free-air  
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)  
L
SN54ABTH32318 SN74ABTH32318  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MHz  
ns  
MIN  
150  
1.4  
1.1  
1.4  
1.8  
2.6  
2.6  
2.5  
2.5  
1.4  
2.4  
1
MAX  
MIN  
150  
1.4  
1.1  
1.4  
1.8  
2.6  
2.6  
2.5  
2.5  
1.4  
2.4  
1
MAX  
f
t
t
t
t
t
t
t
t
t
t
t
t
max  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
6.5  
6.8  
6.7  
6.8  
8
6.1  
6.6  
6.5  
6.5  
7.5  
6.9  
7.4  
6.7  
6.8  
7.1  
6.2  
6
A, B, or C  
SEL  
C, B, or A  
A, B, or C  
A, B, or C  
A, B, or C  
A, B, or C  
A, B, or C  
ns  
ns  
ns  
ns  
ns  
LE  
7.4  
8
CLK  
7.2  
6.9  
7.2  
6.4  
6.4  
OE  
OE  
2
2
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54ABTH32318, SN74ABTH32318  
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS  
SCBS180E – JUNE 1992 – REVISED MAY 1997  
PARAMETER MEASUREMENT INFORMATION  
7 V  
Open  
TEST  
/t  
S1  
S1  
500 Ω  
From Output  
Under Test  
t
Open  
7 V  
PLH PHL  
GND  
t
/t  
PLZ PZL  
C
= 50 pF  
t
/t  
Open  
L
PHZ PZH  
500 Ω  
(see Note A)  
3 V  
0 V  
LOAD CIRCUIT  
Timing Input  
Data Input  
1.5 V  
t
w
t
t
h
su  
3 V  
0 V  
3 V  
0 V  
Input  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
3 V  
0 V  
3 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Input  
t
PZL  
t
t
t
PHL  
PLH  
t
PLZ  
Output  
Waveform 1  
S1 at 7 V  
3.5 V  
V
V
OH  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Output  
V
V
+ 0.3 V  
OL  
V
OL  
OL  
(see Note B)  
t
PHZ  
t
PHL  
PLH  
t
PZH  
Output  
Waveform 2  
S1 at Open  
(see Note B)  
V
OH  
V
V
OH  
– 0.3 V  
OH  
1.5 V  
1.5 V  
Output  
0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time with one transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
6-Feb-2006  
PACKAGING INFORMATION  
Orderable Device  
SN74ABTH32318PN  
SN74ABTH32318PNG4  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
LQFP  
PN  
80  
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
LQFP  
PN  
80  
119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
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Addendum-Page 1  
MECHANICAL DATA  
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996  
PN (S-PQFP-G80)  
PLASTIC QUAD FLATPACK  
0,27  
0,17  
0,50  
60  
M
0,08  
41  
61  
40  
0,13 NOM  
80  
21  
1
20  
Gage Plane  
9,50 TYP  
0,25  
12,20  
SQ  
11,80  
0,05 MIN  
0°7°  
14,20  
SQ  
13,80  
0,75  
0,45  
1,45  
1,35  
Seating Plane  
0,08  
1,60 MAX  
4040135 /B 11/96  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-026  
1
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