SN54AC574_16 [TI]
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS;
| 型号： | SN54AC574_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS 输出元件 |
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SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
SN54AC574 . . . J OR W PACKAGE
SN74AC574 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3-State Outputs Drive Bus Lines Directly
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
Package Options Include Plastic
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
Small-Outline (DW) Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIP Packages
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
GND
SN54AC574 . . . FK PACKAGE
(TOP VIEW)
The eight flip-flops of the ′AC574 are D-type
edge-triggered flip-flops. On the positive transi-
tion of the clock (CLK) input, the Q outputs are set
to the logic levels set up at the data (D) inputs.
3
2
1
20 19
18
4
5
6
7
8
3D
4D
5D
6D
7D
2Q
3Q
4Q
5Q
6Q
17
16
15
14
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the high-
impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines
significantly. The high-impedance state and the
increased drive provide the capability to drive bus
lines in a bus-organized system without need for
interface or pullup components.
9 10 11 12 13
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54AC574 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AC574 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
†
logic symbol
logic diagram (positive logic)
1
OE
1
EN
C1
OE
11
CLK
11
CLK
2
1D
3
19
18
17
16
15
14
13
12
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
C1
1D
2D
4
19
1Q
2
1D
3D
5
4D
6
5D
7
6D
8
7D
9
To Seven Other Channels
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC)
O
Output clamp current, I
(V < 0 or V > V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
CC)
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.6 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
A
DW package . . . . . . . . . . . . . . . . . 1.6 W
N package . . . . . . . . . . . . . . . . . . . 1.3 W
PW package . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
recommended operating conditions (see Note 3)
SN54AC574
SN74AC574
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
6
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
2.1
2.1
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
V
V
IH
0.9
1.35
1.65
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5V
= 5.5 V
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
–12
–24
–24
12
–12
–24
–24
12
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
24
24
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
8
0
8
ns/V
T
A
–55
125
–40
85
°C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
SN54AC574
SN74AC574
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.9
TYP
MAX
MIN
2.9
4.4
5.4
2.4
3.7
4.7
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
3 V
I
= –50 µA
4.4
4.4
OH
5.4
5.4
V
OH
V
I
I
= –12 mA
= –24 mA
2.56
3.94
4.94
2.46
3.76
4.76
OH
4.5 V
5.5 V
3 V
OH
0.1
0.1
0.1
0.1
0.5
0.5
0.5
±1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
0.1
0.1
OL
0.1
V
OL
V
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
±0.1
±0.5
4
0.44
0.44
0.44
±1
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
OL
I
I
I
V = V
or GND
µA
µA
µA
pF
I
I
CC
V
= V or GND
CC
±5
80
±2.5
40
OZ
CC
O
V = V
or GND,
or GND
I
O
= 0
I
CC
CC
C
V = V
4.5
i
I
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V ± 0.3 V
CC
T
= 25°C
SN54AC574
SN74AC574
A
UNIT
MIN
6
MAX
MIN
7.5
6.5
2.5
MAX
MIN
7
MAX
t
w
t
su
t
h
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
ns
ns
ns
2.5
1.5
3
1.5
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V ± 0.5 V
CC
T
= 25°C
SN54AC574
SN74AC574
A
UNIT
MIN
4
MAX
MIN
5
MAX
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
ns
ns
ns
1.5
1.5
3.5
2.5
2
1.5
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
112
8.5
SN54AC574
SN74AC574
TO
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
75
3.5
3.5
2.5
3
MAX
MIN
55
1
MAX
MIN
60
MAX
f
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
13.5
12
16.5
15
3.5
3.5
2.5
3
15
13.5
12
CLK
Q
Q
Q
7.5
1
7
11
1
13
ns
ns
OE
OE
6.5
10.5
12
1
12.5
14
11.5
13
3.5
2
7.5
1
2.5
1.5
5.5
9
1
10.5
10
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
153
6
SN54AC574
SN74AC574
TO
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
95
2
MAX
MIN
85
MAX
MIN
85
2
MAX
f
t
t
t
t
t
t
max
PLH
PHL
PZH
PZL
PHZ
PLZ
9.5
8.5
8.5
8
1.5
1.5
1.5
1.5
1.5
1.5
11.5
10.5
9.5
9.5
11.5
9
11
9.5
9
CLK
Q
Q
Q
2
5.5
5
2
2
2
ns
ns
OE
OE
2
5
1.5
1.5
1
9
2
6
9.5
7.5
10.5
8.5
1
4.5
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
= 50 pF, f = 1 MHz
TYP
40
UNIT
pF
C
C
pd
L
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
Open
From Output
Under Test
t
2 × V
CC
Open
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
V
CC
50% V
Timing Input
Data Input
CC
0 V
t
w
t
h
t
3 V
0 V
su
V
CC
50% V
50% V
Input
CC
CC
50% V
50% V
CC
CC
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
Input
50% V
50% V
50% V
50% V
CC
CC
CC
CC
t
0 V
0 V
t
PZL
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
50% V
CC
CC
CC
V
OL
+ 0.3 V
S1 at 2 × V
(see Note B)
CC
V
OL
V
V
OL
t
PHZ
t
PLH
t
t
PHL
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
OH
0 V
V
OH
– 0.3 V
Out-of-Phase
Output
50% V
50% V
50% V
CC
CC
CC
V
OL
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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performed, except those mandated by government requirements.
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