SN54AC86_15 [TI]
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES;
| 型号： | SN54AC86_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES 输入元件 |
| 文件： | 总6页 (文件大小：97K) |
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SN54AC86, SN74AC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS533A – AUGUST 1995 – REVISED MAY 1996
SN54AC86 . . . J OR W PACKAGE
SN74AC86 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
1A
1B
1Y
2A
2B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
4B
4A
4Y
3B
3A
3Y
2Y
GND
description
8
The ’AC86 are quadruple 2-input exclusive-OR
gates. The devices perform the Boolean function
Y = A B or Y = AB + AB in positive logic.
SN54AC86 . . . FK PACKAGE
(TOP VIEW)
A common application is as a true/complement
element. If one of the inputs is low, the other input
is reproduced in true form at the output. If one of
the inputs is high, the signal on the other input is
reproduced inverted at the output.
3
2
1
20 19
18
4A
NC
4Y
NC
3B
1Y
NC
2A
4
5
6
7
8
17
16
15
14
The SN54AC86 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AC86 is characterized for
operation from –40°C to 85°C.
NC
2B
9 10 11 12 13
FUNCTION TABLE
(each gate)
NC – No internal connection
INPUTS
OUTPUT
Y
A
B
L
L
L
L
H
H
L
H
L
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC86, SN74AC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS533A – AUGUST 1995 – REVISED MAY 1996
†
logic symbol
1
= 1
1A
2
3
6
1Y
2Y
1B
4
2A
5
2B
9
3A
8
10
3Y
4Y
3B
12
11
4A
13
4B
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
= 1
These five equivalent exclusive-OR symbols are valid for an ’AC86 gate in positive logic; negation may be
shown at any two ports.
LOGIC-IDENTITY ELEMENT
EVEN-PARITY ELEMENT
ODD-PARITY ELEMENT
=
2k
2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high)
if an odd number of inputs
(i.e., only 1 of the 2) are
active.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC86, SN74AC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS533A – AUGUST 1995 – REVISED MAY 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . 1.25 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
A
DB package . . . . . . . . . . . . . . . . . . . 0.5 W
N package . . . . . . . . . . . . . . . . . . . . 1.1 W
PW package . . . . . . . . . . . . . . . . . . . 0.5 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
recommended operating conditions (see Note 3)
SN54AC86
SN74AC86
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
6
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
2.1
2.1
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
V
V
IH
0.9
1.35
1.65
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
–12
–24
–24
12
–12
–24
–24
12
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
24
24
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
8
0
8
ns/V
T
A
–55
125
–40
85
°C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC86, SN74AC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS533A – AUGUST 1995 – REVISED MAY 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
SN54AC86
SN74AC86
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.9
TYP
MAX
MIN
2.9
4.4
5.4
2.4
3.7
4.7
3.85
MAX
MIN
2.9
MAX
3 V
I
= –50 µA
4.5 V
5.5 V
3 V
4.4
4.4
OH
5.4
5.4
I
I
= –12 mA
= –24 mA
2.56
3.86
4.86
2.46
3.76
4.76
OH
V
OH
V
4.5 V
5.5 V
5.5 V
5.5 V
3 V
OH
†
†
I
I
= –50 mA
= –75 mA
OH
3.85
OH
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
OL
0.1
0.1
0.1
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.5
0.44
0.44
0.44
OL
V
OL
V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
0.5
OL
0.5
†
†
I
I
= 50 mA
1.65
OL
= 75 mA
1.65
±1
OL
I
I
V = V
or GND
or GND,
or GND
±0.1
±1
µA
µA
pF
I
I
CC
CC
CC
V = V
I
I
O
= 0
2
40
20
CC
C
VI = V
2.6
i
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
6.5
SN54AC86
SN74AC86
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
2
MAX
11.5
11.5
MIN
1
MAX
MIN
1.5
MAX
12.5
12.5
t
t
14
14
PLH
A or B
Y
ns
2
6
1
1.5
PHL
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
4.5
SN54AC86
SN74AC86
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
MAX
8.5
MIN
1
MAX
MIN
1
MAX
9
t
t
10
10
PLH
A or B
Y
ns
1.5
4.5
8.5
1
1
9.5
PHL
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
C
C
25
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC86, SN74AC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS533A – AUGUST 1995 – REVISED MAY 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
S1
500 Ω
From Output
Under Test
Open
TEST
S1
t
/t
Open
PLH PHL
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
t
w
2.7 V
Input
50% V
50% V
CC
CC
0 V
V
CC
50% V
50% V
Input
CC
CC
t
VOLTAGE WAVEFORMS
0 V
t
t
PHL
PLH
V
CC
V
OH
In-Phase
Output
50% V
CC
50% V
Timing Input
50% V
CC
CC
0 V
V
OL
t
t
PLH
su
PHL
t
h
V
V
OH
CC
Data
Input
Out-of-Phase
Output
50% V
50% V
50% V
CC
CC
CC
V
50% V
CC
0 V
OL
VOLTAGE WAVEFORMS
C includes probe and jig capacitance.
L
VOLTAGE WAVEFORMS
NOTES: A.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t
2.5 ns, t
f
2.5 ns.
O
r
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1998, Texas Instruments Incorporated
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