SN54ACT00_16 [TI]
QUADRUPLE 2-INPUT POSITIVE-NAND GATES;
| 型号： | SN54ACT00_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE 2-INPUT POSITIVE-NAND GATES 输入元件 |
| 文件： | 总5页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ACT00, SN74ACT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS523B – AUGUST 1995 – REVISED AUGUST 1999
SN54ACT00 . . . J OR W PACKAGE
SN74ACT00 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
Package Options Include Plastic
1A
1B
1Y
2A
2B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), DIP
(N) Packages, Ceramic Chip Carriers (FK),
Flat (W), and DIP (J) Packages
4B
4A
4Y
3B
3A
3Y
2Y
GND
description
8
The ‘ACT00 devices contain four independent 2-input
NAND gates. Each gate performs the Boolean
function of Y = A B or Y = A + B in positive logic.
SN54ACT00 . . . FK PACKAGE
(TOP VIEW)
The SN54ACT00 is characterized for operation over
the full military temperature range of –55°C to 125°C.
The SN74ACT00 is characterized for operation from
–40°C to 85°C.
3
2
1
20 19
18
1Y
NC
2A
4A
NC
4Y
NC
3B
4
5
6
7
8
17
16
15
14
FUNCTION TABLE
(each gate)
NC
2B
INPUTS
OUTPUT
Y
9 10 11 12 13
A
B
H
X
L
H
L
L
H
H
X
NC – No internal connection
†
logic symbol
logic diagram, each gate (positive logic)
1
1A
2
A
Y
B
&
3
6
1Y
2Y
3Y
4Y
1B
4
2A
5
2B
9
3A
10
3B
12
4A
13
4B
8
11
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT00, SN74ACT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS523B – AUGUST 1995 – REVISED AUGUST 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions (see Note 3)
SN54ACT00
SN74ACT00
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
– 24
24
– 24
24
8
mA
mA
ns/V
°C
OH
OL
∆t/∆v
0
8
0
T
–55
125
–40
85
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT00, SN74ACT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS523B – AUGUST 1995 – REVISED AUGUST 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
SN54ACT00
SN74ACT00
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
4.49
I
I
= – 50 µA
OH
5.4
5.49
5.4
5.4
3.86
4.86
3.7
3.76
4.76
V
OH
V
= – 24 mA
= – 50 mA
OH
4.7
†
I
I
3.85
OH
†
= –75 mA
3.85
OH
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
OL
OL
0.36
0.36
0.5
0.44
0.44
V
OL
I
= 24 mA
V
0.5
†
†
I
I
= 50 mA
1.65
OL
= 75 mA
1.65
±1
OL
I
I
V = V
or GND
or GND,
±0.1
±1
µA
µA
I
I
CC
CC
V = V
I = 0
O
2
40
20
CC
I
One input at 3.4 V,
Other inputs at GND or V
‡
∆I
CC
5.5 V
5 V
0.6
2.6
1.6
1.5
mA
pF
CC
C
V = V
I
or GND
CC
i
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
5.5
SN54ACT00
SN74ACT00
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
MAX
MIN
1
MAX
9.5
8
MIN
1
MAX
9.5
8
t
t
9
7
PLH
A or B
Y
ns
1.5
4
1
1
PHL
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
C
C
40
pF
pd
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT00, SN74ACT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS523B – AUGUST 1995 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
TEST
/t
S1
1.5 V
1.5 V
Input
t
Open
PLH PHL
t
t
t
PHL
PLH
PHL
V
2 × V
CC
Open
OH
In-Phase
Output
S1
50% V
CC
50% V
50% V
500 Ω
CC
From Output
Under Test
V
OL
t
PLH
C
= 50 pF
L
500 Ω
V
OH
(see Note A)
Out-of-Phase
Output
50% V
CC
CC
V
OL
LOAD CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1999, Texas Instruments Incorporated
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