SN54ACT16240_14 [TI]
16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS;
| 型号： | SN54ACT16240_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 驱动 输出元件 |
| 文件： | 总6页 (文件大小：109K) |
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SN54ACT16240, 74ACT16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS137C – JULY 1989 – REVISED NOVEMBER 1996
SN54ACT16240 . . . WD PACKAGE
74ACT16240 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
1OE
1Y1
1Y2
GND
1Y3
1Y4
2OE
1A1
1A2
GND
1A3
1A4
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
Flow-Through Architecture Optimizes
PCB Layout
3
4
5
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
6
V
V
7
CC
CC
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
8
9
500-mA Typical Latch-Up Immunity at
125°C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Spacings
V
V
CC
CC
description
4Y1
4Y2
GND
4Y3
4Y4
4A1
4A2
GND
4A3
4A4
3OE
The SN54ACT16240 and 74ACT16240 are 16-bit
buffers or line drivers designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters. The
devices can be used as four 4-bit buffers, two 8-bit
buffers, or one 16-bit buffer. These devices
provide inverting outputs and symmetrical
active-low output-enable (OE) inputs.
4OE
The 74ACT16240 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ACT16240 is characterized for operation over the full military temperature range of –55°C to 125°C.
The 74ACT16240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each section)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT16240, 74ACT16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS137C – JULY 1989 – REVISED NOVEMBER 1996
†
logic symbol
1
1OE
EN1
EN2
EN3
EN4
48
2OE
3OE
25
24
4OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1
1
1
1
1
2
3
4
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
5
6
8
9
11
12
13
14
16
17
19
20
22
23
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT16240, 74ACT16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS137C – JULY 1989 – REVISED NOVEMBER 1996
logic diagram (positive logic)
1
25
36
35
33
32
1OE
3OE
3A1
3A2
3A3
3A4
13
2
3
5
6
47
3Y1
1Y1
1Y2
1Y3
1A1
14
46
3Y2
1A2
16
44
3Y3
1A3
17
43
3Y4
1A4
1Y4
24
30
29
27
48
4OE
4A1
4A2
4A3
4A4
2OE
19
8
9
41
4Y1
2Y1
2Y2
2A1
20
40
4Y2
2A2
22
11
12
38
4Y3
2A3
2Y3
2Y4
23
26
37
4Y4
2A4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum package power dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.2 W
Storage temperature range, T
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT16240, 74ACT16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS137C – JULY 1989 – REVISED NOVEMBER 1996
recommended operating conditions (see Note 3)
SN54ACT16240
MIN NOM MAX
74ACT16240
MIN NOM
UNIT
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
24
–24
24
mA
mA
ns/V
°C
OH
OL
I
∆t/∆v
0
10
0
10
T
–55
125
–40
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
SN54ACT16240 74ACT16240
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
5.4
3.8
4.8
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
I
= –50 µA
OH
5.4
5.4
3.94
4.94
3.7
V
OH
= –24 mA
V
OH
4.7
†
†
I
I
= –50 mA
= –75 mA
3.85
OH
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
OL
OL
0.36
0.36
0.5
0.44
0.44
V
OL
I
= 24 mA
V
0.5
†
†
I
I
= 50 mA
1.65
OL
= 75 mA
1.65
±1
OL
I
I
I
V = V
or GND
±0.1
±0.5
8
±1
±10
160
µA
µA
µA
I
I
CC
CC
V
= V
or GND
±5
OZ
CC
O
CC
V = V
or GND,
I
O
= 0
80
I
One input at 3.4 V,
Other inputs at VCC or GND
‡
5.5 V
0.9
1
1
mA
∆I
CC
C
C
V = V or GND
5.5 V
5 V
4.5
12
pF
pF
i
I
CC
= V or GND
CC
V
O
o
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT16240, 74ACT16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS137C – JULY 1989 – REVISED NOVEMBER 1996
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
5
SN54ACT16240 74ACT16240
UNIT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
2.3
4.1
2.6
3.3
5.9
5.1
MAX
7.7
MIN
MAX
MIN
2.3
4.1
2.6
3.3
5.9
5.1
MAX
t
t
t
t
t
t
2
9.5
8.5
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
6.7
9.2
3
11.5
10.1
12.2
12.7
12
10.2
9.4
5.6
8.5
2
OE
OE
6.7
10.2
11
2.5
4.5
4
11.4
12
8.3
7.4
9.9
10.7
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
38
9
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per driver
C
= 50 pF,
L
f = 1 MHz
pF
pd
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
500 Ω
t
t
/t
Open
PLH PHL
/t
From Output
Under Test
t
2 × V
PLZ PZL
CC
/t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
Output
Control
(low-level
enabling)
LOAD CIRCUIT
3 V
0 V
1.5 V
1.5 V
t
PZL
3 V
0 V
t
PLZ
Output
V
CC
Input
1.5 V
1.5 V
Waveform 1
S1 at 2 × V
50% V
CC
20% V
CC
CC
CC
V
V
OL
t
(see Note B)
PHL
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
80% V
50% V
50% V
Output
CC
CC
V
50% V
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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