SN54ACT3641PCB [TI]
1024 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY; 1024 】 36主频先入先出存储器
| 型号： | SN54ACT3641PCB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1024 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY |
| 文件： | 总26页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Output-Ready and Almost-Empty Flags
Synchronized by CLKB
Clocked FIFO Buffering Data From Port A
to Port B
Low-Power 0.8 µm Advanced CMOS
Technology
Memory Size: 1024 × 36
Supports Clock Frequencies up to 50 MHz
Fast Access Times of 15 ns
Synchronous Read-Retransmit Capability
Mailbox Register in Each Direction
Released as DSCC SMD (Standard
Microcircuit Drawing) 5962-9560801QYA
and 5962-9560801NXD
Programmable Almost-Full and
Almost-Empty Flags
Package Options include 132-Pin Ceramic
Quad Flat (HFP) and 120-Pin Plastic Quad
Flat (PCB) Packages
Microprocessor Interface Control Logic
Input-Ready and Almost-Full Flags
Synchronized by CLKA
description
The SN54ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies
up to 50 MHz and has read access times as fast as 15 ns. The 1024 × 36 dual-port SRAM FIFO buffers data
from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be
accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths.
Expansion is also possible in word depth.
The SN54ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfersthroughaportaregatedtothelow-to-hightransitionofacontinuous(free-running)portclockbyenable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The
output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset
values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.
The SN54ACT3641 is characterized for operation over the full military temperature range of – 55°C to 125°C.
For more information on this device family, see the following application reports:
•
•
•
FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering
(literature number SCAA009)
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
Metastability Performance of Clocked FIFOs (literature number SCZA004)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
HFP PACKAGE
(TOP VIEW)
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1 132 130 128
131
129
126 124
127 125
122 120 118
123
121 119
117
116
NC
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
NC
NC
A35
A34
A33
A32
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
V
CC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
V
CC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
98
97
V
CC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
96
95
94
93
92
V
91
CC
B15
B14
B13
B12
GND
NC
90
89
88
87
V
86
CC
A12
NC
85
NC
84
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
PCB PACKAGE
(TOP VIEW)
A35
A34
A33
A32
1
2
3
4
5
6
7
8
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
V
A31
CC
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
CC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
V
CC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
V
CC
B15
B14
B13
B12
GND
V
A12
CC
NC – No internal connection
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
functional block diagram
MBF1
Mail1
Register
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBA
1024 × 36
SRAM
Reset
Logic
RST
RTM
RFM
36
Write
Pointer
Read
Pointer
A0–A35
B0–B35
Status-Flag
IR
AF
OR
AE
Logic
Flag-Offset
Register
FS0/SD
FS1/SEN
CLKB
CSB
W/RB
ENB
Port-B
Control
Logic
10
Mail2
Register
MBB
MBF2
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
Terminal Functions
TERMINAL
NAME
I/O
I/O
O
DESCRIPTION
A0–A35
Port-A data. The 36-bit bidirectional data port for side A.
Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less
than or equal to the value in the almost-empty offset register (X).
AE
Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO
is less than or equal to the value in the almost-full offset register (Y).
AF
O
I/O
I
B0–B35
CLKA
Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. IR and AF are synchronous to the low-to-high transition of CLKA.
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. OR and AE are synchronous to the low-to-high transition of CLKB.
CLKB
CSA
CSB
I
I
I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0–B35 outputs are in the high-impedance state when CSB is high.
ENA
ENB
I
I
Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
Flag offset select 1/serial enable, flag offset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs used
for flag offset-register programming. During a device reset, FS1/SEN and FS0/SD select the flag offset-programming
method. Three offset-register programming methods are available: automatically load one of two preset values, parallel
load from port A, and serial load.
FS1/SEN,
FS0/SD
I
When serial load is selected for flag offset-register programming, FS1/SEN is used as an enable synchronous to the
low-to-high transition of CLKA. When FS1/SEN is low, a rising edge on CLKA loads the bit present on FS0/SD into the
X-and Y-offset registers. The number of bit writes required to program the offset registers is 20. The first bit write stores
the Y-register MSB and the last bit write stores the X-register LSB.
Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes to
its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point
of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.
IR
O
I
MBA
MBB
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
FIFO data for output.
I
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. MBF1
is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by a
reset.
MBF1
MBF2
OR
O
O
O
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. MBF2
is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by a
reset.
Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and
reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during
the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.
Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to reset
the read pointer to the beginning retransmit location and output the first selected retransmit data.
RFM
RST
I
I
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.
Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high
transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected
word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low, taking the FIFO
out of retransmit mode.
RTM
I
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high.
W/RA
W/RB
I
I
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a
low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is low.
detailed description
reset
The SN54ACT3641 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset
initializes the memory read and write pointers and forces the IR flag low, the OR flag low, the AE flag low, and
the AF flag high. Resetting the device also forces the mailbox flags (MBF1, MBF2) high. After a FIFO is reset,
its IR flag is set high after at least two clock cycles to begin normal operation. A FIFO must be reset after power
up before data is written to its memory.
almost-empty flag and almost-full flag offset programming
Two registers in the SN54ACT3641 are used to hold the offset values for the AE and AF flags. The AE flag offset
register is labeled X, and the AF flag offset register is labeled Y. The offset registers can be loaded with a value
in three ways: one of two preset values are loaded into the offset registers, parallel load from port A, or serial
load. The offset register programming mode is chosen by the flag select (FS1, FS0) inputs during a low-to-high
transition on RST (see Table 1).
Table 1. Flag Programming
†
FS1
H
FS0
H
RST
X AND Y REGISTERS
↑
↑
↑
↑
Serial load
H
L
64
8
L
H
L
L
Parallel load from port A
†
X register holds the offset for AE; Y register holds the
offset for AF.
preset values
If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of an RST low-to-high transition according to
Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is
necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.
parallel load from port A
To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high
transition of RST. After this reset is complete, IR is set high after two low-to-high transitions on CLKA. The first
two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offset
register of the SN54ACT3641 uses port-A inputs (A9–A0). Data input A9 is used as the most-significant bit of
the binary number. Each register value can be programmed from 1 to 1020. After both offset registers are
programmed from port A, subsequent FIFO writes store data in the SRAM.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
serial load
To program the X and Y registers serially, the device is reset with FS0/SD and FS1/SEN high during the
low-to-high transition of RST. After this reset is complete, the X-and Y-register values are loaded bitwise through
FS0/SD on each low-to-high transition of CLKA that FS1/SEN is low. Twenty-bit writes are needed to complete
the programming. The first bit write stores the most-significant bit of the Y register, and the last bit write stores
the least-significant bit of the the X register. Each register value can be programmed from 1 to 1020.
When the option is chosen to program the offset registers serially, IR remains low until all 20 bits are written.
IR is set high by the low-to-high transition of CLKA after the last bit is loaded to allow normal FIFO operation.
FIFO write/read operation
The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0–A35 outputs are active when both CSA and W/RA are low.
Data is loaded into the FIFO from the A0–A35 inputs on a low-to-high transition of CLKA when CSA and the
port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the IR flag are high (see Table 2).
Writes to the FIFO are independent of any concurrent FIFO reads.
Table 2. Port-A Enable Function Table
CSA W/RA ENA
MBA CLKA
A0–A35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, mail2 register
Active, mail2 register
Active, mail2 register
Active, mail2 register
PORT FUNCTION
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
None
None
FIFO write
Mail1 write
None
H
H
L
H
L
↑
X
↑
L
H
L
L
None
L
H
H
X
↑
None
L
H
Mail2 read (set MBF2 high)
The port-B control signals are identical to those of port A with the exception that the port-B write/read select
(W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0–B35) outputs is
controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0–B35 outputs are
in the high-impedance state when either CSB is high or W/RB is low. The B0–B35 outputs are active when CSB
is low and W/RB is high.
Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB and the port-B
mailbox select (MBB) are low, W/RB, the port-B enable (ENB), and the OR flag are high (see Table 3). Reads
from the FIFO are independent of any concurrent FIFO writes.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
FIFO write/read operation (continued)
Table 3. Port-B Enable Function Table
CSB W/RB ENB
MBB CLKB
B0–B35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO output register
Active, FIFO output register
Active, mail1 register
PORT FUNCTION
H
L
L
L
L
L
L
L
X
L
X
L
X
X
L
X
X
↑
None
None
None
L
H
H
L
L
H
L
↑
Mail2 write
None
H
H
H
H
X
↑
H
L
L
FIFO read
H
H
X
↑
None
H
Active, mail1 register
Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select can change states during the
setup- and hold-time window of the cycle.
When OR is low, the next data word is sent to the FIFO output register automatically by the CLKB low-to-high
transition that sets the flag high. When OR is high, an available data word is clocked to the FIFO output register
only when a FIFO read is selected by the port-B chip select (CSB), write/read select (W/RB), enable (ENB), and
mailbox select (MBB).
synchronized FIFO flags
Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve the flags’
reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate
asynchronously to one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA.
Table 4 shows the relationship of each flag to the number of words stored in memory.
Table 4. FIFO Flag Operation
SYNCHRONIZED
TO CLKB
SYNCHRONIZED
TO CLKA
NUMBER OF WORDS IN
†‡
FIFO
OR
L
AE
L
AF
H
H
H
L
IR
H
H
H
H
L
0
1 to X
(X + 1) to [1024 – (Y + 1)]
(1024 – Y) to 1023
1024
H
L
H
H
H
H
H
H
L
†
‡
X is the almost-empty offset for AE. Y is the almost-full offset for AF.
When a word is present in the FIFO output register, its previous memory
location is free.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
output-ready flag (OR)
The OR flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). When the OR
flag is high, new data is present in the FIFO output register. When OR is low, the previous data word is present
in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine
that controls an OR flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO
SRAM status is empty, empty+1, or empty+2. From the time a word is written to a FIFO, it can be shifted to the
FIFO output register in a minimum of three cycles of CLKB; therefore, an OR flag is low if a word in memory
is the next data to be sent to the FIFO output register and three CLKB cycles have not elapsed since the time
the word was written. The OR flag of the FIFO remains low until the third low-to-high transition of CLKB occurs,
simultaneously forcing OR high and shifting the word to the FIFO output register.
A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition
occurs at time t
synchronization cycle (see Figure 6).
, or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first
sk(1)
input-ready flag (IR)
The IR flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). When IR is high, a
memory location is free in the SRAM to write new data. No memory locations are free when the IR flag is low
and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an IR
flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full,
full–1, or full–2. From the time a word is read from a FIFO, its previous memory location is ready to be written
in a minimum of three cycles of CLKA. Therefore, IR is low if less than two cycles of CLKA have elapsed since
the next memory write location has been read. The second low-to-high transition on CLKA after the read sets
IR high, and data can be written in the following cycle.
A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition
occurs at time t
synchronization cycle (see Figure 7).
, or greater, after the read. Otherwise, the subsequent CLKA cycle can be the first
sk(1)
almost-empty flag (AE)
The AE flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). The state machine
that controls an AE flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO
SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is defined by the
contents of register X. This register is loaded with a preset value during a FIFO reset, programmed from port
A, or programmed serially (see almost-empty flag and almost-full flag offset programming). AE is low when the
FIFO contains X or fewer words and is high when the FIFO contains (X + 1) or more words. A data word present
in the FIFO output register has been read from memory.
Two low-to-high transitions of CLKB are required after a FIFO write for the AE flag to reflect the new level of
fill. Therefore, the AE flag of a FIFO containing (X + 1) or more words remains low if two cycles of CLKB have
not elapsed since the write that filled the memory to the (X + 1) level. AE is set high by the second low-to-high
transition of CLKB after the FIFO write that fills memory to the (X
A low-to-high transition of CLKB begins the first synchronization cycle if it occurs at time t
+
1) level.
, or greater, after
sk(2)
the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first
synchronization cycle (see Figure 8).
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
almost-full flag (AF)
The AF flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). The state machine
that controls an AF flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO
SRAM status is almost full, almost full–1, or almost full–2. The almost-full state is defined by the contents of
register Y. This register is loaded with a preset value during a FIFO reset, programmed from port A, or
programmed serially (see almost-empty flag and almost-full flag offset programming). AF is low when the
number of words in the FIFO is greater than or equal to (1024 – Y). AF is high when the number of words in the
FIFO is less than or equal to [1024 – (Y + 1)]. A data word present in the FIFO output register has been read
from memory.
Two low-to-high transitions of CLKA are required after a FIFO read for its AF flag to reflect the new level of fill.
Therefore, the AF flag of a FIFO containing [1024 – (Y + 1)] or fewer words remains low if two cycles of CLKA
have not elapsed since the read that reduced the number of words in memory to [1024 – (Y + 1)]. AF is set high
by the second low-to-high transition of CLKA after the FIFO read that reduces the number of words in memory
to [1024 – (Y + 1)]. A low-to-high transition of CLKA begins the first synchronization cycle if it occurs at time
t
, or greater, after the read that reduces the number of words in memory to [1024 – (Y + 1)]. Otherwise, the
sk(2)
subsequent CLKA cycle can be the first synchronization cycle (see Figure 9).
synchronous retransmit
The synchronous-retransmit feature of the SN54ACT3641 allows FIFO data to be read repeatedly, starting at
a user-selected position. First the FIFO is put into retransmit mode to select a beginning word and prevent
ongoing FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three
words can retransmit repeatedly starting at the selected word. The FIFO can be taken out of retransmit mode
at any time and allow normal device operation.
The FIFO is put in retransmit mode by a low-to-high transition on CLKB when the retransmit-mode (RTM) input
is high and OR is high. This rising CLKB edge marks the data present in the FIFO output register as the first
retransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low.
When two or more reads have been done, past the initial retransmit word, a retransmit is initiated by a
low-to-high transition on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the
first retransmit word to the FIFO output register and subsequent reads can begin immediately. Retransmit loops
can be done endlessly while the FIFO is in retransmit mode. RFM must be low during the CLKB rising edge that
takes the FIFO out of retransmit mode.
When the FIFO is put into retransmit mode, it operates with two read pointers. The current read pointer operates
normally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE
flags. The shadow read pointer stores the SRAM location at the time the device is put into retransmit mode and
does not change until the device is taken out of retransmit mode. The shadow read pointer is used by the IR
and AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write that
stores (102 – Y) words after the first retransmit word. The IR flag is set low by the 1024th write after the first
retransmit word.
When the FIFO is in retransmit mode and RFM is high, a rising CLKB edge loads the current read pointer with
theshadowread-pointervalueandtheORflagreflectsthenewleveloffillimmediately. Iftheretransmitchanges
the FIFO status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle are
needed to switch AE high (see Figure 11). The rising CLKB edge that takes the FIFO out of retransmit mode
shifts the read pointer used by the IR and AF flags from the shadow to the current read pointer. If the change
of read pointer used by IR and AF should cause one or both flags to transition high, at least two CLKA
synchronizing cycles are needed before the flags reflect the change. A rising CLKA edge after the FIFO is taken
out of retransmit mode is the first synchronizing cycle of IR if it occurs at time t
, or greater, after the rising
sk(1)
CLKB edge (see Figure 12). A rising CLKA edge after the FIFO is taken out of retransmit mode is the first
synchronizing cycle of AF if it occurs at time t , or greater, after the rising CLKB edge (see Figure 14).
sk(2)
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
mailbox registers
Two36-bitbypassregistersareontheSN54ACT3641topasscommandandcontrol information between portA
and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data
transferoperation. Alow-to-hightransitiononCLKAwritesA0–A35 data to the mail1 register when a portAwrite
is selected by CSA, W/RA, and ENA with MBA high. A low-to-high transition on CLKB writes B0–B35 data to
the mail2 register when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail
register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while
its mail flag is low.
When the port-B data (B0–B35) outputs are active, the data on the bus comes from the FIFO output register
when the port-B mailbox select (MBB) input is low and from the mail1 register when MBB is high. Mail2 data
is always present on the port-A data (A0–A35) outputs when they are active. The mail1 register flag (MBF1)
is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB with
MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read
is selected by CSA, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is read
and changes only when new data is written to the register.
CLKA
t
h(RS)
CLKB
t
h(FS)
t
su(RS)
t
su(FS)
RST
FS1, FS0
0,1
t
t
pd(C-IR)
pd(C-IR)
IR
OR
AE
AF
t
pd(C-OR)
t
pd(R-F)
t
pd(R-F)
pd(R-F)
t
MBF1,
MBF2
Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
CLKA
RST
4
t
su(FS)
t
h(FS)
FS1, FS0
t
pd(C-IR)
IR
ENA
t
h(EN1)
t
su(EN1)
t
h(D)
t
su(D)
A0–A35
AF Offset
(Y)
AE Offset First Word Stored in FIFO
(X)
NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.
Figure 2. Programming the AF Flag and AE Flag Offset Values From Port A
CLKA
RST
4
t
pd(C-IR)
IR
FS1/SEN
FS0/SD
t
t
t
t
t
h(SP)
h(SEN)
h(SEN)
t
t
su(SEN)
su(FS)
t
su(SEN)
h(SD)
h(SD)
t
su(FS)
t
t
t
su(SD)
h(FS)
su(SD)
AF Offset
(Y) MSB
AE Offset
(X) LSB
NOTE B: It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set high.
Figure 3. Programming the AF Flag and AE Flag Offset Values Serially
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
IR
High
t
t
t
su(EN2)
h(EN2)
CSA
t
t
su(EN2)
h(EN2)
W/RA
MBA
ENA
t
t
su(EN2)
h(EN2)
t
t
h(EN1)
h(EN1)
t
t
t
t
su(EN1)
h(EN1)
su(EN1)
su(EN1)
t
su(D)
h(D)
A0–A35
No Operation
W1
W2
Figure 4. FIFO Write-Cycle Timing
t
c
t
t
w(CLKH)
w(CLKL)
CLKB
OR High
CSB
W/RB
MBB
t
t
t
su(EN1)
su(EN1)
su(EN1)
t
t
t
h(EN1)
h(EN1)
h(EN1)
ENB
No
Operation
t
pd(M-DV)
t
t
a
dis
t
a
t
en
W1
W2
W3
B0–B35
Figure 5. FIFO Read-Cycle Timing
13
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
Low
CSA
W/RA
High
t
su(EN2)
t
h(EN2)
MBA
ENA
t
su(EN1)
t
h(EN1)
High
IR
t
su(D)
t
h(D)
A0–A35
W1
t
t
c
†
t
sk(1)
w(CLKL)
t
w(CLKH)
1
2
t
3
CLKB
OR
t
pd(C-OR)
pd(C-OR)
Old Data in FIFO Output Register
CSB Low
W/RB
High
MBB Low
ENB
t
t
h(EN1)
su(EN1)
t
a
B0–B35
W1
Old Data in FIFO Output Register
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition high and to clock the next word to the
sk(1)
FIFO output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
of OR high and the first word load to the output register can occur one CLKB cycle later than shown.
, the transition
sk(1)
Figure 6. OR-Flag Timing and First Data-Word Fall Through When the FIFO Is Empty
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKB
Low
CSB
W/RB
MBB
High
Low
t
t
h(EN1)
su(EN1)
ENB
OR
High
t
a
B0–B35
FIFO Output Register
Next Word From FIFO
†
t
sk(1)
t
c
t
t
w(CLKL)
w(CLKH)
1
2
CLKA
IR
t
t
pd(C-IR)
pd(C-IR)
FIFO Full
CSA
W/RA
MBA
Low
High
t
t
t
h(EN2)
su(EN2)
t
su(EN1)
h(EN1)
ENA
t
t
su(D)
h(D)
Write
A0–A35
†
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time
sk(1)
between the rising CLKB edge and rising CLKA edge is less than t
, IR can transition high one CLKA cycle later than shown.
sk(1)
Figure 7. IR-Flag Timing and First Available Write When the FIFO Is Full
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
CLKA
t
h(EN1)
t
su(EN1)
ENA
†
t
sk(2)
CLKB
AE
1
2
t
t
pd(C-AE)
pd(C-AE)
X Words in FIFO
(X + 1) Words in FIFO
t
h(EN1)
t
su(EN1)
ENB
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time
sk(2)
between the rising CLKA edge and rising CLKB edge is less than t
, AE can transition high one CLKB cycle later than shown.
sk(2)
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)
Figure 8. Timing for AE When FIFO Is Almost Empty
‡
t
sk(2)
CLKA
ENA
1
2
t
h(EN1)
t
su(EN1)
t
t
pd(C-AF)
pd(C-AF)
(1024 – Y) Words in FIFO
AF
[1024 – (Y + 1)] Words in FIFO
CLKB
ENB
t
h(EN1)
t
su(EN1)
‡
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time
sk(2)
between the rising CLKB edge and rising CLKA edge is less than t
, AF can transition high one CLKA cycle later than shown.
sk(2)
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)
Figure 9. Timing for AF When FIFO Is Almost Full
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
CLKB
ENB
t
t
t
su(EN1)
h(EN1)
t
t
h(RM)
t
su(RM)
su(RM)
h(RM)
RTM
RFM
t
t
h(RM)
su(RM)
OR
High
t
a
t
a
t
a
t
a
B0–B35
W0
W1
W2
W0
W1
Initiate Retransmit Mode
With W0 as First Word
Retransmit From
Selected Position
End Retransmit
Mode
NOTE A: CSB= L, W/RB=H, MBB=L. NoinputenablesotherthanRTMandRFMareneededtocontrolretransmitmodeorbeginaretransmit.
Other enables are shown only to relate retransmit operations to the FIFO output register.
Figure 10. Retransmit Timing Showing Minimum Retransmit Length
CLKB
RTM
1
2
High
t
h(RM)
t
su(RM)
RFM
AE
t
pd(C-AE)
X or Fewer Words From Empty
(X + 1) or More Words From Empty
NOTE A: X is the value loaded in the AE flag offset register.
Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
†
t
sk(1)
CLKA
IR
1
2
t
pd(C-IR)
FIFO Filled to First Retransmit Word
One or More Write Locations Available
CLKB
t
t
h(RM)
su(RM)
RTM
†
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time
sk(1)
between the rising CLKB edge and rising CLKA edge is less than t
, IR can transition high one CLKA cycle later than shown.
sk(1)
Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Available
‡
t
sk(2)
CLKA
AF
1
2
t
pd(C-AE)
(1024 – Y) or More Words Past First Retransmit Word
(Y + 1) or More Write Locations Available
CLKB
t
t
h(RM)
su(RM)
RTM
‡
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition high in the next CLKA cycle. If the time
sk(2)
between the rising CLKB edge and rising CLKA edge is less than t
, AF can transition high one CLKA cycle later than shown.
sk(2)
NOTE A: Y is the value loaded in the AF flag offset register.
Figure 13. AF Timing From the End of Retransmit Mode When (Y + 1)
or More Write Locations Are Available
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
CLKA
t
h(EN2)
t
su(EN2)
CSA
W/RA
MBA
ENA
t
h(D)
t
su(D)
A0–A35
W1
CLKB
MBF1
t
t
pd(C-MF)
pd(C-MF)
CSB
W/RB
MBB
ENB
t
h(EN1)
t
su(EN1)
t
pd(M-DV)
t
dis
t
en
t
pd(C-MR)
B0–B35
W1 (remains valid in mail1 register after read)
FIFO Output Register
Figure 14. Timing for Mail1 Register and MBF1 Flag
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
CLKB
t
h(EN2)
t
su(EN2)
CSB
W/RB
MBB
ENB
t
h(D)
t
su(D)
B0–B35
W1
CLKA
MBF2
t
t
pd(C-MF)
pd(C-MF)
CSA
W/RA
MBA
ENA
t
h(EN1)
t
su(EN1)
t
t
en
dis
t
pd(C-MR)
A0–A35
W1 (remains valid in mail2 register after read)
Figure 15. Timing for Mail2 Register and MBF2 Flag
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Storage temperature range, T
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
CC
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
recommended operating conditions
MIN
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
IH
0.8
–4
8
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–55
125
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
= –4 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I
I
2.4
OH
CC
CC
CC
CC
CC
OH
= 8 mA
0.5
±5
V
OL
OL
I
I
I
V = V
or 0
µA
µA
µA
I
I
CC
V
= V
or 0
±5
OZ
CC
O
CC
§
V = V
– 0.2 V or 0
CSA = V
CSB = V
CSA = V
CSB = V
400
I
CC
A0–A35
B0–B35
A0–A35
B0–B35
0
0
IH
IH
IL
IL
V
CC
= 5.5 V, One input at 3.4 V,
¶
∆I
CC
1
1
1
mA
Other inputs at V
or GND
CC
All other inputs
C
C
V = 0,
f = 1 MHz
f = 1 MHz
4
8
pF
pF
i
I
V
O
= 0,
o
‡
§
¶
All typical values are at V
= 5 V, T = 25°C.
A
CC
is measured in the A to B direction.
I
CC
This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
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SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 16)
MIN
MAX
UNIT
MHz
ns
f
t
t
t
t
t
Clock frequency, CLKA or CLKB
50
clock
Clock cycle time, CLKA or CLKB
20
8
c
Pulse duration, CLKA and CLKB high
Pulse duration, CLKA and CLKB low
ns
w(CH)
w(CL)
su(D)
su(EN1)
8
ns
Setup time, A0–A35 before CLKA↑ and B0–B35 before CLKB↑
Setup time, ENA to CLKA↑; ENB to CLKB↑
6
ns
6
ns
7.5
Setup time, CSA, W/RA, and MBA to CLKA↑; CSB, W/RB, and MBB to CLKB↑
t
ns
su(EN2)
9
6.5
6
W/RA to CLKA↑
t
t
t
t
t
t
t
Setup time, RTM and RFM to CLKB↑
ns
ns
ns
ns
ns
ns
ns
su(RM)
su(RS)
su(FS)
†
Setup time, RST low before CLKA↑ or CLKB↑
Setup time, FS0 and FS1 before RST high
Setup time, FS0/SD before CLKA↑
10
6
‡
su(SD)
‡
Setup time, FS1/SEN before CLKA↑
6
su(SEN)
h(D)
Hold time, A0–A35 after CLKA↑ and B0–B35 after CLKB↑
Hold time, ENA after CLKA↑; ENB after CLKB↑
0
0
n(EN1)
Hold time, CSA, W/RA, and MBA after CLKA↑;
CSB, W/RB, and MBB after CLKB↑
t
0
ns
n(EN2)
t
t
t
t
t
t
t
t
Hold time, RTM and RFM after CLKB↑
0
6
ns
ns
ns
ns
ns
ns
ns
ns
n(RM)
h(RS)
h(FS)
†
Hold time, RST low after CLKA↑ or CLKB↑
Hold time, FS0 and FS1 after RST high
Hold time, FS1/SEN high after RST high
Hold time, FS0/SD after CLKA↑
0
‡
0
h(SP)
‡
0
h(SD)
‡
Hold time, FS1/SEN after CLKA↑
0
h(SEN)
§
Skew time between CLKA↑ and CLKB↑ for OR and IR
Skew time between CLKA↑ and CLKB↑ for AE and AF
11
16
sk(1)
§
sk(2)
†
‡
§
Requirement to count the clock edge as one of at least four needed to reset a FIFO
Applies only when serial load method is used to program flag offset registers
Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
22
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1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 30 pF (see Figures 1 through 16)
L
PARAMETER
MIN
50
3
MAX
UNIT
MHz
ns
f
t
t
t
t
t
max
Access time, CLKB↑ to B0–B35
15
10
10
10
10
a
Propagation delay time, CLKA↑ to IR
Propagation delay time, CLKB↑ to OR
Propagation delay time, CLKB↑ to AE
Propagation delay time, CLKA↑ to AF
1
ns
pd(C-IR)
pd(C-OR)
pd(C-AE)
pd(C-AF)
1
ns
1
ns
1
ns
Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and
CLKB↑ to MBF2 low or MBF1 high
t
0
10
ns
pd(C-MF)
†
‡
t
t
t
Propagation delay time, CLKA↑ to B0–B35 and CLKB↑ to A0–A35
3
3
1
15
15
20
ns
ns
ns
pd(C-MR)
pd(M-DV)
pd(R-F)
Propagation delay time, MBB to B0–B35 valid
Propagation delay time, RST low to AE low and AF high
Enable time, CSA and W/RA low to A0–A35 active and
CSB low and W/RB high to B0–B35 active
t
2
1
13
10
ns
ns
en
Disable time, CSA or W/RA high to A0–A35 at high impedance and
CSB high or W/RB low to B0–B35 at high impedance
t
dis
†
‡
Writing data to the mail1 register when the B0–B35 outputs are active and MBB is high
Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
I
OL
Output
Under Test
V
Load
C
L
(see Note A)
I
OH
LOAD CIRCUIT
3 V
3 V
Timing
Input
High-Level
Input
1.5 V
1.5 V
1.5 V
1.5 V
GND
GND
3 V
t
t
w
h
t
su
Data,
Enable
Input
3 V
1.5 V
1.5 V
Low-Level
Input
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
GND
t
t
PLZ
PZL
≈ 3 V
3 V
Low-Level
Output
1.5 V
1.5 V
1.5 V
Input
V
V
+ 300mV
– 300mV
OL
V
V
OL
GND
t
PZH
t
t
pd
pd
OH
OH
High-Level
Output
V
V
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
≈ 0 V
OL
t
PHZ
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. Includes probe and jig capacitance
B.
C.
t
t
and t
and t
are the same as t
.
en
PZL
PLZ
PZH
PHZ
are the same as t
.
dis
CONDITIONS FOR LOAD CIRCUIT
†
C
L
PARAMETER
I
I
V
Load
OL
OH
(typical)
t
t
t
t
4 mA
4 mA
4 mA
4 mA
8 mA
8 mA
8 mA
8 mA
0 V
3 V
0 V
3 V
20 pF
PZH
PZL
PHZ
PLZ
20 pF
20 pF
20 pF
t
8 mA
4 mA
1.5 V
20 pF
PD
†
Includes probe and test-fixture capacitance
Figure 16. Load Circuit and Voltage Waveforms
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309A – AUGUST 1995 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250
200
150
100
50
f
T
C
= 1/2 f
clock
data
A
L
V
CC
= 5.5 V
= 25°C
= 0 pF
V
CC
= 5 V
V
CC
= 4.5 V
0
0
10
20
30
40
50
60
70
f
– Clock Frequency – MHz
clock
Figure 17
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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