SN54ALVTH16601_08 [TI]
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS;
| 型号： | SN54ALVTH16601_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 输出元件 |
| 文件： | 总12页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
SN54ALVTH16601 . . . WD PACKAGE
SN74ALVTH16601 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
CLKENAB
CLKAB
B1
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus Design for
2.5-V and 3.3-V Operation and Low
Static-Power Dissipation
2
3
4
GND
A2
GND
B2
5
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
6
A3
B3
7
V
V
B4
CC
A4
CC
3.6-V V
)
8
CC
9
A5
A6
B5
B6
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
= 3.3 V, T = 25°C
A
GND
A7
A8
GND
B7
B8
High-Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V
)
CC
I
and Power-Up 3-State Support Hot
off
A9
B9
Insertion
A10
A11
A12
GND
A13
A14
A15
B10
B11
B12
GND
B13
B14
B15
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
+ 0.5 V
CC
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
V
V
CC
CC
A16
A17
GND
A18
OEBA
LEBA
B16
B17
GND
B18
CLKBA
CLKENBA
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR and
the DGVR package is abbreviated to VR.
description
The ’ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V V operation, but
CC
with the capability to provide a TTL interface to a 5-V system environment.
The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked
modes.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UBT and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
description (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is
low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
When V
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16601 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH16601 is characterized for operation from –40°C to 85°C.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
CLKAB
A
X
L
CLKENAB OEAB
LEAB
X
X
X
H
H
L
H
L
L
L
L
L
L
L
X
H
H
L
X
Z
L
X
X
H
X
X
L
H
‡
‡
X
B
B
0
0
L
X
L
↑
↑
L
L
L
H
X
H
‡
B
0
L
L
L or H
†
‡
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
Output level before the indicated steady-state input conditions were
established
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
logic diagram (positive logic)
1
OEAB
56
CLKENAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
29
CLKENBA
27
OEBA
CE
3
A1
54
1D
C1
B1
CLK
CE
1D
C1
CLK
To 17 Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V (see Note 1) . . . . . . . . . –0.5 V to 7 V
O
Output current in the low state, I : SN54ALVTH16601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ALVTH16601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Output current in the high state, I : SN54ALVTH16601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA
O
SN74ALVTH16601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions, V
= 2.5 V ± 0.2 V (see Note 3)
CC
SN54ALVTH16601
SN74ALVTH16601
UNIT
MIN
2.3
TYP
MAX
MIN
2.3
TYP
MAX
V
V
V
V
Supply voltage
2.7
2.7
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
1.7
1.7
0.7
5.5
–6
6
0.7
5.5
–8
8
V
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
18
10
24
10
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
recommended operating conditions, V
= 3.3 V ± 0.3 V (see Note 3)
CC
SN54ALVTH16601
SN74ALVTH16601
UNIT
MIN
3
TYP
MAX
MIN
3
TYP
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
2
2
0.8
5.5
–24
24
0.8
5.5
–32
32
V
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
48
64
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
10
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted)
CC
SN54ALVTH16601
SN74ALVTH16601
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 2.3 V to 2.7 V,
I
I
I
I
I
I
I
I
I
= –100 µA
= –6 mA
= –8 mA
= 100 µA
= 6 mA
V
–0.2
CC
1.8
V
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
CC
V
OH
V
V
= 2.3 V
CC
1.8
= 2.3 V to 2.7 V,
0.2
0.4
0.2
0.4
CC
V
V
= 8 mA
V
V
OL
V
CC
= 2.3 V
= 2.7 V
= 18 mA
= 24 mA
0.5
0.5
= 1 mA,
O
I
‡
V
CC
0.55
0.55
RST
V = V
or GND
CC
CC
V
V
= 2.7 V,
V = V
or GND
±1
10
10
1
±1
10
CC
I
Control inputs
A or B ports
= 0 or 2.7 V,
V = 5.5 V
I
CC
I
I
V = 5.5 V
I
10
µA
V
CC
= 2.7 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
§
= 2.3 V,
= 2.3 V,
= 2.7 V,
= 2.7 V,
= 2.3 V,
V = 0.7 V
I
115
–10
115
–10
BHL
¶
V = 1.7 V
I
BHH
#
V = 0 to V
300
–300
300
–300
BHLO
I
CC
CC
||
V = 0 to V
I
BHHO
EX
V
O
= 5.5 V
125
125
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
I
OZ(PU/PD)
CC
V = GND or V , OE = don’t care
I
Outputs high
Outputs low
0.04
2.5
0.04
3
0.1
4.5
0.1
0.04
2.5
0.04
3
0.1
4.5
0.1
V
I
= 2.7 V,
= 0,
CC
O
I
mA
V = V
I
or GND
CC
Outputs disabled
C
C
V
V
= 2.5 V,
= 2.5 V,
V = 2.5 V or 0
I
pF
pF
i
CC
V
O
= 2.5 V or 0
7
7
io
CC
†
‡
§
All typical values are at V
Data must not be loaded into the flip-flops/latches after applying power.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
= 2.5 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
IN
IL
BHL
¶
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
High-impedance state during power up or power down
O
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted)
V
CC
SN54ALVTH16601
SN74ALVTH16601
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 3 V to 3.6 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –24 mA
= –32 mA
= 100 µA
= 16 mA
= 24 mA
= 32 mA
= 48 mA
= 64 mA
V
CC
–0.2
2
V
CC
–0.2
2
CC
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
V
OH
V
V
= 3 V
CC
= 3 V to 3.6 V,
0.2
0.5
0.2
0.4
CC
V
V
OL
V
CC
= 3 V
0.5
0.55
0.55
0.55
= 1 mA,
O
‡
V
CC
= 3.6 V
0.55
V
RST
V = V
or GND
I
CC
V
V
= 3.6 V,
V = V
or GND
±1
10
10
1
±1
10
CC
I
CC
Control inputs
A or B ports
= 0 or 3.6 V,
V = 5.5 V
I
CC
I
I
V = 5.5 V
I
10
µA
V
CC
= 3.6 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
§
= 3 V,
= 3 V,
= 3.6 V,
= 3.6 V,
= 3 V,
V = 0.8 V
I
75
75
BHL
¶
V = 2 V
I
–75
500
–75
500
BHH
#
V = 0 to V
BHLO
I
CC
CC
||
V = 0 to V
I
–500
–500
BHHO
EX
V
O
= 5.5 V
125
125
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
mA
mA
I
OZ(PU/PD)
CC
V = GND or V , OE = don’t care
I
Outputs high
Outputs low
0.06
3.5
0.1
5
0.06
3.5
0.1
5
V
I
= 3.6 V,
= 0,
CC
O
I
V = V
I
or GND
CC
Outputs disabled
0.06
0.1
0.06
0.1
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
0.4
0.4
∆I
CC
◊
or GND
CC
C
C
V
V
= 3.3 V,
= 3.3 V,
V = 3.3 V or 0
3
7
3
7
pF
pF
i
CC
I
V
O
= 3.3 V or 0
io
CC
†
‡
§
All typical values are at V
Data must not be loaded into the flip-flops/latches after applying power.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
= 3.3 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
IN
IL
BHL
¶
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
High-impedance state during power up or power down
O
CC
◊ This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V ± 0.2 V
CC
SN54ALVTH16601 SN74ALVTH16601
UNIT
MHz
ns
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
150
150
clock
LE high
1.8
2.3
4
1.8
2.3
4
w
CLK high or low
Data high
Data low
CLK high
CLK low
Data high
Data low
Data high
Data low
A or B before CLK↑
A or B before LE↓
5.2
0.7
0.9
1.7
2.3
0.5
0.5
5.2
0.7
0.9
1.7
2.3
0.5
0.5
t
su
Setup time
ns
CLKEN before CLK↑
A or B after CLK↑
A or B after LE↓
CLK high
CLK low
2.3
2.4
2.3
2.4
t
h
Hold time
ns
Data high
Data low
0.5
0.5
0.5
0.5
CLKEN after CLK↑
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 2)
= 3.3 V ± 0.3 V
CC
SN54ALVTH16601 SN74ALVTH16601
UNIT
MHz
ns
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
150
150
clock
LE high
1.8
2.3
2.4
3.8
1
1.8
2.3
2.4
3.8
1
w
CLK high or low
Data high
Data low
CLK high
CLK low
Data high
Data low
Data high
Data low
A or B before CLK↑
A or B before LE↓
t
su
Setup time
ns
0.6
1.4
1.9
0.5
0.5
0.6
1.4
1.9
0.5
0.5
CLKEN before CLK↑
A or B after CLK↑
A or B after LE↓
CLK high
CLK low
2
2
t
h
Hold time
ns
2.3
2.3
Data high
Data low
0.6
0.5
0.6
0.5
CLKEN after CLK↑
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
switching characteristics over recommended operating free-air temperature range, C = 30 pF,
L
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
SN54ALVTH16601 SN74ALVTH16601
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
150
1.1
1.6
2.1
2.4
2
MAX
MIN
150
1.1
1.6
2.1
2.4
2
MAX
f
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
4.1
4.8
5
4.1
4.8
5
A or B
A or B
A or B
A or B
A or B
B or A
ns
ns
ns
ns
LEBA or LEAB
CLKBA or CLKAB
OEBA or OEAB
OEBA or OEAB
5.4
5
5.4
5
2.5
1.2
1
5.9
4.8
4.6
5.2
3.9
2.5
1.2
1
5.9
4.8
4.6
5.2
3.9
1.2
1
1.2
1
switching characteristics over recommended operating free-air temperature range, C = 50 pF,
L
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
CC
SN54ALVTH16601 SN74ALVTH16601
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
150
1.4
1.1
2
MAX
MIN
150
1.4
1.1
2
MAX
f
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
3.9
3.9
4.6
4.6
4.5
4.6
4.2
4.4
5.3
4.6
3.9
3.9
4.6
4.6
4.5
4.6
4.2
4.4
5.3
4.6
A or B
A or B
A or B
A or B
A or B
B or A
ns
ns
ns
ns
LEBA or LEAB
CLKBA or CLKAB
OEBA or OEAB
OEBA or OEAB
2.1
1.9
2.2
1
2.1
1.9
2.2
1
1
1
1.8
1.7
1.8
1.7
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
6 V
S1
Open
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
6 V
PLH PHL
/t
C
= 50 pF
t
L
PLZ PZL
500 Ω
(see Note A)
/t
GND
PHZ PZH
LOAD CIRCUIT
t
w
3 V
0 V
3 V
0 V
1.5 V
Input
1.5 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
Data
Input
3 V
0 V
1.5 V
1.5 V
1.5 V
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
S1 at 6 V
3 V
V
3 V
0 V
1.5 V
1.5 V
1.5 V
Input
V
V
+ 0.3 V
OL
(see Note B)
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
SN54ALVTH16827W
ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, CDFP56, 0.380 INCH, FINE PITCH, CERAMIC, FP-56
TI
SN54ALVTH16841WD
ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, CDFP56, 0.380 INCH, FINE PITCH, CERAMIC, FP-56
TI
SN54ALVTH16841WDR
ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, CDFP56, 0.380 INCH, FINE PITCH, CERAMIC, FP-56
TI
©2020 ICPDF网 联系我们和版权申明