SN54HC161-SP [TI]
同步 4 位二进制计数器;
| 型号： | SN54HC161-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 同步 4 位二进制计数器 计数器 |
| 文件： | 总33页 (文件大小：1481K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢆ
ꢃ ꢊꢋꢌ ꢍ ꢀꢎ ꢁꢅꢄꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁꢒꢏꢎ ꢅꢐ ꢑ ꢁꢍ ꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
D
D
D
D
D
Low Input Current of 1 µA Max
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Low Power Consumption, 80-µA Max I
CC
Typical t = 14 ns
pd
4-mA Output Drive at 5 V
Synchronously Programmable
SN54HC161 . . . J OR W PACKAGE
SN74HC161 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54HC161 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
V
CC
RCO
3
2
1
20 19
18
A
B
Q
Q
4
5
6
7
8
A
B
Q
Q
Q
Q
A
B
C
D
17
16
15
14
B
C
D
NC
C
NC
Q
Q
C
D
D
ENP
GND
ENT
LOAD
9 10 11 12 13
NC − No internal connection
description/ordering information
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. The ’HC161 devices are 4-bit binary counters. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed
by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output
counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK)
input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC161N
SN74HC161N
SN74HC161D
SN74HC161DR
SN74HC161DT
SN74HC161NSR
SN74HC161PW
SN74HC161PWR
SN74HC161PWT
SNJ54HC161J
SNJ54HC161W
SNJ54HC161FK
SOIC − D
SOP − NS
HC161
HC161
−40°C to 85°C
TSSOP − PW
HC161
CDIP − J
CFP − W
LCCC − FK
SNJ54HC161J
SNJ54HC161W
SNJ54HC161FK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢐ ꢗ ꢢ ꢚ ꢙꢥ ꢠꢟ ꢝꢞ ꢟꢙ ꢛꢢ ꢤꢖ ꢜꢗ ꢝ ꢝꢙ ꢬꢌ ꢭꢊ ꢔꢏ ꢮ ꢊꢯꢰꢂ ꢯꢂꢈ ꢜꢤꢤ ꢢꢜ ꢚ ꢜ ꢛꢡ ꢝꢡꢚ ꢞ ꢜ ꢚ ꢡ ꢝꢡ ꢞꢝꢡ ꢥ
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ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢆ ꢇ ꢆ
ꢃꢊ ꢋꢌ ꢍ ꢀꢎ ꢁꢅ ꢄ ꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁ ꢒꢏꢎ ꢅꢐ ꢑꢁ ꢍꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
description/ordering information (continued)
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’HC161 devices is asynchronous. A low level at the clear (CLR) input sets all four of
the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
2
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢆ
ꢃ ꢊꢋꢌ ꢍ ꢀꢎ ꢁꢅꢄꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁꢒꢏꢎ ꢅꢐ ꢑ ꢁꢍ ꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
9
LOAD
10
ENT
15
RCO
†
LD
7
ENP
†
CK
2
CLK
CK
LD
1
CLR
R
M1
G2
14
13
1, 2T/1C3
G4
Q
Q
A
B
3
3D
4R
A
M1
G2
1, 2T/1C3
G4
3D
4R
4
B
M1
G2
12
1, 2T/1C3
Q
C
G4
3D
4R
5
C
M1
G2
11
1, 2T/1C3
Q
D
G4
3D
4R
6
D
†
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
3
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢆ ꢇ ꢆ
ꢃꢊ ꢋꢌ ꢍ ꢀꢎ ꢁꢅ ꢄ ꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁ ꢒꢏꢎ ꢅꢐ ꢑꢁ ꢍꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
logic symbol, each D/T flip-flop
LD (Load)
M1
G2
TE (Toggle Enable)
CK (Clock)
1, 2T/1C3
G4
Q (Output)
D (Inverted Data)
R (Inverted Reset)
3D
4R
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
†
TG
TG
LD
TG
Q
TG
†
LD
†
CK
D
R
†
CK
TG
TG
†
†
CK
CK
†
The origins of LD and CK are shown in the logic diagram of the overall device.
4
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢆ
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SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (asynchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃꢊ ꢋꢌ ꢍ ꢀꢎ ꢁꢅ ꢄ ꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁ ꢒꢏꢎ ꢅꢐ ꢑꢁ ꢍꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC161
MIN NOM
SN74HC161
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
‡
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
IL
IH
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢆ
ꢃ ꢊꢋꢌ ꢍ ꢀꢎ ꢁꢅꢄꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁꢒꢏꢎ ꢅꢐ ꢑ ꢁꢍ ꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC161
SN74HC161
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
V
V = V or V
IH
V
OH
OL
I
IL
I
I
= −4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
8
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V = V or V
V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.4
0.33
0.33
1000
80
OL
= 5.2 mA
0.4
OL
I
I
V = V
I
or 0
6 V
1000
160
10
nA
µA
pF
I
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
CC
C
2 V to 6 V
3
10
10
i
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC161
SN74HC161
A
V
UNIT
CC
MIN
MAX
6
MIN
MAX
4.2
21
MIN
MAX
5
2 V
4.5 V
6 V
31
25
f
Clock frequency
Pulse duration
MHz
clock
36
25
29
2 V
80
16
14
80
16
14
150
30
26
135
27
23
170
34
29
125
25
21
0
120
24
20
120
24
20
225
45
38
205
41
35
255
51
43
190
38
32
0
100
20
17
100
20
17
190
38
32
170
34
29
215
43
37
155
31
26
0
4.5 V
6 V
CLK high or low
CLR low
t
w
ns
2 V
4.5 V
6 V
2 V
4.5 V
6 V
A, B, C, or D
LOAD low
2 V
4.5 V
6 V
t
su
Setup time before CLK↑
ns
2 V
4.5 V
6 V
ENP, ENT
2 V
4.5 V
6 V
CLR inactive
2 V
t
h
Hold time, all synchronous inputs after CLK↑
4.5 V
6 V
0
0
0
ns
0
0
0
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢆ ꢇ ꢆ
ꢃꢊ ꢋꢌ ꢍ ꢀꢎ ꢁꢅ ꢄ ꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁ ꢒꢏꢎ ꢅꢐ ꢑꢁ ꢍꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
14
SN54HC161
SN74HC161
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
31
36
40
25
29
f
max
MHz
44
25
2 V
83
215
43
325
65
270
54
4.5 V
6 V
24
RCO
Any Q
RCO
Any Q
RCO
Any
20
37
55
46
CLK
ENT
CLR
2 V
80
205
41
310
62
255
51
4.5 V
6 V
25
t
pd
ns
21
35
53
43
2 V
62
195
39
295
59
245
49
4.5 V
6 V
17
14
33
50
42
2 V
105
21
210
42
315
63
265
53
4.5 V
6 V
18
36
54
45
t
t
ns
ns
PHL
2 V
110
22
220
44
330
66
275
55
4.5 V
6 V
19
37
56
47
2 V
38
75
110
22
95
4.5 V
6 V
8
15
19
t
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
60
pF
pd
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢆ
ꢃ ꢊꢋꢌ ꢍ ꢀꢎ ꢁꢅꢄꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁꢒꢏꢎ ꢅꢐ ꢑ ꢁꢍ ꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
50%
50%
50%
Pulse
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
Low-Level
Pulse
(see Note A)
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢆ ꢇ ꢆ
ꢃꢊ ꢋꢌ ꢍ ꢀꢎ ꢁꢅ ꢄ ꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁ ꢒꢏꢎ ꢅꢐ ꢑꢁ ꢍꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
n-bit synchronous counters
This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit
counter. The ’HC161 devices count in binary. Virtually any count mode (modulo-N, N -to-N , N -to-maximum)
1
2
1
can be used with this fast look-ahead circuit.
The application circuit shown in Figure 2 is not valid for clock frequencies above 18 MHz (at 25°C and
4.5-V V ). The reason for this is that there is a glitch that is produced on the second stage’s RCO and every
CC
succeeding stage’s RCO. This glitch is common to all HC vendors that Texas Instruments has evaluated, in
addition to the bipolar equivalents (LS, ALS, AS).
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢆ
ꢃ ꢊꢋꢌ ꢍ ꢀꢎ ꢁꢅꢄꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁꢒꢏꢎ ꢅꢐ ꢑ ꢁꢍ ꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
LSB
CTR
CLR
Clear (L)
CT=0
LOAD
M1
RCO
RCO
RCO
RCO
3CT=MAX
ENT
Count (H)/
Disable (L)
G3
ENP
G4
CLK
C5/2,3,4+
Load (L)
[1]
[2]
[3]
[4]
A
B
C
D
1,5D
Q
Q
Q
Q
A
B
C
D
Count (H)/
Disable (L)
Clock
CTR
CLR
LOAD
ENT
CT=0
M1
3CT=MAX
G3
ENP
CLK
G4
C5/2,3,4+
[1]
[2]
[3]
[4]
A
B
C
D
1,5D
Q
Q
Q
Q
A
B
C
D
CTR
CLR
LOAD
ENT
CT=0
M1
3CT=MAX
G3
ENP
CLK
G4
C5/2,3,4+
[1]
[2]
[3]
[4]
A
B
C
D
1,5D
Q
Q
Q
Q
A
B
C
D
CTR
CLR
CT=0
M1
LOAD
ENT
3CT=MAX
G3
ENP
CLK
G4
C5/2,3,4+
A
B
C
D
1,5D [1]
Q
Q
Q
Q
A
B
C
D
[2]
[3]
[4]
To More−Significant Stages
Figure 2
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢆ ꢇ ꢆ
ꢃꢊ ꢋꢌ ꢍ ꢀꢎ ꢁꢅ ꢄ ꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁ ꢒꢏꢎ ꢅꢐ ꢑꢁ ꢍꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
The glitch on RCO is caused because the propagation delay of the rising edge of Q of the second stage is
A
shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, Q , Q , Q , and Q
A
B
C
D
(ENT × Q × Q × Q × Q ). The resulting glitch is about 7−12 ns in duration. Figure 3 shows the condition in
A
B
C
D
which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to
other stages. Q , Q , and Q of the first and second stage are at logic one, and Q of both stages are at logic
B
C
D
A
zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, Q and RCO of the
A
first stage go high. On the rising edge of the third clock pulse, Q and RCO of the first stage return to a low level,
A
and Q of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears
A
because of the race condition inside the chip.
1
2
3
4
5
CLK
ENT1
Q
, Q , Q
B1 C1 D1
Q
A1
RCO1, ENT2
Q
, Q , Q
B2 C2 D2
Q
A2
RCO2
Glitch (7−12 ns)
Figure 3
The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock
edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the
inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (t ). In other words,
g
f
= 1/(t CLK-to-RCO + t ). For example, at 25°C at 4.5-V V , the clock-to-RCO propagation delay is
max
pd g CC
43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the
cascaded counters can use is 18 MHz. The following tables contain the f
applications that use more than two ’HC161 devices cascaded together.
, t , and f
specifications for
clock
w
max
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢆ
ꢃ ꢊꢋꢌ ꢍ ꢀꢎ ꢁꢅꢄꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁꢒꢏꢎ ꢅꢐ ꢑ ꢁꢍ ꢓꢏ ꢀ
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC161
SN74HC161
A
V
UNIT
CC
MIN
MAX
3.6
18
MIN
MAX
2.5
12
MIN
MAX
2.9
14
2 V
4.5 V
6 V
f
t
Clock frequency
MHz
clock
21
14
17
2 V
140
28
200
40
170
36
Pulse duration, CLK high or low
4.5 V
6 V
ns
w
24
36
30
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Note 4)
T = 25°C
A
SN54HC161
SN74HC161
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
3.6
18
MAX
MIN
2.5
12
MAX
MIN
2.9
14
MAX
2 V
4.5 V
6 V
f
MHz
max
21
14
17
NOTE 4: These limits apply only to applications that use more than two ’HC161 devices cascaded together.
If the ’HC161 devices are used as a single unit, or only two cascaded together, then the maximum clock
frequency that the device can use is not limited because of the glitch. In these situations, the device can be
operated at the maximum specifications.
A glitch can appear on RCO of a single ’HC161 device, depending on the relationship of ENT to CLK. Any
application that uses RCO to drive any input except an ENT of another cascaded ’HC161 device must take this
into consideration.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
5962-8407501VEA
84075012A
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
CDIP
J
16
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
N / A for Pkg Type
5962-8407501VE
Samples
Samples
A
SNV54HC161J
ACTIVE
LCCC
FK
1
Non-RoHS
& Green
SNPB
-55 to 125
84075012A
SNJ54HC
161FK
8407501EA
8407501FA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
W
J
16
16
16
16
16
1
1
Non-RoHS
& Green
SNPB
SNPB
SNPB
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
8407501EA
SNJ54HC161J
Samples
Samples
Samples
Samples
Samples
Non-RoHS
& Green
8407501FA
SNJ54HC161W
JM38510/66302BEA
M38510/66302BEA
SN54HC161J
CDIP
CDIP
CDIP
1
Non-RoHS
& Green
JM38510/
66302BEA
J
1
Non-RoHS
& Green
JM38510/
66302BEA
J
1
Non-RoHS
& Green
SN54HC161J
SN74HC161D
SN74HC161DR
SN74HC161DRE4
SN74HC161DT
SN74HC161N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
16
16
16
16
16
16
16
16
16
20
40
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNPB
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
HC161
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
2500 RoHS & Green
2500 RoHS & Green
HC161
SOIC
D
HC161
SOIC
D
250
25
RoHS & Green
RoHS & Green
HC161
PDIP
N
SN74HC161N
HC161
SN74HC161NSR
SN74HC161PW
SN74HC161PWR
SN74HC161PWT
SNJ54HC161FK
SO
NS
PW
PW
PW
FK
2000 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TSSOP
TSSOP
TSSOP
LCCC
HC161
HC161
250
1
RoHS & Green
HC161
Non-RoHS
& Green
84075012A
SNJ54HC
161FK
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SNJ54HC161J
SNJ54HC161W
ACTIVE
CDIP
CFP
J
16
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
8407501EA
SNJ54HC161J
Samples
Samples
ACTIVE
W
1
Non-RoHS
& Green
SNPB
8407501FA
SNJ54HC161W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
OTHER QUALIFIED VERSIONS OF SN54HC161, SN54HC161-SP, SN74HC161 :
Catalog : SN74HC161, SN54HC161
•
Military : SN54HC161
•
Space : SN54HC161-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC161DR
SN74HC161NSR
SN74HC161PWR
SN74HC161PWT
SOIC
SO
D
16
16
16
16
2500
2000
2000
250
330.0
330.0
330.0
330.0
16.4
16.4
12.4
12.4
6.5
8.2
6.9
6.9
10.3
10.5
5.6
2.1
2.5
1.6
1.6
8.0
12.0
8.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
NS
PW
PW
TSSOP
TSSOP
5.6
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC161DR
SN74HC161NSR
SN74HC161PWR
SN74HC161PWT
SOIC
SO
D
16
16
16
16
2500
2000
2000
250
340.5
356.0
356.0
356.0
336.1
356.0
356.0
356.0
32.0
35.0
35.0
35.0
NS
PW
PW
TSSOP
TSSOP
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
84075012A
8407501FA
FK
W
LCCC
CFP
20
16
16
16
16
16
20
16
1
1
506.98
506.98
507
12.06
26.16
8
2030
6220
3940
11230
11230
3600
2030
6220
NA
NA
SN74HC161D
SN74HC161N
SN74HC161N
SN74HC161PW
SNJ54HC161FK
SNJ54HC161W
D
SOIC
PDIP
PDIP
TSSOP
LCCC
CFP
40
25
25
90
1
4.32
4.32
4.32
3.5
N
506
13.97
13.97
10.2
N
506
PW
FK
W
530
506.98
506.98
12.06
26.16
NA
1
NA
Pack Materials-Page 3
GENERIC PACKAGE VIEW
FK 20
8.89 x 8.89, 1.27 mm pitch
LCCC - 2.03 mm max height
LEADLESS CERAMIC CHIP CARRIER
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229370\/A\
www.ti.com
PACKAGE OUTLINE
NS0016A
SOP - 2.00 mm max height
S
C
A
L
E
1
.
5
0
0
SOP
C
SEATING PLANE
8.2
7.4
TYP
0.1 C
A
PIN 1 ID
AREA
14X 1.27
16
1
2X
10.4
10.0
NOTE 3
8.89
8
9
0.51
0.35
16X
5.4
5.2
B
2.00 MAX
0.25
C A B
NOTE 4
0.15 TYP
SEE DETAIL A
0.25
0.3
0.1
GAGE PLANE
0 - 10
1.05
0.55
DETAIL A
TYPICAL
(1.25)
4220735/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
NS0016A
SOP - 2.00 mm max height
SOP
16X (1.85)
16X (0.6)
SEE
DETAILS
SYMM
1
16
SYMM
14X (1.27)
9
8
(R0.05) TYP
(7)
LAND PATTERN EXAMPLE
SCALE:7X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220735/A 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
NS0016A
SOP - 2.00 mm max height
SOP
16X (1.85)
16X (0.6)
SYMM
1
16
SYMM
14X (1.27)
8
9
(R0.05) TYP
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220735/A 12/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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