SN54HC240J [TI]
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS; 八路缓冲器并用3态输出线路驱动器
| 型号： | SN54HC240J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总6页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC240, SN74HC240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS128B – DECEMBER 1982 – REVISED MAY 1997
SN54HC240 . . . J OR W PACKAGE
SN74HC240 . . . DW OR N PACKAGE
(TOP VIEW)
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
High-Current Outputs Drive up to 15 LSTTL
Loads
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
Package Options Include Plastic (DW) and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
2OE
1Y1
2A4
1Y2
2A3
1Y3
description
13 2A2
12 1Y4
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. The ’HC240 are organized as two
4-bit buffers/drivers with separate output-enable
(OE) inputs. When OE is low, the device passes
inverted data from the A inputs to the Y outputs.
When OE is high, the outputs are in the
high-impedance state.
11
2A1
SN54HC240 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
4
5
6
7
8
17
16
15
14
The SN54HC240 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC240 is characterized for
operation from –40°C to 85°C.
9 10 11 12 13
FUNCTION TABLE
(each buffer/driver)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC240, SN74HC240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS128B – DECEMBER 1982 – REVISED MAY 1997
†
logic symbol
1
19
EN
EN
2OE
1OE
2
4
6
8
18
11
13
15
17
9
7
5
3
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
16
14
12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
19
1OE
2OE
18
16
2
9
7
11
13
1Y1
1Y2
1Y3
1Y4
1A1
2Y1
2Y2
2A1
2A2
2A3
2A4
4
1A2
14
12
5
3
6
15
17
1A3
2Y3
2Y4
8
1A4
‡
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC240, SN74HC240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS128B – DECEMBER 1982 – REVISED MAY 1997
recommended operating conditions
SN54HC240
MIN NOM
SN74HC240
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
3.15
4.2
0
5
6
2
1.5
3.15
4.2
0
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
0
0
0
0
V
V
Input voltage
0
V
V
0
V
V
V
V
I
CC
CC
Output voltage
0
0
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
0
1000
500
400
125
0
1000
500
400
85
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
0
0
ns
t
0
0
T
–55
–40
°C
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC240
SN74HC240
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.4
OH
V
V = V or V
IH
5.9
V
OH
OL
I
IL
IL
I
I
= –6 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= –7.8 mA
OH
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
4.5 V
6 V
OL
V
V = V or V
0.1
0.1
0.1
V
I
IH
I
I
= 6 mA
4.5 V
6 V
0.26
0.26
±100
±0.5
8
0.4
0.33
0.33
±1000
±5
OL
= 7.8 mA
0.15
0.4
OL
I
I
I
V = V
I
or 0
6 V
±0.1
±1000
±10
160
10
nA
µA
µA
pF
I
CC
CC
V
O
= V
or 0
6 V
±0.01
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
80
C
2 V to 6 V
3
10
10
i
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC240, SN74HC240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS128B – DECEMBER 1982 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
50
10
9
SN54HC240
SN74HC240
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
100
20
MIN
MAX
150
30
MIN
MAX
125
25
2 V
4.5 V
6 V
t
t
t
t
A
Y
Y
Y
Y
ns
pd
en
dis
t
17
25
21
2 V
75
15
13
44
22
21
28
8
150
30
225
45
190
38
OE
OE
4.5 V
6 V
ns
ns
ns
26
38
32
2 V
150
30
225
45
190
38
4.5 V
6 V
26
38
32
2 V
60
90
75
4.5 V
6 V
12
18
15
6
10
15
13
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
75
SN54HC240
SN74HC240
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
150
30
MIN
MAX
225
45
MIN
MAX
190
38
2 V
4.5 V
6 V
t
pd
t
en
t
t
A
Y
Y
Y
15
ns
13
26
38
32
2 V
100
20
200
40
300
60
250
50
OE
4.5 V
6 V
ns
ns
17
34
51
43
2 V
45
210
42
315
63
265
53
4.5 V
6 V
17
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
Power dissipation capacitance per buffer/driver
TEST CONDITIONS
TYP
UNIT
C
No load
35
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC240, SN74HC240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS128B – DECEMBER 1982 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
S1
S2
t
t
Open
Closed
Closed
Open
PZH
Test
Point
t
t
1 kΩ
1 kΩ
en
R
L
From Output
Under Test
PZL
t
t
Open
Closed
Open
PHZ
PLZ
50 pF
C
dis
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
––
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Input
50%
50%
0 V
t
t
PLH
PHL
90%
V
V
OH
In-Phase
Output
90%
50%
10%
50%
10%
OL
t
Output
Control
(Low-Level
Enabling)
t
r
f
f
V
CC
t
t
PLH
PHL
90%
50%
50%
V
V
OH
90%
t
0 V
Out-of-Phase
Output
50%
10%
50%
10%
t
t
PLZ
PZL
OL
t
≈ V
≈ V
r
Output
Waveform 1
(See Note B)
CC
CC
50%
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
10%
90%
V
OL
t
PZH
V
CC
V
Output
Waveform 2
(See Note B)
OH
90%
t
90%
Input
50%
10%
50%
10%
50%
0 V
≈ 0 V
t
PHZ
t
r
f
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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