SN54HC595FKR [TI]
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| 型号： | SN54HC595FKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 暂无描述 移位寄存器 输出元件 |
| 文件： | 总9页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MAY 1997
SN54HC595 . . . J OR W PACKAGE
SN74HC595 . . . D OR N PACKAGE
(TOP VIEW)
8-Bit Serial-In, Parallel-Out Shift
High-Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
Shift Register Has Direct Clear
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Q
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
C
D
A
Q
SER
Q
OE
E
Q
RCLK
SRCLK
SRCLR
F
Q
G
Q
H
description
GND
Q
H′
The ’HC595 contain an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state
outputs. Separate clocks are provided for both the
shift and storage register. The shift register has a
direct overriding clear (SRCLR) input, serial
(SER) input, and serial outputs for cascading.
SN54HC595 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
SER
OE
Q
4
5
6
7
8
D
Q
17
16
15
14
Both the shift register clock (RCLK) and storage
register clock (SRCLK) are positive-edge trig-
gered. If both clocks are connected together, the
shift register is always one clock pulse ahead of
the storage register.
E
NC
NC
RCLK
SRCLK
Q
F
Q
G
9 10 11 12 13
The SN54HC595 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC595 is characterized for
operation from –40°C to 85°C.
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MAY 1997
†
logic symbol
13
EN3
C2
OE
12
RCLK
SRG8
10
11
R
SRCLR
SRCLK
C1/
15
1
14
Q
Q
2D
3
SER
1D
A
B
2
Q
Q
C
D
3
4
5
6
7
9
Q
Q
E
F
Q
Q
G
H
2D
3
Q
H′
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MAY 1997
logic diagram (positive logic)
13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
SER
1D
C1
R
3R
C3
3S
15
Q
Q
A
B
2S
2R
C2
3R
C3
1
2
3
4
5
6
R
3S
2S
2R
3R
C2
C3
Q
Q
C
D
R
3S
2S
2R
3R
C2
C3
R
3S
2S
2R
3R
Q
Q
Q
C2
C3
E
F
R
3S
2S
2R
3R
C2
C3
R
3S
2S
2R
3R
C2
C3
G
R
3S
2S
2R
C2
3R
C3
3S
7
9
Q
Q
H
R
H′
Pin numbers shown are for the D, J, N, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HC595
MIN NOM
SN74HC595
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
3.15
4.2
0
5
6
2
1.5
3.15
4.2
0
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
0
0
0
0
V
V
Input voltage
0
V
V
0
V
V
V
V
I
CC
CC
Output voltage
0
0
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
0
1000
500
400
125
0
1000
500
400
85
‡
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
0
0
ns
t
0
0
T
A
–55
–40
°C
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
IL IH
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC595
SN74HC595
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
3.7
5.2
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.4
OH
5.9
V
OH
V = V or V
IH
Q
, I
H′ OH
= –4 mA
3.98
4.3
4.3
3.84
3.84
5.34
5.34
V
I
IL
4.5 V
6 V
Q –Q , I
= –6 mA
3.98
5.48
5.48
A
H
OH
Q
, I
H′ OH
= –5.2 mA
5.8
Q –Q , I
= –7.8 mA
5.8
A
H
OH
2 V
4.5 V
6 V
0.002
0.001
0.001
0.17
0.17
0.15
0.15
±0.1
±0.01
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
OL
0.1
0.1
0.1
V
OL
V = V or V
Q
, I
H′ OL
= 4 mA
0.26
0.26
0.26
0.26
±100
±0.5
8
0.4
0.33
0.33
0.33
0.33
±1000
±5
V
I
IH
IL
4.5 V
6 V
Q –Q , I
= 6 mA
0.4
A
H
OL
Q
, I
H′ OL
= 5.2 mA
0.4
Q –Q , I = 7.8 mA
H OL
0.4
A
I
I
I
V = V
or 0
6 V
6 V
6 V
±1000
±10
160
nA
µA
µA
I
I
CC
CC
V
O
= V
or 0
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
80
2 V
to 6 V
C
3
10
10
10
pF
i
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MAY 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC595
SN74HC595
A
V
UNIT
CC
MIN
0
MAX
6
MIN
0
MAX
4.2
21
MIN
0
MAX
5
2 V
4.5 V
6 V
f
Clock frequency
Pulse duration
0
31
0
0
25
MHz
clock
0
36
0
25
0
29
2 V
80
16
14
80
16
14
100
20
17
75
15
13
50
10
9
120
24
20
120
24
20
150
30
25
113
23
19
75
15
13
75
15
13
0
100
20
17
100
20
17
125
25
21
94
19
16
65
13
11
60
12
11
0
SRCLK or RCLK high or low
SRCLR low
4.5 V
6 V
t
w
ns
2 V
4.5 V
6 V
2 V
SER before SRCLK↑
4.5 V
6 V
2 V
†
SRCLK↑ before RCLK↑
4.5 V
6 V
t
su
Setup time
ns
2 V
SRCLR low before RCLK↑
4.5 V
6 V
2 V
50
10
9
SRCLR high (inactive) before SRCLK↑
4.5 V
6 V
2 V
0
t
h
Hold time, SER after SRCLK↑
4.5 V
6 V
0
0
0
ns
0
0
0
†
This setup time ensures the output register sees stable data from the shift-register outputs. The clocks may be tied together, in which case the
output register is one clock pulse behind the shift register.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
26
38
42
50
17
14
50
17
14
51
18
15
40
15
13
42
23
20
28
8
SN54HC595
SN74HC595
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
f
t
31
36
25
29
MHz
max
pd
25
2 V
160
32
240
48
200
40
SRCLK
RCLK
SRCLR
OE
Q
4.5 V
6 V
H′
27
41
34
ns
2 V
150
30
225
45
187
37
Q –Q
A
4.5 V
6 V
H
26
38
32
2 V
175
35
261
52
219
44
t
t
t
Q
4.5 V
6 V
ns
ns
ns
PHL
H′
30
44
37
2 V
150
30
225
45
187
37
Q –Q
A
4.5 V
6 V
en
H
H
H
26
38
32
2 V
200
40
300
60
250
50
OE
Q –Q
A
4.5 V
6 V
dis
34
51
43
2 V
60
90
75
Q –Q
A
4.5 V
6 V
12
18
15
6
10
15
13
t
t
ns
2 V
28
8
75
110
22
95
Q
4.5 V
6 V
15
19
H′
6
13
19
16
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
60
SN54HC595
SN74HC595
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
200
40
MIN
MAX
300
60
MIN
MAX
250
50
2 V
4.5 V
6 V
t
pd
t
en
t
t
RCLK
OE
Q –Q
A
22
ns
H
H
H
19
34
51
43
2 V
70
200
40
298
60
250
50
Q –Q
A
4.5 V
6 V
23
ns
ns
19
34
51
43
2 V
45
210
42
315
63
265
53
Q –Q
A
4.5 V
6 V
17
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
400
pF
pd
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
t
Open
Closed
Closed
Open
S1
S2
PZH
Test
Point
t
t
1 kΩ
1 kΩ
en
R
t
L
PZL
From Output
Under Test
t
t
Open
Closed
Open
PHZ
PLZ
50 pF
C
dis
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
––
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
High-Level
Pulse
50%
50%
t
t
h
su
0 V
V
CC
t
Data
Input
w
90%
90%
50%
10%
50%
10%
V
CC
Low-Level
Pulse
0 V
50%
50%
t
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
V
CC
V
CC
Control
(Low-Level
Enabling)
Input
50%
50%
50%
50%
0 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
V
OH
≈ V
CC
50%
≈ V
CC
Output
Waveform 1
(See Note B)
In-Phase
Output
90%
t
50%
10%
50%
10%
10%
90%
OL
V
OL
t
r
f
t
t
t
PZH
PHL
90%
PLH
V
V
OH
V
Output
Waveform 2
(See Note B)
OH
90%
t
Out-of-
Phase
Output
50%
10%
50%
10%
50%
≈ 0 V
OL
t
t
PHZ
f
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured when the input duty cycle is 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
pd
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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