SN54LV05A_08 [TI]

HEX INVERTERS WITH OPEN-DRAIN OUTPUTS; 具有漏极开路输出六路反向器
SN54LV05A_08
型号: SN54LV05A_08
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

HEX INVERTERS WITH OPEN-DRAIN OUTPUTS
具有漏极开路输出六路反向器

输出元件
文件: 总15页 (文件大小:498K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ꢊꢋꢌ ꢍꢁ ꢅꢋ ꢎ ꢏꢋ ꢎꢀ  
SCLS391I − APRIL 1998 − REVISED APRIL 2005  
SN54LV05A . . . J OR W PACKAGE  
SN74LV05A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
2-V to 5.5-V V  
Operation  
CC  
Typical V  
OLP  
(Output Ground Bounce)  
= 3.3 V, T = 25°C  
<0.8 V at V  
CC  
A
1A  
1Y  
V
CC  
D
D
D
D
D
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
1
2
3
4
5
6
7
14  
13  
12  
11  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
6A  
6Y  
5A  
A
2A  
Support Mixed-Mode Voltage Operation on  
All Ports  
2Y  
3A  
10 5Y  
I
Supports Partial-Power-Down Mode  
off  
9
8
3Y  
4A  
4Y  
Operation  
GND  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
SN54LV05A . . . FK PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
3
2
1 20 19  
18  
6Y  
NC  
5A  
2A  
NC  
2Y  
4
5
6
7
8
description/ordering information  
17  
16  
The ’LV05A devices contain six independent  
inverters designed for 2-V to 5.5-V V  
operation.  
CC  
15 NC  
14  
9 10 11 12 13  
NC  
3A  
5Y  
These devices perform the Boolean function  
Y = A.  
The open-drain outputs require pullup resistors to  
perform correctly and can be connected to other  
open-drain outputs to implement active-low  
wired-OR or active-high wired-AND functions.  
NC − No internal connection  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube of 50  
SN74LV05AD  
SOIC − D  
LV05A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV05ADR  
SN74LV05ANSR  
SN74LV05ADBR  
SN74LV05APW  
SN74LV05APWR  
SN74LV05APWT  
SN74LV05ADGVR  
SNJ54LV05AJ  
SOP − NS  
74LV05A  
LV05A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV05A  
TVSOP − DGV  
CDIP − J  
LV05A  
SNJ54LV05AJ  
SNJ54LV05AW  
SNJ54LV05AFK  
−55°C to 125°C  
CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV05AW  
SNJ54LV05AFK  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢕ ꢁ ꢄꢋꢀꢀ ꢑ ꢏꢊ ꢋꢎꢐ ꢍꢀ ꢋ ꢁ ꢑꢏꢋꢔ ꢖꢗ ꢘꢙ ꢚꢛꢜ ꢝꢞꢟ ꢠꢖ ꢜꢛ ꢠꢖꢡ ꢘꢠꢙ ꢒꢎ ꢑ ꢔ ꢕ ꢢꢏ ꢍꢑ ꢁ  
ꢏꢟꢩ  
ꢟꢠ  
ꢥꢡ ꢤ ꢡ ꢞ ꢟ ꢖ ꢟ ꢤ ꢙ ꢨ  
ꢜꢟ  
ꢙꢖ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢂ ꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢆ ꢂꢇ  
ꢊ ꢋꢌ ꢍ ꢁ ꢅꢋꢎ ꢏ ꢋꢎ ꢀ  
ꢐꢍ ꢏ ꢊ ꢑꢒꢋ ꢁꢓꢔ ꢎ ꢇꢍ ꢁ ꢑ ꢕꢏꢒ ꢕꢏ ꢀ  
SCLS391I − APRIL 1998 − REVISED APRIL 2005  
FUNCTION TABLE  
(each inverter)  
INPUT  
A
OUTPUT  
Y
H
L
L
H
logic diagram (positive logic)  
A
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
I
Voltage range applied to any output in the high-impedance  
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
O
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
+ 0.5 V  
CC  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA  
IK  
OK  
I
Output clamp current, I  
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA  
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA  
Continuous current through V  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W  
JA  
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W  
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W  
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W  
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.  
2. This value is limited to 5.5 V maximum.  
3. The package thermal impedance is calculated in accordance with JESD 51-7.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢄꢅ  
ꢊꢋꢌ ꢍꢁ ꢅꢋ ꢎ ꢏꢋ ꢎꢀ  
SCLS391I − APRIL 1998 − REVISED APRIL 2005  
recommended operating conditions (see Note 4)  
SN54LV05A  
MIN MAX  
SN74LV05A  
UNIT  
MIN  
2
MAX  
V
V
Supply voltage  
2
5.5  
5.5  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 2 V  
1.5  
1.5  
= 2.3 V to 2.7 V  
= 3 V to 3.6 V  
= 4.5 V to 5.5 V  
= 2 V  
V
V
V
× 0.7  
× 0.7  
× 0.7  
V
V
V
× 0.7  
CC  
CC  
CC  
CC  
CC  
CC  
High-level input voltage  
V
IH  
× 0.7  
× 0.7  
0.5  
0.5  
= 2.3 V to 2.7 V  
= 3 V to 3.6 V  
= 4.5 V to 5.5 V  
V
V
V
× 0.3  
× 0.3  
× 0.3  
V
V
V
× 0.3  
CC  
CC  
CC  
CC  
CC  
CC  
V
IL  
Low-level input voltage  
V
× 0.3  
× 0.3  
V
V
Input voltage  
0
0
5.5  
5.5  
50  
0
0
5.5  
5.5  
50  
2
V
V
I
Output voltage  
O
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 2 V  
µA  
= 2.3 V to 2.7 V  
= 3 V to 3.6 V  
= 4.5 V to 5.5 V  
= 2.3 V to 2.7 V  
= 3 V to 3.6 V  
= 4.5 V to 5.5 V  
2
I
Low-level output current  
OL  
6
6
mA  
12  
12  
200  
100  
20  
85  
200  
100  
20  
t/v Input transition rise or fall rate  
ns/V  
T
A
Operating free-air temperature  
−55  
125  
−40  
°C  
NOTE 4: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
SN54LV05A  
SN74LV05A  
PARAMETER  
TEST CONDITIONS  
UNIT  
V
CC  
MIN  
TYP  
MAX  
0.1  
0.4  
0.44  
0.55  
1
MIN  
TYP  
MAX  
0.1  
0.4  
0.44  
0.55  
1
I
I
I
I
= 50 µA  
2 V to 5.5 V  
2.3 V  
OL  
OL  
OL  
OL  
= 2 mA  
= 6 mA  
= 12 mA  
V
OL  
V
3 V  
4.5 V  
I
I
I
V = 5.5 V or GND  
0 to 5.5 V  
5.5 V  
µA  
µA  
µA  
pF  
I
I
V = V  
CC  
or GND,  
I = 0  
O
20  
20  
CC  
off  
I
V or V = 0 to 5.5 V  
0
5
5
I
O
C
V = V  
or GND  
3.3 V  
2.5  
2.5  
i
I
CC  
ꢚꢟ ꢙ ꢘ ꢬꢠ ꢥꢗ ꢡ ꢙ ꢟ ꢛꢣ ꢚꢟ ꢭ ꢟ ꢧꢛ ꢥꢞꢟ ꢠꢖꢨ ꢢ ꢗꢡ ꢤꢡ ꢜꢖ ꢟꢤ ꢘꢙ ꢖꢘ ꢜ ꢚꢡ ꢖꢡ ꢡꢠ ꢚ ꢛꢖ ꢗꢟꢤ  
ꢜ ꢗꢡ ꢠ ꢬꢟ ꢛꢤ ꢚꢘ ꢙ ꢜ ꢛꢠ ꢖꢘ ꢠꢝꢟ ꢖ ꢗꢟ ꢙ ꢟ ꢥꢤ ꢛꢚ ꢝꢜꢖ ꢙ ꢪ ꢘꢖꢗ ꢛꢝꢖ ꢠꢛꢖ ꢘꢜꢟ ꢨ  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢂ ꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢆ ꢂꢇ  
ꢊ ꢋꢌ ꢍ ꢁ ꢅꢋꢎ ꢏ ꢋꢎ ꢀ  
ꢐꢍ ꢏ ꢊ ꢑꢒꢋ ꢁꢓꢔ ꢎ ꢇꢍ ꢁ ꢑ ꢕꢏꢒ ꢕꢏ ꢀ  
SCLS391I − APRIL 1998 − REVISED APRIL 2005  
switching characteristics over recommended operating free-air temperature range,  
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)  
CC  
T = 25°C  
A
SN54LV05A  
SN74LV05A  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
UNIT  
ns  
MIN  
TYP  
MAX  
MIN  
1*  
MAX  
13*  
15*  
18  
MIN  
1
MAX  
13  
t
t
t
3.6* 10.4*  
5.8* 12.2*  
PLH  
PHL  
PLH  
A
A
Y
Y
C
C
= 15 pF  
= 50 pF  
L
L
1*  
1
15  
6.1  
8.1  
15.2  
16.6  
1
1
18  
ns  
t
1
19.5  
1
19.5  
PHL  
* On products compliant to MIL-PRF-38535, this parameter is not production tested.  
switching characteristics over recommended operating free-air temperature range,  
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)  
CC  
T
A
= 25°C  
TYP  
2.9*  
4*  
SN54LV05A  
SN74LV05A  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
UNIT  
ns  
MIN  
MAX  
7.1*  
7.1*  
10.6  
MIN  
1*  
MAX  
8.5*  
8.5*  
12  
MIN  
1
MAX  
8.5  
8.5  
12  
t
t
t
PLH  
PHL  
PLH  
A
A
Y
Y
C
C
= 15 pF  
= 50 pF  
L
L
1*  
1
4.7  
1
1
ns  
t
5.8  
10.6  
1
12  
1
12  
PHL  
* On products compliant to MIL-PRF-38535, this parameter is not production tested.  
switching characteristics over recommended operating free-air temperature range,  
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)  
CC  
T
A
= 25°C  
TYP  
2.2*  
SN54LV05A  
SN74LV05A  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
UNIT  
ns  
MIN  
MAX  
5.5*  
5.5*  
7.5  
MIN  
1*  
MAX  
6.5*  
6.5*  
8.5  
MIN  
1
MAX  
6.5  
t
t
t
PLH  
PHL  
PLH  
A
A
Y
Y
C
C
= 15 pF  
= 50 pF  
L
L
2.9*  
1*  
1
6.5  
3.4  
1
1
8.5  
ns  
t
4.2  
7.5  
1
8.5  
1
8.5  
PHL  
* On products compliant to MIL-PRF-38535, this parameter is not production tested.  
noise characteristics, V  
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)  
CC  
L
A
SN74LV05A  
PARAMETER  
UNIT  
MIN  
TYP  
0.55  
MAX  
0.8  
V
V
V
V
V
Quiet output, maximum dynamic V  
V
V
V
V
V
OL(P)  
OL(V)  
OH(V)  
IH(D)  
IL(D)  
OL  
Quiet output, minimum dynamic V  
Quiet output, minimum dynamic V  
High-level dynamic input voltage  
Low-level dynamic input voltage  
−0.04  
3.12  
−0.8  
OL  
OH  
2.31  
0.97  
NOTE 5: Characteristics are for surface-mount packages only.  
operating characteristics, T = 25°C  
A
PARAMETER  
TEST CONDITIONS  
= 50 pF, f = 10 MHz  
L
V
TYP  
2.5  
3
UNIT  
CC  
3.3 V  
5 V  
C
Power dissipation capacitance  
C
pF  
pd  
ꢚ ꢟ ꢙ ꢘ ꢬ ꢠ ꢥꢗ ꢡ ꢙ ꢟ ꢛꢣ ꢚꢟ ꢭ ꢟ ꢧ ꢛꢥ ꢞꢟ ꢠ ꢖꢨ ꢢ ꢗꢡ ꢤꢡ ꢜꢖ ꢟꢤ ꢘꢙ ꢖꢘ ꢜ ꢚꢡ ꢖꢡ ꢡꢠ ꢚ ꢛꢖ ꢗꢟꢤ  
ꢜ ꢗ ꢡ ꢠ ꢬꢟ ꢛꢤ ꢚꢘ ꢙ ꢜ ꢛꢠ ꢖꢘ ꢠꢝ ꢟ ꢖ ꢗꢟ ꢙ ꢟ ꢥꢤ ꢛ ꢚꢝꢜ ꢖꢙ ꢪ ꢘꢖꢗ ꢛꢝꢖ ꢠꢛꢖ ꢘꢜꢟ ꢨ  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢄꢅ  
ꢊꢋꢌ ꢍꢁ ꢅꢋ ꢎ ꢏꢋ ꢎꢀ  
SCLS391I − APRIL 1998 − REVISED APRIL 2005  
PARAMETER MEASUREMENT INFORMATION  
V
CC  
V
CC  
R
= 1 kΩ  
50% V  
CC  
50% V  
Input  
L
CC  
0 V  
From Output  
Under Test  
Test  
Point  
t
t
PHL  
PLH  
V  
C
CC  
L
50% V  
CC  
(see Note A)  
Output  
V
OL  
+ 0.3 V  
V
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
LOAD CIRCUIT FOR  
OPEN-DRAIN OUTPUTS  
NOTES: A.  
C
includes probe and jig capacitance.  
L
B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t 3 ns, t 3 ns.  
O
r
f
C. The outputs are measured one at a time, with one input transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Jun-2007  
PACKAGING INFORMATION  
Orderable Device  
SN74LV05AD  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LV05ADBR  
SN74LV05ADBRE4  
SN74LV05ADBRG4  
SN74LV05ADE4  
SSOP  
SSOP  
SSOP  
SOIC  
DB  
DB  
DB  
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LV05ADG4  
SN74LV05ADGVR  
SN74LV05ADGVRE4  
SN74LV05ADGVRG4  
SN74LV05ADR  
SOIC  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TVSOP  
TVSOP  
TVSOP  
SOIC  
DGV  
DGV  
DGV  
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LV05ADRE4  
SN74LV05ADRG4  
SN74LV05ANSR  
SN74LV05ANSRE4  
SN74LV05ANSRG4  
SN74LV05APW  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
NS  
NS  
NS  
PW  
PW  
PW  
PW  
PW  
PW  
PW  
PW  
PW  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LV05APWE4  
SN74LV05APWG4  
SN74LV05APWR  
SN74LV05APWRE4  
SN74LV05APWRG4  
SN74LV05APWT  
SN74LV05APWTE4  
SN74LV05APWTG4  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Jun-2007  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-Mar-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
SN74LV05ADBR  
SN74LV05ADGVR  
SN74LV05ADR  
SSOP  
TVSOP  
SOIC  
DB  
DGV  
D
14  
14  
14  
14  
14  
2000  
2000  
2500  
2000  
2000  
330.0  
330.0  
330.0  
330.0  
330.0  
16.4  
12.4  
16.4  
16.4  
12.4  
8.2  
6.8  
6.5  
8.2  
7.0  
6.6  
4.0  
2.5  
1.6  
2.1  
2.5  
1.6  
12.0  
8.0  
16.0  
12.0  
16.0  
16.0  
12.0  
Q1  
Q1  
Q1  
Q1  
Q1  
9.0  
8.0  
SN74LV05ANSR  
SN74LV05APWR  
SO  
NS  
10.5  
5.6  
12.0  
8.0  
TSSOP  
PW  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-Mar-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
SN74LV05ADBR  
SN74LV05ADGVR  
SN74LV05ADR  
SSOP  
TVSOP  
SOIC  
DB  
DGV  
D
14  
14  
14  
14  
14  
2000  
2000  
2500  
2000  
2000  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
33.0  
29.0  
33.0  
33.0  
29.0  
SN74LV05ANSR  
SN74LV05APWR  
SO  
NS  
TSSOP  
PW  
Pack Materials-Page 2  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000  
DGV (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
24 PINS SHOWN  
0,23  
0,13  
M
0,07  
0,40  
24  
13  
0,16 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
0°ā8°  
0,75  
1
12  
0,50  
A
Seating Plane  
0,08  
0,15  
0,05  
1,20 MAX  
PINS **  
14  
16  
20  
24  
38  
48  
56  
DIM  
A MAX  
A MIN  
3,70  
3,50  
3,70  
3,50  
5,10  
4,90  
5,10  
4,90  
7,90  
7,70  
9,80  
9,60  
11,40  
11,20  
4073251/E 08/00  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.  
D. Falls within JEDEC: 24/48 Pins – MO-153  
14/16/20/56 Pins – MO-194  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are  
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
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