SN54LV594A_07 [TI]
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS; 8位的移位寄存器与输出寄存器
| 型号： | SN54LV594A_07 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS |
| 文件： | 总20页 (文件大小：437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢃ ꢇꢈ ꢀꢁꢉ ꢃꢄꢅ ꢂꢆ ꢃꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏꢍ ꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ ꢍꢎ ꢏ ꢕ ꢖꢎ ꢗꢖꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
SCLS413I − APRIL 1998 − REVISED APRIL 2005
SN54LV594A . . . J OR W PACKAGE
SN74LV594A . . . D, DB, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
2-V to 5.5-V V
Operation
CC
Max t of 6.5 ns at 5 V
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
= 3.3 V, T = 25°C
B
A
Q
C
D
A
D
D
D
D
D
D
D
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
Q
SER
= 3.3 V, T = 25°C
A
Q
RCLR
E
Support Mixed-Mode Voltage Operation
on All Ports
Q
12 RCLK
F
11
10
9
Q
SRCLK
SRCLR
G
8-Bit Serial-In, Parallel-Out Shift
Registers With Storage
Q
H
GND
Q
H′
Independent Direct Overriding Clears
on Shift and Storage Registers
SN54LV594A . . . FK PACKAGE
(TOP VIEW)
Independent Clocks for Shift and
Storage Registers
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
3
2
1
20 19
18
SER
RCLR
NC
Q
4
5
6
7
8
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Q
17
16
E
NC
15 RCLK
14
9 10 11 12 13
Q
F
− 1000-V Charged-Device Model (C101)
SRCLK
Q
G
description/ordering information
The ’LV594A devices are 8-bit shift registers
designed for 2-V to 5.5-V V
operation.
CC
NC − No internal connection
These devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR, SRCLR) inputs are
provided on the shift and storage registers. A serial output (Q ) is provided for cascading purposes.
H′
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 40
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74LV594AD
SOIC − D
LV594A
SN74LV594ADR
SN74LV594ANSR
SN74LV594ADBR
SN74LV594APW
SN74LV594APWR
SN74LV594APWT
SNJ54LV594AJ
SNJ54LV594AW
SNJ54LV594AFK
SOP − NS
74LV594A
LV594A
SSOP − DB
−40°C to 85°C
TSSOP − PW
LV594A
CDIP − J
CFP − W
LCCC − FK
SNJ54LV594AJ
SNJ54LV594AW
SNJ54LV594AFK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢖ ꢁ ꢄꢒꢀꢀ ꢕ ꢎꢏ ꢒꢑꢔ ꢍꢀ ꢒ ꢁ ꢕꢎꢒꢘ ꢙꢚ ꢛꢜ ꢝꢞꢟ ꢠꢡꢢ ꢣꢙ ꢟꢞ ꢣꢙꢤ ꢛꢣꢜ ꢗꢑ ꢕ ꢘ ꢖ ꢥꢎ ꢍꢕ ꢁ
ꢙ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢃꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢃ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕꢖ ꢎ ꢗꢖ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS413I − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
The shift-register (SRCLK) and storage-register (RCLK) clocks are positive-edge triggered. If the clocks are tied
together, the shift register always is one clock pulse ahead of the storage register.
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK
RCLR
X
X
L
X
X
Shift register is cleared.
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
X
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
H
↑
H
X
L
X
X
X
↓
X
X
X
H
X
X
X
X
X
↑
↓
X
L
Shift register state is not changed.
Storage register is cleared.
H
H
Shift register data is stored in the storage register.
Storage register state is not changed.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢃ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂꢆ ꢃꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏ ꢍꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ ꢍꢎ ꢏ ꢕ ꢖꢎ ꢗꢖꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
SCLS413I − APRIL 1998 − REVISED APRIL 2005
logic diagram (positive logic)
13
RCLR
12
RCLK
10
SRCLR
11
SRCLK
R
3D
C3
14
15
SER
Q
Q
Q
1D
C1
R
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
A
B
C
D
E
F
R
3D
1
2
2D
C2
R
C3
R
3D
2D
C2
C3
R
R
3
4
5
6
Q
Q
2D
C2
3D
C3
Q
Q
R
R
2D
C2
3D
C3
R
R
2D
C2
3D
C3
Q
Q
Q
Q
Q
Q
R
R
2D
C2
3D
C3
G
R
R
7
9
Q
Q
2D
C2
3D
C3
H
R
H′
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢃꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢃ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕꢖ ꢎ ꢗꢖ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS413I − APRIL 1998 − REVISED APRIL 2005
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H’
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢃ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂꢆ ꢃꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏ ꢍꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ ꢍꢎ ꢏ ꢕ ꢖꢎ ꢗꢖꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
SCLS413I − APRIL 1998 − REVISED APRIL 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance or
power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢃꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢃ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕꢖ ꢎ ꢗꢖ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS413I − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 4)
SN54LV594A
SN74LV594A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
V
V
V
× 0.3
× 0.3
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
Input voltage
0
0
5.5
0
0
5.5
V
V
I
Output voltage
V
V
O
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
200
100
20
∆t/∆v Input transition rise or fall rate
ns/V
T
Operating free-air temperature
−55
125
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV594A
SN74LV594A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
V
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
V = V
CC
or GND,
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
3.5
3.5
i
I
CC
ꢗ
ꢑ
ꢕ
ꢘ
ꢖ
ꢥ
ꢎ
ꢗ
ꢑ
ꢒ
ꢅ
ꢍ
ꢒ
ꢔ
ꢛ
ꢣ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢧ
ꢣ
ꢜ
ꢨ
ꢧ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢯ ꢣ ꢨꢚ ꢤ ꢜ ꢢ ꢞꢦ ꢝꢢ ꢰ ꢢ ꢪ ꢞꢨ ꢡꢢ ꢣ ꢙꢫ ꢥ ꢚꢤ ꢧꢤ ꢟꢙ ꢢꢧ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢧ
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ꢟ ꢚ ꢤ ꢣ ꢯꢢ ꢞꢧ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢨꢧ ꢞ ꢝꢠꢟ ꢙꢜ ꢭ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢫ
ꢙ
ꢜ
ꢧ
ꢢ
ꢜ
ꢢ
ꢧ
ꢰ
ꢢꢜ
ꢙ
ꢚ
ꢢ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
ꢙ
ꢞ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢃ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂꢆ ꢃꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏ ꢍꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ ꢍꢎ ꢏ ꢕ ꢖꢎ ꢗꢖꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
SCLS413I − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV594A SN74LV594A
A
UNIT
MIN
7
MAX
MIN
7.5
6.5
5.5
9
MAX
MIN
7.5
6.5
5.5
9
MAX
RCLK or SRCLK high or low
RCLR or SRCLR low
t
w
Pulse duration
ns
6
SER before SRCLK↑
5.5
8
†
SRCLK↑ before RCLK↑
SRCLR low before RCLK↑
8.5
6
9.5
6.8
7.6
1.5
9.5
6.8
7.6
1.5
Setup time
Hold time
t
t
ns
ns
su
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before RCLK↑
SER after SRCLK↑
6.7
1.5
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV594A SN74LV594A
A
UNIT
MIN
5.5
5
MAX
MIN
5.5
5
MAX
MIN
5.5
5
MAX
RCLK or SRCLK high or low
RCLR or SRCLR low
t
w
Pulse duration
ns
SER before SRCLK↑
3.5
8
3.5
8.5
9
3.5
8.5
9
†
SRCLK↑ before RCLK↑
SRCLR low before RCLK↑
8
Setup time
Hold time
t
t
ns
ns
su
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before RCLK↑
SER after SRCLK↑
4.2
4.6
1.5
4.8
5.3
1.5
4.8
5.3
1.5
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV594A SN74LV594A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
RCLK or SRCLK high or low
RCLR or SRCLR low
t
w
Pulse duration
ns
5.2
3
5.2
3
5.2
3
SER before SRCLK↑
†
SRCLK↑ before RCLK↑
5
5
5
SRCLR low before RCLK↑
5
5
5
Setup time
Hold time
t
t
ns
ns
su
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before RCLK↑
SER after SRCLK↑
2.9
3.2
2
3.3
3.7
2
3.3
3.7
2
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
ꢗ
ꢑ
ꢕ
ꢘ
ꢖ
ꢥ
ꢎ
ꢗ
ꢑ
ꢒ
ꢅ
ꢍ
ꢒ
ꢔ
ꢛ
ꢣ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢧ
ꢣ
ꢜ
ꢨ
ꢧ
ꢞ
ꢝ
ꢠ
ꢝꢢ ꢜ ꢛ ꢯꢣ ꢨꢚ ꢤ ꢜ ꢢ ꢞꢦ ꢝꢢ ꢰ ꢢ ꢪꢞ ꢨꢡꢢ ꢣꢙꢫ ꢥ ꢚꢤ ꢧꢤ ꢟꢙ ꢢꢧ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢧ
ꢟ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢰ
ꢢ
ꢞ
ꢧ
ꢜ
ꢨ
ꢢ
ꢟ
ꢛ
ꢦ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢧ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢯ
ꢣ
ꢯ
ꢞ
ꢤ
ꢪ
ꢜ
ꢫ
ꢎ
ꢢ
ꢬ
ꢤ
ꢜ
ꢍ
ꢣ
ꢜ
ꢙ
ꢧ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚꢤ ꢣ ꢯꢢ ꢞꢧ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢨꢧ ꢞꢝ ꢠꢟꢙ ꢜ ꢭ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢫ
ꢙ
ꢜ
ꢧ
ꢢ
ꢜ
ꢢ
ꢧ
ꢰ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
ꢙ
ꢞ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢃꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢃ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕꢖ ꢎ ꢗꢖ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS413I − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
80*
SN54LV594A SN74LV594A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
65*
60
MAX
MIN
45*
40
MAX
MIN
45
40
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
70
t
t
t
t
6.4* 10.6*
6.3* 10.4*
7.4* 12.1*
7.2* 11.6*
7.9* 12.7*
1* 11.1*
1* 11.1*
1* 12.8*
1* 12.8*
1* 13.6*
11.1
11.1
12.8
12.8
13.6
PLH
PHL
PLH
PHL
RCLK
Q −Q
A
H
1
1
SRCLK
Q
C
= 15 pF
ns
H′
L
1
1
RCLR
Q −Q
A
H
t
PHL
7.4* 11.9*
1* 13.1*
1
1
1
1
1
1
13.1
14.6
17.2
16.5
18.6
19
SRCLR
Q
H′
t
t
t
t
9.5
10.8
10.6
11.3
12.1
14.1
15.5
15.7
16.1
17.4
1
1
1
1
1
14.6
17.2
16.5
18.6
19
PLH
PHL
PLH
PHL
RCLK
Q −Q
A
H
SRCLK
Q
C
= 50 pF
ns
H′
L
RCLR
Q −Q
A
H
t
PHL
11.6
16.5
1
18.6
1
18.6
SRCLR
Q
H′
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
120*
105
SN54LV594A SN74LV594A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
80*
55
MAX
MIN
70*
50
1*
MAX
MIN
70
50
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
t
t
t
t
4.6*
4.9*
5.4*
5.5*
6*
8*
8.2*
9.1*
9.2*
9.8*
8.5*
8.8*
9.7*
9.9*
8.5
8.8
PLH
PHL
PLH
PHL
RCLK
Q −Q
A
H
1*
1
1*
1
9.7
SRCLK
Q
C
= 15 pF
ns
H′
L
1*
1
9.9
1* 10.6*
1
10.6
RCLR
Q −Q
A
H
t
PHL
5.6*
6.9
8.1
7.7
8.4
9.1
9.2*
10.5
11.9
11.7
12.5
13.1
1*
1
10*
11.1
13.1
12.4
13.9
14.4
1
1
1
1
1
1
10
11.1
13.1
12.4
13.9
14.4
SRCLR
Q
H′
t
t
t
t
PLH
PHL
PLH
PHL
RCLK
Q −Q
A
H
1
1
SRCLK
Q
C
= 50 pF
ns
H′
L
1
1
RCLR
Q −Q
A
H
t
PHL
8.5
12.4
1
14
1
14
SRCLR
Q
H′
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢗ
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ꢥ
ꢎ
ꢗ
ꢑ
ꢒ
ꢅ
ꢍ
ꢒ
ꢔ
ꢛ
ꢣ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢧ
ꢣ
ꢜ
ꢨ
ꢧ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢯ ꢣ ꢨꢚ ꢤ ꢜ ꢢ ꢞꢦ ꢝꢢ ꢰ ꢢ ꢪ ꢞꢨ ꢡꢢ ꢣ ꢙꢫ ꢥ ꢚꢤ ꢧꢤ ꢟꢙ ꢢꢧ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢧ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢰ
ꢢ
ꢞ
ꢧ
ꢜ
ꢨ
ꢢ
ꢟ
ꢛ
ꢦ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢧ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢯ
ꢣ
ꢯ
ꢞ
ꢤ
ꢪ
ꢜ
ꢫ
ꢎ
ꢢ
ꢬ
ꢤ
ꢜ
ꢍ
ꢣ
ꢜ
ꢙ
ꢧ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚ ꢤ ꢣ ꢯꢢ ꢞꢧ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢨꢧ ꢞ ꢝꢠꢟ ꢙꢜ ꢭ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢫ
ꢙ
ꢜ
ꢧ
ꢢ
ꢜ
ꢢ
ꢧ
ꢰ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
ꢙ
ꢞ
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢃ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂꢆ ꢃꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏ ꢍꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ ꢍꢎ ꢏ ꢕ ꢖꢎ ꢗꢖꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
SCLS413I − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
170*
140
SN54LV594A SN74LV594A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
135*
120
MAX
MIN
115*
95
MAX
MIN
115
95
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
t
t
t
t
3.3*
6.2*
6.5*
6.8*
7.2*
7.6*
1*
6.5*
6.9*
7.2*
7.6*
8.2*
6.5
6.9
7.2
7.6
8.2
PLH
PHL
PLH
PHL
RCLK
Q −Q
A
H
3.7*
1*
1
3.7*
1*
1
SRCLK
Q
C
= 15 pF
ns
H′
L
4.1*
1*
1
4.5*
1*
1
RCLR
Q −Q
A
H
t
PHL
4.1*
4.9
5.8
5.5
6
7.1*
7.8
8.9
8.6
9.2
10
1*
1
7.6*
8.3
1
1
1
1
1
1
7.6
8.3
SRCLR
Q
H′
t
t
t
t
PLH
PHL
PLH
PHL
RCLK
Q −Q
A
H
1
9.7
9.7
1
9.1
9.1
SRCLK
Q
C
= 50 pF
ns
H′
L
1
10.1
10.7
10.1
10.7
6.6
1
RCLR
Q −Q
A
H
t
PHL
6
9.2
1
10.1
1
10.1
SRCLR
Q
H′
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV594A
PARAMETER
UNIT
MIN
TYP
0.5
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.1
2.8
−0.8
OL
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
TEST
CONDITIONS
PARAMETER
V
CC
TYP
UNIT
3.3 V
5 V
93
C
Power dissipation capacitance
f = 10 MHz
pF
pd
112
ꢗ
ꢑ
ꢕ
ꢘ
ꢖ
ꢥ
ꢎ
ꢗ
ꢑ
ꢒ
ꢅ
ꢍ
ꢒ
ꢔ
ꢛ
ꢣ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢧ
ꢣ
ꢜ
ꢨ
ꢧ
ꢞ
ꢝ
ꢠ
ꢝꢢ ꢜ ꢛ ꢯꢣ ꢨꢚ ꢤ ꢜ ꢢ ꢞꢦ ꢝꢢ ꢰ ꢢ ꢪꢞ ꢨꢡꢢ ꢣꢙꢫ ꢥ ꢚꢤ ꢧꢤ ꢟꢙ ꢢꢧ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢧ
ꢟ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢰ
ꢢ
ꢞ
ꢧ
ꢜ
ꢨ
ꢢ
ꢟ
ꢛ
ꢦ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢧ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢯ
ꢣ
ꢯ
ꢞ
ꢤ
ꢪ
ꢜ
ꢫ
ꢎ
ꢢ
ꢬ
ꢤ
ꢜ
ꢍ
ꢣ
ꢜ
ꢙ
ꢧ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚꢤ ꢣ ꢯꢢ ꢞꢧ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢨꢧ ꢞꢝ ꢠꢟꢙ ꢜ ꢭ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢫ
ꢙ
ꢜ
ꢧ
ꢢ
ꢜ
ꢢ
ꢧ
ꢰ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
ꢙ
ꢞ
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢃꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢃ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕꢖ ꢎ ꢗꢖ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS413I − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
t
CC
CC
0 V
0 V
t
t
t
t
Output
Waveform 1
PLZ
PLH
PHL
PZL
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
SN74LV594AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV594ADBR
SN74LV594ADBRE4
SN74LV594ADBRG4
SN74LV594ADE4
SN74LV594ADG4
SN74LV594ADR
SSOP
SSOP
SSOP
SOIC
DB
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV594ADRE4
SN74LV594ADRG4
SN74LV594ANSR
SN74LV594ANSRE4
SN74LV594ANSRG4
SN74LV594APW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV594APWE4
SN74LV594APWG4
SN74LV594APWR
SN74LV594APWRE4
SN74LV594APWRG4
SN74LV594APWT
SN74LV594APWTE4
SN74LV594APWTG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
(mm)
16
SN74LV594ADBR
SN74LV594ADR
SN74LV594ANSR
SN74LV594APWR
DB
D
16
16
16
16
MLA
FMX
MLA
MLA
8.2
6.5
8.2
7.0
6.6
10.3
10.5
5.6
2.5
2.1
2.5
1.6
12
8
16
16
16
12
Q1
Q1
Q1
Q1
16
NS
PW
16
12
8
12
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74LV594ADBR
SN74LV594ADR
SN74LV594ANSR
SN74LV594APWR
DB
D
16
16
16
16
MLA
FMX
MLA
MLA
346.0
342.9
346.0
346.0
346.0
336.6
346.0
346.0
33.0
28.58
33.0
NS
PW
29.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Pack Materials-Page 3
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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DSP
Applications
Audio
amplifier.ti.com
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dsp.ti.com
www.ti.com/audio
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Digital Control
Military
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interface.ti.com
logic.ti.com
Logic
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Security
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Wireless
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Copyright © 2007, Texas Instruments Incorporated
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