SN54LVTH16244A_09 [TI]
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 3.3 -V ABT 16位缓冲器/驱动器，具有三态输出
| 型号： | SN54LVTH16244A_09 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总21页 (文件大小：649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS142T–MAY 1992–REVISED NOVEMBER 2006
FEATURES
SN54LVTH16244A . . . WD PACKAGE
SN74LVTH16244A . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
Members of the Texas Instruments
Widebus™ Family
•
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
2OE
1A1
1A2
GND
1A3
1A4
2
3
4
•
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
5
6
3.3-V VCC
)
7
V
CC
V
CC
•
•
•
•
•
•
Support Unregulated Battery Operation
Down to 2.7 V
8
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
9
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA
Per JESD 17
V
CC
V
CC
ESD Protection Exceeds JESD 22
4Y1
4Y2
GND
4Y3
4Y4
4OE
4A1
4A2
GND
4A3
4A4
3OE
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
The 'LVTH16244A devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) VCC operation, but
with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four
4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical
active-low output-enable (OE) inputs.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1992–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS142T–MAY 1992–REVISED NOVEMBER 2006
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
FBGA – GRD
SN74LVTH16244AGRDR
SN74LVTH16244AZRDR
SN74LVTH16244ADL
Reel of 1000
Tube of 25
LL244A
FBGA – ZRD (Pb-free)
SN74LVTH16244ADLG4
SN74LVTH16244ADLR
74LVTH16244ADLRG4
SN74LVTH16244ADGGR
74LVTH16244ADGGRE4
74LVTH16244ADGGRG4
SN74LVTH16244ADGVR
74LVTH16244ADGVRE4
SN74LVTH16244AGQLR
SN74LVTH16244AZQLR
SNJ54LVTH16244AWD
SSOP – DL
LVTH16244A
Reel of 1000
–40°C to 85°C
TSSOP – DGG
TVSOP – DGV
Reel of 2000
Reel of 2000
LVTH16244A
LL244A
VFBGA – GQL
Reel of 1000
Tube
LL244A
VFBGA – ZQL (Pb-free)
–55°C to 125°C CFP – WD
SNJ54LVTH16244AWD
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
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SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS142T–MAY 1992–REVISED NOVEMBER 2006
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
GQL OR ZQL PACKAGE
(TOP VIEW)
1 2 3 4 5
6
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Y2
1Y4
2Y2
2Y4
3Y1
3Y3
4Y1
4Y3
4OE
NC
NC
NC
NC
2OE
1A2
1A4
2A2
2A4
3A1
3A3
4A1
4A3
3OE
A
B
C
D
E
F
G
H
J
1Y1
1Y3
2Y1
2Y3
3Y2
3Y4
4Y2
4Y4
NC
GND
VCC
GND
GND
VCC
GND
1A1
1A3
2A1
2A3
3A2
3A4
4A2
4A4
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
K
blk
blk
blk
K
(1) NC – No internal connection
xxxxx
xxxxx
xxxxx
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1Y1
1Y3
2Y1
2Y3
3Y1
3Y3
4Y1
4Y3
4Y4
NC
1OE
NC
2OE
NC
NC
1A1
1A3
2A1
2A3
3A1
3A3
4A1
4A3
4A4
A
B
C
D
1Y2
1Y4
2Y2
2Y4
3Y2
3Y4
4Y2
NC
1A2
1A4
2A2
2A4
3A2
3A4
4A2
NC
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
E
F
G
H
J
G
H
J
4OE
3OE
(1) NC – No internal connection
3
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SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS142T–MAY 1992–REVISED NOVEMBER 2006
FUNCTION TABLE
(EACH 4-BIT BUFFER)
INPUTS
OUTPUT
Y
OE
L
A
H
L
H
L
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
25
1OE
1A1
3OE
47
46
2
3
5
6
36
35
33
32
13
14
16
17
1Y1
1Y2
1Y3
1Y4
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
1A2
1A3
1A4
44
43
48
41
40
24
30
29
2OE
2A1
2A2
2A3
2A4
4OE
4A1
4A2
4A3
4A4
8
9
19
20
22
23
2Y1
2Y2
2Y3
2Y4
4Y1
4Y2
4Y3
4Y4
38
37
11
12
27
26
Pin numbers shown are for the DGG, DGV, DL, and WD packages.
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SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS142T–MAY 1992–REVISED NOVEMBER 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC Supply voltage range
4.6
VI
Input voltage range(2)
7
V
VO
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high state(2)
7
VCC + 0.5
96
V
V
V
SN54LVTH16244A
Current into any output in the low state
IO
SN74LVTH16244A
128
48
SN54LVTH16244A
Current into any output in the high state(3)
SN74LVTH16244A
IO
64
IIK
Input clamp current
Output clamp current
VI < 0
–50
–50
70
mA
mA
IOK
VO < 0
DGG package
DGV package
DL package
GQL/ZQL package
GRD/ZRD package
58
θJA
Package thermal impedance(4)
63
°C/W
42
36
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
SN54LVTH16244A SN74LVTH16244A
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
VCC
VIH
VIL
Supply voltage
3.6
3.6
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
–25
48
0.8
5.5
–32
64
V
VI
V
IOH
IOL
High-level output current
Low-level output current
Input transition rise or fall rate
mA
mA
ns/V
µs/V
°C
∆t/∆v
Outputs enabled
10
10
∆t/∆VCC Power-up ramp rate
TA Operating free-air temperature
200
–55
200
–40
125
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS142T–MAY 1992–REVISED NOVEMBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVTH16244A
SN74LVTH16244A
MIN TYP(1)
PARAMETER
VIK
TEST CONDITIONS
UNIT
MIN TYP(1)
MAX
MAX
–1.2
VCC = 2.7 V,
II = –18 mA
–1.2
V
VCC = 2.7 V to 3.6 V, IOL = –100 µA
VCC – 0.2
VCC – 0.2
VCC = 2.7 V,
IOH = –8 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 48 mA
IOL = 64 mA
VI = 5.5 V
2.4
2
2.4
VOH
V
V
VCC = 3 V
2
0.2
0.5
0.2
0.5
0.4
0.5
VCC = 2.7 V
VCC = 3 V
0.4
VOL
0.5
0.55
0.55
10
VCC = 0 or 3.6 V,
VCC = 3.6 V,
50
Control
inputs
VI = VCC or GND
±1
±1
II
µA
VI = VCC
1
1
–5
Data
inputs
VCC = 3.6 V
VCC = 0,
VI = 0
–5
Ioff
VI or VO = 0 to 4.5 V
VI = 0.8 V
VI = 2 V
±100
µA
µA
75
75
VCC = 3 V
Data
–75
–75
II(hold)
inputs
500
– 750
VCC = 3.6 V(2)
,
VI = 0 to 3.6 V
IOZH
IOZL
VCC = 3.6 V,
VCC = 3.6 V,
VO = 3 V
5
5
µA
µA
VO = 0.5 V
–5
–5
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
IOZPU
IOZPD
±100(3)
±100(3)
±100
±100
µA
µA
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don't care
Outputs high
VCC = 3.6 V,
0.19
5
0.19
5
ICC
IO = 0,
Outputs low
mA
mA
VI = VCC or GND
Outputs disabled
0.19
0.19
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
(4)
∆ICC
0.2
0.2
Ci
VI = 3 V or 0 V
VO = 3 V or 0 V
4
9
4
9
pF
pF
Co
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) On products compliant to MIL-PRF-38535, this parameter does not apply.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
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SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS142T–MAY 1992–REVISED NOVEMBER 2006
Switching Characteristics
over recommended operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1 )
SN54LVTH16244A
VCC = 3.3 V
SN74LVTH16244A
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC = 2.7 V
VCC = 2.7 V
UNIT
± 0.3 V
MIN
1.1
MAX
4.4
3.6
4.6
5.4
5.7
5
MIN MAX
MIN TYP(1)
MAX MIN
MAX
3.7
3.7
5
tPLH
tPHL
4.6
3.9
5.4
6.2
6.2
4.7
1.2
1.2
1.2
1.2
2.2
2
2.3
2
3.2
3.2
4
A
Y
Y
Y
ns
ns
ns
ns
1.1
tPZH
1.1
2.6
2.7
3.3
3.1
OE
OE
tPZL
1.1
4
5
tPHZ
1.6
4.5
4.2
0.5
0.5
5
tPLZ
1.2
4.4
tsk(LH)
tsk(HL)
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
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SN54LVTH16244A, SN74LVTH16244A
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS142T–MAY 1992–REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION
6 V
Open
S1
500 Ω
TEST
/t
S1
From Output
Under Test
GND
t
t
t
Open
6 V
GND
PLH PHL
/t
PLZ PZL
C = 50 pF
L
500 Ω
/t
PHZ PZH
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
+ 0.3 V
OL
V
OL
(see Note B)
OL
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
− 0.3 V
OH
1.5 V
VOLTAGE WAVEFORMS
1.5 V
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9668501QXA
5962-9668501VXA
ACTIVE
ACTIVE
ACTIVE
CFP
WD
48
48
48
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
CFP
WD
74LVTH16244ADGGRE4
TSSOP
DGG
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74LVTH16244ADGGRG4
74LVTH16244ADGVRE4
74LVTH16244ADGVRG4
74LVTH16244ADLRG4
SN74LVTH16244ADGGR
SN74LVTH16244ADGVR
SN74LVTH16244ADL
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
TSSOP
TVSOP
TVSOP
SSOP
DGG
DGV
DGV
DL
48
48
48
48
48
48
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
SSOP
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH16244ADLG4
SN74LVTH16244ADLR
SN74LVTH16244AGQLR
SSOP
DL
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQL
1000
TBD
SNPB
Level-1-240C-UNLIM
Level-1-240C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SN74LVTH16244AGRDR
SN74LVTH16244AZQLR
SN74LVTH16244AZRDR
SNJ54LVTH16244AWD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GRD
ZQL
ZRD
WD
54
56
54
48
1000
TBD
SNPB
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
A42
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
CFP
1
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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OTHER QUALIFIED VERSIONS OF SN54LVTH16244A, SN54LVTH16244A-SP, SN74LVTH16244A :
Enhanced Product: SN74LVTH16244A-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVTH16244ADGGR TSSOP
SN74LVTH16244ADGVR TVSOP
DGG
DGV
DL
48
48
48
56
2000
2000
1000
1000
330.0
330.0
330.0
330.0
24.4
16.4
32.4
16.4
8.6
7.1
15.8
10.2
1.8
1.6
12.0
12.0
16.0
8.0
24.0
16.0
32.0
16.0
Q1
Q1
Q1
Q1
SN74LVTH16244ADLR
SSOP
11.35 16.2
3.1
SN74LVTH16244AGQLR BGA MI
GQL
4.8
5.8
4.8
5.8
7.3
8.3
7.3
8.3
1.45
CROSTA
R JUNI
OR
SN74LVTH16244AGRDR BGA MI
GRD
ZQL
ZRD
54
56
54
1000
1000
1000
330.0
330.0
330.0
16.4
16.4
16.4
1.55
1.45
1.55
8.0
8.0
8.0
16.0
16.0
16.0
Q1
Q1
Q1
CROSTA
R JUNI
OR
SN74LVTH16244AZQLR BGA MI
CROSTA
R JUNI
OR
SN74LVTH16244AZRDR BGA MI
CROSTA
R JUNI
OR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVTH16244ADGGR
SN74LVTH16244ADGVR
SN74LVTH16244ADLR
TSSOP
TVSOP
SSOP
DGG
DGV
DL
48
48
48
56
2000
2000
1000
1000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
41.0
33.0
49.0
33.0
SN74LVTH16244AGQLR BGA MICROSTAR
JUNIOR
GQL
SN74LVTH16244AGRDR BGA MICROSTAR
JUNIOR
GRD
ZQL
ZRD
54
56
54
1000
1000
1000
346.0
346.0
346.0
346.0
346.0
346.0
33.0
33.0
33.0
SN74LVTH16244AZQLR BGA MICROSTAR
JUNIOR
SN74LVTH16244AZRDR BGA MICROSTAR
JUNIOR
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN54LVTH162541WDR
LVT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, CDFP48, 0.380 INCH, FINE PITCH, CERAMIC, FP-48
TI
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