SN54LVTH16245A_14 [TI]
3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS;
| 型号： | SN54LVTH16245A_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 输出元件 |
| 文件： | 总18页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVTH16245A, SN74LVTH16245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS143Q–MAY 1992–REVISED OCTOBER 2005
FEATURES
SN54LVTH16245A . . . WD PACKAGE
SN74LVTH16245A . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
Members of the Texas Instruments Widebus™
Family
•
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
3
•
•
•
•
•
•
•
•
•
Support Mixed-Mode Signal Operation (5-V
4
Input and Output Voltages With 3.3-V VCC
)
5
Support Unregulated Battery Operation Down
to 2.7 V
6
7
V
CC
V
CC
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Flow-Through Architecture Optimizes PCB
Layout
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
V
CC
V
CC
Latch-Up Performance Exceeds 500 mA Per
JESD 17
2B5
2B6
GND
2B7
2B8
2DIR
2A5
2A6
GND
2A7
2A8
2OE
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVTH16245AGRDR
SN74LVTH16245AZRDR
74LVTH16245ADLG4
TOP-SIDE MARKING
FBGA – GRD
Tape and reel
Tape and reel
LL245A
FBGA – ZRD (Pb-free)
SSOP – DL
LVTH16245A
74LVTH16245ADLRG4
SN74LVTH16245ADGGR
74LVTH16245ADGGRE4
74LVTH16245ADGGRG4
SN74LVTH16245ADGVR
74LVTH16245ADGVRE4
SN74LVTH16245AKR
–40°C to 85°C
TSSOP – DGG
TVSOP – DGV
Tape and reel
Tape and reel
LVTH16245A
LL245A
VFBGA – GQL
Tape and reel
Tube
LL245A
VFBGA – ZQL (Pb-free)
CFP – WD
74LVTH16245AZQLR
–55°C to 125°C
SNJ54LVTH16245AWD
SNJ54LVTH16245AWD
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1992–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
SN54LVTH16245A, SN74LVTH16245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS143Q–MAY 1992–REVISED OCTOBER 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The 'LVTH16245A devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices are designed for asynchronous communication between two data buses. The logic levels of the
direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level
applied to prevent excess ICC and ICCZ
.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
GQL OR ZQL PACKAGE
TERMINAL ASSIGNMENTS(1)
(TOP VIEW)
(56-Ball GQL/ZQL Package)
1
2 3 4 5 6
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
VCC
GND
GND
VCC
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
K
K
abc
abc
abc
(1) NC – No internal connection
2
SN54LVTH16245A, SN74LVTH16245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS143Q–MAY 1992–REVISED OCTOBER 2005
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B7
2B8
NC
1DIR
NC
1OE
NC
NC
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A7
2A8
A
B
C
D
1B2
1B4
1B6
1B8
2B2
2B4
2B6
NC
1A2
1A4
1A6
1A8
2A2
2A4
2A6
NC
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
E
F
G
H
J
2DIR
2OE
G
H
J
(1) NC – No internal connection
FUNCTION TABLE(1)
(EACH 8-BIT SECTION)
CONTROL
INPUTS
OUTPUT CIRCUITS
OPERATION
OE
L
DIR
A PORT
Enabled
Hi-Z
B PORT
Hi-Z
L
H
X
B data to A bus
A data to B bus
Isolation
L
Enabled
Hi-Z
H
Hi-Z
(1) Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
24
1
2DIR
1DIR
48
25
13
1OE
2OE
36
47
1A1
2A1
2
2B1
1B1
To Seven Other Channels
To Seven Other Channels
3
SN54LVTH16245A, SN74LVTH16245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS143Q–MAY 1992–REVISED OCTOBER 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
4.6
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high state(2)
V
7
7
V
V
V
VO
VO
–0.5 VCC + 0.5
SN54LVTH16245A
Current into any output in the low state
96
128
48
IO
mA
mA
SN74LVTH16245A
SN54LVTH16245A
Current into any output in the high state(3)
SN74LVTH16245A
IO
64
IIK
Input clamp current
Output clamp current
VI < 0
–50
–50
70
mA
mA
IOK
VO < 0
DGG package
DGV package
DL package
GQL/ZQL package
GRD/ZRD package
58
θJA
Package thermal impedance(4)
63
°C/W
42
36
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
SN54LVTH16245A SN74LVTH16245A
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
VCC
VIH
Supply voltage
3.6
3.6
V
V
High-level input voltage
Low-level input voltage
Input voltage
VIL
0.8
5.5
–24
48
0.8
5.5
–32
64
V
VI
V
IOH
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
IOL
∆t/∆v
∆t/∆VCC
TA
Outputs enabled
10
10 ns/V
200
–55
200
–40
µs/V
Operating free-air temperature
125
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN54LVTH16245A, SN74LVTH16245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS143Q–MAY 1992–REVISED OCTOBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVTH16245A
MIN TYP(1)
SN74LVTH16245A
MIN TYP(1)
MAX
PARAMETER
VIK
TEST CONDITIONS
UNIT
MAX
VCC = 2.7 V,
II = –18 mA
–1.2
–1.2
V
VCC = 2.7 V to 3.6 V, IOH = –100 µA
VCC – 0.2
VCC – 0.2
VCC = 2.7 V,
IOH = –8 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 48 mA
IOL = 64 mA
VI = VCC or GND
VI = 5.5 V
2.4
2
2.4
VOH
V
V
VCC = 3 V
2
0.2
0.5
0.2
0.5
0.4
0.5
VCC = 2.7 V
VCC = 3 V
0.4
VOL
0.5
0.55
0.55
±1
VCC = 3.6 V,
±1
10
20
5
Control
inputs
VCC = 0 or 3.6 V,
10
II
VI = 5.5 V
20
µA
A or B
port(2)
VCC = 3.6 V
VI = VCC
5
VI = 0
–5
–5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
VI = 0.8 V
±100
µA
µA
75
75
VCC = 3 V
A or B
port
VI = 2 V
–75
–75
II(hold)
500
–750
VCC = 3.6 V,(3)
VI = 0 to 3.6 V
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
IOZPU
IOZPD
±100(4)
±100(4)
±100
±100
µA
µA
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don't care
Outputs high
VCC = 3.6 V,
0.19
5
0.19
5
ICC
IO = 0,
Outputs low
mA
mA
VI = VCC or GND
Outputs disabled
0.19
0.19
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
(5)
∆ICC
0.2
0.2
Ci
VI = 3 V or 0
VO = 3 V or 0
4
4
pF
pF
Cio
10
10
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) Unused pins at VCC or GND
(3) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(4) On products compliant to MIL-PRF-38535, this parameter is not production tested.
(5) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
5
SN54LVTH16245A, SN74LVTH16245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS143Q–MAY 1992–REVISED OCTOBER 2005
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH16245A
VCC = 3.3 V
± 0.3 V
MIN MAX MIN MAX MIN TYP(1) MAX MIN MAX
SN74LVTH16245A
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC = 2.7 V
VCC = 2.7 V
UNIT
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
0.5
0.5
0.5
0.5
1
4.5
4.4
6.5
5.4
6.8
6.2
4.6
3.9
6.6
6.2
7
1.5
1.3
1.5
1.6
2.3
2.2
2.3
2.1
2.8
2.9
3.7
3.5
3.3
3.3
4.5
4.6
5.1
5.1
0.5
3.7
3.5
5.3
5.2
5.5
5.4
0.5
A or B
OE
B or A
A or B
A or B
ns
ns
OE
ns
ns
1
6.3
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6
SN54LVTH16245A, SN74LVTH16245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS143Q–MAY 1992–REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
6 V
GND
PLH PHL
t
t
/t
PLZ PZL
C = 50 pF
L
/t
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
Output
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
− 0.3 V
OH
1.5 V
Output
1.5 V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9668601QXA
5962-9668601VXA
ACTIVE
ACTIVE
ACTIVE
CFP
WD
48
48
48
1
1
TBD
TBD
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
CFP
WD
74LVTH16245ADGGRE4
TSSOP
DGG
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74LVTH16245ADGGRG4
74LVTH16245ADGVRE4
74LVTH16245ADLG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TVSOP
SSOP
DGG
DGV
DL
48
48
48
48
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74LVTH16245ADLRG4
SN74LVTH16245ADGGR
SN74LVTH16245ADGVR
SN74LVTH16245ADL
SN74LVTH16245ADLR
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
SSOP
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH16245AGQLR
SN74LVTH16245AGRDR
SN74LVTH16245AZQLR
ACTIVE
ACTIVE
ACTIVE
VFBGA
LFBGA
VFBGA
GQL
GRD
ZQL
56
54
56
1000
1000
TBD
TBD
SNPB
SNPB
Level-1-240C-UNLIM
Level-1-240C-UNLIM
Level-1-260C-UNLIM
1000 Green (RoHS &
no Sb/Br)
SNAGCU
SN74LVTH16245AZRDR
SNJ54LVTH16245AWD
ACTIVE
ACTIVE
LFBGA
CFP
ZRD
WD
54
48
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Call TI
Level-1-260C-UNLIM
Level-NC-NC-NC
1
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2005
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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